Hotfix: BMA Accel wedges I2C if probed too fast after boot

Only an issue on Pinecil as it boots much faster than Miniware units.

.github/workflows/push.yml

@@ -1,6 +1,6 @@
 name: CI
 
-on: [push,pull_request]
+on: [push, pull_request]
 
 jobs:
   build_TS80:
@@ -10,8 +10,8 @@ jobs:
       - uses: actions/checkout@v2
 
       - name: chmod
-        run: chmod +x setup.sh && chmod +x workspace/TS100/build.sh && sudo mkdir -p /build/cache && sudo chmod -R 777 /build
-      
+        run: chmod +x setup.sh && chmod +x source/build.sh && sudo mkdir -p /build/cache && sudo chmod -R 777 /build
+
       - name: Cached compiler source files
         uses: actions/cache@v2
         env:
@@ -27,15 +27,15 @@ jobs:
         run: ./setup.sh
 
       - name: build TS80
-        run: cd workspace/TS100 && ./build.sh -m TS80
+        run: cd source && ./build.sh -m TS80
 
       - name: Archive TS80 artifacts
         uses: actions/upload-artifact@v2
         with:
           name: TS80
           path: |
-            workspace/TS100/Hexfile/TS80_*.hex
-            workspace/TS100/Hexfile/TS80_*.bin
+            source/Hexfile/TS80_*.hex
+            source/Hexfile/TS80_*.bin
           if-no-files-found: error
   build_TS80P:
     runs-on: ubuntu-latest
@@ -44,7 +44,7 @@ jobs:
       - uses: actions/checkout@v2
 
       - name: chmod
-        run: chmod +x setup.sh && chmod +x workspace/TS100/build.sh && sudo mkdir -p /build/cache && sudo chmod -R 777 /build
+        run: chmod +x setup.sh && chmod +x source/build.sh && sudo mkdir -p /build/cache && sudo chmod -R 777 /build
 
       - name: Cached compiler source files
         uses: actions/cache@v2
@@ -61,15 +61,15 @@ jobs:
         run: ./setup.sh
 
       - name: build TS80P
-        run: cd workspace/TS100 && ./build.sh -m TS80P
+        run: cd source && ./build.sh -m TS80P
 
       - name: Archive TS80P artifacts
         uses: actions/upload-artifact@v2
         with:
           name: TS80P
           path: |
-            workspace/TS100/Hexfile/TS80P_*.hex
-            workspace/TS100/Hexfile/TS80P_*.bin
+            source/Hexfile/TS80P_*.hex
+            source/Hexfile/TS80P_*.bin
           if-no-files-found: error
   build_TS100:
     runs-on: ubuntu-latest
@@ -78,8 +78,8 @@ jobs:
       - uses: actions/checkout@v2
 
       - name: chmod
-        run: chmod +x setup.sh && chmod +x workspace/TS100/build.sh && sudo mkdir -p /build/cache && sudo chmod -R 777 /build
-        
+        run: chmod +x setup.sh && chmod +x source/build.sh && sudo mkdir -p /build/cache && sudo chmod -R 777 /build
+
       - name: Cached compiler source files
         uses: actions/cache@v2
         env:
@@ -95,15 +95,15 @@ jobs:
         run: ./setup.sh
 
       - name: build TS100
-        run: cd workspace/TS100 && ./build.sh -m TS100
+        run: cd source && ./build.sh -m TS100
 
       - name: Archive TS100 artifacts
         uses: actions/upload-artifact@v2
         with:
           name: TS100
           path: |
-            workspace/TS100/Hexfile/TS100_*.hex
-            workspace/TS100/Hexfile/TS100_*.bin
+            source/Hexfile/TS100_*.hex
+            source/Hexfile/TS100_*.bin
           if-no-files-found: error
 
   build_Pinecil:
@@ -113,8 +113,8 @@ jobs:
       - uses: actions/checkout@v2
 
       - name: chmod
-        run: chmod +x setup.sh && chmod +x workspace/TS100/build.sh && sudo mkdir -p /build/cache && sudo chmod -R 777 /build
-        
+        run: chmod +x setup.sh && chmod +x source/build.sh && sudo mkdir -p /build/cache && sudo chmod -R 777 /build
+
       - name: Cached compiler source files
         uses: actions/cache@v2
         env:
@@ -130,13 +130,13 @@ jobs:
         run: ./setup.sh
 
       - name: build Pinecil
-        run: cd workspace/TS100 && ./build.sh -m Pinecil
+        run: cd source && ./build.sh -m Pinecil
 
       - name: Archive Pinecil artifacts
         uses: actions/upload-artifact@v2
         with:
           name: Pinecil
           path: |
-            workspace/TS100/Hexfile/Pinecil_*.hex
-            workspace/TS100/Hexfile/Pinecil_*.bin
+            source/Hexfile/Pinecil_*.hex
+            source/Hexfile/Pinecil_*.bin
           if-no-files-found: error

.gitignore

@@ -27,48 +27,33 @@
 *.app
 *.i*86
 *.x86_64
-workspace/*.hex
 
 # Debug files
 *.dSYM/
 *.su
-workspace/ts100/Debug/*
-workspace/.metadata/*
+source/.metadata/*
 
-workspace/ts100/.settings/language.settings.xml
-workspace/ts100/.cproject
 TS100/KiCad/TS100.bak
 Logo GUI/TS100 Logo Editor/TS100 Logo Editor/obj/
 Logo GUI/TS100 Logo Editor/TS100 Logo Editor/bin/
-workspace/ts100/ts100.xml
-workspace/ts100_old/*
 *.cache
-workspace/TS100/.settings/language.settings.xml
-workspace/TS100A/Release/TS100A.map
-workspace/TS100A/Release/TS100A.list
-workspace/TS100A/Release/TS100A.hex
-workspace/TS100A/.settings/language.settings.xml
-workspace/TS100A/.metadata/
 Translation Editor/.vscode/
 Translation Editor/__pycache__/
 *.pyc
-workspace/TS100/src/Translation.cpp
 *.lst
 *.mk
 *.list
-workspace/TS100/Release/
-workspace/TS100/Hexfile/
-workspace/RemoteSystemsTempFiles/
-workspace/TS100/.settings/
-workspace/TS100/TS80/
+source/Hexfile/
+source/Objects/
+
 ci/artefacts/
 ci/secrets/unencrypted/
 codeship.aes
 .vscode/settings.json
 
 # Auto generated files
-workspace/TS100/Core/Src/Translation.cpp
-workspace/TS100/Core/Inc/unit.h
+source/Core/Inc/unit.h
+source/Core/Gen/
 # IDE configs
 .vs/*
 .settings/*
@@ -191,4 +176,3 @@ fabric.properties
 
 CoreCompileInputs.cache
 .vscode/settings.json
-workspace/TS100/TS100/

Documentation/DebugMenu.md

@@ -40,15 +40,17 @@ This is the raw tip reading in uV. This can be used when assessing the calibrati
 
 ### CTip
 
-This is the tip temperature in deg C. This can be used with RTip for assessing temperature processing performance.
+This is the tip temperature in deg C. 
+This can be used with RTip for assessing temperature processing performance.
 
 ### CHan
 
 This is the handle temperature in C. This is used for cold junction compensation of the tip temp.
+This is shown in degrees C x10, so 200 == 20.0C
 
 ### Vin 
 
-The input voltage reading. 
+The input voltage as read by the internal ADC. Can be used to sanity check its being read correctly.
 
 ### PCB 
 

Documentation/Development.md

@@ -4,11 +4,14 @@ Building this software can be performed two ways, using the STMCubeIDE or using
 
 ## STM Cube IDE
 
-The repository is setup to try and make this painless, when starting the IDE you can import the project by pointing the internal search to the workspace folder of this repository. If you start with a fresh installation, close the welcome screen tab, and then in the left sidebar, there is an option to "import". Select General -> Import existing projects -> Set the top location option to this repositories workspace -> Should find the TS100 project.
+The easiest way to start working using the STM Cube IDE is to create a new project for the STM32F103RCTx.
+Then once this is created remove the auto-generated source code.
+Next drag the contents of the `source` folder into the project and choose to link to files.
+You will need to update the build settings for include paths & point to the new `.ld` linker file
 
 ## Developing with command line tools & building a release
 
-In the `workspace/TS100` folder there is a makefile that can be used to build the repository using command line tools.
+In the `source` folder there is a makefile that can be used to build the repository using command line tools.
 when running the `make` command, specify which model of the device & the language you would like to use.
 
 `make -j8 lang=EN model=TS80`
@@ -23,4 +26,5 @@ To update the language translation files & associated font map, execute the `mak
 
 I highly reccomend using the command line tools and using docker to run the compiler.
 Its a bit more fussy on setup than the STM tooling and this is by far the easiest way.
-If you _need_ an IDE I have used [Nuclei's IDE](https://nucleisys.com/download.php)
+If you _need_ an IDE I have used [Nuclei's IDE](https://nucleisys.com/download.php)
+And follow same idea as the STM Cube IDE notes above.

Documentation/Flashing.md

@@ -4,7 +4,7 @@
 
 ### Main release
 
-Main releases are made to the [releases page](/releases).
+Main releases are made to the [releases page](https://github.com/Ralim/IronOS/releases).
 Download the zip file that matches your model of soldering iron, and extract it.
 You then need to use the appropriate file type for your unit, in general Miniware irons are `.hex` and Pinecil is `.bin.`
 Flash according to details below
@@ -12,7 +12,7 @@ Flash according to details below
 ### Bleeding edge / latest
 
 For the _latest_ code, you will need to download the zip file from the artefacts page on the build for what you want.
-Head to the [Actions](/actions) page and then select the run for the appropriate branch you would like.
+Head to the [Actions](https://github.com/Ralim/IronOS/actions) page and then select the run for the appropriate branch you would like.
 In general you probably want `master`.
 
 Once you click on a run, scroll down to the "Artifacts" section and then click on your model to download a zip file.
@@ -20,7 +20,7 @@ Then this works the same as a production release (use the correct file).
 
 ## Miniware irons (TS100, TS80, TS80P)
 
-This is completely safe, but if it goes wrong just put the .hex file from the official website onto the unit and you're back to the old firmware. Downloads for the hex files to flash are available on the [releases page.](https://github.com/Ralim/ts100/releases) The file you want is called *(MODEL)_EN.hex* unless you want the translations, they are (MODEL)_*language short name*.hex. Where (MODEL) is either TS100 or TS80.
+This is completely safe, but if it goes wrong just put the .hex file from the official website onto the unit and you're back to the old firmware. Downloads for the hex files to flash are available on the [releases page.](https://github.com/Ralim/IronOS/releases) The file you want is called *(MODEL)_EN.hex* unless you want the translations, they are (MODEL)_*language short name*.hex. Where (MODEL) is either TS100 or TS80.
 
 Officially the bootloader on the iron only works under Windows (use the built-in File Explorer, as alternative file managers or copy handlers like Teracopy will fail). However, users have reported that it does work under Mac, and can be made to work under Linux *sometimes*. Details over on the [wiki page](https://github.com/Ralim/ts100/wiki/Upgrading-Firmware). 
 

Documentation/Temperature.md

@@ -0,0 +1,58 @@
+# Tip temperature measurement
+
+The soldering irons use a modified N-type thermocouple in the tip to measure the tip temperature.
+This is constructed for free by using a different type of metal to join one of the rings to the heating coil. This effectively creates a free temperature sensor for very low cost and construction difficulty.
+
+The downsides of this are twofold; one, it is made using non-optimal metals and has a non-constant temperature response; and two, as this uses the same connections as the heating current, you can't measure the temperature while you are heating the tip.
+
+
+
+##  How a thermocouple works (brief)
+
+A thermocouple uses a junction of two dissimilar metals to create a very small amount of power (microvolts). This can then be measured and used with a known transfer function to derive the temperature of the junction.
+This has some fairly large limitations, but it also has the benefit of being extremely cheap.
+
+Conventionally a thermocouple is created using two dissimilar metals that join, and then the other ends of these metals are terminated to copper contacts. These copper contacts are also part of the construction of the thermocouple and are referred to as the cold junction.
+As there are these extra two joins between the thermocouple wires and the copper; these also have properties of their own in their reactions with temperature.
+
+If the cold junction is held at 0 degree's C, then their effect is considered to be null, and so they can be ignored. However, in the real world the joins to copper are often at room temperature, and as such the measured voltage from the thermocouple must be compensated to remove the influence of these joints. This process is often called cold junction compensation.
+
+Every time in the circuit there is a join between two different metals, there is a small thermocouple created, this means that _every_ soldered connection is also one. 
+
+
+## How these irons implement the temperature reading
+
+If you analyse one of the open circuit schematics (Pinecil, TS100, TS80) they all use the same approximate formula.
+This consists of an op-amp that is connected directly across the heating connections to the tip, and a separate handle temperature sensor.
+
+When the iron is **not** heating the tip, the microcontroller uses the ADC to read the output from the op-amp. This produces a voltage that _should_ be linear to the temperature of (tip-handle). This value is then offset compensated (to remove ADC+op-amp offsets), and then converted into a temperature delta in C/K. This temperature delta can then be added to the handle temperature to derive the tip temperature in C.
+
+Depending on the construction of the tip, the lookup values used for converting the tip reading in uV into degrees C/K varies. It is worth noting, however, that TS100 and Pinecil tips are approximately the same as the Hakko T12 tips. (In @Ralim's testing, to within measurement error). This makes sense as these tips are cheap and would have made an excellent design for Miniware to have cloned in making the TS100 in the first place.
+
+## Implications of this
+
+### Reading accuracy vs Heating performance tradeoff
+
+Because the tip can only be measured when the unit is not heating, the more often the tip is measured (for finer temperature control) the less time the unit can spend heating up the tip. This means that for fast heat up and fine temperature control the firmware now implements two speeds to the controller loop. During heating up the system runs fewer temperature measurements and instead allows the tip to spend more time burning power. Once the unit is up to temperature the rate of taking temperature readings is doubled to allow for faster reaction times.
+
+### Tip heat up lag time
+
+As the temperature sensor is a part of the heater coil inside of the tip (or very close by, not entirely certain); the temperature reading is of the _inside_ of the tip, rather than the outside. The outside temperature is the most critical for the user as this is where the solder is actually melting and performing work.
+
+The PID controller in the firmware is tuned to be slightly underdamped and thus more "jumpy" than some people would expect. This is based on the theory that if the inside of the tip is seeing the temperature droop; the outside temperature has dropped more and so we should overcompensate until they equalise.
+
+This is why sometimes the temperature may flick around a little during use but the tip temperature itself is quite stable. The thermal mass of the tip smooths these small amounts out nicely for the user. Though seeing larger jumps on some tips than others _may_ indicate that the tip does not have optimal internal thermal bonding between the heater coil and the tip itself.
+
+The firmware uses the theory that these irons are more towards the power users territory than most, so it tries to not hide the actual temperature. What some soldering iron controllers do is that they hide the actual measurement once you are within a certain tolerance of this. For example, on a digital Weller unit Ralim has to hand, if set to 350C, it will regulate to within around +-3 C but not indicate you are outside of this bad until you exceed +-5C. This gives the illusion that it's holding the temperature perfectly when in actuality it's moving around as well.
+
+Given enough time (3-5 seconds) with no external cooling, the inside and outside temperatures of the tip will be equal. When testing the tip temperature accuracy try to allow time for the system to stabilise.
+
+### Complexity of measurement
+
+The firmware in these irons does a best-effort of calculating an accurate temperature, but as always there is a tradeoff between perfect accuracy and firmware complexity and setup. As these irons are built down to a cost, expecting accuracy greater than 1% is not really an option as the voltage reference is only 1% accurate at best. So _all_ measurements are affected by its accuracy. And the low-cost chips used in the irons do not come calibrated from the factory so we do not have an internal calibration we can use to try and measure this inaccuracy.
+
+The firmware only accounts for cold junction compensation and then treats the remaining error as being a constant offset. 
+While the error is small, it is actually composed of both a constant offset as well as an offset that is linear to the handle temperature.
+This offset that is linear to handle temperature is as of current not modelled into the firmware and there is assumed to be constant. This is generally "close enough" as once the unit is in use, the handle temperature is usually within 10C as the components inside warm-up from use. This means that this error is "relatively" constant once the unit is being used. However, this can cause odd behaviour when the tip temperature ~= room temperature. And can cause some jumping and movement in the readings when attempting to control the tip to sub 100C.
+
+This is a known tradeoff that is made as the irons intended use case means that it will spend most of its time above 150C, at which point these errors are no longer the dominant error sources in the system.

Documentation/Translation.md

@@ -1,6 +1,6 @@
 # Translation
-If you would like to contribute a translation, use the [Translation Editor](http://htmlpreview.github.io/?https://github.com/Ralim/ts100/blob/master/Translation%20Editor/TranslationEditor.html).
+If you would like to contribute a translation, use the [Translation Editor](http://htmlpreview.github.io/?https://github.com/Ralim/ts100/blob/master/Translations/TranslationEditor.html).
 
-[Open a reference language file and optionally a target language file](https://github.com/Ralim/ts100/tree/master/Translation%20Editor).
+[Open a reference language file and optionally a target language file](https://github.com/Ralim/ts100/tree/master/Translations).
 
 You can create a pull request with the new / updated json configuration file, and this will include this language into the new builds for the firmware.

Flashing/flash_ts100_linux.sh

@@ -13,13 +13,13 @@ function usage() {
     echo
     echo "This script has been tested to work on Fedora."
     echo "If you experience any issues please open a ticket at:"
-    echo "https://github.com/Ralim/ts100/issues/new"
+    echo "https://github.com/Ralim/IronOS/issues/new"
     echo
 }
 
 GAUTOMOUNT=0
 function disable_gautomount {
-    GSETTINGS=`which gsettings`
+    GSETTINGS=$(which gsettings)
     if [ $? -ne 0 ]; then
         return 1
     fi
@@ -37,11 +37,11 @@ function enable_gautomount {
 }
 
 function is_attached {
-    output=`lsblk -b --raw --output NAME,MODEL | grep 'DFU.*Disk'`
+    output=$(lsblk -b --raw --output NAME,MODEL | grep 'DFU.*Disk')
     if [ $? -ne 0 ]; then
       return 1
     fi
-    DEVICE=`echo $output | awk '{print "/dev/"$1}'`
+    DEVICE=$(echo $output | awk '{print "/dev/"$1}')
 }
 
 instructions="not printed"
@@ -102,7 +102,7 @@ if [ ! -f "$1" ]; then
     exit 1
 fi
 
-if [ `head -c1 "$1"` != ":" ] || [ `tail -n1 "$1" | head -c1` != ":" ]; then
+if [ $(head -c1 "$1") != ":" ] || [ $(tail -n1 "$1" | head -c1) != ":" ]; then
     echo "'$1' doesn't look like a valid HEX file. Please provide a HEX file to flash"
     usage
     exit 1

Translations/make_translation.py

@@ -80,9 +80,6 @@ def writeStart(f):
             """// WARNING: THIS FILE WAS AUTO GENERATED BY make_translation.py. PLEASE DO NOT EDIT.
 
 #include "Translation.h"
-#ifndef LANG
-#define LANG_EN
-#endif
 """
         )
     )
@@ -512,9 +509,7 @@ def writeUnit(languageCode, defs, f, UnitCodes):
 
 
 def readVersion():
-    with open(
-        os.path.relpath(jsonDir + "/../workspace/TS100/version.h"), "r"
-    ) as version_file:
+    with open(os.path.relpath(jsonDir + "/../source/version.h"), "r") as version_file:
         try:
             for line in version_file:
                 if re.findall(r"^.*(?<=(#define)).*(?<=(BUILD_VERSION))", line):
@@ -554,13 +549,15 @@ def read_opts():
     if len(sys.argv) > 2:
         outFileTranslationCPP = sys.argv[2]
     else:
-        outDir = os.path.relpath(jsonDir + "/../workspace/TS100/Core/Src")
+        outDir = os.path.relpath(jsonDir + "/../source/Core/Gen")
+        if not os.path.exists(outDir):
+            os.makedirs(outDir)
         outFileTranslationCPP = os.path.join(outDir, TRANSLATION_CPP)
 
     if len(sys.argv) > 3:
         outFileUnitH = sys.argv[3]
     else:
-        outDir = os.path.relpath(jsonDir + "/../workspace/TS100/Core/Inc")
+        outDir = os.path.relpath(jsonDir + "/../source/Core/Inc")
         outFileUnitH = os.path.join(outDir, UNIT_H)
 
     if len(sys.argv) > 4:

Translations/translation_bg.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Нулиране завършено",
 		"YourGainMessage": "Усилване:",
 		"SettingsResetMessage": "Настройките бяха\nнулирани!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_cs.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Zisk:",
 		"SettingsResetMessage": "Tov. nas. obnov.",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_da.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Your gain:",
 		"SettingsResetMessage": "Settings were\nreset!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_de.json

@@ -6,7 +6,7 @@
 	"messages": {
 		"SettingsCalibrationDone": "Kalibrierung abgeschlossen!",
 		"SettingsCalibrationWarning": "Vor dem Fortfahren muss die Lötspitze vollständig abgekühlt sein!",
-		"SettingsResetWarning": "Sind Sie sicher, dass Sie alle Werte zurücksetzen wollen?",
+		"SettingsResetWarning": "Sicher, dass alle Werte zurückgesetzt werden sollen?",
 		"UVLOWarningString": "V niedr.",
 		"UndervoltageString": "Unterspannung",
 		"InputVoltageString": "V Eingang: ",
@@ -14,7 +14,7 @@
 		"BadTipString": "Spitze Defekt",
 		"SleepingSimpleString": "Zzz ",
 		"SleepingAdvancedString": "Ruhemodus...",
-		"WarningSimpleString": "HEIß",
+		"WarningSimpleString": "HEIß!",
 		"WarningAdvancedString": "! Achtung Heiß !",
 		"SleepingTipAdvancedString": "Temp:",
 		"IdleTipString": "Ist:",
@@ -22,30 +22,32 @@
 		"TipDisconnectedString": "Spitze fehlt",
 		"SolderingAdvancedPowerPrompt": "Leistung: ",
 		"OffString": "Aus",
+		"NoAccelerometerMessage": "Kein Bewegungssensor\nerkannt!",
+		"NoPowerDeliveryMessage": "Kein USB-PD IC\nerkannt!",
 		"ResetOKMessage": "Reset OK",
-		"YourGainMessage": "Your Gain:",
-		"SettingsResetMessage": "Einstellungen\nzurück gesetzt!",
-		"LockingKeysString": " LOCKED",
-		"UnlockingKeysString": "UNLOCKED",
-		"WarningKeysLockedString": "!LOCKED!"
+		"YourGainMessage": "Dein Faktor:",
+		"SettingsResetMessage": "Einstellungen\nzurückgesetzt!",
+		"LockingKeysString": "GESPERRT",
+		"UnlockingKeysString": "ENTSPERRT",
+		"WarningKeysLockedString": "!GESPERRT!"
 	},
 	"characters": {
 		"SettingRightChar": "R",
 		"SettingLeftChar": "L",
 		"SettingAutoChar": "A",
-		"SettingFastChar": "F",
-		"SettingSlowChar": "S",
-		"SettingStartSolderingChar": "T",
-		"SettingStartSleepChar": "S",
-		"SettingStartSleepOffChar": "O",
-		"SettingStartNoneChar": "F",
-		"SettingSensitivityOff": "O",
-		"SettingSensitivityLow": "L",
+		"SettingFastChar": "S",
+		"SettingSlowChar": "L",
+		"SettingStartSolderingChar": "L",
+		"SettingStartSleepChar": "R",
+		"SettingStartSleepOffChar": "K",
+		"SettingStartNoneChar": "A",
+		"SettingSensitivityOff": "A",
+		"SettingSensitivityLow": "N",
 		"SettingSensitivityMedium": "M",
 		"SettingSensitivityHigh": "H",
 		"SettingLockDisableChar": "D",
 		"SettingLockBoostChar": "B",
-		"SettingLockFullChar": "F"
+		"SettingLockFullChar": "V"
 	},
 	"menuGroups": {
 		"SolderingMenu": {
@@ -57,7 +59,7 @@
 		},
 		"PowerSavingMenu": {
 			"text2": [
-				"Schlaf-",
+				"Ruhe-",
 				"modus"
 			],
 			"desc": "Energiespareinstellungen"
@@ -87,38 +89,38 @@
 		},
 		"SleepTemperature": {
 			"text2": [
-				"Ruhetemp-",
-				"eratur"
+				"Ruhe-",
+				"temperatur"
 			],
-			"desc": "Ruhetemperatur"
+			"desc": "Ruhetemperatur der Spitze"
 		},
 		"SleepTimeout": {
 			"text2": [
 				"Ruhever-",
 				"zögerung"
 			],
-			"desc": "Ruhemodus nach <Sekunden/Minuten>"
+			"desc": "System wechselt in Ruhemodus, wenn innerhalb dieser Dauer nicht bewegt <S=Sekunden | M=Minuten>"
 		},
 		"ShutdownTimeout": {
 			"text2": [
 				"Abschalt-",
 				"zeit"
 			],
-			"desc": "Abschalten nach <Minuten>"
+			"desc": "System schaltet ab, wenn innerhalb dieser Dauer nicht bewegt <M=Minuten>"
 		},
 		"MotionSensitivity": {
 			"text2": [
 				"Bewegungs-",
 				"empfindlichk."
 			],
-			"desc": "Bewegungsempfindlichkeit <0=Aus, 1=Minimal ... 9=Maximal>"
+			"desc": "0=aus | 1=minimal | ... | 9=maximal"
 		},
 		"TemperatureUnit": {
 			"text2": [
 				"Temperatur-",
 				"einheit"
 			],
-			"desc": "Temperatureinheit <C=Celsius, F=Fahrenheit>"
+			"desc": "C=Celsius | F=Fahrenheit"
 		},
 		"AdvancedIdle": {
 			"text2": [
@@ -132,28 +134,28 @@
 				"Anzeige-",
 				"ausrichtung"
 			],
-			"desc": "Ausrichtung der Anzeige <A=Automatisch, L=Linkshändig, R=Rechtshändig>"
+			"desc": "A=automatisch | L=linkshändig | R=rechtshändig"
 		},
 		"BoostTemperature": {
 			"text2": [
-				"Boosttemp-",
-				"eratur"
+				"Boost-",
+				"temperatur"
 			],
-			"desc": "Temperatur im Boostmodus  (In der eingestellten Einheit)"
+			"desc": "Temperatur der Lötspitze im Boostmodus"
 		},
 		"AutoStart": {
 			"text2": [
 				"Start im",
-				"Lötmodus?"
+				"Lötmodus"
 			],
-			"desc": "Automatischer Start-Modus beim Einschalten der Spannungsversorgung. <T=Lötmodus S=Ruhezustand F=Aus>"
+			"desc": "Bestimmt das Heizverhalten beim Einschalten der Spannungsversorgung <A=aus | L=Lötmodus | R=Ruhemodus | K=Ruhemodus mit klater Spitze>"
 		},
 		"CooldownBlink": {
 			"text2": [
 				"Abkühl-",
-				"blinken?"
+				"blinken"
 			],
-			"desc": "Blinkende Temperaturanzeige beim Abkühlen, solange heiß ist."
+			"desc": "Temperaturanzeige blinkt beim Abkühlen, solange Spitze heiß ist"
 		},
 		"TemperatureCalibration": {
 			"text2": [
@@ -167,7 +169,7 @@
 				"Einstellungen",
 				"zurücksetzen?"
 			],
-			"desc": "Einstellungen auf werkseinstellungen zurück setzen"
+			"desc": "Werte werden auf Werkseinstellungen zurückgesetzt!"
 		},
 		"VoltageCalibration": {
 			"text2": [
@@ -188,7 +190,7 @@
 				"Scroll-",
 				"geschw."
 			],
-			"desc": "Scrollgeschwindigkeit der Texte <S=Langsam F=Schnell>"
+			"desc": "Scrollgeschwindigkeit der Erläuterungen <L=langsam | S=schnell>"
 		},
 		"TipModel": {
 			"text2": [
@@ -202,7 +204,7 @@
 				"Einfache",
 				"Kalibrierung"
 			],
-			"desc": "Einfache Kalibrierung mittels heißem Wasser"
+			"desc": "Einfache Kalibrierung mittels heißen Wassers"
 		},
 		"AdvancedCalibrationMode": {
 			"text2": [
@@ -213,66 +215,66 @@
 		},
 		"QCMaxVoltage": {
 			"text2": [
-				"Leistungs-",
-				"Aufnahme"
+				"Spannungs-",
+				"grenze"
 			],
-			"desc": "Leistungsaufnahme der verwendeten Spannungsversorgung"
+			"desc": "Maximal zulässige Spannung der verwendeten Spannungsversorgung <V=Volt>"
 		},
 		"PowerLimit": {
 			"text2": [
 				"Leistungs-",
-				"Limit"
+				"grenze"
 			],
-			"desc": "Maximale aufnahme der Lötspitze <Watt>"
+			"desc": "Maximale zulässige Leistungsaufnahme des Lötkolbens <W=Watt>"
 		},
 		"ReverseButtonTempChange": {
 			"text2": [
-				"Taste +-",
-				"Umkehren?"
+				"+- Tasten",
+				"umkehren?"
 			],
-			"desc": "Temperatur-Änderungs-Tasten-Belegung Plus-Minus umkehren?"
+			"desc": "Tastenbelegung zur Temperaturänderung umkehren"
 		},
 		"TempChangeShortStep": {
 			"text2": [
-				"T. Schritt",
-				"Taste kurz?"
+				"Temp-Schritt",
+				"Druck kurz"
 			],
-			"desc": "Temperaturwechselschritte bei kurzem Tastendruck!"
+			"desc": "Schrittweite für Temperaturwechsel bei kurzem Tastendruck"
 		},
 		"TempChangeLongStep": {
 			"text2": [
-				"T. Schritt",
-				"Taste Lang?"
+				"Temp-Schritt",
+				"Druck lang"
 			],
-			"desc": "Temperaturwechselschritte bei langem Tastendruck!"
+			"desc": "Schrittweite für Temperaturwechsel bei langem Tastendruck"
 		},
 		"PowerPulsePower": {
 			"text2": [
-				"Power",
-				"Pulse W"
+				"Leistungs-",
+				"impuls"
 			],
-			"desc": "Keep awake pulse power intensity"
+			"desc": "Powerbank wird mittels eines Impulses wach gehalten <Watt>"
 		},
 		"TipGain": {
 			"text2": [
-				"Modify",
-				"tip gain"
+				"Ändere",
+				"Spitzen Faktor"
 			],
-			"desc": "Tip gain"
+			"desc": "Spitzen Faktor"
 		},
 		"HallEffSensitivity": {
 			"text2": [
-				"Hall Eff",
-				"Sensitivity"
+				"Hall Sensor",
+				"Empfindlichkeit"
 			],
-			"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
+			"desc": "Empfindlichkeit des Hall Effekt Sensors beim Erkennen des Ruhemodus <A=aus | N=niedrig | M=mittel | H=hoch>"
 		},
 		"LockingMode": {
 			"text2": [
-				"Allow buttons",
-				"locking"
+				"Knopf-",
+				"sperre"
 			],
-			"desc": "When soldering, long press on both buttons lock them <D=Disable, B=Boost only, F=Full locking>"
+			"desc": "Langes drücken beider Knöpfe im Lötmodus, sperrt diese <D=deaktiviert | B=nur Boost | V=vollständig gesperrt>"
 		}
 	}
-}
+}

Translations/translation_en.json

@@ -6,7 +6,7 @@
 	"messages": {
 		"SettingsCalibrationDone": "Calibration done!",
 		"SettingsCalibrationWarning": "Please ensure the tip is at room temperature, before continuing!",
-		"SettingsResetWarning": "Are you sure you want to reset settings to default values?",
+		"SettingsResetWarning": "Sure you want to restore default settings?",
 		"UVLOWarningString": "DC LOW",
 		"UndervoltageString": "Undervoltage",
 		"InputVoltageString": "Input V: ",
@@ -15,17 +15,19 @@
 		"SleepingSimpleString": "Zzzz",
 		"SleepingAdvancedString": "Sleeping...",
 		"WarningSimpleString": "HOT!",
-		"WarningAdvancedString": "!!! TIP HOT !!!",
+		"WarningAdvancedString": "!!! HOT TIP !!!",
 		"SleepingTipAdvancedString": "Tip:",
 		"IdleTipString": "Tip:",
 		"IdleSetString": " Set:",
-		"TipDisconnectedString": "TIP DISCONNECTED",
+		"TipDisconnectedString": "NO TIP",
 		"SolderingAdvancedPowerPrompt": "Power: ",
 		"OffString": "Off",
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Your gain:",
 		"SettingsResetMessage": "Settings were\nreset!",
-		"LockingKeysString": " LOCKED",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
+		"LockingKeysString": "LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"
 	},
@@ -35,10 +37,10 @@
 		"SettingAutoChar": "A",
 		"SettingFastChar": "F",
 		"SettingSlowChar": "S",
-		"SettingStartSolderingChar": "T",
-		"SettingStartSleepChar": "S",
-		"SettingStartSleepOffChar": "O",
-		"SettingStartNoneChar": "F",
+		"SettingStartSolderingChar": "S",
+		"SettingStartSleepChar": "Z",
+		"SettingStartSleepOffChar": "R",
+		"SettingStartNoneChar": "O",
 		"SettingSensitivityOff": "O",
 		"SettingSensitivityLow": "L",
 		"SettingSensitivityMedium": "M",
@@ -58,7 +60,7 @@
 		"PowerSavingMenu": {
 			"text2": [
 				"Sleep",
-				"modes"
+				"mode"
 			],
 			"desc": "Power saving settings"
 		},
@@ -90,35 +92,35 @@
 				"Sleep",
 				"temp"
 			],
-			"desc": "Sleep temperature"
+			"desc": "Tip temperature while in \"sleep mode\""
 		},
 		"SleepTimeout": {
 			"text2": [
 				"Sleep",
 				"timeout"
 			],
-			"desc": "Sleep timeout <Minutes/Seconds>"
+			"desc": "Interval before \"sleep mode\" kicks in <S=seconds | M=minutes>"
 		},
 		"ShutdownTimeout": {
 			"text2": [
 				"Shutdown",
 				"timeout"
 			],
-			"desc": "Shutdown timeout <Minutes>"
+			"desc": "Interval before the iron shuts down <M=minutes>"
 		},
 		"MotionSensitivity": {
 			"text2": [
 				"Motion",
 				"sensitivity"
 			],
-			"desc": "Motion sensitivity <0=Off 1=Least sensitive 9=Most sensitive>"
+			"desc": "0=off | 1=least sensitive | ... | 9=most sensitive"
 		},
 		"TemperatureUnit": {
 			"text2": [
 				"Temperature",
 				"unit"
 			],
-			"desc": "Temperature unit <C=Celsius F=Fahrenheit>"
+			"desc": "C=Celsius | F=Fahrenheit"
 		},
 		"AdvancedIdle": {
 			"text2": [
@@ -132,63 +134,63 @@
 				"Display",
 				"orientation"
 			],
-			"desc": "Display orientation <A=Automatic L=Left-handed R=Right-handed>"
+			"desc": "A=automatic | L=left-handed | R=right-handed"
 		},
 		"BoostTemperature": {
 			"text2": [
 				"Boost",
 				"temp"
 			],
-			"desc": "Temperature when in \"boost mode\""
+			"desc": "Temperature used in \"boost mode\""
 		},
 		"AutoStart": {
 			"text2": [
 				"Auto",
 				"start"
 			],
-			"desc": "Automatically starts the iron into soldering on power up <F=Off T=Soldering S=Sleep O=Sleep at room temperature>"
+			"desc": "Starts the iron into soldering mode on power up <O=off | S=soldering | Z=sleep | R=sleep at room temperature>"
 		},
 		"CooldownBlink": {
 			"text2": [
 				"Cooldown",
 				"blink"
 			],
-			"desc": "Blink the temperature on the cooling screen while the tip is still hot"
+			"desc": "Flash the temperature after heating was halted, while the tip is still hot"
 		},
 		"TemperatureCalibration": {
 			"text2": [
 				"Calibrate",
 				"temperature?"
 			],
-			"desc": "Calibrate tip offset?"
+			"desc": "Start tip temperature offset calibration"
 		},
 		"SettingsReset": {
 			"text2": [
 				"Factory",
-				"Reset?"
+				"reset?"
 			],
-			"desc": "Reset all settings!"
+			"desc": "Reset settings to default"
 		},
 		"VoltageCalibration": {
 			"text2": [
 				"Calibrate",
 				"input voltage?"
 			],
-			"desc": "VIN Calibration <long press to exit>"
+			"desc": "Start VIN calibration <long press to exit>"
 		},
 		"AdvancedSoldering": {
 			"text2": [
 				"Detailed",
 				"solder screen"
 			],
-			"desc": "Display detailed information while soldering"
+			"desc": "Display detailed information in a smaller font on soldering screen"
 		},
 		"ScrollingSpeed": {
 			"text2": [
 				"Scrolling",
 				"speed"
 			],
-			"desc": "Speed this text scrolls past at <S=Slow F=Fast>"
+			"desc": "Speed info text scrolls past at <S=slow | F=fast>"
 		},
 		"TipModel": {
 			"text2": [
@@ -202,28 +204,28 @@
 				"Simple",
 				"calibration"
 			],
-			"desc": "Simple calibration using hot water"
+			"desc": "Using hot water to calibrate tip"
 		},
 		"AdvancedCalibrationMode": {
 			"text2": [
 				"Advanced",
 				"calibration"
 			],
-			"desc": "Advanced calibration using thermocouple on the tip"
+			"desc": "Using a thermocouple on the tip to calibrate it"
 		},
 		"QCMaxVoltage": {
 			"text2": [
 				"QC",
-				"Voltage"
+				"voltage"
 			],
-			"desc": "Desired max QC Voltage negotiated for"
+			"desc": "Desired max QC voltage the iron negotiates for"
 		},
 		"PowerLimit": {
 			"text2": [
 				"Power",
 				"limit"
 			],
-			"desc": "Maximum power the iron can use <Watts>"
+			"desc": "Maximum power the iron can use <W=watt>"
 		},
 		"ReverseButtonTempChange": {
 			"text2": [
@@ -237,21 +239,21 @@
 				"Temp change",
 				"short"
 			],
-			"desc": "Temperature change steps on short button press"
+			"desc": "Temperature change increment on short button press"
 		},
 		"TempChangeLongStep": {
 			"text2": [
 				"Temp change",
 				"long"
 			],
-			"desc": "Temperature change steps on long button press"
+			"desc": "Temperature change increment on long button press"
 		},
 		"PowerPulsePower": {
 			"text2": [
 				"Power",
-				"Pulse W"
+				"pulse"
 			],
-			"desc": "Keep awake pulse power intensity"
+			"desc": "Intensity of power of keep-awake-pulse <watt>"
 		},
 		"TipGain": {
 			"text2": [
@@ -262,17 +264,17 @@
 		},
 		"HallEffSensitivity": {
 			"text2": [
-				"Hall Eff",
-				"Sensitivity"
+				"Hall sensor",
+				"sensitivity"
 			],
-			"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
+			"desc": "Sensitivity of the Hall effect sensor to detect sleep <O=off | L=low | M=medium | H=high>"
 		},
 		"LockingMode": {
 			"text2": [
-				"Allow buttons",
-				"locking"
+				"Allow locking",
+				"buttons"
 			],
-			"desc": "When soldering, long press on both buttons lock them <D=Disable, B=Boost only, F=Full locking>"
+			"desc": "When soldering, long press both buttons, to lock them <D=disable | B=\"boost mode\" only | F=full locking>"
 		}
 	}
-}
+}

Translations/translation_es.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Hecho.       ",
 		"YourGainMessage": "Gananc.:",
 		"SettingsResetMessage": "Ajustes borrados",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_fi.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Your gain:",
 		"SettingsResetMessage": "Settings were\nreset!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_fr.json

@@ -5,25 +5,27 @@
 	"messages": {
 		"SettingsCalibrationDone": "Calibration effectuée !",
 		"SettingsCalibrationWarning": "Assurez-vous que la panne soit à température ambiante avant de continuer !",
-		"SettingsResetWarning": "Voulez-vous vraiment réinitialiser les paramètres aux valeurs d'usine ?",
+		"SettingsResetWarning": "Voulez-vous vraiment réinitialiser les paramètres aux valeurs par défaut ?",
 		"UVLOWarningString": "DC FAIBL",
 		"UndervoltageString": "Sous-tension",
-		"InputVoltageString": "V d'entrée :",
-		"WarningTipTempString": "Temp. Panne :",
+		"InputVoltageString": "V d'entrée : ",
+		"WarningTipTempString": "Temp. Panne : ",
 		"BadTipString": "PANNE HS",
 		"SleepingSimpleString": "Zzzz",
 		"SleepingAdvancedString": "En veille...",
 		"WarningSimpleString": "CHAUD !",
 		"WarningAdvancedString": "ATTENTION ! CHAUD !",
-		"SleepingTipAdvancedString": "Panne :",
-		"IdleTipString": "Act :",
-		"IdleSetString": " Reg :",
+		"SleepingTipAdvancedString": "Panne : ",
+		"IdleTipString": "Act : ",
+		"IdleSetString": "Reg : ",
 		"TipDisconnectedString": "PANNE DÉBRANCHÉE",
 		"SolderingAdvancedPowerPrompt": "Puissance : ",
 		"OffString": "Off",
 		"ResetOKMessage": "Reset OK",
-		"YourGainMessage": "Gain :",
+		"YourGainMessage": "Gain : ",
 		"SettingsResetMessage": "Réglage réinit. !",
+		"NoAccelerometerMessage": "Accéléromètre\nnon détecté !",
+		"NoPowerDeliveryMessage": "Pas d'USB-PD\ndétecté !",
 		"LockingKeysString": "VERROUIL",
 		"UnlockingKeysString": "DEVERROU",
 		"WarningKeysLockedString": "! VERR. !"
@@ -38,8 +40,8 @@
 		"SettingStartSleepChar": "V",
 		"SettingStartSleepOffChar": "O",
 		"SettingStartNoneChar": "D",
-		"SettingSensitivityOff": "O",
-		"SettingSensitivityLow": "L",
+		"SettingSensitivityOff": "D",
+		"SettingSensitivityLow": "B",
 		"SettingSensitivityMedium": "M",
 		"SettingSensitivityHigh": "H",
 		"SettingLockDisableChar": "D",
@@ -80,9 +82,9 @@
 		"DCInCutoff": {
 			"text2": [
 				"Source",
-				"d'alim"
+				"d'alim."
 			],
-			"desc": "Source d'alimentation. Règle la tension de coupure <DC=10V S=3.3V par cellules>"
+			"desc": "Source d'alimentation. Règle la tension de coupure <DC=10V> <S=3.3V par cellules>"
 		},
 		"SleepTemperature": {
 			"text2": [
@@ -96,42 +98,42 @@
 				"Délai",
 				"veille"
 			],
-			"desc": "Délai avant mise en veille <Minutes>"
+			"desc": "Délai avant mise en veille <S=secondes | M=minutes>"
 		},
 		"ShutdownTimeout": {
 			"text2": [
 				"Délai",
 				"extinction"
 			],
-			"desc": "Délai avant extinction <Minutes>"
+			"desc": "Délai avant extinction <M=minutes>"
 		},
 		"MotionSensitivity": {
 			"text2": [
 				"Sensibilité",
 				"au mouvement"
 			],
-			"desc": "Sensibilité du capteur de mouvement <0=Inactif 1=Peu sensible 9=Tres sensible>"
+			"desc": "0=inactif | 1=peu sensible | ... | 9=très sensible"
 		},
 		"TemperatureUnit": {
 			"text2": [
 				"Unité de",
 				"température"
 			],
-			"desc": "Unité de température <C=Celsius F=Fahrenheit>"
+			"desc": "Unité de température <C=Celsius | F=Fahrenheit>"
 		},
 		"AdvancedIdle": {
 			"text2": [
 				"Écran veille",
 				"détaillé"
 			],
-			"desc": "Afficher des informations détaillées lors de la veille."
+			"desc": "Afficher les informations détaillées lors de la veille."
 		},
 		"DisplayRotation": {
 			"text2": [
 				"Orientation",
 				"de l'écran"
 			],
-			"desc": "Orientation de l'affichage <A=Automatique G=Gaucher D=Droitier>"
+			"desc": "Orientation de l'affichage <A=automatique | G=gaucher | D=droitier>"
 		},
 		"BoostTemperature": {
 			"text2": [
@@ -145,7 +147,7 @@
 				"Démarrage",
 				"automatique"
 			],
-			"desc": "Démarrer automatiquement la soudure a l'allumage <A=Activé, V=Mode Veille, D=Désactivé>"
+			"desc": "Démarrer automatiquement la soudure à l'allumage <D=désactivé | A=activé | V=mode veille | O=mode veille à température ambiante>"
 		},
 		"CooldownBlink": {
 			"text2": [
@@ -173,21 +175,21 @@
 				"Étalonner",
 				"tension d'entrée"
 			],
-			"desc": "Étalonner tension d'entrée. Boutons pour ajuster, appui long pour quitter"
+			"desc": "Étalonner tension d'entrée <appui long pour quitter>"
 		},
 		"AdvancedSoldering": {
 			"text2": [
 				"Écran soudure",
 				"détaillé"
 			],
-			"desc": "Afficher des informations détaillées pendant la soudure"
+			"desc": "Afficher les informations détaillées pendant la soudure"
 		},
 		"ScrollingSpeed": {
 			"text2": [
 				"Vitesse de",
 				"défilement"
 			],
-			"desc": "Vitesse de défilement de ce texte en <R=Rapide L=Lent>"
+			"desc": "Vitesse de défilement du texte <R=rapide | L=lent>"
 		},
 		"TipModel": {
 			"text2": [
@@ -206,30 +208,30 @@
 		"AdvancedCalibrationMode": {
 			"text2": [
 				"Calibration",
-				"avancées"
+				"avancée"
 			],
-			"desc": "Calibration avancées à l'aide d'un thermocouple sur la panne"
+			"desc": "Calibration avancée à l'aide d'un thermocouple sur la panne"
 		},
 		"QCMaxVoltage": {
 			"text2": [
-				"Puissance de",
-				"l'alimentation"
+				"Tension max.",
+				"QC"
 			],
-			"desc": "Puissance de l'alimentation utilisée"
+			"desc": "Tension maximale désirée avec une alimentation QC"
 		},
 		"PowerLimit": {
 			"text2": [
-				"Puissance",
-				"limite"
+				"Limite de",
+				"puissance"
 			],
-			"desc": "Puissance maximale utilisable <Watts>"
+			"desc": "Puissance maximale utilisable <W=watts>"
 		},
 		"ReverseButtonTempChange": {
 			"text2": [
 				"Inverser les",
-				"touches + - ?"
+				"touches + -"
 			],
-			"desc": "Inversez l'assignation +/- du bouton de changement de température de la pointe."
+			"desc": "Inverser l'assignation des boutons d'ajustement de température de la panne."
 		},
 		"TempChangeShortStep": {
 			"text2": [
@@ -248,9 +250,9 @@
 		"PowerPulsePower": {
 			"text2": [
 				"Puissance des",
-				"impulsion W"
+				"impulsions"
 			],
-			"desc": "Puissance des impulsions pour éviter la mise en veille des batteries"
+			"desc": "Puissance des impulsions pour éviter la mise en veille des batteries <watt>"
 		},
 		"TipGain": {
 			"text2": [
@@ -261,17 +263,17 @@
 		},
 		"LockingMode": {
 			"text2": [
-				"Autoriser le",
-				"verrouillage"
+				"Verrouiller",
+				"les boutons"
 			],
-			"desc": "Permet de verrouiller les touches pendant la soudure sur un appuis long des 2 bouttons <D=Désactiver, B=Boost seulement, V=Verr. total>"
+			"desc": "Pendant la soudure, appuyer sur les deux boutons pour les verrouiller <D=désactivé | B=boost seulement | V=verr. total>"
 		},
 		"HallEffSensitivity": {
 			"text2": [
 				"Sensibilité",
 				"capteur effet hall"
 			],
-			"desc": "Sensibilité du capteur à effet Hall lors de la détection de mise en veille <O=Off,L=Low,M=Medium,H=High>"
+			"desc": "Sensibilité du capteur à effet Hall lors de la détection de mise en veille <D=désactivé | B=basse | M=moyenne | H=haute>"
 		}
 	}
 }

Translations/translation_hr.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Your gain:",
 		"SettingsResetMessage": "Settings were\nreset!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_hu.json

@@ -4,29 +4,31 @@
 	"cyrillicGlyphs": false,
 	"messages": {
 		"SettingsCalibrationDone": "Kalibráció befejezve!",
-		"SettingsCalibrationWarning": "Folytatás előtt győződjön meg róla, hogy a hegy szobahőmérsékletű!",
+		"SettingsCalibrationWarning": "Folytatás előtt győződjön meg róla, hogy a páka szobahőmérsékletű!",
 		"SettingsResetWarning": "Biztosan visszaállítja a beállításokat az alapértelmezett értékekre?",
 		"UVLOWarningString": "DC KEVÉS",
 		"UndervoltageString": "Alulfeszültség",
 		"InputVoltageString": "Bemenet V: ",
 		"WarningTipTempString": "Hegy hő: ",
-		"BadTipString": "HEGY HIB",
+		"BadTipString": "PÁKAHIBA",
 		"SleepingSimpleString": "Zzzz",
 		"SleepingAdvancedString": "Alvás...",
-		"WarningSimpleString": "FORR",
-		"WarningAdvancedString": "!! FORRÓ HEGY !!",
-		"SleepingTipAdvancedString": "Hegy:",
-		"IdleTipString": "Hegy:",
-		"IdleSetString": " Cél:",
-		"TipDisconnectedString": "HEGY LEVÉVE",
+		"WarningSimpleString": "FORRÓ!",
+		"WarningAdvancedString": "!! FORRÓ PÁKA !!",
+		"SleepingTipAdvancedString": "Páka:",
+		"IdleTipString": "Páka:",
+		"IdleSetString": "Cél:",
+		"TipDisconnectedString": "PÁKA LEVÉVE",
 		"SolderingAdvancedPowerPrompt": "Telj: ",
 		"OffString": "Ki",
-		"ResetOKMessage": "Reset OK",
-		"YourGainMessage": "Your gain:",
-		"SettingsResetMessage": "Settings were\nreset!",
-		"LockingKeysString": " LOCKED",
-		"UnlockingKeysString": "UNLOCKED",
-		"WarningKeysLockedString": "!LOCKED!"
+		"ResetOKMessage": "Törlés OK",
+		"YourGainMessage": "Erősítés:",
+		"SettingsResetMessage": "Beállítások\ntörölve!",
+		"NoAccelerometerMessage": "Nincs gyorsulásmérő!",
+		"NoPowerDeliveryMessage": "Nincs USB-PD IC!",
+		"LockingKeysString": "LEZÁRVA",
+		"UnlockingKeysString": "FELOLDVA",
+		"WarningKeysLockedString": "!LEZÁRVA!"
 	},
 	"characters": {
 		"SettingRightChar": "J",
@@ -34,17 +36,17 @@
 		"SettingAutoChar": "A",
 		"SettingFastChar": "G",
 		"SettingSlowChar": "L",
-		"SettingStartSolderingChar": "T",
-		"SettingStartSleepChar": "S",
-		"SettingStartSleepOffChar": "O",
-		"SettingStartNoneChar": "F",
-		"SettingSensitivityOff": "O",
-		"SettingSensitivityLow": "L",
-		"SettingSensitivityMedium": "M",
-		"SettingSensitivityHigh": "H",
-		"SettingLockDisableChar": "D",
+		"SettingStartSolderingChar": "F",
+		"SettingStartSleepChar": "Z",
+		"SettingStartSleepOffChar": "S",
+		"SettingStartNoneChar": "K",
+		"SettingSensitivityOff": "0",
+		"SettingSensitivityLow": "A",
+		"SettingSensitivityMedium": "K",
+		"SettingSensitivityHigh": "M",
+		"SettingLockDisableChar": "K",
 		"SettingLockBoostChar": "B",
-		"SettingLockFullChar": "F"
+		"SettingLockFullChar": "T"
 	},
 	"menuGroups": {
 		"SolderingMenu": {
@@ -63,7 +65,7 @@
 		},
 		"UIMenu": {
 			"text2": [
-				"Felhasználó",
+				"Felhasználói",
 				"felület"
 			],
 			"desc": "Felhasználói felület beállításai"
@@ -82,21 +84,21 @@
 				"Áram",
 				"forrás"
 			],
-			"desc": "Áramforrás. Beállítja a lekapcsolási feszültséget. <DC 10V> <S 3.3V cellánként>"
+			"desc": "Kikapcsolási feszültség beállítása (DC:10V, S:3.3V/LiPo cella)"
 		},
 		"SleepTemperature": {
 			"text2": [
 				"Alvási",
-				"hőfok"
+				"hőmérs."
 			],
-			"desc": "Alvási hőmérséklet <C>"
+			"desc": "Hőmérséklet alvó módban <C/F>"
 		},
 		"SleepTimeout": {
 			"text2": [
 				"Alvás",
 				"időzítő"
 			],
-			"desc": "Alvás időzítő <perc/másodperc>"
+			"desc": "Alvási időzítő <perc/másodperc>"
 		},
 		"ShutdownTimeout": {
 			"text2": [
@@ -110,33 +112,33 @@
 				"Mozgás",
 				"érzékenység"
 			],
-			"desc": "Mozgás érzékenység beállítása. <0.kikapcsolva 1.legkevésbé érzékeny 9.legérzékenyebb>"
+			"desc": "Mozgás érzékenység beállítása (0=kikapcsolva 1=legkevésbé érzékeny 9=legérzékenyebb)"
 		},
 		"TemperatureUnit": {
 			"text2": [
 				"Hőmérséklet",
 				"mértékegysége"
 			],
-			"desc": "Hőmérséklet mértékegysége <C=Celsius F=Fahrenheit>"
+			"desc": "Hőmérséklet mértékegysége (C=Celsius F=Fahrenheit)"
 		},
 		"AdvancedIdle": {
 			"text2": [
 				"Részletes",
 				"készenlét"
 			],
-			"desc": "Részletes információ megjelenítése kisebb betűméretben a készenléti képernyőn."
+			"desc": "Részletes információk megjelenítése kisebb betűméretben a készenléti képernyőn"
 		},
 		"DisplayRotation": {
 			"text2": [
 				"Kijelző",
 				"tájolása"
 			],
-			"desc": "Kijelző tájolása <A. automatikus B. balkezes J. jobbkezes>"
+			"desc": "Kijelző tájolása (A=automatikus B=balkezes J=jobbkezes)"
 		},
 		"BoostTemperature": {
 			"text2": [
 				"Boost",
-				"hőfok"
+				"hőmérs."
 			],
 			"desc": "Hőmérséklet \"boost\" módban"
 		},
@@ -145,21 +147,21 @@
 				"Automatikus",
 				"indítás"
 			],
-			"desc": "Bekapcsolás után automatikusan lépjen forrasztás módba. T=forrasztás, S=alvó mód, F=ki"
+			"desc": "Bekapcsolás után automatikusan lépjen forrasztás módba (F=forrasztás S=szobahőmérséklet Z=alvó mód K=ki)"
 		},
 		"CooldownBlink": {
 			"text2": [
 				"Villogás",
 				"hűléskor"
 			],
-			"desc": "Villogjon a hőmérséklet hűlés közben, amíg a hegy forró."
+			"desc": "Villogjon a hőmérséklet hűlés közben, amíg a páka forró"
 		},
 		"TemperatureCalibration": {
 			"text2": [
 				"Hőmérséklet",
 				"kalibrálása?"
 			],
-			"desc": "Hegy hőmérséklet-különbségének kalibrálása."
+			"desc": "Páka hőmérséklet-érzékelőjének kalibrálása"
 		},
 		"SettingsReset": {
 			"text2": [
@@ -170,15 +172,15 @@
 		},
 		"VoltageCalibration": {
 			"text2": [
-				"Bemeneti fesz",
+				"Bemeneti fesz.",
 				"kalibrálása?"
 			],
-			"desc": "Bemeneti feszültség kalibrálása. Röviden megnyomva módosítás, hosszan megnyomva kilépés"
+			"desc": "Bemeneti feszültség kalibrálása (röviden megnyomva módosítás, hosszan megnyomva kilépés)"
 		},
 		"AdvancedSoldering": {
 			"text2": [
 				"Részletes",
-				"forr. kép."
+				"forr.kép"
 			],
 			"desc": "Részletes információk megjelenítése forrasztás közben"
 		},
@@ -191,10 +193,10 @@
 		},
 		"TipModel": {
 			"text2": [
-				"Forrasztóhegy",
+				"Forr.páka",
 				"modell"
 			],
-			"desc": "Forrasztóhegy modell kiválasztása"
+			"desc": "Forrasztópáka modell kiválasztása"
 		},
 		"SimpleCalibrationMode": {
 			"text2": [
@@ -212,66 +214,66 @@
 		},
 		"QCMaxVoltage": {
 			"text2": [
-				"Bemeneti",
-				"teljesítmény"
+				"Max. USB",
+				"fesz."
 			],
-			"desc": "A tápegység által leadott teljesítmény"
+			"desc": "Maximális USB feszültség (QuickCharge)"
 		},
 		"PowerLimit": {
 			"text2": [
-				"Telj",
+				"Teljesítm.",
 				"maximum"
 			],
-			"desc": "Maximális teljesitmény beállitása <Watts>"
+			"desc": "Maximális felvett teljesitmény beállitása"
 		},
 		"ReverseButtonTempChange": {
 			"text2": [
-				"GOMB +-",
-				"Felcseréled?"
+				"+/- gomb",
+				"fordítva"
 			],
-			"desc": "A páka hömérséklet növelés csökkentési gombok felcserélése."
+			"desc": "Páka hőmérséklet növelés/csökkentés gombok felcserélése"
 		},
 		"TempChangeShortStep": {
 			"text2": [
-				"Hömérséklet",
-				"váltás rövid?"
+				"Hőm.váltás",
+				"rövid"
 			],
-			"desc": "Hömérséklet váltás rövid gombnyomásrs bekapcsolva!"
+			"desc": "Hőmérséklet váltás rövid gombnyomásra <C/F>"
 		},
 		"TempChangeLongStep": {
 			"text2": [
-				"Hömérséklet",
-				"váltás hosszú?"
+				"Hőm.váltás",
+				"hosszú"
 			],
-			"desc": "Hömérséklet váltás hosszú gombnyomásrs bekapcsolva!"
+			"desc": "Hőmérséklet váltás hosszú gombnyomásra <C/F>"
 		},
 		"PowerPulsePower": {
 			"text2": [
-				"Telj power",
-				"bank üzem W"
+				"Ébrentartó",
+				"pulzus W"
 			],
-			"desc": "Powerbank üzemnél nem engedi a powerbankot kikapcsolni idönkénti áram felvételt generál. "
+			"desc": "Powerbankot ébrentartó áramfelvételi pulzusok nagysága <W>"
 		},
 		"TipGain": {
 			"text2": [
-				"Modify",
-				"tip gain"
+				"Pákaerősítés",
+				""
 			],
-			"desc": "Tip gain"
+			"desc": "Pákaerősítés állítása"
 		},
 		"HallEffSensitivity": {
 			"text2": [
-				"Hall Eff",
-				"Sensitivity"
+				"Alvásérzékelő",
+				"érzékenység"
 			],
-			"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
+			"desc": "Alvásérzékelő gyorsulásmérő érzékenysége (0=ki A=alacsony K=közepes M=magas)"
 		},
 		"LockingMode": {
 			"text2": [
-				"Allow buttons",
-				"locking"
+				"Lezárás",
+				"enged."
 			],
-			"desc": "When soldering, long press on both buttons lock them <D=Disable, B=Boost only, F=Full locking>"
+			"desc": "Forrasztás közben mindkét gombot hosszan lenyomva rögzíti a hőmérsékletet (K=ki B=csak \"boost\" mód T=teljes lezárás)"
 		}
 	}
-}
+}

Translations/translation_it.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Guad.: ",
 		"SettingsResetMessage": "Reset effettuato",
+		"NoAccelerometerMessage": "Accelerometro\nnon rilevato",
+		"NoPowerDeliveryMessage": "USB-PD non\ndisponibile",
 		"LockingKeysString": "Blocc.",
 		"UnlockingKeysString": "Sblocc.",
 		"WarningKeysLockedString": "BLOCCATO"

Translations/translation_lt.json

@@ -19,11 +19,13 @@
 		"IdleTipString": "Ant:",
 		"IdleSetString": " Nust:",
 		"TipDisconnectedString": "NĖRA ANTGALIO",
-		"SolderingAdvancedPowerPrompt": "Maitinimas: ",
+		"SolderingAdvancedPowerPrompt": "Galia: ",
 		"OffString": "Išj",
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Gain:",
 		"SettingsResetMessage": "Nust. atstatyti!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " UŽRAKIN",
 		"UnlockingKeysString": "ATRAKIN",
 		"WarningKeysLockedString": "!UŽRAK!"
@@ -274,4 +276,4 @@
 			"desc": "Lituodami, ilgai paspauskite abu mygtukus, kad juos užrakintumėte <I=Išjungta, T=Tik turbo režimas, V=Visiškas užrakinimas>"
 		}
 	}
-}
+}

Translations/translation_nl.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Niveau:",
 		"SettingsResetMessage": "Instellingen zijn\ngereset!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " GEBLOKKEERD",
 		"UnlockingKeysString": "GEDEBLOKKEERD",
 		"WarningKeysLockedString": "!GEBLOKKEERD!"

Translations/translation_nl_be.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Your gain:",
 		"SettingsResetMessage": "Settings were\nreset!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_no.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Your gain:",
 		"SettingsResetMessage": "Settings were\nreset!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_pl.json

@@ -25,6 +25,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Us.zysk:",
 		"SettingsResetMessage": "Ust. zresetowane",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " ZABLOK.",
 		"UnlockingKeysString": "ODBLOK.",
 		"WarningKeysLockedString": "!ZABLOK!"
@@ -251,7 +253,7 @@
 				"Moc",
 				"impulsu"
 			],
-			"desc": "Utrzymuj moc impulsu na wybranym poziomie <W>"
+			"desc": "W przypadku używania powerbanku, utrzymuj moc na poziomie <W> aby nie uśpić powerbanku"
 		},
 		"TipGain": {
 			"text2": [

Translations/translation_pt.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Your gain:",
 		"SettingsResetMessage": "Settings were\nreset!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_ru.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Сброс OK",
 		"YourGainMessage": "Прирост:",
 		"SettingsResetMessage": "Настройки сброшены!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"
@@ -274,4 +276,4 @@
 			"desc": "При работе длинное нажатие обеих кнопок блокирует их <D=Отключено, B=Только турбо, F=Полная блокировка>"
 		}
 	}
-}
+}

Translations/translation_sk.json

@@ -5,28 +5,30 @@
 	"messages": {
 		"SettingsCalibrationDone": "Kalibrácia hotová!",
 		"SettingsCalibrationWarning": "Najprv sa prosím uistite, že hrot má izbovú teplotu!",
-		"SettingsResetWarning": "Naozaj chcete obnovit nastavenia?",
+		"SettingsResetWarning": "Naozaj chcete obnovit továrenské nastavenia?",
 		"UVLOWarningString": "Nízke U!",
 		"UndervoltageString": "Nízke napätie",
 		"InputVoltageString": "Vstupné U: ",
 		"WarningTipTempString": "Tep. hrotu: ",
 		"BadTipString": "ZLÝ HROT",
 		"SleepingSimpleString": "Chrr",
-		"SleepingAdvancedString": "Kľudový režim...",
-		"WarningSimpleString": "HOT!",
+		"SleepingAdvancedString": "Pokojový režim..",
+		"WarningSimpleString": "PÁLI",
 		"WarningAdvancedString": "HROT JE HORÚCI !",
 		"SleepingTipAdvancedString": "Hrot:",
 		"IdleTipString": "Hrot:",
-		"IdleSetString": " Set:",
+		"IdleSetString": "Cieľ:",
 		"TipDisconnectedString": "HROT ODPOJENÝ",
 		"SolderingAdvancedPowerPrompt": "Výkon: ",
 		"OffString": "Vyp",
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Zisk:",
-		"SettingsResetMessage": "Nast. Obnovené!",
-		"LockingKeysString": " LOCKED",
-		"UnlockingKeysString": "UNLOCKED",
-		"WarningKeysLockedString": "!LOCKED!"
+		"SettingsResetMessage": "Tov. nas. obnov.",
+		"NoAccelerometerMessage": "Bez pohyb. senz.",
+		"NoPowerDeliveryMessage": "Chýba čip USB-PD",
+		"LockingKeysString": " ZABLOK.",
+		"UnlockingKeysString": "ODBLOK.",
+		"WarningKeysLockedString": "!ZABLOK!"
 	},
 	"characters": {
 		"SettingRightChar": "P",
@@ -38,13 +40,13 @@
 		"SettingStartSleepChar": "K",
 		"SettingStartSleepOffChar": "O",
 		"SettingStartNoneChar": "N",
-		"SettingSensitivityOff": "O",
-		"SettingSensitivityLow": "L",
-		"SettingSensitivityMedium": "M",
-		"SettingSensitivityHigh": "H",
-		"SettingLockDisableChar": "D",
+		"SettingSensitivityOff": "Z",
+		"SettingSensitivityLow": "N",
+		"SettingSensitivityMedium": "S",
+		"SettingSensitivityHigh": "V",
+		"SettingLockDisableChar": "Z",
 		"SettingLockBoostChar": "B",
-		"SettingLockFullChar": "F"
+		"SettingLockFullChar": "P"
 	},
 	"menuGroups": {
 		"SolderingMenu": {
@@ -86,24 +88,24 @@
 		},
 		"SleepTemperature": {
 			"text2": [
-				"Kľudová",
+				"Pokojová",
 				"teplota"
 			],
-			"desc": "Kľudová teplota (v nastavených jednotkách)"
+			"desc": "Pokojová teplota (v nastavených jednotkách)"
 		},
 		"SleepTimeout": {
 			"text2": [
-				"Kľudový",
+				"Pokojový",
 				"režim po"
 			],
-			"desc": "Kludovy rezim po <sekundach/minutach>"
+			"desc": "Pokojový režim po <S=sekundách/M=minútach>"
 		},
 		"ShutdownTimeout": {
 			"text2": [
 				"Vypnutie",
 				"po"
 			],
-			"desc": "Čas na vypnutie <minuty>"
+			"desc": "Čas na vypnutie <minúty>"
 		},
 		"MotionSensitivity": {
 			"text2": [
@@ -122,9 +124,9 @@
 		"AdvancedIdle": {
 			"text2": [
 				"Detaily v",
-				"kľud. režime"
+				"pokoj. režime"
 			],
-			"desc": "Zobraziť detailné informácie v kľudovom režime <T=Zap, F=Vyp>"
+			"desc": "Zobraziť detailné informácie v pokojovom režime <T=Zap, F=Vyp>"
 		},
 		"DisplayRotation": {
 			"text2": [
@@ -171,9 +173,9 @@
 		"VoltageCalibration": {
 			"text2": [
 				"Kalibrácia",
-				"vst. napätia"
+				"nap. napätia"
 			],
-			"desc": "Kalibrácia napätia. Krátke stlačenie mení nastavenie, dlhé stlačenie pre návrat"
+			"desc": "Kalibrácia napájacieho napätia. Krátke stlačenie mení nastavenie, dlhé stlačenie pre návrat"
 		},
 		"AdvancedSoldering": {
 			"text2": [
@@ -187,7 +189,7 @@
 				"Rýchlost",
 				"skrolovania"
 			],
-			"desc": "Rychlost pohybu tohoto textu"
+			"desc": "Rýchlosť pohybu tohto textu"
 		},
 		"TipModel": {
 			"text2": [
@@ -247,31 +249,31 @@
 		},
 		"PowerPulsePower": {
 			"text2": [
-				"Impulz",
-				"W"
+				"Intenzita",
+				"impulzu"
 			],
-			"desc": "Impulz udržujúci napájací zdroj zapnutý <watt>"
+			"desc": "Impulz udržujúci napájací zdroj zapnutý (power banky) <watt>"
 		},
 		"TipGain": {
 			"text2": [
 				"Zisk",
 				"hrotu"
 			],
-			"desc": "Úprava zisku hrotu"
+			"desc": "Úprava zisku hrotu (meranie)"
 		},
 		"HallEffSensitivity": {
 			"text2": [
-				"Hall Eff",
-				"Sensitivity"
+				"Citliv.",
+				"Hall"
 			],
-			"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
+			"desc": "Citlivosť Halloveho senzora pre detekciu spánku <Z=Zakázať,N=Nízka,S=Stredná,V=Vysoká>"
 		},
 		"LockingMode": {
 			"text2": [
-				"Allow buttons",
-				"locking"
+				"Povoliť zámok",
+				"tlačidiel"
 			],
-			"desc": "When soldering, long press on both buttons lock them <D=Disable, B=Boost only, F=Full locking>"
+			"desc": "Zamknutie tlačidiel - dlhé stlačenie oboch naraz počas spájkovania <Z=Zakázať, B=Okrem boost, P=Plné zamknutie>"
 		}
 	}
-}
+}

Translations/translation_sl.json

@@ -1,32 +1,34 @@
 {
 	"languageCode": "SL",
-	"languageLocalName": "Slovensko",
+	"languageLocalName": "Slovenščina",
 	"cyrillicGlyphs": false,
 	"messages": {
 		"SettingsCalibrationDone": "Kalibracija opravljena!",
-		"SettingsCalibrationWarning": "Preden nadaljujete, mora biti konica na sobni temperaturi!",
-		"SettingsResetWarning": "Ste prepričani, da želite ponastaviti nastavitve na privzete vrednosti?",
+		"SettingsCalibrationWarning": "Pred nadaljevanjem mora biti konica segreta na sobno temperaturo!",
+		"SettingsResetWarning": "Res želite ponastaviti na privzete nastavitve?",
 		"UVLOWarningString": "NIZKA U",
 		"UndervoltageString": "Nizka napetost",
 		"InputVoltageString": "Vhodna U: ",
 		"WarningTipTempString": "Temp. kon.: ",
-		"BadTipString": "OKVARA K",
+		"BadTipString": "KONICA?",
 		"SleepingSimpleString": "Zzzz",
 		"SleepingAdvancedString": "Spim...",
-		"WarningSimpleString": "HOT!",
-		"WarningAdvancedString": "!!!VROČA KON.!!!",
-		"SleepingTipAdvancedString": "Knica:",
+		"WarningSimpleString": "VROČ",
+		"WarningAdvancedString": "!!VROČA KONICA!!",
+		"SleepingTipAdvancedString": "Konica",
 		"IdleTipString": "Kon:",
-		"IdleSetString": " nst.:",
-		"TipDisconnectedString": "KONICA ODSTRANJ.",
+		"IdleSetString": " temp:",
+		"TipDisconnectedString": "NI KONICE",
 		"SolderingAdvancedPowerPrompt": "Moč: ",
-		"OffString": "Izk",
+		"OffString": "Off",
 		"ResetOKMessage": "Reset OK",
-		"YourGainMessage": "Ojačan.:",
-		"SettingsResetMessage": "Settings were\nreset!",
-		"LockingKeysString": " LOCKED",
-		"UnlockingKeysString": "UNLOCKED",
-		"WarningKeysLockedString": "!LOCKED!"
+		"YourGainMessage": "Ojačenje",
+		"SettingsResetMessage": "Nastavitve OK!",
+		"NoAccelerometerMessage": "Ni pospeševalnik",
+		"NoPowerDeliveryMessage": "Ni USB-PD čipa!",
+		"LockingKeysString": "ZAKLENJ.",
+		"UnlockingKeysString": "ODKLENJ.",
+		"WarningKeysLockedString": "ZAKLENJ."
 	},
 	"characters": {
 		"SettingRightChar": "D",
@@ -34,17 +36,17 @@
 		"SettingAutoChar": "S",
 		"SettingFastChar": "H",
 		"SettingSlowChar": "P",
-		"SettingStartSolderingChar": "T",
-		"SettingStartSleepChar": "S",
-		"SettingStartSleepOffChar": "O",
-		"SettingStartNoneChar": "F",
-		"SettingSensitivityOff": "O",
-		"SettingSensitivityLow": "L",
-		"SettingSensitivityMedium": "M",
-		"SettingSensitivityHigh": "H",
-		"SettingLockDisableChar": "D",
-		"SettingLockBoostChar": "B",
-		"SettingLockFullChar": "F"
+		"SettingStartSolderingChar": "S",
+		"SettingStartSleepChar": "Z",
+		"SettingStartSleepOffChar": "V",
+		"SettingStartNoneChar": "U",
+		"SettingSensitivityOff": "U",
+		"SettingSensitivityLow": "N",
+		"SettingSensitivityMedium": "S",
+		"SettingSensitivityHigh": "V",
+		"SettingLockDisableChar": "O",
+		"SettingLockBoostChar": "L",
+		"SettingLockFullChar": "P"
 	},
 	"menuGroups": {
 		"SolderingMenu": {
@@ -56,7 +58,7 @@
 		},
 		"PowerSavingMenu": {
 			"text2": [
-				"Načini",
+				"Način",
 				"spanja"
 			],
 			"desc": "Nastavitve varčevanja z energijo"
@@ -89,70 +91,70 @@
 				"Temp. med",
 				"spanjem"
 			],
-			"desc": "Temperatura med spanjem <C>"
+			"desc": "Temperatura med spanjem"
 		},
 		"SleepTimeout": {
 			"text2": [
 				"Čas do",
 				"spanja"
 			],
-			"desc": "Čas pred spanjem <minute/sekunde>"
+			"desc": "Čas pred spanjem <S=sekunde | M=minute>"
 		},
 		"ShutdownTimeout": {
 			"text2": [
 				"Čas do",
 				"izklopa"
 			],
-			"desc": "Čas pred izklopom <minute>"
+			"desc": "Čas do izklopa <M=minute>"
 		},
 		"MotionSensitivity": {
 			"text2": [
 				"Občutljivost",
 				"premikanja"
 			],
-			"desc": "Občutljivost premikanja <0.izklopljeno 1.najmanj 9.najbolj občutljivo>"
+			"desc": "0=izklopljeno | 1=najmanjša | ... | 9=največja"
 		},
 		"TemperatureUnit": {
 			"text2": [
 				"Enota za",
 				"temperaturo"
 			],
-			"desc": "Enota za temperaturo <C=celzija F=fahrenheita>"
+			"desc": "Enota za temperaturo <C=celzij | F=fahrenheit>"
 		},
 		"AdvancedIdle": {
 			"text2": [
-				"Več info na",
-				"zaslonu v mir"
+				"Več info. na",
+				"mir. zaslonu"
 			],
-			"desc": "Prikaže več informacij z manjšo pisavo na zaslonu med mirovanjem."
+			"desc": "Prikaži več informacij z manjšo pisavo na mirovalnem zaslonu."
 		},
 		"DisplayRotation": {
 			"text2": [
 				"Orientacija",
 				"zaslona"
 			],
-			"desc": "Orientacija zaslona <S. samodejno L. levo D. desno>"
+			"desc": "S=samodejno | L=levičar | D=desničar"
 		},
 		"BoostTemperature": {
 			"text2": [
-				"Temperat.",
-				"v boost"
+				"Pospešena",
+				"temp."
 			],
-			"desc": "Temperatura v \"boost\" načinu"
+			"desc": "Temperatura v pospešenem načinu"
 		},
 		"AutoStart": {
 			"text2": [
 				"Samodejni",
 				"zagon"
 			],
-			"desc": "Samodejno segrej konico ob vklopu. T=segrej, S=spanje, F=izklop"
+			"desc": "Samodejno gretje konice ob vklopu <U=ugasnjeno | S=spajkanje | Z=spanje | V=spanje na sobni temperaturi>"
 		},
 		"CooldownBlink": {
 			"text2": [
 				"Utripanje med",
 				"hlajenjem"
 			],
-			"desc": "Utripaj temperaturo med hlajenjem, ko je konica še vroča."
+			"desc": "Ko je konica še vroča, utripaj prikaz temperature med hlajenjem."
 		},
 		"TemperatureCalibration": {
 			"text2": [
@@ -173,7 +175,7 @@
 				"Kalibriram",
 				"vhodno napetost?"
 			],
-			"desc": "Kalibracija VIN. Nastavitve z gumbi, dolgi pritisk za izhod."
+			"desc": "Kalibracija VIN <nastavitve z gumbi, dolg pritisk za izhod>"
 		},
 		"AdvancedSoldering": {
 			"text2": [
@@ -187,11 +189,11 @@
 				"Hitrost",
 				"besedila"
 			],
-			"desc": "Hitrost, s katero se prikazuje besedilo"
+			"desc": "Hitrost, s katero se prikazuje besedilo <P=počasi | H=hitro>"
 		},
 		"TipModel": {
 			"text2": [
-				"Model",
+				"Tip",
 				"konice"
 			],
 			"desc": "Izbira tipa konice"
@@ -212,66 +214,66 @@
 		},
 		"QCMaxVoltage": {
 			"text2": [
-				"Moč napajalnega",
-				"vira"
+				"QC",
+				"napetost"
 			],
-			"desc": "Moč v W napajalnega vira"
+			"desc": "Moč napajalnega vira v vatih [W]"
 		},
 		"PowerLimit": {
 			"text2": [
-				"Power",
-				"Limit"
+				"Meja",
+				"moči"
 			],
-			"desc": "Maximum power the iron can use <Watts>"
+			"desc": "Največja dovoljena moč v vatih [W]"
 		},
 		"ReverseButtonTempChange": {
 			"text2": [
-				"Key +-",
-				"reverse?"
+				"Obrni",
+				"tipki + -?"
 			],
-			"desc": "Reverse the tip temperature change buttons plus minus assignment."
+			"desc": "Zamenjaj funkciji gumbov."
 		},
 		"TempChangeShortStep": {
 			"text2": [
-				"Temp change",
-				"short?"
+				"Kratka sprememba",
+				"temperature?"
 			],
-			"desc": "Temperature change steps on short button press!"
+			"desc": "Temperatura se spremeni ob kratkem pritisku na gumb."
 		},
 		"TempChangeLongStep": {
 			"text2": [
-				"Temp change",
-				"long?"
+				"Dolga sprememba",
+				"temperature?"
 			],
-			"desc": "Temperature change steps on long button press!"
+			"desc": "Temperatura se spremeni ob dolgem pritisku na gumb."
 		},
 		"PowerPulsePower": {
 			"text2": [
-				"Power",
-				"Pulse W"
+				"Pulz",
+				"moči"
 			],
-			"desc": "Keep awake pulse power intensity"
+			"desc": "Velikost moči za vzdrževanje budnosti."
 		},
 		"TipGain": {
 			"text2": [
-				"Modify",
-				"tip gain"
+				"Nastavi",
+				"moč kon."
 			],
-			"desc": "Tip gain"
+			"desc": "Nastavi moč konice."
 		},
 		"HallEffSensitivity": {
 			"text2": [
-				"Hall Eff",
-				"Sensitivity"
+				"Občut.",
+				"Hall son"
 			],
-			"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
+			"desc": "Občutljivost Hallove sonde za zaznavanje spanja <U=ugasnjen | N=nizka | S=srednja | V=visoka>"
 		},
 		"LockingMode": {
 			"text2": [
-				"Allow buttons",
-				"locking"
+				"Omogoči",
+				"zaklep gumbov"
 			],
-			"desc": "When soldering, long press on both buttons lock them <D=Disable, B=Boost only, F=Full locking>"
+			"desc": "Za zaklep med spajkanjem drži oba gumba <O=onemogoči | L=le pospešeno | P=polno>"
 		}
 	}
 }

Translations/translation_sr_cyrl.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Your gain:",
 		"SettingsResetMessage": "Settings were\nreset!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_sr_latn.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Your gain:",
 		"SettingsResetMessage": "Settings were\nreset!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_sv.json

@@ -24,6 +24,8 @@
 		"ResetOKMessage": "Reset OK",
 		"YourGainMessage": "Your gain:",
 		"SettingsResetMessage": "Settings were\nreset!",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!",
 		"LockingKeysString": " LOCKED",
 		"UnlockingKeysString": "UNLOCKED",
 		"WarningKeysLockedString": "!LOCKED!"

Translations/translation_tr.json

@@ -23,7 +23,9 @@
 		"OffString": "Kapalı",
 		"ResetOKMessage": "Sıfırlama Tamam",
 		"YourGainMessage": "Kazancınız:",
-		"SettingsResetMessage": "Ayarlar Sıfırlandı"
+		"SettingsResetMessage": "Ayarlar Sıfırlandı",
+		"NoAccelerometerMessage": "No accelerometer\ndetected!",
+		"NoPowerDeliveryMessage": "No USB-PD IC\ndetected!"
 	},
 	"characters": {
 		"SettingRightChar": "R",

Translations/translation_uk.json

@@ -24,9 +24,11 @@
 		"ResetOKMessage": "Скидання OK",
 		"YourGainMessage": "Приріст:",
 		"SettingsResetMessage": "Налаштування скинуті!",
-		"LockingKeysString": " LOCKED",
-		"UnlockingKeysString": "UNLOCKED",
-		"WarningKeysLockedString": "!LOCKED!"
+		"NoAccelerometerMessage": "Акселерометр\nне виявлено!",
+		"NoPowerDeliveryMessage": "USB-PD IC\nне виявлено!",
+		"LockingKeysString": " ЗАБЛОКОВАНО",
+		"UnlockingKeysString": "РОЗБЛОКОВАНО",
+		"WarningKeysLockedString": "!ЗАБЛОКОВАНО!"
 	},
 	"characters": {
 		"SettingRightChar": "П",
@@ -38,13 +40,13 @@
 		"SettingStartSleepChar": "О",
 		"SettingStartSleepOffChar": "К",
 		"SettingStartNoneChar": "В",
-		"SettingSensitivityOff": "O",
-		"SettingSensitivityLow": "L",
-		"SettingSensitivityMedium": "M",
-		"SettingSensitivityHigh": "H",
-		"SettingLockDisableChar": "D",
-		"SettingLockBoostChar": "B",
-		"SettingLockFullChar": "F"
+		"SettingSensitivityOff": "В",
+		"SettingSensitivityLow": "Н",
+		"SettingSensitivityMedium": "С",
+		"SettingSensitivityHigh": "М",
+		"SettingLockDisableChar": "В",
+		"SettingLockBoostChar": "Т",
+		"SettingLockFullChar": "П"
 	},
 	"menuGroups": {
 		"SolderingMenu": {
@@ -261,17 +263,17 @@
 		},
 		"HallEffSensitivity": {
 			"text2": [
-				"Hall Eff",
-				"Sensitivity"
+				"Чутливість",
+				"Ефекту Холла"
 			],
-			"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
+			"desc": "Чутливість датчика ефекту Холла при виявленні сну <В=Вимк,Н=Низький,С=Середній,М=Макс>"
 		},
 		"LockingMode": {
 			"text2": [
-				"Allow buttons",
-				"locking"
+				"Дозволити",
+				"блокування кнопок"
 			],
-			"desc": "When soldering, long press on both buttons lock them <D=Disable, B=Boost only, F=Full locking>"
+			"desc": "Під час пайки тривале натискання обох кнопок заблокує їх <В=Вимк, Т=Тільки турбо, П=Повне>"
 		}
 	}
-}
+}

Translations/translations_def.js

@@ -95,6 +95,16 @@ var def =
 			"maxLen": 16,
 			"default": "Settings were\nreset!"
 		},
+		{
+			"id": "NoAccelerometerMessage",
+			"maxLen": 16,
+			"default": "No accelerometer\ndetected!"
+		},
+		{
+			"id": "NoPowerDeliveryMessage",
+			"maxLen": 16,
+			"default": "No USB-PD IC\ndetected!"
+		},
 		{
 			"id": "LockingKeysString",
 			"maxLen": 8,

ci/buildAll.sh

@@ -5,9 +5,9 @@ set -u
 mkdir -p /build/ci/artefacts
 
 # Build STM code
-cd /build/source/workspace/TS100/
+cd /build/source/source/
 bash ./build.sh || exit 1
 echo "All Firmware built"
 # Copy out all the final resulting files we would like to store for the next op
-cp -r /build/source/workspace/TS100/Hexfile/*.hex  /build/ci/artefacts/
-cp -r /build/source/workspace/TS100/Hexfile/*.bin  /build/ci/artefacts/
+cp -r /build/source/source/Hexfile/*.hex  /build/ci/artefacts/
+cp -r /build/source/source/Hexfile/*.bin  /build/ci/artefacts/

source/.clang-format

@@ -0,0 +1,138 @@
+# Roughly based on LLVM, tweaked a tad for readability on wide screens
+---
+Language:        Cpp
+# BasedOnStyle:  LLVM
+AccessModifierOffset: -2
+AlignAfterOpenBracket: Align
+AlignConsecutiveMacros: true
+AlignConsecutiveAssignments: true
+AlignConsecutiveDeclarations: true
+AlignEscapedNewlines: Left
+AlignOperands:   true
+AlignTrailingComments: true
+AllowAllArgumentsOnNextLine: true
+AllowAllConstructorInitializersOnNextLine: true
+AllowAllParametersOfDeclarationOnNextLine: true
+AllowShortBlocksOnASingleLine: Empty
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: All
+AllowShortLambdasOnASingleLine: All
+AllowShortIfStatementsOnASingleLine: Never
+AllowShortLoopsOnASingleLine: false
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakAfterReturnType: None
+AlwaysBreakBeforeMultilineStrings: false
+AlwaysBreakTemplateDeclarations: MultiLine
+BinPackArguments: true
+BinPackParameters: true
+BraceWrapping:
+  AfterCaseLabel:  false
+  AfterClass:      false
+  AfterControlStatement: false
+  AfterEnum:       false
+  AfterFunction:   false
+  AfterNamespace:  false
+  AfterObjCDeclaration: false
+  AfterStruct:     false
+  AfterUnion:      false
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+ForEachMacros:
+  - foreach
+  - Q_FOREACH
+  - BOOST_FOREACH
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+ReflowComments:  true
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+SortUsingDeclarations: true
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+

source/Core/BSP/BSP.h

@@ -1,10 +1,10 @@
-#include <stdint.h>
-#include <stdbool.h>
 #include "BSP_Flash.h"
 #include "BSP_Power.h"
 #include "BSP_QC.h"
 #include "Defines.h"
 #include "Model_Config.h"
+#include <stdbool.h>
+#include <stdint.h>
 /*
  * BSP.h -- Board Support
  *
@@ -59,16 +59,16 @@ void reboot();
 // If the user has programmed in a bootup logo, draw it to the screen from flash
 // Returns 1 if the logo was printed so that the unit waits for the timeout or button
 uint8_t showBootLogoIfavailable();
-//delay wrapper for delay using the hardware timer (used before RTOS)
-void delay_ms(uint16_t count) ;
-//Used to allow knowledge of if usb_pd is being used
+// delay wrapper for delay using the hardware timer (used before RTOS)
+void delay_ms(uint16_t count);
+// Used to allow knowledge of if usb_pd is being used
 uint8_t usb_pd_detect();
-bool getHallSensorFitted();
+bool    getHallSensorFitted();
 // If the iron has a hall effect sensor in the handle, return an signed count of the reading
 // If the sensor is single polarity (or polarity insensitive) just return 0..32768
 int16_t getRawHallEffect();
 
-//Returns true if power is from dumb "DC" input rather than "smart" QC or PD
+// Returns true if power is from dumb "DC" input rather than "smart" QC or PD
 bool getIsPoweredByDCIN();
 
 #ifdef __cplusplus

source/Core/BSP/BSP_Flash.h

@@ -16,7 +16,7 @@ extern "C" {
  * Should allow reading and writing to the flash
  */
 
-//Erase the flash, then save the buffer. Returns 1 if worked
+// Erase the flash, then save the buffer. Returns 1 if worked
 uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length);
 
 void flash_read_buffer(uint8_t *buffer, const uint16_t length);

source/Core/BSP/BSP_PD.h

@@ -12,5 +12,5 @@
  * An array of all of the desired voltages & minimum currents in preferred order
  */
 extern const uint16_t USB_PD_Desired_Levels[];
-extern const uint8_t USB_PD_Desired_Levels_Len;
+extern const uint8_t  USB_PD_Desired_Levels_Len;
 #endif /* USER_BSP_PD_H_ */

source/Core/BSP/BSP_Power.h

@@ -12,7 +12,6 @@
 extern "C" {
 #endif
 
-
 // Called periodically in the movement handling thread
 // Can be used to check any details for the power system
 void power_check();

source/Core/BSP/Defines.h

@@ -0,0 +1,18 @@
+/*
+ * Defines.h
+ *
+ *  Created on: 29 May 2020
+ *      Author: Ralim
+ */
+
+#ifndef BSP_DEFINES_H_
+#define BSP_DEFINES_H_
+
+enum Orientation { ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3 };
+
+// It is assumed that all hardware implements an 8Hz update period at this time
+#define PID_TIM_HZ   (8)
+#define TICKS_SECOND configTICK_RATE_HZ
+#define TICKS_MIN    (60 * TICKS_SECOND)
+#define TICKS_100MS  (TICKS_SECOND / 10)
+#endif /* BSP_DEFINES_H_ */

source/Core/BSP/Miniware/BSP.cpp

@@ -0,0 +1,340 @@
+// BSP mapping functions
+
+#include "BSP.h"
+#include "I2C_Wrapper.hpp"
+#include "Model_Config.h"
+#include "Pins.h"
+#include "Setup.h"
+#include "history.hpp"
+#include "main.hpp"
+#include <IRQ.h>
+volatile uint16_t PWMSafetyTimer = 0;
+volatile uint8_t  pendingPWM     = 0;
+
+const uint16_t       powerPWM         = 255;
+static const uint8_t holdoffTicks     = 14; // delay of 8 ms
+static const uint8_t tempMeasureTicks = 14;
+
+uint16_t totalPWM; // htim2.Init.Period, the full PWM cycle
+
+static bool fastPWM;
+
+// 2 second filter (ADC is PID_TIM_HZ Hz)
+history<uint16_t, PID_TIM_HZ> rawTempFilter = {{0}, 0, 0};
+void                          resetWatchdog() { HAL_IWDG_Refresh(&hiwdg); }
+#ifdef TEMP_NTC
+// Lookup table for the NTC
+// Stored as ADCReading,Temp in degC
+static const uint16_t NTCHandleLookup[] = {
+    // ADC Reading , Temp in C
+    29189, 0,  //
+    29014, 1,  //
+    28832, 2,  //
+    28644, 3,  //
+    28450, 4,  //
+    28249, 5,  //
+    28042, 6,  //
+    27828, 7,  //
+    27607, 8,  //
+    27380, 9,  //
+    27146, 10, //
+    26906, 11, //
+    26660, 12, //
+    26407, 13, //
+    26147, 14, //
+    25882, 15, //
+    25610, 16, //
+    25332, 17, //
+    25049, 18, //
+    24759, 19, //
+    24465, 20, //
+    24164, 21, //
+    23859, 22, //
+    23549, 23, //
+    23234, 24, //
+    22915, 25, //
+    22591, 26, //
+    22264, 27, //
+    21933, 28, //
+    21599, 29, //
+    21261, 30, //
+    20921, 31, //
+    20579, 32, //
+    20234, 33, //
+    19888, 34, //
+    19541, 35, //
+    19192, 36, //
+    18843, 37, //
+    18493, 38, //
+    18143, 39, //
+    17793, 40, //
+    17444, 41, //
+    17096, 42, //
+    16750, 43, //
+    16404, 44, //
+    16061, 45, //
+               //		15719, 46, //
+               //		15380, 47, //
+               //		15044, 48, //
+               //		14710, 49, //
+               //		14380, 50, //
+               //		14053, 51, //
+               //		13729, 52, //
+               //		13410, 53, //
+               //		13094, 54, //
+               //		12782, 55, //
+               //		12475, 56, //
+               //		12172, 57, //
+               //		11874, 58, //
+               //		11580, 59, //
+               //		11292, 60, //
+};
+#endif
+
+uint16_t getHandleTemperature() {
+#ifdef TEMP_NTC
+  // TS80P uses 100k NTC resistors instead
+  // NTCG104EF104FT1X from TDK
+  // For now not doing interpolation
+  int32_t result = getADC(0);
+  for (uint32_t i = 0; i < (sizeof(NTCHandleLookup) / (2 * sizeof(uint16_t))); i++) {
+    if (result > NTCHandleLookup[(i * 2) + 0]) {
+      return NTCHandleLookup[(i * 2) + 1] * 10;
+    }
+  }
+  return 45 * 10;
+#endif
+#ifdef TEMP_TMP36
+  // We return the current handle temperature in X10 C
+  // TMP36 in handle, 0.5V offset and then 10mV per deg C (0.75V @ 25C for
+  // example) STM32 = 4096 count @ 3.3V input -> But We oversample by 32/(2^2) =
+  // 8 times oversampling Therefore 32768 is the 3.3V input, so 0.1007080078125
+  // mV per count So we need to subtract an offset of 0.5V to center on 0C
+  // (4964.8 counts)
+  //
+  int32_t result = getADC(0);
+  result -= 4965; // remove 0.5V offset
+  // 10mV per C
+  // 99.29 counts per Deg C above 0C. Tends to read a tad over across all of my sample units
+  result *= 100;
+  result /= 994;
+  return result;
+#endif
+}
+
+uint16_t getTipInstantTemperature() {
+  uint16_t sum = 0; // 12 bit readings * 8 -> 15 bits
+  uint16_t readings[8];
+  // Looking to reject the highest outlier readings.
+  // As on some hardware these samples can run into the op-amp recovery time
+  // Once this time is up the signal stabilises quickly, so no need to reject minimums
+  readings[0] = hadc1.Instance->JDR1;
+  readings[1] = hadc1.Instance->JDR2;
+  readings[2] = hadc1.Instance->JDR3;
+  readings[3] = hadc1.Instance->JDR4;
+  readings[4] = hadc2.Instance->JDR1;
+  readings[5] = hadc2.Instance->JDR2;
+  readings[6] = hadc2.Instance->JDR3;
+  readings[7] = hadc2.Instance->JDR4;
+
+  for (int i = 0; i < 8; i++) {
+    sum += readings[i];
+  }
+  return sum; // 8x over sample
+}
+
+uint16_t getTipRawTemp(uint8_t refresh) {
+  if (refresh) {
+    uint16_t lastSample = getTipInstantTemperature();
+    rawTempFilter.update(lastSample);
+    return lastSample;
+  } else {
+    return rawTempFilter.average();
+  }
+}
+
+uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) {
+// ADC maximum is 32767 == 3.3V at input == 28.05V at VIN
+// Therefore we can divide down from there
+// Multiplying ADC max by 4 for additional calibration options,
+// ideal term is 467
+#ifdef MODEL_TS100
+#define BATTFILTERDEPTH 32
+#else
+#define BATTFILTERDEPTH 8
+
+#endif
+  static uint8_t  preFillneeded = 10;
+  static uint32_t samples[BATTFILTERDEPTH];
+  static uint8_t  index = 0;
+  if (preFillneeded) {
+    for (uint8_t i = 0; i < BATTFILTERDEPTH; i++)
+      samples[i] = getADC(1);
+    preFillneeded--;
+  }
+  if (sample) {
+    samples[index] = getADC(1);
+    index          = (index + 1) % BATTFILTERDEPTH;
+  }
+  uint32_t sum = 0;
+
+  for (uint8_t i = 0; i < BATTFILTERDEPTH; i++)
+    sum += samples[i];
+
+  sum /= BATTFILTERDEPTH;
+  if (divisor == 0) {
+    divisor = 1;
+  }
+  return sum * 4 / divisor;
+}
+
+void setTipPWM(uint8_t pulse) {
+  PWMSafetyTimer = 10; // This is decremented in the handler for PWM so that the tip pwm is
+                       // disabled if the PID task is not scheduled often enough.
+
+  pendingPWM = pulse;
+}
+
+static void switchToFastPWM(void) {
+  fastPWM             = true;
+  totalPWM            = powerPWM + tempMeasureTicks * 2 + holdoffTicks;
+  htim2.Instance->ARR = totalPWM;
+  // ~3.5 Hz rate
+  htim2.Instance->CCR1 = powerPWM + holdoffTicks * 2;
+  // 2 MHz timer clock/2000 = 1 kHz tick rate
+  htim2.Instance->PSC = 2000;
+}
+
+static void switchToSlowPWM(void) {
+  fastPWM             = false;
+  totalPWM            = powerPWM + tempMeasureTicks + holdoffTicks;
+  htim2.Instance->ARR = totalPWM;
+  // ~1.84 Hz rate
+  htim2.Instance->CCR1 = powerPWM + holdoffTicks;
+  // 2 MHz timer clock/4000 = 500 Hz tick rate
+  htim2.Instance->PSC = 4000;
+}
+
+bool tryBetterPWM(uint8_t pwm) {
+  if (fastPWM && pwm == powerPWM) {
+    // maximum power for fast PWM reached, need to go slower to get more
+    switchToSlowPWM();
+    return true;
+  } else if (!fastPWM && pwm < 230) {
+    // 254 in fast PWM mode gives the same power as 239 in slow
+    // allow for some reasonable hysteresis by switching only when it goes
+    // below 230 (equivalent to 245 in fast mode)
+    switchToFastPWM();
+    return true;
+  }
+  return false;
+}
+
+// These are called by the HAL after the corresponding events from the system
+// timers.
+
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
+  // Period has elapsed
+  if (htim->Instance == TIM2) {
+    // we want to turn on the output again
+    PWMSafetyTimer--;
+    // We decrement this safety value so that lockups in the
+    // scheduler will not cause the PWM to become locked in an
+    // active driving state.
+    // While we could assume this could never happen, its a small price for
+    // increased safety
+    htim2.Instance->CCR4 = pendingPWM;
+    if (htim2.Instance->CCR4 && PWMSafetyTimer) {
+      HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1);
+    } else {
+      HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1);
+    }
+  } else if (htim->Instance == TIM1) {
+    // STM uses this for internal functions as a counter for timeouts
+    HAL_IncTick();
+  }
+}
+
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) {
+  // This was a when the PWM for the output has timed out
+  if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) {
+    HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1);
+  }
+}
+void unstick_I2C() {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  int              timeout     = 100;
+  int              timeout_cnt = 0;
+
+  // 1. Clear PE bit.
+  hi2c1.Instance->CR1 &= ~(0x0001);
+  /**I2C1 GPIO Configuration
+   PB6     ------> I2C1_SCL
+   PB7     ------> I2C1_SDA
+   */
+  //  2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_OD;
+  GPIO_InitStruct.Pull  = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+
+  GPIO_InitStruct.Pin = SCL_Pin;
+  HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct);
+  HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
+
+  GPIO_InitStruct.Pin = SDA_Pin;
+  HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct);
+  HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET);
+
+  while (GPIO_PIN_SET != HAL_GPIO_ReadPin(SDA_GPIO_Port, SDA_Pin)) {
+    // Move clock to release I2C
+    HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_RESET);
+    asm("nop");
+    asm("nop");
+    asm("nop");
+    asm("nop");
+    HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
+
+    timeout_cnt++;
+    if (timeout_cnt > timeout)
+      return;
+  }
+
+  // 12. Configure the SCL and SDA I/Os as Alternate function Open-Drain.
+  GPIO_InitStruct.Mode  = GPIO_MODE_AF_OD;
+  GPIO_InitStruct.Pull  = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+
+  GPIO_InitStruct.Pin = SCL_Pin;
+  HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = SDA_Pin;
+  HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct);
+
+  HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
+  HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET);
+
+  // 13. Set SWRST bit in I2Cx_CR1 register.
+  hi2c1.Instance->CR1 |= 0x8000;
+
+  asm("nop");
+
+  // 14. Clear SWRST bit in I2Cx_CR1 register.
+  hi2c1.Instance->CR1 &= ~0x8000;
+
+  asm("nop");
+
+  // 15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register
+  hi2c1.Instance->CR1 |= 0x0001;
+
+  // Call initialization function.
+  HAL_I2C_Init(&hi2c1);
+}
+
+uint8_t getButtonA() { return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ? 1 : 0; }
+uint8_t getButtonB() { return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ? 1 : 0; }
+
+void BSPInit(void) { switchToFastPWM(); }
+
+void reboot() { NVIC_SystemReset(); }
+
+void delay_ms(uint16_t count) { HAL_Delay(count); }

source/Core/BSP/Miniware/BSP_PD.c

@@ -12,11 +12,11 @@
  * An array of all of the desired voltages & minimum currents in preferred order
  */
 const uint16_t USB_PD_Desired_Levels[] = {
-//mV desired input, mA minimum required current
-		12000, 2400, //12V @ 2.4A
-		9000, 2000, //9V @ 2A
-		5000, 100, //5V @ whatever
+    // mV desired input, mA minimum required current
+    12000, 2400, // 12V @ 2.4A
+    9000,  2000, // 9V @ 2A
+    5000,  100,  // 5V @ whatever
 
-		};
+};
 const uint8_t USB_PD_Desired_Levels_Len = 3;
 #endif

source/Core/BSP/Miniware/FreeRTOSConfig.h

@@ -92,27 +92,27 @@
 extern uint32_t SystemCoreClock;
 #endif
 
-#define configUSE_PREEMPTION                     1
-#define configSUPPORT_STATIC_ALLOCATION          1
-#define configSUPPORT_DYNAMIC_ALLOCATION         0
-#define configUSE_IDLE_HOOK                      1
-#define configUSE_TICK_HOOK                      0
-#define configCPU_CLOCK_HZ                       ( SystemCoreClock )
-#define configTICK_RATE_HZ                       ((TickType_t)1000)
-#define configMAX_PRIORITIES                     ( 6 )
-#define configMINIMAL_STACK_SIZE                 ((uint16_t)256)
-#define configTOTAL_HEAP_SIZE                    ((size_t)1024*14) /*Currently use about 9000*/
-#define configMAX_TASK_NAME_LEN                  ( 32 )
-#define configUSE_16_BIT_TICKS                   0
-#define configUSE_MUTEXES                        1
-#define configQUEUE_REGISTRY_SIZE                8
-#define configUSE_TIMERS                         0
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION  1
-#define configCHECK_FOR_STACK_OVERFLOW			 2 /*Bump this to 2 during development and bug hunting*/
+#define configUSE_PREEMPTION                    1
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+#define configUSE_IDLE_HOOK                     1
+#define configUSE_TICK_HOOK                     0
+#define configCPU_CLOCK_HZ                      (SystemCoreClock)
+#define configTICK_RATE_HZ                      ((TickType_t)1000)
+#define configMAX_PRIORITIES                    (6)
+#define configMINIMAL_STACK_SIZE                ((uint16_t)256)
+#define configTOTAL_HEAP_SIZE                   ((size_t)1024 * 14) /*Currently use about 9000*/
+#define configMAX_TASK_NAME_LEN                 (32)
+#define configUSE_16_BIT_TICKS                  0
+#define configUSE_MUTEXES                       1
+#define configQUEUE_REGISTRY_SIZE               8
+#define configUSE_TIMERS                        0
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#define configCHECK_FOR_STACK_OVERFLOW          2 /*Bump this to 2 during development and bug hunting*/
 
 /* Co-routine definitions. */
-#define configUSE_CO_ROUTINES                    0
-#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )
+#define configUSE_CO_ROUTINES           0
+#define configMAX_CO_ROUTINE_PRIORITIES (2)
 
 /* Set the following definitions to 1 to include the API function, or zero
  to exclude the API function. */
@@ -128,15 +128,15 @@ extern uint32_t SystemCoreClock;
 
 /* Cortex-M specific definitions. */
 #ifdef __NVIC_PRIO_BITS
- /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
- #define configPRIO_BITS         __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
 #else
-#define configPRIO_BITS         4
+#define configPRIO_BITS 4
 #endif
 
 /* The lowest interrupt priority that can be used in a call to a "set priority"
  function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   15
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
 
 /* The highest interrupt priority that can be used by any interrupt service
  routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
@@ -146,15 +146,20 @@ extern uint32_t SystemCoreClock;
 
 /* Interrupt priorities used by the kernel port layer itself.  These are generic
  to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
 /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
 
 /* Normal assert() semantics without relying on the provision of an assert.h
  header file. */
 /* USER CODE BEGIN 1 */
-#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} 
+#define configASSERT(x)       \
+  if ((x) == 0) {             \
+    taskDISABLE_INTERRUPTS(); \
+    for (;;)                  \
+      ;                       \
+  }
 /* USER CODE END 1 */
 
 /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
@@ -163,9 +168,9 @@ extern uint32_t SystemCoreClock;
 #define xPortPendSVHandler PendSV_Handler
 
 #if configUSE_TIMERS
-#define configTIMER_TASK_PRIORITY 2
-#define configTIMER_QUEUE_LENGTH 8
-#define configTIMER_TASK_STACK_DEPTH (512/4)
+#define configTIMER_TASK_PRIORITY    2
+#define configTIMER_QUEUE_LENGTH     8
+#define configTIMER_TASK_STACK_DEPTH (512 / 4)
 #endif
 
 #endif /* FREERTOS_CONFIG_H */

source/Core/BSP/Miniware/I2C_Wrapper.cpp

@@ -0,0 +1,91 @@
+/*
+ * FRToSI2C.cpp
+ *
+ *  Created on: 14Apr.,2018
+ *      Author: Ralim
+ */
+#include "BSP.h"
+#include "Setup.h"
+#include <I2C_Wrapper.hpp>
+SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr;
+StaticSemaphore_t FRToSI2C::xSemaphoreBuffer;
+
+void FRToSI2C::CpltCallback() {
+  hi2c1.State = HAL_I2C_STATE_READY; // Force state reset (even if tx error)
+  if (I2CSemaphore) {
+    xSemaphoreGiveFromISR(I2CSemaphore, NULL);
+  }
+}
+
+bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size) {
+
+  if (!lock())
+    return false;
+  if (HAL_I2C_Mem_Read(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT, pData, Size, 500) != HAL_OK) {
+
+    I2C_Unstick();
+    unlock();
+    return false;
+  }
+
+  unlock();
+  return true;
+}
+bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }
+
+uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) {
+  uint8_t tx_data[1];
+  Mem_Read(add, reg, tx_data, 1);
+  return tx_data[0];
+}
+bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size) {
+
+  if (!lock())
+    return false;
+  if (HAL_I2C_Mem_Write(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT, pData, Size, 500) != HAL_OK) {
+
+    I2C_Unstick();
+    unlock();
+    return false;
+  }
+
+  unlock();
+  return true;
+}
+
+bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
+  if (!lock())
+    return false;
+  if (HAL_I2C_Master_Transmit_DMA(&hi2c1, DevAddress, pData, Size) != HAL_OK) {
+    I2C_Unstick();
+    unlock();
+    return false;
+  }
+  return true;
+}
+
+bool FRToSI2C::probe(uint16_t DevAddress) {
+  if (!lock())
+    return false;
+  uint8_t buffer[1];
+  bool    worked = HAL_I2C_Mem_Read(&hi2c1, DevAddress, 0x0F, I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000) == HAL_OK;
+  unlock();
+  return worked;
+}
+
+void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
+
+void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); }
+
+bool FRToSI2C::lock() { return xSemaphoreTake(I2CSemaphore, (TickType_t)50) == pdTRUE; }
+
+bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) {
+  for (int index = 0; index < registersLength; index++) {
+    if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) {
+      return false;
+    }
+    if (registers[index].pause_ms)
+      delay_ms(registers[index].pause_ms);
+  }
+  return true;
+}

source/Core/BSP/Miniware/IRQ.cpp

@@ -13,37 +13,22 @@
  * runs again
  */
 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) {
-	BaseType_t xHigherPriorityTaskWoken = pdFALSE;
-	if (hadc == &hadc1) {
-		if (pidTaskNotification) {
-			vTaskNotifyGiveFromISR(pidTaskNotification,
-					&xHigherPriorityTaskWoken);
-			portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
-		}
-	}
-}
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
-	FRToSI2C::CpltCallback();
-}
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
-	FRToSI2C::CpltCallback();
-}
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
-	FRToSI2C::CpltCallback();
-}
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c __unused) {
-
-	FRToSI2C::CpltCallback();
-}
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
-
-	FRToSI2C::CpltCallback();
-}
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
-	FRToSI2C::CpltCallback();
+  BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+  if (hadc == &hadc1) {
+    if (pidTaskNotification) {
+      vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken);
+      portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+    }
+  }
 }
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
 
 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
-	(void) GPIO_Pin;
-	InterruptHandler::irqCallback();
+  (void)GPIO_Pin;
+  InterruptHandler::irqCallback();
 }

source/Core/BSP/Miniware/IRQ.h

@@ -9,10 +9,10 @@
 #define BSP_MINIWARE_IRQ_H_
 
 #include "BSP.h"
-#include "stm32f1xx_hal.h"
 #include "I2C_Wrapper.hpp"
 #include "Setup.h"
 #include "main.hpp"
+#include "stm32f1xx_hal.h"
 
 #ifdef __cplusplus
 extern "C" {

source/Core/BSP/Miniware/Model_Config.h

@@ -11,9 +11,9 @@
  * Lookup for mapping features <-> Models
  */
 
-#if defined(MODEL_TS100) + defined(MODEL_TS80)+defined(MODEL_TS80P) > 1
+#if defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) > 1
 #error "Multiple models defined!"
-#elif defined(MODEL_TS100) + defined(MODEL_TS80)+ defined(MODEL_TS80P) == 0
+#elif defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) == 0
 #error "No model defined!"
 #endif
 
@@ -29,18 +29,19 @@
 #define ACCEL_LIS
 #define POW_QC
 #define TEMP_TMP36
-#define ACCEL_ORI_FLIP
+#define LIS_ORI_FLIP
 #define OLED_FLIP
 #define BATTFILTERDEPTH 8
 #endif
 
 #ifdef MODEL_TS80P
 #define ACCEL_LIS
+#define ACCEL_MSA
 #define POW_PD
 #define POW_QC
 #define TEMP_NTC
 #define I2C_SOFT
-#define ACCEL_ORI_FLIP
+#define LIS_ORI_FLIP
 #define OLED_FLIP
 #define BATTFILTERDEPTH 8
 #endif

source/Core/BSP/Miniware/Pins.h

@@ -0,0 +1,126 @@
+/*
+ * Pins.h
+ *
+ *  Created on: 29 May 2020
+ *      Author: Ralim
+ */
+
+#ifndef BSP_MINIWARE_PINS_H_
+#define BSP_MINIWARE_PINS_H_
+#include "Model_Config.h"
+
+#ifdef MODEL_TS100
+
+#define KEY_B_Pin                 GPIO_PIN_6
+#define KEY_B_GPIO_Port           GPIOA
+#define TMP36_INPUT_Pin           GPIO_PIN_7
+#define TMP36_INPUT_GPIO_Port     GPIOA
+#define TMP36_ADC1_CHANNEL        ADC_CHANNEL_7
+#define TMP36_ADC2_CHANNEL        ADC_CHANNEL_7
+#define TIP_TEMP_Pin              GPIO_PIN_0
+#define TIP_TEMP_GPIO_Port        GPIOB
+#define TIP_TEMP_ADC1_CHANNEL     ADC_CHANNEL_8
+#define TIP_TEMP_ADC2_CHANNEL     ADC_CHANNEL_8
+#define VIN_Pin                   GPIO_PIN_1
+#define VIN_GPIO_Port             GPIOB
+#define VIN_ADC1_CHANNEL          ADC_CHANNEL_9
+#define VIN_ADC2_CHANNEL          ADC_CHANNEL_9
+#define OLED_RESET_Pin            GPIO_PIN_8
+#define OLED_RESET_GPIO_Port      GPIOA
+#define KEY_A_Pin                 GPIO_PIN_9
+#define KEY_A_GPIO_Port           GPIOA
+#define INT_Orientation_Pin       GPIO_PIN_3
+#define INT_Orientation_GPIO_Port GPIOB
+#define PWM_Out_Pin               GPIO_PIN_4
+#define PWM_Out_GPIO_Port         GPIOB
+#define PWM_Out_CHANNEL           TIM_CHANNEL_1
+#define PWM_Out_CCR
+#define INT_Movement_Pin       GPIO_PIN_5
+#define INT_Movement_GPIO_Port GPIOB
+#define SCL_Pin                GPIO_PIN_6
+#define SCL_GPIO_Port          GPIOB
+#define SDA_Pin                GPIO_PIN_7
+#define SDA_GPIO_Port          GPIOB
+#endif
+#ifdef MODEL_TS80
+// TS80 pin map
+#define KEY_B_Pin             GPIO_PIN_0
+#define KEY_B_GPIO_Port       GPIOB
+#define TMP36_INPUT_Pin       GPIO_PIN_4
+#define TMP36_INPUT_GPIO_Port GPIOA
+#define TMP36_ADC1_CHANNEL    ADC_CHANNEL_4
+#define TMP36_ADC2_CHANNEL    ADC_CHANNEL_4
+#define TIP_TEMP_Pin          GPIO_PIN_3
+#define TIP_TEMP_GPIO_Port    GPIOA
+#define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_3
+#define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_3
+
+#define VIN_Pin                   GPIO_PIN_2
+#define VIN_GPIO_Port             GPIOA
+#define VIN_ADC1_CHANNEL          ADC_CHANNEL_2
+#define VIN_ADC2_CHANNEL          ADC_CHANNEL_2
+#define OLED_RESET_Pin            GPIO_PIN_15
+#define OLED_RESET_GPIO_Port      GPIOA
+#define KEY_A_Pin                 GPIO_PIN_1
+#define KEY_A_GPIO_Port           GPIOB
+#define INT_Orientation_Pin       GPIO_PIN_4
+#define INT_Orientation_GPIO_Port GPIOB
+#define PWM_Out_Pin               GPIO_PIN_6
+#define PWM_Out_GPIO_Port         GPIOA
+#define PWM_Out_CHANNEL           TIM_CHANNEL_1
+#define INT_Movement_Pin          GPIO_PIN_5
+#define INT_Movement_GPIO_Port    GPIOB
+#define SCL_Pin                   GPIO_PIN_6
+#define SCL_GPIO_Port             GPIOB
+#define SDA_Pin                   GPIO_PIN_7
+#define SDA_GPIO_Port             GPIOB
+#define SCL2_Pin                  GPIO_PIN_5
+#define SCL2_GPIO_Port            GPIOA
+#define SDA2_Pin                  GPIO_PIN_1
+#define SDA2_GPIO_Port            GPIOA
+#define INT_PD_Pin                GPIO_PIN_9
+#define INT_PD_GPIO_Port          GPIOA
+
+#endif
+#ifdef MODEL_TS80P
+// TS80P pin map
+#define KEY_B_Pin             GPIO_PIN_0
+#define KEY_B_GPIO_Port       GPIOB
+#define TMP36_INPUT_Pin       GPIO_PIN_4
+#define TMP36_INPUT_GPIO_Port GPIOA
+#define TMP36_ADC1_CHANNEL    ADC_CHANNEL_4
+#define TMP36_ADC2_CHANNEL    ADC_CHANNEL_4
+#define TIP_TEMP_Pin          GPIO_PIN_3
+#define TIP_TEMP_GPIO_Port    GPIOA
+#define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_3
+#define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_3
+
+#define VIN_Pin                   GPIO_PIN_2
+#define VIN_GPIO_Port             GPIOA
+#define VIN_ADC1_CHANNEL          ADC_CHANNEL_2
+#define VIN_ADC2_CHANNEL          ADC_CHANNEL_2
+#define OLED_RESET_Pin            GPIO_PIN_15
+#define OLED_RESET_GPIO_Port      GPIOA
+#define KEY_A_Pin                 GPIO_PIN_1
+#define KEY_A_GPIO_Port           GPIOB
+#define INT_Orientation_Pin       GPIO_PIN_4
+#define INT_Orientation_GPIO_Port GPIOB
+#define PWM_Out_Pin               GPIO_PIN_6
+#define PWM_Out_GPIO_Port         GPIOA
+#define PWM_Out_CHANNEL           TIM_CHANNEL_1
+#define INT_Movement_Pin          GPIO_PIN_5
+#define INT_Movement_GPIO_Port    GPIOB
+#define SCL_Pin                   GPIO_PIN_6
+#define SCL_GPIO_Port             GPIOB
+#define SDA_Pin                   GPIO_PIN_7
+#define SDA_GPIO_Port             GPIOB
+#define SCL2_Pin                  GPIO_PIN_5
+#define SCL2_GPIO_Port            GPIOA
+#define SDA2_Pin                  GPIO_PIN_1
+#define SDA2_GPIO_Port            GPIOA
+#define INT_PD_Pin                GPIO_PIN_9
+#define INT_PD_GPIO_Port          GPIOA
+
+#endif
+
+#endif /* BSP_MINIWARE_PINS_H_ */

source/Core/BSP/Miniware/Power.cpp

@@ -1,50 +1,48 @@
 #include "BSP.h"
 #include "BSP_Power.h"
+#include "Model_Config.h"
+#include "Pins.h"
 #include "QC3.h"
 #include "Settings.h"
-#include "Pins.h"
 #include "fusbpd.h"
-#include "Model_Config.h"
-#include "policy_engine.h"
 #include "int_n.h"
+#include "policy_engine.h"
 bool FUSB302_present = false;
 
 void power_check() {
 #ifdef POW_PD
-	if (FUSB302_present) {
-		//Cant start QC until either PD works or fails
-		if (PolicyEngine::setupCompleteOrTimedOut() == false) {
-			return;
-		}
-		if (PolicyEngine::pdHasNegotiated()) {
-			return;
-		}
-	}
+  if (FUSB302_present) {
+    // Cant start QC until either PD works or fails
+    if (PolicyEngine::setupCompleteOrTimedOut() == false) {
+      return;
+    }
+    if (PolicyEngine::pdHasNegotiated()) {
+      return;
+    }
+  }
 #endif
 #ifdef POW_QC
-	QC_resync();
+  QC_resync();
 #endif
 }
 uint8_t usb_pd_detect() {
 #ifdef POW_PD
-	FUSB302_present = fusb302_detect();
-
-	return FUSB302_present;
+  FUSB302_present = fusb302_detect();
+  return FUSB302_present;
 #endif
-	return false;
+  return false;
 }
 
 bool getIsPoweredByDCIN() {
 #ifdef MODEL_TS80
-	return false;
+  return false;
 #endif
 
 #ifdef MODEL_TS80P
-	return false;
+  return false;
 #endif
 
 #ifdef MODEL_TS100
-	return true;
+  return true;
 #endif
 }
-

source/Core/BSP/Miniware/QC_GPIO.cpp

@@ -0,0 +1,76 @@
+/*
+ * QC.c
+ *
+ *  Created on: 29 May 2020
+ *      Author: Ralim
+ */
+#include "BSP.h"
+#include "Model_Config.h"
+#include "Pins.h"
+#include "QC3.h"
+#include "Settings.h"
+#include "stm32f1xx_hal.h"
+#ifdef POW_QC
+void QC_DPlusZero_Six() {
+  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_RESET); // pull down D+
+}
+void QC_DNegZero_Six() {
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET);
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET);
+}
+void QC_DPlusThree_Three() {
+  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_SET); // pull up D+
+}
+void QC_DNegThree_Three() {
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET);
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_SET);
+}
+void QC_DM_PullDown() {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Mode  = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull  = GPIO_PULLDOWN;
+  GPIO_InitStruct.Pin   = GPIO_PIN_11;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+void QC_DM_No_PullDown() {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Mode  = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull  = GPIO_NOPULL;
+  GPIO_InitStruct.Pin   = GPIO_PIN_11;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+void QC_Init_GPIO() {
+  // Setup any GPIO into the right states for QC
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Pin   = GPIO_PIN_3;
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Pin  = GPIO_PIN_8 | GPIO_PIN_10;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+  // Turn off output mode on pins that we can
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Pin  = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_13;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+void QC_Post_Probe_En() {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin   = GPIO_PIN_8 | GPIO_PIN_10;
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+
+uint8_t QC_DM_PulledDown() { return HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11) == GPIO_PIN_RESET ? 1 : 0; }
+#endif
+void QC_resync() {
+#ifdef POW_QC
+  seekQC((systemSettings.QCIdealVoltage) ? 120 : 90,
+         systemSettings.voltageDiv); // Run the QC seek again if we have drifted too much
+#endif
+}

source/Core/BSP/Miniware/Setup.c

@@ -0,0 +1,469 @@
+/*
+ * Setup.c
+ *
+ *  Created on: 29Aug.,2017
+ *      Author: Ben V. Brown
+ */
+#include "Setup.h"
+#include "Pins.h"
+ADC_HandleTypeDef hadc1;
+ADC_HandleTypeDef hadc2;
+DMA_HandleTypeDef hdma_adc1;
+
+I2C_HandleTypeDef hi2c1;
+DMA_HandleTypeDef hdma_i2c1_rx;
+DMA_HandleTypeDef hdma_i2c1_tx;
+
+IWDG_HandleTypeDef hiwdg;
+TIM_HandleTypeDef  htim2;
+TIM_HandleTypeDef  htim3;
+#define ADC_CHANNELS 2
+#define ADC_SAMPLES  16
+uint32_t ADCReadings[ADC_SAMPLES * ADC_CHANNELS]; // room for 32 lots of the pair of readings
+
+// Functions
+static void SystemClock_Config(void);
+static void MX_ADC1_Init(void);
+static void MX_I2C1_Init(void);
+static void MX_IWDG_Init(void);
+static void MX_TIM3_Init(void);
+static void MX_TIM2_Init(void);
+static void MX_DMA_Init(void);
+static void MX_GPIO_Init(void);
+static void MX_ADC2_Init(void);
+void        Setup_HAL() {
+  SystemClock_Config();
+
+#ifndef SWD_ENABLE
+  __HAL_AFIO_REMAP_SWJ_DISABLE();
+#else
+  __HAL_AFIO_REMAP_SWJ_NOJTAG();
+#endif
+
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_I2C1_Init();
+  MX_ADC1_Init();
+  MX_ADC2_Init();
+  MX_TIM3_Init();
+  MX_TIM2_Init();
+  MX_IWDG_Init();
+  HAL_ADC_Start(&hadc2);
+  HAL_ADCEx_MultiModeStart_DMA(&hadc1, ADCReadings, (ADC_SAMPLES * ADC_CHANNELS)); // start DMA of normal readings
+  HAL_ADCEx_InjectedStart(&hadc1);                                                 // enable injected readings
+  HAL_ADCEx_InjectedStart(&hadc2);                                                 // enable injected readings
+}
+
+// channel 0 -> temperature sensor, 1-> VIN
+uint16_t getADC(uint8_t channel) {
+  uint32_t sum = 0;
+  for (uint8_t i = 0; i < ADC_SAMPLES; i++) {
+    uint16_t adc1Sample = ADCReadings[channel + (i * ADC_CHANNELS)];
+    uint16_t adc2Sample = ADCReadings[channel + (i * ADC_CHANNELS)] >> 16;
+
+    sum += (adc1Sample + adc2Sample);
+  }
+  return sum >> 2;
+}
+
+/** System Clock Configuration
+ */
+void SystemClock_Config(void) {
+  RCC_OscInitTypeDef       RCC_OscInitStruct;
+  RCC_ClkInitTypeDef       RCC_ClkInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInit;
+
+  /**Initializes the CPU, AHB and APB busses clocks
+   */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI;
+  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = 16;
+  RCC_OscInitStruct.LSIState            = RCC_LSI_ON;
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64MHz
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /**Initializes the CPU, AHB and APB busses clocks
+   */
+  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV16; // TIM
+                                                     // 2,3,4,5,6,7,12,13,14
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;  // 64 mhz to some peripherals and adc
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+  PeriphClkInit.AdcClockSelection    = RCC_ADCPCLK2_DIV6; // 6 or 8 are the only non overclocked options
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+  /**Configure the Systick interrupt time
+   */
+  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
+
+  /**Configure the Systick
+   */
+  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+
+  /* SysTick_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
+}
+
+/* ADC1 init function */
+static void MX_ADC1_Init(void) {
+  ADC_MultiModeTypeDef multimode;
+
+  ADC_ChannelConfTypeDef   sConfig;
+  ADC_InjectionConfTypeDef sConfigInjected;
+  /**Common config
+   */
+  hadc1.Instance                   = ADC1;
+  hadc1.Init.ScanConvMode          = ADC_SCAN_ENABLE;
+  hadc1.Init.ContinuousConvMode    = ENABLE;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
+  hadc1.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.NbrOfConversion       = ADC_CHANNELS;
+  HAL_ADC_Init(&hadc1);
+
+  /**Configure the ADC multi-mode
+   */
+  multimode.Mode = ADC_DUALMODE_REGSIMULT_INJECSIMULT;
+  HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode);
+
+  /**Configure Regular Channel
+   */
+  sConfig.Channel      = TMP36_ADC1_CHANNEL;
+  sConfig.Rank         = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
+  HAL_ADC_ConfigChannel(&hadc1, &sConfig);
+
+  /**Configure Regular Channel
+   */
+  sConfig.Channel = VIN_ADC1_CHANNEL;
+  sConfig.Rank    = ADC_REGULAR_RANK_2;
+  HAL_ADC_ConfigChannel(&hadc1, &sConfig);
+
+  /**Configure Injected Channel
+   */
+  // F in = 10.66 MHz
+  /*
+   * Injected time is 1 delay clock + (12 adc cycles*4)+4*sampletime =~217
+   * clocks = 0.2ms Charge time is 0.016 uS ideally So Sampling time must be >=
+   * 0.016uS 1/10.66MHz is 0.09uS, so 1 CLK is *should* be enough
+   * */
+  sConfigInjected.InjectedChannel               = TIP_TEMP_ADC1_CHANNEL;
+  sConfigInjected.InjectedRank                  = 1;
+  sConfigInjected.InjectedNbrOfConversion       = 4;
+  sConfigInjected.InjectedSamplingTime          = ADC_SAMPLETIME_1CYCLE_5;
+  sConfigInjected.ExternalTrigInjecConv         = ADC_EXTERNALTRIGINJECCONV_T2_CC1;
+  sConfigInjected.AutoInjectedConv              = DISABLE;
+  sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
+  sConfigInjected.InjectedOffset                = 0;
+
+  HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
+  sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+
+  sConfigInjected.InjectedRank = 2;
+  HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
+  sConfigInjected.InjectedRank = 3;
+  HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
+  sConfigInjected.InjectedRank = 4;
+  HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
+  SET_BIT(hadc1.Instance->CR1, (ADC_CR1_JEOCIE)); // Enable end of injected conv irq
+  // Run ADC internal calibration
+  while (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK)
+    ;
+}
+
+/* ADC2 init function */
+static void MX_ADC2_Init(void) {
+  ADC_ChannelConfTypeDef   sConfig;
+  ADC_InjectionConfTypeDef sConfigInjected;
+
+  /**Common config
+   */
+  hadc2.Instance                   = ADC2;
+  hadc2.Init.ScanConvMode          = ADC_SCAN_ENABLE;
+  hadc2.Init.ContinuousConvMode    = ENABLE;
+  hadc2.Init.DiscontinuousConvMode = DISABLE;
+  hadc2.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
+  hadc2.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+  hadc2.Init.NbrOfConversion       = ADC_CHANNELS;
+  HAL_ADC_Init(&hadc2);
+
+  /**Configure Regular Channel
+   */
+  sConfig.Channel      = TMP36_ADC2_CHANNEL;
+  sConfig.Rank         = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
+  HAL_ADC_ConfigChannel(&hadc2, &sConfig);
+
+  sConfig.Channel = VIN_ADC2_CHANNEL;
+  sConfig.Rank    = ADC_REGULAR_RANK_2;
+  HAL_ADC_ConfigChannel(&hadc2, &sConfig);
+
+  /**Configure Injected Channel
+   */
+  sConfigInjected.InjectedChannel               = TIP_TEMP_ADC2_CHANNEL;
+  sConfigInjected.InjectedRank                  = ADC_INJECTED_RANK_1;
+  sConfigInjected.InjectedNbrOfConversion       = 4;
+  sConfigInjected.InjectedSamplingTime          = ADC_SAMPLETIME_1CYCLE_5;
+  sConfigInjected.ExternalTrigInjecConv         = ADC_EXTERNALTRIGINJECCONV_T2_CC1;
+  sConfigInjected.AutoInjectedConv              = DISABLE;
+  sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
+  sConfigInjected.InjectedOffset                = 0;
+  HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
+  sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+
+  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_2;
+  HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
+  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_3;
+  HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
+  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_4;
+  HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
+
+  // Run ADC internal calibration
+  while (HAL_ADCEx_Calibration_Start(&hadc2) != HAL_OK)
+    ;
+}
+/* I2C1 init function */
+static void MX_I2C1_Init(void) {
+  hi2c1.Instance        = I2C1;
+  hi2c1.Init.ClockSpeed = 75000;
+  // OLED doesnt handle >100k when its asleep (off).
+  hi2c1.Init.DutyCycle       = I2C_DUTYCYCLE_2;
+  hi2c1.Init.OwnAddress1     = 0;
+  hi2c1.Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;
+  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c1.Init.OwnAddress2     = 0;
+  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c1.Init.NoStretchMode   = I2C_NOSTRETCH_DISABLE;
+  HAL_I2C_Init(&hi2c1);
+}
+
+/* IWDG init function */
+static void MX_IWDG_Init(void) {
+  hiwdg.Instance       = IWDG;
+  hiwdg.Init.Prescaler = IWDG_PRESCALER_256;
+  hiwdg.Init.Reload    = 100;
+#ifndef SWD_ENABLE
+  HAL_IWDG_Init(&hiwdg);
+#endif
+}
+
+/* TIM3 init function */
+static void MX_TIM3_Init(void) {
+  TIM_ClockConfigTypeDef  sClockSourceConfig;
+  TIM_MasterConfigTypeDef sMasterConfig;
+  TIM_OC_InitTypeDef      sConfigOC;
+
+  htim3.Instance               = TIM3;
+  htim3.Init.Prescaler         = 8;
+  htim3.Init.CounterMode       = TIM_COUNTERMODE_UP;
+  htim3.Init.Period            = 100;                           // 5 Khz PWM freq
+  htim3.Init.ClockDivision     = TIM_CLOCKDIVISION_DIV4;        // 4mhz before div
+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; // Preload the ARR register (though we dont use this)
+  HAL_TIM_Base_Init(&htim3);
+
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig);
+
+  HAL_TIM_PWM_Init(&htim3);
+
+  HAL_TIM_OC_Init(&htim3);
+
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode     = TIM_MASTERSLAVEMODE_DISABLE;
+  HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig);
+
+  sConfigOC.OCMode     = TIM_OCMODE_PWM1;
+  sConfigOC.Pulse      = 50; // 50% duty cycle, that is AC coupled through the cap
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
+  HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, PWM_Out_CHANNEL);
+
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  /**TIM3 GPIO Configuration
+   PWM_Out_Pin     ------> TIM3_CH1
+   */
+  GPIO_InitStruct.Pin   = PWM_Out_Pin;
+  GPIO_InitStruct.Mode  = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // We would like sharp rising edges
+  HAL_GPIO_Init(PWM_Out_GPIO_Port, &GPIO_InitStruct);
+#ifdef MODEL_TS100
+  // Remap TIM3_CH1 to be on PB4
+  __HAL_AFIO_REMAP_TIM3_PARTIAL();
+#else
+  // No re-map required
+#endif
+  HAL_TIM_PWM_Start(&htim3, PWM_Out_CHANNEL);
+}
+/* TIM3 init function */
+static void MX_TIM2_Init(void) {
+  /*
+   * We use the channel 1 to trigger the ADC at end of PWM period
+   * And we use the channel 4 as the PWM modulation source using Interrupts
+   * */
+  TIM_ClockConfigTypeDef  sClockSourceConfig;
+  TIM_MasterConfigTypeDef sMasterConfig;
+  TIM_OC_InitTypeDef      sConfigOC;
+
+  // Timer 2 is fairly slow as its being used to run the PWM and trigger the ADC
+  // in the PWM off time.
+  htim2.Instance = TIM2;
+  // dummy value, will be reconfigured by BSPInit()
+  htim2.Init.Prescaler = 2000; // 2 MHz timer clock/2000 = 1 kHz tick rate
+
+  // pwm out is 10k from tim3, we want to run our PWM at around 10hz or slower on the output stage
+  // These values give a rate of around 3.5 Hz for "fast" mode and 1.84 Hz for "slow"
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  // dummy value, will be reconfigured by BSPInit()
+  htim2.Init.Period            = 255 + 17 * 2;
+  htim2.Init.ClockDivision     = TIM_CLOCKDIVISION_DIV4; // 8 MHz (x2 APB1) before divide
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  htim2.Init.RepetitionCounter = 0;
+  HAL_TIM_Base_Init(&htim2);
+
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig);
+
+  HAL_TIM_PWM_Init(&htim2);
+  HAL_TIM_OC_Init(&htim2);
+
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode     = TIM_MASTERSLAVEMODE_DISABLE;
+  HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig);
+
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+  // dummy value, will be reconfigured by BSPInit() in the BSP.cpp
+  sConfigOC.Pulse = 255 + 13 * 2; // 13 -> Delay of 7 ms
+  // 255 is the largest time period of the drive signal, and then offset ADC sample to be a bit delayed after this
+  /*
+   * It takes 4 milliseconds for output to be stable after PWM turns off.
+   * Assume ADC samples in 0.5ms
+   * We need to set this to 100% + 4.5ms
+   * */
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
+  HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1);
+  sConfigOC.Pulse = 0; // default to entirely off
+  HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4);
+
+  HAL_TIM_Base_Start_IT(&htim2);
+  HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
+  HAL_TIM_PWM_Start_IT(&htim2, TIM_CHANNEL_4);
+  HAL_NVIC_SetPriority(TIM2_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(TIM2_IRQn);
+}
+
+/**
+ * Enable DMA controller clock
+ */
+static void MX_DMA_Init(void) {
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel6_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn);
+  /* DMA1_Channel7_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
+}
+
+/** Configure pins as
+ * Analog
+ * Input
+ * Output
+ * EVENT_OUT
+ * EXTI
+ * Free pins are configured automatically as Analog
+ PB0   ------> ADCx_IN8
+ PB1   ------> ADCx_IN9
+ */
+static void MX_GPIO_Init(void) {
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET);
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  /*Configure GPIO pins : PD0 PD1 */
+  GPIO_InitStruct.Pin  = GPIO_PIN_0 | GPIO_PIN_1;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+  /*Configure peripheral I/O remapping */
+  __HAL_AFIO_REMAP_PD01_ENABLE();
+  //^ remap XTAL so that pins can be analog (all input buffers off).
+  // reduces power consumption
+
+  /*
+   * Configure All pins as analog by default
+   */
+  GPIO_InitStruct.Pin  = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_15;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
+#ifdef MODEL_TS100
+                        GPIO_PIN_3 |
+#endif
+                        GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+#ifdef MODEL_TS100
+#ifndef SWD_ENABLE
+  /* Pull USB and SWD lines low to prevent enumeration attempts and EMI affecting
+   * the debug core */
+  GPIO_InitStruct.Pin   = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14;
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_11, GPIO_PIN_RESET);
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, GPIO_PIN_RESET);
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_13, GPIO_PIN_RESET);
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_14, GPIO_PIN_RESET);
+#else
+  /* Make all lines affecting SWD floating to allow debugging */
+  GPIO_InitStruct.Pin  = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_13;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+#endif
+#else
+  /* TS80 */
+  /* Leave USB lines open circuit*/
+
+#endif
+
+  /*Configure GPIO pins : KEY_B_Pin KEY_A_Pin */
+  GPIO_InitStruct.Pin  = KEY_B_Pin | KEY_A_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  HAL_GPIO_Init(KEY_B_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : OLED_RESET_Pin */
+  GPIO_InitStruct.Pin   = OLED_RESET_Pin;
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(OLED_RESET_GPIO_Port, &GPIO_InitStruct);
+  HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET);
+
+  // Pull down LCD reset
+  HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET);
+  HAL_Delay(30);
+  HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_SET);
+}
+#ifdef USE_FULL_ASSERT
+void assert_failed(uint8_t *file, uint32_t line) { asm("bkpt"); }
+#endif

source/Core/BSP/Miniware/Setup.h

@@ -26,10 +26,10 @@ extern IWDG_HandleTypeDef hiwdg;
 
 extern TIM_HandleTypeDef htim2;
 extern TIM_HandleTypeDef htim3;
-void Setup_HAL();
-uint16_t getADC(uint8_t channel);
+void                     Setup_HAL();
+uint16_t                 getADC(uint8_t channel);
 
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); //Since the hal header file does not define this one
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); // Since the hal header file does not define this one
 
 #ifdef __cplusplus
 }

source/Core/BSP/Miniware/Software_I2C.h

@@ -0,0 +1,30 @@
+/*
+ * Software_I2C.h
+ *
+ *  Created on: 25 Jul 2020
+ *      Author: Ralim
+ */
+
+#ifndef BSP_MINIWARE_SOFTWARE_I2C_H_
+#define BSP_MINIWARE_SOFTWARE_I2C_H_
+#include "BSP.h"
+#include "Model_Config.h"
+#include "stm32f1xx_hal.h"
+#ifdef I2C_SOFT
+
+#define SOFT_SCL_HIGH() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_SET)
+#define SOFT_SCL_LOW()  HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_RESET)
+#define SOFT_SDA_HIGH() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_SET)
+#define SOFT_SDA_LOW()  HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET)
+#define SOFT_SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port, SDA2_Pin) == GPIO_PIN_SET ? 1 : 0)
+#define SOFT_SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port, SCL2_Pin) == GPIO_PIN_SET ? 1 : 0)
+#define SOFT_I2C_DELAY()              \
+  {                                   \
+    for (int xx = 0; xx < 40; xx++) { \
+      asm("nop");                     \
+    }                                 \
+  }
+
+#endif
+
+#endif /* BSP_MINIWARE_SOFTWARE_I2C_H_ */

source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h

@@ -0,0 +1,216 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx.h
+ * @author  MCD Application Team
+ * @version V4.2.0
+ * @date    31-March-2017
+ * @brief   CMSIS STM32F1xx Device Peripheral Access Layer Header File.
+ *
+ *          The file is the unique include file that the application programmer
+ *          is using in the C source code, usually in main.c. This file contains:
+ *            - Configuration section that allows to select:
+ *              - The STM32F1xx device used in the target application
+ *              - To use or not the peripheral<61>s drivers in application code(i.e.
+ *                code will be based on direct access to peripheral<61>s registers
+ *                rather than drivers API), this option is controlled by
+ *                "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx
+ * @{
+ */
+
+#ifndef __STM32F1XX_H
+#define __STM32F1XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined(STM32F1)
+#define STM32F1
+#endif /* STM32F1 */
+
+/* Uncomment the line below according to the target STM32L device used in your
+   application
+  */
+
+#if !defined(STM32F100xB) && !defined(STM32F100xE) && !defined(STM32F101x6) && !defined(STM32F101xB) && !defined(STM32F101xE) && !defined(STM32F101xG) && !defined(STM32F102x6) \
+    && !defined(STM32F102xB) && !defined(STM32F103x6) && !defined(STM32F103xB) && !defined(STM32F103xE) && !defined(STM32F103xG) && !defined(STM32F105xC) && !defined(STM32F107xC)
+/* #define STM32F100xB  */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
+/* #define STM32F100xE */  /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
+/* #define STM32F101x6  */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
+/* #define STM32F101xB  */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
+/* #define STM32F101xE */  /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
+/* #define STM32F101xG  */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
+/* #define STM32F102x6 */  /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
+/* #define STM32F102xB  */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
+/* #define STM32F103x6  */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
+/* #define STM32F103xB  */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
+/* #define STM32F103xE */  /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
+/* #define STM32F103xG  */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
+/* #define STM32F105xC */  /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
+/* #define STM32F107xC  */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined(USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+/*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V4.2.0
+ */
+#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
+#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F1_CMSIS_VERSION_RC   (0x00) /*!< [7:0]  release candidate */
+#define __STM32F1_CMSIS_VERSION      ((__STM32F1_CMSIS_VERSION_MAIN << 24) | (__STM32F1_CMSIS_VERSION_SUB1 << 16) | (__STM32F1_CMSIS_VERSION_SUB2 << 8) | (__STM32F1_CMSIS_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F100xB)
+#include "stm32f100xb.h"
+#elif defined(STM32F100xE)
+#include "stm32f100xe.h"
+#elif defined(STM32F101x6)
+#include "stm32f101x6.h"
+#elif defined(STM32F101xB)
+#include "stm32f101xb.h"
+#elif defined(STM32F101xE)
+#include "stm32f101xe.h"
+#elif defined(STM32F101xG)
+#include "stm32f101xg.h"
+#elif defined(STM32F102x6)
+#include "stm32f102x6.h"
+#elif defined(STM32F102xB)
+#include "stm32f102xb.h"
+#elif defined(STM32F103x6)
+#include "stm32f103x6.h"
+#elif defined(STM32F103xB)
+#include "stm32f103xb.h"
+#elif defined(STM32F103xE)
+#include "stm32f103xe.h"
+#elif defined(STM32F103xG)
+#include "stm32f103xg.h"
+#elif defined(STM32F105xC)
+#include "stm32f105xc.h"
+#elif defined(STM32F107xC)
+#include "stm32f107xc.h"
+#else
+#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
+
+typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrorStatus;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+/**
+ * @}
+ */
+
+#if defined(USE_HAL_DRIVER)
+#include "stm32f1xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F1xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h

@@ -0,0 +1,115 @@
+/**
+ ******************************************************************************
+ * @file    system_stm32f10x.h
+ * @author  MCD Application Team
+ * @version V4.2.0
+ * @date    31-March-2017
+ * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern uint32_t      SystemCoreClock;    /*!< System Clock Frequency (Core Clock) */
+extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8U];  /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_common_tables.h

@@ -1,42 +1,42 @@
 /* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date:        19. October 2015
-* $Revision: 	V.1.4.5 a
-*
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_common_tables.h
-*
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
+ * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+ *
+ * $Date:        19. October 2015
+ * $Revision: 	V.1.4.5 a
+ *
+ * Project: 	    CMSIS DSP Library
+ * Title:	    arm_common_tables.h
+ *
+ * Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+ *
+ * Target Processor: Cortex-M4/Cortex-M3
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *   - Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   - Neither the name of ARM LIMITED nor the names of its contributors
+ *     may be used to endorse or promote products derived from this
+ *     software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
 
 #ifndef _ARM_COMMON_TABLES_H
 #define _ARM_COMMON_TABLES_H
@@ -44,8 +44,8 @@
 #include "arm_math.h"
 
 extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
+extern const q15_t    armRecipTableQ15[64];
+extern const q31_t    armRecipTableQ31[64];
 /* extern const q31_t realCoefAQ31[1024]; */
 /* extern const q31_t realCoefBQ31[1024]; */
 extern const float32_t twiddleCoef_16[32];
@@ -58,24 +58,24 @@ extern const float32_t twiddleCoef_1024[2048];
 extern const float32_t twiddleCoef_2048[4096];
 extern const float32_t twiddleCoef_4096[8192];
 #define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
+extern const q31_t     twiddleCoef_16_q31[24];
+extern const q31_t     twiddleCoef_32_q31[48];
+extern const q31_t     twiddleCoef_64_q31[96];
+extern const q31_t     twiddleCoef_128_q31[192];
+extern const q31_t     twiddleCoef_256_q31[384];
+extern const q31_t     twiddleCoef_512_q31[768];
+extern const q31_t     twiddleCoef_1024_q31[1536];
+extern const q31_t     twiddleCoef_2048_q31[3072];
+extern const q31_t     twiddleCoef_4096_q31[6144];
+extern const q15_t     twiddleCoef_16_q15[24];
+extern const q15_t     twiddleCoef_32_q15[48];
+extern const q15_t     twiddleCoef_64_q15[96];
+extern const q15_t     twiddleCoef_128_q15[192];
+extern const q15_t     twiddleCoef_256_q15[384];
+extern const q15_t     twiddleCoef_512_q15[768];
+extern const q15_t     twiddleCoef_1024_q15[1536];
+extern const q15_t     twiddleCoef_2048_q15[3072];
+extern const q15_t     twiddleCoef_4096_q15[6144];
 extern const float32_t twiddleCoef_rfft_32[32];
 extern const float32_t twiddleCoef_rfft_64[64];
 extern const float32_t twiddleCoef_rfft_128[128];
@@ -85,14 +85,13 @@ extern const float32_t twiddleCoef_rfft_1024[1024];
 extern const float32_t twiddleCoef_rfft_2048[2048];
 extern const float32_t twiddleCoef_rfft_4096[4096];
 
-
 /* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
 #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
 #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
 #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
@@ -108,13 +107,13 @@ extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENG
 extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
 
 /* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
 #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
 #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
 
@@ -130,7 +129,7 @@ extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4
 
 /* Tables for Fast Math Sine and Cosine */
 extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t     sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t     sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
 
 #endif /*  ARM_COMMON_TABLES_H */

source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_const_structs.h

@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+ *
+ * $Date:        19. March 2015
+ * $Revision: 	V.1.4.5
+ *
+ * Project: 	    CMSIS DSP Library
+ * Title:	    arm_const_structs.h
+ *
+ * Description:	This file has constant structs that are initialized for
+ *              user convenience.  For example, some can be given as
+ *              arguments to the arm_cfft_f32() function.
+ *
+ * Target Processor: Cortex-M4/Cortex-M3
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *   - Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   - Neither the name of ARM LIMITED nor the names of its contributors
+ *     may be used to endorse or promote products derived from this
+ *     software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_common_tables.h"
+#include "arm_math.h"
+
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_armcc.h

@@ -1,9 +1,9 @@
-/**************************************************************************//**
- * @file     cmsis_armcc.h
- * @brief    CMSIS Cortex-M Core Function/Instruction Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
+/**************************************************************************/ /**
+                                                                              * @file     cmsis_armcc.h
+                                                                              * @brief    CMSIS Cortex-M Core Function/Instruction Header File
+                                                                              * @version  V4.30
+                                                                              * @date     20. October 2015
+                                                                              ******************************************************************************/
 /* Copyright (c) 2009 - 2015 ARM LIMITED
 
    All rights reserved.
@@ -31,13 +31,11 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #ifndef __CMSIS_ARMCC_H
 #define __CMSIS_ARMCC_H
 
-
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
 #endif
 
 /* ###########################  Core Function Access  ########################### */
@@ -54,252 +52,212 @@
   \details Returns the content of the Control Register.
   \return               Control Register value
  */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
+__STATIC_INLINE uint32_t __get_CONTROL(void) {
+  register uint32_t __regControl __ASM("control");
+  return (__regControl);
 }
 
-
 /**
   \brief   Set Control Register
   \details Writes the given value to the Control Register.
   \param [in]    control  Control Register value to set
  */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
+__STATIC_INLINE void __set_CONTROL(uint32_t control) {
+  register uint32_t __regControl __ASM("control");
   __regControl = control;
 }
 
-
 /**
   \brief   Get IPSR Register
   \details Returns the content of the IPSR Register.
   \return               IPSR Register value
  */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
+__STATIC_INLINE uint32_t __get_IPSR(void) {
+  register uint32_t __regIPSR __ASM("ipsr");
+  return (__regIPSR);
 }
 
-
 /**
   \brief   Get APSR Register
   \details Returns the content of the APSR Register.
   \return               APSR Register value
  */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
+__STATIC_INLINE uint32_t __get_APSR(void) {
+  register uint32_t __regAPSR __ASM("apsr");
+  return (__regAPSR);
 }
 
-
 /**
   \brief   Get xPSR Register
   \details Returns the content of the xPSR Register.
   \return               xPSR Register value
  */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
+__STATIC_INLINE uint32_t __get_xPSR(void) {
+  register uint32_t __regXPSR __ASM("xpsr");
+  return (__regXPSR);
 }
 
-
 /**
   \brief   Get Process Stack Pointer
   \details Returns the current value of the Process Stack Pointer (PSP).
   \return               PSP Register value
  */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
+__STATIC_INLINE uint32_t __get_PSP(void) {
+  register uint32_t __regProcessStackPointer __ASM("psp");
+  return (__regProcessStackPointer);
 }
 
-
 /**
   \brief   Set Process Stack Pointer
   \details Assigns the given value to the Process Stack Pointer (PSP).
   \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) {
+  register uint32_t __regProcessStackPointer __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
 
-
 /**
   \brief   Get Main Stack Pointer
   \details Returns the current value of the Main Stack Pointer (MSP).
   \return               MSP Register value
  */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
+__STATIC_INLINE uint32_t __get_MSP(void) {
+  register uint32_t __regMainStackPointer __ASM("msp");
+  return (__regMainStackPointer);
 }
 
-
 /**
   \brief   Set Main Stack Pointer
   \details Assigns the given value to the Main Stack Pointer (MSP).
   \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) {
+  register uint32_t __regMainStackPointer __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
 
-
 /**
   \brief   Get Priority Mask
   \details Returns the current state of the priority mask bit from the Priority Mask Register.
   \return               Priority Mask value
  */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
+__STATIC_INLINE uint32_t __get_PRIMASK(void) {
+  register uint32_t __regPriMask __ASM("primask");
+  return (__regPriMask);
 }
 
-
 /**
   \brief   Set Priority Mask
   \details Assigns the given value to the Priority Mask Register.
   \param [in]    priMask  Priority Mask
  */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) {
+  register uint32_t __regPriMask __ASM("primask");
   __regPriMask = (priMask);
 }
 
-
-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
 
 /**
   \brief   Enable FIQ
   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
            Can only be executed in Privileged modes.
  */
-#define __enable_fault_irq                __enable_fiq
-
+#define __enable_fault_irq __enable_fiq
 
 /**
   \brief   Disable FIQ
   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
            Can only be executed in Privileged modes.
  */
-#define __disable_fault_irq               __disable_fiq
-
+#define __disable_fault_irq __disable_fiq
 
 /**
   \brief   Get Base Priority
   \details Returns the current value of the Base Priority register.
   \return               Base Priority register value
  */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
+__STATIC_INLINE uint32_t __get_BASEPRI(void) {
+  register uint32_t __regBasePri __ASM("basepri");
+  return (__regBasePri);
 }
 
-
 /**
   \brief   Set Base Priority
   \details Assigns the given value to the Base Priority register.
   \param [in]    basePri  Base Priority value to set
  */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) {
+  register uint32_t __regBasePri __ASM("basepri");
   __regBasePri = (basePri & 0xFFU);
 }
 
-
 /**
   \brief   Set Base Priority with condition
   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
            or the new value increases the BASEPRI priority level.
   \param [in]    basePri  Base Priority value to set
  */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) {
+  register uint32_t __regBasePriMax __ASM("basepri_max");
   __regBasePriMax = (basePri & 0xFFU);
 }
 
-
 /**
   \brief   Get Fault Mask
   \details Returns the current value of the Fault Mask register.
   \return               Fault Mask register value
  */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
+__STATIC_INLINE uint32_t __get_FAULTMASK(void) {
+  register uint32_t __regFaultMask __ASM("faultmask");
+  return (__regFaultMask);
 }
 
-
 /**
   \brief   Set Fault Mask
   \details Assigns the given value to the Fault Mask register.
   \param [in]    faultMask  Fault Mask value to set
  */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) {
+  register uint32_t __regFaultMask __ASM("faultmask");
   __regFaultMask = (faultMask & (uint32_t)1);
 }
 
 #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
 
-
-#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
 
 /**
   \brief   Get FPSCR
   \details Returns the current value of the Floating Point Status/Control register.
   \return               Floating Point Status/Control register value
  */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
+__STATIC_INLINE uint32_t __get_FPSCR(void) {
 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
+  register uint32_t __regfpscr __ASM("fpscr");
+  return (__regfpscr);
 #else
-   return(0U);
+  return (0U);
 #endif
 }
 
-
 /**
   \brief   Set FPSCR
   \details Assigns the given value to the Floating Point Status/Control register.
   \param [in]    fpscr  Floating Point Status/Control value to set
  */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) {
 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
-  register uint32_t __regfpscr         __ASM("fpscr");
+  register uint32_t __regfpscr __ASM("fpscr");
   __regfpscr = (fpscr);
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
 
-
-
 /*@} end of CMSIS_Core_RegAccFunctions */
 
-
 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions
@@ -310,30 +268,26 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
   \brief   No Operation
   \details No Operation does nothing. This instruction can be used for code alignment purposes.
  */
-#define __NOP                             __nop
-
+#define __NOP __nop
 
 /**
   \brief   Wait For Interrupt
   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
  */
-#define __WFI                             __wfi
-
+#define __WFI __wfi
 
 /**
   \brief   Wait For Event
   \details Wait For Event is a hint instruction that permits the processor to enter
            a low-power state until one of a number of events occurs.
  */
-#define __WFE                             __wfe
-
+#define __WFE __wfe
 
 /**
   \brief   Send Event
   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  */
-#define __SEV                             __sev
-
+#define __SEV __sev
 
 /**
   \brief   Instruction Synchronization Barrier
@@ -341,33 +295,36 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
            so that all instructions following the ISB are fetched from cache or memory,
            after the instruction has been completed.
  */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
+#define __ISB()           \
+  do {                    \
+    __schedule_barrier(); \
+    __isb(0xF);           \
+    __schedule_barrier(); \
+  } while (0U)
 
 /**
   \brief   Data Synchronization Barrier
   \details Acts as a special kind of Data Memory Barrier.
            It completes when all explicit memory accesses before this instruction complete.
  */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
+#define __DSB()           \
+  do {                    \
+    __schedule_barrier(); \
+    __dsb(0xF);           \
+    __schedule_barrier(); \
+  } while (0U)
 
 /**
   \brief   Data Memory Barrier
   \details Ensures the apparent order of the explicit memory operations before
            and after the instruction, without ensuring their completion.
  */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
+#define __DMB()           \
+  do {                    \
+    __schedule_barrier(); \
+    __dmb(0xF);           \
+    __schedule_barrier(); \
+  } while (0U)
 
 /**
   \brief   Reverse byte order (32 bit)
@@ -375,8 +332,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
-#define __REV                             __rev
-
+#define __REV __rev
 
 /**
   \brief   Reverse byte order (16 bit)
@@ -385,11 +341,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
   \return               Reversed value
  */
 #ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr }
 #endif
 
 /**
@@ -399,14 +351,9 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
   \return               Reversed value
  */
 #ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr }
 #endif
 
-
 /**
   \brief   Rotate Right in unsigned value (32 bit)
   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@@ -414,8 +361,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
   \param [in]    value  Number of Bits to rotate
   \return               Rotated value
  */
-#define __ROR                             __ror
-
+#define __ROR __ror
 
 /**
   \brief   Breakpoint
@@ -424,8 +370,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
   \param [in]    value  is ignored by the processor.
                  If required, a debugger can use it to store additional information about the breakpoint.
  */
-#define __BKPT(value)                       __breakpoint(value)
-
+#define __BKPT(value) __breakpoint(value)
 
 /**
   \brief   Reverse bit order of value
@@ -433,37 +378,33 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
   \param [in]    value  Value to reverse
   \return               Reversed value
  */
-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
-  #define __RBIT                          __rbit
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+#define __RBIT __rbit
 #else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
   uint32_t result;
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+  int32_t  s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
 
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value; value >>= 1U)
-  {
+  result = value; /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U) {
     result <<= 1U;
     result |= value & 1U;
     s--;
   }
-  result <<= s;                        /* shift when v's highest bits are zero */
-  return(result);
+  result <<= s; /* shift when v's highest bits are zero */
+  return (result);
 }
 #endif
 
-
 /**
   \brief   Count leading zeros
   \details Counts the number of leading zeros of a data value.
   \param [in]  value  Value to count the leading zeros
   \return             number of leading zeros in value
  */
-#define __CLZ                             __clz
+#define __CLZ __clz
 
-
-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
 
 /**
   \brief   LDR Exclusive (8 bit)
@@ -472,12 +413,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return             value of type uint8_t at (*ptr)
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#define __LDREXB(ptr) ((uint8_t)__ldrex(ptr))
 #else
-  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop")
 #endif
 
-
 /**
   \brief   LDR Exclusive (16 bit)
   \details Executes a exclusive LDR instruction for 16 bit values.
@@ -485,12 +425,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return        value of type uint16_t at (*ptr)
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#define __LDREXH(ptr) ((uint16_t)__ldrex(ptr))
 #else
-  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop")
 #endif
 
-
 /**
   \brief   LDR Exclusive (32 bit)
   \details Executes a exclusive LDR instruction for 32 bit values.
@@ -498,12 +437,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return        value of type uint32_t at (*ptr)
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#define __LDREXW(ptr) ((uint32_t)__ldrex(ptr))
 #else
-  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop")
 #endif
 
-
 /**
   \brief   STR Exclusive (8 bit)
   \details Executes a exclusive STR instruction for 8 bit values.
@@ -513,12 +451,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return          1  Function failed
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#define __STREXB(value, ptr) __strex(value, ptr)
 #else
-  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
 #endif
 
-
 /**
   \brief   STR Exclusive (16 bit)
   \details Executes a exclusive STR instruction for 16 bit values.
@@ -528,12 +465,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return          1  Function failed
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#define __STREXH(value, ptr) __strex(value, ptr)
 #else
-  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
 #endif
 
-
 /**
   \brief   STR Exclusive (32 bit)
   \details Executes a exclusive STR instruction for 32 bit values.
@@ -543,18 +479,16 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return          1  Function failed
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#define __STREXW(value, ptr) __strex(value, ptr)
 #else
-  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
 #endif
 
-
 /**
   \brief   Remove the exclusive lock
   \details Removes the exclusive lock which is created by LDREX.
  */
-#define __CLREX                           __clrex
-
+#define __CLREX __clrex
 
 /**
   \brief   Signed Saturate
@@ -563,8 +497,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \param [in]    sat  Bit position to saturate to (1..32)
   \return             Saturated value
  */
-#define __SSAT                            __ssat
-
+#define __SSAT __ssat
 
 /**
   \brief   Unsigned Saturate
@@ -573,8 +506,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \param [in]    sat  Bit position to saturate to (0..31)
   \return             Saturated value
  */
-#define __USAT                            __usat
-
+#define __USAT __usat
 
 /**
   \brief   Rotate Right with Extend (32 bit)
@@ -584,22 +516,16 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return               Rotated value
  */
 #ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr }
 #endif
 
-
 /**
   \brief   LDRT Unprivileged (8 bit)
   \details Executes a Unprivileged LDRT instruction for 8 bit value.
   \param [in]    ptr  Pointer to data
   \return             value of type uint8_t at (*ptr)
  */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
+#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
 
 /**
   \brief   LDRT Unprivileged (16 bit)
@@ -607,8 +533,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
   \param [in]    ptr  Pointer to data
   \return        value of type uint16_t at (*ptr)
  */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
+#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
 
 /**
   \brief   LDRT Unprivileged (32 bit)
@@ -616,8 +541,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
   \param [in]    ptr  Pointer to data
   \return        value of type uint32_t at (*ptr)
  */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
+#define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
 
 /**
   \brief   STRT Unprivileged (8 bit)
@@ -625,8 +549,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
  */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
+#define __STRBT(value, ptr) __strt(value, ptr)
 
 /**
   \brief   STRT Unprivileged (16 bit)
@@ -634,8 +557,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
  */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
+#define __STRHT(value, ptr) __strt(value, ptr)
 
 /**
   \brief   STRT Unprivileged (32 bit)
@@ -643,92 +565,87 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
  */
-#define __STRT(value, ptr)                __strt(value, ptr)
+#define __STRT(value, ptr) __strt(value, ptr)
 
 #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-
 /* ###################  Compiler specific Intrinsics  ########################### */
 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
   Access to dedicated SIMD instructions
   @{
 */
 
-#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
 
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
+#define __SADD8   __sadd8
+#define __QADD8   __qadd8
+#define __SHADD8  __shadd8
+#define __UADD8   __uadd8
+#define __UQADD8  __uqadd8
+#define __UHADD8  __uhadd8
+#define __SSUB8   __ssub8
+#define __QSUB8   __qsub8
+#define __SHSUB8  __shsub8
+#define __USUB8   __usub8
+#define __UQSUB8  __uqsub8
+#define __UHSUB8  __uhsub8
+#define __SADD16  __sadd16
+#define __QADD16  __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16  __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16  __ssub16
+#define __QSUB16  __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16  __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX    __sasx
+#define __QASX    __qasx
+#define __SHASX   __shasx
+#define __UASX    __uasx
+#define __UQASX   __uqasx
+#define __UHASX   __uhasx
+#define __SSAX    __ssax
+#define __QSAX    __qsax
+#define __SHSAX   __shsax
+#define __USAX    __usax
+#define __UQSAX   __uqsax
+#define __UHSAX   __uhsax
+#define __USAD8   __usad8
+#define __USADA8  __usada8
+#define __SSAT16  __ssat16
+#define __USAT16  __usat16
+#define __UXTB16  __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16  __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD   __smuad
+#define __SMUADX  __smuadx
+#define __SMLAD   __smlad
+#define __SMLADX  __smladx
+#define __SMLALD  __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD   __smusd
+#define __SMUSDX  __smusdx
+#define __SMLSD   __smlsd
+#define __SMLSDX  __smlsdx
+#define __SMLSLD  __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL     __sel
+#define __QADD    __qadd
+#define __QSUB    __qsub
 
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))
 
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))
 
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+#define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U)) >> 32U))
 
 #endif /* (__CORTEX_M >= 0x04) */
 /*@} end of group CMSIS_SIMD_intrinsics */
 
-
 #endif /* __CMSIS_ARMCC_H */

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0.h

@@ -0,0 +1,723 @@
+/**************************************************************************/ /**
+                                                                              * @file     core_cm0.h
+                                                                              * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+                                                                              * @version  V4.30
+                                                                              * @date     20. October 2015
+                                                                              ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x04U)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB  (0x1EU)                                                       /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION      ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
+
+#if defined(__CC_ARM)
+#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
+#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
+#define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
+#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
+#define __STATIC_INLINE static __inline
+
+#elif defined(__GNUC__)
+#define __ASM           __asm  /*!< asm keyword for GNU Compiler */
+#define __INLINE        inline /*!< inline keyword for GNU Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined(__ICCARM__)
+#define __ASM           __asm  /*!< asm keyword for IAR Compiler */
+#define __INLINE        inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE static inline
+
+#elif defined(__TMS470__)
+#define __ASM           __asm /*!< asm keyword for TI CCS Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined(__TASKING__)
+#define __ASM           __asm  /*!< asm keyword for TASKING Compiler */
+#define __INLINE        inline /*!< inline keyword for TASKING Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined(__CSMC__)
+#define __packed
+#define __ASM           _asm   /*!< asm keyword for COSMIC Compiler */
+#define __INLINE        inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+#define __STATIC_INLINE static inline
+
+#else
+#error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined(__CC_ARM)
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__GNUC__)
+#if defined(__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__ICCARM__)
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__TMS470__)
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__TASKING__)
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__CSMC__)
+#if (__CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "core_cmFunc.h"  /* Core Function Access */
+#include "core_cmInstr.h" /* Core Instruction Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0_REV
+#define __CM0_REV 0x0000U
+#warning "__CM0_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O  volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM  volatile const /*! Defines 'read only' structure member permissions */
+#define __OM  volatile       /*! Defines 'write only' structure member permissions */
+#define __IOM volatile       /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+  struct {
+    uint32_t _reserved0 : 28; /*!< bit:  0..27  Reserved */
+    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
+    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
+    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
+    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U                 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U                 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U                 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+  struct {
+    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+  struct {
+    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
+    uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1 : 3;  /*!< bit: 25..27  Reserved */
+    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
+    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
+    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
+    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+  struct {
+    uint32_t _reserved0 : 1;  /*!< bit:      0  Reserved */
+    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+  __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+  uint32_t       RESERVED0[31U];
+  __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+  uint32_t       RSERVED1[31U];
+  __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+  uint32_t       RESERVED2[31U];
+  __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+  uint32_t       RESERVED3[31U];
+  uint32_t       RESERVED4[64U];
+  __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+  __IM uint32_t  CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;  /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  uint32_t       RESERVED0;
+  __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;   /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;   /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  uint32_t       RESERVED1;
+  __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE     (0xE000E000UL)        /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE    (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE     (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB     ((SCB_Type *)SCB_BASE)         /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC    ((NVIC_Type *)NVIC_BASE)       /*!< NVIC configuration struct */
+
+/*@} */
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)   ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
+#define _IP_IDX(IRQn)    ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
+  if ((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  } else {
+    NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
+
+  if ((int32_t)(IRQn) < 0) {
+    return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  } else {
+    return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void) {
+  __DSB(); /* Ensure all outstanding memory accesses included
+              buffered write are completed before reset */
+  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB(); /* Ensure completion of memory access */
+
+  for (;;) /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+    return (1UL); /* Reload value impossible */
+  }
+
+  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
+  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
+  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                                                    /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0plus.h

@@ -0,0 +1,839 @@
+/**************************************************************************/ /**
+                                                                              * @file     core_cm0plus.h
+                                                                              * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+                                                                              * @version  V4.30
+                                                                              * @date     20. October 2015
+                                                                              ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)                                                               /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x1EU)                                                               /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
+
+#if defined(__CC_ARM)
+#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
+#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
+#define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
+#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
+#define __STATIC_INLINE static __inline
+
+#elif defined(__GNUC__)
+#define __ASM           __asm  /*!< asm keyword for GNU Compiler */
+#define __INLINE        inline /*!< inline keyword for GNU Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined(__ICCARM__)
+#define __ASM           __asm  /*!< asm keyword for IAR Compiler */
+#define __INLINE        inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE static inline
+
+#elif defined(__TMS470__)
+#define __ASM           __asm /*!< asm keyword for TI CCS Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined(__TASKING__)
+#define __ASM           __asm  /*!< asm keyword for TASKING Compiler */
+#define __INLINE        inline /*!< inline keyword for TASKING Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined(__CSMC__)
+#define __packed
+#define __ASM           _asm   /*!< asm keyword for COSMIC Compiler */
+#define __INLINE        inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+#define __STATIC_INLINE static inline
+
+#else
+#error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined(__CC_ARM)
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__GNUC__)
+#if defined(__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__ICCARM__)
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__TMS470__)
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__TASKING__)
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__CSMC__)
+#if (__CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "core_cmFunc.h"  /* Core Function Access */
+#include "core_cmInstr.h" /* Core Instruction Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0PLUS_REV
+#define __CM0PLUS_REV 0x0000U
+#warning "__CM0PLUS_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT 0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O  volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM  volatile const /*! Defines 'read only' structure member permissions */
+#define __OM  volatile       /*! Defines 'write only' structure member permissions */
+#define __IOM volatile       /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+  struct {
+    uint32_t _reserved0 : 28; /*!< bit:  0..27  Reserved */
+    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
+    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
+    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
+    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U                 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U                 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U                 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+  struct {
+    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+  struct {
+    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
+    uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1 : 3;  /*!< bit: 25..27  Reserved */
+    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
+    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
+    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
+    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+  struct {
+    uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+  __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+  uint32_t       RESERVED0[31U];
+  __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+  uint32_t       RSERVED1[31U];
+  __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+  uint32_t       RESERVED2[31U];
+  __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+  uint32_t       RESERVED3[31U];
+  uint32_t       RESERVED4[64U];
+  __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+  __IM uint32_t  CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;  /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+  uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;   /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;   /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  uint32_t       RESERVED1;
+  __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U                                  /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+  __IM uint32_t  TYPE; /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;  /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U                              /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U                               /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U                                 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U                               /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U                               /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U                                 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U                                /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U                          /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U                                 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U                              /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U                      /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U                        /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U                         /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U                     /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U                     /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U                     /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U                           /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U                               /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE     (0xE000E000UL)        /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE    (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE     (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB     ((SCB_Type *)SCB_BASE)         /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC    ((NVIC_Type *)NVIC_BASE)       /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL)  /*!< Memory Protection Unit */
+#define MPU      ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)   ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
+#define _IP_IDX(IRQn)    ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
+  if ((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  } else {
+    NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
+
+  if ((int32_t)(IRQn) < 0) {
+    return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  } else {
+    return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void) {
+  __DSB(); /* Ensure all outstanding memory accesses included
+              buffered write are completed before reset */
+  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB(); /* Ensure completion of memory access */
+
+  for (;;) /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+    return (1UL); /* Reload value impossible */
+  }
+
+  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
+  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
+  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                                                    /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmFunc.h

@@ -1,9 +1,9 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
+/**************************************************************************/ /**
+                                                                              * @file     core_cmFunc.h
+                                                                              * @brief    CMSIS Cortex-M Core Function Access Header File
+                                                                              * @version  V4.30
+                                                                              * @date     20. October 2015
+                                                                              ******************************************************************************/
 /* Copyright (c) 2009 - 2015 ARM LIMITED
 
    All rights reserved.
@@ -31,17 +31,15 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
+#pragma clang system_header /* treat file as system include file */
 #endif
 
 #ifndef __CORE_CMFUNC_H
 #define __CORE_CMFUNC_H
 
-
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@@ -49,36 +47,36 @@
 */
 
 /*------------------ RealView Compiler -----------------*/
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
+#if defined(__CC_ARM)
+#include "cmsis_armcc.h"
 
 /*------------------ ARM Compiler V6 -------------------*/
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armcc_V6.h"
+#include "cmsis_armcc_V6.h"
 
 /*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
+#elif defined(__GNUC__)
+#include "cmsis_gcc.h"
 
 /*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iar.h>
+#elif defined(__ICCARM__)
+#include <cmsis_iar.h>
 
 /*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
-  #include <cmsis_ccs.h>
+#elif defined(__TMS470__)
+#include <cmsis_ccs.h>
 
 /*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
+#elif defined(__TASKING__)
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
 
 /*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
-  #include <cmsis_csm.h>
+#elif defined(__CSMC__)
+#include <cmsis_csm.h>
 
 #endif
 

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmInstr.h

@@ -1,9 +1,9 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
+/**************************************************************************/ /**
+                                                                              * @file     core_cmInstr.h
+                                                                              * @brief    CMSIS Cortex-M Core Instruction Access Header File
+                                                                              * @version  V4.30
+                                                                              * @date     20. October 2015
+                                                                              ******************************************************************************/
 /* Copyright (c) 2009 - 2015 ARM LIMITED
 
    All rights reserved.
@@ -31,17 +31,15 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
+#pragma clang system_header /* treat file as system include file */
 #endif
 
 #ifndef __CORE_CMINSTR_H
 #define __CORE_CMINSTR_H
 
-
 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions
@@ -49,36 +47,36 @@
 */
 
 /*------------------ RealView Compiler -----------------*/
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
+#if defined(__CC_ARM)
+#include "cmsis_armcc.h"
 
 /*------------------ ARM Compiler V6 -------------------*/
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armcc_V6.h"
+#include "cmsis_armcc_V6.h"
 
 /*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
+#elif defined(__GNUC__)
+#include "cmsis_gcc.h"
 
 /*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iar.h>
+#elif defined(__ICCARM__)
+#include <cmsis_iar.h>
 
 /*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
-  #include <cmsis_ccs.h>
+#elif defined(__TMS470__)
+#include <cmsis_ccs.h>
 
 /*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
+#elif defined(__TASKING__)
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
 
 /*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
-  #include <cmsis_csm.h>
+#elif defined(__CSMC__)
+#include <cmsis_csm.h>
 
 #endif
 

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmSimd.h

@@ -1,9 +1,9 @@
-/**************************************************************************//**
- * @file     core_cmSimd.h
- * @brief    CMSIS Cortex-M SIMD Header File
- * @version  V4.30
- * @date     20. October 2015
- ******************************************************************************/
+/**************************************************************************/ /**
+                                                                              * @file     core_cmSimd.h
+                                                                              * @brief    CMSIS Cortex-M SIMD Header File
+                                                                              * @version  V4.30
+                                                                              * @date     20. October 2015
+                                                                              ******************************************************************************/
 /* Copyright (c) 2009 - 2015 ARM LIMITED
 
    All rights reserved.
@@ -31,21 +31,19 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
+#pragma clang system_header /* treat file as system include file */
 #endif
 
 #ifndef __CORE_CMSIMD_H
 #define __CORE_CMSIMD_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-
 /* ###################  Compiler specific Intrinsics  ########################### */
 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
   Access to dedicated SIMD instructions
@@ -53,42 +51,41 @@
 */
 
 /*------------------ RealView Compiler -----------------*/
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
+#if defined(__CC_ARM)
+#include "cmsis_armcc.h"
 
 /*------------------ ARM Compiler V6 -------------------*/
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armcc_V6.h"
+#include "cmsis_armcc_V6.h"
 
 /*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
+#elif defined(__GNUC__)
+#include "cmsis_gcc.h"
 
 /*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iar.h>
+#elif defined(__ICCARM__)
+#include <cmsis_iar.h>
 
 /*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
-  #include <cmsis_ccs.h>
+#elif defined(__TMS470__)
+#include <cmsis_ccs.h>
 
 /*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
+#elif defined(__TASKING__)
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
 
 /*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
-  #include <cmsis_csm.h>
+#elif defined(__CSMC__)
+#include <cmsis_csm.h>
 
 #endif
 
 /*@} end of group CMSIS_SIMD_intrinsics */
 
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_sc000.h

@@ -0,0 +1,849 @@
+/**************************************************************************/ /**
+                                                                              * @file     core_sc000.h
+                                                                              * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+                                                                              * @version  V4.30
+                                                                              * @date     20. October 2015
+                                                                              ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (0x04U)                                                           /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB  (0x1EU)                                                           /*!< [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION      ((__SC000_CMSIS_VERSION_MAIN << 16U) | __SC000_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+#if defined(__CC_ARM)
+#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
+#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
+#define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
+#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
+#define __STATIC_INLINE static __inline
+
+#elif defined(__GNUC__)
+#define __ASM           __asm  /*!< asm keyword for GNU Compiler */
+#define __INLINE        inline /*!< inline keyword for GNU Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined(__ICCARM__)
+#define __ASM           __asm  /*!< asm keyword for IAR Compiler */
+#define __INLINE        inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE static inline
+
+#elif defined(__TMS470__)
+#define __ASM           __asm /*!< asm keyword for TI CCS Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined(__TASKING__)
+#define __ASM           __asm  /*!< asm keyword for TASKING Compiler */
+#define __INLINE        inline /*!< inline keyword for TASKING Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined(__CSMC__)
+#define __packed
+#define __ASM           _asm   /*!< asm keyword for COSMIC Compiler */
+#define __INLINE        inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+#define __STATIC_INLINE static inline
+
+#else
+#error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined(__CC_ARM)
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__GNUC__)
+#if defined(__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__ICCARM__)
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__TMS470__)
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__TASKING__)
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__CSMC__)
+#if (__CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "core_cmFunc.h"  /* Core Function Access */
+#include "core_cmInstr.h" /* Core Instruction Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC000_REV
+#define __SC000_REV 0x0000U
+#warning "__SC000_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O  volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM  volatile const /*! Defines 'read only' structure member permissions */
+#define __OM  volatile       /*! Defines 'write only' structure member permissions */
+#define __IOM volatile       /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+  struct {
+    uint32_t _reserved0 : 28; /*!< bit:  0..27  Reserved */
+    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
+    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
+    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
+    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U                 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U                 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U                 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+  struct {
+    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+  struct {
+    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
+    uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1 : 3;  /*!< bit: 25..27  Reserved */
+    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
+    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
+    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
+    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+  struct {
+    uint32_t _reserved0 : 1;  /*!< bit:      0  Reserved */
+    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+  __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+  uint32_t       RESERVED0[31U];
+  __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+  uint32_t       RSERVED1[31U];
+  __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+  uint32_t       RESERVED2[31U];
+  __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+  uint32_t       RESERVED3[31U];
+  uint32_t       RESERVED4[64U];
+  __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+  __IM uint32_t  CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;  /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;  /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;   /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;   /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  uint32_t       RESERVED0[1U];
+  __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  uint32_t       RESERVED1[154U];
+  __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U                                   /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+  uint32_t       RESERVED0[2U];
+  __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U                                       /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+  __IM uint32_t  TYPE; /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;  /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U                              /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U                               /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U                                 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U                               /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U                               /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U                                 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U                                /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U                          /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U                                 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U                              /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U                      /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U                        /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U                         /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U                     /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U                     /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U                     /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U                           /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U                               /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE     (0xE000E000UL)        /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE    (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE     (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB  ((SCnSCB_Type *)SCS_BASE)      /*!< System control Register not in SCB */
+#define SCB     ((SCB_Type *)SCB_BASE)         /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC    ((NVIC_Type *)NVIC_BASE)       /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL)  /*!< Memory Protection Unit */
+#define MPU      ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)   ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
+#define _IP_IDX(IRQn)    ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
+  if ((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  } else {
+    NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
+
+  if ((int32_t)(IRQn) < 0) {
+    return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  } else {
+    return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void) {
+  __DSB(); /* Ensure all outstanding memory accesses included
+              buffered write are completed before reset */
+  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB(); /* Ensure completion of memory access */
+
+  for (;;) /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+    return (1UL); /* Reload value impossible */
+  }
+
+  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
+  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
+  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                                                    /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h

@@ -0,0 +1,358 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal.h
+ * @author  MCD Application Team
+ * @brief   This file contains all the functions prototypes for the HAL
+ *          module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_H
+#define __STM32F1xx_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_conf.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+typedef enum { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef;
+/**
+ * @}
+ */
+/* Exported types ------------------------------------------------------------*/
+extern uint32_t            uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
+
+/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
+ * @brief   Freeze/Unfreeze Peripherals in Debug mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ *                  STM32F101xC/D/E and STM32F103xC/D/E,
+ *                  STM32F101xF/G and STM32F103xF/G
+ *                  STM32F10xx4 and STM32F10xx6
+ *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ *       debug mode (not accessible by the user software in normal mode).
+ *       Refer to errata sheet of these devices for more details.
+ * @{
+ */
+
+/* Peripherals on APB1 */
+/**
+ * @brief  TIM2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM2()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
+
+/**
+ * @brief  TIM3 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM3()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
+
+#if defined(DBGMCU_CR_DBG_TIM4_STOP)
+/**
+ * @brief  TIM4 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM4()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM5_STOP)
+/**
+ * @brief  TIM5 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM5()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM6_STOP)
+/**
+ * @brief  TIM6 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM6()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM7_STOP)
+/**
+ * @brief  TIM7 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM7()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM12_STOP)
+/**
+ * @brief  TIM12 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM12()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM13_STOP)
+/**
+ * @brief  TIM13 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM13()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM14_STOP)
+/**
+ * @brief  TIM14 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM14()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
+#endif
+
+/**
+ * @brief  WWDG Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_WWDG()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
+
+/**
+ * @brief  IWDG Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_IWDG()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
+
+/**
+ * @brief  I2C1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
+
+#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+/**
+ * @brief  I2C2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#endif
+
+#if defined(DBGMCU_CR_DBG_CAN1_STOP)
+/**
+ * @brief  CAN1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_CAN1()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_CAN2_STOP)
+/**
+ * @brief  CAN2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_CAN2()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
+#endif
+
+/* Peripherals on APB2 */
+#if defined(DBGMCU_CR_DBG_TIM1_STOP)
+/**
+ * @brief  TIM1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM1()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM8_STOP)
+/**
+ * @brief  TIM8 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM8()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM9_STOP)
+/**
+ * @brief  TIM9 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM9()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM10_STOP)
+/**
+ * @brief  TIM10 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM10()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM11_STOP)
+/**
+ * @brief  TIM11 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM11()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM15_STOP)
+/**
+ * @brief  TIM15 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM15()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM16_STOP)
+/**
+ * @brief  TIM16 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM16()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM17_STOP)
+/**
+ * @brief  TIM17 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM17()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void              HAL_MspInit(void);
+void              HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions  ************************************************/
+void                HAL_IncTick(void);
+void                HAL_Delay(uint32_t Delay);
+uint32_t            HAL_GetTick(void);
+uint32_t            HAL_GetTickPrio(void);
+HAL_StatusTypeDef   HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void                HAL_SuspendTick(void);
+void                HAL_ResumeTick(void);
+uint32_t            HAL_GetHalVersion(void);
+uint32_t            HAL_GetREVID(void);
+uint32_t            HAL_GetDEVID(void);
+void                HAL_DBGMCU_EnableDBGSleepMode(void);
+void                HAL_DBGMCU_DisableDBGSleepMode(void);
+void                HAL_DBGMCU_EnableDBGStopMode(void);
+void                HAL_DBGMCU_DisableDBGStopMode(void);
+void                HAL_DBGMCU_EnableDBGStandbyMode(void);
+void                HAL_DBGMCU_DisableDBGStandbyMode(void);
+void                HAL_GetUID(uint32_t *UID);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h

@@ -0,0 +1,875 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_adc.h
+ * @author  MCD Application Team
+ * @brief   Header file containing functions prototypes of ADC HAL library.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_ADC_H
+#define __STM32F1xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief  Structure definition of ADC and regular group initialization
+ * @note   Parameters of this structure are shared within 2 scopes:
+ *          - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
+ *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
+ * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+ *         ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct {
+  uint32_t DataAlign;          /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
+                                    or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset
+                                  application): MSB on register bit 14 and LSB on register bit 3).          This parameter can be a value of @ref ADC_Data_align */
+  uint32_t ScanConvMode;       /*!< Configures the sequencer of regular and injected groups.
+                                    This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+                                    If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+                                                 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+                                    If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+                                                 Scan direction is upward: from rank1 to rank 'n'.
+                                    This parameter can be a value of @ref ADC_Scan_mode
+                                    Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
+                                          or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
+                                          the last conversion of the sequence. All previous conversions would be overwritten by the last one.
+                                          Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
+  uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+                                    after the selected trigger occurred (software start or external trigger).
+                                    This parameter can be set to ENABLE or DISABLE. */
+  uint32_t NbrOfConversion;    /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+                                    To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                    This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+  uint32_t
+      DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+                                  Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                  Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+                                  This parameter can be set to ENABLE or DISABLE. */
+  uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+                                     If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+  uint32_t ExternalTrigConv;    /*!< Selects the external event used to trigger the conversion start of regular group.
+                                     If set to ADC_SOFTWARE_START, external triggers are disabled.
+                                     If set to external trigger source, triggering is on event rising edge.
+                                     This parameter can be a value of @ref ADC_External_trigger_source_Regular */
+} ADC_InitTypeDef;
+
+/**
+ * @brief  Structure definition of ADC channel for regular group
+ * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ *         ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct {
+  uint32_t
+      Channel;           /*!< Specifies the channel to configure into ADC regular group.
+                              This parameter can be a value of @ref ADC_channels
+                              Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
+                              Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
+                              Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection
+                            trigger.      It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.      Refer to errata sheet of these devices for more details. */
+  uint32_t Rank;         /*!< Specifies the rank in the regular group sequencer
+                              This parameter can be a value of @ref ADC_regular_rank
+                              Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or
+                            parameter number of conversions can be adjusted) */
+  uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+                              Unit: ADC clock cycles
+                              Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
+                              This parameter can be a value of @ref ADC_sampling_times
+                              Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+                                       If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+                              Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
+                                    sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                    Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
+} ADC_ChannelConfTypeDef;
+
+/**
+ * @brief  ADC Configuration analog watchdog definition
+ * @note   The setting of these parameters with function is conditioned to ADC state.
+ *         ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
+ */
+typedef struct {
+  uint32_t WatchdogMode;   /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
+                                This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+  uint32_t Channel;        /*!< Selects which ADC channel to monitor by analog watchdog.
+                                This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
+                                This parameter can be a value of @ref ADC_channels. */
+  uint32_t ITMode;         /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
+                                This parameter can be set to ENABLE or DISABLE */
+  uint32_t HighThreshold;  /*!< Configures the ADC analog watchdog High threshold value.
+                                This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+  uint32_t LowThreshold;   /*!< Configures the ADC analog watchdog High threshold value.
+                                This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+  uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
+} ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief  HAL ADC state machine: ADC states definition (bitfields)
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET         0x00000000U /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY         0x00000001U /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT       0x00000004U /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG   0x00000020U /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA      0x00000040U /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY                                                                                                     \
+  0x00000100U                               /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, \
+                                                external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_REG_EOC   0x00000200U /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR   0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised  */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY                                                                                                          \
+  0x00001000U                               /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, \
+                                                external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_INJ_EOC   0x00002000U /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */
+
+/**
+ * @brief  ADC handle Structure definition
+ */
+typedef struct {
+  ADC_TypeDef *Instance; /*!< Register base address */
+
+  ADC_InitTypeDef Init; /*!< ADC required parameters */
+
+  DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+
+  HAL_LockTypeDef Lock; /*!< ADC locking object */
+
+  __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+
+  __IO uint32_t ErrorCode; /*!< ADC Error code */
+} ADC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE 0x00U /*!< No error                                              */
+#define HAL_ADC_ERROR_INTERNAL                                                      \
+  0x01U                         /*!< ADC IP internal error: if problem of clocking, \
+                                     enable/disable, erroneous state                       */
+#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error                                         */
+#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error                                    */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Data_align ADC data alignment
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT 0x00000000U
+#define ADC_DATAALIGN_LEFT  ((uint32_t)ADC_CR2_ALIGN)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Scan_mode ADC scan mode
+ * @{
+ */
+/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for     */
+/*       compatibility with other STM32 devices having a sequencer with       */
+/*       additional options.                                                  */
+#define ADC_SCAN_DISABLE 0x00000000U
+#define ADC_SCAN_ENABLE  ((uint32_t)ADC_CR1_SCAN)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE   0x00000000U
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels ADC channels
+ * @{
+ */
+/* Note: Depending on devices, some channels may not be available on package  */
+/*       pins. Refer to device datasheet for channels availability.           */
+#define ADC_CHANNEL_0  0x00000000U
+#define ADC_CHANNEL_1  ((uint32_t)(ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_2  ((uint32_t)(ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_3  ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_4  ((uint32_t)(ADC_SQR3_SQ1_2))
+#define ADC_CHANNEL_5  ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_6  ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_7  ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_8  ((uint32_t)(ADC_SQR3_SQ1_3))
+#define ADC_CHANNEL_9  ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
+#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
+
+#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
+#define ADC_CHANNEL_VREFINT    ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times ADC sampling times
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5    0x00000000U                                                          /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_7CYCLES_5   ((uint32_t)(ADC_SMPR2_SMP0_0))                                       /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_13CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_1))                                       /*!< Sampling time 13.5 ADC clock cycles */
+#define ADC_SAMPLETIME_28CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))                    /*!< Sampling time 28.5 ADC clock cycles */
+#define ADC_SAMPLETIME_41CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_2))                                       /*!< Sampling time 41.5 ADC clock cycles */
+#define ADC_SAMPLETIME_55CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0))                    /*!< Sampling time 55.5 ADC clock cycles */
+#define ADC_SAMPLETIME_71CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1))                    /*!< Sampling time 71.5 ADC clock cycles */
+#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank ADC rank into regular group
+ * @{
+ */
+#define ADC_REGULAR_RANK_1  0x00000001U
+#define ADC_REGULAR_RANK_2  0x00000002U
+#define ADC_REGULAR_RANK_3  0x00000003U
+#define ADC_REGULAR_RANK_4  0x00000004U
+#define ADC_REGULAR_RANK_5  0x00000005U
+#define ADC_REGULAR_RANK_6  0x00000006U
+#define ADC_REGULAR_RANK_7  0x00000007U
+#define ADC_REGULAR_RANK_8  0x00000008U
+#define ADC_REGULAR_RANK_9  0x00000009U
+#define ADC_REGULAR_RANK_10 0x0000000AU
+#define ADC_REGULAR_RANK_11 0x0000000BU
+#define ADC_REGULAR_RANK_12 0x0000000CU
+#define ADC_REGULAR_RANK_13 0x0000000DU
+#define ADC_REGULAR_RANK_14 0x0000000EU
+#define ADC_REGULAR_RANK_15 0x0000000FU
+#define ADC_REGULAR_RANK_16 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE            0x00000000U
+#define ADC_ANALOGWATCHDOG_SINGLE_REG      ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG         ((uint32_t)ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC       ((uint32_t)ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC    ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_conversion_group ADC conversion group
+ * @{
+ */
+#define ADC_REGULAR_GROUP          ((uint32_t)(ADC_FLAG_EOC))
+#define ADC_INJECTED_GROUP         ((uint32_t)(ADC_FLAG_JEOC))
+#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Event_type ADC Event type
+ * @{
+ */
+#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
+
+#define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+ * @{
+ */
+#define ADC_IT_EOC  ADC_CR1_EOCIE  /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IT_AWD  ADC_CR1_AWDIE  /*!< ADC Analog watchdog interrupt source */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+ * @{
+ */
+#define ADC_FLAG_STRT  ADC_SR_STRT  /*!< ADC Regular group start flag */
+#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
+#define ADC_FLAG_EOC   ADC_SR_EOC   /*!< ADC End of Regular conversion flag */
+#define ADC_FLAG_JEOC  ADC_SR_JEOC  /*!< ADC End of Injected conversion flag */
+#define ADC_FLAG_AWD   ADC_SR_AWD   /*!< ADC Analog watchdog flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/** @defgroup ADC_conversion_cycles ADC conversion cycles
+ * @{
+ */
+/* ADC conversion cycles (unit: ADC clock cycles)                           */
+/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
+/* resolution 12 bits)                                                      */
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5    14U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5   20U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5  26U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5  41U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5  54U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5  68U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5  84U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
+ * @{
+ */
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
+  (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
+  (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2)
+
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
+  (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
+  (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1)
+
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
+  (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
+  (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0)
+
+#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS    0x00000000U
+#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
+#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
+#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
+#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+
+#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS    0x00000000U
+#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
+#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
+#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
+#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+/**
+ * @}
+ */
+
+/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user.                                                                */
+
+/**
+ * @brief Enable the ADC peripheral
+ * @note ADC enable requires a delay for ADC stabilization time
+ *       (refer to device datasheet, parameter tSTAB)
+ * @note On STM32F1, if ADC is already enabled this macro trigs a conversion
+ *       SW start on regular group.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
+
+/**
+ * @brief Disable the ADC peripheral
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
+
+/** @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ *          This parameter can be any combination of the following values:
+ *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ *          This parameter can be any combination of the following values:
+ *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC interrupt source to check
+ *          This parameter can be any combination of the following values:
+ *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ *          This parameter can be any combination of the following values:
+ *            @arg ADC_FLAG_STRT: ADC Regular group start flag
+ *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
+ *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
+ *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the ADC's pending flags
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ *          This parameter can be any combination of the following values:
+ *            @arg ADC_FLAG_STRT: ADC Regular group start flag
+ *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
+ *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
+ *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @retval None
+ */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
+
+/** @brief  Reset ADC handle state
+ * @param  __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Private macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+ * @brief Verification of ADC state: enabled or disabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON)) ? SET : RESET)
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ *        or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ *        or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
+
+/**
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ *        the first parameter is the ADC handle State, the second parameter is the
+ *        bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Set ADC number of conversions into regular channel sequence length.
+ * @param _NbrOfConversion_: Regular channel sequence length
+ * @retval None
+ */
+#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 10 and 18.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_)-10)))
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 0 and 9.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 1 and 6.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_)-1)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 7 and 12.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_)-7)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 13 and 16.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_)-13)))
+
+/**
+ * @brief Set the injected sequence length.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_)-1) << ADC_JSQR_JL_Pos)
+
+/**
+ * @brief Set the selected injected channel rank
+ *        Note: on STM32F1 devices, channel rank position in JSQR register
+ *              is depending on total number of ranks selected into
+ *              injected sequencer (ranks sequence starting from 4-JL)
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_: Continuous mode.
+ * @retval None
+ */
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
+
+/**
+ * @brief Configures the number of discontinuous conversions for the regular group channels.
+ * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_)-1) << ADC_CR1_DISCNUM_Pos)
+
+/**
+ * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
+ * @param _SCAN_MODE_: Scan conversion mode.
+ * @retval None
+ */
+/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter   */
+/*       is equivalent to ADC_SCAN_ENABLE.                                    */
+#define ADC_CR1_SCAN_SET(_SCAN_MODE_) ((((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)) ? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE))
+
+/**
+ * @brief Get the maximum ADC conversion cycles on all channels.
+ * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
+ * Approximation of sampling time within 4 ranges, returns the highest value:
+ *   below 7.5 cycles {1.5 cycle; 7.5 cycles},
+ *   between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
+ *   between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
+ *   equal to 239.5 cycles
+ * Unit: ADC clock cycles
+ * @param __HANDLE__: ADC handle
+ * @retval ADC conversion cycles on all channels
+ */
+#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                                                                                                            \
+  (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET))             \
+       ?                                                                                                                                                                                \
+                                                                                                                                                                                        \
+       (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET))        \
+            ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5                                                                                                                             \
+            : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5)                                                                                                                           \
+       : ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET))     \
+           || ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) \
+              ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5                                                                                                                          \
+              : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5))
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT))
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || ((SCAN_MODE) == ADC_SCAN_ENABLE))
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING))
+
+#define IS_ADC_CHANNEL(CHANNEL)                                                                                                                                                                      \
+  (((CHANNEL) == ADC_CHANNEL_0) || ((CHANNEL) == ADC_CHANNEL_1) || ((CHANNEL) == ADC_CHANNEL_2) || ((CHANNEL) == ADC_CHANNEL_3) || ((CHANNEL) == ADC_CHANNEL_4) || ((CHANNEL) == ADC_CHANNEL_5)      \
+   || ((CHANNEL) == ADC_CHANNEL_6) || ((CHANNEL) == ADC_CHANNEL_7) || ((CHANNEL) == ADC_CHANNEL_8) || ((CHANNEL) == ADC_CHANNEL_9) || ((CHANNEL) == ADC_CHANNEL_10) || ((CHANNEL) == ADC_CHANNEL_11) \
+   || ((CHANNEL) == ADC_CHANNEL_12) || ((CHANNEL) == ADC_CHANNEL_13) || ((CHANNEL) == ADC_CHANNEL_14) || ((CHANNEL) == ADC_CHANNEL_15) || ((CHANNEL) == ADC_CHANNEL_16)                              \
+   || ((CHANNEL) == ADC_CHANNEL_17))
+
+#define IS_ADC_SAMPLE_TIME(TIME)                                                                                                                                 \
+  (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || ((TIME) == ADC_SAMPLETIME_28CYCLES_5) \
+   || ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
+
+#define IS_ADC_REGULAR_RANK(CHANNEL)                                                                                                                                                             \
+  (((CHANNEL) == ADC_REGULAR_RANK_1) || ((CHANNEL) == ADC_REGULAR_RANK_2) || ((CHANNEL) == ADC_REGULAR_RANK_3) || ((CHANNEL) == ADC_REGULAR_RANK_4) || ((CHANNEL) == ADC_REGULAR_RANK_5)         \
+   || ((CHANNEL) == ADC_REGULAR_RANK_6) || ((CHANNEL) == ADC_REGULAR_RANK_7) || ((CHANNEL) == ADC_REGULAR_RANK_8) || ((CHANNEL) == ADC_REGULAR_RANK_9) || ((CHANNEL) == ADC_REGULAR_RANK_10)     \
+   || ((CHANNEL) == ADC_REGULAR_RANK_11) || ((CHANNEL) == ADC_REGULAR_RANK_12) || ((CHANNEL) == ADC_REGULAR_RANK_13) || ((CHANNEL) == ADC_REGULAR_RANK_14) || ((CHANNEL) == ADC_REGULAR_RANK_15) \
+   || ((CHANNEL) == ADC_REGULAR_RANK_16))
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)                                                                                                                                                        \
+  (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \
+   || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC))
+
+#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || ((CONVERSION) == ADC_INJECTED_GROUP) || ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP))
+
+#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
+
+/** @defgroup ADC_range_verification ADC range verification
+ * For a unique ADC resolution: 12 bits
+ * @{
+ */
+#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
+ * @{
+ */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
+ * @{
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include ADC HAL Extension module */
+#include "stm32f1xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void              HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void              HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/* IO operation functions  *****************************************************/
+
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @{
+ */
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+/** @addtogroup ADC_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
+/**
+ * @}
+ */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Internal HAL driver functions **********************************************/
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef *hadc);
+void              ADC_StabilizationTime(uint32_t DelayUs);
+void              ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void              ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void              ADC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h

@@ -0,0 +1,623 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_adc_ex.h
+ * @author  MCD Application Team
+ * @brief   Header file of ADC HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_ADC_EX_H
+#define __STM32F1xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief  ADC Configuration injected Channel structure definition
+ * @note   Parameters of this structure are shared within 2 scopes:
+ *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
+ *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+ *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+ * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ *         ADC state can be either:
+ *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
+ *          - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
+ */
+typedef struct {
+  uint32_t InjectedChannel;         /*!< Selection of ADC channel to configure
+                                         This parameter can be a value of @ref ADC_channels
+                                         Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
+                                         Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
+                                         Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with
+                                       injection         trigger.              It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.              Refer to
+                                       errata         sheet of these devices for more details. */
+  uint32_t InjectedRank;            /*!< Rank in the injected group sequencer
+                                         This parameter must be a value of @ref ADCEx_injected_rank
+                                         Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel
+                                       setting (or parameter number of conversions can be adjusted) */
+  uint32_t InjectedSamplingTime;    /*!< Sampling time value to be set for the selected channel.
+                                         Unit: ADC clock cycles
+                                         Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
+                                         This parameter can be a value of @ref ADC_sampling_times
+                                         Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+                                                  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+                                         Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
+                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
+  uint32_t InjectedOffset;          /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+                                         Offset value must be a positive number.
+                                         Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+                                         this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+  uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+                                         To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                  configure a channel on injected group can impact the configuration of other channels previously set. */
+  uint32_t
+      InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive
+                                        parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous
+                                        mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE
+                                        or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group.
+                                        Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */
+  uint32_t AutoInjectedConv;         /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+                                          This parameter can be set to ENABLE or DISABLE.
+                                          Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+                                          Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+                                          Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+                                                To maintain JAUTO always enabled, DMA must be configured in circular mode.
+                                          Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
+  uint32_t ExternalTrigInjecConv;    /*!< Selects the external event used to trigger the conversion start of injected group.
+                                          If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+                                          If set to external trigger source, triggering is on event rising edge.
+                                          This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
+                                          Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+                                                If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on
+                                        the fly)    Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
+} ADC_InjectionConfTypeDef;
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+ * @brief  Structure definition of ADC multimode
+ * @note   The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
+ *         State of ADCs of the common group must be: disabled.
+ */
+typedef struct {
+  uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
+                      This parameter can be a value of @ref ADCEx_Common_mode
+                      Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any
+                    configuration change. Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1
+                    and ADC2. Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC
+                    clock cycles for slow interleaved mode. Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration
+                    structure can have additional parameters). The equivalences are:
+                              - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several
+                    ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
+                              - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32
+                    devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
+
+} ADC_MultiModeTypeDef;
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 0x00000001U
+#define ADC_INJECTED_RANK_2 0x00000002U
+#define ADC_INJECTED_RANK_3 0x00000003U
+#define ADC_INJECTED_RANK_4 0x00000004U
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE   0x00000000U
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
+ * @{
+ */
+/*!< List of external triggers with generic trigger name, independently of    */
+/* ADC target, sorted by trigger name:                                        */
+
+/*!< External triggers of regular group for ADC1&ADC2 only */
+#define ADC_EXTERNALTRIGCONV_T1_CC1   ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2   ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T2_CC2   ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T3_TRGO  ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_CC4   ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+/*!< External triggers of regular group for ADC3 only */
+#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3
+#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1
+#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1
+#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3
+#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1
+#endif /* STM32F103xE || defined STM32F103xG */
+
+/*!< External triggers of regular group for all ADC instances */
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and   */
+/*         XL-density devices.                                                */
+/*         To use it on ADC or ADC2, a remap of trigger must be done from     */
+/*         EXTI line 11 to TIM8_TRGO with macro:                              */
+/*           __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()                           */
+/*           __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()                           */
+
+/* Note for internal constant value management: If TIM8_TRGO is available,    */
+/* its definition is set to value for ADC1&ADC2 by default and changed to     */
+/* value for ADC3 by HAL ADC driver if ADC3 is selected.                      */
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
+#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#define ADC_SOFTWARE_START ADC1_2_3_SWSTART
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
+ * @{
+ */
+/*!< List of external triggers with generic trigger name, independently of    */
+/* ADC target, sorted by trigger name:                                        */
+
+/*!< External triggers of injected group for ADC1&ADC2 only */
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO  ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1   ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4   ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO  ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+/*!< External triggers of injected group for ADC3 only */
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC3  ADC3_EXTERNALTRIGINJEC_T4_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC2  ADC3_EXTERNALTRIGINJEC_T8_CC2
+#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T5_CC4  ADC3_EXTERNALTRIGINJEC_T5_CC4
+#endif /* STM32F103xE || defined STM32F103xG */
+
+/*!< External triggers of injected group for all ADC instances */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4  ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and    */
+/*         XL-density devices.                                                */
+/*         To use it on ADC1 or ADC2, a remap of trigger must be done from    */
+/*         EXTI line 11 to TIM8_CC4 with macro:                               */
+/*           __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()                           */
+/*           __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()                           */
+
+/* Note for internal constant value management: If TIM8_CC4 is available,     */
+/* its definition is set to value for ADC1&ADC2 by default and changed to     */
+/* value for ADC3 by HAL ADC driver if ADC3 is selected.                      */
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
+#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
+/**
+ * @}
+ */
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT               0x00000000U                     /*!< ADC dual mode disabled (ADC independent mode) */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG   ((uint32_t)(ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
+#define ADC_DUALMODE_INJECSIMULT_INTERLFAST                                                                                                                                                          \
+  ((uint32_t)(ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling \
+                                                         phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW                                                                                                                                                           \
+  ((uint32_t)(ADC_CR1_DUALMOD_2)) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock \
+                                     cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
+#define ADC_DUALMODE_REGSIMULT   ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
+#define ADC_DUALMODE_INTERLFAST                                                                                                                                                                      \
+  ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles \
+                                                                             (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INTERLSLOW                                                                                                                                                        \
+  ((uint32_t)(ADC_CR1_DUALMOD_3)) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter \
+                                     "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
+/**
+ * @}
+ */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
+ * @{
+ */
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
+ * @{
+ */
+/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC    */
+/* instance is available on the selected device).                             */
+/* (used internally by HAL driver. To not use into HAL structure parameters)  */
+
+/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
+#define ADC1_2_EXTERNALTRIG_T1_CC1   0x00000000U
+#define ADC1_2_EXTERNALTRIG_T1_CC2   ((uint32_t)(ADC_CR2_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T2_CC2   ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_TRGO  ((uint32_t)(ADC_CR2_EXTSEL_2))
+#define ADC1_2_EXTERNALTRIG_T4_CC4   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG)
+/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and     */
+/* XL-density devices.                                                        */
+#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
+#endif
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+/* External triggers of regular group for ADC3 */
+#define ADC3_EXTERNALTRIG_T3_CC1  ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC3_EXTERNALTRIG_T2_CC3  ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC3_EXTERNALTRIG_T8_CC1  ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC3_EXTERNALTRIG_T5_CC1  ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC3_EXTERNALTRIG_T5_CC3  ADC1_2_EXTERNALTRIG_EXT_IT11
+#endif
+
+/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
+#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)(ADC_CR2_EXTSEL_1))
+#define ADC1_2_3_SWSTART             ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
+ * @{
+ */
+/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC    */
+/* instance is available on the selected device).                             */
+/* (used internally by HAL driver. To not use into HAL structure parameters)  */
+
+/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO  ((uint32_t)(ADC_CR2_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1   ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4   ((uint32_t)(ADC_CR2_JEXTSEL_2))
+#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO  ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG)
+/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and      */
+/* XL-density devices.                                                        */
+#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+#endif
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+/* External triggers of injected group for ADC3 */
+#define ADC3_EXTERNALTRIGINJEC_T4_CC3  ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC3_EXTERNALTRIGINJEC_T8_CC2  ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC3_EXTERNALTRIGINJEC_T8_CC4  ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC3_EXTERNALTRIGINJEC_T5_CC4  ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+#endif /* STM32F103xE || defined STM32F103xG */
+
+/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
+#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
+#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4  ((uint32_t)(ADC_CR2_JEXTSEL_0))
+#define ADC1_2_3_JSWSTART                  ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+ * @brief For devices with 3 ADCs: Defines the external trigger source
+ *        for regular group according to ADC into common group ADC1&ADC2 or
+ *        ADC3 (some triggers with same source have different value to
+ *        be programmed into ADC EXTSEL bits of CR2 register).
+ *        For devices with 2 ADCs or less: this macro makes no change.
+ * @param __HANDLE__: ADC handle
+ * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
+ * @retval External trigger to be programmed into EXTSEL bits of CR2 register
+ */
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
+  (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO) ? (ADC3_EXTERNALTRIG_T8_TRGO) : (__EXT_TRIG_CONV__)) : (__EXT_TRIG_CONV__))
+#else
+#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) (__EXT_TRIG_CONV__)
+#endif /* STM32F103xE || STM32F103xG */
+
+/**
+ * @brief For devices with 3 ADCs: Defines the external trigger source
+ *        for injected group according to ADC into common group ADC1&ADC2 or
+ *        ADC3 (some triggers with same source have different value to
+ *        be programmed into ADC JEXTSEL bits of CR2 register).
+ *        For devices with 2 ADCs or less: this macro makes no change.
+ * @param __HANDLE__: ADC handle
+ * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
+ * @retval External trigger to be programmed into JEXTSEL bits of CR2 register
+ */
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
+  (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) ? (ADC3_EXTERNALTRIGINJEC_T8_CC4) : (__EXT_TRIG_INJECTCONV__)) : (__EXT_TRIG_INJECTCONV__))
+#else
+#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) (__EXT_TRIG_INJECTCONV__)
+#endif /* STM32F103xE || STM32F103xG */
+
+/**
+ * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
+ */
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_DUALMOD) : (RESET))
+#else
+#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (RESET)
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (((((__HANDLE__)->Instance) == ADC2)) ? ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) : (!RESET))
+#else
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (!RESET)
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_JAUTO) : (RESET))
+#else
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (RESET)
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+ * @brief Set handle of the other ADC sharing the common multimode settings
+ * @param __HANDLE__: ADC handle
+ * @param __HANDLE_OTHER_ADC__: other ADC handle
+ * @retval None
+ */
+#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
+
+/**
+ * @brief Set handle of the ADC slave associated to the ADC master
+ * On STM32F1 devices, ADC slave is always ADC2 (this can be different
+ * on other STM32 devices)
+ * @param __HANDLE_MASTER__: ADC master handle
+ * @param __HANDLE_SLAVE__: ADC slave handle
+ * @retval None
+ */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ((__HANDLE_SLAVE__)->Instance = ADC2)
+
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || ((CHANNEL) == ADC_INJECTED_RANK_2) || ((CHANNEL) == ADC_INJECTED_RANK_3) || ((CHANNEL) == ADC_INJECTED_RANK_4))
+
+#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
+
+/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
+ * @{
+ */
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
+/**
+ * @}
+ */
+
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
+    || defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
+#endif
+#if defined(STM32F101xE)
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
+#endif
+#if defined(STM32F101xG)
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
+#endif
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                              \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)     \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)   \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
+#endif
+
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
+    || defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
+#endif
+#if defined(STM32F101xE)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
+#endif
+#if defined(STM32F101xG)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
+#endif
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)   \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)   \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
+#endif
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define IS_ADC_MODE(MODE)                                                                                                                                                                \
+  (((MODE) == ADC_MODE_INDEPENDENT) || ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) \
+   || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || ((MODE) == ADC_DUALMODE_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT) || ((MODE) == ADC_DUALMODE_INTERLFAST)               \
+   || ((MODE) == ADC_DUALMODE_INTERLSLOW) || ((MODE) == ADC_DUALMODE_ALTERTRIG))
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* ADC calibration */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+/** @addtogroup ADCEx_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected);
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_ADC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h

@@ -0,0 +1,388 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_cortex.h
+ * @author  MCD Application Team
+ * @brief   Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CORTEX_H
+#define __STM32F1xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1U)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @brief  MPU Region initialization structure
+ * @{
+ */
+typedef struct {
+  uint8_t Enable;           /*!< Specifies the status of the region.
+                                 This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t Number;           /*!< Specifies the number of the region to protect.
+                                 This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t BaseAddress;     /*!< Specifies the base address of the region to protect.                           */
+  uint8_t  Size;            /*!< Specifies the size of the region to protect.
+                                 This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
+  uint8_t TypeExtField;     /*!< Specifies the TEX field level.
+                                 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
+  uint8_t AccessPermission; /*!< Specifies the region access permission type.
+                                 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t DisableExec;      /*!< Specifies the instruction access status.
+                                 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t IsShareable;      /*!< Specifies the shareability status of the protected region.
+                                 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t IsCacheable;      /*!< Specifies the cacheable status of the region protected.
+                                 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t IsBufferable;     /*!< Specifies the bufferable status of the protected region.
+                                 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+} MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+#define NVIC_PRIORITYGROUP_0                       \
+  0x00000007U /*!< 0 bits for pre-emption priority \
+                   4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1                       \
+  0x00000006U /*!< 1 bits for pre-emption priority \
+                   3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2                       \
+  0x00000005U /*!< 2 bits for pre-emption priority \
+                   2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3                       \
+  0x00000004U /*!< 3 bits for pre-emption priority \
+                   1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4                       \
+  0x00000003U /*!< 4 bits for pre-emption priority \
+                   0 bits for subpriority */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK      0x00000004U
+
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
+#define MPU_HARDFAULT_NMI      MPU_CTRL_HFNMIENA_Msk
+#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
+#define MPU_HFNMI_PRIVDEF      (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE  ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE  ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE     ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE     ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE     ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B   ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B   ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B  ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B  ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B  ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB   ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB   ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB   ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB   ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB  ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB  ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB  ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB   ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB   ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB   ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB   ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB  ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB  ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB  ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB   ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB   ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB   ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS   ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW     ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO     ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void     HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void     HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void     HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void     HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void     HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void     HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void     HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void     HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void     HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void     HAL_SYSTICK_IRQHandler(void);
+void     HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) \
+  (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1U)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)                                                                                                                                    \
+  (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) \
+   || ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)                                                                                                                                                \
+  (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) \
+   || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)                                                                                                                                                          \
+  (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B)         \
+   || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB)        \
+   || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) \
+   || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB)        \
+   || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) \
+   || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h

@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_def.h
+ * @author  MCD Application Team
+ * @brief   This file contains HAL common defines, enumeration, macros and
+ *          structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DEF
+#define __STM32F1xx_HAL_DEF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+#if defined(USE_HAL_LEGACY)
+#include "Legacy/stm32_hal_legacy.h"
+#endif
+#include <stdio.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief  HAL Status structures definition
+ */
+typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef;
+
+/**
+ * @brief  HAL Lock structures definition
+ */
+typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#define HAL_MAX_DELAY 0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+  do {                                                               \
+    (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__);             \
+    (__DMA_HANDLE__).Parent         = (__HANDLE__);                  \
+  } while (0U)
+
+#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__: specifies the Peripheral Handle.
+ * @note  This macro can be used for the following purpose:
+ *          - When the Handle is declared as local variable; before passing it as parameter
+ *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ *            to set to 0 the Handle's "State" field.
+ *            Otherwise, "State" field may have any random value and the first time the function
+ *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ *            (i.e. HAL_PPP_MspInit() will not be executed).
+ *          - When there is a need to reconfigure the low level hardware: instead of calling
+ *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1U)
+/* Reserved for future use */
+#error "USE_RTOS should be 0 in the current HAL release"
+#else
+#define __HAL_LOCK(__HANDLE__)              \
+  do {                                      \
+    if ((__HANDLE__)->Lock == HAL_LOCKED) { \
+      return HAL_BUSY;                      \
+    } else {                                \
+      (__HANDLE__)->Lock = HAL_LOCKED;      \
+    }                                       \
+  } while (0U)
+
+#define __HAL_UNLOCK(__HANDLE__)       \
+  do {                                 \
+    (__HANDLE__)->Lock = HAL_UNLOCKED; \
+  } while (0U)
+#endif /* USE_RTOS */
+
+#if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__((aligned(4)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined(__CC_ARM) /* ARM Compiler */
+#define __ALIGN_BEGIN __align(4)
+#elif defined(__ICCARM__) /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief  __RAM_FUNC definition
+ */
+#if defined(__CC_ARM)
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined(__ICCARM__)
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined(__GNUC__)
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+/**
+ * @brief  __NOINLINE definition
+ */
+#if defined(__CC_ARM) || defined(__GNUC__)
+/* ARM & GNUCompiler
+   ----------------
+*/
+#define __NOINLINE __attribute__((noinline))
+
+#elif defined(__ICCARM__)
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F1xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h

@@ -0,0 +1,453 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_dma.h
+ * @author  MCD Application Team
+ * @brief   Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DMA_H
+#define __STM32F1xx_HAL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief  DMA Configuration Structure definition
+ */
+typedef struct {
+  uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+                           from memory to memory or from peripheral to memory.
+                           This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+  uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+  uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+                        This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+  uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+                                     This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+  uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+                                  This parameter can be a value of @ref DMA_Memory_data_size */
+
+  uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+                      This parameter can be a value of @ref DMA_mode
+                      @note The circular buffer mode cannot be used if the memory-to-memory
+                            data transfer is configured on the selected Channel */
+
+  uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+                          This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+ * @brief  HAL DMA State structures definition
+ */
+typedef enum {
+  HAL_DMA_STATE_RESET   = 0x00U, /*!< DMA not yet initialized or disabled    */
+  HAL_DMA_STATE_READY   = 0x01U, /*!< DMA initialized and ready for use      */
+  HAL_DMA_STATE_BUSY    = 0x02U, /*!< DMA process is ongoing                 */
+  HAL_DMA_STATE_TIMEOUT = 0x03U  /*!< DMA timeout state                      */
+} HAL_DMA_StateTypeDef;
+
+/**
+ * @brief  HAL DMA Error Code structure definition
+ */
+typedef enum {
+  HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER = 0x01U  /*!< Half Transfer     */
+} HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief  HAL DMA Callback ID structure definition
+ */
+typedef enum {
+  HAL_DMA_XFER_CPLT_CB_ID     = 0x00U, /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer     */
+  HAL_DMA_XFER_ERROR_CB_ID    = 0x02U, /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID    = 0x03U, /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID      = 0x04U  /*!< All               */
+
+} HAL_DMA_CallbackIDTypeDef;
+
+/**
+ * @brief  DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef {
+  DMA_Channel_TypeDef *Instance; /*!< Register base address                  */
+
+  DMA_InitTypeDef Init; /*!< DMA communication parameters           */
+
+  HAL_LockTypeDef Lock; /*!< DMA locking object                     */
+
+  HAL_DMA_StateTypeDef State; /*!< DMA transfer state                     */
+
+  void *Parent; /*!< Parent object state                    */
+
+  void (*XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback         */
+
+  void (*XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback    */
+
+  void (*XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback            */
+
+  void (*XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback            */
+
+  __IO uint32_t ErrorCode; /*!< DMA Error code                         */
+
+  DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address               */
+
+  uint32_t ChannelIndex; /*!< DMA Channel Index                      */
+
+} DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE          0x00000000U /*!< No error             */
+#define HAL_DMA_ERROR_TE            0x00000001U /*!< Transfer error       */
+#define HAL_DMA_ERROR_NO_XFER       0x00000004U /*!< no ongoing transfer  */
+#define HAL_DMA_ERROR_TIMEOUT       0x00000020U /*!< Timeout error        */
+#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode                    */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY 0x00000000U                 /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE  ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE 0x00000000U              /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE  ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable  */
+#define DMA_MINC_DISABLE 0x00000000U              /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE     0x00000000U                 /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD     ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word     */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE     0x00000000U                 /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD     ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word     */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode DMA mode
+ * @{
+ */
+#define DMA_NORMAL   0x00000000U              /*!< Normal mode                  */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode                */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @{
+ */
+#define DMA_PRIORITY_LOW       0x00000000U              /*!< Priority level : Low       */
+#define DMA_PRIORITY_MEDIUM    ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium    */
+#define DMA_PRIORITY_HIGH      ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High      */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)   /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @{
+ */
+#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @{
+ */
+#define DMA_FLAG_GL1 0x00000001U
+#define DMA_FLAG_TC1 0x00000002U
+#define DMA_FLAG_HT1 0x00000004U
+#define DMA_FLAG_TE1 0x00000008U
+#define DMA_FLAG_GL2 0x00000010U
+#define DMA_FLAG_TC2 0x00000020U
+#define DMA_FLAG_HT2 0x00000040U
+#define DMA_FLAG_TE2 0x00000080U
+#define DMA_FLAG_GL3 0x00000100U
+#define DMA_FLAG_TC3 0x00000200U
+#define DMA_FLAG_HT3 0x00000400U
+#define DMA_FLAG_TE3 0x00000800U
+#define DMA_FLAG_GL4 0x00001000U
+#define DMA_FLAG_TC4 0x00002000U
+#define DMA_FLAG_HT4 0x00004000U
+#define DMA_FLAG_TE4 0x00008000U
+#define DMA_FLAG_GL5 0x00010000U
+#define DMA_FLAG_TC5 0x00020000U
+#define DMA_FLAG_HT5 0x00040000U
+#define DMA_FLAG_TE5 0x00080000U
+#define DMA_FLAG_GL6 0x00100000U
+#define DMA_FLAG_TC6 0x00200000U
+#define DMA_FLAG_HT6 0x00400000U
+#define DMA_FLAG_TE6 0x00800000U
+#define DMA_FLAG_GL7 0x01000000U
+#define DMA_FLAG_TC7 0x02000000U
+#define DMA_FLAG_HT7 0x04000000U
+#define DMA_FLAG_TE7 0x08000000U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @brief  Reset DMA handle state.
+ * @param  __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief  Enable the specified DMA Channel.
+ * @param  __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+/**
+ * @brief  Disable the specified DMA Channel.
+ * @param  __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief  Enables the specified DMA Channel interrupts.
+ * @param  __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+ *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+ *            @arg DMA_IT_TE:  Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+
+/**
+ * @brief  Disable the specified DMA Channel interrupts.
+ * @param  __HANDLE__: DMA handle
+ * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+ *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+ *            @arg DMA_IT_TE:  Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+
+/**
+ * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
+ * @param  __HANDLE__: DMA handle
+ * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+ *          This parameter can be one of the following values:
+ *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+ *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+ *            @arg DMA_IT_TE:  Transfer error interrupt mask
+ * @retval The state of DMA_IT (SET or RESET).
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief  Return the number of remaining data units in the current DMA Channel transfer.
+ * @param  __HANDLE__: DMA handle
+ * @retval The number of remaining data units in the current DMA Channel transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+ * @}
+ */
+
+/* Include DMA HAL Extension module */
+#include "stm32f1xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @{
+ */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h

@@ -0,0 +1,336 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_dma_ex.h
+ * @author  MCD Application Team
+ * @brief   Header file of DMA HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DMA_EX_H
+#define __STM32F1xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMAEx DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
+ * @{
+ */
+/* Interrupt & Flag management */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
+ * @{
+ */
+
+/**
+ * @brief  Returns the current DMA Channel transfer complete flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)                                                                            \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
+       ? DMA_FLAG_TC1                                                                                                      \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
+             ? DMA_FLAG_TC2                                                                                                \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
+                   ? DMA_FLAG_TC3                                                                                          \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
+                         ? DMA_FLAG_TC4                                                                                    \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
+                               ? DMA_FLAG_TC5                                                                              \
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
+                                     ? DMA_FLAG_TC6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_TC7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_TC1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_TC2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_TC3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 : DMA_FLAG_TC5)
+
+/**
+ * @brief  Returns the current DMA Channel half transfer complete flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)                                                                            \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
+       ? DMA_FLAG_HT1                                                                                                      \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
+             ? DMA_FLAG_HT2                                                                                                \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
+                   ? DMA_FLAG_HT3                                                                                          \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
+                         ? DMA_FLAG_HT4                                                                                    \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
+                               ? DMA_FLAG_HT5                                                                              \
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
+                                     ? DMA_FLAG_HT6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_HT7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_HT1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_HT2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_HT3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 : DMA_FLAG_HT5)
+
+/**
+ * @brief  Returns the current DMA Channel transfer error flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)                                                                            \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
+       ? DMA_FLAG_TE1                                                                                                      \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
+             ? DMA_FLAG_TE2                                                                                                \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
+                   ? DMA_FLAG_TE3                                                                                          \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
+                         ? DMA_FLAG_TE4                                                                                    \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
+                               ? DMA_FLAG_TE5                                                                              \
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
+                                     ? DMA_FLAG_TE6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_TE7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_TE1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_TE2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_TE3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 : DMA_FLAG_TE5)
+
+/**
+ * @brief  Return the current DMA Channel Global interrupt flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)                                                                            \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
+       ? DMA_FLAG_GL1                                                                                                      \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
+             ? DMA_FLAG_GL2                                                                                                \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
+                   ? DMA_FLAG_GL3                                                                                          \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
+                         ? DMA_FLAG_GL4                                                                                    \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
+                               ? DMA_FLAG_GL5                                                                              \
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
+                                     ? DMA_FLAG_GL6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_GL7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_GL1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_GL2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_GL3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 : DMA_FLAG_GL5)
+
+/**
+ * @brief  Get the DMA Channel pending flags.
+ * @param  __HANDLE__: DMA handle
+ * @param  __FLAG__: Get the specified flag.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_FLAG_TCx:  Transfer complete flag
+ *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+ *            @arg DMA_FLAG_TEx:  Transfer error flag
+ *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
+
+/**
+ * @brief  Clears the DMA Channel pending flags.
+ * @param  __HANDLE__: DMA handle
+ * @param  __FLAG__: specifies the flag to clear.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_FLAG_TCx:  Transfer complete flag
+ *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+ *            @arg DMA_FLAG_TEx:  Transfer error flag
+ *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
+
+/**
+ * @}
+ */
+
+#else
+/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
+ * @{
+ */
+
+/**
+ * @brief  Returns the current DMA Channel transfer complete flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)                                                             \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
+       ? DMA_FLAG_TC1                                                                                       \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
+             ? DMA_FLAG_TC2                                                                                 \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
+                   ? DMA_FLAG_TC3                                                                           \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_TC4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 : DMA_FLAG_TC7)
+
+/**
+ * @brief  Return the current DMA Channel half transfer complete flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)                                                             \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
+       ? DMA_FLAG_HT1                                                                                       \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
+             ? DMA_FLAG_HT2                                                                                 \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
+                   ? DMA_FLAG_HT3                                                                           \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_HT4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 : DMA_FLAG_HT7)
+
+/**
+ * @brief  Return the current DMA Channel transfer error flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)                                                             \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
+       ? DMA_FLAG_TE1                                                                                       \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
+             ? DMA_FLAG_TE2                                                                                 \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
+                   ? DMA_FLAG_TE3                                                                           \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_TE4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 : DMA_FLAG_TE7)
+
+/**
+ * @brief  Return the current DMA Channel Global interrupt flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)                                                             \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
+       ? DMA_FLAG_GL1                                                                                       \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
+             ? DMA_FLAG_GL2                                                                                 \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
+                   ? DMA_FLAG_GL3                                                                           \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_GL4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 : DMA_FLAG_GL7)
+
+/**
+ * @brief  Get the DMA Channel pending flags.
+ * @param  __HANDLE__: DMA handle
+ * @param  __FLAG__: Get the specified flag.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_FLAG_TCx:  Transfer complete flag
+ *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+ *            @arg DMA_FLAG_TEx:  Transfer error flag
+ *            @arg DMA_FLAG_GLx:  Global interrupt flag
+ *         Where x can be 1_7 to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
+
+/**
+ * @brief  Clear the DMA Channel pending flags.
+ * @param  __HANDLE__: DMA handle
+ * @param  __FLAG__: specifies the flag to clear.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_FLAG_TCx:  Transfer complete flag
+ *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+ *            @arg DMA_FLAG_TEx:  Transfer error flag
+ *            @arg DMA_FLAG_GLx:  Global interrupt flag
+ *         Where x can be 1_7 to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
+       /* STM32F103xG || STM32F105xC || STM32F107xC */
+
+#endif /* __STM32F1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h

@@ -0,0 +1,336 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_flash.h
+ * @author  MCD Application Team
+ * @brief   Header file of Flash HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_FLASH_H
+#define __STM32F1xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+
+#if defined(FLASH_ACR_LATENCY)
+#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1) || ((__LATENCY__) == FLASH_LATENCY_2))
+
+#else
+#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
+#endif /* FLASH_ACR_LATENCY */
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+/**
+ * @brief  FLASH Procedure structure definition
+ */
+typedef enum {
+  FLASH_PROC_NONE              = 0U,
+  FLASH_PROC_PAGEERASE         = 1U,
+  FLASH_PROC_MASSERASE         = 2U,
+  FLASH_PROC_PROGRAMHALFWORD   = 3U,
+  FLASH_PROC_PROGRAMWORD       = 4U,
+  FLASH_PROC_PROGRAMDOUBLEWORD = 5U
+} FLASH_ProcedureTypeDef;
+
+/**
+ * @brief  FLASH handle Structure definition
+ */
+typedef struct {
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+
+  __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
+
+  __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
+
+  __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
+
+  HAL_LockTypeDef Lock; /*!< FLASH locking object                */
+
+  __IO uint32_t ErrorCode; /*!< FLASH error code
+                                This parameter can be a value of @ref FLASH_Error_Codes  */
+} FLASH_ProcessTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Error_Codes FLASH Error Codes
+ * @{
+ */
+
+#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
+#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
+#define HAL_FLASH_ERROR_WRP  0x02U /*!< Write protection error */
+#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+ * @{
+ */
+#define FLASH_TYPEPROGRAM_HALFWORD   0x01U /*!<Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_WORD       0x02U /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/
+
+/**
+ * @}
+ */
+
+#if defined(FLASH_ACR_LATENCY)
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#define FLASH_LATENCY_0 0x00000000U         /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
+
+/**
+ * @}
+ */
+
+#else
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
+
+/**
+ * @}
+ */
+
+#endif /* FLASH_ACR_LATENCY */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ *  @brief macros to control FLASH features
+ *  @{
+ */
+
+/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
+ *  @brief macros to handle FLASH half cycle
+ * @{
+ */
+
+/**
+  * @brief  Enable the FLASH half cycle access.
+  * @note   half cycle access can only be used with a low-frequency clock of less than
+            8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
+  * @retval None
+  */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
+
+/**
+  * @brief  Disable the FLASH half cycle access.
+  * @note   half cycle access can only be used with a low-frequency clock of less than
+            8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
+  * @retval None
+  */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
+
+/**
+ * @}
+ */
+
+#if defined(FLASH_ACR_LATENCY)
+/** @defgroup FLASH_EM_Latency FLASH Latency
+ *  @brief macros to handle FLASH Latency
+ * @{
+ */
+
+/**
+ * @brief  Set the FLASH Latency.
+ * @param  __LATENCY__ FLASH Latency
+ *         The value of this parameter depend on device used within the same series
+ * @retval None
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__))
+
+/**
+ * @brief  Get the FLASH Latency.
+ * @retval FLASH Latency
+ *         The value of this parameter depend on device used within the same series
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+ * @}
+ */
+
+#endif /* FLASH_ACR_LATENCY */
+/** @defgroup FLASH_Prefetch FLASH Prefetch
+ *  @brief macros to handle FLASH Prefetch buffer
+ * @{
+ */
+/**
+ * @brief  Enable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
+
+/**
+ * @brief  Disable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extended module */
+#include "stm32f1xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+
+/* FLASH IRQ handler function */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+void              HAL_FLASH_OB_Launch(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_FLASH_GetError(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function -------------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+#if defined(FLASH_BANK2_END)
+HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
+#endif /* FLASH_BANK2_END */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h

@@ -0,0 +1,791 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_flash_ex.h
+ * @author  MCD Application Team
+ * @brief   Header file of Flash HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_FLASH_EX_H
+#define __STM32F1xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Private_Constants
+ * @{
+ */
+
+#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
+#define OBR_REG_INDEX            1U
+#define SR_FLAG_MASK             ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
+
+#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#if defined(FLASH_BANK2_END)
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+#endif /* FLASH_BANK2_END */
+
+/* Low Density */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                                  \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U)                      \
+       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU)        \
+       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U)               \
+              ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU) \
+              : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))))
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                           \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U)              \
+       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0807FFFFU) \
+       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0805FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU)))
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080FFFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080BFFFFU))
+#endif /* FLASH_BANK2_END */
+
+/* Connectivity Line */
+#if (defined(STM32F105xC) || defined(STM32F107xC))
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                           \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U)              \
+       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU) \
+       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU)))
+#endif /* STM32F105xC || STM32F107xC */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
+
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || ((BANK) == FLASH_BANK_BOTH))
+#else
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* FLASH_BANK2_END */
+
+/* Low Density */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
+
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                      \
+  (((ADDRESS) >= FLASH_BASE)                                                                   \
+   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U)                                    \
+           ? ((ADDRESS) <= FLASH_BANK1_END)                                                    \
+           : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS) <= 0x0800FFFF) \
+                                                                   : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
+
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                     \
+  (((ADDRESS) >= FLASH_BASE)                                                                  \
+   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS) <= FLASH_BANK1_END) \
+                                                             : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
+
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
+
+#endif /* FLASH_BANK2_END */
+
+/* Connectivity Line */
+#if (defined(STM32F105xC) || defined(STM32F107xC))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                     \
+  (((ADDRESS) >= FLASH_BASE)                                                                  \
+   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS) <= FLASH_BANK1_END) \
+                                                             : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief  FLASH Erase structure definition
+ */
+typedef struct {
+  uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
+                           This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+  uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
+                       This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
+                             This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
+                             (x = 1 or 2 depending on devices)*/
+
+  uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
+                         This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief  FLASH Options bytes program structure definition
+ */
+typedef struct {
+  uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+                            This parameter can be a value of @ref FLASHEx_OB_Type */
+
+  uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+                          This parameter can be a value of @ref FLASHEx_OB_WRP_State */
+
+  uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
+                         This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
+
+  uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
+                       This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+                         This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
+
+#if defined(FLASH_BANK2_END)
+  uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+                           IWDG / STOP / STDBY / BOOT1
+                           This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
+                           @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
+#else
+  uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+                           IWDG / STOP / STDBY
+                           This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
+                           @ref FLASHEx_OB_nRST_STDBY */
+#endif /* FLASH_BANK2_END */
+
+  uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
+                             This parameter can be a value of @ref FLASHEx_OB_Data_Address */
+
+  uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
+                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Constants FLASH Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Page_Size Page Size
+ * @{
+ */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define FLASH_PAGE_SIZE 0x400U
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+       /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
+#define FLASH_PAGE_SIZE 0x800U
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+       /* STM32F101xG || STM32F103xG */
+       /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Type_Erase Type Erase
+ * @{
+ */
+#define FLASH_TYPEERASE_PAGES     0x00U /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE 0x02U /*!<Flash mass erase activation*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Banks Banks
+ * @{
+ */
+#if defined(FLASH_BANK2_END)
+#define FLASH_BANK_1    1U                                      /*!< Bank 1   */
+#define FLASH_BANK_2    2U                                      /*!< Bank 2   */
+#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+
+#else
+#define FLASH_BANK_1 1U /*!< Bank 1   */
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_OB_Type Option Bytes Type
+ * @{
+ */
+#define OPTIONBYTE_WRP  0x01U /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP  0x02U /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER 0x04U /*!<USER option byte configuration*/
+#define OPTIONBYTE_DATA 0x08U /*!<DATA option byte configuration*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
+ * @{
+ */
+#define OB_WRPSTATE_DISABLE 0x00U /*!<Disable the write protection of the desired pages*/
+#define OB_WRPSTATE_ENABLE  0x01U /*!<Enable the write protection of the desired pagess*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
+ * @{
+ */
+/* STM32 Low and Medium density devices */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES0TO3   0x00000001U /*!< Write protection of page 0 to 3 */
+#define OB_WRP_PAGES4TO7   0x00000002U /*!< Write protection of page 4 to 7 */
+#define OB_WRP_PAGES8TO11  0x00000004U /*!< Write protection of page 8 to 11 */
+#define OB_WRP_PAGES12TO15 0x00000008U /*!< Write protection of page 12 to 15 */
+#define OB_WRP_PAGES16TO19 0x00000010U /*!< Write protection of page 16 to 19 */
+#define OB_WRP_PAGES20TO23 0x00000020U /*!< Write protection of page 20 to 23 */
+#define OB_WRP_PAGES24TO27 0x00000040U /*!< Write protection of page 24 to 27 */
+#define OB_WRP_PAGES28TO31 0x00000080U /*!< Write protection of page 28 to 31 */
+#endif                                 /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+                                       /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+/* STM32 Medium-density devices */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES32TO35   0x00000100U /*!< Write protection of page 32 to 35 */
+#define OB_WRP_PAGES36TO39   0x00000200U /*!< Write protection of page 36 to 39 */
+#define OB_WRP_PAGES40TO43   0x00000400U /*!< Write protection of page 40 to 43 */
+#define OB_WRP_PAGES44TO47   0x00000800U /*!< Write protection of page 44 to 47 */
+#define OB_WRP_PAGES48TO51   0x00001000U /*!< Write protection of page 48 to 51 */
+#define OB_WRP_PAGES52TO55   0x00002000U /*!< Write protection of page 52 to 55 */
+#define OB_WRP_PAGES56TO59   0x00004000U /*!< Write protection of page 56 to 59 */
+#define OB_WRP_PAGES60TO63   0x00008000U /*!< Write protection of page 60 to 63 */
+#define OB_WRP_PAGES64TO67   0x00010000U /*!< Write protection of page 64 to 67 */
+#define OB_WRP_PAGES68TO71   0x00020000U /*!< Write protection of page 68 to 71 */
+#define OB_WRP_PAGES72TO75   0x00040000U /*!< Write protection of page 72 to 75 */
+#define OB_WRP_PAGES76TO79   0x00080000U /*!< Write protection of page 76 to 79 */
+#define OB_WRP_PAGES80TO83   0x00100000U /*!< Write protection of page 80 to 83 */
+#define OB_WRP_PAGES84TO87   0x00200000U /*!< Write protection of page 84 to 87 */
+#define OB_WRP_PAGES88TO91   0x00400000U /*!< Write protection of page 88 to 91 */
+#define OB_WRP_PAGES92TO95   0x00800000U /*!< Write protection of page 92 to 95 */
+#define OB_WRP_PAGES96TO99   0x01000000U /*!< Write protection of page 96 to 99 */
+#define OB_WRP_PAGES100TO103 0x02000000U /*!< Write protection of page 100 to 103 */
+#define OB_WRP_PAGES104TO107 0x04000000U /*!< Write protection of page 104 to 107 */
+#define OB_WRP_PAGES108TO111 0x08000000U /*!< Write protection of page 108 to 111 */
+#define OB_WRP_PAGES112TO115 0x10000000U /*!< Write protection of page 112 to 115 */
+#define OB_WRP_PAGES116TO119 0x20000000U /*!< Write protection of page 115 to 119 */
+#define OB_WRP_PAGES120TO123 0x40000000U /*!< Write protection of page 120 to 123 */
+#define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */
+#endif                                   /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+/* STM32 High-density, XL-density and Connectivity line devices */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+#define OB_WRP_PAGES0TO1    0x00000001U /*!< Write protection of page 0 TO 1 */
+#define OB_WRP_PAGES2TO3    0x00000002U /*!< Write protection of page 2 TO 3 */
+#define OB_WRP_PAGES4TO5    0x00000004U /*!< Write protection of page 4 TO 5 */
+#define OB_WRP_PAGES6TO7    0x00000008U /*!< Write protection of page 6 TO 7 */
+#define OB_WRP_PAGES8TO9    0x00000010U /*!< Write protection of page 8 TO 9 */
+#define OB_WRP_PAGES10TO11  0x00000020U /*!< Write protection of page 10 TO 11 */
+#define OB_WRP_PAGES12TO13  0x00000040U /*!< Write protection of page 12 TO 13 */
+#define OB_WRP_PAGES14TO15  0x00000080U /*!< Write protection of page 14 TO 15 */
+#define OB_WRP_PAGES16TO17  0x00000100U /*!< Write protection of page 16 TO 17 */
+#define OB_WRP_PAGES18TO19  0x00000200U /*!< Write protection of page 18 TO 19 */
+#define OB_WRP_PAGES20TO21  0x00000400U /*!< Write protection of page 20 TO 21 */
+#define OB_WRP_PAGES22TO23  0x00000800U /*!< Write protection of page 22 TO 23 */
+#define OB_WRP_PAGES24TO25  0x00001000U /*!< Write protection of page 24 TO 25 */
+#define OB_WRP_PAGES26TO27  0x00002000U /*!< Write protection of page 26 TO 27 */
+#define OB_WRP_PAGES28TO29  0x00004000U /*!< Write protection of page 28 TO 29 */
+#define OB_WRP_PAGES30TO31  0x00008000U /*!< Write protection of page 30 TO 31 */
+#define OB_WRP_PAGES32TO33  0x00010000U /*!< Write protection of page 32 TO 33 */
+#define OB_WRP_PAGES34TO35  0x00020000U /*!< Write protection of page 34 TO 35 */
+#define OB_WRP_PAGES36TO37  0x00040000U /*!< Write protection of page 36 TO 37 */
+#define OB_WRP_PAGES38TO39  0x00080000U /*!< Write protection of page 38 TO 39 */
+#define OB_WRP_PAGES40TO41  0x00100000U /*!< Write protection of page 40 TO 41 */
+#define OB_WRP_PAGES42TO43  0x00200000U /*!< Write protection of page 42 TO 43 */
+#define OB_WRP_PAGES44TO45  0x00400000U /*!< Write protection of page 44 TO 45 */
+#define OB_WRP_PAGES46TO47  0x00800000U /*!< Write protection of page 46 TO 47 */
+#define OB_WRP_PAGES48TO49  0x01000000U /*!< Write protection of page 48 TO 49 */
+#define OB_WRP_PAGES50TO51  0x02000000U /*!< Write protection of page 50 TO 51 */
+#define OB_WRP_PAGES52TO53  0x04000000U /*!< Write protection of page 52 TO 53 */
+#define OB_WRP_PAGES54TO55  0x08000000U /*!< Write protection of page 54 TO 55 */
+#define OB_WRP_PAGES56TO57  0x10000000U /*!< Write protection of page 56 TO 57 */
+#define OB_WRP_PAGES58TO59  0x20000000U /*!< Write protection of page 58 TO 59 */
+#define OB_WRP_PAGES60TO61  0x40000000U /*!< Write protection of page 60 TO 61 */
+#define OB_WRP_PAGES62TO127 0x80000000U /*!< Write protection of page 62 TO 127 */
+#define OB_WRP_PAGES62TO255 0x80000000U /*!< Write protection of page 62 TO 255 */
+#define OB_WRP_PAGES62TO511 0x80000000U /*!< Write protection of page 62 TO 511 */
+#endif                                  /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+                                        /* STM32F101xG || STM32F103xG */
+                                        /* STM32F105xC || STM32F107xC */
+
+#define OB_WRP_ALLPAGES 0xFFFFFFFFU /*!< Write protection of all Pages */
+
+/* Low Density */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
+#define OB_WRP_PAGES0TO31MASK 0x000000FFU
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES0TO31MASK   0x000000FFU
+#define OB_WRP_PAGES32TO63MASK  0x0000FF00U
+#define OB_WRP_PAGES64TO95MASK  0x00FF0000U
+#define OB_WRP_PAGES96TO127MASK 0xFF000000U
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
+#define OB_WRP_PAGES0TO15MASK   0x000000FFU
+#define OB_WRP_PAGES16TO31MASK  0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK  0x00FF0000U
+#define OB_WRP_PAGES48TO255MASK 0xFF000000U
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define OB_WRP_PAGES0TO15MASK   0x000000FFU
+#define OB_WRP_PAGES16TO31MASK  0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK  0x00FF0000U
+#define OB_WRP_PAGES48TO511MASK 0xFF000000U
+#endif /* STM32F101xG || STM32F103xG */
+
+/* Connectivity line devices */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define OB_WRP_PAGES0TO15MASK   0x000000FFU
+#define OB_WRP_PAGES16TO31MASK  0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK  0x00FF0000U
+#define OB_WRP_PAGES48TO127MASK 0xFF000000U
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xA5)
+#define OB_RDP_LEVEL_1 ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
+ * @{
+ */
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
+ * @{
+ */
+#define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST    ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
+ * @{
+ */
+#define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST    ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+/**
+ * @}
+ */
+
+#if defined(FLASH_BANK2_END)
+/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
+ * @{
+ */
+#define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET   ((uint16_t)0x0008) /*!< BOOT1 Set */
+/**
+ * @}
+ */
+#endif /* FLASH_BANK2_END */
+
+/** @defgroup FLASHEx_OB_Data_Address  Option Byte Data Address
+ * @{
+ */
+#define OB_DATA_ADDRESS_DATA0 0x1FFFF804U
+#define OB_DATA_ADDRESS_DATA1 0x1FFFF806U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Flag_definition Flag definition
+ * @brief Flag definition
+ * @{
+ */
+#if defined(FLASH_BANK2_END)
+#define FLASH_FLAG_BSY    FLASH_FLAG_BSY_BANK1    /*!< FLASH Bank1 Busy flag                   */
+#define FLASH_FLAG_PGERR  FLASH_FLAG_PGERR_BANK1  /*!< FLASH Bank1 Programming error flag      */
+#define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag  */
+#define FLASH_FLAG_EOP    FLASH_FLAG_EOP_BANK1    /*!< FLASH Bank1 End of Operation flag       */
+
+#define FLASH_FLAG_BSY_BANK1    FLASH_SR_BSY      /*!< FLASH Bank1 Busy flag                   */
+#define FLASH_FLAG_PGERR_BANK1  FLASH_SR_PGERR    /*!< FLASH Bank1 Programming error flag      */
+#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag  */
+#define FLASH_FLAG_EOP_BANK1    FLASH_SR_EOP      /*!< FLASH Bank1 End of Operation flag       */
+
+#define FLASH_FLAG_BSY_BANK2    (FLASH_SR2_BSY << 16U)      /*!< FLASH Bank2 Busy flag                   */
+#define FLASH_FLAG_PGERR_BANK2  (FLASH_SR2_PGERR << 16U)    /*!< FLASH Bank2 Programming error flag      */
+#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag  */
+#define FLASH_FLAG_EOP_BANK2    (FLASH_SR2_EOP << 16U)      /*!< FLASH Bank2 End of Operation flag       */
+
+#else
+
+#define FLASH_FLAG_BSY    FLASH_SR_BSY      /*!< FLASH Busy flag                          */
+#define FLASH_FLAG_PGERR  FLASH_SR_PGERR    /*!< FLASH Programming error flag             */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag         */
+#define FLASH_FLAG_EOP    FLASH_SR_EOP      /*!< FLASH End of Operation flag              */
+
+#endif
+#define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error        */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition Interrupt definition
+ * @brief FLASH Interrupt definition
+ * @{
+ */
+#if defined(FLASH_BANK2_END)
+#define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */
+#define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1                  */
+
+#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */
+#define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1                  */
+
+#define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */
+#define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2                  */
+
+#else
+
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source                  */
+
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
+ * @{
+ */
+
+/** @defgroup FLASH_Interrupt Interrupt
+ *  @brief macros to handle FLASH interrupts
+ * @{
+ */
+
+#if defined(FLASH_BANK2_END)
+/**
+ * @brief  Enable the specified FLASH interrupt.
+ * @param  __INTERRUPT__  FLASH interrupt
+ *     This parameter can be any combination of the following values:
+ *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
+ *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
+ *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
+ *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)           \
+  do {                                                 \
+    /* Enable Bank1 IT */                              \
+    SET_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
+    /* Enable Bank2 IT */                              \
+    SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U));     \
+  } while (0U)
+
+/**
+ * @brief  Disable the specified FLASH interrupt.
+ * @param  __INTERRUPT__  FLASH interrupt
+ *     This parameter can be any combination of the following values:
+ *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
+ *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
+ *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
+ *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)            \
+  do {                                                   \
+    /* Disable Bank1 IT */                               \
+    CLEAR_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
+    /* Disable Bank2 IT */                               \
+    CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U));     \
+  } while (0U)
+
+/**
+ * @brief  Get the specified FLASH flag status.
+ * @param  __FLAG__ specifies the FLASH flag to check.
+ *          This parameter can be one of the following values:
+ *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
+ *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
+ *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
+ *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
+ *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
+ *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
+ *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
+ *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
+ *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) \
+  (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : ((((__FLAG__)&SR_FLAG_MASK) != RESET) ? (FLASH->SR & ((__FLAG__)&SR_FLAG_MASK)) : (FLASH->SR2 & ((__FLAG__) >> 16U))))
+
+/**
+ * @brief  Clear the specified FLASH flag.
+ * @param  __FLAG__ specifies the FLASH flags to clear.
+ *          This parameter can be any combination of the following values:
+ *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
+ *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
+ *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
+ *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
+ *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
+ *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
+ *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
+ *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
+ *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        \
+  do {                                          \
+    /* Clear FLASH_FLAG_OPTVERR flag */         \
+    if ((__FLAG__) == FLASH_FLAG_OPTVERR) {     \
+      CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR);  \
+    } else {                                    \
+      /* Clear Flag in Bank1 */                 \
+      if (((__FLAG__)&SR_FLAG_MASK) != RESET) { \
+        FLASH->SR = ((__FLAG__)&SR_FLAG_MASK);  \
+      }                                         \
+      /* Clear Flag in Bank2 */                 \
+      if (((__FLAG__) >> 16U) != RESET) {       \
+        FLASH->SR2 = ((__FLAG__) >> 16U);       \
+      }                                         \
+    }                                           \
+  } while (0U)
+#else
+                      /**
+                       * @brief  Enable the specified FLASH interrupt.
+                       * @param  __INTERRUPT__  FLASH interrupt
+                       *         This parameter can be any combination of the following values:
+                       *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+                       *     @arg @ref FLASH_IT_ERR Error Interrupt
+                       * @retval none
+                       */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
+
+/**
+ * @brief  Disable the specified FLASH interrupt.
+ * @param  __INTERRUPT__  FLASH interrupt
+ *         This parameter can be any combination of the following values:
+ *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+ *     @arg @ref FLASH_IT_ERR Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief  Get the specified FLASH flag status.
+ * @param  __FLAG__ specifies the FLASH flag to check.
+ *          This parameter can be one of the following values:
+ *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag
+ *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
+ *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag
+ *            @arg @ref FLASH_FLAG_BSY    FLASH Busy flag
+ *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__)        (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : (FLASH->SR & (__FLAG__)))
+/**
+ * @brief  Clear the specified FLASH flag.
+ * @param  __FLAG__ specifies the FLASH flags to clear.
+ *          This parameter can be any combination of the following values:
+ *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag
+ *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
+ *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag
+ *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)       \
+  do {                                         \
+    /* Clear FLASH_FLAG_OPTVERR flag */        \
+    if ((__FLAG__) == FLASH_FLAG_OPTVERR) {    \
+      CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
+    } else {                                   \
+      /* Clear Flag in Bank1 */                \
+      FLASH->SR = (__FLAG__);                  \
+    }                                          \
+  } while (0U)
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+uint32_t          HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h

@@ -0,0 +1,309 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_gpio.h
+ * @author  MCD Application Team
+ * @brief   Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_GPIO_H
+#define __STM32F1xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct {
+  uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+                     This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+                      This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                      This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed; /*!< Specifies the speed for the selected pins.
+                       This parameter can be a value of @ref GPIO_speed_define */
+} GPIO_InitTypeDef;
+
+/**
+ * @brief  GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define GPIO pins define
+ * @{
+ */
+#define GPIO_PIN_0   ((uint16_t)0x0001) /* Pin 0 selected    */
+#define GPIO_PIN_1   ((uint16_t)0x0002) /* Pin 1 selected    */
+#define GPIO_PIN_2   ((uint16_t)0x0004) /* Pin 2 selected    */
+#define GPIO_PIN_3   ((uint16_t)0x0008) /* Pin 3 selected    */
+#define GPIO_PIN_4   ((uint16_t)0x0010) /* Pin 4 selected    */
+#define GPIO_PIN_5   ((uint16_t)0x0020) /* Pin 5 selected    */
+#define GPIO_PIN_6   ((uint16_t)0x0040) /* Pin 6 selected    */
+#define GPIO_PIN_7   ((uint16_t)0x0080) /* Pin 7 selected    */
+#define GPIO_PIN_8   ((uint16_t)0x0100) /* Pin 8 selected    */
+#define GPIO_PIN_9   ((uint16_t)0x0200) /* Pin 9 selected    */
+#define GPIO_PIN_10  ((uint16_t)0x0400) /* Pin 10 selected   */
+#define GPIO_PIN_11  ((uint16_t)0x0800) /* Pin 11 selected   */
+#define GPIO_PIN_12  ((uint16_t)0x1000) /* Pin 12 selected   */
+#define GPIO_PIN_13  ((uint16_t)0x2000) /* Pin 13 selected   */
+#define GPIO_PIN_14  ((uint16_t)0x4000) /* Pin 14 selected   */
+#define GPIO_PIN_15  ((uint16_t)0x8000) /* Pin 15 selected   */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode_define GPIO mode define
+ * @brief GPIO Configuration Mode
+ *        Elements values convention: 0xX0yz00YZ
+ *           - X  : GPIO mode or EXTI Mode
+ *           - y  : External IT or Event trigger detection
+ *           - z  : IO configuration on External IT or Event
+ *           - Y  : Output type (Push Pull or Open Drain)
+ *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT     0x00000000U     /*!< Input Floating Mode                   */
+#define GPIO_MODE_OUTPUT_PP 0x00000001U     /*!< Output Push Pull Mode                 */
+#define GPIO_MODE_OUTPUT_OD 0x00000011U     /*!< Output Open Drain Mode                */
+#define GPIO_MODE_AF_PP     0x00000002U     /*!< Alternate Function Push Pull Mode     */
+#define GPIO_MODE_AF_OD     0x00000012U     /*!< Alternate Function Open Drain Mode    */
+#define GPIO_MODE_AF_INPUT  GPIO_MODE_INPUT /*!< Alternate Function Input Mode         */
+
+#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode  */
+
+#define GPIO_MODE_IT_RISING         0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define GPIO_MODE_IT_FALLING        0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+
+#define GPIO_MODE_EVT_RISING         0x10120000U /*!< External Event Mode with Rising edge trigger detection               */
+#define GPIO_MODE_EVT_FALLING        0x10220000U /*!< External Event Mode with Falling edge trigger detection              */
+#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection       */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_speed_define  GPIO speed define
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_FREQ_LOW    (GPIO_CRL_MODE0_1) /*!< Low speed */
+#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
+#define GPIO_SPEED_FREQ_HIGH   (GPIO_CRL_MODE0)   /*!< High speed */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_pull_define GPIO pull define
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL   0x00000000U /*!< No Pull-up or Pull-down activation  */
+#define GPIO_PULLUP   0x00000001U /*!< Pull-up activation                  */
+#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation                */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief  Checks whether the specified EXTI line flag is set or not.
+ * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+ *         This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief  Clears the EXTI's line pending flags.
+ * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+ *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief  Checks whether the specified EXTI line is asserted or not.
+ * @param  __EXTI_LINE__: specifies the EXTI line to check.
+ *          This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief  Clears the EXTI's line pending bits.
+ * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+ *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief  Generates a Software interrupt on selected EXTI line.
+ * @param  __EXTI_LINE__: specifies the EXTI line to check.
+ *          This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+/**
+ * @}
+ */
+
+/* Include GPIO HAL Extension module */
+#include "stm32f1xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(PIN)           ((((PIN)&GPIO_PIN_MASK) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_MODE(MODE)                                                                                                                                                                             \
+  (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING)  \
+   || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) \
+   || ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
+#define IS_GPIO_PULL(PULL)   (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h

@@ -0,0 +1,895 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_gpio_ex.h
+ * @author  MCD Application Team
+ * @brief   Header file of GPIO HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_GPIO_EX_H
+#define __STM32F1xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
+ * @brief This section propose definition to use the Cortex EVENTOUT signal.
+ * @{
+ */
+
+/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
+ * @{
+ */
+
+#define AFIO_EVENTOUT_PIN_0  AFIO_EVCR_PIN_PX0  /*!< EVENTOUT on pin 0 */
+#define AFIO_EVENTOUT_PIN_1  AFIO_EVCR_PIN_PX1  /*!< EVENTOUT on pin 1 */
+#define AFIO_EVENTOUT_PIN_2  AFIO_EVCR_PIN_PX2  /*!< EVENTOUT on pin 2 */
+#define AFIO_EVENTOUT_PIN_3  AFIO_EVCR_PIN_PX3  /*!< EVENTOUT on pin 3 */
+#define AFIO_EVENTOUT_PIN_4  AFIO_EVCR_PIN_PX4  /*!< EVENTOUT on pin 4 */
+#define AFIO_EVENTOUT_PIN_5  AFIO_EVCR_PIN_PX5  /*!< EVENTOUT on pin 5 */
+#define AFIO_EVENTOUT_PIN_6  AFIO_EVCR_PIN_PX6  /*!< EVENTOUT on pin 6 */
+#define AFIO_EVENTOUT_PIN_7  AFIO_EVCR_PIN_PX7  /*!< EVENTOUT on pin 7 */
+#define AFIO_EVENTOUT_PIN_8  AFIO_EVCR_PIN_PX8  /*!< EVENTOUT on pin 8 */
+#define AFIO_EVENTOUT_PIN_9  AFIO_EVCR_PIN_PX9  /*!< EVENTOUT on pin 9 */
+#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
+#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
+#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
+#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
+#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
+#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
+
+#define IS_AFIO_EVENTOUT_PIN(__PIN__)                                                                                                                                                                 \
+  (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4)         \
+   || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9)      \
+   || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) \
+   || ((__PIN__) == AFIO_EVENTOUT_PIN_15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
+ * @{
+ */
+
+#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
+#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
+#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
+#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
+#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
+
+#define IS_AFIO_EVENTOUT_PORT(__PORT__) \
+  (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
+ * @brief This section propose definition to remap the alternate function to some other port/pins.
+ * @{
+ */
+
+/**
+ * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @note  ENABLE: Remap     (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
+
+/**
+ * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
+
+/**
+ * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
+ * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
+
+/**
+ * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
+ * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
+
+/**
+ * @brief Enable the remapping of USART1 alternate function TX and RX.
+ * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
+
+/**
+ * @brief Disable the remapping of USART1 alternate function TX and RX.
+ * @note  DISABLE: No remap (TX/PA9, RX/PA10)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
+
+/**
+ * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
+
+/**
+ * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
+
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+ * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+ * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+ * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @note  ENABLE: Full remap     (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
+ * @note  TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @note  PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
+ * @note  TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+ * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
+ * @note  DISABLE: No remap      (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
+ * @note  TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
+ * @note  ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
+ * @note  TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
+ * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
+ * @note  TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)
+
+#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)
+
+#endif
+
+/**
+ * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ *        on 100-pin and 144-pin packages, no need for remapping).
+ * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)
+
+/**
+ * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ *        on 100-pin and 144-pin packages, no need for remapping).
+ * @note  DISABLE: No remapping of PD0 and PD1
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)
+
+#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
+/**
+ * @brief Enable the remapping of TIM5CH4.
+ * @note  ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
+ * @note  This function is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)
+
+/**
+ * @brief Disable the remapping of TIM5CH4.
+ * @note  DISABLE: TIM5_CH4 is connected to PA3
+ * @note  This function is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)
+#endif
+
+#if defined(AFIO_MAPR_ETH_REMAP)
+/**
+ * @brief Enable the remapping of Ethernet MAC connections with the PHY.
+ * @note  ENABLE: Remap     (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)
+
+/**
+ * @brief Disable the remapping of Ethernet MAC connections with the PHY.
+ * @note  DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5,  RXD2/PB0,  RXD3/PB1)
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_CAN2_REMAP)
+
+/**
+ * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @note  ENABLE: Remap     (CAN2_RX/PB5,  CAN2_TX/PB6)
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)
+
+/**
+ * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_MII_RMII_SEL)
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @note  ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)
+
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @note  ETH_MII: Configure Ethernet MAC for connection with an MII PHY
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)
+#endif
+
+/**
+ * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
+
+#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
+#endif
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note  ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note  NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note  NOJTAG: JTAG-DP Disabled and SW-DP Enabled
+ * @retval None
+ */
+
+#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
+
+/**
+ * @brief Disable the Serial wire JTAG configuration
+ * @note  DISABLE: JTAG-DP Disabled and SW-DP Disabled
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)
+
+#if defined(AFIO_MAPR_SPI3_REMAP)
+
+/**
+ * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @note  ENABLE: Remap     (SPI3_NSS-I2S3_WS/PA4,  SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)
+
+/**
+ * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @note  DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3,  SPI3_MISO/PB4,  SPI3_MOSI-I2S3_SD/PB5).
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @note  TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @note  TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
+#endif
+
+#if defined(AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note  ENABLE: PTP_PPS is output on PB5 pin.
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note  DISABLE: PTP_PPS not output on PB5 pin.
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM9_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @note  ENABLE: Remap     (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @note  DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM10_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM10_CH1.
+ * @note  ENABLE: Remap     (TIM10_CH1 on PF6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM10_CH1.
+ * @note  DISABLE: No remap (TIM10_CH1 on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM11_REMAP)
+/**
+ * @brief Enable the remapping of TIM11_CH1.
+ * @note  ENABLE: Remap     (TIM11_CH1 on PF7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM11_CH1.
+ * @note  DISABLE: No remap (TIM11_CH1 on PB9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM13_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM13_CH1.
+ * @note  ENABLE: Remap     STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM13_CH1.
+ * @note  DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM14_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM14_CH1.
+ * @note  ENABLE: Remap     STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM14_CH1.
+ * @note  DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @note  DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
+ * @retval None
+ */
+#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @note  CONNECTED: The NADV signal is connected to the output (default).
+ * @retval None
+ */
+#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM15_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @note  ENABLE: Remap     (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @note  DISABLE: No remap (TIM15_CH1 on PA2  and TIM15_CH2 on PA3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM16_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM16_CH1.
+ * @note  ENABLE: Remap     (TIM16_CH1 on PA6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM16_CH1.
+ * @note  DISABLE: No remap (TIM16_CH1 on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM17_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM17_CH1.
+ * @note  ENABLE: Remap     (TIM17_CH1 on PA7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM17_CH1.
+ * @note  DISABLE: No remap (TIM17_CH1 on PB9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_CEC_REMAP)
+
+/**
+ * @brief Enable the remapping of CEC.
+ * @note  ENABLE: Remap     (CEC on PB10).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
+
+/**
+ * @brief Disable the remapping of CEC.
+ * @note  DISABLE: No remap (CEC on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @note  ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @note  DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @note  ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @note  DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM12_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @note  ENABLE: Remap     (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
+ * @note  This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @note  DISABLE: No remap (TIM12_CH1 on PC4  and TIM12_CH2 on PC5).
+ * @note  This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_MISC_REMAP)
+
+/**
+ * @brief Miscellaneous features remapping.
+ *        This bit is set and cleared by software. It controls miscellaneous features.
+ *        The DMA2 channel 5 interrupt position in the vector table.
+ *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @note  ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
+ *        selected as DAC Trigger 3, TIM15 triggers TIM1/3.
+ * @note  This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
+
+/**
+ * @brief Miscellaneous features remapping.
+ *        This bit is set and cleared by software. It controls miscellaneous features.
+ *        The DMA2 channel 5 interrupt position in the vector table.
+ *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @note  DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
+ *        event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
+ * @note  This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
+ * @{
+ */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : 3U)
+#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : 4U)
+#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#define GPIO_GET_INDEX(__GPIOx__) \
+  (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : ((__GPIOx__) == (GPIOE)) ? 4U : ((__GPIOx__) == (GPIOF)) ? 5U : 6U)
+#endif
+
+#define AFIO_REMAP_ENABLE(REMAP_PIN) \
+  do {                               \
+    uint32_t tmpreg = AFIO->MAPR;    \
+    tmpreg |= AFIO_MAPR_SWJ_CFG;     \
+    tmpreg |= REMAP_PIN;             \
+    AFIO->MAPR = tmpreg;             \
+  } while (0U)
+
+#define AFIO_REMAP_DISABLE(REMAP_PIN) \
+  do {                                \
+    uint32_t tmpreg = AFIO->MAPR;     \
+    tmpreg |= AFIO_MAPR_SWJ_CFG;      \
+    tmpreg &= ~REMAP_PIN;             \
+    AFIO->MAPR = tmpreg;              \
+  } while (0U)
+
+#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) \
+  do {                                                \
+    uint32_t tmpreg = AFIO->MAPR;                     \
+    tmpreg &= ~REMAP_PIN_MASK;                        \
+    tmpreg |= AFIO_MAPR_SWJ_CFG;                      \
+    tmpreg |= REMAP_PIN;                              \
+    AFIO->MAPR = tmpreg;                              \
+  } while (0U)
+
+#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) \
+  do {                                    \
+    uint32_t tmpreg = AFIO->MAPR;         \
+    tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk;     \
+    tmpreg |= DBGAFR_SWJCFG;              \
+    AFIO->MAPR = tmpreg;                  \
+  } while (0U)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GPIOEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIOEx_Exported_Functions_Group1
+ * @{
+ */
+void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
+void HAL_GPIOEx_EnableEventout(void);
+void HAL_GPIOEx_DisableEventout(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h

@@ -0,0 +1,638 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_i2c.h
+ * @author  MCD Application Team
+ * @brief   Header file of I2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_I2C_H
+#define __STM32F1xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
+/**
+ * @brief  I2C Configuration Structure definition
+ */
+typedef struct {
+  uint32_t ClockSpeed; /*!< Specifies the clock frequency.
+                            This parameter must be set to a value lower than 400kHz */
+
+  uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+                           This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint32_t OwnAddress1; /*!< Specifies the first device own address.
+                             This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                This parameter can be a value of @ref I2C_addressing_mode */
+
+  uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+                                 This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+  uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+                             This parameter can be a 7-bit address. */
+
+  uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+                                 This parameter can be a value of @ref I2C_general_call_addressing_mode */
+
+  uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+                               This parameter can be a value of @ref I2C_nostretch_mode */
+
+} I2C_InitTypeDef;
+
+/**
+ * @brief  HAL State structure definition
+ * @note  HAL I2C State value coding follow below described bitmap :
+ *          b7-b6  Error information
+ *             00 : No Error
+ *             01 : Abort (Abort user request on going)
+ *             10 : Timeout
+ *             11 : Error
+ *          b5     IP initilisation status
+ *             0  : Reset (IP not initialized)
+ *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)
+ *          b4     (not used)
+ *             x  : Should be set to 0
+ *          b3
+ *             0  : Ready or Busy (No Listen mode ongoing)
+ *             1  : Listen (IP in Address Listen Mode)
+ *          b2     Intrinsic process state
+ *             0  : Ready
+ *             1  : Busy (IP busy with some configuration or internal operations)
+ *          b1     Rx state
+ *             0  : Ready (no Rx operation ongoing)
+ *             1  : Busy (Rx operation ongoing)
+ *          b0     Tx state
+ *             0  : Ready (no Tx operation ongoing)
+ *             1  : Busy (Tx operation ongoing)
+ */
+typedef enum {
+  HAL_I2C_STATE_RESET          = 0x00U, /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY          = 0x20U, /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY           = 0x24U, /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX        = 0x21U, /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX        = 0x22U, /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN         = 0x28U, /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
+                                            process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
+                                            process is ongoing                         */
+  HAL_I2C_STATE_ABORT   = 0x60U,        /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT = 0xA0U,        /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR   = 0xE0U         /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+ * @brief  HAL Mode structure definition
+ * @note  HAL I2C Mode value coding follow below described bitmap :
+ *          b7     (not used)
+ *             x  : Should be set to 0
+ *          b6
+ *             0  : None
+ *             1  : Memory (HAL I2C communication is in Memory Mode)
+ *          b5
+ *             0  : None
+ *             1  : Slave (HAL I2C communication is in Slave Mode)
+ *          b4
+ *             0  : None
+ *             1  : Master (HAL I2C communication is in Master Mode)
+ *          b3-b2-b1-b0  (not used)
+ *             xxxx : Should be set to 0000
+ */
+typedef enum {
+  HAL_I2C_MODE_NONE   = 0x00U, /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE  = 0x20U, /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM    = 0x40U  /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+ * @brief  I2C handle Structure definition
+ */
+typedef struct {
+  I2C_TypeDef *Instance; /*!< I2C registers base address               */
+
+  I2C_InitTypeDef Init; /*!< I2C communication parameters             */
+
+  uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer           */
+
+  uint16_t XferSize; /*!< I2C transfer size                        */
+
+  __IO uint16_t XferCount; /*!< I2C transfer counter                     */
+
+  __IO uint32_t XferOptions; /*!< I2C transfer options                     */
+
+  __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
+                                    context for internal usage               */
+
+  DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters             */
+
+  DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters             */
+
+  HAL_LockTypeDef Lock; /*!< I2C locking object                       */
+
+  __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state                  */
+
+  __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode                   */
+
+  __IO uint32_t ErrorCode; /*!< I2C Error code                           */
+
+  __IO uint32_t Devaddress; /*!< I2C Target device address                */
+
+  __IO uint32_t Memaddress; /*!< I2C Target memory address                */
+
+  __IO uint32_t MemaddSize; /*!< I2C Target memory address  size          */
+
+  __IO uint32_t EventCount; /*!< I2C Event counter                        */
+
+} I2C_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_Error_Code I2C Error Code
+ * @brief    I2C Error Code
+ * @{
+ */
+#define HAL_I2C_ERROR_NONE    0x00000000U /*!< No error           */
+#define HAL_I2C_ERROR_BERR    0x00000001U /*!< BERR error         */
+#define HAL_I2C_ERROR_ARLO    0x00000002U /*!< ARLO error         */
+#define HAL_I2C_ERROR_AF      0x00000004U /*!< AF error           */
+#define HAL_I2C_ERROR_OVR     0x00000008U /*!< OVR error          */
+#define HAL_I2C_ERROR_DMA     0x00000010U /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error      */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
+ * @{
+ */
+#define I2C_DUTYCYCLE_2    0x00000000U
+#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
+/**
+ * @}
+ */
+
+/** @defgroup I2C_addressing_mode I2C addressing mode
+ * @{
+ */
+#define I2C_ADDRESSINGMODE_7BIT  0x00004000U
+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLE 0x00000000U
+#define I2C_DUALADDRESS_ENABLE  I2C_OAR2_ENDUAL
+/**
+ * @}
+ */
+
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
+ * @{
+ */
+#define I2C_GENERALCALL_DISABLE 0x00000000U
+#define I2C_GENERALCALL_ENABLE  I2C_CR1_ENGC
+/**
+ * @}
+ */
+
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLE 0x00000000U
+#define I2C_NOSTRETCH_ENABLE  I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+ * @{
+ */
+#define I2C_MEMADD_SIZE_8BIT  0x00000001U
+#define I2C_MEMADD_SIZE_16BIT 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
+ * @{
+ */
+#define I2C_DIRECTION_RECEIVE  0x00000000U
+#define I2C_DIRECTION_TRANSMIT 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
+ * @{
+ */
+#define I2C_FIRST_FRAME          0x00000001U
+#define I2C_NEXT_FRAME           0x00000002U
+#define I2C_FIRST_AND_LAST_FRAME 0x00000004U
+#define I2C_LAST_FRAME           0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+ * @{
+ */
+#define I2C_IT_BUF I2C_CR2_ITBUFEN
+#define I2C_IT_EVT I2C_CR2_ITEVTEN
+#define I2C_IT_ERR I2C_CR2_ITERREN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+ * @{
+ */
+#define I2C_FLAG_SMBALERT   0x00018000U
+#define I2C_FLAG_TIMEOUT    0x00014000U
+#define I2C_FLAG_PECERR     0x00011000U
+#define I2C_FLAG_OVR        0x00010800U
+#define I2C_FLAG_AF         0x00010400U
+#define I2C_FLAG_ARLO       0x00010200U
+#define I2C_FLAG_BERR       0x00010100U
+#define I2C_FLAG_TXE        0x00010080U
+#define I2C_FLAG_RXNE       0x00010040U
+#define I2C_FLAG_STOPF      0x00010010U
+#define I2C_FLAG_ADD10      0x00010008U
+#define I2C_FLAG_BTF        0x00010004U
+#define I2C_FLAG_ADDR       0x00010002U
+#define I2C_FLAG_SB         0x00010001U
+#define I2C_FLAG_DUALF      0x00100080U
+#define I2C_FLAG_SMBHOST    0x00100040U
+#define I2C_FLAG_SMBDEFAULT 0x00100020U
+#define I2C_FLAG_GENCALL    0x00100010U
+#define I2C_FLAG_TRA        0x00100004U
+#define I2C_FLAG_BUSY       0x00100002U
+#define I2C_FLAG_MSL        0x00100001U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2C handle state
+ * @param  __HANDLE__: specifies the I2C Handle.
+ *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
+/** @brief  Enable or disable the specified I2C interrupts.
+ * @param  __HANDLE__: specifies the I2C Handle.
+ *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+ *         This parameter can be one of the following values:
+ *            @arg I2C_IT_BUF: Buffer interrupt enable
+ *            @arg I2C_IT_EVT: Event interrupt enable
+ *            @arg I2C_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
+ * @param  __HANDLE__: specifies the I2C Handle.
+ *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
+ *          This parameter can be one of the following values:
+ *            @arg I2C_IT_BUF: Buffer interrupt enable
+ *            @arg I2C_IT_EVT: Event interrupt enable
+ *            @arg I2C_IT_ERR: Error interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks whether the specified I2C flag is set or not.
+ * @param  __HANDLE__: specifies the I2C Handle.
+ *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param  __FLAG__: specifies the flag to check.
+ *         This parameter can be one of the following values:
+ *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ *            @arg I2C_FLAG_PECERR: PEC error in reception flag
+ *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
+ *            @arg I2C_FLAG_AF: Acknowledge failure flag
+ *            @arg I2C_FLAG_ARLO: Arbitration lost flag
+ *            @arg I2C_FLAG_BERR: Bus error flag
+ *            @arg I2C_FLAG_TXE: Data register empty flag
+ *            @arg I2C_FLAG_RXNE: Data register not empty flag
+ *            @arg I2C_FLAG_STOPF: Stop detection flag
+ *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
+ *            @arg I2C_FLAG_BTF: Byte transfer finished flag
+ *            @arg I2C_FLAG_ADDR: Address sent flag
+ *                                Address matched flag
+ *            @arg I2C_FLAG_SB: Start bit flag
+ *            @arg I2C_FLAG_DUALF: Dual flag
+ *            @arg I2C_FLAG_SMBHOST: SMBus host header
+ *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header
+ *            @arg I2C_FLAG_GENCALL: General call header flag
+ *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ *            @arg I2C_FLAG_BUSY: Bus busy flag
+ *            @arg I2C_FLAG_MSL: Master/Slave flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)                                                                                            \
+  ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? ((((__HANDLE__)->Instance->SR1) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)) \
+                                             : ((((__HANDLE__)->Instance->SR2) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)))
+
+/** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
+ * @param  __HANDLE__: specifies the I2C Handle.
+ *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param  __FLAG__: specifies the flag to clear.
+ *         This parameter can be any combination of the following values:
+ *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ *            @arg I2C_FLAG_PECERR: PEC error in reception flag
+ *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ *            @arg I2C_FLAG_AF: Acknowledge failure flag
+ *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ *            @arg I2C_FLAG_BERR: Bus error flag
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__)&I2C_FLAG_MASK))
+
+/** @brief  Clears the I2C ADDR pending flag.
+ * @param  __HANDLE__: specifies the I2C Handle.
+ *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)            \
+  do {                                                  \
+    __IO uint32_t tmpreg = 0x00U;                       \
+    tmpreg               = (__HANDLE__)->Instance->SR1; \
+    tmpreg               = (__HANDLE__)->Instance->SR2; \
+    UNUSED(tmpreg);                                     \
+  } while (0U)
+
+/** @brief  Clears the I2C STOPF pending flag.
+ * @param  __HANDLE__: specifies the I2C Handle.
+ *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)            \
+  do {                                                  \
+    __IO uint32_t tmpreg = 0x00U;                       \
+    tmpreg               = (__HANDLE__)->Instance->SR1; \
+    (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;          \
+    UNUSED(tmpreg);                                     \
+  } while (0U)
+
+/** @brief  Enable the I2C peripheral.
+ * @param  __HANDLE__: specifies the I2C Handle.
+ *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
+
+/** @brief  Disable the I2C peripheral.
+ * @param  __HANDLE__: specifies the I2C Handle.
+ *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void              HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void              HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions  *****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State, Mode and Errors functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+#define I2C_FLAG_MASK              0x0000FFFFU
+#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz                     */
+#define I2C_MIN_PCLK_FREQ_FAST     4000000U /*!< 4 MHz                     */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macros I2C Private Macros
+ * @{
+ */
+
+#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__)              (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
+#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__)-1U) / ((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
+#define I2C_FREQRANGE(__PCLK__)                             ((__PCLK__) / 1000000U)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)             (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__)*300U) / 1000U) + 1U))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)             ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U) ? 4U : I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) \
+  (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2) ? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)                       \
+  (((__SPEED__) <= 100000U) ? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) \
+                            : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U) ? 1U : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_READ(__ADDRESS__)  ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define I2C_10BIT_ADDRESS(__ADDRESS__)      ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__)  ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
+ * @{
+ */
+#define IS_I2C_DUTY_CYCLE(CYCLE)                 (((CYCLE) == I2C_DUTYCYCLE_2) || ((CYCLE) == I2C_DUTYCYCLE_16_9))
+#define IS_I2C_ADDRESSING_MODE(ADDRESS)          (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)             (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+#define IS_I2C_GENERAL_CALL(CALL)                (((CALL) == I2C_GENERALCALL_DISABLE) || ((CALL) == I2C_GENERALCALL_ENABLE))
+#define IS_I2C_NO_STRETCH(STRETCH)               (((STRETCH) == I2C_NOSTRETCH_DISABLE) || ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+#define IS_I2C_MEMADD_SIZE(SIZE)                 (((SIZE) == I2C_MEMADD_SIZE_8BIT) || ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+#define IS_I2C_CLOCK_SPEED(SPEED)                (((SPEED) > 0) && ((SPEED) <= 400000U))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)            (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)            (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || ((REQUEST) == I2C_NEXT_FRAME) || ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h

@@ -0,0 +1,230 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_iwdg.h
+ * @author  MCD Application Team
+ * @brief   Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_IWDG_H
+#define __STM32F1xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief  IWDG Init structure definition
+ */
+typedef struct {
+  uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+                           This parameter can be a value of @ref IWDG_Prescaler */
+
+  uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+                        This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/**
+ * @brief  IWDG Handle Structure definition
+ */
+typedef struct {
+  IWDG_TypeDef *Instance; /*!< Register base address    */
+
+  IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+
+} IWDG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4   0x00000000U                   /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8   IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16  IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32  (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64  IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief  Enable the IWDG peripheral.
+ * @param  __HANDLE__  IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+ * @brief  Reload IWDG counter with value defined in the reload register
+ *         (write access to IWDG_PR & IWDG_RLR registers disabled).
+ * @param  __HANDLE__  IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+ * @{
+ */
+/* Initialization/Start functions  ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+/**
+ * @brief  IWDG Key Register BitMask
+ */
+#define IWDG_KEY_RELOAD               0x0000AAAAU /*!< IWDG Reload Counter Enable   */
+#define IWDG_KEY_ENABLE               0x0000CCCCU /*!< IWDG Peripheral Enable       */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE  0x00005555U /*!< IWDG KR Write Access Enable  */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+ * @{
+ */
+
+/**
+ * @brief  Enable write access to IWDG_PR and IWDG_RLR registers.
+ * @param  __HANDLE__  IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief  Disable write access to IWDG_PR and IWDG_RLR registers.
+ * @param  __HANDLE__  IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+ * @brief  Check IWDG prescaler value.
+ * @param  __PRESCALER__  IWDG prescaler value
+ * @retval None
+ */
+#define IS_IWDG_PRESCALER(__PRESCALER__)                                                                                                                              \
+  (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) \
+   || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128) || ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+ * @brief  Check IWDG reload value.
+ * @param  __RELOAD__  IWDG reload value
+ * @retval None
+ */
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h

@@ -0,0 +1,388 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_pwr.h
+ * @author  MCD Application Team
+ * @brief   Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_PWR_H
+#define __STM32F1xx_HAL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+ * @{
+ */
+
+/**
+ * @brief  PWR PVD configuration structure definition
+ */
+typedef struct {
+  uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
+                          This parameter can be a value of @ref PWR_PVD_detection_level */
+
+  uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+                      This parameter can be a value of @ref PWR_PVD_Mode */
+} PWR_PVDTypeDef;
+
+/**
+ * @}
+ */
+
+/* Internal constants --------------------------------------------------------*/
+
+/** @addtogroup PWR_Private_Constants
+ * @{
+ */
+
+#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
+#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
+#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
+#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
+#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
+#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
+#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+ * @{
+ */
+#define PWR_PVD_MODE_NORMAL               0x00000000U /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING            0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING           0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING    0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING         0x00020001U /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING        0x00020002U /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
+ * @{
+ */
+
+#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON     0x00000000U
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag PWR Flag
+ * @{
+ */
+#define PWR_FLAG_WU   PWR_CSR_WUF
+#define PWR_FLAG_SB   PWR_CSR_SBF
+#define PWR_FLAG_PVDO PWR_CSR_PVDO
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @brief  Check PWR flag is set or not.
+ * @param  __FLAG__: specifies the flag to check.
+ *           This parameter can be one of the following values:
+ *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+ *                  was received from the WKUP pin or from the RTC alarm
+ *                  An additional wakeup event is detected if the WKUP pin is enabled
+ *                  (by setting the EWUP bit) when the WKUP pin level is already high.
+ *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ *                  resumed from StandBy mode.
+ *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+ *                  For this reason, this bit is equal to 0 after Standby or reset
+ *                  until the PVDE bit is set.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the PWR's pending flags.
+ * @param  __FLAG__: specifies the flag to clear.
+ *          This parameter can be one of the following values:
+ *            @arg PWR_FLAG_WU: Wake Up flag
+ *            @arg PWR_FLAG_SB: StandBy flag
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
+
+/**
+ * @brief Enable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief  PVD EXTI line configuration: set falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief  PVD EXTI line configuration: set rising edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();              \
+  __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();              \
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Clear the PVD EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+#define IS_PWR_PVD_LEVEL(LEVEL)                                                                                                                                                           \
+  (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) \
+   || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+
+#define IS_PWR_PVD_MODE(MODE)                                                                                                                                       \
+  (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) \
+   || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *******************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+/* #define HAL_PWR_ConfigPVD 12*/
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/