Merge pull request #940 from Ralim/MHP30

MHP30 Support

.github/workflows/push.yml

@@ -7,7 +7,7 @@ jobs:
     runs-on: ubuntu-20.04
     strategy:
       matrix:
-        model: ["TS100", "TS80", "TS80P", "Pinecil"]
+        model: ["TS100", "TS80", "TS80P", "Pinecil", "MHP30"]
       fail-fast: true
 
     steps:

Documentation/Hardware.md

@@ -0,0 +1,8 @@
+## Notes on the various supported hardware
+
+### MHP30
+
+- Accelerometer is the MSA301, this is mounted roughly in the middle of the unit
+- USB-PD is using the FUSB302
+- The hardware I2C bus on PB6/7 is used for the MSA301 and FUSB302
+- The OLED is the same SSD1306 as everything else, but its on a bit-banged bus

Translations/translation_DE.json

@@ -15,7 +15,7 @@
 		"InputVoltageString": "V Eingang: ",
 		"WarningTipTempString": "Temperatur: ",
 		"BadTipString": "Spitze Defekt",
-		"SleepingSimpleString": "Zzz ",
+		"SleepingSimpleString": "Zzzz",
 		"SleepingAdvancedString": "Ruhemodus...",
 		"WarningSimpleString": "HEISS!",
 		"WarningAdvancedString": "! Achtung Heiß !",
@@ -34,12 +34,12 @@
 			"zurückgesetzt!"
 		],
 		"NoAccelerometerMessage": [
-			"Kein Bewegungssensor",
+			"Bewegungssensor",
-			"erkannt!"
+			"nicht erkannt!"
 		],
 		"NoPowerDeliveryMessage": [
-			"Kein USB-PD IC",
+			"USB-PD IC",
-			"erkannt!"
+			"nicht erkannt!"
 		],
 		"LockingKeysString": "GESPERRT",
 		"UnlockingKeysString": "ENTSPERRT",
@@ -128,7 +128,7 @@
 		"ShutdownTimeout": {
 			"text2": [
 				"Abschalt-",
-				"zeit"
+				"verzög."
 			],
 			"desc": "Dauer vor automatischer Abschaltung <M=Minuten>"
 		},
@@ -219,14 +219,14 @@
 		"QCMaxVoltage": {
 			"text2": [
 				"Spannungs-",
-				"grenze"
+				"maximum"
 			],
 			"desc": "Maximal zulässige Spannung der verwendeten Spannungsversorgung <V=Volt>"
 		},
 		"PowerLimit": {
 			"text2": [
 				"Leistungs-",
-				"grenze"
+				"maximum"
 			],
 			"desc": "Maximale zulässige Leistungsaufnahme des Lötkolbens <W=Watt>"
 		},
@@ -260,8 +260,8 @@
 		},
 		"HallEffSensitivity": {
 			"text2": [
-				"Hall-Sonde",
+				"Empfindlichkeit",
-				"Empfindlichkeit"
+				"der Hall-Sonde"
 			],
 			"desc": "Empfindlichkeit der Hall-Sonde beim Erkennen des Ruhemodus <A=aus | N=niedrig | M=mittel | H=hoch>"
 		},
@@ -274,17 +274,17 @@
 		},
 		"MinVolCell": {
 			"text2": [
-				"Minimum",
+				"Minimale",
 				"Spannung"
 			],
-			"desc": "Minimal zulässige Spannung pro Zelle <Volt> <3S: 3,0V - 3,7V, 4/5/6S: 2,4V - 3,7V>"
+			"desc": "Minimal zulässige Spannung pro Zelle <3S: 3,0V - 3,7V | 4/5/6S: 2,4V - 3,7V>"
 		},
 		"AnimLoop": {
 			"text2": [
 				"Anim.",
 				"Schleife"
 			],
-			"desc": "Icon-Animationen im Stammmenü wiederholen"
+			"desc": "Icon-Animationen im Hauptmenü wiederholen"
 		},
 		"AnimSpeed": {
 			"text2": [
@@ -295,21 +295,21 @@
 		},
 		"PowerPulseWait": {
 			"text2": [
-				"Leistungsimpulse",
+				"Impuls-",
-				"Wartezeit"
+				"verzögerung"
 			],
-			"desc": "Dauer vor Abgabe von Wachhalteimpulsen (x 2,5s)"
+			"desc": "Dauer vor Abgabe von Wachhalteimpulsen <x 2,5s>"
 		},
 		"PowerPulseDuration": {
 			"text2": [
-				"Leistungsimpulse",
+				"Impuls-",
-				"Dauer"
+				"dauer"
 			],
-			"desc": "Dauer des Wachhalteimpulses (x 250ms)"
+			"desc": "Dauer des Wachhalteimpulses <x 0,25s>"
 		},
 		"LanguageSwitch": {
 			"text2": [
-				"Language:",
+				"Sprache:",
 				" DE     Deutsch"
 			],
 			"desc": ""

Translations/translation_FR.json

@@ -68,10 +68,10 @@
 	"menuGroups": {
 		"PowerMenu": {
 			"text2": [
-				"Power",
+				"Paramètres",
-				"settings"
+				"d'alim."
 			],
-			"desc": "Power settings"
+			"desc": "Paramètres d'alimentation"
 		},
 		"SolderingMenu": {
 			"text2": [
@@ -217,8 +217,8 @@
 		},
 		"QCMaxVoltage": {
 			"text2": [
-				"Tension max.",
+				"Tension",
-				"QC"
+				"max. QC"
 			],
 			"desc": "Tension maximale désirée avec une alimentation QC"
 		},
@@ -280,17 +280,17 @@
 		},
 		"AnimLoop": {
 			"text2": [
-				"Icônes",
+				"Rejouer",
-				"animées"
+				"anim. icônes"
 			],
-			"desc": "Animations des icônes dans le menu principal"
+			"desc": "Rejouer en boucle les animations des icônes dans le menu principal"
 		},
 		"AnimSpeed": {
 			"text2": [
 				"Vitesse",
-				"d'animations"
+				"anim. icônes"
 			],
-			"desc": "Vitesse des animations des icônes dans le menu <D=désactivé | L=lente | M=moyenne | H=haute>"
+			"desc": "Vitesse des animations des icônes dans le menu <D=désactivé | L=lente | M=moyenne | R=rapide>"
 		},
 		"PowerPulseWait": {
 			"text2": [
@@ -308,7 +308,7 @@
 		},
 		"LanguageSwitch": {
 			"text2": [
-				"Language:",
+				"Langue :",
 				" FR    Français"
 			],
 			"desc": ""

Translations/translation_HU.json

@@ -20,7 +20,7 @@
 		"WarningAdvancedString": "!! FORRÓ PÁKA !!",
 		"SleepingTipAdvancedString": "Páka:",
 		"IdleTipString": "Páka:",
-		"IdleSetString": "Cél:",
+		"IdleSetString": " Cél:",
 		"TipDisconnectedString": "PÁKA LEVÉVE",
 		"SolderingAdvancedPowerPrompt": "Telj: ",
 		"OffString": "Ki",
@@ -53,7 +53,7 @@
 		"SettingAutoChar": "A",
 		"SettingFastChar": "G",
 		"SettingSlowChar": "L",
-		"SettingMediumChar": "M",
+		"SettingMediumChar": "K",
 		"SettingOffChar": "0",
 		"SettingStartSolderingChar": "F",
 		"SettingStartSleepChar": "Z",
@@ -71,10 +71,10 @@
 	"menuGroups": {
 		"PowerMenu": {
 			"text2": [
-				"Power",
+				"Táp",
-				"settings"
+				"beállítások"
 			],
-			"desc": "Power settings"
+			"desc": "Táp beállítások"
 		},
 		"SolderingMenu": {
 			"text2": [
@@ -116,7 +116,7 @@
 		"SleepTemperature": {
 			"text2": [
 				"Alvási",
-				"hőmérs."
+				"hőmérséklet"
 			],
 			"desc": "Hőmérséklet alvó módban <C/F>"
 		},
@@ -165,7 +165,7 @@
 		"BoostTemperature": {
 			"text2": [
 				"Boost",
-				"hőmérs."
+				"hőmérséklet"
 			],
 			"desc": "Hőmérséklet \"boost\" módban"
 		},
@@ -207,7 +207,7 @@
 		"AdvancedSoldering": {
 			"text2": [
 				"Részletes",
-				"forr.kép"
+				"forrasztás"
 			],
 			"desc": "Részletes információk megjelenítése forrasztás közben"
 		},
@@ -221,13 +221,13 @@
 		"QCMaxVoltage": {
 			"text2": [
 				"Max. USB",
-				"fesz."
+				"feszültség"
 			],
 			"desc": "Maximális USB feszültség (QuickCharge)"
 		},
 		"PowerLimit": {
 			"text2": [
-				"Teljesítm.",
+				"Teljesítmény",
 				"maximum"
 			],
 			"desc": "Maximális felvett teljesitmény beállitása"
@@ -241,22 +241,22 @@
 		},
 		"TempChangeShortStep": {
 			"text2": [
-				"Hőm.váltás",
+				"Hőm. váltás",
 				"rövid"
 			],
 			"desc": "Hőmérséklet váltás rövid gombnyomásra <C/F>"
 		},
 		"TempChangeLongStep": {
 			"text2": [
-				"Hőm.váltás",
+				"Hőm. váltás",
 				"hosszú"
 			],
 			"desc": "Hőmérséklet váltás hosszú gombnyomásra <C/F>"
 		},
 		"PowerPulsePower": {
 			"text2": [
-				"Ébrentartó",
+				"Ébr. pulzus",
-				"pulzus W"
+				"nagysága"
 			],
 			"desc": "Powerbankot ébrentartó áramfelvételi pulzusok nagysága <W>"
 		},
@@ -270,44 +270,44 @@
 		"LockingMode": {
 			"text2": [
 				"Lezárás",
-				"enged."
+				"engedélyezés"
 			],
 			"desc": "Forrasztás közben mindkét gombot hosszan lenyomva rögzíti a hőmérsékletet (K=ki B=csak \"boost\" mód T=teljes lezárás)"
 		},
 		"MinVolCell": {
 			"text2": [
 				"Minimum",
-				"voltage"
+				"feszültség"
 			],
-			"desc": "Minimum allowed voltage per cell <Volts> <3S: 3.0V - 3.7V, 4/5/6S: 2.4V - 3.7V>"
+			"desc": "Minimális engedélyezett cellafeszültség <V> (3S: 3.0V-3.7V, 4/5/6S: 2.4V-3.7V)"
 		},
 		"AnimLoop": {
 			"text2": [
-				"Anim.",
+				"Folytonos",
-				"loop"
+				"animáció"
 			],
-			"desc": "Loop icon animations in root menu"
+			"desc": "Főmenü ikonjainak folytonos animációja"
 		},
 		"AnimSpeed": {
 			"text2": [
-				"Anim.",
+				"Animáció",
-				"speed"
+				"sebessége"
 			],
-			"desc": "Speed of icon animations in menu <O=off | L=low | M=medium | H=high>"
+			"desc": "Menüikonok animációjának sebessége (0=ki L=lassú K=közepes G=gyors)"
 		},
 		"PowerPulseWait": {
 			"text2": [
-				"Power pulse",
+				"Ébr. pulzus",
-				"wait time"
+				"időköze"
 			],
-			"desc": "Time to wait before triggering every keep-awake pulse (x 2.5s)"
+			"desc": "Powerbankot ébrentartó áramfelvételi pulzusok időköze <x2.5s>"
 		},
 		"PowerPulseDuration": {
 			"text2": [
-				"Power pulse",
+				"Ébr. pulzus",
-				"duration"
+				"időtartama"
 			],
-			"desc": "Keep-awake-pulse duration (x 250ms)"
+			"desc": "Powerbankot ébrentartó áramfelvételi pulzusok időtartama <x250ms>"
 		},
 		"LanguageSwitch": {
 			"text2": [

Translations/translation_IT.json

@@ -218,7 +218,7 @@
 		"QCMaxVoltage": {
 			"text2": [
 				"Voltaggio",
-				"Quick Charge"
+				"QC"
 			],
 			"desc": "Imposta il massimo voltaggio negoziabile con un alimentatore Quick Charge"
 		},
@@ -269,14 +269,14 @@
 				"Blocco",
 				"tasti"
 			],
-			"desc": "Blocca i tasti durante la modalità Saldatura; tieni premuto entrambi per bloccare o sbloccare [D: disattiva; T: blocca Turbo; C: blocco completo]"
+			"desc": "Blocca i tasti durante la modalità Saldatura; tieni premuto entrambi per bloccare o sbloccare [D: disattiva; T: consenti Turbo; C: blocco completo]"
 		},
 		"MinVolCell": {
 			"text2": [
 				"Tensione",
 				"min celle"
 			],
-			"desc": "Modifica il valore di tensione minima \"di scaricamento\" per le celle di una batteria Li-Po [3S: 3,0-3,7 V; 4S/5S/6S: 2,4-3,7 V]"
+			"desc": "Modifica la tensione di minima carica delle celle di una batteria Li-Po [3S: 3,0-3,7 V; 4S/5S/6S: 2,4-3,7 V]"
 		},
 		"AnimLoop": {
 			"text2": [
@@ -308,7 +308,7 @@
 		},
 		"LanguageSwitch": {
 			"text2": [
-				"Language:",
+				"Lingua:",
 				" IT    Italiano"
 			],
 			"desc": ""

Translations/translation_LT.json

@@ -53,7 +53,7 @@
 		"SettingAutoChar": "A",
 		"SettingFastChar": "G",
 		"SettingSlowChar": "L",
-		"SettingMediumChar": "M",
+		"SettingMediumChar": "V",
 		"SettingOffChar": "I",
 		"SettingStartSolderingChar": "T",
 		"SettingStartSleepChar": "M",
@@ -71,10 +71,10 @@
 	"menuGroups": {
 		"PowerMenu": {
 			"text2": [
-				"Power",
+				"Maitinimo",
-				"settings"
+				"nustatymai"
 			],
-			"desc": "Power settings"
+			"desc": "Su maitinblokiu susiję nustatymai"
 		},
 		"SolderingMenu": {
 			"text2": [
@@ -171,7 +171,7 @@
 		},
 		"AutoStart": {
 			"text2": [
-				"Auto",
+				"Automatinis",
 				"paleidimas"
 			],
 			"desc": "Ar pradėti kaitininti iš karto įjungus lituoklį <N=Ne, T=Taip, M=Miegas, K=Miegoti kambario temperatūroje>"
@@ -181,7 +181,7 @@
 				"Atvėsimo",
 				"mirksėjimas"
 			],
-			"desc": "Ar mirksėti temperatūrą ekrane kol vėstantis antgalis vis dar karštas"
+			"desc": "Ar mirksėti temperatūrą ekrane kol vėstantis antgalis vis dar karštas?"
 		},
 		"TemperatureCalibration": {
 			"text2": [
@@ -195,14 +195,14 @@
 				"Atstatyti",
 				"nustatymus?"
 			],
-			"desc": "Nustatyti nustatymus iš naujo"
+			"desc": "Nustato nustatymus į numatytuosius"
 		},
 		"VoltageCalibration": {
 			"text2": [
 				"Kalibruoti",
 				"įvesties įtampą?"
 			],
-			"desc": "Įvesties įtampos kalibravimas. Trumpai paspauskite, norėdami nustatyti, ilgai paspauskite, kad išeitumėte"
+			"desc": "Įvesties įtampos kalibravimas. Trumpai paspauskite, norėdami nustatyti, ilgai paspauskite, kad išeitumėte."
 		},
 		"AdvancedSoldering": {
 			"text2": [
@@ -256,7 +256,7 @@
 		"PowerPulsePower": {
 			"text2": [
 				"Galios",
-				"Pulso W"
+				"pulso W"
 			],
 			"desc": "Periodinis galios pulso intensyvumas maitinblokiui, neleidžiantis jam užmigti."
 		},
@@ -272,46 +272,46 @@
 				"Mygtukų",
 				"užraktas"
 			],
-			"desc": "Lituodami, ilgai paspauskite abu mygtukus, kad juos užrakintumėte <I=Išjungta, T=Tik turbo režimas, V=Visiškas užrakinimas>"
+			"desc": "Lituodami, ilgai paspauskite abu mygtukus, kad juos užrakintumėte <I=Išjungta, T=leidžiamas tik Turbo režimas, V=Visiškas užrakinimas>"
 		},
 		"MinVolCell": {
 			"text2": [
-				"Minimum",
+				"Minimalus",
-				"voltage"
+				"voltažas"
 			],
-			"desc": "Minimum allowed voltage per cell <Volts> <3S: 3.0V - 3.7V, 4/5/6S: 2.4V - 3.7V>"
+			"desc": "Minimalus voltažas, kuris yra leidžiamas kiekvienam baterijos elementui <Voltai> <3S: 3.0V - 3.7V, 4/5/6S: 2.4V - 3.7V>"
 		},
 		"AnimLoop": {
 			"text2": [
-				"Anim.",
+				"Animacijų",
-				"loop"
+				"pakartojimas"
 			],
-			"desc": "Loop icon animations in root menu"
+			"desc": "Leidžia kartoti animacijas be sustojimo pagrindiniame meniu."
 		},
 		"AnimSpeed": {
 			"text2": [
-				"Anim.",
+				"Animacijų",
-				"speed"
+				"greitis"
 			],
-			"desc": "Speed of icon animations in menu <O=off | L=low | M=medium | H=high>"
+			"desc": "Paveiksliukų animacijų greitis meniu punktuose <I=Išjungtas | L=Lėtas | V=Vidutinis | G=Greitas>"
 		},
 		"PowerPulseWait": {
 			"text2": [
-				"Power pulse",
+				"Galios pulso",
-				"wait time"
+				"dažnumas"
 			],
-			"desc": "Time to wait before triggering every keep-awake pulse (x 2.5s)"
+			"desc": "Pasikartojantis laiko intervalas (x 2.5s), ties kuriuo kartojamas galios pulsas maitinblokiui, neleidžiantis jam užmigti."
 		},
 		"PowerPulseDuration": {
 			"text2": [
-				"Power pulse",
+				"Galios pulso",
-				"duration"
+				"trukmė"
 			],
-			"desc": "Keep-awake-pulse duration (x 250ms)"
+			"desc": "Galios pulso aktyvioji trukmė (x 250ms)"
 		},
 		"LanguageSwitch": {
 			"text2": [
-				"Language:",
+				"Kalba:",
 				" LT    Lietuvių"
 			],
 			"desc": ""

source/Core/BSP/BSP.h

@@ -74,6 +74,21 @@ bool getIsPoweredByDCIN();
 // Logs the system state to a debug interface if supported
 void log_system_state(int32_t PWMWattsx10);
 
+// Returns true if the tip is disconnected
+bool isTipDisconnected();
+
+// Status LED controls
+
+enum StatusLED {
+  LED_OFF = 0,           // Turn off status led
+  LED_STANDBY,           // unit is in sleep /standby
+  LED_HEATING,           // The unit is heating up to temperature
+  LED_HOT,               // The unit is at operating temperature
+  LED_COOLING_STILL_HOT, // The unit is off and cooling but still hot
+  LED_UNKNOWN,           //
+};
+void setStatusLED(const enum StatusLED state);
+
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/BSP_PD.h

@@ -8,6 +8,5 @@
 #ifndef USER_BSP_PD_H_
 #define USER_BSP_PD_H_
 #include "BSP.h"
-bool getFUS302IRQLow(); // Return true if the IRQ line is still held low
 
 #endif /* USER_BSP_PD_H_ */

source/Core/BSP/Defines.h

@@ -10,8 +10,6 @@
 #include "FreeRTOSConfig.h"
 enum Orientation { ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3 };
 
-// It is assumed that all hardware implements an 8Hz update period at this time
-#define PID_TIM_HZ   (8)
 #define TICKS_SECOND configTICK_RATE_HZ
 #define TICKS_MIN    (60 * TICKS_SECOND)
 #define TICKS_100MS  (TICKS_SECOND / 10)

source/Core/BSP/MHP30/BSP.cpp

@@ -0,0 +1,462 @@
+// BSP mapping functions
+
+#include "BSP.h"
+#include "I2C_Wrapper.hpp"
+#include "Model_Config.h"
+#include "Pins.h"
+#include "Setup.h"
+#include "TipThermoModel.h"
+#include "Utils.h"
+#include "WS2812.h"
+#include "configuration.h"
+#include "history.hpp"
+#include "main.hpp"
+#include <IRQ.h>
+
+WS2812<GPIOA_BASE, WS2812_Pin, 1> ws2812;
+volatile uint16_t                 PWMSafetyTimer = 0;
+volatile uint8_t                  pendingPWM     = 0;
+uint16_t                          totalPWM       = 255;
+const uint16_t                    powerPWM       = 255;
+
+history<uint16_t, PID_TIM_HZ> rawTempFilter = {{0}, 0, 0};
+void                          resetWatchdog() { HAL_IWDG_Refresh(&hiwdg); }
+
+#ifdef TEMP_NTC
+// Lookup table for the NTC
+// Stored as ADCReading,Temp in degC
+static const uint16_t NTCHandleLookup[] = {
+    // ADC Reading , Temp in Cx10
+    808,   1600, //
+    832,   1590, //
+    848,   1580, //
+    872,   1570, //
+    888,   1560, //
+    912,   1550, //
+    936,   1540, //
+    960,   1530, //
+    984,   1520, //
+    1008,  1510, //
+    1032,  1500, //
+    1056,  1490, //
+    1080,  1480, //
+    1112,  1470, //
+    1136,  1460, //
+    1168,  1450, //
+    1200,  1440, //
+    1224,  1430, //
+    1256,  1420, //
+    1288,  1410, //
+    1328,  1400, //
+    1360,  1390, //
+    1392,  1380, //
+    1432,  1370, //
+    1464,  1360, //
+    1504,  1350, //
+    1544,  1340, //
+    1584,  1330, //
+    1632,  1320, //
+    1672,  1310, //
+    1720,  1300, //
+    1760,  1290, //
+    1808,  1280, //
+    1856,  1270, //
+    1912,  1260, //
+    1960,  1250, //
+    2016,  1240, //
+    2072,  1230, //
+    2128,  1220, //
+    2184,  1210, //
+    2248,  1200, //
+    2304,  1190, //
+    2368,  1180, //
+    2440,  1170, //
+    2504,  1160, //
+    2576,  1150, //
+    2648,  1140, //
+    2720,  1130, //
+    2792,  1120, //
+    2872,  1110, //
+    2952,  1100, //
+    3040,  1090, //
+    3128,  1080, //
+    3216,  1070, //
+    3304,  1060, //
+    3400,  1050, //
+    3496,  1040, //
+    3592,  1030, //
+    3696,  1020, //
+    3800,  1010, //
+    3912,  1000, //
+    4024,  990,  //
+    4136,  980,  //
+    4256,  970,  //
+    4376,  960,  //
+    4504,  950,  //
+    4632,  940,  //
+    4768,  930,  //
+    4904,  920,  //
+    5048,  910,  //
+    5192,  900,  //
+    5336,  890,  //
+    5488,  880,  //
+    5648,  870,  //
+    5808,  860,  //
+    5976,  850,  //
+    6144,  840,  //
+    6320,  830,  //
+    6504,  820,  //
+    6688,  810,  //
+    6872,  800,  //
+    7072,  790,  //
+    7264,  780,  //
+    7472,  770,  //
+    7680,  760,  //
+    7896,  750,  //
+    8112,  740,  //
+    8336,  730,  //
+    8568,  720,  //
+    8800,  710,  //
+    9040,  700,  //
+    9288,  690,  //
+    9536,  680,  //
+    9792,  670,  //
+    10056, 660,  //
+    10320, 650,  //
+    10592, 640,  //
+    10872, 630,  //
+    11152, 620,  //
+    11440, 610,  //
+    11728, 600,  //
+    12024, 590,  //
+    12320, 580,  //
+    12632, 570,  //
+    12936, 560,  //
+    13248, 550,  //
+    13568, 540,  //
+    13888, 530,  //
+    14216, 520,  //
+    14544, 510,  //
+    14880, 500,  //
+    15216, 490,  //
+    15552, 480,  //
+    15888, 470,  //
+    16232, 460,  //
+    16576, 450,  //
+    16920, 440,  //
+    17272, 430,  //
+    17616, 420,  //
+    17968, 410,  //
+    18320, 400,  //
+    18664, 390,  //
+    19016, 380,  //
+    19368, 370,  //
+    19712, 360,  //
+    20064, 350,  //
+    20408, 340,  //
+    20752, 330,  //
+    21088, 320,  //
+    21432, 310,  //
+    21768, 300,  //
+    22096, 290,  //
+    22424, 280,  //
+    22752, 270,  //
+    23072, 260,  //
+    23392, 250,  //
+    23704, 240,  //
+    24008, 230,  //
+    24312, 220,  //
+    24608, 210,  //
+    24904, 200,  //
+    25192, 190,  //
+    25472, 180,  //
+    25744, 170,  //
+    26016, 160,  //
+    26280, 150,  //
+    26536, 140,  //
+    26784, 130,  //
+    27024, 120,  //
+    27264, 110,  //
+    27496, 100,  //
+    27720, 90,   //
+    27936, 80,   //
+    28144, 70,   //
+    28352, 60,   //
+    28544, 50,   //
+    28736, 40,   //
+    28920, 30,   //
+    29104, 20,   //
+    29272, 10,   //
+};
+const int NTCHandleLookupItems = sizeof(NTCHandleLookup) / (2 * sizeof(uint16_t));
+#endif
+
+// These are called by the HAL after the corresponding events from the system
+// timers.
+
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
+  // Period has elapsed
+  if (htim->Instance == TIM4) {
+    // STM uses this for internal functions as a counter for timeouts
+    HAL_IncTick();
+  }
+}
+uint16_t getHandleTemperature() {
+  int32_t result = getADC(0);
+  return Utils::InterpolateLookupTable(NTCHandleLookup, NTCHandleLookupItems, result);
+}
+
+uint16_t getTipInstantTemperature() { return getADC(2); }
+
+uint16_t getTipRawTemp(uint8_t refresh) {
+  if (refresh) {
+    uint16_t lastSample = getTipInstantTemperature();
+    rawTempFilter.update(lastSample);
+    return lastSample;
+  } else {
+    return rawTempFilter.average();
+  }
+}
+
+uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) {
+  // ADC maximum is 32767 == 3.3V at input == 28.05V at VIN
+  // Therefore we can divide down from there
+  // Multiplying ADC max by 4 for additional calibration options,
+  // ideal term is 467
+  static uint8_t  preFillneeded = 10;
+  static uint32_t samples[BATTFILTERDEPTH];
+  static uint8_t  index = 0;
+  if (preFillneeded) {
+    for (uint8_t i = 0; i < BATTFILTERDEPTH; i++)
+      samples[i] = getADC(1);
+    preFillneeded--;
+  }
+  if (sample) {
+    samples[index] = getADC(1);
+    index          = (index + 1) % BATTFILTERDEPTH;
+  }
+  uint32_t sum = 0;
+
+  for (uint8_t i = 0; i < BATTFILTERDEPTH; i++)
+    sum += samples[i];
+
+  sum /= BATTFILTERDEPTH;
+  if (divisor == 0) {
+    divisor = 1;
+  }
+  return sum * 4 / divisor;
+}
+bool tryBetterPWM(uint8_t pwm) {
+  // We dont need this for the MHP30
+  return false;
+}
+void setTipPWM(uint8_t pulse) {
+  // We can just set the timer directly
+  if (htim3.Instance->PSC > 20) {
+    htim3.Instance->CCR1 = 0;
+  } else {
+    htim3.Instance->CCR1 = pulse;
+  }
+}
+
+void unstick_I2C() {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  int              timeout     = 100;
+  int              timeout_cnt = 0;
+
+  // 1. Clear PE bit.
+  hi2c1.Instance->CR1 &= ~(0x0001);
+  /**I2C1 GPIO Configuration
+   PB6     ------> I2C1_SCL
+   PB7     ------> I2C1_SDA
+   */
+  //  2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_OD;
+  GPIO_InitStruct.Pull  = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+
+  GPIO_InitStruct.Pin = SCL_Pin;
+  HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct);
+  HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
+
+  GPIO_InitStruct.Pin = SDA_Pin;
+  HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct);
+  HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET);
+
+  while (GPIO_PIN_SET != HAL_GPIO_ReadPin(SDA_GPIO_Port, SDA_Pin)) {
+    // Move clock to release I2C
+    HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_RESET);
+    asm("nop");
+    asm("nop");
+    asm("nop");
+    asm("nop");
+    HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
+
+    timeout_cnt++;
+    if (timeout_cnt > timeout)
+      return;
+  }
+
+  // 12. Configure the SCL and SDA I/Os as Alternate function Open-Drain.
+  GPIO_InitStruct.Mode  = GPIO_MODE_AF_OD;
+  GPIO_InitStruct.Pull  = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+
+  GPIO_InitStruct.Pin = SCL_Pin;
+  HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = SDA_Pin;
+  HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct);
+
+  HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
+  HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET);
+
+  // 13. Set SWRST bit in I2Cx_CR1 register.
+  hi2c1.Instance->CR1 |= 0x8000;
+
+  asm("nop");
+
+  // 14. Clear SWRST bit in I2Cx_CR1 register.
+  hi2c1.Instance->CR1 &= ~0x8000;
+
+  asm("nop");
+
+  // 15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register
+  hi2c1.Instance->CR1 |= 0x0001;
+
+  // Call initialization function.
+  HAL_I2C_Init(&hi2c1);
+}
+
+uint8_t getButtonA() { return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ? 1 : 0; }
+uint8_t getButtonB() { return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ? 1 : 0; }
+
+void BSPInit(void) { ws2812.init(); }
+
+void reboot() { NVIC_SystemReset(); }
+
+void delay_ms(uint16_t count) { HAL_Delay(count); }
+
+void setPlatePullup(bool pullingUp) {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Pin   = PLATE_SENSOR_PULLUP_Pin;
+  GPIO_InitStruct.Pull  = GPIO_NOPULL;
+  if (pullingUp) {
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    HAL_GPIO_WritePin(PLATE_SENSOR_PULLUP_GPIO_Port, PLATE_SENSOR_PULLUP_Pin, GPIO_PIN_SET);
+  } else {
+    // Hi-z
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    HAL_GPIO_WritePin(PLATE_SENSOR_PULLUP_GPIO_Port, PLATE_SENSOR_PULLUP_Pin, GPIO_PIN_RESET);
+  }
+  HAL_GPIO_Init(PLATE_SENSOR_PULLUP_GPIO_Port, &GPIO_InitStruct);
+}
+
+uint16_t tipSenseResistancex10Ohms = 0;
+bool     isTipDisconnected() {
+  static bool       lastTipDisconnectedState = true;
+  static uint16_t   adcReadingPD1Set         = 0;
+  static TickType_t lastMeas                 = 0;
+  // For the MHP30 we want to include a little extra logic in here
+  // As when the tip is first connected we want to measure the ~100 ohm resistor on the base of the tip
+  // And likewise if its removed we want to clear that measurement
+  /*
+   * plate_sensor_res = ((adc5_value_PD1_set - adc5_value_PD1_cleared) / (adc5_value_PD1_cleared + 4096 - adc5_value_PD1_set)) * 1000.0;
+   * */
+
+  bool tipDisconnected = getADC(2) > (4090 * 8);
+  // We have to handle here that this ^ will trip while measuring the gain resistor
+  if (xTaskGetTickCount() - lastMeas < (TICKS_100MS * 2 + (TICKS_100MS / 2))) {
+    tipDisconnected = false;
+  }
+
+  if (tipDisconnected != lastTipDisconnectedState) {
+    if (tipDisconnected) {
+      // Tip is now disconnected
+      tipSenseResistancex10Ohms = 0; // zero out the resistance
+      adcReadingPD1Set          = 0;
+      lastMeas                  = 0;
+    }
+    lastTipDisconnectedState = tipDisconnected;
+  }
+  if (!tipDisconnected) {
+    if (tipSenseResistancex10Ohms == 0) {
+      if (lastMeas == 0) {
+        lastMeas = xTaskGetTickCount();
+        setPlatePullup(true);
+      } else if (xTaskGetTickCount() - lastMeas > (TICKS_100MS)) {
+        lastMeas = xTaskGetTickCount();
+        // We are sensing the resistance
+        if (adcReadingPD1Set == 0) {
+          // We will record the reading for PD1 being set
+          adcReadingPD1Set = getADC(3);
+          setPlatePullup(false);
+        } else {
+          // We have taken reading one
+          uint16_t adcReadingPD1Cleared = getADC(3);
+          uint32_t a                    = ((int)adcReadingPD1Set - (int)adcReadingPD1Cleared);
+          a *= 10000;
+          uint32_t b = ((int)adcReadingPD1Cleared + (32768 - (int)adcReadingPD1Set));
+          if (b) {
+            tipSenseResistancex10Ohms = a / b;
+          } else {
+            tipSenseResistancex10Ohms = adcReadingPD1Set = lastMeas = 0;
+          }
+          if (tipSenseResistancex10Ohms > 1100 || tipSenseResistancex10Ohms < 900) {
+            tipSenseResistancex10Ohms = 0; // out of range
+            adcReadingPD1Set          = 0;
+            lastMeas                  = 0;
+          }
+        }
+      }
+      return true; // we fake tip being disconnected until this is measured
+    }
+  }
+
+  return tipDisconnected;
+}
+void setBuzzer(bool on) {
+  if (on) {
+    htim3.Instance->CCR2 = 128;
+    htim3.Instance->PSC  = 100; // drop down into audible range
+  } else {
+    htim3.Instance->CCR2 = 0;
+    htim3.Instance->PSC  = 1; // revert back out of hearing range
+  }
+}
+void setStatusLED(const enum StatusLED state) {
+  static enum StatusLED lastState = LED_UNKNOWN;
+  static TickType_t     buzzerEnd = 0;
+
+  if (lastState != state || state == LED_HEATING) {
+    switch (state) {
+    default:
+    case LED_UNKNOWN:
+    case LED_OFF:
+      ws2812.led_set_color(0, 0, 0, 0);
+      break;
+    case LED_STANDBY:
+      ws2812.led_set_color(0, 0, 0xFF, 0); // green
+      break;
+    case LED_HEATING: {
+      ws2812.led_set_color(0, ((HAL_GetTick() / 10) % 192) + 64, 0, 0); // Red fade
+    } break;
+    case LED_HOT:
+      ws2812.led_set_color(0, 0xFF, 0, 0); // red
+      // We have hit the right temp, run buzzer for a short period
+      buzzerEnd = xTaskGetTickCount() + TICKS_SECOND / 3;
+      break;
+    case LED_COOLING_STILL_HOT:
+      ws2812.led_set_color(0, 0xFF, 0x8C, 0x00); // Orange
+      break;
+    }
+    ws2812.led_update();
+    lastState = state;
+  }
+  if (state == LED_HOT && xTaskGetTickCount() < buzzerEnd) {
+    setBuzzer(true);
+  } else {
+    setBuzzer(false);
+  }
+}

source/Core/BSP/MHP30/FreeRTOSConfig.h

@@ -0,0 +1,180 @@
+/*
+ FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ ***************************************************************************
+ >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+ >>!   distribute a combined work that includes FreeRTOS without being   !<<
+ >>!   obliged to provide the source code for proprietary components     !<<
+ >>!   outside of the FreeRTOS kernel.                                   !<<
+ ***************************************************************************
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+ link: http://www.freertos.org/a00114.html
+
+ ***************************************************************************
+ *                                                                       *
+ *    FreeRTOS provides completely free yet professionally developed,    *
+ *    robust, strictly quality controlled, supported, and cross          *
+ *    platform software that is more than just the market leader, it     *
+ *    is the industry's de facto standard.                               *
+ *                                                                       *
+ *    Help yourself get started quickly while simultaneously helping     *
+ *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+ *    tutorial book, reference manual, or both:                          *
+ *    http://www.FreeRTOS.org/Documentation                              *
+ *                                                                       *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+ the FAQ page "My application does not run, what could be wrong?".  Have you
+ defined configASSERT()?
+
+ http://www.FreeRTOS.org/support - In return for receiving this top quality
+ embedded software for free we request you assist our global community by
+ participating in the support forum.
+
+ http://www.FreeRTOS.org/training - Investing in training allows your team to
+ be as productive as possible as early as possible.  Now you can receive
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+ Ltd, and the world's leading authority on the world's leading RTOS.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+ Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and commercial middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* USER CODE BEGIN Includes */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* USER CODE END Includes */
+
+/* Ensure stdint is only used by the compiler, and not the assembler. */
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
+#include <stdint.h>
+extern uint32_t SystemCoreClock;
+#endif
+
+#define configUSE_PREEMPTION                    1
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+#define configUSE_IDLE_HOOK                     1
+#define configUSE_TICK_HOOK                     0
+#define configCPU_CLOCK_HZ                      (SystemCoreClock)
+#define configTICK_RATE_HZ                      ((TickType_t)1000)
+#define configMAX_PRIORITIES                    (6)
+#define configMINIMAL_STACK_SIZE                ((uint16_t)256)
+#define configTOTAL_HEAP_SIZE                   ((size_t)1024 * 14) /*Currently use about 9000*/
+#define configMAX_TASK_NAME_LEN                 (32)
+#define configUSE_16_BIT_TICKS                  0
+#define configUSE_MUTEXES                       1
+#define configQUEUE_REGISTRY_SIZE               8
+#define configUSE_TIMERS                        0
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#define configCHECK_FOR_STACK_OVERFLOW          2 /*Bump this to 2 during development and bug hunting*/
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES           0
+#define configMAX_CO_ROUTINE_PRIORITIES (2)
+
+/* Set the following definitions to 1 to include the API function, or zero
+ to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet            1
+#define INCLUDE_uxTaskPriorityGet           0
+#define INCLUDE_vTaskDelete                 0
+#define INCLUDE_vTaskCleanUpResources       0
+#define INCLUDE_vTaskSuspend                0
+#define INCLUDE_vTaskDelayUntil             0
+#define INCLUDE_vTaskDelay                  1
+#define INCLUDE_xTaskGetSchedulerState      1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 4
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+ function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
+
+/* The highest interrupt priority that can be used by any interrupt service
+ routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+ INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+ PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+ to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+ header file. */
+/* USER CODE BEGIN 1 */
+#define configASSERT(x)       \
+  if ((x) == 0) {             \
+    taskDISABLE_INTERRUPTS(); \
+    for (;;)                  \
+      ;                       \
+  }
+/* USER CODE END 1 */
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+ standard names. */
+#define vPortSVCHandler    SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+
+#if configUSE_TIMERS
+#define configTIMER_TASK_PRIORITY    2
+#define configTIMER_QUEUE_LENGTH     8
+#define configTIMER_TASK_STACK_DEPTH (512 / 4)
+#endif
+#ifdef __cplusplus
+}
+#endif
+#endif /* FREERTOS_CONFIG_H */

source/Core/BSP/MHP30/I2C_Wrapper.cpp

@@ -0,0 +1,91 @@
+/*
+ * FRToSI2C.cpp
+ *
+ *  Created on: 14Apr.,2018
+ *      Author: Ralim
+ */
+#include "BSP.h"
+#include "Setup.h"
+#include <I2C_Wrapper.hpp>
+SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr;
+StaticSemaphore_t FRToSI2C::xSemaphoreBuffer;
+
+void FRToSI2C::CpltCallback() {
+  hi2c1.State = HAL_I2C_STATE_READY; // Force state reset (even if tx error)
+  if (I2CSemaphore) {
+    xSemaphoreGiveFromISR(I2CSemaphore, NULL);
+  }
+}
+
+bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size) {
+
+  if (!lock())
+    return false;
+  if (HAL_I2C_Mem_Read(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT, pData, Size, 500) != HAL_OK) {
+
+    I2C_Unstick();
+    unlock();
+    return false;
+  }
+
+  unlock();
+  return true;
+}
+bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }
+
+uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) {
+  uint8_t tx_data[1];
+  Mem_Read(add, reg, tx_data, 1);
+  return tx_data[0];
+}
+bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size) {
+
+  if (!lock())
+    return false;
+  if (HAL_I2C_Mem_Write(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT, pData, Size, 500) != HAL_OK) {
+
+    I2C_Unstick();
+    unlock();
+    return false;
+  }
+
+  unlock();
+  return true;
+}
+
+bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
+  if (!lock())
+    return false;
+  if (HAL_I2C_Master_Transmit_DMA(&hi2c1, DevAddress, pData, Size) != HAL_OK) {
+    I2C_Unstick();
+    unlock();
+    return false;
+  }
+  return true;
+}
+
+bool FRToSI2C::probe(uint16_t DevAddress) {
+  if (!lock())
+    return false;
+  uint8_t buffer[1];
+  bool    worked = HAL_I2C_Mem_Read(&hi2c1, DevAddress, 0x0F, I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000) == HAL_OK;
+  unlock();
+  return worked;
+}
+
+void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
+
+void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); }
+
+bool FRToSI2C::lock() { return xSemaphoreTake(I2CSemaphore, (TickType_t)50) == pdTRUE; }
+
+bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) {
+  for (int index = 0; index < registersLength; index++) {
+    if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) {
+      return false;
+    }
+    if (registers[index].pause_ms)
+      delay_ms(registers[index].pause_ms);
+  }
+  return true;
+}

source/Core/BSP/MHP30/IRQ.cpp

@@ -0,0 +1,49 @@
+/*
+ * IRQ.c
+ *
+ *  Created on: 30 May 2020
+ *      Author: Ralim
+ */
+
+#include "IRQ.h"
+#include "Pins.h"
+#include "int_n.h"
+
+/*
+ * Catch the IRQ that says that the conversion is done on the temperature
+ * readings coming in Once these have come in we can unblock the PID so that it
+ * runs again
+ */
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) {
+  static uint8_t counter                  = 0;
+  BaseType_t     xHigherPriorityTaskWoken = pdFALSE;
+  if (hadc == &hadc1) {
+    counter++;
+    if (counter % 32 == 0) { // 64 = 128ms, 32 = 64ms
+      if (pidTaskNotification) {
+        vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken);
+        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+      }
+    }
+  }
+}
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
+
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
+  (void)GPIO_Pin;
+  InterruptHandler::irqCallback();
+}
+
+bool getFUS302IRQLow() {
+#ifdef POW_PD
+  // Return true if the IRQ line is still held low
+  return HAL_GPIO_ReadPin(INT_PD_GPIO_Port, INT_PD_Pin) == GPIO_PIN_RESET;
+#else
+  return false;
+#endif
+}

source/Core/BSP/MHP30/IRQ.h

@@ -0,0 +1,32 @@
+/*
+ * Irqs.h
+ *
+ *  Created on: 30 May 2020
+ *      Author: Ralim
+ */
+
+#ifndef BSP_MINIWARE_IRQ_H_
+#define BSP_MINIWARE_IRQ_H_
+
+#include "BSP.h"
+#include "I2C_Wrapper.hpp"
+#include "Setup.h"
+#include "main.hpp"
+#include "stm32f1xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_GPIO_EXTI_Callback(uint16_t);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MINIWARE_IRQ_H_ */

source/Core/BSP/MHP30/Model_Config.h

@@ -0,0 +1,30 @@
+/*
+ * Model_Config.h
+ *
+ *  Created on: 25 Jul 2020
+ *      Author: Ralim
+ */
+
+#ifndef BSP_MINIWARE_MODEL_CONFIG_H_
+#define BSP_MINIWARE_MODEL_CONFIG_H_
+/*
+ * Lookup for mapping features <-> Models
+ */
+
+#ifndef MODEL_MHP30
+#error "No model defined!"
+#endif
+
+#ifdef MODEL_MHP30
+#define ACCEL_MSA
+#define POW_PD
+#define TEMP_NTC
+#define I2C_SOFT
+#define BATTFILTERDEPTH 8
+#define OLED_I2CBB
+#define ACCEL_EXITS_ON_MOVEMENT
+#endif
+#ifdef ACCEL_EXITS_ON_MOVEMENT
+#define NO_SLEEP_MODE
+#endif
+#endif /* BSP_MINIWARE_MODEL_CONFIG_H_ */

source/Core/BSP/MHP30/Pins.h

@@ -0,0 +1,59 @@
+/*
+ * Pins.h
+ *
+ *  Created on: 29 May 2020
+ *      Author: Ralim
+ */
+
+#ifndef BSP_MINIWARE_PINS_H_
+#define BSP_MINIWARE_PINS_H_
+#include "Model_Config.h"
+
+// MHP30 pin map
+#define KEY_B_Pin                     GPIO_PIN_0
+#define KEY_B_GPIO_Port               GPIOB
+#define TMP36_INPUT_Pin               GPIO_PIN_1
+#define TMP36_INPUT_GPIO_Port         GPIOB
+#define TMP36_ADC1_CHANNEL            ADC_CHANNEL_9
+#define TMP36_ADC2_CHANNEL            ADC_CHANNEL_9
+#define TIP_TEMP_Pin                  GPIO_PIN_2
+#define TIP_TEMP_GPIO_Port            GPIOA
+#define TIP_TEMP_ADC1_CHANNEL         ADC_CHANNEL_2
+#define TIP_TEMP_ADC2_CHANNEL         ADC_CHANNEL_2
+#define VIN_Pin                       GPIO_PIN_1
+#define VIN_GPIO_Port                 GPIOA
+#define VIN_ADC1_CHANNEL              ADC_CHANNEL_1
+#define VIN_ADC2_CHANNEL              ADC_CHANNEL_1
+#define OLED_RESET_Pin                GPIO_PIN_4
+#define OLED_RESET_GPIO_Port          GPIOB
+#define KEY_A_Pin                     GPIO_PIN_10
+#define KEY_A_GPIO_Port               GPIOA
+#define PWM_Out_Pin                   GPIO_PIN_6
+#define PWM_Out_GPIO_Port             GPIOA
+#define PWM_Out_CHANNEL               TIM_CHANNEL_1
+#define BUZZER_Pin                    GPIO_PIN_7
+#define BUZZER_GPIO_Port              GPIOA
+#define BUZZER_CHANNEL                TIM_CHANNEL_2
+#define SCL_Pin                       GPIO_PIN_6
+#define SCL_GPIO_Port                 GPIOB
+#define SDA_Pin                       GPIO_PIN_7
+#define SDA_GPIO_Port                 GPIOB
+#define SCL2_Pin                      GPIO_PIN_3
+#define SCL2_GPIO_Port                GPIOB
+#define SDA2_Pin                      GPIO_PIN_15
+#define SDA2_GPIO_Port                GPIOA
+#define INT_PD_Pin                    GPIO_PIN_5
+#define INT_PD_GPIO_Port              GPIOB
+#define HEAT_EN_Pin                   GPIO_PIN_3
+#define HEAT_EN_GPIO_Port             GPIOA
+#define PLATE_SENSOR_PULLUP_Pin       GPIO_PIN_1
+#define PLATE_SENSOR_PULLUP_GPIO_Port GPIOD
+
+#define PLATE_SENSOR_Pin          GPIO_PIN_5
+#define PLATE_SENSOR_GPIO_Port    GPIOA
+#define PLATE_SENSOR_ADC1_CHANNEL ADC_CHANNEL_5
+#define PLATE_SENSOR_ADC2_CHANNEL ADC_CHANNEL_5
+
+#define WS2812_Pin       GPIO_PIN_8
+#define WS2812_GPIO_Port GPIOA
+#endif /* BSP_MINIWARE_PINS_H_ */

source/Core/BSP/MHP30/Power.cpp

@@ -0,0 +1,44 @@
+#include "BSP.h"
+#include "BSP_Power.h"
+#include "Model_Config.h"
+#include "Pins.h"
+#include "QC3.h"
+#include "Settings.h"
+#include "fusb_user.h"
+#include "fusbpd.h"
+#include "int_n.h"
+#include "policy_engine.h"
+bool FUSB302_present = false;
+bool FUSB302_probed  = false;
+
+void power_check() {
+#ifdef POW_PD
+  if (FUSB302_present) {
+    PolicyEngine::PPSTimerCallback();
+    // Cant start QC until either PD works or fails
+    if (PolicyEngine::setupCompleteOrTimedOut() == false) {
+      return;
+    }
+    if (PolicyEngine::pdHasNegotiated()) {
+      return;
+    }
+  }
+#endif
+#ifdef POW_QC
+  QC_resync();
+#endif
+}
+uint8_t usb_pd_detect() {
+#ifdef POW_PD
+  if (FUSB302_probed) {
+    return FUSB302_present;
+  } else {
+    FUSB302_present = fusb302_detect();
+    FUSB302_probed  = true;
+  }
+  return FUSB302_present;
+#endif
+  return false;
+}
+
+bool getIsPoweredByDCIN() { return false; }

source/Core/BSP/MHP30/QC_GPIO.cpp

@@ -0,0 +1,76 @@
+/*
+ * QC.c
+ *
+ *  Created on: 29 May 2020
+ *      Author: Ralim
+ */
+#include "BSP.h"
+#include "Model_Config.h"
+#include "Pins.h"
+#include "QC3.h"
+#include "Settings.h"
+#include "stm32f1xx_hal.h"
+#ifdef POW_QC
+void QC_DPlusZero_Six() {
+  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_RESET); // pull down D+
+}
+void QC_DNegZero_Six() {
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET);
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET);
+}
+void QC_DPlusThree_Three() {
+  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_SET); // pull up D+
+}
+void QC_DNegThree_Three() {
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET);
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_SET);
+}
+void QC_DM_PullDown() {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Mode  = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull  = GPIO_PULLDOWN;
+  GPIO_InitStruct.Pin   = GPIO_PIN_11;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+void QC_DM_No_PullDown() {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Mode  = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull  = GPIO_NOPULL;
+  GPIO_InitStruct.Pin   = GPIO_PIN_11;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+void QC_Init_GPIO() {
+  // Setup any GPIO into the right states for QC
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Pin   = GPIO_PIN_3;
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Pin  = GPIO_PIN_8 | GPIO_PIN_10;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+  // Turn off output mode on pins that we can
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Pin  = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_13;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+void QC_Post_Probe_En() {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin   = GPIO_PIN_8 | GPIO_PIN_10;
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+
+uint8_t QC_DM_PulledDown() { return HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11) == GPIO_PIN_RESET ? 1 : 0; }
+#endif
+void QC_resync() {
+#ifdef POW_QC
+  seekQC((systemSettings.QCIdealVoltage) ? 120 : 90,
+         systemSettings.voltageDiv); // Run the QC seek again if we have drifted too much
+#endif
+}

source/Core/BSP/MHP30/README.md

@@ -0,0 +1,12 @@
+# BSP section for STM32F103 based Miniware products
+
+This folder contains the hardware abstractions required for the TS100, TS80 and probably TS80P soldering irons.
+
+## Main abstractions
+
+* Hardware Init
+* -> Should contain all bootstrap to bring the hardware up to an operating point
+* -> Two functions are required, a pre and post FreeRToS call
+* I2C read/write
+* Set PWM for the tip
+* Links between IRQ's on the system and the calls in the rest of the firmware

source/Core/BSP/MHP30/Setup.c

@@ -0,0 +1,388 @@
+/*
+ * Setup.c
+ *
+ *  Created on: 29Aug.,2017
+ *      Author: Ben V. Brown
+ */
+#include "Setup.h"
+#include "Pins.h"
+#include <string.h>
+ADC_HandleTypeDef hadc1;
+ADC_HandleTypeDef hadc2;
+DMA_HandleTypeDef hdma_adc1;
+
+I2C_HandleTypeDef hi2c1;
+DMA_HandleTypeDef hdma_i2c1_rx;
+DMA_HandleTypeDef hdma_i2c1_tx;
+
+IWDG_HandleTypeDef hiwdg;
+TIM_HandleTypeDef  htim2;
+TIM_HandleTypeDef  htim3;
+#define ADC_CHANNELS 4
+#define ADC_SAMPLES  16
+uint32_t ADCReadings[ADC_SAMPLES * ADC_CHANNELS]; // room for 32 lots of the pair of readings
+
+// Functions
+static void SystemClock_Config(void);
+static void MX_ADC1_Init(void);
+static void MX_I2C1_Init(void);
+static void MX_IWDG_Init(void);
+static void MX_TIM3_Init(void);
+static void MX_TIM2_Init(void);
+static void MX_DMA_Init(void);
+static void MX_GPIO_Init(void);
+static void MX_ADC2_Init(void);
+void        Setup_HAL() {
+  SystemClock_Config();
+
+  __HAL_AFIO_REMAP_SWJ_NOJTAG();
+
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_I2C1_Init();
+  MX_ADC1_Init();
+  MX_ADC2_Init();
+  MX_TIM3_Init();
+  MX_TIM2_Init();
+  MX_IWDG_Init();
+  HAL_ADC_Start(&hadc2);
+  HAL_ADCEx_MultiModeStart_DMA(&hadc1, ADCReadings,
+                               (ADC_SAMPLES * ADC_CHANNELS)); // start DMA of normal readings
+                                                              //	HAL_ADCEx_InjectedStart(&hadc1);                 // enable injected readings
+                                                              //	HAL_ADCEx_InjectedStart(&hadc2);                 // enable injected readings
+}
+
+// channel 0 -> temperature sensor, 1-> VIN, 2-> tip
+uint16_t getADC(uint8_t channel) {
+  uint32_t sum = 0;
+  for (uint8_t i = 0; i < ADC_SAMPLES; i++) {
+    uint16_t adc1Sample = ADCReadings[channel + (i * ADC_CHANNELS)];
+    uint16_t adc2Sample = ADCReadings[channel + (i * ADC_CHANNELS)] >> 16;
+
+    sum += (adc1Sample + adc2Sample);
+  }
+  return sum >> 2;
+}
+
+/** System Clock Configuration
+ */
+void SystemClock_Config(void) {
+  RCC_OscInitTypeDef       RCC_OscInitStruct;
+  RCC_ClkInitTypeDef       RCC_ClkInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInit;
+
+  /**Initializes the CPU, AHB and APB busses clocks
+   */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI;
+  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.LSIState            = RCC_LSI_ON;
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64MHz
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /**Initializes the CPU, AHB and APB busses clocks
+   */
+  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // TIM
+                                                    // 2,3,4,5,6,7,12,13,14
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 mhz to some peripherals and adc
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+  PeriphClkInit.AdcClockSelection    = RCC_CFGR_ADCPRE_DIV8; // 6 or 8 are the only non overclocked options
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+  /**Configure the Systick interrupt time
+   */
+  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
+
+  /**Configure the Systick
+   */
+  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+
+  /* SysTick_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
+}
+
+/* ADC1 init function */
+static void MX_ADC1_Init(void) {
+  ADC_MultiModeTypeDef multimode;
+
+  ADC_ChannelConfTypeDef sConfig;
+  /**Common config
+   */
+  hadc1.Instance                   = ADC1;
+  hadc1.Init.ScanConvMode          = ADC_SCAN_ENABLE;
+  hadc1.Init.ContinuousConvMode    = ENABLE;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
+  hadc1.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.NbrOfConversion       = ADC_CHANNELS;
+  HAL_ADC_Init(&hadc1);
+
+  /**Configure the ADC multi-mode
+   */
+  multimode.Mode = ADC_DUALMODE_REGSIMULT_INJECSIMULT;
+  HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode);
+
+  /**Configure Regular Channel
+   */
+  sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
+
+  sConfig.Channel = TMP36_ADC1_CHANNEL;
+  sConfig.Rank    = ADC_REGULAR_RANK_1;
+  HAL_ADC_ConfigChannel(&hadc1, &sConfig);
+
+  /**Configure Regular Channel
+   */
+  sConfig.Channel = VIN_ADC1_CHANNEL;
+  sConfig.Rank    = ADC_REGULAR_RANK_2;
+  HAL_ADC_ConfigChannel(&hadc1, &sConfig);
+
+  sConfig.Channel = TIP_TEMP_ADC1_CHANNEL;
+  sConfig.Rank    = ADC_REGULAR_RANK_3;
+  HAL_ADC_ConfigChannel(&hadc1, &sConfig);
+
+  sConfig.Channel = PLATE_SENSOR_ADC1_CHANNEL;
+  sConfig.Rank    = ADC_REGULAR_RANK_4;
+  HAL_ADC_ConfigChannel(&hadc1, &sConfig);
+
+  SET_BIT(hadc1.Instance->CR1, (ADC_CR1_EOSIE)); // Enable end of Normal
+  // Run ADC internal calibration
+  while (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK)
+    ;
+}
+
+/* ADC2 init function */
+static void MX_ADC2_Init(void) {
+  ADC_ChannelConfTypeDef sConfig;
+
+  /**Common config
+   */
+  hadc2.Instance                   = ADC2;
+  hadc2.Init.ScanConvMode          = ADC_SCAN_ENABLE;
+  hadc2.Init.ContinuousConvMode    = ENABLE;
+  hadc2.Init.DiscontinuousConvMode = DISABLE;
+  hadc2.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
+  hadc2.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+  hadc2.Init.NbrOfConversion       = ADC_CHANNELS;
+  HAL_ADC_Init(&hadc2);
+  sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
+
+  /**Configure Regular Channel
+   */
+  sConfig.Channel = TMP36_ADC2_CHANNEL;
+  sConfig.Rank    = ADC_REGULAR_RANK_1;
+  HAL_ADC_ConfigChannel(&hadc2, &sConfig);
+
+  sConfig.Channel = VIN_ADC2_CHANNEL;
+  sConfig.Rank    = ADC_REGULAR_RANK_2;
+  HAL_ADC_ConfigChannel(&hadc2, &sConfig);
+  sConfig.Channel = TIP_TEMP_ADC1_CHANNEL;
+  sConfig.Rank    = ADC_REGULAR_RANK_3;
+  HAL_ADC_ConfigChannel(&hadc2, &sConfig);
+  sConfig.Channel = PLATE_SENSOR_ADC2_CHANNEL;
+  sConfig.Rank    = ADC_REGULAR_RANK_4;
+  HAL_ADC_ConfigChannel(&hadc2, &sConfig);
+
+  // Run ADC internal calibration
+  while (HAL_ADCEx_Calibration_Start(&hadc2) != HAL_OK)
+    ;
+}
+/* I2C1 init function */
+static void MX_I2C1_Init(void) {
+  hi2c1.Instance             = I2C1;
+  hi2c1.Init.ClockSpeed      = 300000;
+  hi2c1.Init.DutyCycle       = I2C_DUTYCYCLE_2;
+  hi2c1.Init.OwnAddress1     = 0;
+  hi2c1.Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;
+  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c1.Init.OwnAddress2     = 0;
+  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c1.Init.NoStretchMode   = I2C_NOSTRETCH_DISABLE;
+  HAL_I2C_Init(&hi2c1);
+}
+
+/* IWDG init function */
+static void MX_IWDG_Init(void) {
+  hiwdg.Instance       = IWDG;
+  hiwdg.Init.Prescaler = IWDG_PRESCALER_256;
+  hiwdg.Init.Reload    = 100;
+#ifndef SWD_ENABLE
+  HAL_IWDG_Init(&hiwdg);
+#endif
+}
+
+/* TIM3 init function */
+static void MX_TIM3_Init(void) {
+  TIM_ClockConfigTypeDef  sClockSourceConfig;
+  TIM_MasterConfigTypeDef sMasterConfig;
+  TIM_OC_InitTypeDef      sConfigOC;
+  memset(&sClockSourceConfig, 0, sizeof(sClockSourceConfig));
+  memset(&sMasterConfig, 0, sizeof(sMasterConfig));
+  memset(&sConfigOC, 0, sizeof(sConfigOC));
+  htim3.Instance               = TIM3;
+  htim3.Init.Prescaler         = 1;
+  htim3.Init.CounterMode       = TIM_COUNTERMODE_UP;
+  htim3.Init.Period            = 255;                           //
+  htim3.Init.ClockDivision     = TIM_CLOCKDIVISION_DIV1;        // 4mhz before div
+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; // Preload the ARR register (though we dont use this)
+  HAL_TIM_Base_Init(&htim3);
+
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig);
+
+  HAL_TIM_PWM_Init(&htim3);
+
+  HAL_TIM_OC_Init(&htim3);
+
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode     = TIM_MASTERSLAVEMODE_DISABLE;
+  HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig);
+
+  sConfigOC.OCMode     = TIM_OCMODE_PWM1;
+  sConfigOC.Pulse      = 0; // Output control
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
+  HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, PWM_Out_CHANNEL);
+  HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, BUZZER_CHANNEL);
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  /**TIM3 GPIO Configuration
+   PWM_Out_Pin     ------> TIM3_CH1
+   */
+  GPIO_InitStruct.Pin   = PWM_Out_Pin | BUZZER_Pin;
+  GPIO_InitStruct.Mode  = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // We would like sharp rising edges
+  HAL_GPIO_Init(PWM_Out_GPIO_Port, &GPIO_InitStruct);
+  HAL_TIM_PWM_Start(&htim3, PWM_Out_CHANNEL);
+  HAL_TIM_PWM_Start(&htim3, BUZZER_CHANNEL);
+}
+/* TIM3 init function */
+static void MX_TIM2_Init(void) {
+
+  TIM_ClockConfigTypeDef  sClockSourceConfig;
+  TIM_MasterConfigTypeDef sMasterConfig;
+  TIM_OC_InitTypeDef      sConfigOC;
+
+  htim2.Instance       = TIM2;
+  htim2.Init.Prescaler = 200; // 2 MHz timer clock/2000 = 1 kHz tick rate
+
+  // pwm out is 10k from tim3, we want to run our PWM at around 10hz or slower on the output stage
+  // These values give a rate of around 3.5 Hz for "fast" mode and 1.84 Hz for "slow"
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  // dummy value, will be reconfigured by BSPInit()
+  htim2.Init.Period            = 10;
+  htim2.Init.ClockDivision     = TIM_CLOCKDIVISION_DIV1; // 8 MHz (x2 APB1) before divide
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  htim2.Init.RepetitionCounter = 0;
+  HAL_TIM_Base_Init(&htim2);
+
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig);
+
+  HAL_TIM_PWM_Init(&htim2);
+
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode     = TIM_MASTERSLAVEMODE_DISABLE;
+  HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig);
+
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+  // dummy value, will be reconfigured by BSPInit() in the BSP.cpp
+  sConfigOC.Pulse      = 5;
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
+  HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4);
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Pin   = HEAT_EN_Pin;
+  GPIO_InitStruct.Mode  = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // We would like sharp rising edges
+  HAL_GPIO_Init(HEAT_EN_GPIO_Port, &GPIO_InitStruct);
+  HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);
+}
+
+/**
+ * Enable DMA controller clock
+ */
+static void MX_DMA_Init(void) {
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 10, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel6_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn);
+  /* DMA1_Channel7_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
+}
+
+static void MX_GPIO_Init(void) {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct));
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET);
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  /*Configure GPIO pins : PD0 PD1 */
+  GPIO_InitStruct.Pin  = GPIO_PIN_0 | GPIO_PIN_1;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+  /*Configure peripheral I/O remapping */
+  __HAL_AFIO_REMAP_PD01_ENABLE();
+  //^ remap XTAL so that pins used
+
+  /*
+   * Configure All pins as analog by default
+   */
+  GPIO_InitStruct.Pin  = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_10 | GPIO_PIN_15;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12
+                        | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : KEY_B_Pin KEY_A_Pin */
+  GPIO_InitStruct.Pin  = KEY_B_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  HAL_GPIO_Init(KEY_B_GPIO_Port, &GPIO_InitStruct);
+  GPIO_InitStruct.Pin  = KEY_A_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  HAL_GPIO_Init(KEY_A_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : OLED_RESET_Pin */
+  GPIO_InitStruct.Pin   = OLED_RESET_Pin;
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(OLED_RESET_GPIO_Port, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin   = WS2812_Pin;
+  GPIO_InitStruct.Pull  = GPIO_NOPULL;
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(WS2812_GPIO_Port, &GPIO_InitStruct);
+  HAL_GPIO_WritePin(WS2812_GPIO_Port, WS2812_Pin, GPIO_PIN_RESET);
+  // Pull down LCD reset
+  HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET);
+  HAL_Delay(30);
+  HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_SET);
+}
+
+#ifdef USE_FULL_ASSERT
+void assert_failed(uint8_t *file, uint32_t line) { asm("bkpt"); }
+#endif

source/Core/BSP/MHP30/Setup.h

@@ -0,0 +1,40 @@
+/*
+ * Setup.h
+ *
+ *  Created on: 29Aug.,2017
+ *      Author: Ben V. Brown
+ */
+
+#ifndef SETUP_H_
+#define SETUP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stm32f1xx_hal.h"
+
+extern ADC_HandleTypeDef hadc1;
+extern ADC_HandleTypeDef hadc2;
+extern DMA_HandleTypeDef hdma_adc1;
+
+extern DMA_HandleTypeDef hdma_i2c1_rx;
+extern DMA_HandleTypeDef hdma_i2c1_tx;
+extern I2C_HandleTypeDef hi2c1;
+
+extern IWDG_HandleTypeDef hiwdg;
+
+extern TIM_HandleTypeDef htim1;
+extern DMA_HandleTypeDef hdma_tim1_ch1;
+extern TIM_HandleTypeDef htim2;
+extern TIM_HandleTypeDef htim3;
+void                     Setup_HAL();
+uint16_t                 getADC(uint8_t channel);
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); // Since the hal header file does not define this one
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SETUP_H_ */

source/Core/BSP/MHP30/Software_I2C.h

@@ -0,0 +1,30 @@
+/*
+ * Software_I2C.h
+ *
+ *  Created on: 25 Jul 2020
+ *      Author: Ralim
+ */
+
+#ifndef BSP_MINIWARE_SOFTWARE_I2C_H_
+#define BSP_MINIWARE_SOFTWARE_I2C_H_
+#include "BSP.h"
+#include "Model_Config.h"
+#include "stm32f1xx_hal.h"
+#ifdef I2C_SOFT
+
+#define SOFT_SCL_HIGH() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_SET)
+#define SOFT_SCL_LOW()  HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_RESET)
+#define SOFT_SDA_HIGH() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_SET)
+#define SOFT_SDA_LOW()  HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET)
+#define SOFT_SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port, SDA2_Pin) == GPIO_PIN_SET ? 1 : 0)
+#define SOFT_SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port, SCL2_Pin) == GPIO_PIN_SET ? 1 : 0)
+#define SOFT_I2C_DELAY()              \
+  {                                   \
+    for (int xx = 0; xx < 20; xx++) { \
+      asm("nop");                     \
+    }                                 \
+  }
+
+#endif
+
+#endif /* BSP_MINIWARE_SOFTWARE_I2C_H_ */

source/Core/BSP/MHP30/ThermoModel.cpp

@@ -0,0 +1,22 @@
+/*
+ * ThermoModel.cpp
+ *
+ *  Created on: 1 May 2021
+ *      Author: Ralim
+ */
+#include "Setup.h"
+#include "TipThermoModel.h"
+#include "Utils.h"
+#include "configuration.h"
+extern uint16_t tipSenseResistancex10Ohms;
+uint32_t        TipThermoModel::convertuVToDegC(uint32_t tipuVDelta) {
+  // For the MHP30, we are mimicing the original code and using the resistor fitted to the base of the heater head, this is measured in the isTipDisconnected() function
+  if (tipSenseResistancex10Ohms > 900 && tipSenseResistancex10Ohms <= 1100) {
+    int32_t a = ((tipSenseResistancex10Ohms / 10) + 300) * (3300000 - tipuVDelta);
+    int32_t b = a / 1000000;
+    int32_t c = tipuVDelta - b;
+    int32_t d = c * 243 / 1000;
+    return d / 10;
+  }
+  return 0xFFFF;
+}

source/Core/BSP/MHP30/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h

@@ -0,0 +1,198 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx.h
+ * @author  MCD Application Team
+ * @brief   CMSIS STM32F1xx Device Peripheral Access Layer Header File.
+ *
+ *          The file is the unique include file that the application programmer
+ *          is using in the C source code, usually in main.c. This file contains:
+ *            - Configuration section that allows to select:
+ *              - The STM32F1xx device used in the target application
+ *              - To use or not the peripheral<61>s drivers in application code(i.e.
+ *                code will be based on direct access to peripheral<61>s registers
+ *                rather than drivers API), this option is controlled by
+ *                "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx
+ * @{
+ */
+
+#ifndef __STM32F1XX_H
+#define __STM32F1XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined(STM32F1)
+#define STM32F1
+#endif /* STM32F1 */
+
+/* Uncomment the line below according to the target STM32L device used in your
+   application
+  */
+
+#if !defined(STM32F100xB) && !defined(STM32F100xE) && !defined(STM32F101x6) && !defined(STM32F101xB) && !defined(STM32F101xE) && !defined(STM32F101xG) && !defined(STM32F102x6) \
+    && !defined(STM32F102xB) && !defined(STM32F103x6) && !defined(STM32F103xB) && !defined(STM32F103xE) && !defined(STM32F103xG) && !defined(STM32F105xC) && !defined(STM32F107xC)
+/* #define STM32F100xB  */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
+/* #define STM32F100xE */  /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
+/* #define STM32F101x6  */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
+/* #define STM32F101xB  */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
+/* #define STM32F101xE */  /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
+/* #define STM32F101xG  */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
+/* #define STM32F102x6 */  /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
+/* #define STM32F102xB  */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
+/* #define STM32F103x6  */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
+/* #define STM32F103xB  */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
+/* #define STM32F103xE */  /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
+/* #define STM32F103xG  */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
+/* #define STM32F105xC */  /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
+/* #define STM32F107xC  */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined(USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+/*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V4.3.2
+ */
+#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
+#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
+#define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8]  sub2 version */
+#define __STM32F1_CMSIS_VERSION_RC   (0x00) /*!< [7:0]  release candidate */
+#define __STM32F1_CMSIS_VERSION      ((__STM32F1_CMSIS_VERSION_MAIN << 24) | (__STM32F1_CMSIS_VERSION_SUB1 << 16) | (__STM32F1_CMSIS_VERSION_SUB2 << 8) | (__STM32F1_CMSIS_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F100xB)
+#include "stm32f100xb.h"
+#elif defined(STM32F100xE)
+#include "stm32f100xe.h"
+#elif defined(STM32F101x6)
+#include "stm32f101x6.h"
+#elif defined(STM32F101xB)
+#include "stm32f101xb.h"
+#elif defined(STM32F101xE)
+#include "stm32f101xe.h"
+#elif defined(STM32F101xG)
+#include "stm32f101xg.h"
+#elif defined(STM32F102x6)
+#include "stm32f102x6.h"
+#elif defined(STM32F102xB)
+#include "stm32f102xb.h"
+#elif defined(STM32F103x6)
+#include "stm32f103x6.h"
+#elif defined(STM32F103xB)
+#include "stm32f103xb.h"
+#elif defined(STM32F103xE)
+#include "stm32f103xe.h"
+#elif defined(STM32F103xG)
+#include "stm32f103xg.h"
+#elif defined(STM32F105xC)
+#include "stm32f105xc.h"
+#elif defined(STM32F107xC)
+#include "stm32f107xc.h"
+#else
+#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
+
+typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum { SUCCESS = 0U, ERROR = !SUCCESS } ErrorStatus;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+/**
+ * @}
+ */
+
+#if defined(USE_HAL_DRIVER)
+#include "stm32f1xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F1xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h

@@ -0,0 +1,97 @@
+/**
+ ******************************************************************************
+ * @file    system_stm32f10x.h
+ * @author  MCD Application Team
+ * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern uint32_t      SystemCoreClock;    /*!< System Clock Frequency (Core Clock) */
+extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8U];  /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_armcc.h

@@ -0,0 +1,764 @@
+/**************************************************************************/ /**
+                                                                              * @file     cmsis_armcc.h
+                                                                              * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+                                                                              * @version  V5.0.4
+                                                                              * @date     10. January 2018
+                                                                              ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined(__TARGET_ARCH_6_M) && (__TARGET_ARCH_6_M == 1)) || (defined(__TARGET_ARCH_6S_M) && (__TARGET_ARCH_6S_M == 1)))
+#define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined(__TARGET_ARCH_7_M) && (__TARGET_ARCH_7_M == 1))
+#define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined(__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+#define __ARM_ARCH_7EM__ 1
+#endif
+
+/* __ARM_ARCH_8M_BASE__  not applicable */
+/* __ARM_ARCH_8M_MAIN__  not applicable */
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+#define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+#define __RESTRICT __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void) {
+  register uint32_t __regControl __ASM("control");
+  return (__regControl);
+}
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control) {
+  register uint32_t __regControl __ASM("control");
+  __regControl = control;
+}
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void) {
+  register uint32_t __regIPSR __ASM("ipsr");
+  return (__regIPSR);
+}
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void) {
+  register uint32_t __regAPSR __ASM("apsr");
+  return (__regAPSR);
+}
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void) {
+  register uint32_t __regXPSR __ASM("xpsr");
+  return (__regXPSR);
+}
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void) {
+  register uint32_t __regProcessStackPointer __ASM("psp");
+  return (__regProcessStackPointer);
+}
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) {
+  register uint32_t __regProcessStackPointer __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void) {
+  register uint32_t __regMainStackPointer __ASM("msp");
+  return (__regMainStackPointer);
+}
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) {
+  register uint32_t __regMainStackPointer __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void) {
+  register uint32_t __regPriMask __ASM("primask");
+  return (__regPriMask);
+}
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) {
+  register uint32_t __regPriMask __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)))
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void) {
+  register uint32_t __regBasePri __ASM("basepri");
+  return (__regBasePri);
+}
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) {
+  register uint32_t __regBasePri __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) {
+  register uint32_t __regBasePriMax __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void) {
+  register uint32_t __regFaultMask __ASM("faultmask");
+  return (__regFaultMask);
+}
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) {
+  register uint32_t __regFaultMask __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void) {
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U)))
+  register uint32_t __regfpscr __ASM("fpscr");
+  return (__regfpscr);
+#else
+  return (0U);
+#endif
+}
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) {
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U)))
+  register uint32_t __regfpscr __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()           \
+  do {                    \
+    __schedule_barrier(); \
+    __isb(0xF);           \
+    __schedule_barrier(); \
+  } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()           \
+  do {                    \
+    __schedule_barrier(); \
+    __dsb(0xF);           \
+    __schedule_barrier(); \
+  } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()           \
+  do {                    \
+    __schedule_barrier(); \
+    __dmb(0xF);           \
+    __schedule_barrier(); \
+  } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV __rev
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr }
+#endif
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) { revsh r0, r0 bx lr }
+#endif
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR __ror
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)))
+#define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value; /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U) {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s; /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)))
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXB(ptr) ((uint8_t)__ldrex(ptr))
+#else
+#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXH(ptr) ((uint16_t)__ldrex(ptr))
+#else
+#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXW(ptr) ((uint32_t)__ldrex(ptr))
+#else
+#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXB(value, ptr) __strex(value, ptr)
+#else
+#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#else
+#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXW(value, ptr) __strex(value, ptr)
+#else
+#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT __ssat
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT __usat
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr }
+#endif
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+          (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) {
+  if ((sat >= 1U) && (sat <= 32U)) {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max;
+    if (val > max) {
+      return max;
+    } else if (val < min) {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) {
+  if (sat <= 31U) {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max) {
+      return max;
+    } else if (val < 0) {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)))
+
+#define __SADD8   __sadd8
+#define __QADD8   __qadd8
+#define __SHADD8  __shadd8
+#define __UADD8   __uadd8
+#define __UQADD8  __uqadd8
+#define __UHADD8  __uhadd8
+#define __SSUB8   __ssub8
+#define __QSUB8   __qsub8
+#define __SHSUB8  __shsub8
+#define __USUB8   __usub8
+#define __UQSUB8  __uqsub8
+#define __UHSUB8  __uhsub8
+#define __SADD16  __sadd16
+#define __QADD16  __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16  __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16  __ssub16
+#define __QSUB16  __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16  __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX    __sasx
+#define __QASX    __qasx
+#define __SHASX   __shasx
+#define __UASX    __uasx
+#define __UQASX   __uqasx
+#define __UHASX   __uhasx
+#define __SSAX    __ssax
+#define __QSAX    __qsax
+#define __SHSAX   __shsax
+#define __USAX    __usax
+#define __UQSAX   __uqsax
+#define __UHSAX   __uhsax
+#define __USAD8   __usad8
+#define __USADA8  __usada8
+#define __SSAT16  __ssat16
+#define __USAT16  __usat16
+#define __UXTB16  __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16  __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD   __smuad
+#define __SMUADX  __smuadx
+#define __SMLAD   __smlad
+#define __SMLADX  __smladx
+#define __SMLALD  __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD   __smusd
+#define __SMUSDX  __smusdx
+#define __SMLSD   __smlsd
+#define __SMLSDX  __smlsdx
+#define __SMLSLD  __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL     __sel
+#define __QADD    __qadd
+#define __QSUB    __qsub
+
+#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))
+
+#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))
+
+#define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U)) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+#endif /* __CMSIS_ARMCC_H */

source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_compiler.h

@@ -0,0 +1,263 @@
+/**************************************************************************/ /**
+                                                                              * @file     cmsis_compiler.h
+                                                                              * @brief    CMSIS compiler generic header file
+                                                                              * @version  V5.0.4
+                                                                              * @date     10. January 2018
+                                                                              ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined(__CC_ARM)
+#include "cmsis_armcc.h"
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armclang.h"
+
+/*
+ * GNU Compiler
+ */
+#elif defined(__GNUC__)
+#include "cmsis_gcc.h"
+
+/*
+ * IAR Compiler
+ */
+#elif defined(__ICCARM__)
+#include <cmsis_iccarm.h>
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined(__TI_ARM__)
+#include <cmsis_ccs.h>
+
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE __STATIC_INLINE
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+#define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __attribute__((packed))
+#endif
+#ifndef __PACKED_UNION
+#define __PACKED_UNION union __attribute__((packed))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+struct __attribute__((packed)) T_UINT32 {
+  uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+#define __RESTRICT
+#endif
+
+/*
+ * TASKING Compiler
+ */
+#elif defined(__TASKING__)
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#ifndef __ASM
+#define __ASM __asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE __STATIC_INLINE
+#endif
+#ifndef __NO_RETURN
+#define __NO_RETURN __attribute__((noreturn))
+#endif
+#ifndef __USED
+#define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+#define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+#define __PACKED __packed__
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT struct __packed__
+#endif
+#ifndef __PACKED_UNION
+#define __PACKED_UNION union __packed__
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+struct __packed__ T_UINT32 {
+  uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+#define __ALIGNED(x) __align(x)
+#endif
+#ifndef __RESTRICT
+#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+#define __RESTRICT
+#endif
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined(__CSMC__)
+#include <cmsis_csm.h>
+
+#ifndef __ASM
+#define __ASM _asm
+#endif
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE __STATIC_INLINE
+#endif
+#ifndef __NO_RETURN
+// NO RETURN is automatically detected hence no warning here
+#define __NO_RETURN
+#endif
+#ifndef __USED
+#warning No compiler specific solution for __USED. __USED is ignored.
+#define __USED
+#endif
+#ifndef __WEAK
+#define __WEAK __weak
+#endif
+#ifndef __PACKED
+#define __PACKED @packed
+#endif
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT @packed struct
+#endif
+#ifndef __PACKED_UNION
+#define __PACKED_UNION @packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+@packed struct T_UINT32 {
+  uint32_t v;
+};
+#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#ifndef __RESTRICT
+#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+#define __RESTRICT
+#endif
+
+#else
+#error Unknown compiler.
+#endif
+
+#endif /* __CMSIS_COMPILER_H */

source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_iccarm.h

@@ -0,0 +1,802 @@
+/**************************************************************************/ /**
+                                                                              * @file     cmsis_iccarm.h
+                                                                              * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+                                                                              * @version  V5.0.7
+                                                                              * @date     19. June 2018
+                                                                              ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+#error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+#define __ICCARM_V8 1
+#else
+#define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+#if __ICCARM_V8
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#elif (__VER__ >= 7080000)
+/* Needs IAR language extensions */
+#define __ALIGNED(x) __attribute__((aligned(x)))
+#else
+#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#endif
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+#define __ARM_ARCH_8M_MAIN__ 1
+#elif defined(__ARM8M_BASELINE__)
+#define __ARM_ARCH_8M_BASE__ 1
+#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+#if __ARM_ARCH == 6
+#define __ARM_ARCH_6M__ 1
+#elif __ARM_ARCH == 7
+#if __ARM_FEATURE_DSP
+#define __ARM_ARCH_7EM__ 1
+#else
+#define __ARM_ARCH_7M__ 1
+#endif
+#endif /* __ARM_ARCH */
+#endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+#define __ARM_ARCH_6M__ 1
+#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+#define __ARM_ARCH_7M__ 1
+#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+#define __ARM_ARCH_7EM__ 1
+#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+#define __ARM_ARCH_8M_BASE__ 1
+#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+#define __ARM_ARCH_8M_MAIN__ 1
+#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+#define __ARM_ARCH_8M_MAIN__ 1
+#else
+#error "Unknown target."
+#endif
+#endif
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__ == 1
+#define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__ == 1
+#define __IAR_M0_FAMILY 1
+#else
+#define __IAR_M0_FAMILY 0
+#endif
+
+#ifndef __ASM
+#define __ASM __asm
+#endif
+
+#ifndef __INLINE
+#define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+#if __ICCARM_V8
+#define __NO_RETURN __attribute__((__noreturn__))
+#else
+#define __NO_RETURN _Pragma("object_attribute=__noreturn")
+#endif
+#endif
+
+#ifndef __PACKED
+#if __ICCARM_V8
+#define __PACKED __attribute__((packed, aligned(1)))
+#else
+/* Needs IAR language extensions */
+#define __PACKED __packed
+#endif
+#endif
+
+#ifndef __PACKED_STRUCT
+#if __ICCARM_V8
+#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#else
+/* Needs IAR language extensions */
+#define __PACKED_STRUCT __packed struct
+#endif
+#endif
+
+#ifndef __PACKED_UNION
+#if __ICCARM_V8
+#define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#else
+/* Needs IAR language extensions */
+#define __PACKED_UNION __packed union
+#endif
+#endif
+
+#ifndef __RESTRICT
+#define __RESTRICT __restrict
+#endif
+
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+#define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language = save
+#pragma language = extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr) { return *(__packed uint16_t *)(ptr); }
+#pragma language = restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language = save
+#pragma language = extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) {
+  *(__packed uint16_t *)(ptr) = val;
+  ;
+}
+#pragma language = restore
+#define __UNALIGNED_UINT16_WRITE(PTR, VAL) __iar_uint16_write(PTR, VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language = save
+#pragma language = extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr) { return *(__packed uint32_t *)(ptr); }
+#pragma language = restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language = save
+#pragma language = extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) {
+  *(__packed uint32_t *)(ptr) = val;
+  ;
+}
+#pragma language = restore
+#define __UNALIGNED_UINT32_WRITE(PTR, VAL) __iar_uint32_write(PTR, VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language = save
+#pragma language = extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language = restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+#if __ICCARM_V8
+#define __USED __attribute__((used))
+#else
+#define __USED _Pragma("__root")
+#endif
+#endif
+
+#ifndef __WEAK
+#if __ICCARM_V8
+#define __WEAK __attribute__((weak))
+#else
+#define __WEAK _Pragma("__weak")
+#endif
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+#define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+#if defined(__CLZ)
+#undef __CLZ
+#endif
+#if defined(__REVSH)
+#undef __REVSH
+#endif
+#if defined(__RBIT)
+#undef __RBIT
+#endif
+#if defined(__SSAT)
+#undef __SSAT
+#endif
+#if defined(__USAT)
+#undef __USAT
+#endif
+
+#include "iccarm_builtin.h"
+
+#define __disable_fault_irq __iar_builtin_disable_fiq
+#define __disable_irq       __iar_builtin_disable_interrupt
+#define __enable_fault_irq  __iar_builtin_enable_fiq
+#define __enable_irq        __iar_builtin_enable_interrupt
+#define __arm_rsr           __iar_builtin_rsr
+#define __arm_wsr           __iar_builtin_wsr
+
+#define __get_APSR()      (__arm_rsr("APSR"))
+#define __get_BASEPRI()   (__arm_rsr("BASEPRI"))
+#define __get_CONTROL()   (__arm_rsr("CONTROL"))
+#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U)))
+#define __get_FPSCR()      (__arm_rsr("FPSCR"))
+#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+#else
+#define __get_FPSCR()      (0)
+#define __set_FPSCR(VALUE) ((void)VALUE)
+#endif
+
+#define __get_IPSR() (__arm_rsr("IPSR"))
+#define __get_MSP()  (__arm_rsr("MSP"))
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+// without main extensions, the non-secure MSPLIM is RAZ/WI
+#define __get_MSPLIM() (0U)
+#else
+#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+#endif
+#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+#define __get_PSP()     (__arm_rsr("PSP"))
+
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+// without main extensions, the non-secure PSPLIM is RAZ/WI
+#define __get_PSPLIM() (0U)
+#else
+#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+#endif
+
+#define __get_xPSR() (__arm_rsr("xPSR"))
+
+#define __set_BASEPRI(VALUE)     (__arm_wsr("BASEPRI", (VALUE)))
+#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+#define __set_CONTROL(VALUE)     (__arm_wsr("CONTROL", (VALUE)))
+#define __set_FAULTMASK(VALUE)   (__arm_wsr("FAULTMASK", (VALUE)))
+#define __set_MSP(VALUE)         (__arm_wsr("MSP", (VALUE)))
+
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+// without main extensions, the non-secure MSPLIM is RAZ/WI
+#define __set_MSPLIM(VALUE) ((void)(VALUE))
+#else
+#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+#endif
+#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+#define __set_PSP(VALUE)     (__arm_wsr("PSP", (VALUE)))
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+// without main extensions, the non-secure PSPLIM is RAZ/WI
+#define __set_PSPLIM(VALUE) ((void)(VALUE))
+#else
+#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+#endif
+
+#define __TZ_get_CONTROL_NS()        (__arm_rsr("CONTROL_NS"))
+#define __TZ_set_CONTROL_NS(VALUE)   (__arm_wsr("CONTROL_NS", (VALUE)))
+#define __TZ_get_PSP_NS()            (__arm_rsr("PSP_NS"))
+#define __TZ_set_PSP_NS(VALUE)       (__arm_wsr("PSP_NS", (VALUE)))
+#define __TZ_get_MSP_NS()            (__arm_rsr("MSP_NS"))
+#define __TZ_set_MSP_NS(VALUE)       (__arm_wsr("MSP_NS", (VALUE)))
+#define __TZ_get_SP_NS()             (__arm_rsr("SP_NS"))
+#define __TZ_set_SP_NS(VALUE)        (__arm_wsr("SP_NS", (VALUE)))
+#define __TZ_get_PRIMASK_NS()        (__arm_rsr("PRIMASK_NS"))
+#define __TZ_set_PRIMASK_NS(VALUE)   (__arm_wsr("PRIMASK_NS", (VALUE)))
+#define __TZ_get_BASEPRI_NS()        (__arm_rsr("BASEPRI_NS"))
+#define __TZ_set_BASEPRI_NS(VALUE)   (__arm_wsr("BASEPRI_NS", (VALUE)))
+#define __TZ_get_FAULTMASK_NS()      (__arm_rsr("FAULTMASK_NS"))
+#define __TZ_set_FAULTMASK_NS(VALUE) (__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+// without main extensions, the non-secure PSPLIM is RAZ/WI
+#define __TZ_get_PSPLIM_NS()      (0U)
+#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+#else
+#define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+#endif
+
+#define __TZ_get_MSPLIM_NS()      (__arm_rsr("MSPLIM_NS"))
+#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+#define __NOP __iar_builtin_no_operation
+
+#define __CLZ   __iar_builtin_CLZ
+#define __CLREX __iar_builtin_CLREX
+
+#define __DMB __iar_builtin_DMB
+#define __DSB __iar_builtin_DSB
+#define __ISB __iar_builtin_ISB
+
+#define __LDREXB __iar_builtin_LDREXB
+#define __LDREXH __iar_builtin_LDREXH
+#define __LDREXW __iar_builtin_LDREX
+
+#define __RBIT  __iar_builtin_RBIT
+#define __REV   __iar_builtin_REV
+#define __REV16 __iar_builtin_REV16
+
+__IAR_FT int16_t __REVSH(int16_t val) { return (int16_t)__iar_builtin_REVSH(val); }
+
+#define __ROR __iar_builtin_ROR
+#define __RRX __iar_builtin_RRX
+
+#define __SEV __iar_builtin_SEV
+
+#if !__IAR_M0_FAMILY
+#define __SSAT __iar_builtin_SSAT
+#endif
+
+#define __STREXB __iar_builtin_STREXB
+#define __STREXH __iar_builtin_STREXH
+#define __STREXW __iar_builtin_STREX
+
+#if !__IAR_M0_FAMILY
+#define __USAT __iar_builtin_USAT
+#endif
+
+#define __WFE __iar_builtin_WFE
+#define __WFI __iar_builtin_WFI
+
+#if __ARM_MEDIA__
+#define __SADD8   __iar_builtin_SADD8
+#define __QADD8   __iar_builtin_QADD8
+#define __SHADD8  __iar_builtin_SHADD8
+#define __UADD8   __iar_builtin_UADD8
+#define __UQADD8  __iar_builtin_UQADD8
+#define __UHADD8  __iar_builtin_UHADD8
+#define __SSUB8   __iar_builtin_SSUB8
+#define __QSUB8   __iar_builtin_QSUB8
+#define __SHSUB8  __iar_builtin_SHSUB8
+#define __USUB8   __iar_builtin_USUB8
+#define __UQSUB8  __iar_builtin_UQSUB8
+#define __UHSUB8  __iar_builtin_UHSUB8
+#define __SADD16  __iar_builtin_SADD16
+#define __QADD16  __iar_builtin_QADD16
+#define __SHADD16 __iar_builtin_SHADD16
+#define __UADD16  __iar_builtin_UADD16
+#define __UQADD16 __iar_builtin_UQADD16
+#define __UHADD16 __iar_builtin_UHADD16
+#define __SSUB16  __iar_builtin_SSUB16
+#define __QSUB16  __iar_builtin_QSUB16
+#define __SHSUB16 __iar_builtin_SHSUB16
+#define __USUB16  __iar_builtin_USUB16
+#define __UQSUB16 __iar_builtin_UQSUB16
+#define __UHSUB16 __iar_builtin_UHSUB16
+#define __SASX    __iar_builtin_SASX
+#define __QASX    __iar_builtin_QASX
+#define __SHASX   __iar_builtin_SHASX
+#define __UASX    __iar_builtin_UASX
+#define __UQASX   __iar_builtin_UQASX
+#define __UHASX   __iar_builtin_UHASX
+#define __SSAX    __iar_builtin_SSAX
+#define __QSAX    __iar_builtin_QSAX
+#define __SHSAX   __iar_builtin_SHSAX
+#define __USAX    __iar_builtin_USAX
+#define __UQSAX   __iar_builtin_UQSAX
+#define __UHSAX   __iar_builtin_UHSAX
+#define __USAD8   __iar_builtin_USAD8
+#define __USADA8  __iar_builtin_USADA8
+#define __SSAT16  __iar_builtin_SSAT16
+#define __USAT16  __iar_builtin_USAT16
+#define __UXTB16  __iar_builtin_UXTB16
+#define __UXTAB16 __iar_builtin_UXTAB16
+#define __SXTB16  __iar_builtin_SXTB16
+#define __SXTAB16 __iar_builtin_SXTAB16
+#define __SMUAD   __iar_builtin_SMUAD
+#define __SMUADX  __iar_builtin_SMUADX
+#define __SMMLA   __iar_builtin_SMMLA
+#define __SMLAD   __iar_builtin_SMLAD
+#define __SMLADX  __iar_builtin_SMLADX
+#define __SMLALD  __iar_builtin_SMLALD
+#define __SMLALDX __iar_builtin_SMLALDX
+#define __SMUSD   __iar_builtin_SMUSD
+#define __SMUSDX  __iar_builtin_SMUSDX
+#define __SMLSD   __iar_builtin_SMLSD
+#define __SMLSDX  __iar_builtin_SMLSDX
+#define __SMLSLD  __iar_builtin_SMLSLD
+#define __SMLSLDX __iar_builtin_SMLSLDX
+#define __SEL     __iar_builtin_SEL
+#define __QADD    __iar_builtin_QADD
+#define __QSUB    __iar_builtin_QSUB
+#define __PKHBT   __iar_builtin_PKHBT
+#define __PKHTB   __iar_builtin_PKHTB
+#endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#if __IAR_M0_FAMILY
+/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+#define __CLZ      __cmsis_iar_clz_not_active
+#define __SSAT     __cmsis_iar_ssat_not_active
+#define __USAT     __cmsis_iar_usat_not_active
+#define __RBIT     __cmsis_iar_rbit_not_active
+#define __get_APSR __cmsis_iar_get_APSR_not_active
+#endif
+
+#if (!((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))))
+#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+#endif
+
+#ifdef __INTRINSICS_INCLUDED
+#error intrinsics.h is already included previously!
+#endif
+
+#include <intrinsics.h>
+
+#if __IAR_M0_FAMILY
+/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+#undef __CLZ
+#undef __SSAT
+#undef __USAT
+#undef __RBIT
+#undef __get_APSR
+
+__STATIC_INLINE uint8_t __CLZ(uint32_t data) {
+  if (data == 0U) {
+    return 32U;
+  }
+
+  uint32_t count = 0U;
+  uint32_t mask  = 0x80000000U;
+
+  while ((data & mask) == 0U) {
+    count += 1U;
+    mask = mask >> 1U;
+  }
+  return count;
+}
+
+__STATIC_INLINE uint32_t __RBIT(uint32_t v) {
+  uint8_t  sc = 31U;
+  uint32_t r  = v;
+  for (v >>= 1U; v; v >>= 1U) {
+    r <<= 1U;
+    r |= v & 1U;
+    sc--;
+  }
+  return (r << sc);
+}
+
+__STATIC_INLINE uint32_t __get_APSR(void) {
+  uint32_t res;
+  __asm("MRS      %0,APSR" : "=r"(res));
+  return res;
+}
+
+#endif
+
+#if (!((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))))
+#undef __get_FPSCR
+#undef __set_FPSCR
+#define __get_FPSCR()      (0)
+#define __set_FPSCR(VALUE) ((void)VALUE)
+#endif
+
+#pragma diag_suppress = Pe940
+#pragma diag_suppress = Pe177
+
+#define __enable_irq  __enable_interrupt
+#define __disable_irq __disable_interrupt
+#define __NOP         __no_operation
+
+#define __get_xPSR __get_PSR
+
+#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__ == 0)
+
+__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { return __LDREX((unsigned long *)ptr); }
+
+__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { return __STREX(value, (unsigned long *)ptr); }
+#endif
+
+/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+#if (__CORTEX_M >= 0x03)
+
+__IAR_FT uint32_t __RRX(uint32_t value) {
+  uint32_t result;
+  __ASM("RRX      %0, %1" : "=r"(result) : "r"(value) : "cc");
+  return (result);
+}
+
+__IAR_FT void __set_BASEPRI_MAX(uint32_t value) { __asm volatile("MSR      BASEPRI_MAX,%0" ::"r"(value)); }
+
+#define __enable_fault_irq  __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << ((sizeof(op1) * 8) - op2)); }
+
+#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
+
+__IAR_FT uint32_t __get_MSPLIM(void) {
+  uint32_t res;
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  res = 0U;
+#else
+  __asm volatile("MRS      %0,MSPLIM" : "=r"(res));
+#endif
+  return res;
+}
+
+__IAR_FT void __set_MSPLIM(uint32_t value) {
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)value;
+#else
+  __asm volatile("MSR      MSPLIM,%0" ::"r"(value));
+#endif
+}
+
+__IAR_FT uint32_t __get_PSPLIM(void) {
+  uint32_t res;
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  res = 0U;
+#else
+  __asm volatile("MRS      %0,PSPLIM" : "=r"(res));
+#endif
+  return res;
+}
+
+__IAR_FT void __set_PSPLIM(uint32_t value) {
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)value;
+#else
+  __asm volatile("MSR      PSPLIM,%0" ::"r"(value));
+#endif
+}
+
+__IAR_FT uint32_t __TZ_get_CONTROL_NS(void) {
+  uint32_t res;
+  __asm volatile("MRS      %0,CONTROL_NS" : "=r"(res));
+  return res;
+}
+
+__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { __asm volatile("MSR      CONTROL_NS,%0" ::"r"(value)); }
+
+__IAR_FT uint32_t __TZ_get_PSP_NS(void) {
+  uint32_t res;
+  __asm volatile("MRS      %0,PSP_NS" : "=r"(res));
+  return res;
+}
+
+__IAR_FT void __TZ_set_PSP_NS(uint32_t value) { __asm volatile("MSR      PSP_NS,%0" ::"r"(value)); }
+
+__IAR_FT uint32_t __TZ_get_MSP_NS(void) {
+  uint32_t res;
+  __asm volatile("MRS      %0,MSP_NS" : "=r"(res));
+  return res;
+}
+
+__IAR_FT void __TZ_set_MSP_NS(uint32_t value) { __asm volatile("MSR      MSP_NS,%0" ::"r"(value)); }
+
+__IAR_FT uint32_t __TZ_get_SP_NS(void) {
+  uint32_t res;
+  __asm volatile("MRS      %0,SP_NS" : "=r"(res));
+  return res;
+}
+__IAR_FT void __TZ_set_SP_NS(uint32_t value) { __asm volatile("MSR      SP_NS,%0" ::"r"(value)); }
+
+__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) {
+  uint32_t res;
+  __asm volatile("MRS      %0,PRIMASK_NS" : "=r"(res));
+  return res;
+}
+
+__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { __asm volatile("MSR      PRIMASK_NS,%0" ::"r"(value)); }
+
+__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) {
+  uint32_t res;
+  __asm volatile("MRS      %0,BASEPRI_NS" : "=r"(res));
+  return res;
+}
+
+__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { __asm volatile("MSR      BASEPRI_NS,%0" ::"r"(value)); }
+
+__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) {
+  uint32_t res;
+  __asm volatile("MRS      %0,FAULTMASK_NS" : "=r"(res));
+  return res;
+}
+
+__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { __asm volatile("MSR      FAULTMASK_NS,%0" ::"r"(value)); }
+
+__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) {
+  uint32_t res;
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  res = 0U;
+#else
+  __asm volatile("MRS      %0,PSPLIM_NS" : "=r"(res));
+#endif
+  return res;
+}
+
+__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) {
+#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)value;
+#else
+  __asm volatile("MSR      PSPLIM_NS,%0" ::"r"(value));
+#endif
+}
+
+__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) {
+  uint32_t res;
+  __asm volatile("MRS      %0,MSPLIM_NS" : "=r"(res));
+  return res;
+}
+
+__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { __asm volatile("MSR      MSPLIM_NS,%0" ::"r"(value)); }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) {
+  if ((sat >= 1U) && (sat <= 32U)) {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max;
+    if (val > max) {
+      return max;
+    } else if (val < min) {
+      return min;
+    }
+  }
+  return val;
+}
+
+__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) {
+  if (sat <= 31U) {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max) {
+      return max;
+    } else if (val < 0) {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) {
+  uint32_t res;
+  __ASM("LDRBT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
+  return ((uint8_t)res);
+}
+
+__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) {
+  uint32_t res;
+  __ASM("LDRHT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
+  return ((uint16_t)res);
+}
+
+__IAR_FT uint32_t __LDRT(volatile uint32_t *addr) {
+  uint32_t res;
+  __ASM("LDRT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
+  return res;
+}
+
+__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM("STRBT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory"); }
+
+__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM("STRHT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory"); }
+
+__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM("STRT %1, [%0]" : : "r"(addr), "r"(value) : "memory"); }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
+
+__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) {
+  uint32_t res;
+  __ASM volatile("LDAB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+  return ((uint8_t)res);
+}
+
+__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) {
+  uint32_t res;
+  __ASM volatile("LDAH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+  return ((uint16_t)res);
+}
+
+__IAR_FT uint32_t __LDA(volatile uint32_t *ptr) {
+  uint32_t res;
+  __ASM volatile("LDA %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+  return res;
+}
+
+__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("STLB %1, [%0]" ::"r"(ptr), "r"(value) : "memory"); }
+
+__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("STLH %1, [%0]" ::"r"(ptr), "r"(value) : "memory"); }
+
+__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("STL %1, [%0]" ::"r"(ptr), "r"(value) : "memory"); }
+
+__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) {
+  uint32_t res;
+  __ASM volatile("LDAEXB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+  return ((uint8_t)res);
+}
+
+__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) {
+  uint32_t res;
+  __ASM volatile("LDAEXH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+  return ((uint16_t)res);
+}
+
+__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) {
+  uint32_t res;
+  __ASM volatile("LDAEX %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
+  return res;
+}
+
+__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) {
+  uint32_t res;
+  __ASM volatile("STLEXB %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
+  return res;
+}
+
+__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) {
+  uint32_t res;
+  __ASM volatile("STLEXH %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
+  return res;
+}
+
+__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) {
+  uint32_t res;
+  __ASM volatile("STLEX %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
+  return res;
+}
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default = Pe940
+#pragma diag_default = Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_version.h

@@ -0,0 +1,38 @@
+/**************************************************************************/ /**
+                                                                              * @file     cmsis_version.h
+                                                                              * @brief    CMSIS Core(M) Version definitions
+                                                                              * @version  V5.0.2
+                                                                              * @date     19. April 2017
+                                                                              ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__clang__)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN (5U)                                                        /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB  (1U)                                                        /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION      ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB) /*!< CMSIS Core(M) version number */
+#endif

source/Core/BSP/MHP30/Vendor/CMSIS/Include/core_sc000.h

@@ -0,0 +1,933 @@
+/**************************************************************************/ /**
+                                                                              * @file     core_sc000.h
+                                                                              * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+                                                                              * @version  V5.0.5
+                                                                              * @date     28. May 2018
+                                                                              ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__clang__)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                                         /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                                          /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION      ((__SC000_CMSIS_VERSION_MAIN << 16U) | __SC000_CMSIS_VERSION_SUB) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined(__CC_ARM)
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__GNUC__)
+#if defined(__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__ICCARM__)
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__TI_ARM__)
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__TASKING__)
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__CSMC__)
+#if (__CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC000_REV
+#define __SC000_REV 0x0000U
+#warning "__SC000_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O  volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM  volatile const /*! Defines 'read only' structure member permissions */
+#define __OM  volatile       /*! Defines 'write only' structure member permissions */
+#define __IOM volatile       /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+  struct {
+    uint32_t _reserved0 : 28; /*!< bit:  0..27  Reserved */
+    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
+    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
+    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
+    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U                 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U                 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U                 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+  struct {
+    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+  struct {
+    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
+    uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1 : 3;  /*!< bit: 25..27  Reserved */
+    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
+    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
+    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
+    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+  struct {
+    uint32_t _reserved0 : 1;  /*!< bit:      0  Reserved */
+    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
+  } b;                        /*!< Structure used for bit  access */
+  uint32_t w;                 /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+  __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+  uint32_t       RESERVED0[31U];
+  __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+  uint32_t       RSERVED1[31U];
+  __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+  uint32_t       RESERVED2[31U];
+  __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+  uint32_t       RESERVED3[31U];
+  uint32_t       RESERVED4[64U];
+  __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+  __IM uint32_t  CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;  /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;  /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;   /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;   /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  uint32_t       RESERVED0[1U];
+  __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  uint32_t       RESERVED1[154U];
+  __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U                                   /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+  uint32_t       RESERVED0[2U];
+  __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U                                       /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+  __IM uint32_t  TYPE; /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;  /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U                              /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U                               /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U                                 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U                               /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U                               /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U                                 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U                                /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U                          /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U                                 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U                              /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U                      /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U                        /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U                         /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U                     /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U                     /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U                     /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U                           /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U                               /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field##_Pos) & field##_Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value)&field##_Msk) >> field##_Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE     (0xE000E000UL)        /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE    (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE     (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB  ((SCnSCB_Type *)SCS_BASE)      /*!< System control Register not in SCB */
+#define SCB     ((SCB_Type *)SCB_BASE)         /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC    ((NVIC_Type *)NVIC_BASE)       /*!< NVIC configuration struct */
+
+#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL)  /*!< Memory Protection Unit */
+#define MPU      ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+#define NVIC_EnableIRQ       __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ    __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ      __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+#define NVIC_SetPriority     __NVIC_SetPriority
+#define NVIC_GetPriority     __NVIC_GetPriority
+#define NVIC_SystemReset     __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetVector __NVIC_SetVector
+#define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER    (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return                                */
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)   ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
+#define _IP_IDX(IRQn)    ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) {
+  if ((int32_t)(IRQn) >= 0) {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) {
+  if ((int32_t)(IRQn) >= 0) {
+    return ((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  } else {
+    return (0U);
+  }
+}
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) {
+  if ((int32_t)(IRQn) >= 0) {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) {
+  if ((int32_t)(IRQn) >= 0) {
+    return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  } else {
+    return (0U);
+  }
+}
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) {
+  if ((int32_t)(IRQn) >= 0) {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
+  if ((int32_t)(IRQn) >= 0) {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
+  if ((int32_t)(IRQn) >= 0) {
+    NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  } else {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) {
+
+  if ((int32_t)(IRQn) >= 0) {
+    return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  } else {
+    return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+  uint32_t *vectors                             = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) {
+  __DSB(); /* Ensure all outstanding memory accesses included
+              buffered write are completed before reset */
+  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB(); /* Ensure completion of memory access */
+
+  for (;;) /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ }
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+    return (1UL); /* Reload value impossible */
+  }
+
+  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
+  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
+  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                                                    /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

source/Core/BSP/MHP30/Vendor/CMSIS/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__clang__)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include <stdint.h>
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S(void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S(TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S(TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h

@@ -0,0 +1,349 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal.h
+ * @author  MCD Application Team
+ * @brief   This file contains all the functions prototypes for the HAL
+ *          module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_H
+#define __STM32F1xx_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_conf.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+typedef enum { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef;
+/**
+ * @}
+ */
+/* Exported types ------------------------------------------------------------*/
+extern volatile uint32_t   uwTick;
+extern uint32_t            uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
+
+/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
+ * @brief   Freeze/Unfreeze Peripherals in Debug mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ *                  STM32F101xC/D/E and STM32F103xC/D/E,
+ *                  STM32F101xF/G and STM32F103xF/G
+ *                  STM32F10xx4 and STM32F10xx6
+ *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ *       debug mode (not accessible by the user software in normal mode).
+ *       Refer to errata sheet of these devices for more details.
+ * @{
+ */
+
+/* Peripherals on APB1 */
+/**
+ * @brief  TIM2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM2()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
+
+/**
+ * @brief  TIM3 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM3()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
+
+#if defined(DBGMCU_CR_DBG_TIM4_STOP)
+/**
+ * @brief  TIM4 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM4()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM5_STOP)
+/**
+ * @brief  TIM5 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM5()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM6_STOP)
+/**
+ * @brief  TIM6 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM6()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM7_STOP)
+/**
+ * @brief  TIM7 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM7()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM12_STOP)
+/**
+ * @brief  TIM12 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM12()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM13_STOP)
+/**
+ * @brief  TIM13 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM13()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM14_STOP)
+/**
+ * @brief  TIM14 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM14()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
+#endif
+
+/**
+ * @brief  WWDG Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_WWDG()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
+
+/**
+ * @brief  IWDG Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_IWDG()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
+
+/**
+ * @brief  I2C1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
+
+#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+/**
+ * @brief  I2C2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#endif
+
+#if defined(DBGMCU_CR_DBG_CAN1_STOP)
+/**
+ * @brief  CAN1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_CAN1()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_CAN2_STOP)
+/**
+ * @brief  CAN2 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_CAN2()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
+#endif
+
+/* Peripherals on APB2 */
+#if defined(DBGMCU_CR_DBG_TIM1_STOP)
+/**
+ * @brief  TIM1 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM1()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM8_STOP)
+/**
+ * @brief  TIM8 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM8()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM9_STOP)
+/**
+ * @brief  TIM9 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM9()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM10_STOP)
+/**
+ * @brief  TIM10 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM10()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM11_STOP)
+/**
+ * @brief  TIM11 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM11()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM15_STOP)
+/**
+ * @brief  TIM15 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM15()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM16_STOP)
+/**
+ * @brief  TIM16 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM16()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
+#endif
+
+#if defined(DBGMCU_CR_DBG_TIM17_STOP)
+/**
+ * @brief  TIM17 Peripherals Debug mode
+ */
+#define __HAL_DBGMCU_FREEZE_TIM17()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Functions
+ * @{
+ */
+/** @addtogroup HAL_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void              HAL_MspInit(void);
+void              HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions  ************************************************/
+void                HAL_IncTick(void);
+void                HAL_Delay(uint32_t Delay);
+uint32_t            HAL_GetTick(void);
+uint32_t            HAL_GetTickPrio(void);
+HAL_StatusTypeDef   HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void                HAL_SuspendTick(void);
+void                HAL_ResumeTick(void);
+uint32_t            HAL_GetHalVersion(void);
+uint32_t            HAL_GetREVID(void);
+uint32_t            HAL_GetDEVID(void);
+uint32_t            HAL_GetUIDw0(void);
+uint32_t            HAL_GetUIDw1(void);
+uint32_t            HAL_GetUIDw2(void);
+void                HAL_DBGMCU_EnableDBGSleepMode(void);
+void                HAL_DBGMCU_DisableDBGSleepMode(void);
+void                HAL_DBGMCU_EnableDBGStopMode(void);
+void                HAL_DBGMCU_DisableDBGStopMode(void);
+void                HAL_DBGMCU_EnableDBGStandbyMode(void);
+void                HAL_DBGMCU_DisableDBGStandbyMode(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h

@@ -0,0 +1,911 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_adc.h
+ * @author  MCD Application Team
+ * @brief   Header file containing functions prototypes of ADC HAL library.
+ ******************************************************************************
+ * @attention
+ *
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_ADC_H
+#define __STM32F1xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief  Structure definition of ADC and regular group initialization
+ * @note   Parameters of this structure are shared within 2 scopes:
+ *          - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
+ *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
+ * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+ *         ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct {
+  uint32_t DataAlign;                 /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
+                                           or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset
+                                         application): MSB on register bit 14 and LSB on register bit 3).                 This parameter can be a value of @ref ADC_Data_align */
+  uint32_t ScanConvMode;              /*!< Configures the sequencer of regular and injected groups.
+                                           This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+                                           If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+                                                        Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+                                           If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+                                                        Scan direction is upward: from rank1 to rank 'n'.
+                                           This parameter can be a value of @ref ADC_Scan_mode
+                                           Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
+                                                 or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
+                                                 the last conversion of the sequence. All previous conversions would be overwritten by the last one.
+                                                 Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
+  FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+                                          after the selected trigger occurred (software start or external trigger).
+                                          This parameter can be set to ENABLE or DISABLE. */
+  uint32_t NbrOfConversion;           /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+                                           To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                           This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+  FunctionalState
+      DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+                                  Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                  Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+                                  This parameter can be set to ENABLE or DISABLE. */
+  uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+                                     If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+  uint32_t ExternalTrigConv;    /*!< Selects the external event used to trigger the conversion start of regular group.
+                                     If set to ADC_SOFTWARE_START, external triggers are disabled.
+                                     If set to external trigger source, triggering is on event rising edge.
+                                     This parameter can be a value of @ref ADC_External_trigger_source_Regular */
+} ADC_InitTypeDef;
+
+/**
+ * @brief  Structure definition of ADC channel for regular group
+ * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ *         ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct {
+  uint32_t
+      Channel;           /*!< Specifies the channel to configure into ADC regular group.
+                              This parameter can be a value of @ref ADC_channels
+                              Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
+                              Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
+                              Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection
+                            trigger.      It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.      Refer to errata sheet of these devices for more details. */
+  uint32_t Rank;         /*!< Specifies the rank in the regular group sequencer
+                              This parameter can be a value of @ref ADC_regular_rank
+                              Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or
+                            parameter number of conversions can be adjusted) */
+  uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+                              Unit: ADC clock cycles
+                              Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
+                              This parameter can be a value of @ref ADC_sampling_times
+                              Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+                                       If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+                              Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
+                                    sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                    Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
+} ADC_ChannelConfTypeDef;
+
+/**
+ * @brief  ADC Configuration analog watchdog definition
+ * @note   The setting of these parameters with function is conditioned to ADC state.
+ *         ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
+ */
+typedef struct {
+  uint32_t WatchdogMode;   /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
+                                This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+  uint32_t Channel;        /*!< Selects which ADC channel to monitor by analog watchdog.
+                                This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
+                                This parameter can be a value of @ref ADC_channels. */
+  FunctionalState ITMode;  /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
+                                This parameter can be set to ENABLE or DISABLE */
+  uint32_t HighThreshold;  /*!< Configures the ADC analog watchdog High threshold value.
+                                This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+  uint32_t LowThreshold;   /*!< Configures the ADC analog watchdog High threshold value.
+                                This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+  uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
+} ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief  HAL ADC state machine: ADC states definition (bitfields)
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET         0x00000000U /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY         0x00000001U /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT       0x00000004U /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG   0x00000020U /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA      0x00000040U /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY                                                                                                     \
+  0x00000100U                               /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, \
+                                                external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_REG_EOC   0x00000200U /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR   0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised  */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY                                                                                                          \
+  0x00001000U                               /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, \
+                                                external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_INJ_EOC   0x00002000U /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */
+
+/**
+ * @brief  ADC handle Structure definition
+ */
+typedef struct __ADC_HandleTypeDef {
+  ADC_TypeDef *Instance; /*!< Register base address */
+
+  ADC_InitTypeDef Init; /*!< ADC required parameters */
+
+  DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+
+  HAL_LockTypeDef Lock; /*!< ADC locking object */
+
+  __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+
+  __IO uint32_t ErrorCode; /*!< ADC Error code */
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  void (*ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);                                                                 /*!< ADC conversion complete callback */
+  void (*ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);                                                             /*!< ADC conversion DMA half-transfer callback */
+  void (*LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);                                                         /*!< ADC analog watchdog 1 callback */
+  void (*ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                                                                    /*!< ADC error callback */
+  void (*InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */
+  void (*MspInitCallback)(struct __ADC_HandleTypeDef *hadc);                                                                  /*!< ADC Msp Init callback */
+  void (*MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);                                                                /*!< ADC Msp DeInit callback */
+#endif                                                                                                                        /* USE_HAL_ADC_REGISTER_CALLBACKS */
+} ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief  HAL ADC Callback ID enumeration definition
+ */
+typedef enum {
+  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U, /*!< ADC conversion complete callback ID */
+  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U, /*!< ADC analog watchdog 1 callback ID */
+  HAL_ADC_ERROR_CB_ID                   = 0x03U, /*!< ADC error callback ID */
+  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
+  HAL_ADC_MSPINIT_CB_ID                 = 0x09U, /*!< ADC Msp Init callback ID          */
+  HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU  /*!< ADC Msp DeInit callback ID        */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+ * @brief  HAL ADC Callback pointer definition
+ */
+typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE 0x00U /*!< No error                                              */
+#define HAL_ADC_ERROR_INTERNAL                                                      \
+  0x01U                         /*!< ADC IP internal error: if problem of clocking, \
+                                     enable/disable, erroneous state                       */
+#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error                                         */
+#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error                                    */
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
+#endif                                         /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Data_align ADC data alignment
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT 0x00000000U
+#define ADC_DATAALIGN_LEFT  ((uint32_t)ADC_CR2_ALIGN)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Scan_mode ADC scan mode
+ * @{
+ */
+/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for     */
+/*       compatibility with other STM32 devices having a sequencer with       */
+/*       additional options.                                                  */
+#define ADC_SCAN_DISABLE 0x00000000U
+#define ADC_SCAN_ENABLE  ((uint32_t)ADC_CR1_SCAN)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE   0x00000000U
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels ADC channels
+ * @{
+ */
+/* Note: Depending on devices, some channels may not be available on package  */
+/*       pins. Refer to device datasheet for channels availability.           */
+#define ADC_CHANNEL_0  0x00000000U
+#define ADC_CHANNEL_1  ((uint32_t)(ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_2  ((uint32_t)(ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_3  ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_4  ((uint32_t)(ADC_SQR3_SQ1_2))
+#define ADC_CHANNEL_5  ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_6  ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_7  ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_8  ((uint32_t)(ADC_SQR3_SQ1_3))
+#define ADC_CHANNEL_9  ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
+#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
+
+#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
+#define ADC_CHANNEL_VREFINT    ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times ADC sampling times
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5    0x00000000U                                                          /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_7CYCLES_5   ((uint32_t)(ADC_SMPR2_SMP0_0))                                       /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_13CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_1))                                       /*!< Sampling time 13.5 ADC clock cycles */
+#define ADC_SAMPLETIME_28CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))                    /*!< Sampling time 28.5 ADC clock cycles */
+#define ADC_SAMPLETIME_41CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_2))                                       /*!< Sampling time 41.5 ADC clock cycles */
+#define ADC_SAMPLETIME_55CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0))                    /*!< Sampling time 55.5 ADC clock cycles */
+#define ADC_SAMPLETIME_71CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1))                    /*!< Sampling time 71.5 ADC clock cycles */
+#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank ADC rank into regular group
+ * @{
+ */
+#define ADC_REGULAR_RANK_1  0x00000001U
+#define ADC_REGULAR_RANK_2  0x00000002U
+#define ADC_REGULAR_RANK_3  0x00000003U
+#define ADC_REGULAR_RANK_4  0x00000004U
+#define ADC_REGULAR_RANK_5  0x00000005U
+#define ADC_REGULAR_RANK_6  0x00000006U
+#define ADC_REGULAR_RANK_7  0x00000007U
+#define ADC_REGULAR_RANK_8  0x00000008U
+#define ADC_REGULAR_RANK_9  0x00000009U
+#define ADC_REGULAR_RANK_10 0x0000000AU
+#define ADC_REGULAR_RANK_11 0x0000000BU
+#define ADC_REGULAR_RANK_12 0x0000000CU
+#define ADC_REGULAR_RANK_13 0x0000000DU
+#define ADC_REGULAR_RANK_14 0x0000000EU
+#define ADC_REGULAR_RANK_15 0x0000000FU
+#define ADC_REGULAR_RANK_16 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE            0x00000000U
+#define ADC_ANALOGWATCHDOG_SINGLE_REG      ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG         ((uint32_t)ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC       ((uint32_t)ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC    ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_conversion_group ADC conversion group
+ * @{
+ */
+#define ADC_REGULAR_GROUP          ((uint32_t)(ADC_FLAG_EOC))
+#define ADC_INJECTED_GROUP         ((uint32_t)(ADC_FLAG_JEOC))
+#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Event_type ADC Event type
+ * @{
+ */
+#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
+
+#define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+ * @{
+ */
+#define ADC_IT_EOC  ADC_CR1_EOCIE  /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IT_AWD  ADC_CR1_AWDIE  /*!< ADC Analog watchdog interrupt source */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+ * @{
+ */
+#define ADC_FLAG_STRT  ADC_SR_STRT  /*!< ADC Regular group start flag */
+#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
+#define ADC_FLAG_EOC   ADC_SR_EOC   /*!< ADC End of Regular conversion flag */
+#define ADC_FLAG_JEOC  ADC_SR_JEOC  /*!< ADC End of Injected conversion flag */
+#define ADC_FLAG_AWD   ADC_SR_AWD   /*!< ADC Analog watchdog flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/** @defgroup ADC_conversion_cycles ADC conversion cycles
+ * @{
+ */
+/* ADC conversion cycles (unit: ADC clock cycles)                           */
+/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
+/* resolution 12 bits)                                                      */
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5    14U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5   20U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5  26U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5  41U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5  54U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5  68U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5  84U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
+ * @{
+ */
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
+  (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
+  (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2)
+
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
+  (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
+  (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1)
+
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
+  (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
+  (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0)
+
+#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS    0x00000000U
+#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
+#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
+#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
+#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+
+#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS    0x00000000U
+#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
+#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
+#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
+#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+/**
+ * @}
+ */
+
+/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user.                                                                */
+
+/**
+ * @brief Enable the ADC peripheral
+ * @note ADC enable requires a delay for ADC stabilization time
+ *       (refer to device datasheet, parameter tSTAB)
+ * @note On STM32F1, if ADC is already enabled this macro trigs a conversion
+ *       SW start on regular group.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
+
+/**
+ * @brief Disable the ADC peripheral
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
+
+/** @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ *          This parameter can be any combination of the following values:
+ *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ *          This parameter can be any combination of the following values:
+ *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC interrupt source to check
+ *          This parameter can be any combination of the following values:
+ *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ *          This parameter can be any combination of the following values:
+ *            @arg ADC_FLAG_STRT: ADC Regular group start flag
+ *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
+ *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
+ *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the ADC's pending flags
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ *          This parameter can be any combination of the following values:
+ *            @arg ADC_FLAG_STRT: ADC Regular group start flag
+ *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
+ *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
+ *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @retval None
+ */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
+
+/** @brief  Reset ADC handle state
+ * @param  __HANDLE__: ADC handle
+ * @retval None
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)           \
+  do {                                                     \
+    (__HANDLE__)->State             = HAL_ADC_STATE_RESET; \
+    (__HANDLE__)->MspInitCallback   = NULL;                \
+    (__HANDLE__)->MspDeInitCallback = NULL;                \
+  } while (0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif
+
+/**
+ * @}
+ */
+
+/* Private macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+ * @brief Verification of ADC state: enabled or disabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON)) ? SET : RESET)
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ *        or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ *        or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
+
+/**
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ *        the first parameter is the ADC handle State, the second parameter is the
+ *        bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Set ADC number of conversions into regular channel sequence length.
+ * @param _NbrOfConversion_: Regular channel sequence length
+ * @retval None
+ */
+#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 10 and 18.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_)-10)))
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 0 and 9.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 1 and 6.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_)-1)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 7 and 12.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_)-7)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 13 and 16.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_)-13)))
+
+/**
+ * @brief Set the injected sequence length.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_)-1) << ADC_JSQR_JL_Pos)
+
+/**
+ * @brief Set the selected injected channel rank
+ *        Note: on STM32F1 devices, channel rank position in JSQR register
+ *              is depending on total number of ranks selected into
+ *              injected sequencer (ranks sequence starting from 4-JL)
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_: Continuous mode.
+ * @retval None
+ */
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
+
+/**
+ * @brief Configures the number of discontinuous conversions for the regular group channels.
+ * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_)-1) << ADC_CR1_DISCNUM_Pos)
+
+/**
+ * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
+ * @param _SCAN_MODE_: Scan conversion mode.
+ * @retval None
+ */
+/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter   */
+/*       is equivalent to ADC_SCAN_ENABLE.                                    */
+#define ADC_CR1_SCAN_SET(_SCAN_MODE_) ((((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)) ? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE))
+
+/**
+ * @brief Get the maximum ADC conversion cycles on all channels.
+ * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
+ * Approximation of sampling time within 4 ranges, returns the highest value:
+ *   below 7.5 cycles {1.5 cycle; 7.5 cycles},
+ *   between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
+ *   between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
+ *   equal to 239.5 cycles
+ * Unit: ADC clock cycles
+ * @param __HANDLE__: ADC handle
+ * @retval ADC conversion cycles on all channels
+ */
+#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                                                                                                            \
+  (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET))             \
+       ?                                                                                                                                                                                \
+                                                                                                                                                                                        \
+       (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET))        \
+            ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5                                                                                                                             \
+            : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5)                                                                                                                           \
+       : ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET))     \
+           || ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) \
+              ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5                                                                                                                          \
+              : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5))
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT))
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || ((SCAN_MODE) == ADC_SCAN_ENABLE))
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING))
+
+#define IS_ADC_CHANNEL(CHANNEL)                                                                                                                                                                      \
+  (((CHANNEL) == ADC_CHANNEL_0) || ((CHANNEL) == ADC_CHANNEL_1) || ((CHANNEL) == ADC_CHANNEL_2) || ((CHANNEL) == ADC_CHANNEL_3) || ((CHANNEL) == ADC_CHANNEL_4) || ((CHANNEL) == ADC_CHANNEL_5)      \
+   || ((CHANNEL) == ADC_CHANNEL_6) || ((CHANNEL) == ADC_CHANNEL_7) || ((CHANNEL) == ADC_CHANNEL_8) || ((CHANNEL) == ADC_CHANNEL_9) || ((CHANNEL) == ADC_CHANNEL_10) || ((CHANNEL) == ADC_CHANNEL_11) \
+   || ((CHANNEL) == ADC_CHANNEL_12) || ((CHANNEL) == ADC_CHANNEL_13) || ((CHANNEL) == ADC_CHANNEL_14) || ((CHANNEL) == ADC_CHANNEL_15) || ((CHANNEL) == ADC_CHANNEL_16)                              \
+   || ((CHANNEL) == ADC_CHANNEL_17))
+
+#define IS_ADC_SAMPLE_TIME(TIME)                                                                                                                                 \
+  (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || ((TIME) == ADC_SAMPLETIME_28CYCLES_5) \
+   || ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
+
+#define IS_ADC_REGULAR_RANK(CHANNEL)                                                                                                                                                             \
+  (((CHANNEL) == ADC_REGULAR_RANK_1) || ((CHANNEL) == ADC_REGULAR_RANK_2) || ((CHANNEL) == ADC_REGULAR_RANK_3) || ((CHANNEL) == ADC_REGULAR_RANK_4) || ((CHANNEL) == ADC_REGULAR_RANK_5)         \
+   || ((CHANNEL) == ADC_REGULAR_RANK_6) || ((CHANNEL) == ADC_REGULAR_RANK_7) || ((CHANNEL) == ADC_REGULAR_RANK_8) || ((CHANNEL) == ADC_REGULAR_RANK_9) || ((CHANNEL) == ADC_REGULAR_RANK_10)     \
+   || ((CHANNEL) == ADC_REGULAR_RANK_11) || ((CHANNEL) == ADC_REGULAR_RANK_12) || ((CHANNEL) == ADC_REGULAR_RANK_13) || ((CHANNEL) == ADC_REGULAR_RANK_14) || ((CHANNEL) == ADC_REGULAR_RANK_15) \
+   || ((CHANNEL) == ADC_REGULAR_RANK_16))
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)                                                                                                                                                        \
+  (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \
+   || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC))
+
+#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || ((CONVERSION) == ADC_INJECTED_GROUP) || ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP))
+
+#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
+
+/** @defgroup ADC_range_verification ADC range verification
+ * For a unique ADC resolution: 12 bits
+ * @{
+ */
+#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
+ * @{
+ */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
+ * @{
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include ADC HAL Extension module */
+#include "stm32f1xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void              HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void              HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* IO operation functions  *****************************************************/
+
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @{
+ */
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+/** @addtogroup ADC_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
+/**
+ * @}
+ */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Internal HAL driver functions **********************************************/
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef *hadc);
+void              ADC_StabilizationTime(uint32_t DelayUs);
+void              ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void              ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void              ADC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h

@@ -0,0 +1,607 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_adc_ex.h
+ * @author  MCD Application Team
+ * @brief   Header file of ADC HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_ADC_EX_H
+#define __STM32F1xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief  ADC Configuration injected Channel structure definition
+ * @note   Parameters of this structure are shared within 2 scopes:
+ *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
+ *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+ *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+ * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ *         ADC state can be either:
+ *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
+ *          - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
+ */
+typedef struct {
+  uint32_t InjectedChannel;                      /*!< Selection of ADC channel to configure
+                                                      This parameter can be a value of @ref ADC_channels
+                                                      Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
+                                                      Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
+                                                      Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with
+                                                    injection                      trigger.                           It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
+                                                    Refer to errata                      sheet of these devices for more details. */
+  uint32_t InjectedRank;                         /*!< Rank in the injected group sequencer
+                                                      This parameter must be a value of @ref ADCEx_injected_rank
+                                                      Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel
+                                                    setting (or parameter number of conversions can be adjusted) */
+  uint32_t InjectedSamplingTime;                 /*!< Sampling time value to be set for the selected channel.
+                                                      Unit: ADC clock cycles
+                                                      Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
+                                                      This parameter can be a value of @ref ADC_sampling_times
+                                                      Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+                                                               If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+                                                      Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
+                                                            sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+                                                            Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
+  uint32_t InjectedOffset;                       /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+                                                      Offset value must be a positive number.
+                                                      Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+                                                      this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+  uint32_t InjectedNbrOfConversion;              /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+                                                      To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+                                                      This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                               configure a channel on injected group can impact the configuration of other channels previously set. */
+  FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
+                                                    successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is
+                                                    discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is
+                                                    discarded. This parameter can be set to ENABLE or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                               configure a channel on injected group can impact the configuration of other channels previously set. */
+  FunctionalState AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+                                                      This parameter can be set to ENABLE or DISABLE.
+                                                      Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+                                                      Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+                                                      Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+                                                            To maintain JAUTO always enabled, DMA must be configured in circular mode.
+                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                               configure a channel on injected group can impact the configuration of other channels previously set. */
+  uint32_t ExternalTrigInjecConv;                /*!< Selects the external event used to trigger the conversion start of injected group.
+                                                      If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+                                                      If set to external trigger source, triggering is on event rising edge.
+                                                      This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
+                                                      Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+                                                            If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on
+                                                    the fly)                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                               configure a channel on injected group can impact the configuration of other channels previously set. */
+} ADC_InjectionConfTypeDef;
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+ * @brief  Structure definition of ADC multimode
+ * @note   The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
+ *         State of ADCs of the common group must be: disabled.
+ */
+typedef struct {
+  uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
+                      This parameter can be a value of @ref ADCEx_Common_mode
+                      Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any
+                    configuration change. Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1
+                    and ADC2. Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC
+                    clock cycles for slow interleaved mode. Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration
+                    structure can have additional parameters). The equivalences are:
+                              - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several
+                    ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
+                              - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32
+                    devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
+
+} ADC_MultiModeTypeDef;
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 0x00000001U
+#define ADC_INJECTED_RANK_2 0x00000002U
+#define ADC_INJECTED_RANK_3 0x00000003U
+#define ADC_INJECTED_RANK_4 0x00000004U
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE   0x00000000U
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
+ * @{
+ */
+/*!< List of external triggers with generic trigger name, independently of    */
+/* ADC target, sorted by trigger name:                                        */
+
+/*!< External triggers of regular group for ADC1&ADC2 only */
+#define ADC_EXTERNALTRIGCONV_T1_CC1   ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2   ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T2_CC2   ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T3_TRGO  ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_CC4   ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+/*!< External triggers of regular group for ADC3 only */
+#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3
+#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1
+#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1
+#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3
+#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1
+#endif /* STM32F103xE || defined STM32F103xG */
+
+/*!< External triggers of regular group for all ADC instances */
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and   */
+/*         XL-density devices.                                                */
+/*         To use it on ADC or ADC2, a remap of trigger must be done from     */
+/*         EXTI line 11 to TIM8_TRGO with macro:                              */
+/*           __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()                           */
+/*           __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()                           */
+
+/* Note for internal constant value management: If TIM8_TRGO is available,    */
+/* its definition is set to value for ADC1&ADC2 by default and changed to     */
+/* value for ADC3 by HAL ADC driver if ADC3 is selected.                      */
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
+#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#define ADC_SOFTWARE_START ADC1_2_3_SWSTART
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
+ * @{
+ */
+/*!< List of external triggers with generic trigger name, independently of    */
+/* ADC target, sorted by trigger name:                                        */
+
+/*!< External triggers of injected group for ADC1&ADC2 only */
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO  ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1   ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4   ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO  ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+/*!< External triggers of injected group for ADC3 only */
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC3  ADC3_EXTERNALTRIGINJEC_T4_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC2  ADC3_EXTERNALTRIGINJEC_T8_CC2
+#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T5_CC4  ADC3_EXTERNALTRIGINJEC_T5_CC4
+#endif /* STM32F103xE || defined STM32F103xG */
+
+/*!< External triggers of injected group for all ADC instances */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4  ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
+
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and    */
+/*         XL-density devices.                                                */
+/*         To use it on ADC1 or ADC2, a remap of trigger must be done from    */
+/*         EXTI line 11 to TIM8_CC4 with macro:                               */
+/*           __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()                           */
+/*           __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()                           */
+
+/* Note for internal constant value management: If TIM8_CC4 is available,     */
+/* its definition is set to value for ADC1&ADC2 by default and changed to     */
+/* value for ADC3 by HAL ADC driver if ADC3 is selected.                      */
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
+#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
+/**
+ * @}
+ */
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT               0x00000000U                     /*!< ADC dual mode disabled (ADC independent mode) */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG   ((uint32_t)(ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
+#define ADC_DUALMODE_INJECSIMULT_INTERLFAST                                                                                                                                                          \
+  ((uint32_t)(ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling \
+                                                         phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW                                                                                                                                                           \
+  ((uint32_t)(ADC_CR1_DUALMOD_2)) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock \
+                                     cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
+#define ADC_DUALMODE_REGSIMULT   ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
+#define ADC_DUALMODE_INTERLFAST                                                                                                                                                                      \
+  ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles \
+                                                                             (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INTERLSLOW                                                                                                                                                        \
+  ((uint32_t)(ADC_CR1_DUALMOD_3)) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter \
+                                     "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
+/**
+ * @}
+ */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
+ * @{
+ */
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
+ * @{
+ */
+/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC    */
+/* instance is available on the selected device).                             */
+/* (used internally by HAL driver. To not use into HAL structure parameters)  */
+
+/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
+#define ADC1_2_EXTERNALTRIG_T1_CC1   0x00000000U
+#define ADC1_2_EXTERNALTRIG_T1_CC2   ((uint32_t)(ADC_CR2_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T2_CC2   ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_TRGO  ((uint32_t)(ADC_CR2_EXTSEL_2))
+#define ADC1_2_EXTERNALTRIG_T4_CC4   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG)
+/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and     */
+/* XL-density devices.                                                        */
+#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
+#endif
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+/* External triggers of regular group for ADC3 */
+#define ADC3_EXTERNALTRIG_T3_CC1  ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC3_EXTERNALTRIG_T2_CC3  ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC3_EXTERNALTRIG_T8_CC1  ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC3_EXTERNALTRIG_T5_CC1  ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC3_EXTERNALTRIG_T5_CC3  ADC1_2_EXTERNALTRIG_EXT_IT11
+#endif
+
+/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
+#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)(ADC_CR2_EXTSEL_1))
+#define ADC1_2_3_SWSTART             ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
+ * @{
+ */
+/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC    */
+/* instance is available on the selected device).                             */
+/* (used internally by HAL driver. To not use into HAL structure parameters)  */
+
+/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO  ((uint32_t)(ADC_CR2_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1   ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4   ((uint32_t)(ADC_CR2_JEXTSEL_2))
+#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO  ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG)
+/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and      */
+/* XL-density devices.                                                        */
+#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+#endif
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+/* External triggers of injected group for ADC3 */
+#define ADC3_EXTERNALTRIGINJEC_T4_CC3  ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC3_EXTERNALTRIGINJEC_T8_CC2  ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC3_EXTERNALTRIGINJEC_T8_CC4  ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC3_EXTERNALTRIGINJEC_T5_CC4  ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+#endif /* STM32F103xE || defined STM32F103xG */
+
+/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
+#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
+#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4  ((uint32_t)(ADC_CR2_JEXTSEL_0))
+#define ADC1_2_3_JSWSTART                  ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+ * @brief For devices with 3 ADCs: Defines the external trigger source
+ *        for regular group according to ADC into common group ADC1&ADC2 or
+ *        ADC3 (some triggers with same source have different value to
+ *        be programmed into ADC EXTSEL bits of CR2 register).
+ *        For devices with 2 ADCs or less: this macro makes no change.
+ * @param __HANDLE__: ADC handle
+ * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
+ * @retval External trigger to be programmed into EXTSEL bits of CR2 register
+ */
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
+  (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO) ? (ADC3_EXTERNALTRIG_T8_TRGO) : (__EXT_TRIG_CONV__)) : (__EXT_TRIG_CONV__))
+#else
+#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) (__EXT_TRIG_CONV__)
+#endif /* STM32F103xE || STM32F103xG */
+
+/**
+ * @brief For devices with 3 ADCs: Defines the external trigger source
+ *        for injected group according to ADC into common group ADC1&ADC2 or
+ *        ADC3 (some triggers with same source have different value to
+ *        be programmed into ADC JEXTSEL bits of CR2 register).
+ *        For devices with 2 ADCs or less: this macro makes no change.
+ * @param __HANDLE__: ADC handle
+ * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
+ * @retval External trigger to be programmed into JEXTSEL bits of CR2 register
+ */
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
+  (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) ? (ADC3_EXTERNALTRIGINJEC_T8_CC4) : (__EXT_TRIG_INJECTCONV__)) : (__EXT_TRIG_INJECTCONV__))
+#else
+#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) (__EXT_TRIG_INJECTCONV__)
+#endif /* STM32F103xE || STM32F103xG */
+
+/**
+ * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
+ */
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_DUALMOD) : (RESET))
+#else
+#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (RESET)
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (((((__HANDLE__)->Instance) == ADC2)) ? ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) : (!RESET))
+#else
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (!RESET)
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_JAUTO) : (RESET))
+#else
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (RESET)
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+ * @brief Set handle of the other ADC sharing the common multimode settings
+ * @param __HANDLE__: ADC handle
+ * @param __HANDLE_OTHER_ADC__: other ADC handle
+ * @retval None
+ */
+#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
+
+/**
+ * @brief Set handle of the ADC slave associated to the ADC master
+ * On STM32F1 devices, ADC slave is always ADC2 (this can be different
+ * on other STM32 devices)
+ * @param __HANDLE_MASTER__: ADC master handle
+ * @param __HANDLE_SLAVE__: ADC slave handle
+ * @retval None
+ */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ((__HANDLE_SLAVE__)->Instance = ADC2)
+
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || ((CHANNEL) == ADC_INJECTED_RANK_2) || ((CHANNEL) == ADC_INJECTED_RANK_3) || ((CHANNEL) == ADC_INJECTED_RANK_4))
+
+#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
+
+/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
+ * @{
+ */
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
+/**
+ * @}
+ */
+
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
+    || defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
+#endif
+#if defined(STM32F101xE)
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
+#endif
+#if defined(STM32F101xG)
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
+#endif
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                              \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)     \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)   \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
+#endif
+
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
+    || defined(STM32F105xC) || defined(STM32F107xC)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
+#endif
+#if defined(STM32F101xE)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
+#endif
+#if defined(STM32F101xG)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
+#endif
+#if defined(STM32F103xE) || defined(STM32F103xG)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)   \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)   \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
+#endif
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+#define IS_ADC_MODE(MODE)                                                                                                                                                                \
+  (((MODE) == ADC_MODE_INDEPENDENT) || ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) \
+   || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || ((MODE) == ADC_DUALMODE_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT) || ((MODE) == ADC_DUALMODE_INTERLFAST)               \
+   || ((MODE) == ADC_DUALMODE_INTERLSLOW) || ((MODE) == ADC_DUALMODE_ALTERTRIG))
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* ADC calibration */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+/** @addtogroup ADCEx_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected);
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_ADC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h

@@ -0,0 +1,372 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_cortex.h
+ * @author  MCD Application Team
+ * @brief   Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CORTEX_H
+#define __STM32F1xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1U)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @brief  MPU Region initialization structure
+ * @{
+ */
+typedef struct {
+  uint8_t Enable;           /*!< Specifies the status of the region.
+                                 This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t Number;           /*!< Specifies the number of the region to protect.
+                                 This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t BaseAddress;     /*!< Specifies the base address of the region to protect.                           */
+  uint8_t  Size;            /*!< Specifies the size of the region to protect.
+                                 This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
+  uint8_t TypeExtField;     /*!< Specifies the TEX field level.
+                                 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
+  uint8_t AccessPermission; /*!< Specifies the region access permission type.
+                                 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t DisableExec;      /*!< Specifies the instruction access status.
+                                 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t IsShareable;      /*!< Specifies the shareability status of the protected region.
+                                 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t IsCacheable;      /*!< Specifies the cacheable status of the region protected.
+                                 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t IsBufferable;     /*!< Specifies the bufferable status of the protected region.
+                                 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+} MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+#define NVIC_PRIORITYGROUP_0                       \
+  0x00000007U /*!< 0 bits for pre-emption priority \
+                   4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1                       \
+  0x00000006U /*!< 1 bits for pre-emption priority \
+                   3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2                       \
+  0x00000005U /*!< 2 bits for pre-emption priority \
+                   2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3                       \
+  0x00000004U /*!< 3 bits for pre-emption priority \
+                   1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4                       \
+  0x00000003U /*!< 4 bits for pre-emption priority \
+                   0 bits for subpriority */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK      0x00000004U
+
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
+#define MPU_HARDFAULT_NMI      MPU_CTRL_HFNMIENA_Msk
+#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
+#define MPU_HFNMI_PRIVDEF      (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE  ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE  ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE     ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE     ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE     ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B   ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B   ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B  ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B  ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B  ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB   ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB   ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB   ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB   ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB  ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB  ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB  ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB   ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB   ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB   ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB   ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB  ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB  ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB  ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB   ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB   ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB   ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS   ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW     ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO     ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void     HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void     HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void     HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void     HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void     HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void     HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void     HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void     HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void     HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void     HAL_SYSTICK_IRQHandler(void);
+void     HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) \
+  (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1U)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)                                                                                                                                    \
+  (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) \
+   || ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)                                                                                                                                                \
+  (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) \
+   || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)                                                                                                                                                          \
+  (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B)         \
+   || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB)        \
+   || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) \
+   || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB)        \
+   || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) \
+   || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h

@@ -0,0 +1,203 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_def.h
+ * @author  MCD Application Team
+ * @brief   This file contains HAL common defines, enumeration, macros and
+ *          structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DEF
+#define __STM32F1xx_HAL_DEF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "Legacy/stm32_hal_legacy.h"
+#include "stm32f1xx.h"
+#include <stddef.h>
+
+/* Exported types ------------------------------------------------------------*/
+#ifndef USE_HAL_TIM_REGISTER_CALLBACKS
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0
+#endif
+#ifndef USE_HAL_I2C_REGISTER_CALLBACKS
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0
+#endif
+#ifndef USE_HAL_ADC_REGISTER_CALLBACKS
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0
+#endif
+/**
+ * @brief  HAL Status structures definition
+ */
+typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef;
+
+/**
+ * @brief  HAL Lock structures definition
+ */
+typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#define HAL_MAX_DELAY 0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+  do {                                                               \
+    (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__);             \
+    (__DMA_HANDLE__).Parent         = (__HANDLE__);                  \
+  } while (0U)
+
+#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__ specifies the Peripheral Handle.
+ * @note  This macro can be used for the following purpose:
+ *          - When the Handle is declared as local variable; before passing it as parameter
+ *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ *            to set to 0 the Handle's "State" field.
+ *            Otherwise, "State" field may have any random value and the first time the function
+ *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ *            (i.e. HAL_PPP_MspInit() will not be executed).
+ *          - When there is a need to reconfigure the low level hardware: instead of calling
+ *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1U)
+/* Reserved for future use */
+#error "USE_RTOS should be 0 in the current HAL release"
+#else
+#define __HAL_LOCK(__HANDLE__)              \
+  do {                                      \
+    if ((__HANDLE__)->Lock == HAL_LOCKED) { \
+      return HAL_BUSY;                      \
+    } else {                                \
+      (__HANDLE__)->Lock = HAL_LOCKED;      \
+    }                                       \
+  } while (0U)
+
+#define __HAL_UNLOCK(__HANDLE__)       \
+  do {                                 \
+    (__HANDLE__)->Lock = HAL_UNLOCKED; \
+  } while (0U)
+#endif /* USE_RTOS */
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__((aligned(4)))
+#endif
+#elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__((aligned(4)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined(__CC_ARM) /* ARM Compiler V5*/
+#define __ALIGN_BEGIN __align(4)
+#elif defined(__ICCARM__) /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief  __RAM_FUNC definition
+ */
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+   --------------------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined(__ICCARM__)
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined(__GNUC__)
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+/**
+ * @brief  __NOINLINE definition
+ */
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined(__GNUC__)
+/* ARM V4/V5 and V6 & GNU Compiler
+   -------------------------------
+*/
+#define __NOINLINE __attribute__((noinline))
+
+#elif defined(__ICCARM__)
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F1xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h

@@ -0,0 +1,437 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_dma.h
+ * @author  MCD Application Team
+ * @brief   Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DMA_H
+#define __STM32F1xx_HAL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief  DMA Configuration Structure definition
+ */
+typedef struct {
+  uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+                           from memory to memory or from peripheral to memory.
+                           This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+  uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+  uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+                        This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+  uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+                                     This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+  uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+                                  This parameter can be a value of @ref DMA_Memory_data_size */
+
+  uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+                      This parameter can be a value of @ref DMA_mode
+                      @note The circular buffer mode cannot be used if the memory-to-memory
+                            data transfer is configured on the selected Channel */
+
+  uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+                          This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+ * @brief  HAL DMA State structures definition
+ */
+typedef enum {
+  HAL_DMA_STATE_RESET   = 0x00U, /*!< DMA not yet initialized or disabled    */
+  HAL_DMA_STATE_READY   = 0x01U, /*!< DMA initialized and ready for use      */
+  HAL_DMA_STATE_BUSY    = 0x02U, /*!< DMA process is ongoing                 */
+  HAL_DMA_STATE_TIMEOUT = 0x03U  /*!< DMA timeout state                      */
+} HAL_DMA_StateTypeDef;
+
+/**
+ * @brief  HAL DMA Error Code structure definition
+ */
+typedef enum {
+  HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER = 0x01U  /*!< Half Transfer     */
+} HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief  HAL DMA Callback ID structure definition
+ */
+typedef enum {
+  HAL_DMA_XFER_CPLT_CB_ID     = 0x00U, /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer     */
+  HAL_DMA_XFER_ERROR_CB_ID    = 0x02U, /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID    = 0x03U, /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID      = 0x04U  /*!< All               */
+
+} HAL_DMA_CallbackIDTypeDef;
+
+/**
+ * @brief  DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef {
+  DMA_Channel_TypeDef *Instance; /*!< Register base address                  */
+
+  DMA_InitTypeDef Init; /*!< DMA communication parameters           */
+
+  HAL_LockTypeDef Lock; /*!< DMA locking object                     */
+
+  HAL_DMA_StateTypeDef State; /*!< DMA transfer state                     */
+
+  void *Parent; /*!< Parent object state                    */
+
+  void (*XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback         */
+
+  void (*XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback    */
+
+  void (*XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback            */
+
+  void (*XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback            */
+
+  __IO uint32_t ErrorCode; /*!< DMA Error code                         */
+
+  DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address               */
+
+  uint32_t ChannelIndex; /*!< DMA Channel Index                      */
+
+} DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE          0x00000000U /*!< No error             */
+#define HAL_DMA_ERROR_TE            0x00000001U /*!< Transfer error       */
+#define HAL_DMA_ERROR_NO_XFER       0x00000004U /*!< no ongoing transfer  */
+#define HAL_DMA_ERROR_TIMEOUT       0x00000020U /*!< Timeout error        */
+#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode                    */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY 0x00000000U                 /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE  ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE 0x00000000U              /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE  ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable  */
+#define DMA_MINC_DISABLE 0x00000000U              /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE     0x00000000U                 /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD     ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word     */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE     0x00000000U                 /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD     ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word     */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode DMA mode
+ * @{
+ */
+#define DMA_NORMAL   0x00000000U              /*!< Normal mode                  */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode                */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @{
+ */
+#define DMA_PRIORITY_LOW       0x00000000U              /*!< Priority level : Low       */
+#define DMA_PRIORITY_MEDIUM    ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium    */
+#define DMA_PRIORITY_HIGH      ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High      */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)   /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @{
+ */
+#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @{
+ */
+#define DMA_FLAG_GL1 0x00000001U
+#define DMA_FLAG_TC1 0x00000002U
+#define DMA_FLAG_HT1 0x00000004U
+#define DMA_FLAG_TE1 0x00000008U
+#define DMA_FLAG_GL2 0x00000010U
+#define DMA_FLAG_TC2 0x00000020U
+#define DMA_FLAG_HT2 0x00000040U
+#define DMA_FLAG_TE2 0x00000080U
+#define DMA_FLAG_GL3 0x00000100U
+#define DMA_FLAG_TC3 0x00000200U
+#define DMA_FLAG_HT3 0x00000400U
+#define DMA_FLAG_TE3 0x00000800U
+#define DMA_FLAG_GL4 0x00001000U
+#define DMA_FLAG_TC4 0x00002000U
+#define DMA_FLAG_HT4 0x00004000U
+#define DMA_FLAG_TE4 0x00008000U
+#define DMA_FLAG_GL5 0x00010000U
+#define DMA_FLAG_TC5 0x00020000U
+#define DMA_FLAG_HT5 0x00040000U
+#define DMA_FLAG_TE5 0x00080000U
+#define DMA_FLAG_GL6 0x00100000U
+#define DMA_FLAG_TC6 0x00200000U
+#define DMA_FLAG_HT6 0x00400000U
+#define DMA_FLAG_TE6 0x00800000U
+#define DMA_FLAG_GL7 0x01000000U
+#define DMA_FLAG_TC7 0x02000000U
+#define DMA_FLAG_HT7 0x04000000U
+#define DMA_FLAG_TE7 0x08000000U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @brief  Reset DMA handle state.
+ * @param  __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief  Enable the specified DMA Channel.
+ * @param  __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+/**
+ * @brief  Disable the specified DMA Channel.
+ * @param  __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief  Enables the specified DMA Channel interrupts.
+ * @param  __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+ *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+ *            @arg DMA_IT_TE:  Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+
+/**
+ * @brief  Disable the specified DMA Channel interrupts.
+ * @param  __HANDLE__: DMA handle
+ * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+ *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+ *            @arg DMA_IT_TE:  Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+
+/**
+ * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
+ * @param  __HANDLE__: DMA handle
+ * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+ *          This parameter can be one of the following values:
+ *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+ *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+ *            @arg DMA_IT_TE:  Transfer error interrupt mask
+ * @retval The state of DMA_IT (SET or RESET).
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief  Return the number of remaining data units in the current DMA Channel transfer.
+ * @param  __HANDLE__: DMA handle
+ * @retval The number of remaining data units in the current DMA Channel transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+ * @}
+ */
+
+/* Include DMA HAL Extension module */
+#include "stm32f1xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @{
+ */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h

@@ -0,0 +1,320 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_dma_ex.h
+ * @author  MCD Application Team
+ * @brief   Header file of DMA HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DMA_EX_H
+#define __STM32F1xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMAEx DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
+ * @{
+ */
+/* Interrupt & Flag management */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
+ * @{
+ */
+
+/**
+ * @brief  Returns the current DMA Channel transfer complete flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)                                                                            \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
+       ? DMA_FLAG_TC1                                                                                                      \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
+             ? DMA_FLAG_TC2                                                                                                \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
+                   ? DMA_FLAG_TC3                                                                                          \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
+                         ? DMA_FLAG_TC4                                                                                    \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
+                               ? DMA_FLAG_TC5                                                                              \
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
+                                     ? DMA_FLAG_TC6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_TC7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_TC1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_TC2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_TC3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 : DMA_FLAG_TC5)
+
+/**
+ * @brief  Returns the current DMA Channel half transfer complete flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)                                                                            \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
+       ? DMA_FLAG_HT1                                                                                                      \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
+             ? DMA_FLAG_HT2                                                                                                \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
+                   ? DMA_FLAG_HT3                                                                                          \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
+                         ? DMA_FLAG_HT4                                                                                    \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
+                               ? DMA_FLAG_HT5                                                                              \
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
+                                     ? DMA_FLAG_HT6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_HT7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_HT1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_HT2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_HT3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 : DMA_FLAG_HT5)
+
+/**
+ * @brief  Returns the current DMA Channel transfer error flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)                                                                            \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
+       ? DMA_FLAG_TE1                                                                                                      \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
+             ? DMA_FLAG_TE2                                                                                                \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
+                   ? DMA_FLAG_TE3                                                                                          \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
+                         ? DMA_FLAG_TE4                                                                                    \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
+                               ? DMA_FLAG_TE5                                                                              \
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
+                                     ? DMA_FLAG_TE6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_TE7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_TE1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_TE2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_TE3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 : DMA_FLAG_TE5)
+
+/**
+ * @brief  Return the current DMA Channel Global interrupt flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)                                                                            \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
+       ? DMA_FLAG_GL1                                                                                                      \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
+             ? DMA_FLAG_GL2                                                                                                \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
+                   ? DMA_FLAG_GL3                                                                                          \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
+                         ? DMA_FLAG_GL4                                                                                    \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
+                               ? DMA_FLAG_GL5                                                                              \
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
+                                     ? DMA_FLAG_GL6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_GL7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_GL1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_GL2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_GL3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 : DMA_FLAG_GL5)
+
+/**
+ * @brief  Get the DMA Channel pending flags.
+ * @param  __HANDLE__: DMA handle
+ * @param  __FLAG__: Get the specified flag.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_FLAG_TCx:  Transfer complete flag
+ *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+ *            @arg DMA_FLAG_TEx:  Transfer error flag
+ *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
+
+/**
+ * @brief  Clears the DMA Channel pending flags.
+ * @param  __HANDLE__: DMA handle
+ * @param  __FLAG__: specifies the flag to clear.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_FLAG_TCx:  Transfer complete flag
+ *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+ *            @arg DMA_FLAG_TEx:  Transfer error flag
+ *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
+
+/**
+ * @}
+ */
+
+#else
+/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
+ * @{
+ */
+
+/**
+ * @brief  Returns the current DMA Channel transfer complete flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)                                                             \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
+       ? DMA_FLAG_TC1                                                                                       \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
+             ? DMA_FLAG_TC2                                                                                 \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
+                   ? DMA_FLAG_TC3                                                                           \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_TC4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 : DMA_FLAG_TC7)
+
+/**
+ * @brief  Return the current DMA Channel half transfer complete flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)                                                             \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
+       ? DMA_FLAG_HT1                                                                                       \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
+             ? DMA_FLAG_HT2                                                                                 \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
+                   ? DMA_FLAG_HT3                                                                           \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_HT4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 : DMA_FLAG_HT7)
+
+/**
+ * @brief  Return the current DMA Channel transfer error flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)                                                             \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
+       ? DMA_FLAG_TE1                                                                                       \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
+             ? DMA_FLAG_TE2                                                                                 \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
+                   ? DMA_FLAG_TE3                                                                           \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_TE4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 : DMA_FLAG_TE7)
+
+/**
+ * @brief  Return the current DMA Channel Global interrupt flag.
+ * @param  __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)                                                             \
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
+       ? DMA_FLAG_GL1                                                                                       \
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
+             ? DMA_FLAG_GL2                                                                                 \
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
+                   ? DMA_FLAG_GL3                                                                           \
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_GL4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 : DMA_FLAG_GL7)
+
+/**
+ * @brief  Get the DMA Channel pending flags.
+ * @param  __HANDLE__: DMA handle
+ * @param  __FLAG__: Get the specified flag.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_FLAG_TCx:  Transfer complete flag
+ *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+ *            @arg DMA_FLAG_TEx:  Transfer error flag
+ *            @arg DMA_FLAG_GLx:  Global interrupt flag
+ *         Where x can be 1_7 to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
+
+/**
+ * @brief  Clear the DMA Channel pending flags.
+ * @param  __HANDLE__: DMA handle
+ * @param  __FLAG__: specifies the flag to clear.
+ *          This parameter can be any combination of the following values:
+ *            @arg DMA_FLAG_TCx:  Transfer complete flag
+ *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+ *            @arg DMA_FLAG_TEx:  Transfer error flag
+ *            @arg DMA_FLAG_GLx:  Global interrupt flag
+ *         Where x can be 1_7 to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
+       /* STM32F103xG || STM32F105xC || STM32F107xC */
+
+#endif /* __STM32F1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h

@@ -0,0 +1,298 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_exti.h
+ * @author  MCD Application Team
+ * @brief   Header file of EXTI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_HAL_EXTI_H
+#define STM32F1xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup EXTI EXTI
+ * @brief EXTI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+ * @{
+ */
+
+/**
+ * @brief  HAL EXTI common Callback ID enumeration definition
+ */
+typedef enum { HAL_EXTI_COMMON_CB_ID = 0x00U } EXTI_CallbackIDTypeDef;
+
+/**
+ * @brief  EXTI Handle structure definition
+ */
+typedef struct {
+  uint32_t Line;                 /*!<  Exti line number */
+  void (*PendingCallback)(void); /*!<  Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+ * @brief  EXTI Configuration structure definition
+ */
+typedef struct {
+  uint32_t Line;    /*!< The Exti line to be configured. This parameter
+                         can be a value of @ref EXTI_Line */
+  uint32_t Mode;    /*!< The Exit Mode to be configured for a core.
+                         This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
+                         can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
+                         This parameter is only possible for line 0 to 15. It
+                         can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Line  EXTI Line
+ * @{
+ */
+#define EXTI_LINE_0  (EXTI_GPIO | 0x00u)   /*!< External interrupt line 0 */
+#define EXTI_LINE_1  (EXTI_GPIO | 0x01u)   /*!< External interrupt line 1 */
+#define EXTI_LINE_2  (EXTI_GPIO | 0x02u)   /*!< External interrupt line 2 */
+#define EXTI_LINE_3  (EXTI_GPIO | 0x03u)   /*!< External interrupt line 3 */
+#define EXTI_LINE_4  (EXTI_GPIO | 0x04u)   /*!< External interrupt line 4 */
+#define EXTI_LINE_5  (EXTI_GPIO | 0x05u)   /*!< External interrupt line 5 */
+#define EXTI_LINE_6  (EXTI_GPIO | 0x06u)   /*!< External interrupt line 6 */
+#define EXTI_LINE_7  (EXTI_GPIO | 0x07u)   /*!< External interrupt line 7 */
+#define EXTI_LINE_8  (EXTI_GPIO | 0x08u)   /*!< External interrupt line 8 */
+#define EXTI_LINE_9  (EXTI_GPIO | 0x09u)   /*!< External interrupt line 9 */
+#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au)   /*!< External interrupt line 10 */
+#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu)   /*!< External interrupt line 11 */
+#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu)   /*!< External interrupt line 12 */
+#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du)   /*!< External interrupt line 13 */
+#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu)   /*!< External interrupt line 14 */
+#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu)   /*!< External interrupt line 15 */
+#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#if defined(EXTI_IMR_IM18)
+#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */
+#endif                                     /* EXTI_IMR_IM18 */
+#if defined(EXTI_IMR_IM19)
+#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#endif                                     /* EXTI_IMR_IM19 */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+ * @{
+ */
+#define EXTI_MODE_NONE      0x00000000u
+#define EXTI_MODE_INTERRUPT 0x00000001u
+#define EXTI_MODE_EVENT     0x00000002u
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+ * @{
+ */
+#define EXTI_TRIGGER_NONE           0x00000000u
+#define EXTI_TRIGGER_RISING         0x00000001u
+#define EXTI_TRIGGER_FALLING        0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+ * @brief
+ * @{
+ */
+#define EXTI_GPIOA 0x00000000u
+#define EXTI_GPIOB 0x00000001u
+#define EXTI_GPIOC 0x00000002u
+#define EXTI_GPIOD 0x00000003u
+#if defined(GPIOE)
+#define EXTI_GPIOE 0x00000004u
+#endif /* GPIOE */
+#if defined(GPIOF)
+#define EXTI_GPIOF 0x00000005u
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define EXTI_GPIOG 0x00000006u
+#endif /* GPIOG */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+/**
+ * @brief  EXTI Line property definition
+ */
+#define EXTI_PROPERTY_SHIFT 24u
+#define EXTI_CONFIG         (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_PROPERTY_MASK  (EXTI_CONFIG | EXTI_GPIO)
+
+/**
+ * @brief  EXTI bit usage
+ */
+#define EXTI_PIN_MASK 0x0000001Fu
+
+/**
+ * @brief  EXTI Mask for interrupt & event mode
+ */
+#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+ * @brief  EXTI Mask for trigger possibilities
+ */
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+ * @brief  EXTI Line number
+ */
+#if defined(EXTI_IMR_IM19)
+#define EXTI_LINE_NB 20UL
+#elif defined(EXTI_IMR_IM18)
+#define EXTI_LINE_NB 19UL
+#else /* EXTI_IMR_IM17 */
+#define EXTI_LINE_NB 18UL
+#endif /* EXTI_IMR_IM19 */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+ * @{
+ */
+#define IS_EXTI_LINE(__LINE__)                                                                                                                                             \
+  ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && ((((__LINE__)&EXTI_PROPERTY_MASK) == EXTI_CONFIG) || (((__LINE__)&EXTI_PROPERTY_MASK) == EXTI_GPIO)) \
+   && (((__LINE__)&EXTI_PIN_MASK) < EXTI_LINE_NB))
+
+#define IS_EXTI_MODE(__LINE__) ((((__LINE__)&EXTI_MODE_MASK) != 0x00u) && (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+
+#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
+
+#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__)&EXTI_CONFIG) != 0x00u)
+
+#if defined(GPIOG)
+#define IS_EXTI_GPIO_PORT(__PORT__)                                                                                                                                                 \
+  (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOF) \
+   || ((__PORT__) == EXTI_GPIOG))
+#elif defined(GPIOF)
+#define IS_EXTI_GPIO_PORT(__PORT__) \
+  (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOF))
+#elif defined(GPIOE)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD))
+#endif /* GPIOG */
+
+#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+ * @brief    EXTI Exported Functions
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+ * @brief    Configuration functions
+ * @{
+ */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+ * @brief    IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+void     HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void     HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void     HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h

@@ -0,0 +1,320 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_flash.h
+ * @author  MCD Application Team
+ * @brief   Header file of Flash HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_FLASH_H
+#define __STM32F1xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+
+#if defined(FLASH_ACR_LATENCY)
+#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1) || ((__LATENCY__) == FLASH_LATENCY_2))
+
+#else
+#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
+#endif /* FLASH_ACR_LATENCY */
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+/**
+ * @brief  FLASH Procedure structure definition
+ */
+typedef enum {
+  FLASH_PROC_NONE              = 0U,
+  FLASH_PROC_PAGEERASE         = 1U,
+  FLASH_PROC_MASSERASE         = 2U,
+  FLASH_PROC_PROGRAMHALFWORD   = 3U,
+  FLASH_PROC_PROGRAMWORD       = 4U,
+  FLASH_PROC_PROGRAMDOUBLEWORD = 5U
+} FLASH_ProcedureTypeDef;
+
+/**
+ * @brief  FLASH handle Structure definition
+ */
+typedef struct {
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+
+  __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
+
+  __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
+
+  __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
+
+  HAL_LockTypeDef Lock; /*!< FLASH locking object                */
+
+  __IO uint32_t ErrorCode; /*!< FLASH error code
+                                This parameter can be a value of @ref FLASH_Error_Codes  */
+} FLASH_ProcessTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Error_Codes FLASH Error Codes
+ * @{
+ */
+
+#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
+#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
+#define HAL_FLASH_ERROR_WRP  0x02U /*!< Write protection error */
+#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+ * @{
+ */
+#define FLASH_TYPEPROGRAM_HALFWORD   0x01U /*!<Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_WORD       0x02U /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/
+
+/**
+ * @}
+ */
+
+#if defined(FLASH_ACR_LATENCY)
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#define FLASH_LATENCY_0 0x00000000U         /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
+
+/**
+ * @}
+ */
+
+#else
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
+
+/**
+ * @}
+ */
+
+#endif /* FLASH_ACR_LATENCY */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ *  @brief macros to control FLASH features
+ *  @{
+ */
+
+/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
+ *  @brief macros to handle FLASH half cycle
+ * @{
+ */
+
+/**
+  * @brief  Enable the FLASH half cycle access.
+  * @note   half cycle access can only be used with a low-frequency clock of less than
+            8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
+  * @retval None
+  */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
+
+/**
+  * @brief  Disable the FLASH half cycle access.
+  * @note   half cycle access can only be used with a low-frequency clock of less than
+            8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
+  * @retval None
+  */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
+
+/**
+ * @}
+ */
+
+#if defined(FLASH_ACR_LATENCY)
+/** @defgroup FLASH_EM_Latency FLASH Latency
+ *  @brief macros to handle FLASH Latency
+ * @{
+ */
+
+/**
+ * @brief  Set the FLASH Latency.
+ * @param  __LATENCY__ FLASH Latency
+ *         The value of this parameter depend on device used within the same series
+ * @retval None
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__))
+
+/**
+ * @brief  Get the FLASH Latency.
+ * @retval FLASH Latency
+ *         The value of this parameter depend on device used within the same series
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+ * @}
+ */
+
+#endif /* FLASH_ACR_LATENCY */
+/** @defgroup FLASH_Prefetch FLASH Prefetch
+ *  @brief macros to handle FLASH Prefetch buffer
+ * @{
+ */
+/**
+ * @brief  Enable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
+
+/**
+ * @brief  Disable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extended module */
+#include "stm32f1xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+
+/* FLASH IRQ handler function */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+void              HAL_FLASH_OB_Launch(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_FLASH_GetError(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function -------------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+#if defined(FLASH_BANK2_END)
+HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
+#endif /* FLASH_BANK2_END */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h

@@ -0,0 +1,775 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_flash_ex.h
+ * @author  MCD Application Team
+ * @brief   Header file of Flash HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_FLASH_EX_H
+#define __STM32F1xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Private_Constants
+ * @{
+ */
+
+#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
+#define OBR_REG_INDEX            1U
+#define SR_FLAG_MASK             ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
+
+#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#if defined(FLASH_BANK2_END)
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+#endif /* FLASH_BANK2_END */
+
+/* Low Density */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                                  \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U)                      \
+       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU)        \
+       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U)               \
+              ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU) \
+              : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))))
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                           \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U)              \
+       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0807FFFFU) \
+       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0805FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU)))
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080FFFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080BFFFFU))
+#endif /* FLASH_BANK2_END */
+
+/* Connectivity Line */
+#if (defined(STM32F105xC) || defined(STM32F107xC))
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                           \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U)              \
+       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU) \
+       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU)))
+#endif /* STM32F105xC || STM32F107xC */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
+
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || ((BANK) == FLASH_BANK_BOTH))
+#else
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* FLASH_BANK2_END */
+
+/* Low Density */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
+
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                      \
+  (((ADDRESS) >= FLASH_BASE)                                                                   \
+   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U)                                    \
+           ? ((ADDRESS) <= FLASH_BANK1_END)                                                    \
+           : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS) <= 0x0800FFFF) \
+                                                                   : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
+
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                     \
+  (((ADDRESS) >= FLASH_BASE)                                                                  \
+   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS) <= FLASH_BANK1_END) \
+                                                             : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
+
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
+
+#endif /* FLASH_BANK2_END */
+
+/* Connectivity Line */
+#if (defined(STM32F105xC) || defined(STM32F107xC))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                     \
+  (((ADDRESS) >= FLASH_BASE)                                                                  \
+   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS) <= FLASH_BANK1_END) \
+                                                             : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief  FLASH Erase structure definition
+ */
+typedef struct {
+  uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
+                           This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+  uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
+                       This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
+                             This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
+                             (x = 1 or 2 depending on devices)*/
+
+  uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
+                         This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief  FLASH Options bytes program structure definition
+ */
+typedef struct {
+  uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+                            This parameter can be a value of @ref FLASHEx_OB_Type */
+
+  uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+                          This parameter can be a value of @ref FLASHEx_OB_WRP_State */
+
+  uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
+                         This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
+
+  uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
+                       This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+                         This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
+
+#if defined(FLASH_BANK2_END)
+  uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+                           IWDG / STOP / STDBY / BOOT1
+                           This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
+                           @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
+#else
+  uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+                           IWDG / STOP / STDBY
+                           This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
+                           @ref FLASHEx_OB_nRST_STDBY */
+#endif /* FLASH_BANK2_END */
+
+  uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
+                             This parameter can be a value of @ref FLASHEx_OB_Data_Address */
+
+  uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
+                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Constants FLASH Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Page_Size Page Size
+ * @{
+ */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define FLASH_PAGE_SIZE 0x400U
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+       /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
+#define FLASH_PAGE_SIZE 0x800U
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+       /* STM32F101xG || STM32F103xG */
+       /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Type_Erase Type Erase
+ * @{
+ */
+#define FLASH_TYPEERASE_PAGES     0x00U /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE 0x02U /*!<Flash mass erase activation*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Banks Banks
+ * @{
+ */
+#if defined(FLASH_BANK2_END)
+#define FLASH_BANK_1    1U                                      /*!< Bank 1   */
+#define FLASH_BANK_2    2U                                      /*!< Bank 2   */
+#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+
+#else
+#define FLASH_BANK_1 1U /*!< Bank 1   */
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_OB_Type Option Bytes Type
+ * @{
+ */
+#define OPTIONBYTE_WRP  0x01U /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP  0x02U /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER 0x04U /*!<USER option byte configuration*/
+#define OPTIONBYTE_DATA 0x08U /*!<DATA option byte configuration*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
+ * @{
+ */
+#define OB_WRPSTATE_DISABLE 0x00U /*!<Disable the write protection of the desired pages*/
+#define OB_WRPSTATE_ENABLE  0x01U /*!<Enable the write protection of the desired pagess*/
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
+ * @{
+ */
+/* STM32 Low and Medium density devices */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES0TO3   0x00000001U /*!< Write protection of page 0 to 3 */
+#define OB_WRP_PAGES4TO7   0x00000002U /*!< Write protection of page 4 to 7 */
+#define OB_WRP_PAGES8TO11  0x00000004U /*!< Write protection of page 8 to 11 */
+#define OB_WRP_PAGES12TO15 0x00000008U /*!< Write protection of page 12 to 15 */
+#define OB_WRP_PAGES16TO19 0x00000010U /*!< Write protection of page 16 to 19 */
+#define OB_WRP_PAGES20TO23 0x00000020U /*!< Write protection of page 20 to 23 */
+#define OB_WRP_PAGES24TO27 0x00000040U /*!< Write protection of page 24 to 27 */
+#define OB_WRP_PAGES28TO31 0x00000080U /*!< Write protection of page 28 to 31 */
+#endif                                 /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+                                       /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+/* STM32 Medium-density devices */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES32TO35   0x00000100U /*!< Write protection of page 32 to 35 */
+#define OB_WRP_PAGES36TO39   0x00000200U /*!< Write protection of page 36 to 39 */
+#define OB_WRP_PAGES40TO43   0x00000400U /*!< Write protection of page 40 to 43 */
+#define OB_WRP_PAGES44TO47   0x00000800U /*!< Write protection of page 44 to 47 */
+#define OB_WRP_PAGES48TO51   0x00001000U /*!< Write protection of page 48 to 51 */
+#define OB_WRP_PAGES52TO55   0x00002000U /*!< Write protection of page 52 to 55 */
+#define OB_WRP_PAGES56TO59   0x00004000U /*!< Write protection of page 56 to 59 */
+#define OB_WRP_PAGES60TO63   0x00008000U /*!< Write protection of page 60 to 63 */
+#define OB_WRP_PAGES64TO67   0x00010000U /*!< Write protection of page 64 to 67 */
+#define OB_WRP_PAGES68TO71   0x00020000U /*!< Write protection of page 68 to 71 */
+#define OB_WRP_PAGES72TO75   0x00040000U /*!< Write protection of page 72 to 75 */
+#define OB_WRP_PAGES76TO79   0x00080000U /*!< Write protection of page 76 to 79 */
+#define OB_WRP_PAGES80TO83   0x00100000U /*!< Write protection of page 80 to 83 */
+#define OB_WRP_PAGES84TO87   0x00200000U /*!< Write protection of page 84 to 87 */
+#define OB_WRP_PAGES88TO91   0x00400000U /*!< Write protection of page 88 to 91 */
+#define OB_WRP_PAGES92TO95   0x00800000U /*!< Write protection of page 92 to 95 */
+#define OB_WRP_PAGES96TO99   0x01000000U /*!< Write protection of page 96 to 99 */
+#define OB_WRP_PAGES100TO103 0x02000000U /*!< Write protection of page 100 to 103 */
+#define OB_WRP_PAGES104TO107 0x04000000U /*!< Write protection of page 104 to 107 */
+#define OB_WRP_PAGES108TO111 0x08000000U /*!< Write protection of page 108 to 111 */
+#define OB_WRP_PAGES112TO115 0x10000000U /*!< Write protection of page 112 to 115 */
+#define OB_WRP_PAGES116TO119 0x20000000U /*!< Write protection of page 115 to 119 */
+#define OB_WRP_PAGES120TO123 0x40000000U /*!< Write protection of page 120 to 123 */
+#define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */
+#endif                                   /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+/* STM32 High-density, XL-density and Connectivity line devices */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+#define OB_WRP_PAGES0TO1    0x00000001U /*!< Write protection of page 0 TO 1 */
+#define OB_WRP_PAGES2TO3    0x00000002U /*!< Write protection of page 2 TO 3 */
+#define OB_WRP_PAGES4TO5    0x00000004U /*!< Write protection of page 4 TO 5 */
+#define OB_WRP_PAGES6TO7    0x00000008U /*!< Write protection of page 6 TO 7 */
+#define OB_WRP_PAGES8TO9    0x00000010U /*!< Write protection of page 8 TO 9 */
+#define OB_WRP_PAGES10TO11  0x00000020U /*!< Write protection of page 10 TO 11 */
+#define OB_WRP_PAGES12TO13  0x00000040U /*!< Write protection of page 12 TO 13 */
+#define OB_WRP_PAGES14TO15  0x00000080U /*!< Write protection of page 14 TO 15 */
+#define OB_WRP_PAGES16TO17  0x00000100U /*!< Write protection of page 16 TO 17 */
+#define OB_WRP_PAGES18TO19  0x00000200U /*!< Write protection of page 18 TO 19 */
+#define OB_WRP_PAGES20TO21  0x00000400U /*!< Write protection of page 20 TO 21 */
+#define OB_WRP_PAGES22TO23  0x00000800U /*!< Write protection of page 22 TO 23 */
+#define OB_WRP_PAGES24TO25  0x00001000U /*!< Write protection of page 24 TO 25 */
+#define OB_WRP_PAGES26TO27  0x00002000U /*!< Write protection of page 26 TO 27 */
+#define OB_WRP_PAGES28TO29  0x00004000U /*!< Write protection of page 28 TO 29 */
+#define OB_WRP_PAGES30TO31  0x00008000U /*!< Write protection of page 30 TO 31 */
+#define OB_WRP_PAGES32TO33  0x00010000U /*!< Write protection of page 32 TO 33 */
+#define OB_WRP_PAGES34TO35  0x00020000U /*!< Write protection of page 34 TO 35 */
+#define OB_WRP_PAGES36TO37  0x00040000U /*!< Write protection of page 36 TO 37 */
+#define OB_WRP_PAGES38TO39  0x00080000U /*!< Write protection of page 38 TO 39 */
+#define OB_WRP_PAGES40TO41  0x00100000U /*!< Write protection of page 40 TO 41 */
+#define OB_WRP_PAGES42TO43  0x00200000U /*!< Write protection of page 42 TO 43 */
+#define OB_WRP_PAGES44TO45  0x00400000U /*!< Write protection of page 44 TO 45 */
+#define OB_WRP_PAGES46TO47  0x00800000U /*!< Write protection of page 46 TO 47 */
+#define OB_WRP_PAGES48TO49  0x01000000U /*!< Write protection of page 48 TO 49 */
+#define OB_WRP_PAGES50TO51  0x02000000U /*!< Write protection of page 50 TO 51 */
+#define OB_WRP_PAGES52TO53  0x04000000U /*!< Write protection of page 52 TO 53 */
+#define OB_WRP_PAGES54TO55  0x08000000U /*!< Write protection of page 54 TO 55 */
+#define OB_WRP_PAGES56TO57  0x10000000U /*!< Write protection of page 56 TO 57 */
+#define OB_WRP_PAGES58TO59  0x20000000U /*!< Write protection of page 58 TO 59 */
+#define OB_WRP_PAGES60TO61  0x40000000U /*!< Write protection of page 60 TO 61 */
+#define OB_WRP_PAGES62TO127 0x80000000U /*!< Write protection of page 62 TO 127 */
+#define OB_WRP_PAGES62TO255 0x80000000U /*!< Write protection of page 62 TO 255 */
+#define OB_WRP_PAGES62TO511 0x80000000U /*!< Write protection of page 62 TO 511 */
+#endif                                  /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+                                        /* STM32F101xG || STM32F103xG */
+                                        /* STM32F105xC || STM32F107xC */
+
+#define OB_WRP_ALLPAGES 0xFFFFFFFFU /*!< Write protection of all Pages */
+
+/* Low Density */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
+#define OB_WRP_PAGES0TO31MASK 0x000000FFU
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES0TO31MASK   0x000000FFU
+#define OB_WRP_PAGES32TO63MASK  0x0000FF00U
+#define OB_WRP_PAGES64TO95MASK  0x00FF0000U
+#define OB_WRP_PAGES96TO127MASK 0xFF000000U
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
+#define OB_WRP_PAGES0TO15MASK   0x000000FFU
+#define OB_WRP_PAGES16TO31MASK  0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK  0x00FF0000U
+#define OB_WRP_PAGES48TO255MASK 0xFF000000U
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(STM32F101xG) || defined(STM32F103xG)
+#define OB_WRP_PAGES0TO15MASK   0x000000FFU
+#define OB_WRP_PAGES16TO31MASK  0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK  0x00FF0000U
+#define OB_WRP_PAGES48TO511MASK 0xFF000000U
+#endif /* STM32F101xG || STM32F103xG */
+
+/* Connectivity line devices */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define OB_WRP_PAGES0TO15MASK   0x000000FFU
+#define OB_WRP_PAGES16TO31MASK  0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK  0x00FF0000U
+#define OB_WRP_PAGES48TO127MASK 0xFF000000U
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xA5)
+#define OB_RDP_LEVEL_1 ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
+ * @{
+ */
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
+ * @{
+ */
+#define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST    ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
+ * @{
+ */
+#define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST    ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+/**
+ * @}
+ */
+
+#if defined(FLASH_BANK2_END)
+/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
+ * @{
+ */
+#define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET   ((uint16_t)0x0008) /*!< BOOT1 Set */
+/**
+ * @}
+ */
+#endif /* FLASH_BANK2_END */
+
+/** @defgroup FLASHEx_OB_Data_Address  Option Byte Data Address
+ * @{
+ */
+#define OB_DATA_ADDRESS_DATA0 0x1FFFF804U
+#define OB_DATA_ADDRESS_DATA1 0x1FFFF806U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Flag_definition Flag definition
+ * @brief Flag definition
+ * @{
+ */
+#if defined(FLASH_BANK2_END)
+#define FLASH_FLAG_BSY    FLASH_FLAG_BSY_BANK1    /*!< FLASH Bank1 Busy flag                   */
+#define FLASH_FLAG_PGERR  FLASH_FLAG_PGERR_BANK1  /*!< FLASH Bank1 Programming error flag      */
+#define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag  */
+#define FLASH_FLAG_EOP    FLASH_FLAG_EOP_BANK1    /*!< FLASH Bank1 End of Operation flag       */
+
+#define FLASH_FLAG_BSY_BANK1    FLASH_SR_BSY      /*!< FLASH Bank1 Busy flag                   */
+#define FLASH_FLAG_PGERR_BANK1  FLASH_SR_PGERR    /*!< FLASH Bank1 Programming error flag      */
+#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag  */
+#define FLASH_FLAG_EOP_BANK1    FLASH_SR_EOP      /*!< FLASH Bank1 End of Operation flag       */
+
+#define FLASH_FLAG_BSY_BANK2    (FLASH_SR2_BSY << 16U)      /*!< FLASH Bank2 Busy flag                   */
+#define FLASH_FLAG_PGERR_BANK2  (FLASH_SR2_PGERR << 16U)    /*!< FLASH Bank2 Programming error flag      */
+#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag  */
+#define FLASH_FLAG_EOP_BANK2    (FLASH_SR2_EOP << 16U)      /*!< FLASH Bank2 End of Operation flag       */
+
+#else
+
+#define FLASH_FLAG_BSY    FLASH_SR_BSY      /*!< FLASH Busy flag                          */
+#define FLASH_FLAG_PGERR  FLASH_SR_PGERR    /*!< FLASH Programming error flag             */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag         */
+#define FLASH_FLAG_EOP    FLASH_SR_EOP      /*!< FLASH End of Operation flag              */
+
+#endif
+#define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error        */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition Interrupt definition
+ * @brief FLASH Interrupt definition
+ * @{
+ */
+#if defined(FLASH_BANK2_END)
+#define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */
+#define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1                  */
+
+#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */
+#define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1                  */
+
+#define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */
+#define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2                  */
+
+#else
+
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source                  */
+
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
+ * @{
+ */
+
+/** @defgroup FLASH_Interrupt Interrupt
+ *  @brief macros to handle FLASH interrupts
+ * @{
+ */
+
+#if defined(FLASH_BANK2_END)
+/**
+ * @brief  Enable the specified FLASH interrupt.
+ * @param  __INTERRUPT__  FLASH interrupt
+ *     This parameter can be any combination of the following values:
+ *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
+ *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
+ *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
+ *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)           \
+  do {                                                 \
+    /* Enable Bank1 IT */                              \
+    SET_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
+    /* Enable Bank2 IT */                              \
+    SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U));     \
+  } while (0U)
+
+/**
+ * @brief  Disable the specified FLASH interrupt.
+ * @param  __INTERRUPT__  FLASH interrupt
+ *     This parameter can be any combination of the following values:
+ *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
+ *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
+ *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
+ *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)            \
+  do {                                                   \
+    /* Disable Bank1 IT */                               \
+    CLEAR_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
+    /* Disable Bank2 IT */                               \
+    CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U));     \
+  } while (0U)
+
+/**
+ * @brief  Get the specified FLASH flag status.
+ * @param  __FLAG__ specifies the FLASH flag to check.
+ *          This parameter can be one of the following values:
+ *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
+ *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
+ *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
+ *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
+ *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
+ *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
+ *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
+ *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
+ *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) \
+  (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : ((((__FLAG__)&SR_FLAG_MASK) != RESET) ? (FLASH->SR & ((__FLAG__)&SR_FLAG_MASK)) : (FLASH->SR2 & ((__FLAG__) >> 16U))))
+
+/**
+ * @brief  Clear the specified FLASH flag.
+ * @param  __FLAG__ specifies the FLASH flags to clear.
+ *          This parameter can be any combination of the following values:
+ *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
+ *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
+ *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
+ *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
+ *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
+ *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
+ *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
+ *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
+ *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        \
+  do {                                          \
+    /* Clear FLASH_FLAG_OPTVERR flag */         \
+    if ((__FLAG__) == FLASH_FLAG_OPTVERR) {     \
+      CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR);  \
+    } else {                                    \
+      /* Clear Flag in Bank1 */                 \
+      if (((__FLAG__)&SR_FLAG_MASK) != RESET) { \
+        FLASH->SR = ((__FLAG__)&SR_FLAG_MASK);  \
+      }                                         \
+      /* Clear Flag in Bank2 */                 \
+      if (((__FLAG__) >> 16U) != RESET) {       \
+        FLASH->SR2 = ((__FLAG__) >> 16U);       \
+      }                                         \
+    }                                           \
+  } while (0U)
+#else
+                      /**
+                       * @brief  Enable the specified FLASH interrupt.
+                       * @param  __INTERRUPT__  FLASH interrupt
+                       *         This parameter can be any combination of the following values:
+                       *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+                       *     @arg @ref FLASH_IT_ERR Error Interrupt
+                       * @retval none
+                       */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
+
+/**
+ * @brief  Disable the specified FLASH interrupt.
+ * @param  __INTERRUPT__  FLASH interrupt
+ *         This parameter can be any combination of the following values:
+ *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+ *     @arg @ref FLASH_IT_ERR Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief  Get the specified FLASH flag status.
+ * @param  __FLAG__ specifies the FLASH flag to check.
+ *          This parameter can be one of the following values:
+ *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag
+ *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
+ *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag
+ *            @arg @ref FLASH_FLAG_BSY    FLASH Busy flag
+ *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__)        (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : (FLASH->SR & (__FLAG__)))
+/**
+ * @brief  Clear the specified FLASH flag.
+ * @param  __FLAG__ specifies the FLASH flags to clear.
+ *          This parameter can be any combination of the following values:
+ *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag
+ *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
+ *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag
+ *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)       \
+  do {                                         \
+    /* Clear FLASH_FLAG_OPTVERR flag */        \
+    if ((__FLAG__) == FLASH_FLAG_OPTVERR) {    \
+      CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
+    } else {                                   \
+      /* Clear Flag in Bank1 */                \
+      FLASH->SR = (__FLAG__);                  \
+    }                                          \
+  } while (0U)
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+uint32_t          HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h

@@ -0,0 +1,293 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_gpio.h
+ * @author  MCD Application Team
+ * @brief   Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_HAL_GPIO_H
+#define STM32F1xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct {
+  uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+                     This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+                      This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                      This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed; /*!< Specifies the speed for the selected pins.
+                       This parameter can be a value of @ref GPIO_speed_define */
+} GPIO_InitTypeDef;
+
+/**
+ * @brief  GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum { GPIO_PIN_RESET = 0u, GPIO_PIN_SET } GPIO_PinState;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define GPIO pins define
+ * @{
+ */
+#define GPIO_PIN_0   ((uint16_t)0x0001) /* Pin 0 selected    */
+#define GPIO_PIN_1   ((uint16_t)0x0002) /* Pin 1 selected    */
+#define GPIO_PIN_2   ((uint16_t)0x0004) /* Pin 2 selected    */
+#define GPIO_PIN_3   ((uint16_t)0x0008) /* Pin 3 selected    */
+#define GPIO_PIN_4   ((uint16_t)0x0010) /* Pin 4 selected    */
+#define GPIO_PIN_5   ((uint16_t)0x0020) /* Pin 5 selected    */
+#define GPIO_PIN_6   ((uint16_t)0x0040) /* Pin 6 selected    */
+#define GPIO_PIN_7   ((uint16_t)0x0080) /* Pin 7 selected    */
+#define GPIO_PIN_8   ((uint16_t)0x0100) /* Pin 8 selected    */
+#define GPIO_PIN_9   ((uint16_t)0x0200) /* Pin 9 selected    */
+#define GPIO_PIN_10  ((uint16_t)0x0400) /* Pin 10 selected   */
+#define GPIO_PIN_11  ((uint16_t)0x0800) /* Pin 11 selected   */
+#define GPIO_PIN_12  ((uint16_t)0x1000) /* Pin 12 selected   */
+#define GPIO_PIN_13  ((uint16_t)0x2000) /* Pin 13 selected   */
+#define GPIO_PIN_14  ((uint16_t)0x4000) /* Pin 14 selected   */
+#define GPIO_PIN_15  ((uint16_t)0x8000) /* Pin 15 selected   */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode_define GPIO mode define
+ * @brief GPIO Configuration Mode
+ *        Elements values convention: 0xX0yz00YZ
+ *           - X  : GPIO mode or EXTI Mode
+ *           - y  : External IT or Event trigger detection
+ *           - z  : IO configuration on External IT or Event
+ *           - Y  : Output type (Push Pull or Open Drain)
+ *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT     0x00000000u     /*!< Input Floating Mode                   */
+#define GPIO_MODE_OUTPUT_PP 0x00000001u     /*!< Output Push Pull Mode                 */
+#define GPIO_MODE_OUTPUT_OD 0x00000011u     /*!< Output Open Drain Mode                */
+#define GPIO_MODE_AF_PP     0x00000002u     /*!< Alternate Function Push Pull Mode     */
+#define GPIO_MODE_AF_OD     0x00000012u     /*!< Alternate Function Open Drain Mode    */
+#define GPIO_MODE_AF_INPUT  GPIO_MODE_INPUT /*!< Alternate Function Input Mode         */
+
+#define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode  */
+
+#define GPIO_MODE_IT_RISING         0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define GPIO_MODE_IT_FALLING        0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+
+#define GPIO_MODE_EVT_RISING         0x10120000u /*!< External Event Mode with Rising edge trigger detection               */
+#define GPIO_MODE_EVT_FALLING        0x10220000u /*!< External Event Mode with Falling edge trigger detection              */
+#define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection       */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_speed_define  GPIO speed define
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_FREQ_LOW    (GPIO_CRL_MODE0_1) /*!< Low speed */
+#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
+#define GPIO_SPEED_FREQ_HIGH   (GPIO_CRL_MODE0)   /*!< High speed */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_pull_define GPIO pull define
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL   0x00000000u /*!< No Pull-up or Pull-down activation  */
+#define GPIO_PULLUP   0x00000001u /*!< Pull-up activation                  */
+#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation                */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief  Checks whether the specified EXTI line flag is set or not.
+ * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+ *         This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief  Clears the EXTI's line pending flags.
+ * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+ *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief  Checks whether the specified EXTI line is asserted or not.
+ * @param  __EXTI_LINE__: specifies the EXTI line to check.
+ *          This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief  Clears the EXTI's line pending bits.
+ * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+ *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief  Generates a Software interrupt on selected EXTI line.
+ * @param  __EXTI_LINE__: specifies the EXTI line to check.
+ *          This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+/**
+ * @}
+ */
+
+/* Include GPIO HAL Extension module */
+#include "stm32f1xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(PIN)           (((((uint32_t)PIN) & GPIO_PIN_MASK) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u))
+#define IS_GPIO_MODE(MODE)                                                                                                                                                                             \
+  (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING)  \
+   || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) \
+   || ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
+#define IS_GPIO_PULL(PULL)   (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h

@@ -0,0 +1,881 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_gpio_ex.h
+ * @author  MCD Application Team
+ * @brief   Header file of GPIO HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_HAL_GPIO_EX_H
+#define STM32F1xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
+ * @brief This section propose definition to use the Cortex EVENTOUT signal.
+ * @{
+ */
+
+/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
+ * @{
+ */
+
+#define AFIO_EVENTOUT_PIN_0  AFIO_EVCR_PIN_PX0  /*!< EVENTOUT on pin 0 */
+#define AFIO_EVENTOUT_PIN_1  AFIO_EVCR_PIN_PX1  /*!< EVENTOUT on pin 1 */
+#define AFIO_EVENTOUT_PIN_2  AFIO_EVCR_PIN_PX2  /*!< EVENTOUT on pin 2 */
+#define AFIO_EVENTOUT_PIN_3  AFIO_EVCR_PIN_PX3  /*!< EVENTOUT on pin 3 */
+#define AFIO_EVENTOUT_PIN_4  AFIO_EVCR_PIN_PX4  /*!< EVENTOUT on pin 4 */
+#define AFIO_EVENTOUT_PIN_5  AFIO_EVCR_PIN_PX5  /*!< EVENTOUT on pin 5 */
+#define AFIO_EVENTOUT_PIN_6  AFIO_EVCR_PIN_PX6  /*!< EVENTOUT on pin 6 */
+#define AFIO_EVENTOUT_PIN_7  AFIO_EVCR_PIN_PX7  /*!< EVENTOUT on pin 7 */
+#define AFIO_EVENTOUT_PIN_8  AFIO_EVCR_PIN_PX8  /*!< EVENTOUT on pin 8 */
+#define AFIO_EVENTOUT_PIN_9  AFIO_EVCR_PIN_PX9  /*!< EVENTOUT on pin 9 */
+#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
+#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
+#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
+#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
+#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
+#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
+
+#define IS_AFIO_EVENTOUT_PIN(__PIN__)                                                                                                                                                                 \
+  (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4)         \
+   || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9)      \
+   || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) \
+   || ((__PIN__) == AFIO_EVENTOUT_PIN_15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
+ * @{
+ */
+
+#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
+#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
+#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
+#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
+#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
+
+#define IS_AFIO_EVENTOUT_PORT(__PORT__) \
+  (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
+ * @brief This section propose definition to remap the alternate function to some other port/pins.
+ * @{
+ */
+
+/**
+ * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @note  ENABLE: Remap     (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
+
+/**
+ * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
+
+/**
+ * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
+ * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
+
+/**
+ * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
+ * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
+
+/**
+ * @brief Enable the remapping of USART1 alternate function TX and RX.
+ * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
+
+/**
+ * @brief Disable the remapping of USART1 alternate function TX and RX.
+ * @note  DISABLE: No remap (TX/PA9, RX/PA10)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
+
+/**
+ * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
+
+/**
+ * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
+
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+ * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+ * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+ * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @note  ENABLE: Full remap     (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
+ * @note  TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @note  PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
+ * @note  TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+ * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
+ * @note  DISABLE: No remap      (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
+ * @note  TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+ * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
+ * @note  ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
+ * @note  TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
+ * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
+ * @note  TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)
+
+#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)
+
+#endif
+
+/**
+ * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ *        on 100-pin and 144-pin packages, no need for remapping).
+ * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)
+
+/**
+ * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ *        on 100-pin and 144-pin packages, no need for remapping).
+ * @note  DISABLE: No remapping of PD0 and PD1
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)
+
+#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
+/**
+ * @brief Enable the remapping of TIM5CH4.
+ * @note  ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
+ * @note  This function is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)
+
+/**
+ * @brief Disable the remapping of TIM5CH4.
+ * @note  DISABLE: TIM5_CH4 is connected to PA3
+ * @note  This function is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)
+#endif
+
+#if defined(AFIO_MAPR_ETH_REMAP)
+/**
+ * @brief Enable the remapping of Ethernet MAC connections with the PHY.
+ * @note  ENABLE: Remap     (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)
+
+/**
+ * @brief Disable the remapping of Ethernet MAC connections with the PHY.
+ * @note  DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5,  RXD2/PB0,  RXD3/PB1)
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_CAN2_REMAP)
+
+/**
+ * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @note  ENABLE: Remap     (CAN2_RX/PB5,  CAN2_TX/PB6)
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)
+
+/**
+ * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_MII_RMII_SEL)
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @note  ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)
+
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @note  ETH_MII: Configure Ethernet MAC for connection with an MII PHY
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)
+#endif
+
+/**
+ * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
+
+#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
+#endif
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note  ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note  NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @note  NOJTAG: JTAG-DP Disabled and SW-DP Enabled
+ * @retval None
+ */
+
+#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
+
+/**
+ * @brief Disable the Serial wire JTAG configuration
+ * @note  DISABLE: JTAG-DP Disabled and SW-DP Disabled
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)
+
+#if defined(AFIO_MAPR_SPI3_REMAP)
+
+/**
+ * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @note  ENABLE: Remap     (SPI3_NSS-I2S3_WS/PA4,  SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)
+
+/**
+ * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @note  DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3,  SPI3_MISO/PB4,  SPI3_MOSI-I2S3_SD/PB5).
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @note  TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @note  TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
+#endif
+
+#if defined(AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note  ENABLE: PTP_PPS is output on PB5 pin.
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @note  DISABLE: PTP_PPS not output on PB5 pin.
+ * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM9_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @note  ENABLE: Remap     (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @note  DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM10_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM10_CH1.
+ * @note  ENABLE: Remap     (TIM10_CH1 on PF6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM10_CH1.
+ * @note  DISABLE: No remap (TIM10_CH1 on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM11_REMAP)
+/**
+ * @brief Enable the remapping of TIM11_CH1.
+ * @note  ENABLE: Remap     (TIM11_CH1 on PF7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM11_CH1.
+ * @note  DISABLE: No remap (TIM11_CH1 on PB9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM13_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM13_CH1.
+ * @note  ENABLE: Remap     STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM13_CH1.
+ * @note  DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM14_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM14_CH1.
+ * @note  ENABLE: Remap     STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM14_CH1.
+ * @note  DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @note  DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
+ * @retval None
+ */
+#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @note  CONNECTED: The NADV signal is connected to the output (default).
+ * @retval None
+ */
+#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM15_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @note  ENABLE: Remap     (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @note  DISABLE: No remap (TIM15_CH1 on PA2  and TIM15_CH2 on PA3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM16_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM16_CH1.
+ * @note  ENABLE: Remap     (TIM16_CH1 on PA6).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM16_CH1.
+ * @note  DISABLE: No remap (TIM16_CH1 on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM17_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM17_CH1.
+ * @note  ENABLE: Remap     (TIM17_CH1 on PA7).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM17_CH1.
+ * @note  DISABLE: No remap (TIM17_CH1 on PB9).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_CEC_REMAP)
+
+/**
+ * @brief Enable the remapping of CEC.
+ * @note  ENABLE: Remap     (CEC on PB10).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
+
+/**
+ * @brief Disable the remapping of CEC.
+ * @note  DISABLE: No remap (CEC on PB8).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @note  ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @note  DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @note  ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @note  DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM12_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @note  ENABLE: Remap     (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
+ * @note  This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
+
+/**
+ * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @note  DISABLE: No remap (TIM12_CH1 on PC4  and TIM12_CH2 on PC5).
+ * @note  This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_MISC_REMAP)
+
+/**
+ * @brief Miscellaneous features remapping.
+ *        This bit is set and cleared by software. It controls miscellaneous features.
+ *        The DMA2 channel 5 interrupt position in the vector table.
+ *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @note  ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
+ *        selected as DAC Trigger 3, TIM15 triggers TIM1/3.
+ * @note  This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
+
+/**
+ * @brief Miscellaneous features remapping.
+ *        This bit is set and cleared by software. It controls miscellaneous features.
+ *        The DMA2 channel 5 interrupt position in the vector table.
+ *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @note  DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
+ *        event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
+ * @note  This bit is available only in high density value line devices.
+ * @retval None
+ */
+#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
+ * @{
+ */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0uL : ((__GPIOx__) == (GPIOB)) ? 1uL : ((__GPIOx__) == (GPIOC)) ? 2uL : 3uL)
+#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0uL : ((__GPIOx__) == (GPIOB)) ? 1uL : ((__GPIOx__) == (GPIOC)) ? 2uL : ((__GPIOx__) == (GPIOD)) ? 3uL : 4uL)
+#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#define GPIO_GET_INDEX(__GPIOx__) \
+  (((__GPIOx__) == (GPIOA))       \
+       ? 0uL                      \
+       : ((__GPIOx__) == (GPIOB)) ? 1uL : ((__GPIOx__) == (GPIOC)) ? 2uL : ((__GPIOx__) == (GPIOD)) ? 3uL : ((__GPIOx__) == (GPIOE)) ? 4uL : ((__GPIOx__) == (GPIOF)) ? 5uL : 6uL)
+#endif
+
+#define AFIO_REMAP_ENABLE(REMAP_PIN) \
+  do {                               \
+    uint32_t tmpreg = AFIO->MAPR;    \
+    tmpreg |= AFIO_MAPR_SWJ_CFG;     \
+    tmpreg |= REMAP_PIN;             \
+    AFIO->MAPR = tmpreg;             \
+  } while (0u)
+
+#define AFIO_REMAP_DISABLE(REMAP_PIN) \
+  do {                                \
+    uint32_t tmpreg = AFIO->MAPR;     \
+    tmpreg |= AFIO_MAPR_SWJ_CFG;      \
+    tmpreg &= ~REMAP_PIN;             \
+    AFIO->MAPR = tmpreg;              \
+  } while (0u)
+
+#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) \
+  do {                                                \
+    uint32_t tmpreg = AFIO->MAPR;                     \
+    tmpreg &= ~REMAP_PIN_MASK;                        \
+    tmpreg |= AFIO_MAPR_SWJ_CFG;                      \
+    tmpreg |= REMAP_PIN;                              \
+    AFIO->MAPR = tmpreg;                              \
+  } while (0u)
+
+#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) \
+  do {                                    \
+    uint32_t tmpreg = AFIO->MAPR;         \
+    tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk;     \
+    tmpreg |= DBGAFR_SWJCFG;              \
+    AFIO->MAPR = tmpreg;                  \
+  } while (0u)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GPIOEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIOEx_Exported_Functions_Group1
+ * @{
+ */
+void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
+void HAL_GPIOEx_EnableEventout(void);
+void HAL_GPIOEx_DisableEventout(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h

@@ -0,0 +1,727 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_i2c.h
+ * @author  MCD Application Team
+ * @brief   Header file of I2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_I2C_H
+#define __STM32F1xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+ * @brief  I2C Configuration Structure definition
+ * @{
+ */
+typedef struct {
+  uint32_t ClockSpeed; /*!< Specifies the clock frequency.
+                            This parameter must be set to a value lower than 400kHz */
+
+  uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+                           This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint32_t OwnAddress1; /*!< Specifies the first device own address.
+                             This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                This parameter can be a value of @ref I2C_addressing_mode */
+
+  uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+                                 This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+  uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+                             This parameter can be a 7-bit address. */
+
+  uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+                                 This parameter can be a value of @ref I2C_general_call_addressing_mode */
+
+  uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+                               This parameter can be a value of @ref I2C_nostretch_mode */
+
+} I2C_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+ * @brief  HAL State structure definition
+ * @note  HAL I2C State value coding follow below described bitmap :
+ *          b7-b6  Error information
+ *             00 : No Error
+ *             01 : Abort (Abort user request on going)
+ *             10 : Timeout
+ *             11 : Error
+ *          b5     Peripheral initilisation status
+ *             0  : Reset (Peripheral not initialized)
+ *             1  : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
+ *          b4     (not used)
+ *             x  : Should be set to 0
+ *          b3
+ *             0  : Ready or Busy (No Listen mode ongoing)
+ *             1  : Listen (Peripheral in Address Listen Mode)
+ *          b2     Intrinsic process state
+ *             0  : Ready
+ *             1  : Busy (Peripheral busy with some configuration or internal operations)
+ *          b1     Rx state
+ *             0  : Ready (no Rx operation ongoing)
+ *             1  : Busy (Rx operation ongoing)
+ *          b0     Tx state
+ *             0  : Ready (no Tx operation ongoing)
+ *             1  : Busy (Tx operation ongoing)
+ * @{
+ */
+typedef enum {
+  HAL_I2C_STATE_RESET          = 0x00U, /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY          = 0x20U, /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY           = 0x24U, /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX        = 0x21U, /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX        = 0x22U, /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN         = 0x28U, /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
+                                            process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
+                                            process is ongoing                         */
+  HAL_I2C_STATE_ABORT   = 0x60U,        /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT = 0xA0U,        /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR   = 0xE0U         /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+ * @brief  HAL Mode structure definition
+ * @note  HAL I2C Mode value coding follow below described bitmap :\n
+ *          b7     (not used)\n
+ *             x  : Should be set to 0\n
+ *          b6\n
+ *             0  : None\n
+ *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+ *          b5\n
+ *             0  : None\n
+ *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+ *          b4\n
+ *             0  : None\n
+ *             1  : Master (HAL I2C communication is in Master Mode)\n
+ *          b3-b2-b1-b0  (not used)\n
+ *             xxxx : Should be set to 0000
+ * @{
+ */
+typedef enum {
+  HAL_I2C_MODE_NONE   = 0x00U, /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE  = 0x20U, /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM    = 0x40U  /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+ * @brief  I2C Error Code definition
+ * @{
+ */
+#define HAL_I2C_ERROR_NONE      0x00000000U /*!< No error              */
+#define HAL_I2C_ERROR_BERR      0x00000001U /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      0x00000002U /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        0x00000004U /*!< AF error              */
+#define HAL_I2C_ERROR_OVR       0x00000008U /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       0x00000010U /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   0x00000020U /*!< Timeout Error         */
+#define HAL_I2C_ERROR_SIZE      0x00000040U /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error   */
+#define HAL_I2C_WRONG_START     0x00000200U /*!< Wrong start Error     */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
+#endif                                             /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+ * @brief  I2C handle Structure definition
+ * @{
+ */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+typedef struct __I2C_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+{
+  I2C_TypeDef *Instance; /*!< I2C registers base address               */
+
+  I2C_InitTypeDef Init; /*!< I2C communication parameters             */
+
+  uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer           */
+
+  uint16_t XferSize; /*!< I2C transfer size                        */
+
+  __IO uint16_t XferCount; /*!< I2C transfer counter                     */
+
+  __IO uint32_t XferOptions; /*!< I2C transfer options                     */
+
+  __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
+                                    context for internal usage               */
+
+  DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters             */
+
+  DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters             */
+
+  HAL_LockTypeDef Lock; /*!< I2C locking object                       */
+
+  __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state                  */
+
+  __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode                   */
+
+  __IO uint32_t ErrorCode; /*!< I2C Error code                           */
+
+  __IO uint32_t Devaddress; /*!< I2C Target device address                */
+
+  __IO uint32_t Memaddress; /*!< I2C Target memory address                */
+
+  __IO uint32_t MemaddSize; /*!< I2C Target memory address  size          */
+
+  __IO uint32_t EventCount; /*!< I2C Event counter                        */
+#ifndef USE_HAL_I2C_REGISTER_CALLBACKS
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0
+#endif
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (*MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
+  void (*MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
+  void (*SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);  /*!< I2C Slave Tx Transfer completed callback  */
+  void (*SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);  /*!< I2C Slave Rx Transfer completed callback  */
+  void (*ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);   /*!< I2C Listen Complete callback              */
+  void (*MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);    /*!< I2C Memory Tx Transfer completed callback */
+  void (*MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);    /*!< I2C Memory Rx Transfer completed callback */
+  void (*ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);        /*!< I2C Error callback                        */
+  void (*AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);    /*!< I2C Abort callback                        */
+
+  void (*AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
+
+  void (*MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);   /*!< I2C Msp Init callback                     */
+  void (*MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback                   */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief  HAL I2C Callback ID enumeration definition
+ */
+typedef enum {
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID  = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID  = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID    = 0x04U, /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID    = 0x05U, /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID    = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID              = 0x07U, /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID              = 0x08U, /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID   = 0x09U, /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID = 0x0AU  /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+ * @brief  HAL I2C Callback pointer definition
+ */
+typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);                                                        /*!< pointer to an I2C callback function */
+typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
+ * @{
+ */
+#define I2C_DUTYCYCLE_2    0x00000000U
+#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
+/**
+ * @}
+ */
+
+/** @defgroup I2C_addressing_mode I2C addressing mode
+ * @{
+ */
+#define I2C_ADDRESSINGMODE_7BIT  0x00004000U
+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLE 0x00000000U
+#define I2C_DUALADDRESS_ENABLE  I2C_OAR2_ENDUAL
+/**
+ * @}
+ */
+
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
+ * @{
+ */
+#define I2C_GENERALCALL_DISABLE 0x00000000U
+#define I2C_GENERALCALL_ENABLE  I2C_CR1_ENGC
+/**
+ * @}
+ */
+
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLE 0x00000000U
+#define I2C_NOSTRETCH_ENABLE  I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+ * @{
+ */
+#define I2C_MEMADD_SIZE_8BIT  0x00000001U
+#define I2C_MEMADD_SIZE_16BIT 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
+ * @{
+ */
+#define I2C_DIRECTION_RECEIVE  0x00000000U
+#define I2C_DIRECTION_TRANSMIT 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
+ * @{
+ */
+#define I2C_FIRST_FRAME          0x00000001U
+#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U
+#define I2C_NEXT_FRAME           0x00000004U
+#define I2C_FIRST_AND_LAST_FRAME 0x00000008U
+#define I2C_LAST_FRAME_NO_STOP   0x00000010U
+#define I2C_LAST_FRAME           0x00000020U
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define I2C_OTHER_FRAME          (0x00AA0000U)
+#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+ * @brief I2C Interrupt definition
+ *        Elements values convention: 0xXXXXXXXX
+ *           - XXXXXXXX  : Interrupt control mask
+ * @{
+ */
+#define I2C_IT_BUF I2C_CR2_ITBUFEN
+#define I2C_IT_EVT I2C_CR2_ITEVTEN
+#define I2C_IT_ERR I2C_CR2_ITERREN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+ * @{
+ */
+
+#define I2C_FLAG_OVR     0x00010800U
+#define I2C_FLAG_AF      0x00010400U
+#define I2C_FLAG_ARLO    0x00010200U
+#define I2C_FLAG_BERR    0x00010100U
+#define I2C_FLAG_TXE     0x00010080U
+#define I2C_FLAG_RXNE    0x00010040U
+#define I2C_FLAG_STOPF   0x00010010U
+#define I2C_FLAG_ADD10   0x00010008U
+#define I2C_FLAG_BTF     0x00010004U
+#define I2C_FLAG_ADDR    0x00010002U
+#define I2C_FLAG_SB      0x00010001U
+#define I2C_FLAG_DUALF   0x00100080U
+#define I2C_FLAG_GENCALL 0x00100010U
+#define I2C_FLAG_TRA     0x00100004U
+#define I2C_FLAG_BUSY    0x00100002U
+#define I2C_FLAG_MSL     0x00100001U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2C handle state.
+ * @param  __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)           \
+  do {                                                     \
+    (__HANDLE__)->State             = HAL_I2C_STATE_RESET; \
+    (__HANDLE__)->MspInitCallback   = NULL;                \
+    (__HANDLE__)->MspDeInitCallback = NULL;                \
+  } while (0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
+
+/** @brief  Enable or disable the specified I2C interrupts.
+ * @param  __HANDLE__ specifies the I2C Handle.
+ * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+ *         This parameter can be one of the following values:
+ *            @arg I2C_IT_BUF: Buffer interrupt enable
+ *            @arg I2C_IT_EVT: Event interrupt enable
+ *            @arg I2C_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
+ * @param  __HANDLE__ specifies the I2C Handle.
+ * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+ *          This parameter can be one of the following values:
+ *            @arg I2C_IT_BUF: Buffer interrupt enable
+ *            @arg I2C_IT_EVT: Event interrupt enable
+ *            @arg I2C_IT_ERR: Error interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks whether the specified I2C flag is set or not.
+ * @param  __HANDLE__ specifies the I2C Handle.
+ * @param  __FLAG__ specifies the flag to check.
+ *         This parameter can be one of the following values:
+ *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
+ *            @arg I2C_FLAG_AF: Acknowledge failure flag
+ *            @arg I2C_FLAG_ARLO: Arbitration lost flag
+ *            @arg I2C_FLAG_BERR: Bus error flag
+ *            @arg I2C_FLAG_TXE: Data register empty flag
+ *            @arg I2C_FLAG_RXNE: Data register not empty flag
+ *            @arg I2C_FLAG_STOPF: Stop detection flag
+ *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
+ *            @arg I2C_FLAG_BTF: Byte transfer finished flag
+ *            @arg I2C_FLAG_ADDR: Address sent flag
+ *                                Address matched flag
+ *            @arg I2C_FLAG_SB: Start bit flag
+ *            @arg I2C_FLAG_DUALF: Dual flag
+ *            @arg I2C_FLAG_GENCALL: General call header flag
+ *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ *            @arg I2C_FLAG_BUSY: Bus busy flag
+ *            @arg I2C_FLAG_MSL: Master/Slave flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)                                                                                                            \
+  ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? (((((__HANDLE__)->Instance->SR1) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)) ? SET : RESET) \
+                                             : (((((__HANDLE__)->Instance->SR2) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)) ? SET : RESET))
+
+/** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
+ * @param  __HANDLE__ specifies the I2C Handle.
+ * @param  __FLAG__ specifies the flag to clear.
+ *         This parameter can be any combination of the following values:
+ *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ *            @arg I2C_FLAG_AF: Acknowledge failure flag
+ *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ *            @arg I2C_FLAG_BERR: Bus error flag
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__)&I2C_FLAG_MASK))
+
+/** @brief  Clears the I2C ADDR pending flag.
+ * @param  __HANDLE__ specifies the I2C Handle.
+ *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)            \
+  do {                                                  \
+    __IO uint32_t tmpreg = 0x00U;                       \
+    tmpreg               = (__HANDLE__)->Instance->SR1; \
+    tmpreg               = (__HANDLE__)->Instance->SR2; \
+    UNUSED(tmpreg);                                     \
+  } while (0)
+
+/** @brief  Clears the I2C STOPF pending flag.
+ * @param  __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)            \
+  do {                                                  \
+    __IO uint32_t tmpreg = 0x00U;                       \
+    tmpreg               = (__HANDLE__)->Instance->SR1; \
+    SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);   \
+    UNUSED(tmpreg);                                     \
+  } while (0)
+
+/** @brief  Enable the specified I2C peripheral.
+ * @param  __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
+
+/** @brief  Disable the specified I2C peripheral.
+ * @param  __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void              HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void              HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @{
+ */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+#define I2C_FLAG_MASK              0x0000FFFFU
+#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz                     */
+#define I2C_MIN_PCLK_FREQ_FAST     4000000U /*!< 4 MHz                     */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macros I2C Private Macros
+ * @{
+ */
+
+#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__)              (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
+#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__)-1U) / ((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
+#define I2C_FREQRANGE(__PCLK__)                             ((__PCLK__) / 1000000U)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)             (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__)*300U) / 1000U) + 1U))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)             ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U) ? 4U : I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) \
+  (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2) ? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)                       \
+  (((__SPEED__) <= 100000U) ? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) \
+                            : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U) ? 1U : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_READ(__ADDRESS__)  ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define I2C_10BIT_ADDRESS(__ADDRESS__)      ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__)  ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+
+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
+ * @{
+ */
+#define IS_I2C_DUTY_CYCLE(CYCLE)        (((CYCLE) == I2C_DUTYCYCLE_2) || ((CYCLE) == I2C_DUTYCYCLE_16_9))
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || ((CALL) == I2C_GENERALCALL_ENABLE))
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+#define IS_I2C_CLOCK_SPEED(SPEED)       (((SPEED) > 0U) && ((SPEED) <= 400000U))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)   (((ADDRESS1)&0xFFFFFC00U) == 0U)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)   (((ADDRESS2)&0xFFFFFF01U) == 0U)
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)                                                                                                                                          \
+  (((REQUEST) == I2C_FIRST_FRAME) || ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || ((REQUEST) == I2C_NEXT_FRAME) || ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME) \
+   || ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)    ((((__ISR__) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h

@@ -0,0 +1,214 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_iwdg.h
+ * @author  MCD Application Team
+ * @brief   Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_HAL_IWDG_H
+#define STM32F1xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IWDG IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief  IWDG Init structure definition
+ */
+typedef struct {
+  uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+                           This parameter can be a value of @ref IWDG_Prescaler */
+
+  uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+                        This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/**
+ * @brief  IWDG Handle Structure definition
+ */
+typedef struct {
+  IWDG_TypeDef *Instance; /*!< Register base address    */
+
+  IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+} IWDG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4   0x00000000U                   /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8   IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16  IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32  (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64  IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/**
+ * @brief  Enable the IWDG peripheral.
+ * @param  __HANDLE__  IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+ * @brief  Reload IWDG counter with value defined in the reload register
+ *         (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param  __HANDLE__  IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+ * @{
+ */
+/* Initialization/Start functions  ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+/**
+ * @brief  IWDG Key Register BitMask
+ */
+#define IWDG_KEY_RELOAD               0x0000AAAAU /*!< IWDG Reload Counter Enable   */
+#define IWDG_KEY_ENABLE               0x0000CCCCU /*!< IWDG Peripheral Enable       */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE  0x00005555U /*!< IWDG KR Write Access Enable  */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+ * @{
+ */
+
+/**
+ * @brief  Enable write access to IWDG_PR and IWDG_RLR registers.
+ * @param  __HANDLE__  IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief  Disable write access to IWDG_PR and IWDG_RLR registers.
+ * @param  __HANDLE__  IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+ * @brief  Check IWDG prescaler value.
+ * @param  __PRESCALER__  IWDG prescaler value
+ * @retval None
+ */
+#define IS_IWDG_PRESCALER(__PRESCALER__)                                                                                                                              \
+  (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) \
+   || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128) || ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+ * @brief  Check IWDG reload value.
+ * @param  __RELOAD__  IWDG reload value
+ * @retval None
+ */
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h

@@ -0,0 +1,372 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_pwr.h
+ * @author  MCD Application Team
+ * @brief   Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_PWR_H
+#define __STM32F1xx_HAL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+ * @{
+ */
+
+/**
+ * @brief  PWR PVD configuration structure definition
+ */
+typedef struct {
+  uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
+                          This parameter can be a value of @ref PWR_PVD_detection_level */
+
+  uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+                      This parameter can be a value of @ref PWR_PVD_Mode */
+} PWR_PVDTypeDef;
+
+/**
+ * @}
+ */
+
+/* Internal constants --------------------------------------------------------*/
+
+/** @addtogroup PWR_Private_Constants
+ * @{
+ */
+
+#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
+#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
+#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
+#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
+#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
+#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
+#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+ * @{
+ */
+#define PWR_PVD_MODE_NORMAL               0x00000000U /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING            0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING           0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING    0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING         0x00020001U /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING        0x00020002U /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
+ * @{
+ */
+
+#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON     0x00000000U
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag PWR Flag
+ * @{
+ */
+#define PWR_FLAG_WU   PWR_CSR_WUF
+#define PWR_FLAG_SB   PWR_CSR_SBF
+#define PWR_FLAG_PVDO PWR_CSR_PVDO
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @brief  Check PWR flag is set or not.
+ * @param  __FLAG__: specifies the flag to check.
+ *           This parameter can be one of the following values:
+ *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+ *                  was received from the WKUP pin or from the RTC alarm
+ *                  An additional wakeup event is detected if the WKUP pin is enabled
+ *                  (by setting the EWUP bit) when the WKUP pin level is already high.
+ *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ *                  resumed from StandBy mode.
+ *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+ *                  For this reason, this bit is equal to 0 after Standby or reset
+ *                  until the PVDE bit is set.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the PWR's pending flags.
+ * @param  __FLAG__: specifies the flag to clear.
+ *          This parameter can be one of the following values:
+ *            @arg PWR_FLAG_WU: Wake Up flag
+ *            @arg PWR_FLAG_SB: StandBy flag
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
+
+/**
+ * @brief Enable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief  PVD EXTI line configuration: set falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief  PVD EXTI line configuration: set rising edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();              \
+  __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();              \
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Clear the PVD EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+#define IS_PWR_PVD_LEVEL(LEVEL)                                                                                                                                                           \
+  (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) \
+   || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+
+#define IS_PWR_PVD_MODE(MODE)                                                                                                                                       \
+  (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) \
+   || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *******************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+/* #define HAL_PWR_ConfigPVD 12*/
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h

@@ -0,0 +1,255 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_tim_ex.h
+ * @author  MCD Application Team
+ * @brief   Header file of TIM HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_HAL_TIM_EX_H
+#define STM32F1xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief  TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct {
+  uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+                             This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter; /*!< Specifies the input capture filter.
+                           This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+/**
+ * @}
+ */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ *  @brief    Timer Hall Sensor functions
+ * @{
+ */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ *  @brief   Timer Complementary Output Compare functions
+ * @{
+ */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ *  @brief    Timer Complementary PWM functions
+ * @{
+ */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ *  @brief    Timer Complementary One Pulse functions
+ * @{
+ */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ *  @brief    Peripheral Control functions
+ * @{
+ */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief    Extended Callbacks functions
+ * @{
+ */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief    Extended Peripheral State functions
+ * @{
+ */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef        HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c

@@ -0,0 +1,535 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL.
+    [..]
+    The HAL contains two APIs' categories:
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @brief HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+/**
+ * @brief STM32F1xx HAL Driver version number V1.1.7
+ */
+#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
+#define __STM32F1xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8]  sub2 version */
+#define __STM32F1xx_HAL_VERSION_RC   (0x00U) /*!< [7:0]  release candidate */
+#define __STM32F1xx_HAL_VERSION      ((__STM32F1xx_HAL_VERSION_MAIN << 24) | (__STM32F1xx_HAL_VERSION_SUB1 << 16) | (__STM32F1xx_HAL_VERSION_SUB2 << 8) | (__STM32F1xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK 0x00000FFFU
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+__IO uint32_t       uwTick;
+uint32_t            uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;     /* 1KHz */
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+   [..]  This section provides functions allowing to:
+      (+) Initializes the Flash interface, the NVIC allocation and initial clock
+          configuration. It initializes the systick also when timeout is needed
+          and the backup domain when enabled.
+      (+) de-Initializes common part of the HAL.
+      (+) Configure The time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  This function is used to initialize the HAL Library; it must be the first
+ *         instruction to be executed in the main program (before to call any other
+ *         HAL function), it performs the following:
+ *           Configure the Flash prefetch.
+ *           Configures the SysTick to generate an interrupt each 1 millisecond,
+ *           which is clocked by the HSI (at this stage, the clock is not yet
+ *           configured and thus the system is running from the internal HSI at 16 MHz).
+ *           Set NVIC Group Priority to 4.
+ *           Calls the HAL_MspInit() callback function defined in user file
+ *           "stm32f1xx_hal_msp.c" to do the global low level hardware initialization
+ *
+ * @note   SysTick is used as time base for the HAL_Delay() function, the application
+ *         need to ensure that the SysTick time base is always set to 1 millisecond
+ *         to have correct HAL operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void) {
+  /* Configure Flash prefetch */
+#if (PREFETCH_ENABLE != 0)
+#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
+    || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+
+  /* Prefetch buffer is not available on value line devices */
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif
+#endif /* PREFETCH_ENABLE */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  HAL_InitTick(TICK_INT_PRIORITY);
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the systick.
+ *        of time base.
+ * @note This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void) {
+  /* Reset of all peripherals */
+  __HAL_RCC_APB1_FORCE_RESET();
+  __HAL_RCC_APB1_RELEASE_RESET();
+
+  __HAL_RCC_APB2_FORCE_RESET();
+  __HAL_RCC_APB2_RELEASE_RESET();
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  __HAL_RCC_AHB_FORCE_RESET();
+  __HAL_RCC_AHB_RELEASE_RESET();
+#endif
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+ * @brief  Initialize the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void) {
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+ * @brief  DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void) {
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+ * @brief This function configures the source of the time base.
+ *        The time source is configured  to have 1ms time base with a dedicated
+ *        Tick interrupt priority.
+ * @note This function is called  automatically at the beginning of program after
+ *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ *       It is used to generate interrupts at regular time intervals.
+ *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ *       The SysTick interrupt must have higher priority (numerically lower)
+ *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ *       The function is declared as __weak  to be overwritten  in case of other
+ *       implementation  in user file.
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS)) {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  } else {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+  *  @brief    HAL Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief This function is called to increment  a global variable "uwTick"
+ *        used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ *       in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ *      implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void) { uwTick += uwTickFreq; }
+
+/**
+ * @brief Provides a tick value in millisecond.
+ * @note  This function is declared as __weak to be overwritten in case of other
+ *       implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void) { return uwTick; }
+
+/**
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void) { return uwTickPrio; }
+
+/**
+ * @brief Set new tick Freq.
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) {
+  HAL_StatusTypeDef   status = HAL_OK;
+  HAL_TickFreqTypeDef prevTickFreq;
+
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq) {
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+
+    if (status != HAL_OK) {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+ * @brief Return tick frequency.
+ * @retval tick period in Hz
+ */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void) { return uwTickFreq; }
+
+/**
+ * @brief This function provides minimum delay (in milliseconds) based
+ *        on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ *       It is used to generate interrupts at regular time intervals where uwTick
+ *       is incremented.
+ * @note This function is declared as __weak to be overwritten in case of other
+ *       implementations in user file.
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(uint32_t Delay) {
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait      = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY) {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait) {}
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ *       is called, the SysTick interrupt will be disabled and so Tick increment
+ *       is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ *       implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void) {
+  /* Disable SysTick Interrupt */
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ *       is called, the SysTick interrupt will be enabled and so Tick increment
+ *       is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ *       implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void) {
+  /* Enable SysTick Interrupt */
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief  Returns the HAL revision
+ * @retval version 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void) { return __STM32F1xx_HAL_VERSION; }
+
+/**
+ * @brief Returns the device revision identifier.
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ *                  STM32F101xC/D/E and STM32F103xC/D/E,
+ *                  STM32F101xF/G and STM32F103xF/G
+ *                  STM32F10xx4 and STM32F10xx6
+ *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ *       debug mode (not accessible by the user software in normal mode).
+ *       Refer to errata sheet of these devices for more details.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void) { return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); }
+
+/**
+ * @brief  Returns the device identifier.
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ *                  STM32F101xC/D/E and STM32F103xC/D/E,
+ *                  STM32F101xF/G and STM32F103xF/G
+ *                  STM32F10xx4 and STM32F10xx6
+ *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ *       debug mode (not accessible by the user software in normal mode).
+ *       Refer to errata sheet of these devices for more details.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void) { return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); }
+
+/**
+ * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw0(void) { return (READ_REG(*((uint32_t *)UID_BASE))); }
+
+/**
+ * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw1(void) { return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); }
+
+/**
+ * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw2(void) { return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); }
+
+/**
+ * @brief  Enable the Debug Module during SLEEP mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); }
+
+/**
+ * @brief  Disable the Debug Module during SLEEP mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ *                  STM32F101xC/D/E and STM32F103xC/D/E,
+ *                  STM32F101xF/G and STM32F103xF/G
+ *                  STM32F10xx4 and STM32F10xx6
+ *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ *       debug mode (not accessible by the user software in normal mode).
+ *       Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); }
+
+/**
+ * @brief  Enable the Debug Module during STOP mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ *                  STM32F101xC/D/E and STM32F103xC/D/E,
+ *                  STM32F101xF/G and STM32F103xF/G
+ *                  STM32F10xx4 and STM32F10xx6
+ *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ *       debug mode (not accessible by the user software in normal mode).
+ *       Refer to errata sheet of these devices for more details.
+ * Note: On all STM32F1 devices:
+ *       If the system tick timer interrupt is enabled during the Stop mode
+ *       debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
+ *       the system from Stop mode.
+ *       Workaround: To debug the Stop mode, disable the system tick timer
+ *       interrupt.
+ *       Refer to errata sheet of these devices for more details.
+ * Note: On all STM32F1 devices:
+ *       If the system tick timer interrupt is enabled during the Stop mode
+ *       debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
+ *       the system from Stop mode.
+ *       Workaround: To debug the Stop mode, disable the system tick timer
+ *       interrupt.
+ *       Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); }
+
+/**
+ * @brief  Disable the Debug Module during STOP mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ *                  STM32F101xC/D/E and STM32F103xC/D/E,
+ *                  STM32F101xF/G and STM32F103xF/G
+ *                  STM32F10xx4 and STM32F10xx6
+ *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ *       debug mode (not accessible by the user software in normal mode).
+ *       Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); }
+
+/**
+ * @brief  Enable the Debug Module during STANDBY mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ *                  STM32F101xC/D/E and STM32F103xC/D/E,
+ *                  STM32F101xF/G and STM32F103xF/G
+ *                  STM32F10xx4 and STM32F10xx6
+ *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ *       debug mode (not accessible by the user software in normal mode).
+ *       Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); }
+
+/**
+ * @brief  Disable the Debug Module during STANDBY mode
+ * Note: On devices STM32F10xx8 and STM32F10xxB,
+ *                  STM32F101xC/D/E and STM32F103xC/D/E,
+ *                  STM32F101xF/G and STM32F103xF/G
+ *                  STM32F10xx4 and STM32F10xx6
+ *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+ *       debug mode (not accessible by the user software in normal mode).
+ *       Refer to errata sheet of these devices for more details.
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); }
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c

@@ -0,0 +1,469 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CORTEX:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M3 exceptions are managed by CMSIS functions.
+
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+        function according to the following table.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+    (#) please refer to programming manual for details in how to configure priority.
+
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
+         The pending IRQ priority will be managed only by the sub priority.
+
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest preemption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+
+    [..]
+    *** How to configure Systick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+
+   (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+       inside the stm32f1xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX
+ * @brief CORTEX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      Systick functionalities
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Sets the priority grouping field (preemption priority and subpriority)
+ *         using the required unlock sequence.
+ * @param  PriorityGroup: The priority grouping bits length.
+ *         This parameter can be one of the following values:
+ *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+ *                                    4 bits for subpriority
+ *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+ *                                    3 bits for subpriority
+ *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+ *                                    2 bits for subpriority
+ *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+ *                                    1 bits for subpriority
+ *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+ *                                    0 bits for subpriority
+ * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+ *         The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+ * @brief  Sets the priority of an interrupt.
+ * @param  IRQn: External interrupt number.
+ *         This parameter can be an enumerator of IRQn_Type enumeration
+ *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))
+ * @param  PreemptPriority: The preemption priority for the IRQn channel.
+ *         This parameter can be a value between 0 and 15
+ *         A lower priority value indicates a higher priority
+ * @param  SubPriority: the subpriority level for the IRQ channel.
+ *         This parameter can be a value between 0 and 15
+ *         A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) {
+  uint32_t prioritygroup = 0x00U;
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+  prioritygroup = NVIC_GetPriorityGrouping();
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+ * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ *         function should be called before.
+ * @param  IRQn External interrupt number.
+ *         This parameter can be an enumerator of IRQn_Type enumeration
+ *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) {
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param  IRQn External interrupt number.
+ *         This parameter can be an enumerator of IRQn_Type enumeration
+ *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) {
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief  Initiates a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void) {
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+ * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ *         Counter is in free running mode to generate periodic interrupts.
+ * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status:  - 0  Function succeeded.
+ *                  - 1  Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); }
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+  *  @brief   Cortex control functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ * @brief  Disables the MPU
+ * @retval None
+ */
+void HAL_MPU_Disable(void) {
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0U;
+}
+
+/**
+ * @brief  Enable the MPU.
+ * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
+ *          NMI, FAULTMASK and privileged access to the default memory
+ *          This parameter can be one of the following values:
+ *            @arg MPU_HFNMI_PRIVDEF_NONE
+ *            @arg MPU_HARDFAULT_NMI
+ *            @arg MPU_PRIVILEGED_DEFAULT
+ *            @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control) {
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+
+/**
+ * @brief  Initializes and configures the Region and the memory to be protected.
+ * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+ *                the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) {
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != RESET) {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos)
+                | ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos)
+                | ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+  } else {
+    MPU->RBAR = 0x00U;
+    MPU->RASR = 0x00U;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ */
+uint32_t HAL_NVIC_GetPriorityGrouping(void) {
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+ * @brief  Gets the priority of an interrupt.
+ * @param  IRQn: External interrupt number.
+ *         This parameter can be an enumerator of IRQn_Type enumeration
+ *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @param   PriorityGroup: the priority grouping bits length.
+ *         This parameter can be one of the following values:
+ *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+ *                                      4 bits for subpriority
+ *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+ *                                      3 bits for subpriority
+ *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+ *                                      2 bits for subpriority
+ *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+ *                                      1 bits for subpriority
+ *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+ *                                      0 bits for subpriority
+ * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+ * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
+ * @retval None
+ */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) {
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+  /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+ * @brief  Sets Pending bit of an external interrupt.
+ * @param  IRQn External interrupt number
+ *         This parameter can be an enumerator of IRQn_Type enumeration
+ *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) {
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
+ *         and returns the pending bit for the specified interrupt).
+ * @param  IRQn External interrupt number.
+ *         This parameter can be an enumerator of IRQn_Type enumeration
+ *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval status: - 0  Interrupt status is not pending.
+ *                 - 1  Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) {
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief  Clears the pending bit of an external interrupt.
+ * @param  IRQn External interrupt number.
+ *         This parameter can be an enumerator of IRQn_Type enumeration
+ *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+ * @param IRQn External interrupt number
+ *         This parameter can be an enumerator of IRQn_Type enumeration
+ *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
+ * @retval status: - 0  Interrupt status is not pending.
+ *                 - 1  Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) {
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+ * @brief  Configures the SysTick clock source.
+ * @param  CLKSource: specifies the SysTick clock source.
+ *         This parameter can be one of the following values:
+ *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) {
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK) {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  } else {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+ * @brief  This function handles SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); }
+
+/**
+ * @brief  SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void) {
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c

@@ -0,0 +1,826 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA HAL module driver.
+  *         This file provides firmware functions to manage the following
+  *         functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Channel
+       (except for internal SRAM / FLASH memories: no initialization is
+       necessary). Please refer to the Reference manual for connection between peripherals
+       and DMA requests.
+
+   (#) For a given Channel, program the required configuration through the following parameters:
+       Channel request, Transfer Direction, Source and Destination data formats,
+       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
+       using HAL_DMA_Init() function.
+
+   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+       detection.
+
+   (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+              case a fixed Timeout can be configured by User depending from his application.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred.
+              In this case the DMA interrupt is configured
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e. a member of DMA handle structure).
+
+     *** DMA HAL driver macros list ***
+     =============================================
+      [..]
+       Below the list of most used macros in DMA HAL driver.
+
+       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief   Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Channel source
+    and destination addresses, incrementation and data sizes, transfer direction,
+    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Initialize the DMA according to the specified
+ *         parameters in the DMA_InitTypeDef and initialize the associated handle.
+ * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ *               the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) {
+  uint32_t tmp = 0U;
+
+  /* Check the DMA handle allocation */
+  if (hdma == NULL) {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+#if defined(DMA2)
+  /* calculation of the channel index */
+  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
+    /* DMA1 */
+    hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA1;
+  } else {
+    /* DMA2 */
+    hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA2;
+  }
+#else
+  /* DMA1 */
+  hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+  hdma->DmaBaseAddress = DMA1;
+#endif /* DMA2 */
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+  /* Get the CR register value */
+  tmp = hdma->Instance->CCR;
+
+  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+  tmp &= ((uint32_t) ~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR));
+
+  /* Prepare the DMA Channel configuration */
+  tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority;
+
+  /* Write to DMA Channel CR register */
+  hdma->Instance->CCR = tmp;
+
+  /* Initialise the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state*/
+  hdma->State = HAL_DMA_STATE_READY;
+  /* Allocate lock resource and initialize it */
+  hdma->Lock = HAL_UNLOCKED;
+
+  return HAL_OK;
+}
+
+/**
+ * @brief  DeInitialize the DMA peripheral.
+ * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+ *               the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) {
+  /* Check the DMA handle allocation */
+  if (hdma == NULL) {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Disable the selected DMA Channelx */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Reset DMA Channel control register */
+  hdma->Instance->CCR = 0U;
+
+  /* Reset DMA Channel Number of Data to Transfer register */
+  hdma->Instance->CNDTR = 0U;
+
+  /* Reset DMA Channel peripheral address register */
+  hdma->Instance->CPAR = 0U;
+
+  /* Reset DMA Channel memory address register */
+  hdma->Instance->CMAR = 0U;
+
+#if defined(DMA2)
+  /* calculation of the channel index */
+  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
+    /* DMA1 */
+    hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA1;
+  } else {
+    /* DMA2 */
+    hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
+    hdma->DmaBaseAddress = DMA2;
+  }
+#else
+  /* DMA1 */
+  hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+  hdma->DmaBaseAddress = DMA1;
+#endif /* DMA2 */
+
+  /* Clear all flags */
+  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
+
+  /* Clean all callbacks */
+  hdma->XferCpltCallback     = NULL;
+  hdma->XferHalfCpltCallback = NULL;
+  hdma->XferErrorCallback    = NULL;
+  hdma->XferAbortCallback    = NULL;
+
+  /* Reset the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Reset the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   Input and Output operation functions
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start DMA transfer with interrupt
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Start the DMA Transfer.
+ * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+ *               the configuration information for the specified DMA Channel.
+ * @param  SrcAddress: The source memory Buffer address
+ * @param  DstAddress: The destination memory Buffer address
+ * @param  DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if (HAL_DMA_STATE_READY == hdma->State) {
+    /* Change DMA peripheral state */
+    hdma->State     = HAL_DMA_STATE_BUSY;
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length & clear flags*/
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  } else {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    status = HAL_BUSY;
+  }
+  return status;
+}
+
+/**
+ * @brief  Start the DMA Transfer with interrupt enabled.
+ * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+ *               the configuration information for the specified DMA Channel.
+ * @param  SrcAddress: The source memory Buffer address
+ * @param  DstAddress: The destination memory Buffer address
+ * @param  DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if (HAL_DMA_STATE_READY == hdma->State) {
+    /* Change DMA peripheral state */
+    hdma->State     = HAL_DMA_STATE_BUSY;
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length & clear flags*/
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the transfer complete interrupt */
+    /* Enable the transfer Error interrupt */
+    if (NULL != hdma->XferHalfCpltCallback) {
+      /* Enable the Half transfer complete interrupt as well */
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+    } else {
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+    }
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  } else {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Remain BUSY */
+    status = HAL_BUSY;
+  }
+  return status;
+}
+
+/**
+ * @brief  Abort the DMA Transfer.
+ * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+ *               the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) {
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hdma->State != HAL_DMA_STATE_BUSY) {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  } else
+
+  {
+    /* Disable DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+    /* Disable the channel */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+  }
+  /* Change the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+ * @brief  Aborts the DMA Transfer in Interrupt mode.
+ * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+ *                 the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) {
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_DMA_STATE_BUSY != hdma->State) {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    status = HAL_ERROR;
+  } else {
+    /* Disable DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+    /* Disable the channel */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Clear all flags */
+    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Call User Abort callback */
+    if (hdma->XferAbortCallback != NULL) {
+      hdma->XferAbortCallback(hdma);
+    }
+  }
+  return status;
+}
+
+/**
+ * @brief  Polling for transfer complete.
+ * @param  hdma:    pointer to a DMA_HandleTypeDef structure that contains
+ *                  the configuration information for the specified DMA Channel.
+ * @param  CompleteLevel: Specifies the DMA level complete.
+ * @param  Timeout:       Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) {
+  uint32_t temp;
+  uint32_t tickstart = 0U;
+
+  if (HAL_DMA_STATE_BUSY != hdma->State) {
+    /* no transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    __HAL_UNLOCK(hdma);
+    return HAL_ERROR;
+  }
+
+  /* Polling mode not supported in circular mode */
+  if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+
+  /* Get the level transfer complete flag */
+  if (CompleteLevel == HAL_DMA_FULL_TRANSFER) {
+    /* Transfer Complete flag */
+    temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+  } else {
+    /* Half Transfer Complete flag */
+    temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+  }
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while (__HAL_DMA_GET_FLAG(hdma, temp) == RESET) {
+    if ((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) {
+      /* When a DMA transfer error occurs */
+      /* A hardware clear of its EN bits is performed */
+      /* Clear all flags */
+      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+
+      /* Update error code */
+      SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      return HAL_ERROR;
+    }
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY) {
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
+        /* Update error code */
+        SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  if (CompleteLevel == HAL_DMA_FULL_TRANSFER) {
+    /* Clear the transfer complete flag */
+    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+    /* The selected Channelx EN bit is cleared (DMA is disabled and
+    all transfers are complete) */
+    hdma->State = HAL_DMA_STATE_READY;
+  } else {
+    /* Clear the half transfer complete flag */
+    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+ * @brief  Handles DMA interrupt request.
+ * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+ *               the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) {
+  uint32_t flag_it   = hdma->DmaBaseAddress->ISR;
+  uint32_t source_it = hdma->Instance->CCR;
+
+  /* Half Transfer Complete Interrupt management ******************************/
+  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) {
+    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
+      /* Disable the half transfer interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+    }
+    /* Clear the half transfer complete flag */
+    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+    /* DMA peripheral state is not updated in Half Transfer */
+    /* but in Transfer Complete case */
+
+    if (hdma->XferHalfCpltCallback != NULL) {
+      /* Half transfer callback */
+      hdma->XferHalfCpltCallback(hdma);
+    }
+  }
+
+  /* Transfer Complete Interrupt management ***********************************/
+  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) {
+    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
+      /* Disable the transfer complete and error interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+    }
+    /* Clear the transfer complete flag */
+    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    if (hdma->XferCpltCallback != NULL) {
+      /* Transfer complete callback */
+      hdma->XferCpltCallback(hdma);
+    }
+  }
+
+  /* Transfer Error Interrupt management **************************************/
+  else if ((RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) {
+    /* When a DMA transfer error occurs */
+    /* A hardware clear of its EN bits is performed */
+    /* Disable ALL DMA IT */
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+    /* Clear all flags */
+    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+
+    /* Update error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    if (hdma->XferErrorCallback != NULL) {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+  return;
+}
+
+/**
+ * @brief Register callbacks
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ *              the configuration information for the specified DMA Channel.
+ * @param CallbackID: User Callback identifer
+ *                    a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @param pCallback: pointer to private callbacsk function which has pointer to
+ *                   a DMA_HandleTypeDef structure as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma)) {
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if (HAL_DMA_STATE_READY == hdma->State) {
+    switch (CallbackID) {
+    case HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = pCallback;
+      break;
+
+    case HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = pCallback;
+      break;
+
+    case HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = pCallback;
+      break;
+
+    case HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  } else {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+ * @brief UnRegister callbacks
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ *              the configuration information for the specified DMA Channel.
+ * @param CallbackID: User Callback identifer
+ *                    a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) {
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if (HAL_DMA_STATE_READY == hdma->State) {
+    switch (CallbackID) {
+    case HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      break;
+
+    case HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = NULL;
+      break;
+
+    case HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = NULL;
+      break;
+
+    case HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = NULL;
+      break;
+
+    case HAL_DMA_XFER_ALL_CB_ID:
+      hdma->XferCpltCallback     = NULL;
+      hdma->XferHalfCpltCallback = NULL;
+      hdma->XferErrorCallback    = NULL;
+      hdma->XferAbortCallback    = NULL;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  } else {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief    Peripheral State and Errors functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Return the DMA hande state.
+ * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+ *               the configuration information for the specified DMA Channel.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) {
+  /* Return DMA handle state */
+  return hdma->State;
+}
+
+/**
+ * @brief  Return the DMA error code.
+ * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+ *              the configuration information for the specified DMA Channel.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; }
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Sets the DMA Transfer parameter.
+ * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+ *                     the configuration information for the specified DMA Channel.
+ * @param  SrcAddress: The source memory Buffer address
+ * @param  DstAddress: The destination memory Buffer address
+ * @param  DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
+  /* Clear all flags */
+  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+
+  /* Configure DMA Channel data length */
+  hdma->Instance->CNDTR = DataLength;
+
+  /* Memory to Peripheral */
+  if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) {
+    /* Configure DMA Channel destination address */
+    hdma->Instance->CPAR = DstAddress;
+
+    /* Configure DMA Channel source address */
+    hdma->Instance->CMAR = SrcAddress;
+  }
+  /* Peripheral to Memory */
+  else {
+    /* Configure DMA Channel source address */
+    hdma->Instance->CPAR = SrcAddress;
+
+    /* Configure DMA Channel destination address */
+    hdma->Instance->CMAR = DstAddress;
+  }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c

@@ -0,0 +1,510 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt
+        (++) Event
+        (++) Both of them
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two different
+        interrupts pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected through multiplexer.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+ * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+ * of bounds [0,3] in following API :
+ * HAL_EXTI_SetConfigLine
+ * HAL_EXTI_GetConfigLine
+ * HAL_EXTI_ClearConfigLine
+ */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+  *  @brief    Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Set configuration of a dedicated Exti line.
+ * @param  hexti Exti handle.
+ * @param  pExtiConfig Pointer on EXTI configuration to be set.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) {
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL)) {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* Compute line mask */
+  linepos  = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) {
+      EXTI->RTSR |= maskline;
+    } else {
+      EXTI->RTSR &= ~maskline;
+    }
+
+    /* Configure falling trigger */
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) {
+      EXTI->FTSR |= maskline;
+    } else {
+      EXTI->FTSR &= ~maskline;
+    }
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = AFIO->EXTICR[linepos >> 2u];
+      regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      regval |= (pExtiConfig->GPIOSel << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      AFIO->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) {
+    EXTI->IMR |= maskline;
+  } else {
+    EXTI->IMR &= ~maskline;
+  }
+
+  /* Configure event mode : read current mode */
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) {
+    EXTI->EMR |= maskline;
+  } else {
+    EXTI->EMR &= ~maskline;
+  }
+
+  return HAL_OK;
+}
+
+/**
+ * @brief  Get configuration of a dedicated Exti line.
+ * @param  hexti Exti handle.
+ * @param  pExtiConfig Pointer on structure to store Exti configuration.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) {
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL)) {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configuration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* Compute line mask */
+  linepos  = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* 1] Get core mode : interrupt */
+
+  /* Check if selected line is enable */
+  if ((EXTI->IMR & maskline) != 0x00u) {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  } else {
+    pExtiConfig->Mode = EXTI_MODE_NONE;
+  }
+
+  /* Get event mode */
+  /* Check if selected line is enable */
+  if ((EXTI->EMR & maskline) != 0x00u) {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) {
+    /* Check if configuration of selected line is enable */
+    if ((EXTI->RTSR & maskline) != 0x00u) {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    } else {
+      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    }
+
+    /* Get falling configuration */
+    /* Check if configuration of selected line is enable */
+    if ((EXTI->FTSR & maskline) != 0x00u) {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval               = AFIO->EXTICR[linepos >> 2u];
+      pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
+    } else {
+      pExtiConfig->GPIOSel = 0x00u;
+    }
+  } else {
+    /* No Trigger selected */
+    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    pExtiConfig->GPIOSel = 0x00u;
+  }
+
+  return HAL_OK;
+}
+
+/**
+ * @brief  Clear whole configuration of a dedicated Exti line.
+ * @param  hexti Exti handle.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) {
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if (hexti == NULL) {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line mask */
+  linepos  = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* 1] Clear interrupt mode */
+  EXTI->IMR = (EXTI->IMR & ~maskline);
+
+  /* 2] Clear event mode */
+  EXTI->EMR = (EXTI->EMR & ~maskline);
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0x00u) {
+    EXTI->RTSR = (EXTI->RTSR & ~maskline);
+    EXTI->FTSR = (EXTI->FTSR & ~maskline);
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = AFIO->EXTICR[linepos >> 2u];
+      regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      AFIO->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+ * @brief  Register callback for a dedicated Exti line.
+ * @param  hexti Exti handle.
+ * @param  CallbackID User callback identifier.
+ *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+ * @param  pPendingCbfn function pointer to be stored as callback.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) {
+  HAL_StatusTypeDef status = HAL_OK;
+
+  switch (CallbackID) {
+  case HAL_EXTI_COMMON_CB_ID:
+    hexti->PendingCallback = pPendingCbfn;
+    break;
+
+  default:
+    status = HAL_ERROR;
+    break;
+  }
+
+  return status;
+}
+
+/**
+ * @brief  Store line number as handle private field.
+ * @param  hexti Exti handle.
+ * @param  ExtiLine Exti line number.
+ *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) {
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL) {
+    return HAL_ERROR;
+  } else {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+  *  @brief EXTI IO functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Handle EXTI interrupt request.
+ * @param  hexti Exti handle.
+ * @retval none.
+ */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) {
+  uint32_t regval;
+  uint32_t maskline;
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Get pending bit  */
+  regval = (EXTI->PR & maskline);
+  if (regval != 0x00u) {
+    /* Clear pending bit */
+    EXTI->PR = maskline;
+
+    /* Call callback */
+    if (hexti->PendingCallback != NULL) {
+      hexti->PendingCallback();
+    }
+  }
+}
+
+/**
+ * @brief  Get interrupt pending bit of a dedicated line.
+ * @param  hexti Exti handle.
+ * @param  Edge Specify which pending edge as to be checked.
+ *         This parameter can be one of the following values:
+ *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+ *         This parameter is kept for compatibility with other series.
+ * @retval 1 if interrupt is pending else 0.
+ */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) {
+  uint32_t regval;
+  uint32_t maskline;
+  uint32_t linepos;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* Compute line mask */
+  linepos  = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* return 1 if bit is set else 0 */
+  regval = ((EXTI->PR & maskline) >> linepos);
+  return regval;
+}
+
+/**
+ * @brief  Clear interrupt pending bit of a dedicated line.
+ * @param  hexti Exti handle.
+ * @param  Edge Specify which pending edge as to be clear.
+ *         This parameter can be one of the following values:
+ *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+ *         This parameter is kept for compatibility with other series.
+ * @retval None.
+ */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) {
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Clear Pending bit */
+  EXTI->PR = maskline;
+}
+
+/**
+ * @brief  Generate a software interrupt for a dedicated line.
+ * @param  hexti Exti handle.
+ * @retval None.
+ */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) {
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Generate Software interrupt */
+  EXTI->SWIER = maskline;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c

@@ -0,0 +1,864 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_flash.c
+  * @author  MCD Application Team
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+       to the Flash memory. It implements the erase and program Flash memory operations
+       and the read and write protection mechanisms.
+
+  [..] The Flash memory interface accelerates code execution with a system of instruction
+      prefetch.
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Prefetch on I-Code
+      (+) Option Bytes programming
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      This driver provides functions and macros to configure and program the FLASH
+      memory of all STM32F1xx devices.
+
+      (#) FLASH Memory I/O Programming functions: this group includes all needed
+          functions to erase and program the main memory:
+        (++) Lock and Unlock the FLASH interface
+        (++) Erase function: Erase page, erase all pages
+        (++) Program functions: half word, word and doubleword
+      (#) FLASH Option Bytes Programming functions: this group includes all needed
+          functions to manage the Option Bytes:
+        (++) Lock and Unlock the Option Bytes
+        (++) Set/Reset the write protection
+        (++) Set the Read protection Level
+        (++) Program the user Option Bytes
+        (++) Launch the Option Bytes loader
+        (++) Erase Option Bytes
+        (++) Program the data Option Bytes
+        (++) Get the Write protection.
+        (++) Get the user option bytes.
+
+      (#) Interrupts and flags management functions : this group
+          includes all needed functions to:
+        (++) Handle FLASH interrupts
+        (++) Wait for last FLASH operation according to its status
+        (++) Get error flag status
+
+  [..] In addition to these function, this driver includes a set of macros allowing
+       to handle the following operations:
+
+      (+) Set/Get the latency
+      (+) Enable/Disable the prefetch buffer
+      (+) Enable/Disable the half cycle access
+      (+) Enable/Disable the FLASH interrupts
+      (+) Monitor the FLASH flags status
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/** @defgroup FLASH FLASH
+ * @brief FLASH HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro ---------------------------- ---------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+static void FLASH_SetErrorCode(void);
+extern void FLASH_PageErase(uint32_t PageAddress);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+  *  @brief   Programming operation functions
+  *
+@verbatim
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Program halfword, word or double word at a specified address
+ * @note   The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ *         The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note   If an erase and a program operations are requested simultaneously,
+ *         the erase operation is performed before the program one.
+ *
+ * @note   FLASH should be previously erased before new programmation (only exception to this
+ *         is when 0x0000 is programmed)
+ *
+ * @param  TypeProgram:  Indicate the way to program at a specified address.
+ *                       This parameter can be a value of @ref FLASH_Type_Program
+ * @param  Address:      Specifies the address to be programmed.
+ * @param  Data:         Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) {
+  HAL_StatusTypeDef status       = HAL_ERROR;
+  uint8_t           index        = 0;
+  uint8_t           nbiterations = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+#if defined(FLASH_BANK2_END)
+  if (Address <= FLASH_BANK1_END) {
+#endif /* FLASH_BANK2_END */
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+#if defined(FLASH_BANK2_END)
+  } else {
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
+  }
+#endif /* FLASH_BANK2_END */
+
+  if (status == HAL_OK) {
+    if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) {
+      /* Program halfword (16-bit) at a specified address. */
+      nbiterations = 1U;
+    } else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) {
+      /* Program word (32-bit = 2*16-bit) at a specified address. */
+      nbiterations = 2U;
+    } else {
+      /* Program double word (64-bit = 4*16-bit) at a specified address. */
+      nbiterations = 4U;
+    }
+
+    for (index = 0U; index < nbiterations; index++) {
+      FLASH_Program_HalfWord((Address + (2U * index)), (uint16_t)(Data >> (16U * index)));
+
+#if defined(FLASH_BANK2_END)
+      if (Address <= FLASH_BANK1_END) {
+#endif /* FLASH_BANK2_END */
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+        /* If the program operation is completed, disable the PG Bit */
+        CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+#if defined(FLASH_BANK2_END)
+      } else {
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
+
+        /* If the program operation is completed, disable the PG Bit */
+        CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
+      }
+#endif /* FLASH_BANK2_END */
+      /* In case of error, stop programation procedure */
+      if (status != HAL_OK) {
+        break;
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+ * @brief  Program halfword, word or double word at a specified address  with interrupt enabled.
+ * @note   The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ *         The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note   If an erase and a program operations are requested simultaneously,
+ *         the erase operation is performed before the program one.
+ *
+ * @param  TypeProgram: Indicate the way to program at a specified address.
+ *                      This parameter can be a value of @ref FLASH_Type_Program
+ * @param  Address:     Specifies the address to be programmed.
+ * @param  Data:        Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) {
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+#if defined(FLASH_BANK2_END)
+  /* If procedure already ongoing, reject the next one */
+  if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
+    return HAL_ERROR;
+  }
+
+  if (Address <= FLASH_BANK1_END) {
+    /* Enable End of FLASH Operation and Error source interrupts */
+    __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1);
+
+  } else {
+    /* Enable End of FLASH Operation and Error source interrupts */
+    __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
+  }
+#else
+  /* Enable End of FLASH Operation and Error source interrupts */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+#endif /* FLASH_BANK2_END */
+
+  pFlash.Address = Address;
+  pFlash.Data    = Data;
+
+  if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) {
+    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
+    /* Program halfword (16-bit) at a specified address. */
+    pFlash.DataRemaining = 1U;
+  } else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) {
+    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
+    /* Program word (32-bit : 2*16-bit) at a specified address. */
+    pFlash.DataRemaining = 2U;
+  } else {
+    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
+    /* Program double word (64-bit : 4*16-bit) at a specified address. */
+    pFlash.DataRemaining = 4U;
+  }
+
+  /* Program halfword (16-bit) at a specified address. */
+  FLASH_Program_HalfWord(Address, (uint16_t)Data);
+
+  return status;
+}
+
+/**
+ * @brief This function handles FLASH interrupt request.
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void) {
+  uint32_t addresstmp = 0U;
+
+  /* Check FLASH operation error flags */
+#if defined(FLASH_BANK2_END)
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))
+#else
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+#endif /* FLASH_BANK2_END */
+  {
+    /* Return the faulty address */
+    addresstmp = pFlash.Address;
+    /* Reset address */
+    pFlash.Address = 0xFFFFFFFFU;
+
+    /* Save the Error code */
+    FLASH_SetErrorCode();
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(addresstmp);
+
+    /* Stop the procedure ongoing */
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+  }
+
+  /* Check FLASH End of Operation flag  */
+#if defined(FLASH_BANK2_END)
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1);
+#else
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+#endif /* FLASH_BANK2_END */
+
+    /* Process can continue only if no error detected */
+    if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
+      if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) {
+        /* Nb of pages to erased can be decreased */
+        pFlash.DataRemaining--;
+
+        /* Check if there are still pages to erase */
+        if (pFlash.DataRemaining != 0U) {
+          addresstmp = pFlash.Address;
+          /*Indicate user which sector has been erased */
+          HAL_FLASH_EndOfOperationCallback(addresstmp);
+
+          /*Increment sector number*/
+          addresstmp     = pFlash.Address + FLASH_PAGE_SIZE;
+          pFlash.Address = addresstmp;
+
+          /* If the erase operation is completed, disable the PER Bit */
+          CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+          FLASH_PageErase(addresstmp);
+        } else {
+          /* No more pages to Erase, user callback can be called. */
+          /* Reset Sector and stop Erase pages procedure */
+          pFlash.Address = addresstmp = 0xFFFFFFFFU;
+          pFlash.ProcedureOnGoing     = FLASH_PROC_NONE;
+          /* FLASH EOP interrupt user callback */
+          HAL_FLASH_EndOfOperationCallback(addresstmp);
+        }
+      } else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) {
+        /* Operation is completed, disable the MER Bit */
+        CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+
+#if defined(FLASH_BANK2_END)
+        /* Stop Mass Erase procedure if no pending mass erase on other bank */
+        if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) {
+#endif /* FLASH_BANK2_END */
+          /* MassErase ended. Return the selected bank */
+          /* FLASH EOP interrupt user callback */
+          HAL_FLASH_EndOfOperationCallback(0U);
+
+          /* Stop Mass Erase procedure*/
+          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        }
+#if defined(FLASH_BANK2_END)
+      }
+#endif /* FLASH_BANK2_END */
+      else {
+        /* Nb of 16-bit data to program can be decreased */
+        pFlash.DataRemaining--;
+
+        /* Check if there are still 16-bit data to program */
+        if (pFlash.DataRemaining != 0U) {
+          /* Increment address to 16-bit */
+          pFlash.Address += 2U;
+          addresstmp = pFlash.Address;
+
+          /* Shift to have next 16-bit data */
+          pFlash.Data = (pFlash.Data >> 16U);
+
+          /* Operation is completed, disable the PG Bit */
+          CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+          /*Program halfword (16-bit) at a specified address.*/
+          FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
+        } else {
+          /* Program ended. Return the selected address */
+          /* FLASH EOP interrupt user callback */
+          if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) {
+            HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+          } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) {
+            HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
+          } else {
+            HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
+          }
+
+          /* Reset Address and stop Program procedure */
+          pFlash.Address          = 0xFFFFFFFFU;
+          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        }
+      }
+    }
+  }
+
+#if defined(FLASH_BANK2_END)
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
+
+    /* Process can continue only if no error detected */
+    if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
+      if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) {
+        /* Nb of pages to erased can be decreased */
+        pFlash.DataRemaining--;
+
+        /* Check if there are still pages to erase*/
+        if (pFlash.DataRemaining != 0U) {
+          /* Indicate user which page address has been erased*/
+          HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+
+          /* Increment page address to next page */
+          pFlash.Address += FLASH_PAGE_SIZE;
+          addresstmp = pFlash.Address;
+
+          /* Operation is completed, disable the PER Bit */
+          CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
+
+          FLASH_PageErase(addresstmp);
+        } else {
+          /*No more pages to Erase*/
+
+          /*Reset Address and stop Erase pages procedure*/
+          pFlash.Address          = 0xFFFFFFFFU;
+          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+          /* FLASH EOP interrupt user callback */
+          HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+        }
+      } else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) {
+        /* Operation is completed, disable the MER Bit */
+        CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
+
+        if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) {
+          /* MassErase ended. Return the selected bank*/
+          /* FLASH EOP interrupt user callback */
+          HAL_FLASH_EndOfOperationCallback(0U);
+
+          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        }
+      } else {
+        /* Nb of 16-bit data to program can be decreased */
+        pFlash.DataRemaining--;
+
+        /* Check if there are still 16-bit data to program */
+        if (pFlash.DataRemaining != 0U) {
+          /* Increment address to 16-bit */
+          pFlash.Address += 2U;
+          addresstmp = pFlash.Address;
+
+          /* Shift to have next 16-bit data */
+          pFlash.Data = (pFlash.Data >> 16U);
+
+          /* Operation is completed, disable the PG Bit */
+          CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
+
+          /*Program halfword (16-bit) at a specified address.*/
+          FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
+        } else {
+          /*Program ended. Return the selected address*/
+          /* FLASH EOP interrupt user callback */
+          if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) {
+            HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+          } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) {
+            HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
+          } else {
+            HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
+          }
+
+          /* Reset Address and stop Program procedure*/
+          pFlash.Address          = 0xFFFFFFFFU;
+          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        }
+      }
+    }
+  }
+#endif
+
+  if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) {
+#if defined(FLASH_BANK2_END)
+    /* Operation is completed, disable the PG, PER and MER Bits for both bank */
+    CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+    CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER));
+
+    /* Disable End of FLASH Operation and Error source interrupts for both banks */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
+#else
+    /* Operation is completed, disable the PG, PER and MER Bits */
+    CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+
+    /* Disable End of FLASH Operation and Error source interrupts */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+#endif /* FLASH_BANK2_END */
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+ * @brief  FLASH end of operation interrupt callback
+ * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ *                 - Mass Erase: No return value expected
+ *                 - Pages Erase: Address of the page which has been erased
+ *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
+ *                 - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */
+}
+
+/**
+ * @brief  FLASH operation error interrupt callback
+ * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ *                 - Mass Erase: No return value expected
+ *                 - Pages Erase: Address of the page which returned an error
+ *                 - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   management functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Unlock the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void) {
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) {
+    /* Authorize the FLASH Registers access */
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+    /* Verify Flash is unlocked */
+    if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) {
+      status = HAL_ERROR;
+    }
+  }
+#if defined(FLASH_BANK2_END)
+  if (READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) {
+    /* Authorize the FLASH BANK2 Registers access */
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+
+    /* Verify Flash BANK2 is unlocked */
+    if (READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) {
+      status = HAL_ERROR;
+    }
+  }
+#endif /* FLASH_BANK2_END */
+
+  return status;
+}
+
+/**
+ * @brief  Locks the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void) {
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+#if defined(FLASH_BANK2_END)
+  /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
+  SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
+
+#endif /* FLASH_BANK2_END */
+  return HAL_OK;
+}
+
+/**
+ * @brief  Unlock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) {
+  if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) {
+    /* Authorizes the Option Byte register programming */
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+  } else {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+ * @brief  Lock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) {
+  /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
+
+  return HAL_OK;
+}
+
+/**
+ * @brief  Launch the option byte loading.
+ * @note   This function will reset automatically the MCU.
+ * @retval None
+ */
+void HAL_FLASH_OB_Launch(void) {
+  /* Initiates a system reset request to launch the option byte loading */
+  HAL_NVIC_SystemReset();
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
+ *  @brief    Peripheral errors functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time errors of  the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Get the specific FLASH error flag.
+ * @retval FLASH_ErrorCode The returned value can be:
+ *            @ref FLASH_Error_Codes
+ */
+uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; }
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Program a half-word (16-bit) at a specified address.
+ * @param  Address specify the address to be programmed.
+ * @param  Data    specify the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) {
+  /* Clean the error context */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined(FLASH_BANK2_END)
+  if (Address <= FLASH_BANK1_END) {
+#endif /* FLASH_BANK2_END */
+    /* Proceed to program the new data */
+    SET_BIT(FLASH->CR, FLASH_CR_PG);
+#if defined(FLASH_BANK2_END)
+  } else {
+    /* Proceed to program the new data */
+    SET_BIT(FLASH->CR2, FLASH_CR2_PG);
+  }
+#endif /* FLASH_BANK2_END */
+
+  /* Write data in the address */
+  *(__IO uint16_t *)Address = Data;
+}
+
+/**
+ * @brief  Wait for a FLASH operation to complete.
+ * @param  Timeout  maximum flash operation timeout
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) {
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+
+  uint32_t tickstart = HAL_GetTick();
+
+  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) {
+    if (Timeout != HAL_MAX_DELAY) {
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+  }
+
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+    return HAL_ERROR;
+  }
+
+  /* There is no error flag set */
+  return HAL_OK;
+}
+
+#if defined(FLASH_BANK2_END)
+/**
+ * @brief  Wait for a FLASH BANK2 operation to complete.
+ * @param  Timeout maximum flash operation timeout
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) {
+  /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+
+  uint32_t tickstart = HAL_GetTick();
+
+  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) {
+    if (Timeout != HAL_MAX_DELAY) {
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
+  }
+
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+    return HAL_ERROR;
+  }
+
+  /* If there is an error flag set */
+  return HAL_OK;
+}
+#endif /* FLASH_BANK2_END */
+
+/**
+ * @brief  Set the specific FLASH error flag.
+ * @retval None
+ */
+static void FLASH_SetErrorCode(void) {
+  uint32_t flags = 0U;
+
+#if defined(FLASH_BANK2_END)
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
+#else
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+#endif /* FLASH_BANK2_END */
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+#if defined(FLASH_BANK2_END)
+    flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
+#else
+    flags |= FLASH_FLAG_WRPERR;
+#endif /* FLASH_BANK2_END */
+  }
+#if defined(FLASH_BANK2_END)
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
+#else
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+#endif /* FLASH_BANK2_END */
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
+#if defined(FLASH_BANK2_END)
+    flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
+#else
+    flags |= FLASH_FLAG_PGERR;
+#endif /* FLASH_BANK2_END */
+  }
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+  }
+
+  /* Clear FLASH error pending bits */
+  __HAL_FLASH_CLEAR_FLAG(flags);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c

@@ -0,0 +1,544 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+  in several modes:
+  (+) Input mode
+  (+) Analog mode
+  (+) Output mode
+  (+) Alternate function mode
+  (+) External interrupt/event lines
+
+  [..]
+  During and just after reset, the alternate functions and external interrupt
+  lines are not active and the I/O ports are configured in input floating mode.
+
+  [..]
+  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+  activated or not.
+
+  [..]
+  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+  type and the IO speed can be selected depending on the VDD value.
+
+  [..]
+  All ports have external interrupt/event capability. To use external interrupt
+  lines, the port must be configured in input mode. All available GPIO pins are
+  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+  [..]
+  The external interrupt/event controller consists of up to 20 edge detectors in connectivity
+  line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
+  Each input line can be independently configured to select the type (event or interrupt) and
+  the corresponding trigger event (rising or falling or both). Each line can also masked
+  independently. A pending register maintains the status line of the interrupt requests
+
+                     ##### How to use this driver #####
+  ==============================================================================
+ [..]
+   (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
+
+   (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+       (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+       (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+            structure.
+       (++) In case of Output or alternate function mode selection: the speed is
+            configured through "Speed" member from GPIO_InitTypeDef structure
+       (++) Analog mode is required when a pin is to be used as ADC channel
+            or DAC output.
+       (++) In case of external interrupt/event selection the "Mode" member from
+            GPIO_InitTypeDef structure select the type (interrupt or event) and
+            the corresponding trigger event (rising or falling or both).
+
+   (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+       mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+       HAL_NVIC_EnableIRQ().
+
+   (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+   (#) To set/reset the level of a pin configured in output mode use
+       HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+   (#) During and just after reset, the alternate functions are not
+       active and the GPIO pins are configured in input floating mode (except JTAG
+       pins).
+
+   (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+       (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+       priority over the GPIO function.
+
+   (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+       general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
+       The HSE has priority over the GPIO function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+#define GPIO_MODE        0x00000003u
+#define EXTI_MODE        0x10000000u
+#define GPIO_MODE_IT     0x00010000u
+#define GPIO_MODE_EVT    0x00020000u
+#define RISING_EDGE      0x00100000u
+#define FALLING_EDGE     0x00200000u
+#define GPIO_OUTPUT_TYPE 0x00000010u
+
+#define GPIO_NUMBER 16u
+
+/* Definitions for bit manipulation of CRL and CRH register */
+#define GPIO_CR_MODE_INPUT         0x00000000u /*!< 00: Input mode (reset state)  */
+#define GPIO_CR_CNF_ANALOG         0x00000000u /*!< 00: Analog mode  */
+#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004u /*!< 01: Floating input (reset state)  */
+#define GPIO_CR_CNF_INPUT_PU_PD    0x00000008u /*!< 10: Input with pull-up / pull-down  */
+#define GPIO_CR_CNF_GP_OUTPUT_PP   0x00000000u /*!< 00: General purpose output push-pull  */
+#define GPIO_CR_CNF_GP_OUTPUT_OD   0x00000004u /*!< 01: General purpose output Open-drain  */
+#define GPIO_CR_CNF_AF_OUTPUT_PP   0x00000008u /*!< 10: Alternate function output Push-pull  */
+#define GPIO_CR_CNF_AF_OUTPUT_OD   0x0000000Cu /*!< 11: Alternate function output Open-drain  */
+
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]
+    This section provides functions allowing to initialize and de-initialize the GPIOs
+    to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ *         the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) {
+  uint32_t position = 0x00u;
+  uint32_t ioposition;
+  uint32_t iocurrent;
+  uint32_t temp;
+  uint32_t config = 0x00u;
+  __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
+  uint32_t       registeroffset; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00u) {
+    /* Get the IO position */
+    ioposition = (0x01uL << position);
+
+    /* Get the current IO position */
+    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+
+    if (iocurrent == ioposition) {
+      /* Check the Alternate function parameters */
+      assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+
+      /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
+      switch (GPIO_Init->Mode) {
+      /* If we are configuring the pin in OUTPUT push-pull mode */
+      case GPIO_MODE_OUTPUT_PP:
+        /* Check the GPIO speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
+        break;
+
+      /* If we are configuring the pin in OUTPUT open-drain mode */
+      case GPIO_MODE_OUTPUT_OD:
+        /* Check the GPIO speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
+        break;
+
+      /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
+      case GPIO_MODE_AF_PP:
+        /* Check the GPIO speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
+        break;
+
+      /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
+      case GPIO_MODE_AF_OD:
+        /* Check the GPIO speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
+        break;
+
+      /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
+      case GPIO_MODE_INPUT:
+      case GPIO_MODE_IT_RISING:
+      case GPIO_MODE_IT_FALLING:
+      case GPIO_MODE_IT_RISING_FALLING:
+      case GPIO_MODE_EVT_RISING:
+      case GPIO_MODE_EVT_FALLING:
+      case GPIO_MODE_EVT_RISING_FALLING:
+        /* Check the GPIO pull parameter */
+        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+        if (GPIO_Init->Pull == GPIO_NOPULL) {
+          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
+        } else if (GPIO_Init->Pull == GPIO_PULLUP) {
+          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
+
+          /* Set the corresponding ODR bit */
+          GPIOx->BSRR = ioposition;
+        } else /* GPIO_PULLDOWN */
+        {
+          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
+
+          /* Reset the corresponding ODR bit */
+          GPIOx->BRR = ioposition;
+        }
+        break;
+
+      /* If we are configuring the pin in INPUT analog mode */
+      case GPIO_MODE_ANALOG:
+        config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
+        break;
+
+      /* Parameters are checked with assert_param */
+      default:
+        break;
+      }
+
+      /* Check if the current bit belongs to first half or last half of the pin count number
+       in order to address CRH or CRL register*/
+      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
+      registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
+
+      /* Apply the new configuration of the pin to the register */
+      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) {
+        /* Enable AFIO Clock */
+        __HAL_RCC_AFIO_CLK_ENABLE();
+        temp = AFIO->EXTICR[position >> 2u];
+        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
+        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
+        AFIO->EXTICR[position >> 2u] = temp;
+
+        /* Configure the interrupt mask */
+        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) {
+          SET_BIT(EXTI->IMR, iocurrent);
+        } else {
+          CLEAR_BIT(EXTI->IMR, iocurrent);
+        }
+
+        /* Configure the event mask */
+        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) {
+          SET_BIT(EXTI->EMR, iocurrent);
+        } else {
+          CLEAR_BIT(EXTI->EMR, iocurrent);
+        }
+
+        /* Enable or disable the rising trigger */
+        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) {
+          SET_BIT(EXTI->RTSR, iocurrent);
+        } else {
+          CLEAR_BIT(EXTI->RTSR, iocurrent);
+        }
+
+        /* Enable or disable the falling trigger */
+        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) {
+          SET_BIT(EXTI->FTSR, iocurrent);
+        } else {
+          CLEAR_BIT(EXTI->FTSR, iocurrent);
+        }
+      }
+    }
+
+    position++;
+  }
+}
+
+/**
+ * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+ * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param  GPIO_Pin: specifies the port bit to be written.
+ *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) {
+  uint32_t position = 0x00u;
+  uint32_t iocurrent;
+  uint32_t tmp;
+  __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
+  uint32_t       registeroffset;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != 0u) {
+    /* Get current io position */
+    iocurrent = (GPIO_Pin) & (1uL << position);
+
+    if (iocurrent) {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+
+      tmp = AFIO->EXTICR[position >> 2u];
+      tmp &= 0x0FuL << (4u * (position & 0x03u));
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) {
+        tmp = 0x0FuL << (4u * (position & 0x03u));
+        CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp);
+
+        /* Clear EXTI line configuration */
+        CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
+        CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
+        CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
+      }
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Check if the current bit belongs to first half or last half of the pin count number
+       in order to address CRH or CRL register */
+      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
+      registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
+
+      /* CRL/CRH default value is floating input(0x04) shifted to correct position */
+      MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset);
+
+      /* ODR default value is 0 */
+      CLEAR_BIT(GPIOx->ODR, iocurrent);
+    }
+
+    position++;
+  }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ *  @brief   GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the GPIOs.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Reads the specified input port pin.
+ * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param  GPIO_Pin: specifies the port bit to read.
+ *         This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) {
+    bitstatus = GPIO_PIN_SET;
+  } else {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+ * @brief  Sets or clears the selected data port bit.
+ *
+ * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
+ *         accesses. In this way, there is no risk of an IRQ occurring between
+ *         the read and the modify access.
+ *
+ * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param  GPIO_Pin: specifies the port bit to be written.
+ *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @param  PinState: specifies the value to be written to the selected bit.
+ *          This parameter can be one of the GPIO_PinState enum values:
+ *            @arg GPIO_PIN_RESET: to clear the port pin
+ *            @arg GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) {
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET) {
+    GPIOx->BSRR = GPIO_Pin;
+  } else {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
+  }
+}
+
+/**
+ * @brief  Toggles the specified GPIO pin
+ * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param  GPIO_Pin: Specifies the pins to be toggled.
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
+  uint32_t odr;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* get current Ouput Data Register value */
+  odr = GPIOx->ODR;
+
+  /* Set selected pins that were at low level, and reset ones that were high */
+  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+}
+
+/**
+ * @brief  Locks GPIO Pins configuration registers.
+ * @note   The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
+ *         has been applied on a port bit, it is no longer possible to modify the value of the port bit until
+ *         the next reset.
+ * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
+ * @param  GPIO_Pin: specifies the port bit to be locked.
+ *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  SET_BIT(tmp, GPIO_Pin);
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK register. This read is mandatory to complete key lock sequence */
+  tmp = GPIOx->LCKR;
+
+  /* read again in order to confirm lock is active */
+  if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) {
+    return HAL_OK;
+  } else {
+    return HAL_ERROR;
+  }
+}
+
+/**
+ * @brief  This function handles EXTI interrupt request.
+ * @param  GPIO_Pin: Specifies the pins connected EXTI line
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) {
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+}
+
+/**
+ * @brief  EXTI line detection callbacks.
+ * @param  GPIO_Pin: Specifies the pins connected EXTI line
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c

@@ -0,0 +1,120 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_gpio_ex.c
+  * @author  MCD Application Team
+  * @brief   GPIO Extension HAL module driver.
+  *         This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral extension features #####
+  ==============================================================================
+  [..] GPIO module on STM32F1 family, manage also the AFIO register:
+       (+) Possibility to use the EVENTOUT Cortex feature
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to use EVENTOUT Cortex feature
+    (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
+    (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
+    (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
+ *  @brief    Extended features functions
+ *
+@verbatim
+  ==============================================================================
+                 ##### Extended features functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+    (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
+    (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
+    (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
+ * @param  GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
+ *   This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
+ * @param  GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
+ *   This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
+ * @retval None
+ */
+void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) {
+  /* Verify the parameters */
+  assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
+  assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
+
+  /* Apply the new configuration */
+  MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource));
+}
+
+/**
+ * @brief  Enables the Event Output.
+ * @retval None
+ */
+void HAL_GPIOEx_EnableEventout(void) { SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); }
+
+/**
+ * @brief  Disables the Event Output.
+ * @retval None
+ */
+void HAL_GPIOEx_DisableEventout(void) { CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); }
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c

@@ -0,0 +1,251 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_iwdg.c
+  * @author  MCD Application Team
+  * @brief   IWDG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Independent Watchdog (IWDG) peripheral:
+  *           + Initialization and Start functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### IWDG Generic features #####
+  ==============================================================================
+  [..]
+    (+) The IWDG can be started by either software or hardware (configurable
+        through option byte).
+
+    (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
+        active even if the main clock fails.
+
+    (+) Once the IWDG is started, the LSI is forced ON and both cannot be
+        disabled. The counter starts counting down from the reset value (0xFFF).
+        When it reaches the end of count value (0x000) a reset signal is
+        generated (IWDG reset).
+
+    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+        the IWDG_RLR value is reloaded into the counter and the watchdog reset
+        is prevented.
+
+    (+) The IWDG is implemented in the VDD voltage domain that is still functional
+        in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
+        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+        reset occurs.
+
+    (+) Debug mode: When the microcontroller enters debug mode (core halted),
+        the IWDG counter either continues to work normally or stops, depending
+        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
+
+    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+         The IWDG timeout may vary due to LSI clock frequency dispersion.
+         STM32F1xx devices provide the capability to measure the LSI clock
+         frequency (LSI clock is internally connected to TIM5 CH4 input capture).
+         The measured value can be used to have an IWDG timeout with an
+         acceptable accuracy.
+
+    [..] Default timeout value (necessary for IWDG_SR status register update):
+         Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+         This frequency being subject to variations as mentioned above, the
+         default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
+         below) may become too short or too long.
+         In such cases, this default timeout value can be tuned by redefining
+         the constant LSI_VALUE at user-application level (based, for instance,
+         on the measured LSI clock frequency as explained above).
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Use IWDG using HAL_IWDG_Init() function to :
+      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+           clock is forced ON and IWDG counter starts counting down.
+      (++) Enable write access to configuration registers:
+          IWDG_PR and IWDG_RLR.
+      (++) Configure the IWDG prescaler and counter reload value. This reload
+           value will be loaded in the IWDG counter each time the watchdog is
+           reloaded, then the IWDG will start counting down from this value.
+      (++) Wait for status flags to be reset.
+
+    (#) Then the application program must refresh the IWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_IWDG_Refresh() function.
+
+     *** IWDG HAL driver macros list ***
+     ====================================
+     [..]
+       Below the list of most used macros in IWDG HAL driver:
+      (+) __HAL_IWDG_START: Enable the IWDG peripheral
+      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+          the reload register
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
+ * @brief IWDG HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+ * @{
+ */
+/* Status register needs up to 5 LSI clock periods divided by the clock
+   prescaler to be updated. The number of LSI clock periods is upper-rounded to
+   6 for the timeout value calculation.
+   The timeout value is also calculated using the highest prescaler (256) and
+   the LSI_VALUE constant. The value of this constant can be changed by the user
+   to take into account possible LSI clock period variations.
+   The timeout value is multiplied by 1000 to be converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+  *  @brief    Initialization and Start functions.
+  *
+@verbatim
+ ===============================================================================
+          ##### Initialization and Start functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Initialize the IWDG according to the specified parameters in the
+          IWDG_InitTypeDef of associated handle.
+      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+          is reloaded in order to exit function with correct time base.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Initialize the IWDG according to the specified parameters in the
+ *         IWDG_InitTypeDef and start watchdog. Before exiting function,
+ *         watchdog is refreshed in order to have correct time base.
+ * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+ *                the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) {
+  uint32_t tickstart;
+
+  /* Check the IWDG handle allocation */
+  if (hiwdg == NULL) {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+
+  /* Enable IWDG. LSI is turned on automatically */
+  __HAL_IWDG_START(hiwdg);
+
+  /* Enable write access to IWDG_PR and IWDG_RLR registers by writing
+  0x5555 in KR */
+  IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+  /* Write to IWDG registers the Prescaler & Reload values to work with */
+  hiwdg->Instance->PR  = hiwdg->Init.Prescaler;
+  hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+  /* Check pending flag, if previous update not done, return timeout */
+  tickstart = HAL_GetTick();
+
+  /* Wait for register to be updated */
+  while (hiwdg->Instance->SR != 0x00u) {
+    if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Reload IWDG counter with value defined in the reload register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+  *  @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Refresh the IWDG.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Refresh the IWDG.
+ * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+ *                the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) {
+  /* Reload IWDG counter with value defined in the reload register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c

@@ -0,0 +1,584 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_pwr.c
+ * @author  MCD Application Team
+ * @brief   PWR HAL module driver.
+ *
+ *          This file provides firmware functions to manage the following
+ *          functionalities of the Power Controller (PWR) peripheral:
+ *           + Initialization/de-initialization functions
+ *           + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWR PWR
+ * @brief    PWR HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Constants PWR Private Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+ * @{
+ */
+#define PVD_MODE_IT      0x00010000U
+#define PVD_MODE_EVT     0x00020000U
+#define PVD_RISING_EDGE  0x00000001U
+#define PVD_FALLING_EDGE 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup PWR_register_alias_address PWR Register alias address
+ * @{
+ */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET        (PWR_BASE - PERIPH_BASE)
+#define PWR_CR_OFFSET     0x00U
+#define PWR_CSR_OFFSET    0x04U
+#define PWR_CR_OFFSET_BB  (PWR_OFFSET + PWR_CR_OFFSET)
+#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_CR_register_alias PWR CR Register alias address
+ * @{
+ */
+/* --- CR Register ---*/
+/* Alias word address of LPSDSR bit */
+#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
+#define CR_LPSDSR_BB      ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))
+
+/* Alias word address of DBP bit */
+#define DBP_BIT_NUMBER PWR_CR_DBP_Pos
+#define CR_DBP_BB      ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
+#define CR_PVDE_BB      ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
+ * @{
+ */
+
+/* --- CSR Register ---*/
+/* Alias word address of EWUP1 bit */
+#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup PWR_Private_Functions PWR Private Functions
+ * brief   WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
+ * @{
+ */
+static void PWR_OverloadWfe(void);
+
+/* Private functions ---------------------------------------------------------*/
+__NOINLINE
+static void PWR_OverloadWfe(void) {
+  __asm volatile("wfe");
+  __asm volatile("nop");
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief   Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      After reset, the backup domain (RTC registers, RTC backup data
+      registers) is protected against possible unwanted
+      write accesses.
+      To enable access to the RTC Domain and RTC registers, proceed as follows:
+        (+) Enable the Power Controller (PWR) APB1 interface clock using the
+            __HAL_RCC_PWR_CLK_ENABLE() macro.
+        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+ * @retval None
+ */
+void HAL_PWR_DeInit(void) {
+  __HAL_RCC_PWR_FORCE_RESET();
+  __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+ * @brief  Enables access to the backup domain (RTC registers, RTC
+ *         backup data registers ).
+ * @note   If the HSE divided by 128 is used as the RTC clock, the
+ *         Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_EnableBkUpAccess(void) {
+  /* Enable access to RTC and backup registers */
+  *(__IO uint32_t *)CR_DBP_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief  Disables access to the backup domain (RTC registers, RTC
+ *         backup data registers).
+ * @note   If the HSE divided by 128 is used as the RTC clock, the
+ *         Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_DisableBkUpAccess(void) {
+  /* Disable access to RTC and backup registers */
+  *(__IO uint32_t *)CR_DBP_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+  * @brief    Low Power modes configuration functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Peripheral Control functions #####
+ ===============================================================================
+
+    *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a
+          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+
+      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
+          than the PVD threshold. This event is internally connected to the EXTI
+          line16 and can generate an interrupt if enabled. This is done through
+          __HAL_PVD_EXTI_ENABLE_IT() macro.
+      (+) The PVD is stopped in Standby mode.
+
+    *** WakeUp pin configuration ***
+    ================================
+    [..]
+      (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
+          forced in input pull-down configuration and is active on rising edges.
+      (+) There is one WakeUp pin:
+          WakeUp Pin 1 on PA.00.
+
+    [..]
+
+    *** Low Power modes configuration ***
+    =====================================
+     [..]
+      The device features 3 low-power modes:
+      (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
+                      NVIC, SysTick, etc. are kept running
+      (+) Stop mode: All clocks are stopped
+      (+) Standby mode: 1.8V domain powered off
+
+
+   *** Sleep mode ***
+   ==================
+    [..]
+      (+) Entry:
+          The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
+              functions with
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+
+      (+) Exit:
+        (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
+             controller (NVIC) can wake up the device from Sleep mode.
+        (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
+           (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
+           (+++) Any EXTI Line (Internal or External) configured in Event mode
+
+   *** Stop mode ***
+   =================
+    [..]
+      The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
+      clock gating. The voltage regulator can be configured either in normal or low-power mode.
+      In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
+      oscillators are disabled. SRAM and register contents are preserved.
+      In Stop mode, all I/O pins keep the same state as in Run mode.
+
+      (+) Entry:
+           The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
+             function with:
+          (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
+          (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
+          (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
+          (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
+      (+) Exit:
+          (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
+          (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
+
+   *** Standby mode ***
+   ====================
+     [..]
+      The Standby mode allows to achieve the lowest power consumption. It is based on the
+      Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
+      consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
+      switched off. SRAM and register contents are lost except for registers in the Backup domain
+      and Standby circuitry
+
+      (+) Entry:
+        (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+      (+) Exit:
+        (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
+             NRSTpin, IWDG Reset
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+       =============================================
+       [..]
+
+       (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
+           without depending on an external interrupt (Auto-wakeup mode).
+
+       (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
+
+           (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
+                configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+   *** PWR Workarounds linked to Silicon Limitation ***
+       ====================================================
+       [..]
+       Below the list of all silicon limitations known on STM32F1xx prouct.
+
+       (#)Workarounds Implemented inside PWR HAL Driver
+          (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param  sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+ *         information for the PVD.
+ * @note   Refer to the electrical characteristics of your device datasheet for
+ *         more details about the voltage threshold corresponding to each
+ *         detection level.
+ * @retval None
+ */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) {
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+  /* Set PLS[7:5] bits according to PVDLevel value */
+  MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
+
+  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+
+  /* Configure interrupt mode */
+  if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT();
+  }
+
+  /* Configure event mode */
+  if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+  }
+
+  /* Configure the edge */
+  if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+  }
+
+  if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+  }
+}
+
+/**
+ * @brief  Enables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_EnablePVD(void) {
+  /* Enable the power voltage detector */
+  *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief  Disables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_DisablePVD(void) {
+  /* Disable the power voltage detector */
+  *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Enables the WakeUp PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
+ *        This parameter can be one of the following values:
+ *           @arg PWR_WAKEUP_PIN1
+ * @retval None
+ */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) {
+  /* Check the parameter */
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+  /* Enable the EWUPx pin */
+  *(__IO uint32_t *)CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the WakeUp PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+ *        This parameter can be one of the following values:
+ *           @arg PWR_WAKEUP_PIN1
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) {
+  /* Check the parameter */
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+  /* Disable the EWUPx pin */
+  *(__IO uint32_t *)CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Enters Sleep mode.
+ * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
+ * @param Regulator: Regulator state as no effect in SLEEP mode -  allows to support portability from legacy software
+ * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
+ *           When WFI entry is used, tick interrupt have to be disabled if not desired as
+ *           the interrupt wake up source.
+ *           This parameter can be one of the following values:
+ *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) {
+  /* Check the parameters */
+  /* No check on Regulator because parameter not used in SLEEP mode */
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Regulator);
+
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if (SLEEPEntry == PWR_SLEEPENTRY_WFI) {
+    /* Request Wait For Interrupt */
+    __WFI();
+  } else {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+}
+
+/**
+ * @brief Enters Stop mode.
+ * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
+ * @note  When exiting Stop mode by using an interrupt or a wakeup event,
+ *        HSI RC oscillator is selected as system clock.
+ * @note  When the voltage regulator operates in low power mode, an additional
+ *         startup delay is incurred when waking up from Stop mode.
+ *         By keeping the internal regulator ON during Stop mode, the consumption
+ *         is higher although the startup time is reduced.
+ * @param Regulator: Specifies the regulator state in Stop mode.
+ *          This parameter can be one of the following values:
+ *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
+ *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
+ * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
+ *          This parameter can be one of the following values:
+ *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
+ *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) {
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+  /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
+  CLEAR_BIT(PWR->CR, PWR_CR_PDDS);
+
+  /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
+  MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select Stop mode entry --------------------------------------------------*/
+  if (STOPEntry == PWR_STOPENTRY_WFI) {
+    /* Request Wait For Interrupt */
+    __WFI();
+  } else {
+    /* Request Wait For Event */
+    __SEV();
+    PWR_OverloadWfe(); /* WFE redefine locally */
+    PWR_OverloadWfe(); /* WFE redefine locally */
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Enters Standby mode.
+ * @note  In Standby mode, all I/O pins are high impedance except for:
+ *          - Reset pad (still available)
+ *          - TAMPER pin if configured for tamper or calibration out.
+ *          - WKUP pin (PA0) if enabled.
+ * @retval None
+ */
+void HAL_PWR_EnterSTANDBYMode(void) {
+  /* Select Standby mode */
+  SET_BIT(PWR->CR, PWR_CR_PDDS);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* This option is used to ensure that store operations are completed */
+#if defined(__CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ *       re-enters SLEEP mode when an interruption handling is over.
+ *       Setting this bit is useful when the processor is expected to run only on
+ *       interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void) {
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ *       re-enters SLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void) {
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enables CORTEX M3 SEVONPEND bit.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
+ *       WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void) {
+  /* Set SEVONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Disables CORTEX M3 SEVONPEND bit.
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+ *       WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void) {
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief  This function handles the PWR PVD interrupt request.
+ * @note   This API should be called under the PVD_IRQHandler().
+ * @retval None
+ */
+void HAL_PWR_PVD_IRQHandler(void) {
+  /* Check PWR exti flag */
+  if (__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) {
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback();
+
+    /* Clear PWR Exti pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+  }
+}
+
+/**
+ * @brief  PWR PVD interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWR_PVDCallback(void) {
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PWR_PVDCallback could be implemented in the user file
+   */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c

@@ -0,0 +1,757 @@
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_rcc_ex.c
+ * @author  MCD Application Team
+ * @brief   Extended RCC HAL module driver.
+ *          This file provides firmware functions to manage the following
+ *          functionalities RCC extension peripheral:
+ *           + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/** @defgroup RCCEx RCCEx
+ * @brief RCC Extension HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
+  *  @brief  Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) are set to their reset values.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
+ *         RCC_PeriphCLKInitTypeDef.
+ * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ *         contains the configuration information for the Extended Peripherals clocks(RTC clock).
+ *
+ * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ *         the RTC clock source; in this case the Backup domain will be reset in
+ *         order to modify the RTC Clock source, as consequence RTC registers (including
+ *         the backup registers) are set to their reset values.
+ *
+ * @note   In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
+ *         one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
+ *         manually disable it.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) {
+  uint32_t tickstart = 0U, temp_reg = 0U;
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  uint32_t pllactive = 0U;
+#endif /* STM32F105xC || STM32F107xC */
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*------------------------------- RTC/LCD Configuration ------------------------*/
+  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) {
+    /* check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    FlagStatus pwrclkchanged = RESET;
+
+    /* As soon as function is called to change RTC clock source, activation of the
+       power domain is done. */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if (__HAL_RCC_PWR_IS_CLK_DISABLED()) {
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+
+    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR, PWR_CR_DBP);
+
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+
+      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) {
+        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = temp_reg;
+
+      /* Wait for LSERDY if LSE was enabled */
+      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) {
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) {
+          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+
+    /* Require to disable power clock if necessary */
+    if (pwrclkchanged == SET) {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
+  }
+
+  /*------------------------------ ADC clock Configuration ------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) {
+    /* Check the parameters */
+    assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
+
+    /* Configure the ADC clock source */
+    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+  }
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  /*------------------------------ I2S2 Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
+
+    /* Configure the I2S2 clock source */
+    __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
+  }
+
+  /*------------------------------ I2S3 Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
+
+    /* Configure the I2S3 clock source */
+    __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
+  }
+
+  /*------------------------------ PLL I2S Configuration ----------------------*/
+  /* Check that PLLI2S need to be enabled */
+  if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) {
+    /* Update flag to indicate that PLL I2S should be active */
+    pllactive = 1;
+  }
+
+  /* Check if PLL I2S need to be enabled */
+  if (pllactive == 1) {
+    /* Enable PLL I2S only if not active */
+    if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) {
+      /* Check the parameters */
+      assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
+      assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
+
+      /* Prediv2 can be written only when the PLL2 is disabled. */
+      /* Return an error only if new value is different from the programmed value */
+      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) {
+        return HAL_ERROR;
+      }
+
+      /* Configure the HSE prediv2 factor --------------------------------*/
+      __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
+
+      /* Configure the main PLLI2S multiplication factors. */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
+
+      /* Enable the main PLLI2S. */
+      __HAL_RCC_PLLI2S_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till PLLI2S is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) {
+        if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
+          return HAL_TIMEOUT;
+        }
+      }
+    } else {
+      /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
+      if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) {
+        return HAL_ERROR;
+      }
+    }
+  }
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+  /*------------------------------ USB clock Configuration ------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) {
+    /* Check the parameters */
+    assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
+
+    /* Configure the USB clock source */
+    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+  }
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+
+  return HAL_OK;
+}
+
+/**
+ * @brief  Get the PeriphClkInit according to the internal
+ * RCC configuration registers.
+ * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ *         returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) {
+  uint32_t srcclk = 0U;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
+
+  /* Get the RTC configuration -----------------------------------------------*/
+  srcclk = __HAL_RCC_GET_RTC_SOURCE();
+  /* Source clock is LSE or LSI*/
+  PeriphClkInit->RTCClockSelection = srcclk;
+
+  /* Get the ADC clock configuration -----------------------------------------*/
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
+  PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  /* Get the I2S2 clock configuration -----------------------------------------*/
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
+  PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
+
+  /* Get the I2S3 clock configuration -----------------------------------------*/
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
+  PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
+
+#endif /* STM32F105xC || STM32F107xC */
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+  /* Get the I2S2 clock configuration -----------------------------------------*/
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
+  PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
+
+  /* Get the I2S3 clock configuration -----------------------------------------*/
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
+  PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
+
+#endif /* STM32F103xE || STM32F103xG */
+
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+  /* Get the USB clock configuration -----------------------------------------*/
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
+  PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+}
+
+/**
+  * @brief  Returns the peripheral clock frequency
+  * @note   Returns 0 if peripheral clock is unknown
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
+  @if STM32F103xE
+  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  @endif
+  @if STM32F103xG
+  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+  @endif
+  @if STM32F105xC
+  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
+  @endif
+  @if STM32F107xC
+  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
+  @endif
+  @if STM32F102xx
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
+  @endif
+  @if STM32F103xx
+  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
+  @endif
+  * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) {
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
+  const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+
+  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
+  uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
+#endif /* STM32F105xC || STM32F107xC */
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
+  const uint8_t aPredivFactorTable[2]  = {1, 2};
+
+  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+  uint32_t temp_reg = 0U, frequency = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+  switch (PeriphClk) {
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+  case RCC_PERIPHCLK_USB: {
+    /* Get RCC configuration ------------------------------------------------------*/
+    temp_reg = RCC->CFGR;
+
+    /* Check if PLL is enabled */
+    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) {
+      pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
+      if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) {
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE)
+        prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
+#else
+        prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
+#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+        if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) {
+          /* PLL2 selected as Prediv1 source */
+          /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
+          prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
+          pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
+          pllclk  = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
+        } else {
+          /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+          pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+        }
+
+        /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
+        /* In this case need to divide pllclk by 2 */
+        if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) {
+          pllclk = pllclk / 2;
+        }
+#else
+        if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) {
+          /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
+          pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
+        }
+#endif /* STM32F105xC || STM32F107xC */
+      } else {
+        /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
+      }
+
+      /* Calcul of the USB frequency*/
+#if defined(STM32F105xC) || defined(STM32F107xC)
+      /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
+      if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) {
+        /* Prescaler of 2 selected for USB */
+        frequency = pllclk;
+      } else {
+        /* Prescaler of 3 selected for USB */
+        frequency = (2 * pllclk) / 3;
+      }
+#else
+      /* USBCLK = PLLCLK / USB prescaler */
+      if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) {
+        /* No prescaler selected for USB */
+        frequency = pllclk;
+      } else {
+        /* Prescaler of 1.5 selected for USB */
+        frequency = (pllclk * 2) / 3;
+      }
+#endif
+    }
+    break;
+  }
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+  case RCC_PERIPHCLK_I2S2: {
+#if defined(STM32F103xE) || defined(STM32F103xG)
+    /* SYSCLK used as source clock for I2S2 */
+    frequency = HAL_RCC_GetSysClockFreq();
+#else
+    if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) {
+      /* SYSCLK used as source clock for I2S2 */
+      frequency = HAL_RCC_GetSysClockFreq();
+    } else {
+      /* Check if PLLI2S is enabled */
+      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) {
+        /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
+        prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
+        pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
+        frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
+      }
+    }
+#endif /* STM32F103xE || STM32F103xG */
+    break;
+  }
+  case RCC_PERIPHCLK_I2S3: {
+#if defined(STM32F103xE) || defined(STM32F103xG)
+    /* SYSCLK used as source clock for I2S3 */
+    frequency = HAL_RCC_GetSysClockFreq();
+#else
+    if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) {
+      /* SYSCLK used as source clock for I2S3 */
+      frequency = HAL_RCC_GetSysClockFreq();
+    } else {
+      /* Check if PLLI2S is enabled */
+      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) {
+        /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
+        prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
+        pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
+        frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
+      }
+    }
+#endif /* STM32F103xE || STM32F103xG */
+    break;
+  }
+#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+  case RCC_PERIPHCLK_RTC: {
+    /* Get RCC BDCR configuration ------------------------------------------------------*/
+    temp_reg = RCC->BDCR;
+
+    /* Check if LSE is ready if RTC clock selection is LSE */
+    if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) {
+      frequency = LSE_VALUE;
+    }
+    /* Check if LSI is ready if RTC clock selection is LSI */
+    else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) {
+      frequency = LSI_VALUE;
+    } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) {
+      frequency = HSE_VALUE / 128U;
+    }
+    /* Clock not enabled for RTC*/
+    else {
+      /* nothing to do: frequency already initialized to 0U */
+    }
+    break;
+  }
+  case RCC_PERIPHCLK_ADC: {
+    frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
+    break;
+  }
+  default: {
+    break;
+  }
+  }
+  return (frequency);
+}
+
+/**
+ * @}
+ */
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
+  *  @brief  PLLI2S Management functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Extended PLLI2S Management functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the PLLI2S
+    activation or deactivation
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Enable PLLI2S
+ * @param  PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
+ *         contains the configuration information for the PLLI2S
+ * @note   The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) {
+  uint32_t tickstart = 0U;
+
+  /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
+  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) {
+    /* Check the parameters */
+    assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
+    assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
+
+    /* Prediv2 can be written only when the PLL2 is disabled. */
+    /* Return an error only if new value is different from the programmed value */
+    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) {
+      return HAL_ERROR;
+    }
+
+    /* Disable the main PLLI2S. */
+    __HAL_RCC_PLLI2S_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLI2S is ready */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) {
+      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Configure the HSE prediv2 factor --------------------------------*/
+    __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
+
+    /* Configure the main PLLI2S multiplication factors. */
+    __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
+
+    /* Enable the main PLLI2S. */
+    __HAL_RCC_PLLI2S_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLI2S is ready */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) {
+      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
+        return HAL_TIMEOUT;
+      }
+    }
+  } else {
+    /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+ * @brief  Disable PLLI2S
+ * @note   PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) {
+  uint32_t tickstart = 0U;
+
+  /* Disable PLL I2S as not requested by I2S2 or I2S3*/
+  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) {
+    /* Disable the main PLLI2S. */
+    __HAL_RCC_PLLI2S_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLI2S is ready */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) {
+      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
+        return HAL_TIMEOUT;
+      }
+    }
+  } else {
+    /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
+  *  @brief  PLL2 Management functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Extended PLL2 Management functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the PLL2
+    activation or deactivation
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Enable PLL2
+ * @param  PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
+ *         contains the configuration information for the PLL2
+ * @note   The PLL2 configuration not modified if used indirectly as system clock.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) {
+  uint32_t tickstart = 0U;
+
+  /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+    clock (i.e. it is used as PLL clock entry that is used as system clock). */
+  if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+      && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) {
+    return HAL_ERROR;
+  } else {
+    /* Check the parameters */
+    assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
+    assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
+
+    /* Prediv2 can be written only when the PLLI2S is disabled. */
+    /* Return an error only if new value is different from the programmed value */
+    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) {
+      return HAL_ERROR;
+    }
+
+    /* Disable the main PLL2. */
+    __HAL_RCC_PLL2_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL2 is disabled */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) {
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Configure the HSE prediv2 factor --------------------------------*/
+    __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
+
+    /* Configure the main PLL2 multiplication factors. */
+    __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
+
+    /* Enable the main PLL2. */
+    __HAL_RCC_PLL2_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL2 is ready */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) {
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+ * @brief  Disable PLL2
+ * @note   PLL2 is not disabled if used indirectly as system clock.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) {
+  uint32_t tickstart = 0U;
+
+  /* This bit can not be cleared if the PLL2 clock is used indirectly as system
+    clock (i.e. it is used as PLL clock entry that is used as system clock). */
+  if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+      && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) {
+    return HAL_ERROR;
+  } else {
+    /* Disable the main PLL2. */
+    __HAL_RCC_PLL2_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL2 is disabled */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) {
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/flash.c

@@ -0,0 +1,44 @@
+/*
+ * flash.c
+ *
+ *  Created on: 29 May 2020
+ *      Author: Ralim
+ */
+
+#include "BSP.h"
+#include "BSP_Flash.h"
+#include "stm32f1xx_hal.h"
+#include "string.h"
+
+static uint16_t settings_page[512] __attribute__((section(".settings_page")));
+
+uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
+  FLASH_EraseInitTypeDef pEraseInit;
+  pEraseInit.TypeErase    = FLASH_TYPEERASE_PAGES;
+  pEraseInit.Banks        = FLASH_BANK_1;
+  pEraseInit.NbPages      = 1;
+  pEraseInit.PageAddress  = (uint32_t)settings_page;
+  uint32_t failingAddress = 0;
+  resetWatchdog();
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_BSY);
+  HAL_FLASH_Unlock();
+  HAL_Delay(1);
+  resetWatchdog();
+  HAL_FLASHEx_Erase(&pEraseInit, &failingAddress);
+  //^ Erase the page of flash (1024 bytes on this stm32)
+  // erased the chunk
+  // now we program it
+  uint16_t *data = (uint16_t *)buffer;
+  HAL_FLASH_Unlock();
+  for (uint16_t i = 0; i < (length / 2); i++) {
+    resetWatchdog();
+    HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, (uint32_t)&settings_page[i], data[i]);
+  }
+  HAL_FLASH_Lock();
+  return 1;
+}
+
+void flash_read_buffer(uint8_t *buffer, const uint16_t length) {
+  memset(buffer, 0, length);
+  memcpy(buffer, settings_page, length);
+}

source/Core/BSP/MHP30/fusb_user.cpp

@@ -0,0 +1,29 @@
+#include "Model_Config.h"
+#ifdef POW_PD
+#include "BSP.h"
+#include "I2C_Wrapper.hpp"
+#include "Pins.h"
+#include "Setup.h"
+#include "fusb302b.h"
+#include "fusb_user.h"
+
+bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) { return FRToSI2C::Mem_Read(FUSB302B_ADDR, addr, buf, size); }
+
+bool fusb_write_buf(uint8_t addr, uint8_t size, const uint8_t *buf) { return FRToSI2C::Mem_Write(FUSB302B_ADDR, addr, (uint8_t *)buf, size); }
+
+bool fusb302_detect() {
+  // Probe the I2C bus for its address
+  return FRToSI2C::probe(FUSB302B_ADDR);
+}
+
+void setupFUSBIRQ() {
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin   = INT_PD_Pin;
+  GPIO_InitStruct.Mode  = GPIO_MODE_IT_FALLING;
+  GPIO_InitStruct.Pull  = GPIO_PULLUP;
+  HAL_GPIO_Init(INT_PD_GPIO_Port, &GPIO_InitStruct);
+  HAL_NVIC_SetPriority(EXTI9_5_IRQn, 10, 0);
+  HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
+}
+#endif

source/Core/BSP/MHP30/logo.cpp

@@ -0,0 +1,25 @@
+/*
+ * logo.c
+ *
+ *  Created on: 29 May 2020
+ *      Author: Ralim
+ */
+
+#include "BSP.h"
+#include "OLED.hpp"
+
+static uint8_t logo_page[1024] __attribute__((section(".logo_page")));
+
+// Logo header signature.
+#define LOGO_HEADER_VALUE 0xF00DAA55
+
+uint8_t showBootLogoIfavailable() {
+  // Do not show logo data if signature is not found.
+  if (LOGO_HEADER_VALUE != *(reinterpret_cast<const uint32_t *>(logo_page))) {
+    return 0;
+  }
+
+  OLED::drawAreaSwapped(0, 0, 96, 16, (uint8_t *)(logo_page + 4));
+  OLED::refresh();
+  return 1;
+}

source/Core/BSP/MHP30/port.c

@@ -0,0 +1,659 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+ defined.  The value should also ensure backward compatibility.
+ FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+#define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+/* Ensure the SysTick is clocked at the same frequency as the core. */
+#define portNVIC_SYSTICK_CLK_BIT (1UL << 2UL)
+#else
+/* The way the SysTick is clocked is not modified in case it is not the same
+as the core. */
+#define portNVIC_SYSTICK_CLK_BIT (0)
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG          (*((volatile uint32_t *)0xe000e010))
+#define portNVIC_SYSTICK_LOAD_REG          (*((volatile uint32_t *)0xe000e014))
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG (*((volatile uint32_t *)0xe000e018))
+#define portNVIC_SYSPRI2_REG               (*((volatile uint32_t *)0xe000ed20))
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT        (1UL << 1UL)
+#define portNVIC_SYSTICK_ENABLE_BIT     (1UL << 0UL)
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT (1UL << 16UL)
+#define portNVIC_PENDSVCLEAR_BIT        (1UL << 27UL)
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT (1UL << 25UL)
+
+#define portNVIC_PENDSV_PRI  (((uint32_t)configKERNEL_INTERRUPT_PRIORITY) << 16UL)
+#define portNVIC_SYSTICK_PRI (((uint32_t)configKERNEL_INTERRUPT_PRIORITY) << 24UL)
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER (16)
+#define portNVIC_IP_REGISTERS_OFFSET_16 (0xE000E3F0)
+#define portAIRCR_REG                   (*((volatile uint32_t *)0xE000ED0C))
+#define portMAX_8_BIT_VALUE             ((uint8_t)0xff)
+#define portTOP_BIT_OF_BYTE             ((uint8_t)0x80)
+#define portMAX_PRIGROUP_BITS           ((uint8_t)7)
+#define portPRIORITY_GROUP_MASK         (0x07UL << 8UL)
+#define portPRIGROUP_SHIFT              (8UL)
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK (0xFFUL)
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR (0x01000000UL)
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER (0xffffffUL)
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ occurred while the SysTick counter is stopped during tickless idle
+ calculations. */
+#define portMISSED_COUNTS_FACTOR (45UL)
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK ((StackType_t)0xfffffffeUL)
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ prvTaskExitError() in case it messes up unwinding of the stack in the
+ debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+#define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt(void);
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler(void) __attribute__((naked));
+void xPortSysTickHandler(void);
+void vPortSVCHandler(void) __attribute__((naked));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask(void) __attribute__((naked));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError(void);
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if (configUSE_TICKLESS_IDLE == 1)
+static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if (configUSE_TICKLESS_IDLE == 1)
+static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if (configUSE_TICKLESS_IDLE == 1)
+static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if (configASSERT_DEFINED == 1)
+static uint8_t                       ucMaxSysCallPriority         = 0;
+static uint32_t                      ulMaxPRIGROUPValue           = 0;
+static const volatile uint8_t *const pcInterruptPriorityRegisters = (const volatile uint8_t *const)portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) {
+  /* Simulate the stack frame as it would be created by a context switch
+   interrupt. */
+  pxTopOfStack--;                   /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+  *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+  pxTopOfStack--;
+  *pxTopOfStack = ((StackType_t)pxCode) & portSTART_ADDRESS_MASK; /* PC */
+  pxTopOfStack--;
+  *pxTopOfStack = (StackType_t)portTASK_RETURN_ADDRESS; /* LR */
+  pxTopOfStack -= 5;                                    /* R12, R3, R2 and R1. */
+  *pxTopOfStack = (StackType_t)pvParameters;            /* R0 */
+  pxTopOfStack -= 8;                                    /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+  return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError(void) {
+  volatile uint32_t ulDummy = 0UL;
+
+  /* A function that implements a task must not exit or attempt to return to
+   its caller as there is nothing to return to.  If a task wants to exit it
+   should instead call vTaskDelete( NULL ).
+
+   Artificially force an assert() to be triggered if configASSERT() is
+   defined, then stop here so application writers can catch the error. */
+  configASSERT(uxCriticalNesting == ~0UL);
+  portDISABLE_INTERRUPTS();
+  while (ulDummy == 0) {
+    /* This file calls prvTaskExitError() after the scheduler has been
+     started to remove a compiler warning about the function being defined
+     but never called.  ulDummy is used purely to quieten other warnings
+     about code appearing after this function is called - making ulDummy
+     volatile makes the compiler think the function could return and
+     therefore not output an 'unreachable code' warning for code that appears
+     after it. */
+  }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler(void) {
+  __asm volatile("	ldr	r3, pxCurrentTCBConst2		\n"                 /* Restore the context. */
+                 "	ldr r1, [r3]					\n"         /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+                 "	ldr r0, [r1]					\n"         /* The first item in pxCurrentTCB is the task top of stack. */
+                 "	ldmia r0!, {r4-r11}				\n"         /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+                 "	msr psp, r0						\n" /* Restore the task stack pointer. */
+                 "	isb								\n"
+                 "	mov r0, #0 						\n"
+                 "	msr	basepri, r0					\n"
+                 "	orr r14, #0xd					\n"
+                 "	bx r14							\n"
+                 "									\n"
+                 "	.align 4						\n"
+                 "pxCurrentTCBConst2: .word pxCurrentTCB				\n");
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask(void) {
+  __asm volatile(" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+                 " ldr r0, [r0] 			\n"
+                 " ldr r0, [r0] 			\n"
+                 " msr msp, r0			\n"         /* Set the msp back to the start of the stack. */
+                 " cpsie i				\n" /* Globally enable interrupts. */
+                 " cpsie f				\n"
+                 " dsb					\n"
+                 " isb					\n"
+                 " svc 0					\n" /* System call to start first task. */
+                 " nop					\n");
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler(void) {
+  /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+   See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+  configASSERT(configMAX_SYSCALL_INTERRUPT_PRIORITY);
+
+#if (configASSERT_DEFINED == 1)
+  {
+    volatile uint32_t       ulOriginalPriority;
+    volatile uint8_t *const pucFirstUserPriorityRegister = (volatile uint8_t *const)(portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER);
+    volatile uint8_t        ucMaxPriorityValue;
+
+    /* Determine the maximum priority from which ISR safe FreeRTOS API
+     functions can be called.  ISR safe functions are those that end in
+     "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+     ensure interrupt entry is as fast and simple as possible.
+
+     Save the interrupt priority value that is about to be clobbered. */
+    ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+    /* Determine the number of priority bits available.  First write to all
+     possible bits. */
+    *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+    /* Read the value back to see how many bits stuck. */
+    ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+    /* Use the same mask on the maximum system call priority. */
+    ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+    /* Calculate the maximum acceptable priority group value for the number
+     of bits read back. */
+    ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+    while ((ucMaxPriorityValue & portTOP_BIT_OF_BYTE) == portTOP_BIT_OF_BYTE) {
+      ulMaxPRIGROUPValue--;
+      ucMaxPriorityValue <<= (uint8_t)0x01;
+    }
+
+#ifdef __NVIC_PRIO_BITS
+    {
+      /* Check the CMSIS configuration that defines the number of
+      priority bits matches the number of priority bits actually queried
+      from the hardware. */
+      configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == __NVIC_PRIO_BITS);
+    }
+#endif
+
+#ifdef configPRIO_BITS
+    {
+      /* Check the FreeRTOS configuration that defines the number of
+      priority bits matches the number of priority bits actually queried
+      from the hardware. */
+      configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == configPRIO_BITS);
+    }
+#endif
+
+    /* Shift the priority group value back to its position within the AIRCR
+     register. */
+    ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+    ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+    /* Restore the clobbered interrupt priority register to its original
+     value. */
+    *pucFirstUserPriorityRegister = ulOriginalPriority;
+  }
+#endif /* conifgASSERT_DEFINED */
+
+  /* Make PendSV and SysTick the lowest priority interrupts. */
+  portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+  portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+  /* Start the timer that generates the tick ISR.  Interrupts are disabled
+   here already. */
+  vPortSetupTimerInterrupt();
+
+  /* Initialise the critical nesting count ready for the first task. */
+  uxCriticalNesting = 0;
+
+  /* Start the first task. */
+  prvPortStartFirstTask();
+
+  /* Should never get here as the tasks will now be executing!  Call the task
+   exit error function to prevent compiler warnings about a static function
+   not being called in the case that the application writer overrides this
+   functionality by defining configTASK_RETURN_ADDRESS.  Call
+   vTaskSwitchContext() so link time optimisation does not remove the
+   symbol. */
+  vTaskSwitchContext();
+  prvTaskExitError();
+
+  /* Should not get here! */
+  return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler(void) {
+  /* Not implemented in ports where there is nothing to return to.
+   Artificially force an assert. */
+  configASSERT(uxCriticalNesting == 1000UL);
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical(void) {
+  portDISABLE_INTERRUPTS();
+  uxCriticalNesting++;
+
+  /* This is not the interrupt safe version of the enter critical function so
+   assert() if it is being called from an interrupt context.  Only API
+   functions that end in "FromISR" can be used in an interrupt.  Only assert if
+   the critical nesting count is 1 to protect against recursive calls if the
+   assert function also uses a critical section. */
+  if (uxCriticalNesting == 1) {
+    configASSERT((portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK) == 0);
+  }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical(void) {
+  configASSERT(uxCriticalNesting);
+  uxCriticalNesting--;
+  if (uxCriticalNesting == 0) {
+    portENABLE_INTERRUPTS();
+  }
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler(void) {
+  /* This is a naked function. */
+
+  __asm volatile("	mrs r0, psp							\n"
+                 "	isb									\n"
+                 "										\n"
+                 "	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+                 "	ldr	r2, [r3]						\n"
+                 "										\n"
+                 "	stmdb r0!, {r4-r11}					\n" /* Save the remaining registers. */
+                 "	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+                 "										\n"
+                 "	stmdb sp!, {r3, r14}				\n"
+                 "	mov r0, %0							\n"
+                 "	msr basepri, r0						\n"
+                 "	bl vTaskSwitchContext				\n"
+                 "	mov r0, #0							\n"
+                 "	msr basepri, r0						\n"
+                 "	ldmia sp!, {r3, r14}				\n"
+                 "										\n" /* Restore the context, including the critical nesting count. */
+                 "	ldr r1, [r3]						\n"
+                 "	ldr r0, [r1]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+                 "	ldmia r0!, {r4-r11}					\n" /* Pop the registers. */
+                 "	msr psp, r0							\n"
+                 "	isb									\n"
+                 "	bx r14								\n"
+                 "										\n"
+                 "	.align 4							\n"
+                 "pxCurrentTCBConst: .word pxCurrentTCB	\n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY));
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler(void) {
+  /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+   executes all interrupts must be unmasked.  There is therefore no need to
+   save and then restore the interrupt mask value as its value is already
+   known. */
+  portDISABLE_INTERRUPTS();
+  {
+    /* Increment the RTOS tick. */
+    if (xTaskIncrementTick() != pdFALSE) {
+      /* A context switch is required.  Context switching is performed in
+       the PendSV interrupt.  Pend the PendSV interrupt. */
+      portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+    }
+  }
+  portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if (configUSE_TICKLESS_IDLE == 1)
+
+__attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) {
+  uint32_t   ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+  TickType_t xModifiableIdleTime;
+
+  /* Make sure the SysTick reload value does not overflow the counter. */
+  if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks) {
+    xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+  }
+
+  /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+  is accounted for as best it can be, but using the tickless mode will
+  inevitably result in some tiny drift of the time maintained by the
+  kernel with respect to calendar time. */
+  portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+  /* Calculate the reload value required to wait xExpectedIdleTime
+  tick periods.  -1 is used because this code will execute part way
+  through one of the tick periods. */
+  ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + (ulTimerCountsForOneTick * (xExpectedIdleTime - 1UL));
+  if (ulReloadValue > ulStoppedTimerCompensation) {
+    ulReloadValue -= ulStoppedTimerCompensation;
+  }
+
+  /* Enter a critical section but don't use the taskENTER_CRITICAL()
+  method as that will mask interrupts that should exit sleep mode. */
+  __asm volatile("cpsid i" ::: "memory");
+  __asm volatile("dsb");
+  __asm volatile("isb");
+
+  /* If a context switch is pending or a task is waiting for the scheduler
+  to be unsuspended then abandon the low power entry. */
+  if (eTaskConfirmSleepModeStatus() == eAbortSleep) {
+    /* Restart from whatever is left in the count register to complete
+    this tick period. */
+    portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+    /* Restart SysTick. */
+    portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+    /* Reset the reload register to the value required for normal tick
+    periods. */
+    portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+    /* Re-enable interrupts - see comments above the cpsid instruction()
+    above. */
+    __asm volatile("cpsie i" ::: "memory");
+  } else {
+    /* Set the new reload value. */
+    portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+    /* Clear the SysTick count flag and set the count value back to
+    zero. */
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Restart SysTick. */
+    portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+    /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+    set its parameter to 0 to indicate that its implementation contains
+    its own wait for interrupt or wait for event instruction, and so wfi
+    should not be executed again.  However, the original expected idle
+    time variable must remain unmodified, so a copy is taken. */
+    xModifiableIdleTime = xExpectedIdleTime;
+    configPRE_SLEEP_PROCESSING(xModifiableIdleTime);
+    if (xModifiableIdleTime > 0) {
+      __asm volatile("dsb" ::: "memory");
+      __asm volatile("wfi");
+      __asm volatile("isb");
+    }
+    configPOST_SLEEP_PROCESSING(xExpectedIdleTime);
+
+    /* Re-enable interrupts to allow the interrupt that brought the MCU
+    out of sleep mode to execute immediately.  see comments above
+    __disable_interrupt() call above. */
+    __asm volatile("cpsie i" ::: "memory");
+    __asm volatile("dsb");
+    __asm volatile("isb");
+
+    /* Disable interrupts again because the clock is about to be stopped
+    and interrupts that execute while the clock is stopped will increase
+    any slippage between the time maintained by the RTOS and calendar
+    time. */
+    __asm volatile("cpsid i" ::: "memory");
+    __asm volatile("dsb");
+    __asm volatile("isb");
+
+    /* Disable the SysTick clock without reading the
+    portNVIC_SYSTICK_CTRL_REG register to ensure the
+    portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+    the time the SysTick is stopped for is accounted for as best it can
+    be, but using the tickless mode will inevitably result in some tiny
+    drift of the time maintained by the kernel with respect to calendar
+    time*/
+    portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT);
+
+    /* Determine if the SysTick clock has already counted to zero and
+    been set back to the current reload value (the reload back being
+    correct for the entire expected idle time) or if the SysTick is yet
+    to count to zero (in which case an interrupt other than the SysTick
+    must have brought the system out of sleep mode). */
+    if ((portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT) != 0) {
+      uint32_t ulCalculatedLoadValue;
+
+      /* The tick interrupt is already pending, and the SysTick count
+      reloaded with ulReloadValue.  Reset the
+      portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+      period. */
+      ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL) - (ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG);
+
+      /* Don't allow a tiny value, or values that have somehow
+      underflowed because the post sleep hook did something
+      that took too long. */
+      if ((ulCalculatedLoadValue < ulStoppedTimerCompensation) || (ulCalculatedLoadValue > ulTimerCountsForOneTick)) {
+        ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL);
+      }
+
+      portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+      /* As the pending tick will be processed as soon as this
+      function exits, the tick value maintained by the tick is stepped
+      forward by one less than the time spent waiting. */
+      ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+    } else {
+      /* Something other than the tick interrupt ended the sleep.
+      Work out how long the sleep lasted rounded to complete tick
+      periods (not the ulReload value which accounted for part
+      ticks). */
+      ulCompletedSysTickDecrements = (xExpectedIdleTime * ulTimerCountsForOneTick) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+      /* How many complete tick periods passed while the processor
+      was waiting? */
+      ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+      /* The reload value is set to whatever fraction of a single tick
+      period remains. */
+      portNVIC_SYSTICK_LOAD_REG = ((ulCompleteTickPeriods + 1UL) * ulTimerCountsForOneTick) - ulCompletedSysTickDecrements;
+    }
+
+    /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+    again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+    value. */
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+    portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+    vTaskStepTick(ulCompleteTickPeriods);
+    portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+    /* Exit with interrupts enabled. */
+    __asm volatile("cpsie i" ::: "memory");
+  }
+}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__((weak)) void vPortSetupTimerInterrupt(void) {
+  /* Calculate the constants required to configure the tick interrupt. */
+#if (configUSE_TICKLESS_IDLE == 1)
+  {
+    ulTimerCountsForOneTick         = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ);
+    xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+    ulStoppedTimerCompensation      = portMISSED_COUNTS_FACTOR / (configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ);
+  }
+#endif /* configUSE_TICKLESS_IDLE */
+
+  /* Stop and clear the SysTick. */
+  portNVIC_SYSTICK_CTRL_REG          = 0UL;
+  portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+  /* Configure SysTick to interrupt at the requested rate. */
+  portNVIC_SYSTICK_LOAD_REG = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ) - 1UL;
+  portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT);
+}
+/*-----------------------------------------------------------*/
+
+#if (configASSERT_DEFINED == 1)
+
+void vPortValidateInterruptPriority(void) {
+  uint32_t ulCurrentInterrupt;
+  uint8_t  ucCurrentPriority;
+
+  /* Obtain the number of the currently executing interrupt. */
+  __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory");
+
+  /* Is the interrupt number a user defined interrupt? */
+  if (ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER) {
+    /* Look up the interrupt's priority. */
+    ucCurrentPriority = pcInterruptPriorityRegisters[ulCurrentInterrupt];
+
+    /* The following assertion will fail if a service routine (ISR) for
+     an interrupt that has been assigned a priority above
+     configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+     function.  ISR safe FreeRTOS API functions must *only* be called
+     from interrupts that have been assigned a priority at or below
+     configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+     Numerically low interrupt priority numbers represent logically high
+     interrupt priorities, therefore the priority of the interrupt must
+     be set to a value equal to or numerically *higher* than
+     configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+     Interrupts that	use the FreeRTOS API must not be left at their
+     default priority of	zero as that is the highest possible priority,
+     which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+     and	therefore also guaranteed to be invalid.
+
+     FreeRTOS maintains separate thread and ISR API functions to ensure
+     interrupt entry is as fast and simple as possible.
+
+     The following links provide detailed information:
+     http://www.freertos.org/RTOS-Cortex-M3-M4.html
+     http://www.freertos.org/FAQHelp.html */
+    configASSERT(ucCurrentPriority >= ucMaxSysCallPriority);
+  }
+
+  /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+   that define each interrupt's priority to be split between bits that
+   define the interrupt's pre-emption priority bits and bits that define
+   the interrupt's sub-priority.  For simplicity all bits must be defined
+   to be pre-emption priority bits.  The following assertion will fail if
+   this is not the case (if some bits represent a sub-priority).
+
+   If the application only uses CMSIS libraries for interrupt
+   configuration then the correct setting can be achieved on all Cortex-M
+   devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+   scheduler.  Note however that some vendor specific peripheral libraries
+   assume a non-zero priority group setting, in which cases using a value
+   of zero will result in unpredictable behaviour. */
+  configASSERT((portAIRCR_REG & portPRIORITY_GROUP_MASK) <= ulMaxPRIGROUPValue);
+}
+
+#endif /* configASSERT_DEFINED */

source/Core/BSP/MHP30/portmacro.h

@@ -0,0 +1,230 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR       char
+#define portFLOAT      float
+#define portDOUBLE     double
+#define portLONG       long
+#define portSHORT      short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE  long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long           BaseType_t;
+typedef unsigned long  UBaseType_t;
+
+#if (configUSE_16_BIT_TICKS == 1)
+typedef uint16_t TickType_t;
+#define portMAX_DELAY (TickType_t)0xffff
+#else
+typedef uint32_t TickType_t;
+#define portMAX_DELAY           (TickType_t)0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH   (-1)
+#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
+#define portBYTE_ALIGNMENT 8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD()                                                            \
+  {                                                                            \
+    /* Set a PendSV to request a context switch. */                            \
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;                            \
+                                                                               \
+    /* Barriers are normally not required but do ensure the code is completely \
+    within the specified behaviour for the architecture. */                    \
+    __asm volatile("dsb" ::: "memory");                                        \
+    __asm volatile("isb");                                                     \
+  }
+
+#define portNVIC_INT_CTRL_REG  (*((volatile uint32_t *)0xe000ed04))
+#define portNVIC_PENDSVSET_BIT (1UL << 28UL)
+#define portEND_SWITCHING_ISR(xSwitchRequired) \
+  if (xSwitchRequired != pdFALSE)              \
+  portYIELD()
+#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical(void);
+extern void vPortExitCritical(void);
+#define portSET_INTERRUPT_MASK_FROM_ISR()    ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()             vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()              vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()                 vPortEnterCritical()
+#define portEXIT_CRITICAL()                  vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ not necessary for to use this port.  They are defined so the common demo files
+ (which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
+#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
+#define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime)
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+__attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros(uint32_t ulBitmap) {
+  uint8_t ucReturn;
+
+  __asm volatile("clz %0, %1" : "=r"(ucReturn) : "r"(ulBitmap) : "memory");
+  return ucReturn;
+}
+
+/* Check the configuration. */
+#if (configMAX_PRIORITIES > 32)
+#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+#endif
+
+/* Store/clear the ready priorities in a bit map. */
+#define portRECORD_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) |= (1UL << (uxPriority))
+#define portRESET_READY_PRIORITY(uxPriority, uxReadyPriorities)  (uxReadyPriorities) &= ~(1UL << (uxPriority))
+
+/*-----------------------------------------------------------*/
+
+#define portGET_HIGHEST_PRIORITY(uxTopPriority, uxReadyPriorities) uxTopPriority = (31UL - (uint32_t)ucPortCountLeadingZeros((uxReadyPriorities)))
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+void vPortValidateInterruptPriority(void);
+#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+#define portFORCE_INLINE inline __attribute__((always_inline))
+#endif
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) {
+  uint32_t   ulCurrentInterrupt;
+  BaseType_t xReturn;
+
+  /* Obtain the number of the currently executing interrupt. */
+  __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory");
+
+  if (ulCurrentInterrupt == 0) {
+    xReturn = pdFALSE;
+  } else {
+    xReturn = pdTRUE;
+  }
+
+  return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
+  uint32_t ulNewBASEPRI;
+
+  __asm volatile("	mov %0, %1												\n"
+                 "	msr basepri, %0											\n"
+                 "	isb														\n"
+                 "	dsb														\n"
+                 : "=r"(ulNewBASEPRI)
+                 : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+                 : "memory");
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) {
+  uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+  __asm volatile("	mrs %0, basepri											\n"
+                 "	mov %1, %2												\n"
+                 "	msr basepri, %1											\n"
+                 "	isb														\n"
+                 "	dsb														\n"
+                 : "=r"(ulOriginalBASEPRI), "=r"(ulNewBASEPRI)
+                 : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+                 : "memory");
+
+  /* This return will not be reached but is necessary to prevent compiler
+   warnings. */
+  return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { __asm volatile("	msr basepri, %0	" ::"r"(ulNewMaskValue) : "memory"); }
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile("" ::: "memory")
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */

source/Core/BSP/MHP30/postRTOS.cpp

@@ -0,0 +1,14 @@
+#include "BSP.h"
+#include "FreeRTOS.h"
+#include "I2C_Wrapper.hpp"
+#include "QC3.h"
+#include "Settings.h"
+#include "cmsis_os.h"
+#include "fusbpd.h"
+#include "main.hpp"
+#include "power.hpp"
+#include "stdlib.h"
+#include "task.h"
+
+// Initialisation to be performed with scheduler active
+void postRToSInit() {}

source/Core/BSP/MHP30/preRTOS.cpp

@@ -0,0 +1,24 @@
+/*
+ * preRTOS.c
+ *
+ *  Created on: 29 May 2020
+ *      Author: Ralim
+ */
+
+#include "BSP.h"
+#include "I2CBB.hpp"
+#include "Model_Config.h"
+#include "Pins.h"
+#include "Setup.h"
+#include "fusbpd.h"
+#include <I2C_Wrapper.hpp>
+void preRToSInit() {
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick.
+   */
+  HAL_Init();
+  Setup_HAL(); // Setup all the HAL objects
+  BSPInit();
+  I2CBB::init();
+  /* Init the IPC objects */
+  FRToSI2C::FRToSInit();
+}

source/Core/BSP/MHP30/stm32f1xx_hal_msp.c

@@ -0,0 +1,134 @@
+#include "Pins.h"
+#include "Setup.h"
+#include "stm32f1xx_hal.h"
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void) {
+  __HAL_RCC_AFIO_CLK_ENABLE();
+
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* System interrupt init*/
+  /* MemoryManagement_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
+  /* BusFault_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
+  /* UsageFault_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
+  /* SVCall_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
+  /* DebugMonitor_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+  /* SysTick_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
+}
+
+void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {
+
+  GPIO_InitTypeDef GPIO_InitStruct;
+  if (hadc->Instance == ADC1) {
+    __HAL_RCC_ADC1_CLK_ENABLE();
+
+    /* ADC1 DMA Init */
+    /* ADC1 Init */
+    hdma_adc1.Instance                 = DMA1_Channel1;
+    hdma_adc1.Init.Direction           = DMA_PERIPH_TO_MEMORY;
+    hdma_adc1.Init.PeriphInc           = DMA_PINC_DISABLE;
+    hdma_adc1.Init.MemInc              = DMA_MINC_ENABLE;
+    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+    hdma_adc1.Init.MemDataAlignment    = DMA_MDATAALIGN_WORD;
+    hdma_adc1.Init.Mode                = DMA_CIRCULAR;
+    hdma_adc1.Init.Priority            = DMA_PRIORITY_LOW;
+    HAL_DMA_Init(&hdma_adc1);
+
+    __HAL_LINKDMA(hadc, DMA_Handle, hdma_adc1);
+
+    /* ADC1 interrupt Init */
+    HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0);
+    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
+  } else {
+    __HAL_RCC_ADC2_CLK_ENABLE();
+
+    /**ADC2 GPIO Configuration
+     PB0     ------> ADC2_IN8
+     PB1     ------> ADC2_IN9
+     */
+    GPIO_InitStruct.Pin  = TIP_TEMP_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    HAL_GPIO_Init(TIP_TEMP_GPIO_Port, &GPIO_InitStruct);
+    GPIO_InitStruct.Pin  = TMP36_INPUT_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    HAL_GPIO_Init(TMP36_INPUT_GPIO_Port, &GPIO_InitStruct);
+    GPIO_InitStruct.Pin  = VIN_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    HAL_GPIO_Init(VIN_GPIO_Port, &GPIO_InitStruct);
+    GPIO_InitStruct.Pin  = PLATE_SENSOR_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    HAL_GPIO_Init(PLATE_SENSOR_GPIO_Port, &GPIO_InitStruct);
+
+    /* ADC2 interrupt Init */
+    HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0);
+    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
+  }
+}
+
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) {
+
+  GPIO_InitTypeDef GPIO_InitStruct;
+  /**I2C1 GPIO Configuration
+   PB6     ------> I2C1_SCL
+   PB7     ------> I2C1_SDA
+   */
+  GPIO_InitStruct.Pin   = SCL_Pin | SDA_Pin;
+  GPIO_InitStruct.Mode  = GPIO_MODE_AF_OD;
+  GPIO_InitStruct.Pull  = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_I2C1_CLK_ENABLE();
+  /* I2C1 DMA Init */
+  /* I2C1_RX Init */
+  hdma_i2c1_rx.Instance                 = DMA1_Channel7;
+  hdma_i2c1_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;
+  hdma_i2c1_rx.Init.PeriphInc           = DMA_PINC_DISABLE;
+  hdma_i2c1_rx.Init.MemInc              = DMA_MINC_ENABLE;
+  hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+  hdma_i2c1_rx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
+  hdma_i2c1_rx.Init.Mode                = DMA_NORMAL;
+  hdma_i2c1_rx.Init.Priority            = DMA_PRIORITY_LOW;
+  HAL_DMA_Init(&hdma_i2c1_rx);
+
+  __HAL_LINKDMA(hi2c, hdmarx, hdma_i2c1_rx);
+
+  /* I2C1_TX Init */
+  hdma_i2c1_tx.Instance                 = DMA1_Channel6;
+  hdma_i2c1_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
+  hdma_i2c1_tx.Init.PeriphInc           = DMA_PINC_DISABLE;
+  hdma_i2c1_tx.Init.MemInc              = DMA_MINC_ENABLE;
+  hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+  hdma_i2c1_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
+  hdma_i2c1_tx.Init.Mode                = DMA_NORMAL;
+  hdma_i2c1_tx.Init.Priority            = DMA_PRIORITY_MEDIUM;
+  HAL_DMA_Init(&hdma_i2c1_tx);
+
+  __HAL_LINKDMA(hi2c, hdmatx, hdma_i2c1_tx);
+
+  /* I2C1 interrupt Init */
+  HAL_NVIC_SetPriority(I2C1_EV_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
+  HAL_NVIC_SetPriority(I2C1_ER_IRQn, 15, 0);
+  HAL_NVIC_EnableIRQ(I2C1_ER_IRQn);
+}
+
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base) {
+
+  if (htim_base->Instance == TIM3) {
+    __HAL_RCC_TIM3_CLK_ENABLE();
+  } else if (htim_base->Instance == TIM2) {
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  }
+}

source/Core/BSP/MHP30/stm32f1xx_hal_timebase_TIM.c

@@ -0,0 +1,107 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    stm32f1xx_hal_timebase_TIM.c
+ * @brief   HAL time base based on the hardware TIM.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+#include "stm32f1xx_hal_tim.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef htim4;
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief  This function configures the TIM4 as a time base source.
+ *         The time source is configured  to have 1ms time base with a dedicated
+ *         Tick interrupt priority.
+ * @note   This function is called  automatically at the beginning of program after
+ *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param  TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+  RCC_ClkInitTypeDef clkconfig;
+  uint32_t           uwTimclock       = 0;
+  uint32_t           uwPrescalerValue = 0;
+  uint32_t           pFLatency;
+  /*Configure the TIM4 IRQ priority */
+  HAL_NVIC_SetPriority(TIM4_IRQn, TickPriority, 0);
+
+  /* Enable the TIM4 global Interrupt */
+  HAL_NVIC_EnableIRQ(TIM4_IRQn);
+  /* Enable TIM4 clock */
+  __HAL_RCC_TIM4_CLK_ENABLE();
+
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+
+  /* Compute TIM4 clock */
+  uwTimclock = 2 * HAL_RCC_GetPCLK1Freq();
+  /* Compute the prescaler value to have TIM4 counter clock equal to 1MHz */
+  uwPrescalerValue = (uint32_t)((uwTimclock / 1000000U) - 1U);
+
+  /* Initialize TIM4 */
+  htim4.Instance = TIM4;
+
+  /* Initialize TIMx peripheral as follow:
+  + Period = [(TIM4CLK/1000) - 1]. to have a (1/1000) s time base.
+  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+  + ClockDivision = 0
+  + Counter direction = Up
+  */
+  htim4.Init.Period        = (1000000U / 1000U) - 1U;
+  htim4.Init.Prescaler     = uwPrescalerValue;
+  htim4.Init.ClockDivision = 0;
+  htim4.Init.CounterMode   = TIM_COUNTERMODE_UP;
+  if (HAL_TIM_Base_Init(&htim4) == HAL_OK) {
+    /* Start the TIM time Base generation in interrupt mode */
+    return HAL_TIM_Base_Start_IT(&htim4);
+  }
+
+  /* Return function status */
+  return HAL_ERROR;
+}
+
+/**
+ * @brief  Suspend Tick increment.
+ * @note   Disable the tick increment by disabling TIM4 update interrupt.
+ * @param  None
+ * @retval None
+ */
+void HAL_SuspendTick(void) {
+  /* Disable TIM4 update Interrupt */
+  __HAL_TIM_DISABLE_IT(&htim4, TIM_IT_UPDATE);
+}
+
+/**
+ * @brief  Resume Tick increment.
+ * @note   Enable the tick increment by Enabling TIM4 update interrupt.
+ * @param  None
+ * @retval None
+ */
+void HAL_ResumeTick(void) {
+  /* Enable TIM4 Update interrupt */
+  __HAL_TIM_ENABLE_IT(&htim4, TIM_IT_UPDATE);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/MHP30/stm32f1xx_it.c

@@ -0,0 +1,53 @@
+// This is the stock standard STM interrupt file full of handlers
+#include "stm32f1xx_it.h"
+#include "Pins.h"
+#include "Setup.h"
+#include "cmsis_os.h"
+#include "stm32f1xx.h"
+#include "stm32f1xx_hal.h"
+extern TIM_HandleTypeDef htim4; // used for the systick
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Interruption and Exception Handlers         */
+/******************************************************************************/
+
+void NMI_Handler(void) {}
+
+// We have the assembly for a breakpoint trigger here to halt the system when a debugger is connected
+// Hardfault handler, often a screwup in the code
+void HardFault_Handler(void) {}
+
+// Memory management unit had an error
+void MemManage_Handler(void) {}
+
+// Prefetcher or busfault occured
+void BusFault_Handler(void) {}
+
+void UsageFault_Handler(void) {}
+
+void DebugMon_Handler(void) {}
+
+// Systick is used by FreeRTOS tick
+void SysTick_Handler(void) { osSystickHandler(); }
+
+/******************************************************************************/
+/* STM32F1xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file.					                      */
+/******************************************************************************/
+
+// DMA used to move the ADC readings into system ram
+void DMA1_Channel1_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_adc1); }
+// ADC interrupt used for DMA
+void ADC1_2_IRQHandler(void) { HAL_ADC_IRQHandler(&hadc1); }
+
+// used for hal ticks
+void TIM4_IRQHandler(void) { HAL_TIM_IRQHandler(&htim4); }
+void I2C1_EV_IRQHandler(void) { HAL_I2C_EV_IRQHandler(&hi2c1); }
+void I2C1_ER_IRQHandler(void) { HAL_I2C_ER_IRQHandler(&hi2c1); }
+
+void DMA1_Channel6_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_i2c1_tx); }
+
+void DMA1_Channel7_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_i2c1_rx); }
+void EXTI9_5_IRQHandler(void) { HAL_GPIO_EXTI_IRQHandler(INT_PD_Pin); }

source/Core/BSP/MHP30/system_stm32f1xx.c

@@ -0,0 +1,290 @@
+// This file was automatically generated by the STM Cube software
+// And as such, is BSD licneced from STM
+#include "stm32f1xx.h"
+
+#if !defined(HSI_VALUE)
+#define HSI_VALUE                                               \
+  8000000U /*!< Default value of the Internal oscillator in Hz. \
+                This value can be provided and adapted by the user application. */
+#endif     /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM  */
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/*******************************************************************************
+ *  Clock Definitions
+ *******************************************************************************/
+#if defined(STM32F100xB) || defined(STM32F100xE)
+uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */
+#else                                 /*!< HSI Selected as System Clock source */
+uint32_t SystemCoreClock = 64000000U; /*!< System Clock Frequency (Core Clock) */
+#endif
+
+const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8U]  = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+ * @brief  Setup the microcontroller system
+ *         Initialize the Embedded Flash Interface, the PLL and update the
+ *         SystemCoreClock variable.
+ * @note   This function should be used only after reset.
+ * @param  None
+ * @retval None
+ */
+void SystemInit(void) {
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= 0x00000001U;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+  RCC->CFGR &= 0xF8FF0000U;
+#else
+  RCC->CFGR &= 0xF0FF0000U;
+#endif /* STM32F105xC */
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= 0xFEF6FFFFU;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= 0xFF80FFFFU;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEBFFFFFFU;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000U;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000U;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000U;
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+#endif
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR  = FLASH_BASE | 0x8000; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief  Update SystemCoreClock variable according to Clock Register Values.
+ *         The SystemCoreClock variable contains the core clock (HCLK), it can
+ *         be used by the user application to setup the SysTick timer or configure
+ *         other parameters.
+ *
+ * @note   Each time the core clock (HCLK) changes, this function must be called
+ *         to update SystemCoreClock variable value. Otherwise, any configuration
+ *         based on this variable will be incorrect.
+ *
+ * @note   - The system frequency computed by this function is not the real
+ *           frequency in the chip. It is calculated based on the predefined
+ *           constant and the selected clock source:
+ *
+ *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ *             or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ *             8 MHz) but the real value may vary depending on the variations
+ *             in voltage and temperature.
+ *
+ *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+ *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+ *              that HSE_VALUE is same as the real frequency of the crystal used.
+ *              Otherwise, this function may have wrong result.
+ *
+ *         - The result of this function could be not correct when using fractional
+ *           value for HSE crystal.
+ * @param  None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void) {
+  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+  uint32_t prediv1factor = 0U;
+#endif /* STM32F100xB or STM32F100xE */
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp) {
+  case 0x00U: /* HSI used as system clock */
+    SystemCoreClock = HSI_VALUE;
+    break;
+  case 0x04U: /* HSE used as system clock */
+    SystemCoreClock = HSE_VALUE;
+    break;
+  case 0x08U: /* PLL used as system clock */
+
+    /* Get PLL clock source and multiplication factor ----------------------*/
+    pllmull   = RCC->CFGR & RCC_CFGR_PLLMULL;
+    pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+    pllmull = (pllmull >> 18U) + 2U;
+
+    if (pllsource == 0x00U) {
+      /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+      SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
+    } else {
+#if defined(STM32F100xB) || defined(STM32F100xE)
+      prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
+      /* HSE oscillator clock selected as PREDIV1 clock entry */
+      SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+#else
+      /* HSE selected as PLL clock entry */
+      if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) { /* HSE oscillator clock divided by 2 */
+        SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
+      } else {
+        SystemCoreClock = HSE_VALUE * pllmull;
+      }
+#endif
+    }
+#else
+    pllmull = pllmull >> 18U;
+
+    if (pllmull != 0x0DU) {
+      pllmull += 2U;
+    } else { /* PLL multiplication factor = PLL input clock * 6.5 */
+      pllmull = 13U / 2U;
+    }
+
+    if (pllsource == 0x00U) {
+      /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+      SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
+    } else { /* PREDIV1 selected as PLL clock entry */
+
+      /* Get PREDIV1 clock source and division factor */
+      prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+      prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
+
+      if (prediv1source == 0U) {
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+      } else { /* PLL2 clock selected as PREDIV1 clock entry */
+
+        /* Get PREDIV2 division factor and PLL2 multiplication factor */
+        prediv2factor   = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
+        pll2mull        = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
+        SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+      }
+    }
+#endif /* STM32F105xC */
+    break;
+
+  default:
+    SystemCoreClock = HSI_VALUE;
+    break;
+  }
+
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+ * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s
+ *          before jump to __main
+ * @param  None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief  Setup the external memory controller.
+ *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
+ *         This function configures the external SRAM mounted on STM3210E-EVAL
+ *         board (STM32 High density devices). This SRAM will be used as program
+ *         data memory (including heap and stack).
+ * @param  None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void) {
+  __IO uint32_t tmpreg;
+  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+    required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114U;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+  RCC->APB2ENR = 0x000001E0U;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
+
+  (void)(tmpreg);
+
+  /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+  /*----------------  SRAM Address lines configuration -------------------------*/
+  /*----------------  NOE and NWE configuration --------------------------------*/
+  /*----------------  NE3 configuration ----------------------------------------*/
+  /*----------------  NBL0, NBL1 configuration ---------------------------------*/
+
+  GPIOD->CRL = 0x44BB44BBU;
+  GPIOD->CRH = 0xBBBBBBBBU;
+
+  GPIOE->CRL = 0xB44444BBU;
+  GPIOE->CRH = 0xBBBBBBBBU;
+
+  GPIOF->CRL = 0x44BBBBBBU;
+  GPIOF->CRH = 0xBBBB4444U;
+
+  GPIOG->CRL = 0x44BBBBBBU;
+  GPIOG->CRH = 0x444B4B44U;
+
+  /*----------------  FSMC Configuration ---------------------------------------*/
+  /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+  FSMC_Bank1->BTCR[4U] = 0x00001091U;
+  FSMC_Bank1->BTCR[5U] = 0x00110212U;
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/BSP.cpp

@@ -5,6 +5,8 @@
 #include "Model_Config.h"
 #include "Pins.h"
 #include "Setup.h"
+#include "TipThermoModel.h"
+#include "configuration.h"
 #include "history.hpp"
 #include "main.hpp"
 #include <IRQ.h>
@@ -338,3 +340,12 @@ void BSPInit(void) { switchToFastPWM(); }
 void reboot() { NVIC_SystemReset(); }
 
 void delay_ms(uint16_t count) { HAL_Delay(count); }
+
+bool isTipDisconnected() {
+
+  uint16_t tipDisconnectedThres = TipThermoModel::getTipMaxInC() - 5;
+  uint32_t tipTemp              = TipThermoModel::getTipInC();
+  return tipTemp > tipDisconnectedThres;
+}
+
+void setStatusLED(const enum StatusLED state) {}

source/Core/BSP/Miniware/Power.cpp

@@ -4,6 +4,7 @@
 #include "Pins.h"
 #include "QC3.h"
 #include "Settings.h"
+#include "fusb_user.h"
 #include "fusbpd.h"
 #include "int_n.h"
 #include "policy_engine.h"

source/Core/BSP/Miniware/ThermoModel.cpp

@@ -0,0 +1,130 @@
+/*
+ * ThermoModel.cpp
+ *
+ *  Created on: 1 May 2021
+ *      Author: Ralim
+ */
+#include "TipThermoModel.h"
+#include "Utils.h"
+#include "configuration.h"
+
+#ifdef TEMP_uV_LOOKUP_HAKKO
+const uint16_t uVtoDegC[] = {
+    //
+    //
+    0,     0,   //
+    266,   10,  //
+    522,   20,  //
+    770,   30,  //
+    1010,  40,  //
+    1244,  50,  //
+    1473,  60,  //
+    1697,  70,  //
+    1917,  80,  //
+    2135,  90,  //
+    2351,  100, //
+    2566,  110, //
+    2780,  120, //
+    2994,  130, //
+    3209,  140, //
+    3426,  150, //
+    3644,  160, //
+    3865,  170, //
+    4088,  180, //
+    4314,  190, //
+    4544,  200, //
+    4777,  210, //
+    5014,  220, //
+    5255,  230, //
+    5500,  240, //
+    5750,  250, //
+    6003,  260, //
+    6261,  270, //
+    6523,  280, //
+    6789,  290, //
+    7059,  300, //
+    7332,  310, //
+    7609,  320, //
+    7889,  330, //
+    8171,  340, //
+    8456,  350, //
+    8742,  360, //
+    9030,  370, //
+    9319,  380, //
+    9607,  390, //
+    9896,  400, //
+    10183, 410, //
+    10468, 420, //
+    10750, 430, //
+    11029, 440, //
+    11304, 450, //
+    11573, 460, //
+    11835, 470, //
+    12091, 480, //
+    12337, 490, //
+    12575, 500, //
+
+};
+#endif
+
+#ifdef TEMP_uV_LOOKUP_TS80
+
+const uint16_t uVtoDegC[] = {
+    //
+    //
+    530,   0,   //
+    1282,  10,  //
+    2034,  20,  //
+    2786,  30,  //
+    3538,  40,  //
+    4290,  50,  //
+    5043,  60,  //
+    5795,  70,  //
+    6547,  80,  //
+    7299,  90,  //
+    8051,  100, //
+    8803,  110, //
+    9555,  120, //
+    10308, 130, //
+    11060, 140, //
+    11812, 150, //
+    12564, 160, //
+    13316, 170, //
+    14068, 180, //
+    14820, 190, //
+    15573, 200, //
+    16325, 210, //
+    17077, 220, //
+    17829, 230, //
+    18581, 240, //
+    19333, 250, //
+    20085, 260, //
+    20838, 270, //
+    21590, 280, //
+    22342, 290, //
+    23094, 300, //
+    23846, 310, //
+    24598, 320, //
+    25350, 330, //
+    26103, 340, //
+    26855, 350, //
+    27607, 360, //
+    28359, 370, //
+    29111, 380, //
+    29863, 390, //
+    30615, 400, //
+    31368, 410, //
+    32120, 420, //
+    32872, 430, //
+    33624, 440, //
+    34376, 450, //
+    35128, 460, //
+    35880, 470, //
+    36632, 480, //
+    37385, 490, //
+    38137, 500, //
+};
+#endif
+const int uVtoDegCItems = sizeof(uVtoDegC) / (2 * sizeof(uint16_t));
+
+uint32_t TipThermoModel::convertuVToDegC(uint32_t tipuVDelta) { return Utils::InterpolateLookupTable(uVtoDegC, uVtoDegCItems, tipuVDelta); }

source/Core/BSP/Miniware/fusb_user.cpp

@@ -5,21 +5,6 @@
 #include "Setup.h"
 #include "fusb302b.h"
 #include "fusb_user.h"
-/*
- * Read a single byte from the FUSB302B
- *
- * cfg: The FUSB302B to communicate with
- * addr: The memory address from which to read
- *
- * Returns the value read from addr.
- */
-uint8_t fusb_read_byte(uint8_t addr) {
-  uint8_t data[1];
-  if (!I2CBB::Mem_Read(FUSB302B_ADDR, addr, (uint8_t *)data, 1)) {
-    return 0;
-  }
-  return data[0];
-}
 
 /*
  * Read multiple bytes from the FUSB302B
@@ -31,15 +16,6 @@ uint8_t fusb_read_byte(uint8_t addr) {
  */
 bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) { return I2CBB::Mem_Read(FUSB302B_ADDR, addr, buf, size); }
 
-/*
- * Write a single byte to the FUSB302B
- *
- * cfg: The FUSB302B to communicate with
- * addr: The memory address to which we will write
- * byte: The value to write
- */
-bool fusb_write_byte(uint8_t addr, uint8_t byte) { return I2CBB::Mem_Write(FUSB302B_ADDR, addr, (uint8_t *)&byte, 1); }
-
 /*
  * Write multiple bytes to the FUSB302B
  *
@@ -50,7 +26,7 @@ bool fusb_write_byte(uint8_t addr, uint8_t byte) { return I2CBB::Mem_Write(FUSB3
  */
 bool fusb_write_buf(uint8_t addr, uint8_t size, const uint8_t *buf) { return I2CBB::Mem_Write(FUSB302B_ADDR, addr, buf, size); }
 
-uint8_t fusb302_detect() {
+bool fusb302_detect() {
   // Probe the I2C bus for its address
   return I2CBB::probe(FUSB302B_ADDR);
 }

source/Core/BSP/Miniware/stm32f103.ld

@@ -0,0 +1,169 @@
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20005000;    /* end of RAM */
+
+_Min_Heap_Size = 0x300;      /* required amount of heap  */
+_Min_Stack_Size = 1024; /* required amount of stack */
+
+__APP_BASE_ADDRESS__ = 0x08000000 + __BOOTLDR_SIZE__;
+__ROM_REGION_LENGTH__ = __FLASH_SIZE__ - __BOOTLDR_SIZE__;
+__FLASH_END_ADDR__ = __APP_BASE_ADDRESS__ + __ROM_REGION_LENGTH__;
+
+/* Memories definition */
+MEMORY
+{
+  RAM (xrw)		: ORIGIN = 0x20000000, LENGTH = 20K
+  ROM (rx)		: ORIGIN = __APP_BASE_ADDRESS__, LENGTH = __ROM_REGION_LENGTH__
+}
+/* ROM is normally 48K after the bootloader, however we allocate the last page for settings, and the second last one for display boot logo*/
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into ROM memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >ROM
+
+  /* The program code and other data into ROM memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into ROM memory*/
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >ROM
+
+  .ARM.extab   : { 
+  	. = ALIGN(4);
+  	*(.ARM.extab* .gnu.linkonce.armextab.*)
+  	. = ALIGN(4);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into RAM memory */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> ROM
+
+  .logo_page (NOLOAD) :
+  {
+    . = ABSOLUTE(__FLASH_END_ADDR__ - 2048);
+    KEEP (*(.logo_page*))
+  } > ROM
+
+  .settings_page (NOLOAD) :
+  {
+    . = ABSOLUTE(__FLASH_END_ADDR__ - 1024);
+    KEEP (*(.settings_page*))
+  } > ROM
+
+  .bss :
+  {
+    /* Uninitialized data section into RAM memory */
+    . = ALIGN(4);
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

source/Core/BSP/Pine64/BSP.cpp

@@ -2,12 +2,14 @@
 
 #include "BSP.h"
 #include "I2C_Wrapper.hpp"
+#include "IRQ.h"
 #include "Pins.h"
 #include "Setup.h"
+#include "TipThermoModel.h"
+#include "configuration.h"
 #include "gd32vf103_timer.h"
 #include "history.hpp"
 #include "main.hpp"
-#include <IRQ.h>
 
 const uint16_t powerPWM         = 255;
 const uint8_t  holdoffTicks     = 25; // delay of 7 ms
@@ -120,3 +122,12 @@ void     delay_ms(uint16_t count) { delay_1ms(count); }
 uint32_t __get_IPSR(void) {
   return 0; // To shut-up CMSIS
 }
+
+bool isTipDisconnected() {
+
+  uint16_t tipDisconnectedThres = TipThermoModel::getTipMaxInC() - 5;
+  uint32_t tipTemp              = TipThermoModel::getTipInC();
+  return tipTemp > tipDisconnectedThres;
+}
+
+void setStatusLED(const enum StatusLED state) {}

source/Core/BSP/Pine64/Power.cpp

@@ -4,6 +4,7 @@
 #include "Pins.h"
 #include "QC3.h"
 #include "Settings.h"
+#include "fusb_user.h"
 #include "fusbpd.h"
 #include "int_n.h"
 #include "policy_engine.h"

source/Core/BSP/Pine64/ThermoModel.cpp

@@ -0,0 +1,72 @@
+/*
+ * ThermoModel.cpp
+ *
+ *  Created on: 1 May 2021
+ *      Author: Ralim
+ */
+#include "TipThermoModel.h"
+#include "Utils.h"
+#include "configuration.h"
+
+#ifdef TEMP_uV_LOOKUP_HAKKO
+const uint16_t uVtoDegC[] = {
+    //
+    // uv -> temp in C
+    0,     0,   //
+    266,   10,  //
+    522,   20,  //
+    770,   30,  //
+    1010,  40,  //
+    1244,  50,  //
+    1473,  60,  //
+    1697,  70,  //
+    1917,  80,  //
+    2135,  90,  //
+    2351,  100, //
+    2566,  110, //
+    2780,  120, //
+    2994,  130, //
+    3209,  140, //
+    3426,  150, //
+    3644,  160, //
+    3865,  170, //
+    4088,  180, //
+    4314,  190, //
+    4544,  200, //
+    4777,  210, //
+    5014,  220, //
+    5255,  230, //
+    5500,  240, //
+    5750,  250, //
+    6003,  260, //
+    6261,  270, //
+    6523,  280, //
+    6789,  290, //
+    7059,  300, //
+    7332,  310, //
+    7609,  320, //
+    7889,  330, //
+    8171,  340, //
+    8456,  350, //
+    8742,  360, //
+    9030,  370, //
+    9319,  380, //
+    9607,  390, //
+    9896,  400, //
+    10183, 410, //
+    10468, 420, //
+    10750, 430, //
+    11029, 440, //
+    11304, 450, //
+    11573, 460, //
+    11835, 470, //
+    12091, 480, //
+    12337, 490, //
+    12575, 500, //
+
+};
+#endif
+
+const int uVtoDegCItems = sizeof(uVtoDegC) / (2 * sizeof(uint16_t));
+
+uint32_t TipThermoModel::convertuVToDegC(uint32_t tipuVDelta) { return Utils::InterpolateLookupTable(uVtoDegC, uVtoDegCItems, tipuVDelta); }

source/Core/BSP/Pine64/fusb_user.cpp

@@ -5,21 +5,6 @@
 #include "Setup.h"
 #include "fusb302b.h"
 #include "fusb_user.h"
-/*
- * Read a single byte from the FUSB302B
- *
- * cfg: The FUSB302B to communicate with
- * addr: The memory address from which to read
- *
- * Returns the value read from addr.
- */
-uint8_t fusb_read_byte(uint8_t addr) {
-  uint8_t data[1];
-  if (!FRToSI2C::Mem_Read(FUSB302B_ADDR, addr, (uint8_t *)data, 1)) {
-    return 0;
-  }
-  return data[0];
-}
 
 /*
  * Read multiple bytes from the FUSB302B
@@ -31,15 +16,6 @@ uint8_t fusb_read_byte(uint8_t addr) {
  */
 bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) { return FRToSI2C::Mem_Read(FUSB302B_ADDR, addr, buf, size); }
 
-/*
- * Write a single byte to the FUSB302B
- *
- * cfg: The FUSB302B to communicate with
- * addr: The memory address to which we will write
- * byte: The value to write
- */
-bool fusb_write_byte(uint8_t addr, uint8_t byte) { return FRToSI2C::Mem_Write(FUSB302B_ADDR, addr, (uint8_t *)&byte, 1); }
-
 /*
  * Write multiple bytes to the FUSB302B
  *
@@ -50,7 +26,7 @@ bool fusb_write_byte(uint8_t addr, uint8_t byte) { return FRToSI2C::Mem_Write(FU
  */
 bool fusb_write_buf(uint8_t addr, uint8_t size, const uint8_t *buf) { return FRToSI2C::Mem_Write(FUSB302B_ADDR, addr, (uint8_t *)buf, size); }
 
-uint8_t fusb302_detect() {
+bool fusb302_detect() {
   // Probe the I2C bus for its address
   return FRToSI2C::probe(FUSB302B_ADDR);
 }

source/Core/Drivers/FUSB302/fusb302b.cpp

@@ -21,7 +21,9 @@
 #include "fusb_user.h"
 #include "int_n.h"
 #include <pd.h>
-void fusb_send_message(const union pd_msg *msg) {
+uint8_t fusb_read_byte(uint8_t addr);
+bool    fusb_write_byte(uint8_t addr, uint8_t byte);
+void    fusb_send_message(const union pd_msg *msg) {
 
   /* Token sequences for the FUSB302B */
   static uint8_t       sop_seq[5] = {FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP2, FUSB_FIFO_TX_PACKSYM};
@@ -41,6 +43,8 @@ void fusb_send_message(const union pd_msg *msg) {
   fusb_write_buf(FUSB_FIFOS, 4, eop_seq);
 }
 
+bool fusb_rx_pending() { return (fusb_read_byte(FUSB_STATUS1) & FUSB_STATUS1_RX_EMPTY) != FUSB_STATUS1_RX_EMPTY; }
+
 uint8_t fusb_read_message(union pd_msg *msg) {
 
   static uint8_t garbage[4];
@@ -48,7 +52,11 @@ uint8_t fusb_read_message(union pd_msg *msg) {
 
   // Read the header. If its not a SOP we dont actually want it at all
   // But on some revisions of the fusb if you dont both pick them up and read them out of the fifo, it gets stuck
-  fusb_read_byte(FUSB_FIFOS);
+  if ((fusb_read_byte(FUSB_FIFOS) & FUSB_FIFO_RX_TOKEN_BITS) != FUSB_FIFO_RX_SOP) {
+    return 1;
+  }
+
+  //	fusb_read_byte(FUSB_FIFOS);
   /* Read the message header into msg */
   fusb_read_buf(FUSB_FIFOS, 2, msg->bytes);
   /* Get the number of data objects */
@@ -111,11 +119,11 @@ bool fusb_setup() {
 
   /* Select the correct CC line for BMC signaling; also enable AUTO_CRC */
   if (cc1 > cc2) {
-    fusb_write_byte(FUSB_SWITCHES1, 0x25);
+    fusb_write_byte(FUSB_SWITCHES1, 0x25); // TX_CC1|AUTO_CRC|SPECREV0
-    fusb_write_byte(FUSB_SWITCHES0, 0x07);
+    fusb_write_byte(FUSB_SWITCHES0, 0x07); // PWDN1|PWDN2|MEAS_CC1
   } else {
-    fusb_write_byte(FUSB_SWITCHES1, 0x26);
+    fusb_write_byte(FUSB_SWITCHES1, 0x26); // TX_CC2|AUTO_CRC|SPECREV0
-    fusb_write_byte(FUSB_SWITCHES0, 0x0B);
+    fusb_write_byte(FUSB_SWITCHES0, 0x0B); // PWDN1|PWDN2|MEAS_CC2
   }
 
   fusb_reset();
@@ -123,10 +131,10 @@ bool fusb_setup() {
   return true;
 }
 
-void fusb_get_status(union fusb_status *status) {
+bool fusb_get_status(union fusb_status *status) {
 
   /* Read the interrupt and status flags into status */
-  fusb_read_buf(FUSB_STATUS0A, 7, status->bytes);
+  return fusb_read_buf(FUSB_STATUS0A, 7, status->bytes);
 }
 
 enum fusb_typec_current fusb_get_typec_current() {
@@ -144,7 +152,7 @@ void fusb_reset() {
   /* Flush the RX buffer */
   fusb_write_byte(FUSB_CONTROL1, FUSB_CONTROL1_RX_FLUSH);
   /* Reset the PD logic */
-  //	fusb_write_byte( FUSB_RESET, FUSB_RESET_PD_RESET);
+  fusb_write_byte(FUSB_RESET, FUSB_RESET_PD_RESET);
 }
 
 bool fusb_read_id() {
@@ -154,4 +162,28 @@ bool fusb_read_id() {
   if (version == 0 || version == 0xFF)
     return false;
   return true;
-}
+}
+/*
+ * Read a single byte from the FUSB302B
+ *
+ * cfg: The FUSB302B to communicate with
+ * addr: The memory address from which to read
+ *
+ * Returns the value read from addr.
+ */
+uint8_t fusb_read_byte(uint8_t addr) {
+  uint8_t data[1];
+  if (!fusb_read_buf(addr, 1, (uint8_t *)data)) {
+    return 0;
+  }
+  return data[0];
+}
+
+/*
+ * Write a single byte to the FUSB302B
+ *
+ * cfg: The FUSB302B to communicate with
+ * addr: The memory address to which we will write
+ * byte: The value to write
+ */
+bool fusb_write_byte(uint8_t addr, uint8_t byte) { return fusb_write_buf(addr, 1, (uint8_t *)&byte); }

source/Core/Drivers/FUSB302/fusb302b.h

@@ -269,7 +269,7 @@ union fusb_status {
  * Send a USB Power Delivery message to the FUSB302B
  */
 void fusb_send_message(const union pd_msg *msg);
-
+bool fusb_rx_pending();
 /*
  * Read a USB Power Delivery message from the FUSB302B
  */
@@ -283,7 +283,7 @@ void fusb_send_hardrst();
 /*
  * Read the FUSB302B status and interrupt flags into *status
  */
-void fusb_get_status(union fusb_status *status);
+bool fusb_get_status(union fusb_status *status);
 
 /*
  * Read the FUSB302B BC_LVL as an enum fusb_typec_current

source/Core/Drivers/FUSB302/fusb_user.h

@@ -19,11 +19,29 @@
 #define PDB_FUSB_USER_H
 
 #include <stdint.h>
-uint8_t fusb_read_byte(uint8_t addr);
+/*
-bool    fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf);
+ * Read multiple bytes from the FUSB302B
-bool    fusb_write_byte(uint8_t addr, uint8_t byte);
+ *
-bool    fusb_write_buf(uint8_t addr, uint8_t size, const uint8_t *buf);
+ * cfg: The FUSB302B to communicate with
-uint8_t fusb302_detect();
+ * addr: The memory address from which to read
-void    setupFUSBIRQ();
+ * size: The number of bytes to read
+ * buf: The buffer into which data will be read
+ */
+bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf);
+/*
+ * Write multiple bytes to the FUSB302B
+ *
+ * cfg: The FUSB302B to communicate with
+ * addr: The memory address to which we will write
+ * size: The number of bytes to write
+ * buf: The buffer to write
+ */
+bool fusb_write_buf(uint8_t addr, uint8_t size, const uint8_t *buf);
+// Used to poll for the device existing on the I2C bus. This should return non-zero if the device is responding on the bus
+bool fusb302_detect();
+// Once this is called IRQ's should be enabled and routed to the IRQ handler thread
+void setupFUSBIRQ();
+// This should return true if the IRQ line for the FUSB302 is still held low
+bool getFUS302IRQLow();
 
 #endif /* PDB_FUSB302B_H */

source/Core/Drivers/FUSB302/fusbpd.cpp

@@ -12,7 +12,6 @@
 #include "int_n.h"
 #include "policy_engine.h"
 
-#include "protocol_tx.h"
 #include <fusbpd.h>
 #include <pd.h>
 
@@ -20,7 +19,6 @@ void fusb302_start_processing() {
   /* Initialize the FUSB302B */
   if (fusb_setup()) {
     PolicyEngine::init();
-    ProtocolTransmit::init();
     InterruptHandler::init();
   }
 }

source/Core/Drivers/FUSB302/fusbpd.h

@@ -11,8 +11,5 @@
 extern struct pdb_config pdb_config_data;
 #include <stdint.h>
 
-// returns 1 if the FUSB302 is on the I2C bus
-uint8_t fusb302_detect();
-
 void fusb302_start_processing();
 #endif /* DRIVERS_FUSB302_FUSBPD_H_ */