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Shrink flash usage _just_ enough

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This commit is contained in:
Ben V. Brown
2020-07-23 22:45:00 +10:00
parent 85decdc15b
commit ff65e6437b
16 changed files with 213 additions and 517 deletions
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2
workspace/TS100/Core/BSP/BSP.h
View File

@@ -48,7 +48,7 @@ void reboot();
// Returns 1 if the logo was printed so that the unit waits for the timeout or button
uint8_t showBootLogoIfavailable();
//delay wrapper for delay using the hardware timer (used before RTOS)
void delay_ms(uint16_t count);
void delay_ms(uint16_t count) ;
//Used to allow knowledge of if usb_pd is being used
uint8_t usb_pd_detect();
//Returns 0 when the irq line is pulled down

84
workspace/TS100/Core/BSP/Miniware/BSP.cpp
View File

@@ -51,57 +51,37 @@ static const uint16_t NTCHandleLookup[] = {
22264, 27, //
21933, 28, //
21599, 29, //
21261, 30, //
20921, 31, //
20579, 32, //
20234, 33, //
19888, 34, //
19541, 35, //
19192, 36, //
18843, 37, //
18493, 38, //
18143, 39, //
17793, 40, //
17444, 41, //
17096, 42, //
16750, 43, //
16404, 44, //
16061, 45, //
15719, 46, //
15380, 47, //
15044, 48, //
14710, 49, //
14380, 50, //
14053, 51, //
13729, 52, //
13410, 53, //
13094, 54, //
12782, 55, //
12475, 56, //
12172, 57, //
11874, 58, //
11580, 59, //
11292, 60, //
11008, 61, //
10729, 62, //
10455, 63, //
10187, 64, //
9923, 65, //
9665, 66, //
9412, 67, //
9164, 68, //
8921, 69, //
8684, 70, //
8451, 71, //
8225, 72, //
8003, 73, //
7786, 74, //
7575, 75, //
7368, 76, //
7167, 77, //
6970, 78, //
6779, 79, //
6592, 80, //
// 21261, 30, //
// 20921, 31, //
// 20579, 32, //
// 20234, 33, //
// 19888, 34, //
// 19541, 35, //
// 19192, 36, //
// 18843, 37, //
// 18493, 38, //
// 18143, 39, //
// 17793, 40, //
// 17444, 41, //
// 17096, 42, //
// 16750, 43, //
// 16404, 44, //
// 16061, 45, //
// 15719, 46, //
// 15380, 47, //
// 15044, 48, //
// 14710, 49, //
// 14380, 50, //
// 14053, 51, //
// 13729, 52, //
// 13410, 53, //
// 13094, 54, //
// 12782, 55, //
// 12475, 56, //
// 12172, 57, //
// 11874, 58, //
// 11580, 59, //
// 11292, 60, //
};
#endif
uint16_t getHandleTemperature() {
@@ -110,7 +90,7 @@ uint16_t getHandleTemperature() {
//NTCG104EF104FT1X from TDK
//For now not doing interpolation
int32_t result = getADC(0);
for (int i = 0; i < (sizeof(NTCHandleLookup) / (2 * sizeof(uint16_t)));
for (uint32_t i = 0; i < (sizeof(NTCHandleLookup) / (2 * sizeof(uint16_t)));
i++) {
if (result > NTCHandleLookup[(i * 2) + 0]) {
return NTCHandleLookup[(i * 2) + 1] * 10;

1
workspace/TS100/Core/BSP/Miniware/IRQ.cpp
View File

@@ -44,5 +44,6 @@ void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
}
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
(void)GPIO_Pin;
InterruptHandler::irqCallback();
}

6
workspace/TS100/Core/BSP/Miniware/Setup.c
View File

@@ -33,9 +33,9 @@ static void MX_ADC2_Init(void);
void Setup_HAL() {
SystemClock_Config();
// __HAL_AFIO_REMAP_SWJ_DISABLE()
// ;
__HAL_AFIO_REMAP_SWJ_NOJTAG();
__HAL_AFIO_REMAP_SWJ_DISABLE()
;
// __HAL_AFIO_REMAP_SWJ_NOJTAG();
MX_GPIO_Init();
MX_DMA_Init();
MX_I2C1_Init();

52
workspace/TS100/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c vendored
View File

@@ -1041,32 +1041,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
/* - if scan mode is enabled, injected channels sequence length is set to */
/* parameter "InjectedNbrOfConversion". */
if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
{
if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
{
/* Clear the old SQx bits for all injected ranks */
MODIFY_REG(hadc->Instance->JSQR ,
ADC_JSQR_JL |
ADC_JSQR_JSQ4 |
ADC_JSQR_JSQ3 |
ADC_JSQR_JSQ2 |
ADC_JSQR_JSQ1 ,
ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
ADC_INJECTED_RANK_1,
0x01U));
}
/* If another injected rank than rank1 was intended to be set, and could */
/* not due to ScanConvMode disabled, error is reported. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
}
else
// if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
// {
// if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
// {
// /* Clear the old SQx bits for all injected ranks */
// MODIFY_REG(hadc->Instance->JSQR ,
// ADC_JSQR_JL |
// ADC_JSQR_JSQ4 |
// ADC_JSQR_JSQ3 |
// ADC_JSQR_JSQ2 |
// ADC_JSQR_JSQ1 ,
// ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
// ADC_INJECTED_RANK_1,
// 0x01U));
// }
// /* If another injected rank than rank1 was intended to be set, and could */
// /* not due to ScanConvMode disabled, error is reported. */
// else
// {
// /* Update ADC state machine to error */
// SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
//
// tmp_hal_status = HAL_ERROR;
// }
// }
// else
{
/* Since injected channels rank conv. order depends on total number of */
/* injected conversions, selected rank must be below or equal to total */

163
workspace/TS100/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c vendored
View File

@@ -369,57 +369,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
{
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
{
@@ -486,121 +435,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
FlagStatus pwrclkchanged = RESET;
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
{
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
}
#if defined(RCC_CR_PLL2ON)
/*-------------------------------- PLL2 Configuration -----------------------*/

246
workspace/TS100/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c vendored
View File

@@ -3968,129 +3968,129 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
}
break;
case TIM_CLOCKSOURCE_ETRMODE1:
{
/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
/* Check ETR input conditioning related parameters */
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
/* Reset the SMS and TS Bits */
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
}
break;
case TIM_CLOCKSOURCE_ETRMODE2:
{
/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
/* Check ETR input conditioning related parameters */
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
}
break;
case TIM_CLOCKSOURCE_TI1:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
}
break;
case TIM_CLOCKSOURCE_TI2:
{
/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
}
break;
case TIM_CLOCKSOURCE_TI1ED:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
}
break;
case TIM_CLOCKSOURCE_ITR0:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
}
break;
case TIM_CLOCKSOURCE_ITR1:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
}
break;
case TIM_CLOCKSOURCE_ITR2:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
}
break;
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
}
break;
// case TIM_CLOCKSOURCE_ETRMODE1:
// {
// /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
// assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
//
// /* Check ETR input conditioning related parameters */
// assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
// assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
// assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
//
// /* Configure the ETR Clock source */
// TIM_ETR_SetConfig(htim->Instance,
// sClockSourceConfig->ClockPrescaler,
// sClockSourceConfig->ClockPolarity,
// sClockSourceConfig->ClockFilter);
// /* Get the TIMx SMCR register value */
// tmpsmcr = htim->Instance->SMCR;
// /* Reset the SMS and TS Bits */
// tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
// /* Select the External clock mode1 and the ETRF trigger */
// tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
// /* Write to TIMx SMCR */
// htim->Instance->SMCR = tmpsmcr;
// }
// break;
//
// case TIM_CLOCKSOURCE_ETRMODE2:
// {
// /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
// assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
//
// /* Check ETR input conditioning related parameters */
// assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
// assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
// assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
//
// /* Configure the ETR Clock source */
// TIM_ETR_SetConfig(htim->Instance,
// sClockSourceConfig->ClockPrescaler,
// sClockSourceConfig->ClockPolarity,
// sClockSourceConfig->ClockFilter);
// /* Enable the External clock mode2 */
// htim->Instance->SMCR |= TIM_SMCR_ECE;
// }
// break;
//
// case TIM_CLOCKSOURCE_TI1:
// {
// /* Check whether or not the timer instance supports external clock mode 1 */
// assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
//
// /* Check TI1 input conditioning related parameters */
// assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
// assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
//
// TIM_TI1_ConfigInputStage(htim->Instance,
// sClockSourceConfig->ClockPolarity,
// sClockSourceConfig->ClockFilter);
// TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
// }
// break;
// case TIM_CLOCKSOURCE_TI2:
// {
// /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
// assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
//
// /* Check TI2 input conditioning related parameters */
// assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
// assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
//
// TIM_TI2_ConfigInputStage(htim->Instance,
// sClockSourceConfig->ClockPolarity,
// sClockSourceConfig->ClockFilter);
// TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
// }
// break;
// case TIM_CLOCKSOURCE_TI1ED:
// {
// /* Check whether or not the timer instance supports external clock mode 1 */
// assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
//
// /* Check TI1 input conditioning related parameters */
// assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
// assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
//
// TIM_TI1_ConfigInputStage(htim->Instance,
// sClockSourceConfig->ClockPolarity,
// sClockSourceConfig->ClockFilter);
// TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
// }
// break;
// case TIM_CLOCKSOURCE_ITR0:
// {
// /* Check whether or not the timer instance supports external clock mode 1 */
// assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
//
// TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
// }
// break;
// case TIM_CLOCKSOURCE_ITR1:
// {
// /* Check whether or not the timer instance supports external clock mode 1 */
// assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
//
// TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
// }
// break;
// case TIM_CLOCKSOURCE_ITR2:
// {
// /* Check whether or not the timer instance supports external clock mode 1 */
// assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
//
// TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
// }
// break;
// case TIM_CLOCKSOURCE_ITR3:
// {
// /* Check whether or not the timer instance supports external clock mode 1 */
// assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
//
// TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
// }
// break;
default:
break;

2
workspace/TS100/Core/BSP/Miniware/system_stm32f1xx.c
View File

@@ -11,7 +11,7 @@
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
#define LOCAL_BUILD
//#define LOCAL_BUILD
#ifndef LOCAL_BUILD
#define VECT_TAB_OFFSET 0x00004000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */