Move mem_read to new state format
This commit is contained in:
Ben V. Brown
@@ -12,498 +12,487 @@ SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr;
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StaticSemaphore_t FRToSI2C::xSemaphoreBuffer;
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#define I2C_TIME_OUT (uint16_t)(12000)
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void FRToSI2C::CpltCallback() {
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// TODO
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// TODO
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}
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bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }
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bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) {
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return Mem_Write(address, reg, &data, 1);
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}
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uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) {
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uint8_t temp = 0;
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Mem_Read(add, reg, &temp, 1);
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return temp;
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uint8_t temp = 0;
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Mem_Read(add, reg, &temp, 1);
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return temp;
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}
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enum i2c_step {
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//Write+read steps
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Write_start, //Sending start on bus
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Write_device_address, //start sent, send device address
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Write_device_memory_address, //device address sent, write the memory location
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Write_device_data_start, // Write all of the remaining data using DMA
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Write_device_data_wait, // Write all of the remaining data using DMA
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Read_start, //second read
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Read_device_address, // Send device address again for the read
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Read_device_data_start, //read device data via DMA
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Read_device_data_finish, //read device data via DMA
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Send_stop, // send the stop at the end of the transaction
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Wait_stop, // Wait for stop to send and we are done
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Done, //Finished
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Error_occured, //Error occured on the bus
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};
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struct i2c_state {
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i2c_step currentStep;
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dma_parameter_struct dma_init_struct;
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};
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volatile i2c_state currentState;
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bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_buffer, uint16_t number_of_byte) {
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if (!lock())
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return false;
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i2c_interrupt_disable(I2C0, I2C_INT_ERR);
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i2c_interrupt_disable(I2C0, I2C_INT_BUF);
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i2c_interrupt_disable(I2C0, I2C_INT_EV);
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dma_parameter_struct dma_init_struct;
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if (!lock())
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return false;
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i2c_interrupt_disable(I2C0, I2C_INT_ERR);
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i2c_interrupt_disable(I2C0, I2C_INT_BUF);
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i2c_interrupt_disable(I2C0, I2C_INT_EV);
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//Setup DMA
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dma_deinit(DMA0, DMA_CH6);
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currentState.dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
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currentState.dma_init_struct.memory_addr = (uint32_t) p_buffer;
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currentState.dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
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currentState.dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
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currentState.dma_init_struct.number = number_of_byte;
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currentState.dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0);
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currentState.dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
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currentState.dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
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currentState.dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
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dma_init(DMA0, DMA_CH6, (dma_parameter_struct*) ¤tState.dma_init_struct);
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uint8_t state = I2C_START;
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uint8_t in_rx_cycle = 0;
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uint16_t timeout = 0;
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uint8_t tries = 0;
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uint8_t i2c_timeout_flag = 0;
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while (!(i2c_timeout_flag)) {
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switch (state) {
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case I2C_START:
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tries++;
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if (tries > 64) {
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i2c_stop_on_bus(I2C0);
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/* i2c master sends STOP signal successfully */
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while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
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timeout++;
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}
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unlock();
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return false;
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}
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if (0 == in_rx_cycle) {
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/* disable I2C0 */
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i2c_disable(I2C0);
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/* enable I2C0 */
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i2c_enable(I2C0);
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i2c_dma_last_transfer_config(I2C0, I2C_DMALST_ON);
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/* enable acknowledge */
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i2c_ack_config(I2C0, I2C_ACK_ENABLE);
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/* i2c master sends start signal only when the bus is idle */
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while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
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timeout++;
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}
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if (timeout < I2C_TIME_OUT) {
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/* send the start signal */
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i2c_start_on_bus(I2C0);
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timeout = 0;
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state = I2C_SEND_ADDRESS;
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} else {
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I2C_Unstick();
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timeout = 0;
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state = I2C_START;
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}
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} else {
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i2c_start_on_bus(I2C0);
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timeout = 0;
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state = I2C_SEND_ADDRESS;
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}
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break;
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case I2C_SEND_ADDRESS:
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/* i2c master sends START signal successfully */
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while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
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timeout++;
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}
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if (timeout < I2C_TIME_OUT) {
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if (RESET == in_rx_cycle) {
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i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
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state = I2C_CLEAR_ADDRESS_FLAG;
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} else {
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i2c_master_addressing(I2C0, DevAddress, I2C_RECEIVER);
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state = I2C_CLEAR_ADDRESS_FLAG;
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}
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timeout = 0;
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} else {
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timeout = 0;
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state = I2C_START;
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in_rx_cycle = 0;
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}
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break;
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case I2C_CLEAR_ADDRESS_FLAG:
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/* address flag set means i2c slave sends ACK */
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while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) {
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timeout++;
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if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
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i2c_flag_clear(I2C0, I2C_FLAG_AERR);
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i2c_stop_on_bus(I2C0);
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/* i2c master sends STOP signal successfully */
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while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
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timeout++;
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}
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// Address NACK'd
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unlock();
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return false;
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}
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}
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if (timeout < I2C_TIME_OUT) {
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i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
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timeout = 0;
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state = I2C_TRANSMIT_DATA;
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} else {
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i2c_stop_on_bus(I2C0);
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/* i2c master sends STOP signal successfully */
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while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
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timeout++;
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}
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// Address NACK'd
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unlock();
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return false;
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}
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break;
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case I2C_TRANSMIT_DATA:
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if (0 == in_rx_cycle) {
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/* wait until the transmit data buffer is empty */
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while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
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timeout++;
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}
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if (timeout < I2C_TIME_OUT) {
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// Write out the 8 byte address
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i2c_data_transmit(I2C0, read_address);
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timeout = 0;
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} else {
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timeout = 0;
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state = I2C_START;
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in_rx_cycle = 0;
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}
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/* wait until BTC bit is set */
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while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) {
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timeout++;
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}
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if (timeout < I2C_TIME_OUT) {
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timeout = 0;
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state = I2C_START;
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in_rx_cycle = 1;
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} else {
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timeout = 0;
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state = I2C_START;
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in_rx_cycle = 0;
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}
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} else {
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/* one byte master reception procedure (polling) */
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if (number_of_byte < 2) {
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/* disable acknowledge */
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i2c_ack_config(I2C0, I2C_ACK_DISABLE);
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/* clear ADDSEND register by reading I2C_STAT0 then I2C_STAT1 register
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* (I2C_STAT0 has already been read) */
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i2c_flag_get(I2C0, I2C_FLAG_ADDSEND);
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/* send a stop condition to I2C bus*/
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i2c_stop_on_bus(I2C0);
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/* wait for the byte to be received */
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while (!i2c_flag_get(I2C0, I2C_FLAG_RBNE))
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;
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/* read the byte received from the EEPROM */
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*p_buffer = i2c_data_receive(I2C0);
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/* decrement the read bytes counter */
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number_of_byte--;
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timeout = 0;
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} else { /* more than one byte master reception procedure (DMA) */
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dma_deinit(DMA0, DMA_CH6);
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dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
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dma_init_struct.memory_addr = (uint32_t)p_buffer;
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dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
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dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
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dma_init_struct.number = number_of_byte;
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dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0);
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dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
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dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
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dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
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dma_init(DMA0, DMA_CH6, &dma_init_struct);
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currentState.currentStep = Write_start;
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TickType_t timeout = xTaskGetTickCount() + TICKS_SECOND;
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while ((currentState.currentStep != Done) && (currentState.currentStep != Error_occured)) {
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if (xTaskGetTickCount() > timeout) {
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i2c_stop_on_bus(I2C0);
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I2C_Unstick();
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unlock();
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return false;
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}
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switch (currentState.currentStep) {
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case Error_occured:
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i2c_dma_last_transfer_config(I2C0, I2C_DMALST_ON);
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/* enable I2C0 DMA */
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i2c_dma_enable(I2C0, I2C_DMA_ON);
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/* enable DMA0 channel5 */
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dma_channel_enable(DMA0, DMA_CH6);
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/* wait until BTC bit is set */
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while (!dma_flag_get(DMA0, DMA_CH6, DMA_FLAG_FTF)) {}
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/* send a stop condition to I2C bus*/
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i2c_stop_on_bus(I2C0);
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}
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timeout = 0;
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state = I2C_STOP;
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}
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break;
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case I2C_STOP:
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/* i2c master sends STOP signal successfully */
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while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
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timeout++;
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}
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if (timeout < I2C_TIME_OUT) {
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timeout = 0;
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state = I2C_END;
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i2c_timeout_flag = I2C_OK;
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} else {
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timeout = 0;
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state = I2C_START;
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in_rx_cycle = 0;
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}
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break;
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default:
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state = I2C_START;
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in_rx_cycle = 0;
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i2c_timeout_flag = I2C_OK;
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timeout = 0;
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break;
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}
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}
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unlock();
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return true;
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i2c_stop_on_bus(I2C0);
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I2C_Unstick();
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unlock();
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return false;
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break;
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case Write_start:
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/* disable I2C0 */
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i2c_disable(I2C0);
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/* enable I2C0 */
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i2c_enable(I2C0);
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/* enable acknowledge */
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i2c_ack_config(I2C0, I2C_ACK_ENABLE);
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/* i2c master sends start signal only when the bus is idle */
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if (!i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)) {
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/* send the start signal */
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i2c_start_on_bus(I2C0);
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currentState.currentStep = Write_device_address;
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}
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break;
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case Read_start:
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/* wait until BTC bit is set */
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if (i2c_flag_get(I2C0, I2C_FLAG_BTC)) {
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i2c_start_on_bus(I2C0);
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currentState.currentStep = Read_device_address;
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}
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break;
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case Write_device_address:
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/* i2c master sends START signal successfully */
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if (i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) {
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i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
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currentState.currentStep = Write_device_memory_address;
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}
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break;
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case Read_device_address:
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if (i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) {
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i2c_master_addressing(I2C0, DevAddress, I2C_RECEIVER);
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currentState.currentStep = Read_device_data_start;
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}
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break;
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case Write_device_memory_address:
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//Send the device memory location
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if (i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) { //addr sent
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if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
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//Arb error - we lost the bus / nacked
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currentState.currentStep = Error_occured;
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}
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if (i2c_flag_get(I2C0, I2C_FLAG_TBE)) {
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i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
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// Write out the 8 byte address
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i2c_data_transmit(I2C0, read_address);
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currentState.currentStep = Read_start;
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}
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}
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break;
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case Read_device_data_start:
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if (i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) { //addr sent
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if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
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//Arb error - we lost the bus / nacked
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currentState.currentStep = Error_occured;
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}
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i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); //TODO may not be able to do this
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/* one byte master reception procedure (polling) */
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if (number_of_byte == 0) {
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currentState.currentStep = Send_stop;
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} else if (number_of_byte == 1) {
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/* disable acknowledge */
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i2c_ack_config(I2C0, I2C_ACK_DISABLE);
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/* clear ADDSEND register by reading I2C_STAT0 then I2C_STAT1 register
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* (I2C_STAT0 has already been read) */
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i2c_flag_get(I2C0, I2C_FLAG_ADDSEND); //sat0
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i2c_flag_get(I2C0, I2C_FLAG_I2CBSY); //sat1
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/* send a stop condition to I2C bus*/
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i2c_stop_on_bus(I2C0);
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/* wait for the byte to be received */
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while (!i2c_flag_get(I2C0, I2C_FLAG_RBNE))
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;
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/* read the byte received from the EEPROM */
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*p_buffer = i2c_data_receive(I2C0);
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currentState.currentStep = Wait_stop;
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} else { /* more than one byte master reception procedure (DMA) */
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/* enable I2C0 DMA */
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i2c_dma_enable(I2C0, I2C_DMA_ON);
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/* enable DMA0 channel5 */
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dma_channel_enable(DMA0, DMA_CH6);
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currentState.currentStep = Read_device_data_finish;
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}
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}
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break;
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case Read_device_data_finish: //Wait for complete then goto stop
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/* wait until BTC bit is set */
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if (dma_flag_get(DMA0, DMA_CH6, DMA_FLAG_FTF)) {
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currentState.currentStep = Send_stop;
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}
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break;
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case Send_stop:
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/* send a stop condition to I2C bus*/
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i2c_stop_on_bus(I2C0);
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currentState.currentStep = Wait_stop;
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break;
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case Wait_stop:
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/* i2c master sends STOP signal successfully */
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if ((I2C_CTL0(I2C0) & 0x0200) != 0x0200) {
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currentState.currentStep = Done;
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}
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break;
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default:
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//If we get here something is amiss
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unlock();
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return false;
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}
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}
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unlock();
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return true;
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}
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bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_buffer, uint16_t number_of_byte) {
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if (!lock())
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return false;
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if (!lock())
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return false;
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i2c_interrupt_disable(I2C0, I2C_INT_ERR);
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i2c_interrupt_disable(I2C0, I2C_INT_EV);
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i2c_interrupt_disable(I2C0, I2C_INT_BUF);
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dma_parameter_struct dma_init_struct;
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i2c_interrupt_disable(I2C0, I2C_INT_ERR);
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i2c_interrupt_disable(I2C0, I2C_INT_EV);
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i2c_interrupt_disable(I2C0, I2C_INT_BUF);
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dma_parameter_struct dma_init_struct;
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uint8_t state = I2C_START;
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uint16_t timeout = 0;
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bool done = false;
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bool timedout = false;
|
||||
while (!(done || timedout)) {
|
||||
switch (state) {
|
||||
case I2C_START:
|
||||
/* i2c master sends start signal only when the bus is idle */
|
||||
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_start_on_bus(I2C0);
|
||||
timeout = 0;
|
||||
state = I2C_SEND_ADDRESS;
|
||||
} else {
|
||||
I2C_Unstick();
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
case I2C_SEND_ADDRESS:
|
||||
/* i2c master sends START signal successfully */
|
||||
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
|
||||
timeout = 0;
|
||||
state = I2C_CLEAR_ADDRESS_FLAG;
|
||||
} else {
|
||||
timedout = true;
|
||||
done = true;
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
case I2C_CLEAR_ADDRESS_FLAG:
|
||||
/* address flag set means i2c slave sends ACK */
|
||||
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
|
||||
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
// Address NACK'd
|
||||
unlock();
|
||||
return false;
|
||||
}
|
||||
}
|
||||
timeout = 0;
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
|
||||
state = I2C_TRANSMIT_DATA;
|
||||
} else {
|
||||
// Dont retry as this means a NAK
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
unlock();
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case I2C_TRANSMIT_DATA:
|
||||
/* wait until the transmit data buffer is empty */
|
||||
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
/* send the EEPROM's internal address to write to : only one byte
|
||||
* address */
|
||||
i2c_data_transmit(I2C0, MemAddress);
|
||||
timeout = 0;
|
||||
} else {
|
||||
timedout = true;
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
/* wait until BTC bit is set */
|
||||
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC))
|
||||
;
|
||||
dma_deinit(DMA0, DMA_CH5);
|
||||
dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
|
||||
dma_init_struct.memory_addr = (uint32_t)p_buffer;
|
||||
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
||||
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
|
||||
dma_init_struct.number = number_of_byte;
|
||||
dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0);
|
||||
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
||||
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
|
||||
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
||||
dma_init(DMA0, DMA_CH5, &dma_init_struct);
|
||||
/* enable I2C0 DMA */
|
||||
i2c_dma_enable(I2C0, I2C_DMA_ON);
|
||||
/* enable DMA0 channel5 */
|
||||
dma_channel_enable(DMA0, DMA_CH5);
|
||||
/* wait until BTC bit is set */
|
||||
while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {}
|
||||
/* wait until BTC bit is set */
|
||||
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) {}
|
||||
state = I2C_STOP;
|
||||
break;
|
||||
case I2C_STOP:
|
||||
/* send a stop condition to I2C bus */
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
timeout = 0;
|
||||
state = I2C_END;
|
||||
done = true;
|
||||
} else {
|
||||
timedout = true;
|
||||
done = true;
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
state = I2C_START;
|
||||
timeout = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
unlock();
|
||||
return timedout == false;
|
||||
uint8_t state = I2C_START;
|
||||
uint16_t timeout = 0;
|
||||
bool done = false;
|
||||
bool timedout = false;
|
||||
while (!(done || timedout)) {
|
||||
switch (state) {
|
||||
case I2C_START:
|
||||
/* i2c master sends start signal only when the bus is idle */
|
||||
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_start_on_bus(I2C0);
|
||||
timeout = 0;
|
||||
state = I2C_SEND_ADDRESS;
|
||||
} else {
|
||||
I2C_Unstick();
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
case I2C_SEND_ADDRESS:
|
||||
/* i2c master sends START signal successfully */
|
||||
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
|
||||
timeout = 0;
|
||||
state = I2C_CLEAR_ADDRESS_FLAG;
|
||||
} else {
|
||||
timedout = true;
|
||||
done = true;
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
case I2C_CLEAR_ADDRESS_FLAG:
|
||||
/* address flag set means i2c slave sends ACK */
|
||||
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
|
||||
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
// Address NACK'd
|
||||
unlock();
|
||||
return false;
|
||||
}
|
||||
}
|
||||
timeout = 0;
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
|
||||
state = I2C_TRANSMIT_DATA;
|
||||
} else {
|
||||
// Dont retry as this means a NAK
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
unlock();
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case I2C_TRANSMIT_DATA:
|
||||
/* wait until the transmit data buffer is empty */
|
||||
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
/* send the EEPROM's internal address to write to : only one byte
|
||||
* address */
|
||||
i2c_data_transmit(I2C0, MemAddress);
|
||||
timeout = 0;
|
||||
} else {
|
||||
timedout = true;
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
/* wait until BTC bit is set */
|
||||
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC))
|
||||
;
|
||||
dma_deinit(DMA0, DMA_CH5);
|
||||
dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
|
||||
dma_init_struct.memory_addr = (uint32_t) p_buffer;
|
||||
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
||||
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
|
||||
dma_init_struct.number = number_of_byte;
|
||||
dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0);
|
||||
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
||||
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
|
||||
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
||||
dma_init(DMA0, DMA_CH5, &dma_init_struct);
|
||||
/* enable I2C0 DMA */
|
||||
i2c_dma_enable(I2C0, I2C_DMA_ON);
|
||||
/* enable DMA0 channel5 */
|
||||
dma_channel_enable(DMA0, DMA_CH5);
|
||||
/* wait until BTC bit is set */
|
||||
while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {
|
||||
}
|
||||
/* wait until BTC bit is set */
|
||||
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) {
|
||||
}
|
||||
state = I2C_STOP;
|
||||
break;
|
||||
case I2C_STOP:
|
||||
/* send a stop condition to I2C bus */
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
timeout = 0;
|
||||
state = I2C_END;
|
||||
done = true;
|
||||
} else {
|
||||
timedout = true;
|
||||
done = true;
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
state = I2C_START;
|
||||
timeout = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
unlock();
|
||||
return timedout == false;
|
||||
}
|
||||
|
||||
bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) { return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1); }
|
||||
bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
|
||||
return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1);
|
||||
}
|
||||
|
||||
bool FRToSI2C::probe(uint16_t DevAddress) {
|
||||
uint8_t temp[1];
|
||||
return Mem_Read(DevAddress, 0x00, temp, sizeof(temp));
|
||||
uint8_t temp[1];
|
||||
return Mem_Read(DevAddress, 0x00, temp, sizeof(temp));
|
||||
}
|
||||
|
||||
void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
|
||||
void FRToSI2C::I2C_Unstick() {
|
||||
unstick_I2C();
|
||||
}
|
||||
|
||||
bool FRToSI2C::lock() {
|
||||
if (I2CSemaphore == nullptr) {
|
||||
return false;
|
||||
}
|
||||
return xSemaphoreTake(I2CSemaphore, TICKS_SECOND) == pdTRUE;
|
||||
if (I2CSemaphore == nullptr) {
|
||||
return false;
|
||||
}
|
||||
return xSemaphoreTake(I2CSemaphore, TICKS_SECOND) == pdTRUE;
|
||||
}
|
||||
|
||||
void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); }
|
||||
void FRToSI2C::unlock() {
|
||||
xSemaphoreGive(I2CSemaphore);
|
||||
}
|
||||
|
||||
bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) {
|
||||
for (int index = 0; index < registersLength; index++) {
|
||||
if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) {
|
||||
return false;
|
||||
}
|
||||
if (registers[index].pause_ms) {
|
||||
delay_ms(registers[index].pause_ms);
|
||||
}
|
||||
}
|
||||
return true;
|
||||
for (int index = 0; index < registersLength; index++) {
|
||||
if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) {
|
||||
return false;
|
||||
}
|
||||
if (registers[index].pause_ms) {
|
||||
delay_ms(registers[index].pause_ms);
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool FRToSI2C::wakePart(uint16_t DevAddress) {
|
||||
// wakepart is a special case where only the device address is sent
|
||||
if (!lock())
|
||||
return false;
|
||||
// wakepart is a special case where only the device address is sent
|
||||
if (!lock())
|
||||
return false;
|
||||
|
||||
i2c_interrupt_disable(I2C0, I2C_INT_ERR);
|
||||
i2c_interrupt_disable(I2C0, I2C_INT_EV);
|
||||
i2c_interrupt_disable(I2C0, I2C_INT_BUF);
|
||||
i2c_interrupt_disable(I2C0, I2C_INT_ERR);
|
||||
i2c_interrupt_disable(I2C0, I2C_INT_EV);
|
||||
i2c_interrupt_disable(I2C0, I2C_INT_BUF);
|
||||
|
||||
uint8_t state = I2C_START;
|
||||
uint16_t timeout = 0;
|
||||
bool done = false;
|
||||
bool timedout = false;
|
||||
while (!(done || timedout)) {
|
||||
switch (state) {
|
||||
case I2C_START:
|
||||
/* i2c master sends start signal only when the bus is idle */
|
||||
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_start_on_bus(I2C0);
|
||||
timeout = 0;
|
||||
state = I2C_SEND_ADDRESS;
|
||||
} else {
|
||||
I2C_Unstick();
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
case I2C_SEND_ADDRESS:
|
||||
/* i2c master sends START signal successfully */
|
||||
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
|
||||
timeout = 0;
|
||||
state = I2C_CLEAR_ADDRESS_FLAG;
|
||||
} else {
|
||||
timedout = true;
|
||||
done = true;
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
case I2C_CLEAR_ADDRESS_FLAG:
|
||||
/* address flag set means i2c slave sends ACK */
|
||||
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
|
||||
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
// Address NACK'd
|
||||
unlock();
|
||||
return false;
|
||||
}
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
|
||||
timeout = 0;
|
||||
state = I2C_STOP;
|
||||
} else {
|
||||
// Dont retry as this means a NAK
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
unlock();
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
uint8_t state = I2C_START;
|
||||
uint16_t timeout = 0;
|
||||
bool done = false;
|
||||
bool timedout = false;
|
||||
while (!(done || timedout)) {
|
||||
switch (state) {
|
||||
case I2C_START:
|
||||
/* i2c master sends start signal only when the bus is idle */
|
||||
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_start_on_bus(I2C0);
|
||||
timeout = 0;
|
||||
state = I2C_SEND_ADDRESS;
|
||||
} else {
|
||||
I2C_Unstick();
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
case I2C_SEND_ADDRESS:
|
||||
/* i2c master sends START signal successfully */
|
||||
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
|
||||
timeout = 0;
|
||||
state = I2C_CLEAR_ADDRESS_FLAG;
|
||||
} else {
|
||||
timedout = true;
|
||||
done = true;
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
case I2C_CLEAR_ADDRESS_FLAG:
|
||||
/* address flag set means i2c slave sends ACK */
|
||||
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
|
||||
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
// Address NACK'd
|
||||
unlock();
|
||||
return false;
|
||||
}
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
|
||||
timeout = 0;
|
||||
state = I2C_STOP;
|
||||
} else {
|
||||
// Dont retry as this means a NAK
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
unlock();
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
|
||||
case I2C_STOP:
|
||||
/* send a stop condition to I2C bus */
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
timeout = 0;
|
||||
state = I2C_END;
|
||||
done = true;
|
||||
} else {
|
||||
timedout = true;
|
||||
done = true;
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
state = I2C_START;
|
||||
timeout = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
unlock();
|
||||
return timedout == false;
|
||||
}
|
||||
|
||||
void I2C_EV_IRQ() {
|
||||
|
||||
}
|
||||
void I2C_ER_IRQ() {
|
||||
//Error callbacks
|
||||
|
||||
case I2C_STOP:
|
||||
/* send a stop condition to I2C bus */
|
||||
i2c_stop_on_bus(I2C0);
|
||||
/* i2c master sends STOP signal successfully */
|
||||
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
||||
timeout++;
|
||||
}
|
||||
if (timeout < I2C_TIME_OUT) {
|
||||
timeout = 0;
|
||||
state = I2C_END;
|
||||
done = true;
|
||||
} else {
|
||||
timedout = true;
|
||||
done = true;
|
||||
timeout = 0;
|
||||
state = I2C_START;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
state = I2C_START;
|
||||
timeout = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
unlock();
|
||||
return timedout == false;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user