Rework writes to use the new states
This commit is contained in:
Ben V. Brown
@@ -31,7 +31,7 @@ enum i2c_step {
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Write_device_address, //start sent, send device address
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Write_device_address, //start sent, send device address
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Write_device_memory_address, //device address sent, write the memory location
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Write_device_memory_address, //device address sent, write the memory location
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Write_device_data_start, // Write all of the remaining data using DMA
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Write_device_data_start, // Write all of the remaining data using DMA
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Write_device_data_wait, // Write all of the remaining data using DMA
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Write_device_data_finish, // Write all of the remaining data using DMA
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Read_start, //second read
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Read_start, //second read
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Read_device_address, // Send device address again for the read
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Read_device_address, // Send device address again for the read
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@@ -208,143 +208,115 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
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i2c_interrupt_disable(I2C0, I2C_INT_ERR);
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i2c_interrupt_disable(I2C0, I2C_INT_ERR);
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i2c_interrupt_disable(I2C0, I2C_INT_EV);
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i2c_interrupt_disable(I2C0, I2C_INT_EV);
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i2c_interrupt_disable(I2C0, I2C_INT_BUF);
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i2c_interrupt_disable(I2C0, I2C_INT_BUF);
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dma_parameter_struct dma_init_struct;
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dma_deinit(DMA0, DMA_CH5);
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currentState.dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
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uint8_t state = I2C_START;
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currentState.dma_init_struct.memory_addr = (uint32_t) p_buffer;
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uint16_t timeout = 0;
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currentState.dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
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bool done = false;
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currentState.dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
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bool timedout = false;
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currentState.dma_init_struct.number = number_of_byte;
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while (!(done || timedout)) {
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currentState.dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0);
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switch (state) {
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currentState.dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
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case I2C_START:
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currentState.dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
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/* i2c master sends start signal only when the bus is idle */
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currentState.dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
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while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT )) {
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dma_init(DMA0, DMA_CH5, (dma_parameter_struct*) ¤tState.dma_init_struct);
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timeout++;
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currentState.currentStep = Write_start;
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}
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TickType_t timeout = xTaskGetTickCount() + TICKS_SECOND;
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if (timeout < I2C_TIME_OUT) {
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while ((currentState.currentStep != Done) && (currentState.currentStep != Error_occured)) {
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i2c_start_on_bus(I2C0);
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if (xTaskGetTickCount() > timeout) {
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timeout = 0;
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state = I2C_SEND_ADDRESS;
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} else {
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I2C_Unstick();
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timeout = 0;
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state = I2C_START;
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}
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break;
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case I2C_SEND_ADDRESS:
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/* i2c master sends START signal successfully */
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while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT )) {
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timeout++;
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}
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if (timeout < I2C_TIME_OUT) {
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i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
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timeout = 0;
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state = I2C_CLEAR_ADDRESS_FLAG;
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} else {
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timedout = true;
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done = true;
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timeout = 0;
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state = I2C_START;
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}
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break;
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case I2C_CLEAR_ADDRESS_FLAG:
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/* address flag set means i2c slave sends ACK */
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while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT )) {
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timeout++;
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if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
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i2c_flag_clear(I2C0, I2C_FLAG_AERR);
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i2c_stop_on_bus(I2C0);
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/* i2c master sends STOP signal successfully */
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while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
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timeout++;
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}
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// Address NACK'd
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unlock();
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return false;
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}
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}
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timeout = 0;
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if (timeout < I2C_TIME_OUT) {
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i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
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state = I2C_TRANSMIT_DATA;
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} else {
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// Dont retry as this means a NAK
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i2c_stop_on_bus(I2C0);
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/* i2c master sends STOP signal successfully */
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while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
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timeout++;
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}
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unlock();
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return false;
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}
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break;
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case I2C_TRANSMIT_DATA:
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/* wait until the transmit data buffer is empty */
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while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT )) {
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timeout++;
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}
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if (timeout < I2C_TIME_OUT) {
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/* send the EEPROM's internal address to write to : only one byte
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* address */
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i2c_data_transmit(I2C0, MemAddress);
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timeout = 0;
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} else {
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timedout = true;
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timeout = 0;
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state = I2C_START;
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}
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/* wait until BTC bit is set */
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while (!i2c_flag_get(I2C0, I2C_FLAG_BTC))
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;
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dma_deinit(DMA0, DMA_CH5);
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dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
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dma_init_struct.memory_addr = (uint32_t) p_buffer;
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dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
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dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
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dma_init_struct.number = number_of_byte;
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dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0);
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dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
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dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
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dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
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dma_init(DMA0, DMA_CH5, &dma_init_struct);
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/* enable I2C0 DMA */
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i2c_dma_enable(I2C0, I2C_DMA_ON);
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/* enable DMA0 channel5 */
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dma_channel_enable(DMA0, DMA_CH5);
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/* wait until BTC bit is set */
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while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {
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}
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/* wait until BTC bit is set */
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while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) {
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}
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state = I2C_STOP;
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break;
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case I2C_STOP:
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/* send a stop condition to I2C bus */
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i2c_stop_on_bus(I2C0);
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i2c_stop_on_bus(I2C0);
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/* i2c master sends STOP signal successfully */
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I2C_Unstick();
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while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
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unlock();
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timeout++;
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return false;
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}
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switch (currentState.currentStep) {
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case Error_occured:
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i2c_stop_on_bus(I2C0);
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I2C_Unstick();
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unlock();
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return false;
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break;
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case Write_start:
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/* disable I2C0 */
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i2c_disable(I2C0);
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/* enable I2C0 */
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i2c_enable(I2C0);
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/* enable acknowledge */
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i2c_ack_config(I2C0, I2C_ACK_ENABLE);
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/* i2c master sends start signal only when the bus is idle */
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if (!i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)) {
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/* send the start signal */
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i2c_start_on_bus(I2C0);
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currentState.currentStep = Write_device_address;
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}
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}
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if (timeout < I2C_TIME_OUT) {
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break;
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timeout = 0;
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case Write_device_address:
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state = I2C_END;
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/* i2c master sends START signal successfully */
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done = true;
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if (i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) {
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} else {
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i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
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timedout = true;
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currentState.currentStep = Write_device_memory_address;
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done = true;
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}
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timeout = 0;
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break;
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state = I2C_START;
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case Write_device_memory_address:
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//Send the device memory location
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if (i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) { //addr sent
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if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
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//Arb error - we lost the bus / nacked
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currentState.currentStep = Error_occured;
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}
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if (i2c_flag_get(I2C0, I2C_FLAG_TBE)) {
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i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
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// Write out the 8 byte address
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i2c_data_transmit(I2C0, MemAddress);
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currentState.currentStep = Write_device_data_start;
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}
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}
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break;
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case Write_device_data_start:
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/* wait until BTC bit is set */
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if (i2c_flag_get(I2C0, I2C_FLAG_BTC)) {
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/* enable I2C0 DMA */
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i2c_dma_enable(I2C0, I2C_DMA_ON);
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/* enable DMA0 channel5 */
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dma_channel_enable(DMA0, DMA_CH5);
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currentState.currentStep = Write_device_data_finish;
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}
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break;
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case Write_device_data_finish: //Wait for complete then goto stop
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/* wait until BTC bit is set */
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if (dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {
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/* wait until BTC bit is set */
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if (i2c_flag_get(I2C0, I2C_FLAG_BTC)) {
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currentState.currentStep = Send_stop;
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}
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}
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break;
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case Send_stop:
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/* send a stop condition to I2C bus*/
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i2c_stop_on_bus(I2C0);
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currentState.currentStep = Wait_stop;
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break;
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case Wait_stop:
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/* i2c master sends STOP signal successfully */
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if ((I2C_CTL0(I2C0) & 0x0200) != 0x0200) {
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currentState.currentStep = Done;
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}
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}
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break;
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break;
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default:
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default:
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state = I2C_START;
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//If we get here something is amiss
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timeout = 0;
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unlock();
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break;
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return false;
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}
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}
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}
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}
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unlock();
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unlock();
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return timedout == false;
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return true;
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}
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}
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bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
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bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
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