Starting the roughout
This commit is contained in:
Ben V. Brown
40
workspace/TS100/Core/Drivers/FUSB302/FUSB302.hpp
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40
workspace/TS100/Core/Drivers/FUSB302/FUSB302.hpp
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/*
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* FUSB302.hpp
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*
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* Created on: 11-06-2020
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* Author: Ralim
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*/
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#ifndef FUSB302_H_
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#define FUSB302_H_
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#include "BSP.h"
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#include "FUSB302_includes.h"
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#include "I2C_Wrapper.hpp"
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//While the ST4500 is nice, the FUSB302 is _cheap_ so its what is used in the TS80P for example
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class FUSB302 {
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public:
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//Returns true if the FUSB302 is detected on the I2C bus
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bool detect();
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private:
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// Bring up out of reset and clear fifo's
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void fusb302_reset();
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void flush_rx_fifo();
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void flush_tx_fifo();
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void enable_auto_good_crc();
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int set_rp_value(int rp);
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int set_cc(int pull);
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struct fusb302_chip_state {
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int cc_polarity;
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int vconn_enabled;
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/* 1 = pulling up (DFP) 0 = pulling down (UFP) */
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int pulling_up;
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int rx_enable;
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uint8_t mdac_vnc;
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uint8_t mdac_rd;
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};
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fusb302_chip_state state;
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};
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#endif /* LIS2DH12_HPP_ */
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204
workspace/TS100/Core/Drivers/FUSB302/FUSB302_includes.h
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204
workspace/TS100/Core/Drivers/FUSB302/FUSB302_includes.h
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#ifndef FUSB302_INCLUDES_H_
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#define FUSB302_INCLUDES_H_
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/* Whole bunch of includes to make working with the FUSB302 easier*/
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/* Chip Device ID - 302A or 302B */
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#define fusb302_DEVID_302A 0x08
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#define fusb302_DEVID_302B 0x09
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/* I2C slave address varies by part number */
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/* FUSB302BUCX / FUSB302BMPX */
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#define fusb302_I2C_SLAVE_ADDR 0x22 // 7-bit address for Arduino
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/* FUSB302B01MPX */
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#define fusb302_I2C_SLAVE_ADDR_B01 0x23
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/* FUSB302B10MPX */
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#define fusb302_I2C_SLAVE_ADDR_B10 0x24
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/* FUSB302B11MPX */
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#define fusb302_I2C_SLAVE_ADDR_B11 0x25
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/* Default retry count for transmitting */
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#define PD_RETRY_COUNT 3
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/* Time to wait for TCPC to complete transmit */
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#define PD_T_TCPC_TX_TIMEOUT (100 * MSEC)
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#define TCPC_REG_DEVICE_ID 0x01
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#define TCPC_REG_SWITCHES0 0x02
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#define TCPC_REG_SWITCHES0_CC2_PU_EN (1 << 7)
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#define TCPC_REG_SWITCHES0_CC1_PU_EN (1 << 6)
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#define TCPC_REG_SWITCHES0_VCONN_CC2 (1 << 5)
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#define TCPC_REG_SWITCHES0_VCONN_CC1 (1 << 4)
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#define TCPC_REG_SWITCHES0_MEAS_CC2 (1 << 3)
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#define TCPC_REG_SWITCHES0_MEAS_CC1 (1 << 2)
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#define TCPC_REG_SWITCHES0_CC2_PD_EN (1 << 1)
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#define TCPC_REG_SWITCHES0_CC1_PD_EN (1 << 0)
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#define TCPC_REG_SWITCHES1 0x03
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#define TCPC_REG_SWITCHES1_POWERROLE (1 << 7)
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#define TCPC_REG_SWITCHES1_SPECREV1 (1 << 6)
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#define TCPC_REG_SWITCHES1_SPECREV0 (1 << 5)
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#define TCPC_REG_SWITCHES1_DATAROLE (1 << 4)
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#define TCPC_REG_SWITCHES1_AUTO_GCRC (1 << 2)
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#define TCPC_REG_SWITCHES1_TXCC2_EN (1 << 1)
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#define TCPC_REG_SWITCHES1_TXCC1_EN (1 << 0)
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#define TCPC_REG_MEASURE 0x04
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#define TCPC_REG_MEASURE_VBUS (1 << 6)
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#define TCPC_REG_MEASURE_MDAC_MV(mv) (((mv) / 42) & 0x3f)
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#define TCPC_REG_CONTROL0 0x06
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#define TCPC_REG_CONTROL0_TX_FLUSH (1 << 6)
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#define TCPC_REG_CONTROL0_INT_MASK (1 << 5)
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#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3 << 2)
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#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3 << 2)
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#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2 << 2)
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#define TCPC_REG_CONTROL0_HOST_CUR_USB (1 << 2)
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#define TCPC_REG_CONTROL0_TX_START (1 << 0)
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#define TCPC_REG_CONTROL1 0x07
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#define TCPC_REG_CONTROL1_ENSOP2DB (1 << 6)
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#define TCPC_REG_CONTROL1_ENSOP1DB (1 << 5)
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#define TCPC_REG_CONTROL1_BIST_MODE2 (1 << 4)
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#define TCPC_REG_CONTROL1_RX_FLUSH (1 << 2)
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#define TCPC_REG_CONTROL1_ENSOP2 (1 << 1)
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#define TCPC_REG_CONTROL1_ENSOP1 (1 << 0)
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#define TCPC_REG_CONTROL2 0x08
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/* two-bit field, valid values below */
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#define TCPC_REG_CONTROL2_MODE (1 << 1)
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#define TCPC_REG_CONTROL2_MODE_DFP (0x3)
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#define TCPC_REG_CONTROL2_MODE_UFP (0x2)
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#define TCPC_REG_CONTROL2_MODE_DRP (0x1)
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#define TCPC_REG_CONTROL2_MODE_POS (1)
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#define TCPC_REG_CONTROL2_TOGGLE (1 << 0)
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#define TCPC_REG_CONTROL3 0x09
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#define TCPC_REG_CONTROL3_SEND_HARDRESET (1 << 6)
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#define TCPC_REG_CONTROL3_BIST_TMODE (1 << 5) /* 302B Only */
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#define TCPC_REG_CONTROL3_AUTO_HARDRESET (1 << 4)
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#define TCPC_REG_CONTROL3_AUTO_SOFTRESET (1 << 3)
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/* two-bit field */
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#define TCPC_REG_CONTROL3_N_RETRIES (1 << 1)
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#define TCPC_REG_CONTROL3_N_RETRIES_POS (1)
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#define TCPC_REG_CONTROL3_N_RETRIES_SIZE (2)
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#define TCPC_REG_CONTROL3_AUTO_RETRY (1 << 0)
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#define TCPC_REG_MASK 0x0A
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#define TCPC_REG_MASK_VBUSOK (1 << 7)
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#define TCPC_REG_MASK_ACTIVITY (1 << 6)
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#define TCPC_REG_MASK_COMP_CHNG (1 << 5)
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#define TCPC_REG_MASK_CRC_CHK (1 << 4)
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#define TCPC_REG_MASK_ALERT (1 << 3)
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#define TCPC_REG_MASK_WAKE (1 << 2)
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#define TCPC_REG_MASK_COLLISION (1 << 1)
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#define TCPC_REG_MASK_BC_LVL (1 << 0)
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#define TCPC_REG_POWER 0x0B
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#define TCPC_REG_POWER_PWR (1 << 0) /* four-bit field */
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#define TCPC_REG_POWER_PWR_LOW 0x1 /* Bandgap + Wake circuitry */
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#define TCPC_REG_POWER_PWR_MEDIUM 0x3 /* LOW + Receiver + Current refs */
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#define TCPC_REG_POWER_PWR_HIGH 0x7 /* MEDIUM + Measure block */
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#define TCPC_REG_POWER_PWR_ALL 0xF /* HIGH + Internal Oscillator */
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#define TCPC_REG_RESET 0x0C
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#define TCPC_REG_RESET_PD_RESET (1 << 1)
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#define TCPC_REG_RESET_SW_RESET (1 << 0)
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#define TCPC_REG_MASKA 0x0E
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#define TCPC_REG_MASKA_OCP_TEMP (1 << 7)
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#define TCPC_REG_MASKA_TOGDONE (1 << 6)
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#define TCPC_REG_MASKA_SOFTFAIL (1 << 5)
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#define TCPC_REG_MASKA_RETRYFAIL (1 << 4)
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#define TCPC_REG_MASKA_HARDSENT (1 << 3)
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#define TCPC_REG_MASKA_TX_SUCCESS (1 << 2)
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#define TCPC_REG_MASKA_SOFTRESET (1 << 1)
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#define TCPC_REG_MASKA_HARDRESET (1 << 0)
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#define TCPC_REG_MASKB 0x0F
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#define TCPC_REG_MASKB_GCRCSENT (1 << 0)
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#define TCPC_REG_STATUS0A 0x3C
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#define TCPC_REG_STATUS0A_SOFTFAIL (1 << 5)
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#define TCPC_REG_STATUS0A_RETRYFAIL (1 << 4)
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#define TCPC_REG_STATUS0A_POWER (1 << 2) /* two-bit field */
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#define TCPC_REG_STATUS0A_RX_SOFT_RESET (1 << 1)
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#define TCPC_REG_STATUS0A_RX_HARD_RESET (1 << 0)
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#define TCPC_REG_STATUS1A 0x3D
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/* three-bit field, valid values below */
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#define TCPC_REG_STATUS1A_TOGSS (1 << 3)
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#define TCPC_REG_STATUS1A_TOGSS_RUNNING 0x0
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#define TCPC_REG_STATUS1A_TOGSS_SRC1 0x1
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#define TCPC_REG_STATUS1A_TOGSS_SRC2 0x2
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#define TCPC_REG_STATUS1A_TOGSS_SNK1 0x5
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#define TCPC_REG_STATUS1A_TOGSS_SNK2 0x6
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#define TCPC_REG_STATUS1A_TOGSS_AA 0x7
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#define TCPC_REG_STATUS1A_TOGSS_POS (3)
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#define TCPC_REG_STATUS1A_TOGSS_MASK (0x7)
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#define TCPC_REG_STATUS1A_RXSOP2DB (1 << 2)
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#define TCPC_REG_STATUS1A_RXSOP1DB (1 << 1)
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#define TCPC_REG_STATUS1A_RXSOP (1 << 0)
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#define TCPC_REG_INTERRUPTA 0x3E
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#define TCPC_REG_INTERRUPTA_OCP_TEMP (1 << 7)
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#define TCPC_REG_INTERRUPTA_TOGDONE (1 << 6)
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#define TCPC_REG_INTERRUPTA_SOFTFAIL (1 << 5)
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#define TCPC_REG_INTERRUPTA_RETRYFAIL (1 << 4)
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#define TCPC_REG_INTERRUPTA_HARDSENT (1 << 3)
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#define TCPC_REG_INTERRUPTA_TX_SUCCESS (1 << 2)
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#define TCPC_REG_INTERRUPTA_SOFTRESET (1 << 1)
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#define TCPC_REG_INTERRUPTA_HARDRESET (1 << 0)
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#define TCPC_REG_INTERRUPTB 0x3F
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#define TCPC_REG_INTERRUPTB_GCRCSENT (1 << 0)
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#define TCPC_REG_STATUS0 0x40
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#define TCPC_REG_STATUS0_VBUSOK (1 << 7)
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#define TCPC_REG_STATUS0_ACTIVITY (1 << 6)
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#define TCPC_REG_STATUS0_COMP (1 << 5)
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#define TCPC_REG_STATUS0_CRC_CHK (1 << 4)
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#define TCPC_REG_STATUS0_ALERT (1 << 3)
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#define TCPC_REG_STATUS0_WAKE (1 << 2)
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#define TCPC_REG_STATUS0_BC_LVL1 (1 << 1) /* two-bit field */
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#define TCPC_REG_STATUS0_BC_LVL0 (1 << 0) /* two-bit field */
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#define TCPC_REG_STATUS1 0x41
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#define TCPC_REG_STATUS1_RXSOP2 (1 << 7)
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#define TCPC_REG_STATUS1_RXSOP1 (1 << 6)
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#define TCPC_REG_STATUS1_RX_EMPTY (1 << 5)
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#define TCPC_REG_STATUS1_RX_FULL (1 << 4)
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#define TCPC_REG_STATUS1_TX_EMPTY (1 << 3)
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#define TCPC_REG_STATUS1_TX_FULL (1 << 2)
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#define TCPC_REG_INTERRUPT 0x42
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#define TCPC_REG_INTERRUPT_VBUSOK (1 << 7)
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#define TCPC_REG_INTERRUPT_ACTIVITY (1 << 6)
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#define TCPC_REG_INTERRUPT_COMP_CHNG (1 << 5)
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#define TCPC_REG_INTERRUPT_CRC_CHK (1 << 4)
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#define TCPC_REG_INTERRUPT_ALERT (1 << 3)
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#define TCPC_REG_INTERRUPT_WAKE (1 << 2)
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#define TCPC_REG_INTERRUPT_COLLISION (1 << 1)
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#define TCPC_REG_INTERRUPT_BC_LVL (1 << 0)
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#define TCPC_REG_FIFOS 0x43
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/* Tokens defined for the FUSB302 TX FIFO */
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enum fusb302_txfifo_tokens {
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fusb302_TKN_TXON = 0xA1,
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fusb302_TKN_SYNC1 = 0x12,
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fusb302_TKN_SYNC2 = 0x13,
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fusb302_TKN_SYNC3 = 0x1B,
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fusb302_TKN_RST1 = 0x15,
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fusb302_TKN_RST2 = 0x16,
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fusb302_TKN_PACKSYM = 0x80,
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fusb302_TKN_JAMCRC = 0xFF,
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fusb302_TKN_EOP = 0x14,
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fusb302_TKN_TXOFF = 0xFE,
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};
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#define PACKET_IS_GOOD_CRC(head) (PD_HEADER_TYPE(head) == PD_CTRL_GOOD_CRC && \
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PD_HEADER_CNT(head) == 0)
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#endif
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