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Remove bl706

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This commit is contained in:
Ben V. Brown
2022-04-02 18:22:18 +11:00
parent 03a7cb4dd3
commit 66a4e05b74
193 changed files with 91 additions and 131600 deletions
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20
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl602_driver/std_drv/inc/bl602_mfg_flash.h Normal file
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@@ -0,0 +1,20 @@
#ifndef __BL602_MFG_FLASH_H__
#define __BL602_MFG_FLASH_H__
#include "stdint.h"
#include "bl602_sflash.h"
int8_t mfg_flash_init(SPI_Flash_Cfg_Type *flashCfg);
static int8_t mfg_flash_program(void);
static int8_t mfg_flash_read(void);
int8_t mfg_flash_write_xtal_capcode_pre(uint8_t capcode, uint8_t program);
void mfg_flash_write_xtal_capcode(void);
int8_t mfg_flash_read_xtal_capcode(uint8_t *capcode, uint8_t reload);
int8_t mfg_flash_write_poweroffset_pre(int8_t pwrOffset[14], uint8_t program);
void mfg_flash_write_poweroffset(void);
int8_t mfg_flash_read_poweroffset(int8_t pwrOffset[14], uint8_t reload);
int8_t mfg_flash_write_macaddr_pre(uint8_t mac[6], uint8_t program);
void mfg_flash_write_macaddr(void);
int8_t mfg_flash_read_macaddr(uint8_t mac[6], uint8_t reload);
#endif /*__MFG_GPIO_API_H__*/

5
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl602_driver/std_drv/src/bl602_mfg_media.c
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@@ -1,5 +1,6 @@
#include "bl602_mfg_media.h"
#include "bl602_mfg_efuse.h"
#include "bl602_mfg_flash.h
static uint8_t rf_para_on_flash = 0;
int8_t mfg_media_init_need_lock(SPI_Flash_Cfg_Type *flashCfg)
@@ -183,7 +184,7 @@ int8_t mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6], uint8_t program)
return ret;
}
void mfg_media_write_macaddr_need_lock(void)
int mfg_media_write_macaddr_need_lock(void)
{
if (rf_para_on_flash) {
return mfg_flash_write_macaddr();

64
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/CMakeLists.txt
View File

@@ -1,64 +0,0 @@
################# Add global include #################
list(APPEND ADD_INCLUDE
"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/inc"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/inc"
"${CMAKE_CURRENT_SOURCE_DIR}/regs"
"${CMAKE_CURRENT_SOURCE_DIR}/startup"
"${CMAKE_CURRENT_SOURCE_DIR}"
)
#######################################################
################# Add private include #################
list(APPEND ADD_PRIVATE_INCLUDE
"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/default_config"
)
#######################################################
############## Add current dir source files ###########
file(GLOB_RECURSE sources
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/*.c"
"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/src/*.c"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/interrupt.c"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/system_bl702.c"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/GCC/entry.S"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/GCC/start_load.c"
)
list(APPEND ADD_SRCS ${sources})
# aux_source_directory(src ADD_SRCS)
list(REMOVE_ITEM ADD_SRCS "${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_snflash.c"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_romdriver.c"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_clock.c"
)
#######################################################
########### Add required/dependent components #########
list(APPEND ADD_REQUIREMENTS common)
#######################################################
############ Add static libs ##########################
#list(APPEND ADD_STATIC_LIB "lib/libtest.a")
#######################################################
############ Add dynamic libs #########################
# list(APPEND ADD_DYNAMIC_LIB "lib/arch/v831/libmaix_nn.so"
# "lib/arch/v831/libmaix_cam.so"
# )
#######################################################
############ Add global compile option ################
#add components denpend on this component
if(CONFIG_ROMAPI)
list(APPEND ADD_DEFINITIONS -DBFLB_USE_ROM_DRIVER)
endif()
if(CONFIG_HALAPI)
list(APPEND ADD_DEFINITIONS -DBFLB_USE_HAL_DRIVER)
endif()
list(APPEND ADD_DEFINITIONS -DARCH_RISCV)
#######################################################
############ Add private compile option ################
#add compile option for this component that won't affect other modules
# list(APPEND ADD_PRIVATE_DEFINITIONS -DAAAAA=1)
#######################################################
generate_library()

235
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld
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@@ -1,235 +0,0 @@
/****************************************************************************************
* @file bl702_flash.ld
*
* @brief This file is the map file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2021
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
/* INPUT(-lc) */
/* link with the standard GCC library */
/* INPUT(-lgcc) */
/* configure the entry point */
ENTRY(_enter)
StackSize = 0x1000; /* 4KB */
MEMORY
{
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K
itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 16K
dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 16K
ram_memory (!rx) : ORIGIN = 0x4201C000, LENGTH = 80K
hbn_memory (rx) : ORIGIN = 0x40010000, LENGTH = 0xE00 /* hbn ram 4K used 3.5K*/
}
SECTIONS
{
PROVIDE(__metal_chicken_bit = 0);
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(.text.metal.init.enter))
KEEP (*(SORT_NONE(.init)))
/* section information for shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for usb desc */
. = ALIGN(4);
_usb_desc_start = .;
KEEP(*(usb_desc))
. = ALIGN(4);
_usb_desc_end = .;
*(.text)
*(.text.*)
/*put .rodata**/
*(EXCLUDE_FILE( *bl702_glb*.o* \
*bl702_pds*.o* \
*bl702_common*.o* \
*bl702_sf_cfg*.o* \
*bl702_sf_cfg_ext*.o* \
*bl702_sf_ctrl*.o* \
*bl702_sflash*.o* \
*bl702_sflash_ext*.o* \
*bl702_xip_sflash*.o* \
*bl702_xip_sflash_ext*.o* \
*bl702_ef_ctrl*.o*) .rodata*)
*(.srodata)
*(.srodata.*)
. = ALIGN(4);
__text_code_end__ = .;
} > xip_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl702_glb*.o*(.rodata*)
*bl702_pds*.o*(.rodata*)
*bl702_common*.o*(.rodata*)
*bl702_sf_cfg*.o*(.rodata*)
*bl702_sf_cfg_ext*.o*(.rodata*)
*bl702_sf_ctrl*.o*(.rodata*)
*bl702_sflash*.o*(.rodata*)
*bl702_sflash_ext*.o*(.rodata*)
*bl702_xip_sflash*.o*(.rodata*)
*bl702_xip_sflash_ext*.o*(.rodata*)
*bl702_ef_ctrl*.o*(.rodata*)
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__hbn_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.hbn_ram_region : AT (__hbn_load_addr)
{
. = ALIGN(4);
__hbn_ram_start__ = .;
*bl702_hbn_wakeup*.o*(.rodata*)
*(.hbn_ram_code*)
*(.hbn_ram_data)
. = ALIGN(4);
__hbn_ram_end__ = .;
} > hbn_memory
__dtcm_load_addr = __hbn_load_addr + SIZEOF(.hbn_ram_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
/* *finger_print.o(.data*) */
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
PROVIDE( __freertos_irq_stack_top = __StackTop);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__ram_data_end__ = .;
} > ram_memory
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.heap (NOLOAD):
{
. = ALIGN(4);
__HeapBase = .;
KEEP(*(.heap*))
. = ALIGN(4);
__HeapLimit = .;
} > ram_memory
PROVIDE (__heap_min_size = 0x400);
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
ASSERT((__HeapLimit - __HeapBase ) >= __heap_min_size, "heap size is too short.")
}

194
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/bl702_ram.ld
View File

@@ -1,194 +0,0 @@
/****************************************************************************************
* @file bl702_ram.ld
*
* @brief This file is the map file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2021
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
/* INPUT(-lc) */
/* link with the standard GCC library */
/* INPUT(-lgcc) */
/* configure the entry point */
ENTRY(_enter)
StackSize = 0x0400; /* 1KB */
MEMORY
{
itcm_memory (rx) : ORIGIN = 0x22010000, LENGTH = 32K
dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 32K
ram_memory (!rx) : ORIGIN = 0x42020000, LENGTH = 48K
hbn_memory (rx) : ORIGIN = 0x40010000, LENGTH = 4K /* hbn ram 4K*/
}
SECTIONS
{
PROVIDE(__metal_chicken_bit = 0);
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(.text.metal.init.enter))
KEEP (*(SORT_NONE(.init)))
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.srodata)
*(.srodata.*)
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
. = ALIGN(4);
__text_code_end__ = .;
} > itcm_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__hbn_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.hbn_ram_region : AT (__hbn_load_addr)
{
. = ALIGN(4);
__hbn_ram_start__ = .;
*(.hbn_ram_code)
*(.hbn_data)
. = ALIGN(4);
__hbn_ram_end__ = .;
} > hbn_memory
__dtcm_load_addr = __hbn_load_addr + SIZEOF(.hbn_ram_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__ram_data_end__ = .;
} > ram_memory
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.heap (NOLOAD):
{
. = ALIGN(4);
__HeapBase = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.heap*))
. = ALIGN(4);
__HeapLimit = .;
} > ram_memory
PROVIDE (__heap_min_size = 0x400);
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
ASSERT((__HeapLimit - __HeapBase ) >= __heap_min_size, "heap size is too short.")
}

196
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/blsp_boot2_iap_flash.ld
View File

@@ -1,196 +0,0 @@
/****************************************************************************************
* @file map.txt
*
* @brief This file is the map file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2018
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
INPUT(-lc)
/* link with the standard GCC library */
INPUT(-lgcc)
/* configure the entry point */
ENTRY(_enter)
StackSize = 0x1000; /* 4KB */
HeapSize = 0x0; /* 0KB */
PROVIDE(__boot2_pass_param_addr = 0x4202DC00);
MEMORY
{
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 64K
itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 16K
dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 4K
ram_memory (!rx) : ORIGIN = 0x42019000/*0x42020000*/, LENGTH = 88K
}
SECTIONS
{
PROVIDE(__metal_chicken_bit = 0);
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(.text.metal.init.enter))
KEEP (*(SORT_NONE(.init)))
/* section information for usb desc */
. = ALIGN(4);
_usb_desc_start = .;
KEEP(*(usb_desc))
. = ALIGN(4);
_usb_desc_end = .;
*(EXCLUDE_FILE ( *bl702_uart*.o* *hal_uart*.o* ) .text*)
*(.rodata)
*(.rodata.*)
*(.srodata)
*(.srodata.*)
. = ALIGN(4);
__text_code_end__ = .;
} > xip_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl702_romapi*.o*(.text)
*bl702_romapi*.o*(.text.*)
*bl702_romapi*.o*(.rodata)
*bl702_romapi*.o*(.rodata.*)
*bl702_romapi*.o*(.srodata)
*bl702_romapi*.o*(.srodata.*)
*bl702_uart*.o* (.text*)
*hal_uart*.o* (.text*)
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
/* *finger_print.o(.data*) */
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/* .heap_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of heap sections, and assign
* values to heap symbols later */
.heap_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + HeapSize;
. = ALIGN(0x4);
} > dtcm_memory
__HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize;
__HeapSize = HeapSize;
__HeapLimit = __HeapBase + __HeapSize;
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__HeapBase >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__ram_data_end__ = .;
} > ram_memory
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
}

11
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/cpu_flags.cmake
View File

@@ -1,11 +0,0 @@
SET(CPU_ARCH "RISCV")
SET(MCPU "riscv-e24")
SET(MARCH "rv32imafc")
SET(MABI "ilp32f")
list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI})
list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI})
SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl702_flash.ld)
SET(RAM_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl702_ram.ld)
SET(BOOT2_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/blsp_boot2_iap_flash.ld)

17
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/adc_config.h
View File

@@ -1,17 +0,0 @@
#ifndef _ADC_CONFIG_H
#define _ADC_CONFIG_H
#define ADC_DATA_WIDIH_12 (0)
#define ADC_V18_SELECT (2) /*!< ADC 1.8V select */
#define ADC_V11_SELECT (1) /*!< ADC 1.1V select */
#define ADC_PGA_VCM (0) /*!< ADC VCM value */
#define ADC_PGA_GAIN1 (0) /*!< PGA gain 1 */
#define ADC_PGA_GAIN2 (0) /*!< PGA gain 2 */
#define ADC_CHOP_MODE (2) /*!< ADC chop mode select */
#define ADC_BIAS_SELECT (0) /*!< ADC current form main bandgap or aon bandgap */
#define ADC_OFFSET_CALIB_EN (0) /*!< Offset calibration enable */
#define ADC_OFFSER_CALIB_VAL (0) /*!< Offset calibration value */
#endif

7
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/dac_config.h
View File

@@ -1,7 +0,0 @@
#ifndef _DAC_CONFIG_H
#define _DAC_CONFIG_H
#define DAC_REF_SEL (0)
#define DAC_EXT_REF_GPIO (7)
#endif

11
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2s_config.h
View File

@@ -1,11 +0,0 @@
#ifndef _I2S_CONFIG_H
#define _I2S_CONFIG_H
#define I2S_ADUIO_PLL_DEFAULT AUDIO_PLL_12288000_HZ
#define I2S_DATA_ENDIAN I2S_DATA_ENDIAN_MSB
#define I2S_MONO_CHANNEL I2S_RX_MONO_MODE_RIGHT_CHANNEL
#define I2S_LR_EXCHANGE DISABLE /*The position of L/R channel data within each entry is exchanged if enabled*/
#define I2S_FS_INVERT DISABLE
#define I2S_BCLK_INVERT DISABLE
#endif

16
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/uart_config.h
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@@ -1,16 +0,0 @@
#ifndef _UART_CONFIG_H
#define _UART_CONFIG_H
#define UART_CTS_FLOWCONTROL_ENABLE (0)
#define UART_RTS_FLOWCONTROL_ENABLE (0)
#define UART_RX_DEGLITCH_ENABLE (0)
#define UART_MSB_FIRST_ENABLE (0)
#define UART_TX_SWCONTROL_ENABLE (0)
#define UART_TX_LINMODE_ENABLE (0)
#define UART_RX_LINMODE_ENABLE (0)
#define UART_TX_BREAKBIT_CNT (0)
#define UART_FIFO_MAX_LEN 128
#define UART_DEFAULT_RTO_TIMEOUT 100
#endif

62
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_acomp.h
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@@ -1,62 +0,0 @@
#ifndef __HAL_ACOMP_H__
#define __HAL_ACOMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_common.h"
enum acomp_channel_type {
ACOMP_CHANNEL_ADC_CHANNEL0, /*!< Analog compare channel,ADC input channel 0 */
ACOMP_CHANNEL_ADC_CHANNEL1, /*!< Analog compare channel,ADC input channel 1 */
ACOMP_CHANNEL_ADC_CHANNEL2, /*!< Analog compare channel,ADC input channel 2 */
ACOMP_CHANNEL_ADC_CHANNEL3, /*!< Analog compare channel,ADC input channel 3 */
ACOMP_CHANNEL_ADC_CHANNEL4, /*!< Analog compare channel,ADC input channel 4 */
ACOMP_CHANNEL_ADC_CHANNEL5, /*!< Analog compare channel,ADC input channel 5 */
ACOMP_CHANNEL_ADC_CHANNEL6, /*!< Analog compare channel,ADC input channel 6 */
ACOMP_CHANNEL_ADC_CHANNEL7, /*!< Analog compare channel,ADC input channel 7 */
ACOMP_CHANNEL_DAC_CHANNELA, /*!< Analog compare channel,DAC output channel A */
ACOMP_CHANNEL_DAC_CHANNELB, /*!< Analog compare channel,DAC output channel B */
ACOMP_CHANNEL_VREF_1P2V, /*!< Analog compare channel,1.2V ref voltage */
ACOMP_CHANNEL_0P375VBAT, /*!< Analog compare channel,6/16Vbat */
ACOMP_CHANNEL_0P25VBAT, /*!< Analog compare channel,4/16Vbat */
ACOMP_CHANNEL_0P1875VBAT, /*!< Analog compare channel,3/16Vbat */
ACOMP_CHANNEL_0P3125VBAT, /*!< Analog compare channel,5/16Vbat */
ACOMP_CHANNEL_VSS, /*!< Analog compare channel,vss */
};
enum acomp_hysteresis_vol_type {
ACOMP_HYSTERESIS_VOLT_NONE, /*!< Analog compare hysteresis voltage none */
ACOMP_HYSTERESIS_VOLT_10MV, /*!< Analog compare hysteresis voltage 10mv */
ACOMP_HYSTERESIS_VOLT_20MV, /*!< Analog compare hysteresis voltage 20mv */
ACOMP_HYSTERESIS_VOLT_30MV, /*!< Analog compare hysteresis voltage 30mv */
ACOMP_HYSTERESIS_VOLT_40MV, /*!< Analog compare hysteresis voltage 40mv */
ACOMP_HYSTERESIS_VOLT_50MV, /*!< Analog compare hysteresis voltage 50mv */
ACOMP_HYSTERESIS_VOLT_60MV, /*!< Analog compare hysteresis voltage 60mv */
ACOMP_HYSTERESIS_VOLT_70MV, /*!< Analog compare hysteresis voltage 70mv */
};
enum acomp_it_type {
ACOMP_POSITIVE_IT = 1 << 0,
ACOMP_NEGATIVE_IT = 1 << 1,
};
typedef struct acomp_device {
enum acomp_channel_type pos_ch;
enum acomp_channel_type neg_ch;
enum acomp_hysteresis_vol_type pos_hysteresis_vol;
enum acomp_hysteresis_vol_type neg_hysteresis_vol;
} acomp_device_t;
void acomp_init(uint8_t idx,acomp_device_t *device);
void acomp_enable(uint8_t idx);
void acomp_disable(uint8_t idx);
void acomp_interrupt_mask(uint8_t idx,uint32_t flag);
void acomp_interrupt_unmask(uint8_t idx,uint32_t flag);
int acomp_get_result(uint8_t idx);
#ifdef __cplusplus
}
#endif
#endif

185
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_adc.h
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@@ -1,185 +0,0 @@
/**
* @file hal_adc.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_ADC__H__
#define __HAL_ADC__H__
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_ADC_CHANNEL_START 0x10
#define DEVICE_CTRL_ADC_CHANNEL_STOP 0x11
#define DEVICE_CTRL_ADC_CHANNEL_CONFIG 0x12
#define DEVICE_CTRL_ADC_VBAT_ON 0x13
#define DEVICE_CTRL_ADC_VBAT_OFF 0x14
#define DEVICE_CTRL_ADC_TSEN_ON 0x15
#define DEVICE_CTRL_ADC_TSEN_OFF 0x16
#define DEVICE_CTRL_ADC_DATA_PARSE 0x17
enum adc_index_type {
#ifdef BSP_USING_ADC0
ADC0_INDEX,
#endif
ADC_MAX_INDEX
};
#define adc_channel_start(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL)
#define adc_channel_stop(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_STOP, NULL)
#define adc_channel_config(dev, list) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_CONFIG, list)
typedef enum {
ADC_CHANNEL0, /* ADC channel 0 */
ADC_CHANNEL1, /* ADC channel 1 */
ADC_CHANNEL2, /* ADC channel 2 */
ADC_CHANNEL3, /* ADC channel 3 */
ADC_CHANNEL4, /* ADC channel 4 */
ADC_CHANNEL5, /* ADC channel 5 */
ADC_CHANNEL6, /* ADC channel 6 */
ADC_CHANNEL7, /* ADC channel 7 */
ADC_CHANNEL8, /* ADC channel 8 */
ADC_CHANNEL9, /* ADC channel 9 */
ADC_CHANNEL10, /* ADC channel 10 */
ADC_CHANNEL11, /* ADC channel 11 */
ADC_CHANNEL_DAC_OUTA, /* DACA, ADC channel 12 */
ADC_CHANNEL_DAC_OUTB, /* DACB, ADC channel 13 */
ADC_CHANNEL_TSEN_P, /* TSenp, ADC channel 14 */
ADC_CHANNEL_TSEN_N, /* TSenn, ADC channel 15 */
ADC_CHANNEL_VREF, /* Vref, ADC channel 16 */
ADC_CHANNEL_DCTEST, /* DCTest, ADC channel 17 */
ADC_CHANNEL_VABT_HALF, /* VBAT/2, ADC channel 18 */
ADC_CHANNEL_SENP3, /* SenVP3, ADC channel 19 */
ADC_CHANNEL_SENP2, /* SenVP2, ADC channel 20 */
ADC_CHANNEL_SENP1, /* SenVP1, ADC channel 21 */
ADC_CHANNEL_SENP0, /* SenVP0, ADC channel 22 */
ADC_CHANNEL_GND, /* GND, ADC channel 23 */
} adc_channel_t;
typedef enum {
ADC_CLOCK_DIV_1, /*!< ADC clock:on 32M clock is 32M */
ADC_CLOCK_DIV_4, /*!< ADC clock:on 32M clock is 8M */
ADC_CLOCK_DIV_8, /*!< ADC clock:on 32M clock is 4M */
ADC_CLOCK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */
ADC_CLOCK_DIV_16, /*!< ADC clock:on 32M clock is 2M */
ADC_CLOCK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */
ADC_CLOCK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */
ADC_CLOCK_DIV_32, /*!< ADC clock:on 32M clock is 1M */
} adc_clk_div_t;
typedef enum {
ADC_VREF_3V2 = 0, /* ADC select 3.2V as reference voltage */
ADC_VREF_2V = 1, /* ADC select 2V as reference voltage */
} adc_vref_t;
/**
* @brief ADC data width type definition
*/
typedef enum {
ADC_DATA_WIDTH_12B, /*!< ADC 12 bits */
ADC_DATA_WIDTH_14B_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */
ADC_DATA_WIDTH_14B_WITH_64_AVERAGE, /*!< ADC 14 bits,and the value is average of 64 converts */
ADC_DATA_WIDTH_16B_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */
ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */
} adc_data_width_t;
/**
* @brief ADC FIFO threshold type definition
*/
typedef enum {
ADC_FIFO_THRESHOLD_1BYTE, /*!< ADC FIFO threshold is 1 */
ADC_FIFO_THRESHOLD_4BYTE, /*!< ADC FIFO threshold is 4 */
ADC_FIFO_THRESHOLD_8BYTE, /*!< ADC FIFO threshold is 8 */
ADC_FIFO_THRESHOLD_16BYTE, /*!< ADC FIFO threshold is 16 */
} adc_fifo_threshold_t;
/**
* @brief ADC PGA gain type definition
*/
typedef enum {
ADC_GAIN_NONE, /*!< No PGA gain */
ADC_GAIN_1, /*!< PGA gain 1 */
ADC_GAIN_2, /*!< PGA gain 2 */
ADC_GAIN_4, /*!< PGA gain 4 */
ADC_GAIN_8, /*!< PGA gain 8 */
ADC_GAIN_16, /*!< PGA gain 16 */
ADC_GAIN_32, /*!< PGA gain 32 */
} adc_pga_gain_t;
enum adc_event_type {
ADC_EVENT_UNDERRUN,
ADC_EVENT_OVERRUN,
ADC_EVENT_FIFO,
ADC_EVENT_UNKNOWN
};
enum adc_it_type {
ADC_UNDERRUN_IT = 1 << 2,
ADC_OVERRUN_IT = 1 << 3,
ADC_FIFO_IT = 1 << 5,
};
typedef struct {
uint8_t *pos_channel;
uint8_t *neg_channel;
uint8_t num;
} adc_channel_cfg_t;
typedef struct {
int8_t posChan; /*!< Positive channel */
int8_t negChan; /*!< Negative channel */
uint16_t value; /*!< ADC value */
float volt; /*!< ADC voltage result */
} adc_channel_val_t;
typedef struct
{
uint32_t *input;
adc_channel_val_t *output;
uint32_t num;
} adc_data_parse_t;
typedef struct adc_device {
struct device parent;
adc_clk_div_t clk_div; /* CLK is not more than 2Mhz */
adc_vref_t vref; /* ADC voltage reference*/
bool continuous_conv_mode; /** conversion mode: shot conversion mode or continuous conversion mode. */
bool differential_mode; /** Channel type: single-ended or differential. */
adc_data_width_t data_width;
adc_fifo_threshold_t fifo_threshold;
adc_pga_gain_t gain;
void *rx_dma;
} adc_device_t;
#define ADC_DEV(dev) ((adc_device_t *)dev)
int adc_register(enum adc_index_type index, const char *name);
int adc_trim_tsen(uint16_t *tsen_offset);
float adc_get_tsen(uint16_t tsen_offset);
#ifdef __cplusplus
}
#endif
#endif

273
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_boot2.h
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@@ -1,273 +0,0 @@
/**
* *****************************************************************************
* @file hal_boot2_custom.h
* @version 0.1
* @date 2021-07-17
* @brief
* *****************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* *****************************************************************************
*/
#ifndef __HAL_BOOT2_H__
#define __HAL_BOOT2_H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "bl702_sflash.h"
#include "bl702_glb.h"
#define BL_TCM_BASE BL702_TCM_BASE
#define BL_SYS_CLK_PLL GLB_SYS_CLK_DLL144M
#define BL_SFLASH_CLK GLB_SFLASH_CLK_72M
#define HAL_PLL_CFG_MAGICCODE "PCFG"
#define HAL_BOOT2_PK_HASH_SIZE 256 / 8
#define HAL_BOOT2_IMG_HASH_SIZE 256 / 8
#define HAL_BOOT2_ECC_KEYXSIZE 256 / 8
#define HAL_BOOT2_ECC_KEYYSIZE 256 / 8
#define HAL_BOOT2_SIGN_MAXSIZE (2048 / 8)
#define HAL_BOOT2_DEADBEEF_VAL 0xdeadbeef
#define HAL_BOOT2_CPU0_MAGIC "BFNP"
#define HAL_BOOT2_CPU1_MAGIC "BFAP"
#define HAL_BOOT2_CP_FLAG 0x02
#define HAL_BOOT2_MP_FLAG 0x01
#define HAL_BOOT2_SP_FLAG 0x00
#define HAL_BOOT2_SUPPORT_DECOMPRESS 1 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_USB_IAP 0 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 1 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 0 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_CPU_GROUP_MAX 1
#define HAL_BOOT2_CPU_MAX 1
#define HAL_BOOT2_RAM_IMG_COUNT_MAX 0
#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER 4*1024
typedef struct
{
uint8_t encrypted[HAL_BOOT2_CPU_GROUP_MAX];
uint8_t sign[HAL_BOOT2_CPU_GROUP_MAX];
uint8_t hbn_check_sign;
uint8_t rsvd[1];
uint8_t chip_id[8];
uint8_t pk_hash_cpu0[HAL_BOOT2_PK_HASH_SIZE];
uint8_t pk_hash_cpu1[HAL_BOOT2_PK_HASH_SIZE];
uint8_t uart_download_cfg;
uint8_t sf_pin_cfg;
uint8_t keep_dbg_port_closed;
uint8_t boot_pin_cfg;
} boot2_efuse_hw_config;
struct __attribute__((packed, aligned(4))) hal_flash_config
{
uint32_t magicCode; /*'FCFG'*/
SPI_Flash_Cfg_Type cfg;
uint32_t crc32;
} ;
typedef struct
{
uint8_t xtal_type;
uint8_t pll_clk;
uint8_t hclk_div;
uint8_t bclk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t rsvd[2];
} hal_sys_clk_config;
typedef struct
{
uint32_t magicCode; /*'PCFG'*/
hal_sys_clk_config cfg;
uint32_t crc32;
} hal_pll_config;
struct __attribute__((packed, aligned(4))) hal_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t boot2_enable : 1; /* [9] boot2 enable */
uint32_t boot2_rollback : 1; /* [10] boot2 rollback */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t fpga_halt_release : 1; /* [31] FPGA halt release function */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[8]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) hal_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t image_address_offset; /* image address on flash */
uint32_t boot_entry; /* entry point of the m0 image */
uint32_t msp_val; /* msp value */
};
struct hal_bootheader_t
{
uint32_t magicCode; /*'BFXP'*/
uint32_t rivison;
struct hal_flash_config flash_cfg;
hal_pll_config clk_cfg;
__PACKED_UNION
{
__PACKED_STRUCT
{
uint32_t sign : 2; /* [1: 0] for sign*/
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface*/
uint32_t rsvd6_7 : 2; /* [7: 6] for encrypt*/
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t cache_enable : 1; /* [9] for cache */
uint32_t notLoadInBoot : 1; /* [10] not load this img in bootrom */
uint32_t aes_region_lock : 1; /* [11] aes region lock */
uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info*/
uint32_t crcIgnore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash crc */
uint32_t halt_cpu1 : 1; /* [18] halt ap */
uint32_t rsvd19_31 : 13; /* [31:19] rsvd */
}
bval;
uint32_t wval;
}
bootCfg;
__PACKED_UNION
{
uint32_t segment_cnt;
uint32_t img_len;
}
img_segment_info;
uint32_t bootEntry; /* entry point of the image*/
__PACKED_UNION
{
uint32_t ram_addr;
uint32_t flash_offset;
}
img_start;
uint8_t hash[HAL_BOOT2_IMG_HASH_SIZE]; /*hash of the image*/
uint32_t rsv1;
uint32_t rsv2;
uint32_t crc32;
} ;
typedef struct
{
uint8_t img_valid;
uint8_t pk_src;
uint8_t rsvd[2];
struct hal_basic_cfg_t basic_cfg;
struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX];
uint8_t aes_iv[16 + 4]; //iv in boot header
uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header
uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header
uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header
uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header
uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header
uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header
} boot2_image_config;
extern boot2_efuse_hw_config g_efuse_cfg;
extern uint8_t g_ps_mode;
extern uint32_t g_user_hash_ignored;
extern struct device *dev_check_hash;
uint32_t hal_boot2_custom(void);
void hal_boot2_reset_sec_eng(void);
void hal_boot2_sw_system_reset(void);
void hal_boot2_set_psmode_status(uint32_t flag);
uint32_t hal_boot2_get_psmode_status(void);
uint32_t hal_boot2_get_user_fw(void);
void hal_boot2_clr_user_fw(void);
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg);
int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg);
void hal_boot2_sboot_finish(void);
void hal_boot2_uart_gpio_init(void);
void hal_boot2_debug_uart_gpio_init(void);
#if HAL_BOOT2_SUPPORT_USB_IAP
void hal_boot2_debug_usb_port_init(void);
#endif
void hal_boot2_debug_uart_gpio_deinit(void);
int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data);
void hal_boot2_clean_cache(void);
BL_Err_Type hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg);
void hal_boot2_get_ram_img_cnt(char* img_name[],uint32_t *ram_img_cnt );
void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len,uint8_t **hash);
void hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr);
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr);
uint32_t hal_boot2_get_grp_count(void);
uint32_t hal_boot2_get_cpu_count(void);
uint32_t hal_boot2_get_feature_flag(void);
uint32_t hal_boot2_get_bootheader_offset(void);
#ifdef __cplusplus
}
#endif
#endif

112
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_cam.h
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@@ -1,112 +0,0 @@
/**
* @file hal_cam.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_CAM_H__
#define __HAL_CAM_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_CAM_FRAME_CUT 0x10
#define DEVICE_CTRL_CAM_FRAME_DROP 0x11
#define DEVICE_CTRL_CAM_FRAME_WRAP 0x12
enum cam_index_type {
#ifdef BSP_USING_CAM0
CAM0_INDEX,
#endif
CAM_MAX_INDEX
};
#define CAM_AUTO_MODE 0
#define CAM_MANUAL_MODE 1
#define CAM_FRAME_PLANAR_MODE 0
#define CAM_FRAME_INTERLEAVE_MODE 1
#define CAM_HSPOLARITY_LOW 0
#define CAM_HSPOLARITY_HIGH 1
#define CAM_VSPOLARITY_LOW 0
#define CAM_VSPOLARITY_HIGH 1
#define CAM_YUV_FORMAT_YUV422 0
#define CAM_YUV_FORMAT_YUV420_EVEN 1
#define CAM_YUV_FORMAT_YUV420_ODD 2
#define CAM_YUV_FORMAT_YUV400_EVEN 3
#define CAM_YUV_FORMAT_YUV400_ODD 4
enum cam_it_type {
CAM_FRAME_IT = 1 << 0,
};
enum cam_event_type {
CAM_EVENT_FRAME = 0,
};
typedef struct {
int16_t x0;
int16_t x1;
int16_t y0;
int16_t y1;
} cam_frame_area_t;
typedef struct {
uint32_t frame_addr;
uint32_t frame_count;
} cam_frame_info_t;
typedef struct cam_device {
struct device parent;
uint8_t id;
uint8_t software_mode;
uint8_t frame_mode;
uint8_t yuv_format;
uint8_t hsp;
uint8_t vsp;
uint32_t cam_write_ram_addr;
uint32_t cam_write_ram_size;
uint32_t cam_frame_size;
// planar mode need use:
uint32_t cam_write_ram_addr1;
uint32_t cam_write_ram_size1;
uint32_t cam_frame_size1;
} cam_device_t;
#define CAM_DEV(dev) ((cam_device_t *)dev)
int cam_register(enum cam_index_type index, const char *name);
void cam_drop_one_frame_interleave(void);
uint8_t cam_get_one_frame_interleave(uint8_t **pic, uint32_t *len);
#ifdef __cplusplus
}
#endif
#endif

95
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_clock.h
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@@ -1,95 +0,0 @@
/**
* @file hal_clock.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_CLOCK__H__
#define __HAL_CLOCK__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "bl702_config.h"
/*XTAL_TYPE*/
#define XTAL_NONE 0
#define EXTERNAL_XTAL_32M 1
#define INTERNAL_RC_32M 2
/*CLOCK_32K_XTAL*/
#define EXTERNAL_XTAL_32K 0
#define INTERNAL_RC_32K 1
/*BSP_ROOT_CLOCK_SOURCE*/
#if XTAL_TYPE != EXTERNAL_XTAL_32M
#define ROOT_CLOCK_SOURCE_XCLK 0
#else
#define ROOT_CLOCK_SOURCE_XCLK 1
#endif
#define ROOT_CLOCK_SOURCE_PLL_57P6M 2
#define ROOT_CLOCK_SOURCE_PLL_96M 3
#define ROOT_CLOCK_SOURCE_PLL_144M 4
/*BSP_XXX_CLOCK_SOURCE*/
#define ROOT_CLOCK_SOURCE_32K_CLK 5
#define ROOT_CLOCK_SOURCE_FCLK 6
#define ROOT_CLOCK_SOURCE_BCLK 7
#define ROOT_CLOCK_SOURCE_1K_CLK 8
/*BSP_AUDIO_PLL_CLOCK_SOURCE*/
#define ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ 9
#define ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ 10
#define ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ 11
#define ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ 12
#define ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ 13
enum system_clock_type {
SYSTEM_CLOCK_ROOT_CLOCK = 0, /* clock source before fclk_div*/
SYSTEM_CLOCK_FCLK, /* clock source after fclk_div*/
SYSTEM_CLOCK_BCLK, /* clock source after bclk_div*/
SYSTEM_CLOCK_XCLK, /* xtal clock*/
SYSTEM_CLOCK_32K_CLK,
SYSTEM_CLOCK_AUPLL,
};
enum peripheral_clock_type {
PERIPHERAL_CLOCK_UART = 0,
PERIPHERAL_CLOCK_SPI,
PERIPHERAL_CLOCK_I2C,
PERIPHERAL_CLOCK_ADC,
PERIPHERAL_CLOCK_DAC,
PERIPHERAL_CLOCK_I2S,
PERIPHERAL_CLOCK_PWM,
PERIPHERAL_CLOCK_CAM,
PERIPHERAL_CLOCK_TIMER0,
PERIPHERAL_CLOCK_TIMER1,
PERIPHERAL_CLOCK_WDT,
};
void system_clock_init(void);
void peripheral_clock_init(void);
uint32_t system_clock_get(enum system_clock_type type);
uint32_t peripheral_clock_get(enum peripheral_clock_type type);
void system_mtimer_clock_init(void);
void system_mtimer_clock_reinit(void);
#ifdef __cplusplus
}
#endif
#endif

46
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_common.h
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@@ -1,46 +0,0 @@
/**
* @file hal_common.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_COMMON__H__
#define __HAL_COMMON__H__
#ifdef __cplusplus
extern "C" {
#endif
#include "bl702_common.h"
void cpu_global_irq_enable(void);
void cpu_global_irq_disable(void);
void hal_por_reset(void);
void hal_system_reset(void);
void hal_cpu_reset(void);
void hal_get_chip_id(uint8_t chip_id[8]);
void hal_enter_usb_iap(void);
void hal_jump2app(uint32_t flash_offset);
int hal_get_trng_seed(void);
#ifdef __cplusplus
}
#endif
#endif

72
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dac.h
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@@ -1,72 +0,0 @@
/**
* @file hal_dac.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_DAC__H__
#define __HAL_DAC__H__
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
enum dac_index_type {
#ifdef BSP_USING_DAC0
DAC0_INDEX,
#endif
DAC_MAX_INDEX
};
#define DAC_CHANNEL_0 (1 << 0)
#define DAC_CHANNEL_1 (1 << 1)
#define DAC_CHANNEL_ALL (DAC_CHANNEL_0 | DAC_CHANNEL_1)
/* default a_rng and b_rng is 0x03*/
/*output Voltage = (1.8V-0.2V) * digital_val/1024 + 0.2V */
#define DAC_VREF_INTERNAL 0 /*0.2V~1.8V*/
/*output Voltage = (0.9vref-0.1vref) * digital_val/1024 + 0.1vref */
#define DAC_VREF_EXTERNAL 1 /*0.1vref~0.9vref,using gpio7 for GPIO_FUN_ADC*/
enum dac_sample_frequence {
DAC_SAMPLE_FREQ_8KHZ,
DAC_SAMPLE_FREQ_16KHZ,
DAC_SAMPLE_FREQ_44P1KHZ,
DAC_SAMPLE_FREQ_500KHZ,
};
typedef struct dac_device {
struct device parent;
enum dac_sample_frequence sample_freq;
uint8_t channels;
uint8_t vref;
void *tx_dma;
} dac_device_t;
#define DAC_DEV(dev) ((adc_device_t *)dev)
int dac_register(enum dac_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

190
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h
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@@ -1,190 +0,0 @@
/**
* @file hal_dma.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_DMA__H__
#define __HAL_DMA__H__
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_DMA_CHANNEL_GET_STATUS 0x10
#define DEVICE_CTRL_DMA_CHANNEL_START 0x11
#define DEVICE_CTRL_DMA_CHANNEL_STOP 0x12
#define DEVICE_CTRL_DMA_CHANNEL_UPDATE 0x13
#define DEVICE_CTRL_DMA_CONFIG_SI 0x14
#define DEVICE_CTRL_DMA_CONFIG_DI 0x15
enum dma_index_type {
#ifdef BSP_USING_DMA0_CH0
DMA0_CH0_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH1
DMA0_CH1_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH2
DMA0_CH2_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH3
DMA0_CH3_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH4
DMA0_CH4_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH5
DMA0_CH5_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH6
DMA0_CH6_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH7
DMA0_CH7_INDEX,
#endif
DMA_MAX_INDEX
};
#define dma_channel_start(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_START, NULL)
#define dma_channel_stop(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_STOP, NULL)
#define dma_channel_update(dev, list) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_UPDATE, list)
#define dma_channel_check_busy(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_GET_STATUS, NULL)
#define DMA_LLI_ONCE_MODE 0
#define DMA_LLI_CYCLE_MODE 1
#define DMA_ADDR_INCREMENT_DISABLE 0 /*!< Addr increment mode disable */
#define DMA_ADDR_INCREMENT_ENABLE 1 /*!< Addr increment mode enable */
#define DMA_TRANSFER_WIDTH_8BIT 0
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
#define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88)
#define DMA_ADDR_UART1_RDR (0x4000A100 + 0x8C)
#define DMA_ADDR_I2C_TDR (0x4000A300 + 0x88)
#define DMA_ADDR_I2C_RDR (0x4000A300 + 0x8C)
#define DMA_ADDR_SPI_TDR (0x4000A200 + 0x88)
#define DMA_ADDR_SPI_RDR (0x4000A200 + 0x8C)
#define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88)
#define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C)
#define DMA_ADDR_ADC_RDR (0x40002000 + 0x04)
#define DMA_ADDR_DAC_TDR (0x40002000 + 0X48)
#define DMA_REQUEST_NONE 0x00000000 /*!< DMA request peripheral:None */
#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX */
#define DMA_REQUEST_UART0_TX 0x00000001 /*!< DMA request peripheral:UART0 TX */
#define DMA_REQUEST_UART1_RX 0x00000002 /*!< DMA request peripheral:UART1 RX */
#define DMA_REQUEST_UART1_TX 0x00000003 /*!< DMA request peripheral:UART1 TX */
#define DMA_REQUEST_I2C0_RX 0x00000006 /*!< DMA request peripheral:I2C RX */
#define DMA_REQUEST_I2C0_TX 0x00000007 /*!< DMA request peripheral:I2C TX */
#define DMA_REQUEST_SPI0_RX 0x0000000A /*!< DMA request peripheral:SPI RX */
#define DMA_REQUEST_SPI0_TX 0x0000000B /*!< DMA request peripheral:SPI TX */
#define DMA_REQUEST_I2S_RX 0x00000014 /*!< DMA request peripheral:I2S RX */
#define DMA_REQUEST_I2S_TX 0x00000015 /*!< DMA request peripheral:I2S TX */
#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:ADC0 */
#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:DAC0 */
#define DMA_REQUEST_USB_EP0 0x00000018 /*!< DMA request peripheral:USB EP0*/
#define DMA_REQUEST_USB_EP1 0x00000019 /*!< DMA request peripheral:USB EP1*/
#define DMA_REQUEST_USB_EP2 0x0000001A /*!< DMA request peripheral:USB EP2*/
#define DMA_REQUEST_USB_EP3 0x0000001B /*!< DMA request peripheral:USB EP3*/
#define DMA_REQUEST_USB_EP4 0x0000001C /*!< DMA request peripheral:USB EP4*/
#define DMA_REQUEST_USB_EP5 0x0000001D /*!< DMA request peripheral:USB EP5*/
#define DMA_REQUEST_USB_EP6 0x0000001E /*!< DMA request peripheral:USB EP6*/
#define DMA_REQUEST_USB_EP7 0x0000001F /*!< DMA request peripheral:USB EP7 */
/**
* @brief DMA transfer direction type definition
*/
typedef enum {
DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer type:memory to memory */
DMA_MEMORY_TO_PERIPH, /*!< DMA transfer type:memory to peripheral */
DMA_PERIPH_TO_MEMORY, /*!< DMA transfer type:peripheral to memory */
DMA_PERIPH_TO_PERIPH, /*!< DMA transfer type:peripheral to peripheral */
} dma_transfer_dir_type;
typedef union {
struct
{
uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */
uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */
uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */
uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */
uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */
uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */
uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */
uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */
uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */
uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */
uint32_t SI : 1; /* [ 26], r/w, 0x1 */
uint32_t DI : 1; /* [ 27], r/w, 0x1 */
uint32_t Prot : 3; /* [30:28], r/w, 0x0 */
uint32_t I : 1; /* [ 31], r/w, 0x0 */
} bits;
uint32_t WORD;
} dma_control_data_t;
typedef struct
{
uint32_t src_addr;
uint32_t dst_addr;
uint32_t nextlli;
dma_control_data_t cfg;
} dma_lli_ctrl_t;
typedef struct dma_device {
struct device parent;
uint8_t id;
uint8_t ch;
uint8_t transfer_mode;
uint8_t direction;
uint32_t src_req;
uint32_t dst_req;
uint8_t src_addr_inc;
uint8_t dst_addr_inc;
uint8_t src_burst_size;
uint8_t dst_burst_size;
uint8_t src_width;
uint8_t dst_width;
dma_lli_ctrl_t *lli_cfg;
} dma_device_t;
#define DMA_DEV(dev) ((dma_device_t *)dev)
int dma_register(enum dma_index_type index, const char *name);
int dma_allocate_register(const char *name);
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size);
#ifdef __cplusplus
}
#endif
#endif

110
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_emac.h
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@@ -1,110 +0,0 @@
/**
* @file hal_emac.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_EMAC_H__
#define __HAL_EMAC_H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#include "bl702_emac.h"
typedef struct emac_device {
struct device parent;
uint8_t mac_addr[6]; /*!< mac address */
} emac_device_t;
/**
* @brief EMAC PHY configuration type definition
*/
typedef struct
{
uint8_t auto_negotiation; /*!< Speed and mode auto negotiation */
uint8_t full_duplex; /*!< Duplex mode */
#define PHY_STATE_DOWN (0) /* PHY is not usable */
#define PHY_STATE_READY (1) /* PHY is OK, wait for controller */
#define PHY_STATE_UP (2) /* Network is ready for TX/RX */
#define PHY_STATE_RUNNING (3) /* working */
#define PHY_STATE_NOLINK (4) /* no cable connected */
#define PHY_STATE_STOPPED (5) /* PHY has been stopped */
#define PHY_STATE_TESTING (6) /* in test mode */
uint8_t phy_state; /*!< down,ready,up,running,nolink,halted */
uint16_t speed; /*!< Speed mode */
uint16_t phy_address; /*!< PHY address */
uint32_t phy_id; /*!< PHY OUI */
} emac_phy_cfg_t;
#define FULL_PACKET (uint32_t)(-1)
#define NOFULL_PACKET (uint32_t)(0)
#ifndef ETH_TX_BUFFER_SIZE
#define ETH_TX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE)
#endif
#ifndef ETH_RX_BUFFER_SIZE
#define ETH_RX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE)
#endif
#define EMAC_TX_COMMON_FLAGS (EMAC_BD_FIELD_MSK(TX_RD) | \
EMAC_BD_FIELD_MSK(TX_IRQ) | \
EMAC_BD_FIELD_MSK(TX_PAD) | \
EMAC_BD_FIELD_MSK(TX_CRC))
#define EMAC_RX_COMMON_FLAGS (ETH_MAX_PACKET_SIZE << 16) | \
EMAC_BD_FIELD_MSK(RX_IRQ) )
typedef enum _BD_TYPE_ {
EMAC_BD_TYPE_INVLAID,
EMAC_BD_TYPE_TX,
EMAC_BD_TYPE_RX,
EMAC_BD_TYPE_NONE,
EMAC_BD_TYPE_MAX = 0x7FFFFFFF
} EMAC_BD_TYPE_e;
int emac_init(emac_device_t *emac_cfg);
int emac_bd_init(uint8_t *ethTxBuff, uint8_t txBufCount, uint8_t *ethRxBuff, uint8_t rxBufCount);
int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in);
int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out);
__WEAK void emac_rx_done_callback_app(void);
__WEAK void emac_rx_error_callback_app(void);
__WEAK void emac_rx_busy_callback_app(void);
__WEAK void emac_tx_error_callback_app(void);
__WEAK void emac_tx_done_callback_app(void);
int emac_phy_set_address(uint16_t phyAddress);
int emac_phy_config_full_duplex(uint8_t fullDuplex);
int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue);
int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue);
int emac_stop(void);
int emac_start(void);
int emac_start_tx(void);
int emac_stop_tx(void);
int emac_start_rx(void);
int emac_stop_rx(void);
#ifdef __cplusplus
}
#endif
#endif

50
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_flash.h
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@@ -1,50 +0,0 @@
/**
* @file hal_flash.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_FLASH__H__
#define __HAL_FLASH__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "bl702_sflash.h"
#include "bl702_sflash_ext.h"
#define FLASH_NOT_DETECT 0x10
#define BL_FLASH_XIP_BASE BL702_FLASH_XIP_BASE
uint32_t flash_get_jedecid(void);
BL_Err_Type flash_init(void);
BL_Err_Type flash_read_jedec_id(uint8_t *data);
BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_read(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_write(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_erase(uint32_t startaddr, uint32_t len);
BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len);
BL_Err_Type flash_write_protect_set(SFlash_Protect_Kh25v40_Type protect);
#ifdef __cplusplus
}
#endif
#endif

96
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h
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@@ -1,96 +0,0 @@
/**
* @file hal_gpio.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_GPIO__H__
#define __HAL_GPIO__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
enum gpio_pin_type {
GPIO_PIN_0 = 0,
GPIO_PIN_1,
GPIO_PIN_2,
GPIO_PIN_3,
GPIO_PIN_4,
GPIO_PIN_5,
GPIO_PIN_6,
GPIO_PIN_7,
GPIO_PIN_8,
GPIO_PIN_9,
GPIO_PIN_10,
GPIO_PIN_11,
GPIO_PIN_12,
GPIO_PIN_13,
GPIO_PIN_14,
GPIO_PIN_15,
GPIO_PIN_16,
GPIO_PIN_17,
GPIO_PIN_18,
GPIO_PIN_19,
GPIO_PIN_20,
GPIO_PIN_21,
GPIO_PIN_22,
GPIO_PIN_23,
GPIO_PIN_24,
GPIO_PIN_25,
GPIO_PIN_26,
GPIO_PIN_27,
GPIO_PIN_28,
GPIO_PIN_29,
GPIO_PIN_30,
GPIO_PIN_31,
GPIO_PIN_MAX,
};
#define GPIO_OUTPUT_MODE 0
#define GPIO_OUTPUT_PP_MODE 1
#define GPIO_OUTPUT_PD_MODE 2
#define GPIO_INPUT_MODE 3
#define GPIO_INPUT_PP_MODE 4
#define GPIO_INPUT_PD_MODE 5
#define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6
#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7
#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE 8
#define GPIO_ASYNC_LOW_LEVEL_INT_MODE 9
#define GPIO_SYNC_RISING_TRIGER_INT_MODE 10
#define GPIO_SYNC_FALLING_TRIGER_INT_MODE 11
#define GPIO_SYNC_HIGH_LEVEL_INT_MODE 12
#define GPIO_SYNC_LOW_LEVEL_INT_MODE 13
#define GPIO_HZ_MODE 14
void gpio_set_mode(uint32_t pin, uint32_t mode);
void gpio_write(uint32_t pin, uint32_t value);
void gpio_toggle(uint32_t pin);
int gpio_read(uint32_t pin);
void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin));
void gpio_irq_enable(uint32_t pin, uint8_t enabled);
#ifdef __cplusplus
}
#endif
#endif

75
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2c.h
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@@ -1,75 +0,0 @@
/**
* @file hal_i2c.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_I2C__H__
#define __HAL_I2C__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
enum i2c_index_type {
#ifdef BSP_USING_I2C0
I2C0_INDEX,
#endif
I2C_MAX_INDEX
};
#define I2C_WR 0x0000
#define I2C_RD 0x0001
#define I2C_RW_MASK 0x0001
#define SUB_ADDR_0BYTE 0x0010
#define SUB_ADDR_1BYTE 0x0020
#define SUB_ADDR_2BYTE 0x0040
#define I2C_HW_MODE 0
#define I2C_SW_MODE 1
typedef struct i2c_msg {
uint8_t slaveaddr;
uint32_t subaddr;
uint16_t flags;
uint16_t len;
uint8_t *buf;
} i2c_msg_t;
typedef struct i2c_device {
struct device parent;
uint8_t id;
uint8_t mode;
uint32_t phase;
} i2c_device_t;
#define I2C_DEV(dev) ((i2c_device_t *)dev)
int i2c_register(enum i2c_index_type index, const char *name);
int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num);
#ifdef __cplusplus
}
#endif
#endif

125
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2s.h
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@@ -1,125 +0,0 @@
/**
* @file hal_i2s.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_I2S__H__
#define __HAL_I2S__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_I2S_GET_TX_FIFO 0x10
#define DEVICE_CTRL_I2S_GET_RX_FIFO 0x11
#define DEVICE_CTRL_I2S_SET_SAMPL_FREQ 0x12
enum i2s_index_type {
#ifdef BSP_USING_I2S0
I2S0_INDEX,
#endif
I2S_MAX_INDEX
};
#define I2S_DEFAULT_RTO_TIMEOUT 15
/*!
* @brief I2S mode type settings
*
* This enumeration defines the I2S mode type
*/
typedef enum {
I2S_MODE_STD, /*!< I2S STD Mode */
I2S_MODE_LEFT, /*!< Left-Justified Mode */
I2S_MODE_RIGHT, /*!< Right-Justified Mode */
I2S_MODE_DSP_A, /*!< DSP/PCM Mode A*/
I2S_MODE_DSP_B, /*!< DSP/PCM Mode B*/
} interface_mode_t;
/*!
* @brief I2S frame size settings
*
* This enumeration defines the frame size type
*/
typedef enum {
I2S_FRAME_LEN_8 = 1, /*!< I2S frame size 8 bits */
I2S_FRAME_LEN_16 = 2, /*!< I2S frame size 16 bits */
I2S_FRAME_LEN_24 = 3, /*!< I2S frame size 24 bits */
I2S_FRAME_LEN_32 = 4, /*!< I2S frame size 32 bits */
} i2s_frame_size_t;
/*!
* @brief I2S data size settings
*
* This enumeration defines the data size type
*/
typedef enum {
I2S_DATA_LEN_8 = 1, /*!< I2S data size 8 bits */
I2S_DATA_LEN_16 = 2, /*!< I2S data size 16 bits */
I2S_DATA_LEN_24 = 3, /*!< I2S data size 24 bits */
I2S_DATA_LEN_32 = 4, /*!< I2S data size 32 bits */
} i2s_data_size_t;
/*!
* @brief I2S frame channel settings
*
* This enumeration defines the frame channel mode type
*/
typedef enum {
I2S_FS_CHANNELS_NUM_MONO = 1, /*!< I2S frame is for 1 channels */
I2S_FS_CHANNELS_NUM_2 = 2, /*!< I2S frame is for 2 channels */
I2S_FS_CHANNELS_NUM_3 = 3, /*!< I2S frame is for 3 channels, DSP mode only, frame_size must equal data_size*/
I2S_FS_CHANNELS_NUM_4 = 4, /*!< I2S frame is for 4 channels, DSP mode only, frame_size must equal data_size*/
} i2s_channel_num_t;
typedef enum {
I2S_MODE_MASTER = 0, /*!< I2S as master */
I2S_MODE_SLAVE, /*!< I2S as slave */
} i2s_mode_t;
typedef struct i2s_device {
struct device parent;
uint8_t id;
i2s_mode_t iis_mode;
interface_mode_t interface_mode;
uint32_t sampl_freq_hz; /*!< I2S sample data frequency in Hz */
i2s_channel_num_t channel_num;
i2s_frame_size_t frame_size;
i2s_data_size_t data_size;
uint8_t fifo_threshold; /*!< I2S receive and transmit threshold*/
void *tx_dma;
void *rx_dma;
} i2s_device_t;
#define I2S_DEV(dev) ((i2s_device_t *)dev)
int i2s_register(enum i2s_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

97
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_keyscan.h
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@@ -1,97 +0,0 @@
/**
* @file hal_keyscan.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_KEYSCAN__H__
#define __HAL_KEYSCAN__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_KEYSCAN_GET_KEYCODE 0x10
enum keyscan_index_type {
#ifdef BSP_USING_KEYSCAN
KEYSCAN_INDEX,
#endif
KEYSCAN_MAX_INDEX
};
enum col_num_type {
COL_NUM_1 = 1,
COL_NUM_2,
COL_NUM_3,
COL_NUM_4,
COL_NUM_5,
COL_NUM_6,
COL_NUM_7,
COL_NUM_8,
COL_NUM_9,
COL_NUM_10,
COL_NUM_11,
COL_NUM_12,
COL_NUM_13,
COL_NUM_14,
COL_NUM_15,
COL_NUM_16,
COL_NUM_17,
COL_NUM_18,
COL_NUM_19,
COL_NUM_20
};
enum row_num_type {
ROW_NUM_1 = 1,
ROW_NUM_2,
ROW_NUM_3,
ROW_NUM_4,
ROW_NUM_5,
ROW_NUM_6,
ROW_NUM_7,
ROW_NUM_8,
};
enum keyscan_event_type {
KEYSCAN_EVENT_TRIG,
KEYSCAN_EVENT_UNKNOWN
};
typedef struct keyscan_device {
struct device parent;
enum col_num_type col_num;
enum row_num_type row_num;
uint8_t deglitch_count;
} keyscan_device_t;
#define KEYSCAN_DEV(dev) ((keyscan_device_t *)dev)
int keyscan_register(enum keyscan_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

77
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h
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@@ -1,77 +0,0 @@
/**
* @file hal_mjpeg.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_MJPEG__H__
#define __HAL_MJPEG__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define MJPEG_PACKET_ADD_NONE 0
#define MJPEG_PACKET_ADD_DEFAULT 1 << 0
#define MJPEG_PACKET_ADD_FRAME_HEAD 1 << 1
#define MJPEG_PACKET_ADD_FRAME_TAIL 1 << 2
#define MJPEG_PACKET_ADD_END_TAIL 1 << 3
/**
* @brief MJPEG YUV format definition
*/
typedef enum {
MJPEG_YUV_FORMAT_YUV420, /*!< MJPEG YUV420 planar mode */
MJPEG_YUV_FORMAT_YUV400, /*!< MJPEG YUV400 grey scale mode */
MJPEG_YUV_FORMAT_YUV422_PLANAR, /*!< MJPEG YUV422 planar mode */
MJPEG_YUV_FORMAT_YUV422_INTERLEAVE, /*!< MJPEG YUV422 interleave mode */
} mjpeg_yuv_format_t;
typedef struct mjpeg_device {
struct device parent;
uint8_t quality;
mjpeg_yuv_format_t yuv_format;
uint32_t write_buffer_addr; /*!< MJPEG buffer addr */
uint32_t write_buffer_size; /*!< MJPEG buffer size */
uint32_t read_buffer_addr;
uint32_t read_buffer_size;
uint16_t resolution_x; /*!< CAM RESOLUTION X */
uint16_t resolution_y; /*!< CAM RESOLUTION Y */
uint8_t packet_cut_mode;
uint16_t frame_head_length;
uint16_t packet_head_length;
uint16_t packet_body_length;
uint16_t packet_tail_length;
} mjpeg_device_t;
void mjpeg_init(mjpeg_device_t *mjpeg_cfg);
void mjpeg_start(void);
void mjpeg_stop(void);
uint8_t mjpeg_get_one_frame(uint8_t **pic, uint32_t *len, uint8_t *q);
void mjpeg_drop_one_frame(void);
#ifdef __cplusplus
}
#endif
#endif

42
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h
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@@ -1,42 +0,0 @@
/**
* @file hal_mtimer.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_MTIMER__H__
#define __HAL_MTIMER__H__
#include "stdint.h"
#ifdef __cplusplus
extern "C"{
#endif
void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void));
uint64_t mtimer_get_time_ms();
uint64_t mtimer_get_time_us();
void mtimer_delay_ms(uint32_t time);
void mtimer_delay_us(uint32_t time);
#ifdef __cplusplus
}
#endif
#endif

75
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm.h
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@@ -1,75 +0,0 @@
/**
* @file hal_pm.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_PM__H__
#define __HAL_PM__H__
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_common.h"
enum pm_pds_sleep_level {
PM_PDS_LEVEL_0,
PM_PDS_LEVEL_1,
PM_PDS_LEVEL_2,
PM_PDS_LEVEL_3,
PM_PDS_LEVEL_4, /*do not recommend to use*/
PM_PDS_LEVEL_5, /*do not recommend to use*/
PM_PDS_LEVEL_6, /*do not recommend to use*/
PM_PDS_LEVEL_7, /*do not recommend to use*/
PM_PDS_LEVEL_31 = 31,
};
enum pm_hbn_sleep_level {
PM_HBN_LEVEL_0,
PM_HBN_LEVEL_1,
PM_HBN_LEVEL_2,
};
enum pm_event_type {
PM_HBN_WAKEUP_EVENT_NONE,
PM_HBN_GPIO9_WAKEUP_EVENT,
PM_HBN_GPIO10_WAKEUP_EVENT,
PM_HBN_GPIO11_WAKEUP_EVENT,
PM_HBN_GPIO12_WAKEUP_EVENT,
PM_HBN_RTC_WAKEUP_EVENT,
PM_HBN_BOR_WAKEUP_EVENT,
PM_HBN_ACOMP0_WAKEUP_EVENT,
PM_HBN_ACOMP1_WAKEUP_EVENT,
};
void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time);
void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8_t sleep_time);
void pm_hbn_enter_again(bool reset);
void pm_set_wakeup_callback(void (*wakeup_callback)(void));
enum pm_event_type pm_get_wakeup_event(void);
void pm_bor_init(void);
void pm_hbn_out0_irq_register(void);
void pm_hbn_out1_irq_register(void);
void pm_irq_callback(enum pm_event_type event);
#ifdef __cplusplus
}
#endif
#endif

33
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm_util.h
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@@ -1,33 +0,0 @@
/**
* @file hal_pm_util.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_PM_UTIL_H__
#define __HAL_PM_UTIL_H__
#include "hal_common.h"
#define ATTR_PDS_RAM_SECTION __attribute__((section(".pds_ram_code")))
#define ATTR_PDS_RAM_CONST_SECTION __attribute__((section(".pds_ram_data")))
uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles);
void pm_set_hardware_recovery_callback(void (*hardware_recovery_cb)(void));
#endif

90
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pwm.h
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@@ -1,90 +0,0 @@
/**
* @file hal_pwm.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_PWM__H__
#define __HAL_PWM__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_PWM_FREQUENCE_CONFIG 0x10
#define DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG 0x11
#define DEVICE_CTRL_PWM_IT_PULSE_COUNT_CONFIG 0x12
enum pwm_index_type {
#ifdef BSP_USING_PWM_CH0
PWM_CH0_INDEX,
#endif
#ifdef BSP_USING_PWM_CH1
PWM_CH1_INDEX,
#endif
#ifdef BSP_USING_PWM_CH2
PWM_CH2_INDEX,
#endif
#ifdef BSP_USING_PWM_CH3
PWM_CH3_INDEX,
#endif
#ifdef BSP_USING_PWM_CH4
PWM_CH4_INDEX,
#endif
PWM_MAX_INDEX
};
#define pwm_channel_start(dev) device_control(dev, DEVICE_CTRL_RESUME, NULL)
#define pwm_channel_stop(dev) device_control(dev, DEVICE_CTRL_SUSPEND, NULL)
#define pwm_channel_freq_update(dev, count) device_control(dev, DEVICE_CTRL_PWM_FREQUENCE_CONFIG, (void *)count)
#define pwm_channel_dutycycle_update(dev, cfg) device_control(dev, DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG, cfg)
#define pwm_it_pulse_count_update(dev, count) device_control(dev, DEVICE_CTRL_PWM_IT_PULSE_COUNT_CONFIG, (void *)count)
enum pwm_event_type {
PWM_EVENT_COMPLETE,
};
typedef struct
{
uint16_t threshold_low;
uint16_t threshold_high;
} pwm_dutycycle_config_t;
typedef struct pwm_device {
struct device parent;
uint8_t ch;
uint8_t polarity_invert_mode;
uint16_t period;
uint16_t threshold_low;
uint16_t threshold_high;
uint16_t it_pulse_count;
} pwm_device_t;
#define PWM_DEV(dev) ((pwm_device_t *)dev)
int pwm_register(enum pwm_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

83
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_qdec.h
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@@ -1,83 +0,0 @@
/**
* @file hal_qdec.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_QDEC__H__
#define __HAL_QDEC__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_GET_SAMPLE_VAL (0x10)
#define DEVICE_CTRL_GET_SAMPLE_DIR (0x11)
#define DEVICE_CTRL_GET_ERROR_CNT (0x12)
enum qdec_index_type {
#ifdef BSP_USING_QDEC0
QDEC0_INDEX,
#endif
#ifdef BSP_USING_QDEC1
QDEC1_INDEX,
#endif
#ifdef BSP_USING_QDEC2
QDEC2_INDEX,
#endif
QDEC_MAX_INDEX,
};
enum qdec_event_type {
QDEC_REPORT_EVENT = 1 << 0, /*!< report interrupt */
QDEC_SAMPLE_EVENT = 1 << 1, /*!< sample interrupt */
QDEC_ERROR_EVENT = 1 << 2, /*!< error interrupt */
QDEC_OVERFLOW_EVENT = 1 << 3, /*!< ACC1 and ACC2 overflow interrupt */
QDEC_ALL_EVENT = 1 << 4, /*!< interrupt max num */
};
typedef struct qdec_device {
struct device parent;
uint8_t id;
uint8_t acc_mode;
uint8_t sample_mode;
uint8_t sample_period;
uint8_t report_mode;
uint32_t report_period;
uint8_t led_en;
uint8_t led_swap;
uint16_t led_period;
uint8_t deglitch_en;
uint8_t deglitch_strength;
} qdec_device_t;
#define QDEC_DEV(dev) ((qdec_device_t *)dev)
int qdec_register(enum qdec_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif // __HAL_QDEC_H__

39
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_rtc.h
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@@ -1,39 +0,0 @@
/**
* @file hal_rtc.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_RTC__H__
#define __HAL_RTC__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
void rtc_init(uint64_t sleep_time);
void rtc_set_timestamp(uint64_t time_stamp);
uint64_t rtc_get_timestamp(void);
#ifdef __cplusplus
}
#endif
#endif

62
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h
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/**
* @file hal_sec_aes.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_SEC_AES__H__
#define __HAL_SEC_AES__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
typedef enum {
SEC_AES_CBC,
SEC_AES_CTR,
SEC_AES_ECB
} sec_aes_type;
typedef enum {
SEC_AES_KEY_128,
SEC_AES_KEY_256,
SEC_AES_KEY_192
} sec_aes_key_type;
typedef struct sec_aes_handle_t {
sec_aes_type aes_type;
sec_aes_key_type key_type;
} sec_aes_handle_t;
typedef enum {
SEC_AES_DIR_ENCRYPT,
SEC_AES_DIR_DECRYPT
} sec_aes_dir_type;
int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type);
int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir);
int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out);
int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out);
int sec_aes_deinit(sec_aes_handle_t *handle);
#ifdef __cplusplus
}
#endif
#endif

63
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h
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@@ -1,63 +0,0 @@
/**
* @file hal_sec_dsa.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_SEC_DSA__H__
#define __HAL_SEC_DSA__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
typedef struct sec_dsa_crt_cfg_tag {
uint32_t *dP;
uint32_t *dQ;
uint32_t *qInv;
uint32_t *p;
uint32_t *invR_p;
uint32_t *primeN_p;
uint32_t *q;
uint32_t *invR_q;
uint32_t *primeN_q;
} sec_dsa_crt_cfg_t;
typedef struct
{
uint32_t size;
uint32_t crtSize;
uint32_t *n;
uint32_t *e;
uint32_t *d;
sec_dsa_crt_cfg_t crtCfg;
} sec_dsa_handle_t;
int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size);
int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r);
int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r);
int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r);
int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s);
int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s);
#ifdef __cplusplus
}
#endif
#endif

69
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h
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@@ -1,69 +0,0 @@
/**
* @file hal_sec_ecdsa.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_SEC_ECDSA__H__
#define __HAL_SEC_ECDSA__H__
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_common.h"
typedef enum {
ECP_SECP256R1 = 0,
ECP_SECP256K1 = 1,
ECP_TYPE_MAX = 2,
} sec_ecp_type;
typedef struct
{
sec_ecp_type ecpId;
uint32_t *privateKey;
uint32_t *publicKeyx;
uint32_t *publicKeyy;
} sec_ecdsa_handle_t;
typedef struct
{
sec_ecp_type ecpId;
} sec_ecdh_handle_t;
int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id);
int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle);
int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s);
int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s);
int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key);
int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id);
int sec_ecdh_deinit(sec_ecdh_handle_t *handle);
int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size);
int sec_eng_trng_enable(void);
void sec_eng_trng_disable(void);
int sec_eng_trng_read(uint8_t data[32]);
#ifdef __cplusplus
}
#endif
#endif

72
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h
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@@ -1,72 +0,0 @@
/**
* @file hal_sec_hash.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_SEC_HASH__H__
#define __HAL_SEC_HASH__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
enum sec_hash_index_type {
SEC_HASH0_INDEX,
SEC_HASH_MAX_INDEX
};
enum sec_hash_type {
SEC_HASH_SHA1,
SEC_HASH_SHA224,
SEC_HASH_SHA256,
SEC_HASH_SHA384,
SEC_HASH_SHA512,
SEC_HASH_UNKNOWN
};
typedef struct sec_hash_device {
struct device parent;
uint32_t shaBuf[64 / 4]; /*!< Data not processed but in this temp buffer */
uint32_t shaPadding[64 / 4]; /*!< Padding data */
uint8_t type; /*!< Sha has feed data */
} sec_hash_device_t;
typedef struct
{
uint32_t shaBuf[64 / 4]; /*!< Data not processed but in this temp buffer */
uint32_t shaPadding[64 / 4]; /*!< Padding data */
uint8_t type; /*!< Sha has feed data */
} sec_hash_handle_t;
int sec_hash_init(sec_hash_handle_t *handle, uint8_t type);
int sec_hash_deinit(sec_hash_handle_t *handle);
int sec_hash_update(sec_hash_handle_t *handle, const void *buffer, uint32_t size);
int sec_hash_finish(sec_hash_handle_t *handle, void *buffer);
int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name);
int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

123
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_spi.h
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@@ -1,123 +0,0 @@
/**
* @file hal_spi.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_SPI__H__
#define __HAL_SPI__H__
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define SPI_FIFO_LEN 4
#define DEVICE_CTRL_SPI_CONFIG_CLOCK 0x10
#define DEVICE_CTRL_SPI_GET_TX_FIFO 0x11
#define DEVICE_CTRL_SPI_GET_RX_FIFO 0x12
#define DEVICE_CTRL_SPI_CLEAR_TX_FIFO 0x13
#define DEVICE_CTRL_SPI_CLEAR_RX_FIFO 0x14
#define DEVICE_CTRL_SPI_GET_BUS_BUSY_STATUS 0x15
enum spi_index_type {
#ifdef BSP_USING_SPI0
SPI0_INDEX,
#endif
SPI_MAX_INDEX
};
/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
#define SPI_LSB_BYTE0_DIRECTION_FIRST 0
#define SPI_LSB_BYTE3_DIRECTION_FIRST 1
#define SPI_MSB_BYTE0_DIRECTION_FIRST 2
#define SPI_MSB_BYTE3_DIRECTION_FIRST 3
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
#define SPI_DATASIZE_8BIT 0
#define SPI_DATASIZE_16BIT 1
#define SPI_DATASIZE_24BIT 2
#define SPI_DATASIZE_32BIT 3
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
#define SPI_POLARITY_LOW 0
#define SPI_POLARITY_HIGH 1
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
#define SPI_PHASE_1EDGE 0
#define SPI_PHASE_2EDGE 1
/** @defgroup
* @{
*/
#define SPI_SLVAE_MODE 0
#define SPI_MASTER_MODE 1
#define SPI_TRANSFER_TYPE_8BIT 0
#define SPI_TRANSFER_TYPE_16BIT 1
#define SPI_TRANSFER_TPYE_24BIT 2
#define SPI_TRANSFER_TYPE_32BIT 3
enum spi_event_type {
SPI_EVENT_TX_FIFO,
SPI_EVENT_RX_FIFO,
SPI_EVENT_UNKNOWN
};
typedef struct spi_device {
struct device parent;
uint8_t id;
uint32_t clk;
uint8_t mode;
uint8_t direction;
uint8_t clk_polaraity;
uint8_t clk_phase;
uint8_t datasize;
uint8_t fifo_threshold;
uint8_t pin_swap_enable; /*swap mosi and miso*/
uint8_t delitch_cnt;
void *tx_dma;
void *rx_dma;
} spi_device_t;
#define SPI_DEV(dev) ((spi_device_t *)dev)
int spi_register(enum spi_index_type index, const char *name);
int spi_transmit(struct device *dev, void *buffer, uint32_t size, uint8_t type);
int spi_receive(struct device *dev, void *buffer, uint32_t size, uint8_t type);
int spi_transmit_receive(struct device *dev, const void *send_buf, void *recv_buf, uint32_t length, uint8_t type);
#ifdef __cplusplus
}
#endif
#endif

97
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_timer.h
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@@ -1,97 +0,0 @@
/**
* @file hal_timer.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_TIMER__H__
#define __HAL_TIMER__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
enum timer_index_type {
#ifdef BSP_USING_TIMER0
TIMER0_INDEX,
#endif
#ifdef BSP_USING_TIMER1
TIMER1_INDEX,
#endif
TIMER_MAX_INDEX
};
enum timer_preload_trigger_type {
TIMER_PRELOAD_TRIGGER_NONE,
TIMER_PRELOAD_TRIGGER_COMP0,
TIMER_PRELOAD_TRIGGER_COMP1,
TIMER_PRELOAD_TRIGGER_COMP2,
};
enum timer_cnt_mode_type {
TIMER_CNT_PRELOAD,
TIMER_CNT_FREERUN,
};
enum timer_compare_id_type {
TIMER_COMPARE_ID_0,
TIMER_COMPARE_ID_1,
TIMER_COMPARE_ID_2,
};
enum timer_it_type {
TIMER_COMP0_IT = 1 << 0,
TIMER_COMP1_IT = 1 << 1,
TIMER_COMP2_IT = 1 << 2,
};
enum timer_event_type {
TIMER_EVENT_COMP0,
TIMER_EVENT_COMP1,
TIMER_EVENT_COMP2,
TIMER_EVENT_UNKNOWN
};
typedef struct timer_timeout_cfg {
enum timer_compare_id_type timeout_id;
uint32_t timeout_val;
} timer_timeout_cfg_t;
typedef struct timer_device {
struct device parent;
uint8_t id;
enum timer_cnt_mode_type cnt_mode;
enum timer_preload_trigger_type trigger;
uint32_t reload;
uint32_t timeout1;
uint32_t timeout2;
uint32_t timeout3;
} timer_device_t;
#define TIMER_DEV(dev) ((timer_device_t *)dev)
int timer_register(enum timer_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

136
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_uart.h
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@@ -1,136 +0,0 @@
/**
* @file hal_uart.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_UART__H__
#define __HAL_UART__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define UART_FIFO_LEN 128
#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10
#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11
#define DEVICE_CTRL_UART_CLEAR_TX_FIFO 0x12
#define DEVICE_CTRL_UART_CLEAR_RX_FIFO 0x13
enum uart_index_type {
#ifdef BSP_USING_UART0
UART0_INDEX,
#endif
#ifdef BSP_USING_UART1
UART1_INDEX,
#endif
UART_MAX_INDEX
};
/*!
* @brief UART data length settings
*
* This enumeration defines the UART data lengths.
*/
typedef enum {
UART_DATA_LEN_5 = 0, /*!< Data length is 5 bits */
UART_DATA_LEN_6 = 1, /*!< Data length is 6 bits */
UART_DATA_LEN_7 = 2, /*!< Data length is 7 bits */
UART_DATA_LEN_8 = 3 /*!< Data length is 8 bits */
} uart_databits_t;
/*!
* @brief UART stop bit settings
*
* This enumeration defines the UART stop bits.
*/
typedef enum {
UART_STOP_ZERO_D_FIVE = 0, /*!< 0.5 stop bit */
UART_STOP_ONE = 1, /*!< 1 stop bit */
UART_STOP_ONE_D_FIVE = 2, /*!< 1.5 stop bit */
UART_STOP_TWO = 3 /*!< 2 stop bits */
} uart_stopbits_t;
/*!
* @brief UART parity type settings
*
* This enumeration defines the UART parity types.
*/
typedef enum {
UART_PAR_NONE = 0, /*!< No parity */
UART_PAR_ODD = 1, /*!< Parity bit is odd */
UART_PAR_EVEN = 2, /*!< Parity bit is even */
} uart_parity_t;
enum uart_event_type {
UART_EVENT_TX_END,
UART_EVENT_TX_FIFO,
UART_EVENT_RX_END,
UART_EVENT_RX_FIFO,
UART_EVENT_RTO,
UART_EVENT_PCE,
UART_EVENT_TX_FER,
UART_EVENT_RX_FER,
UART_EVENT_UNKNOWN
};
enum uart_it_type {
UART_TX_END_IT = 1 << 0,
UART_RX_END_IT = 1 << 1,
UART_TX_FIFO_IT = 1 << 2,
UART_RX_FIFO_IT = 1 << 3,
UART_RTO_IT = 1 << 4,
UART_PCE_IT = 1 << 5,
UART_TX_FER_IT = 1 << 6,
UART_RX_FER_IT = 1 << 7,
UART_ALL_IT = 1 << 8
};
typedef struct
{
uint32_t baudrate;
uart_databits_t databits;
uart_stopbits_t stopbits;
uart_parity_t parity;
} uart_param_cfg_t;
typedef struct uart_device {
struct device parent;
uint8_t id;
uint32_t baudrate;
uart_databits_t databits;
uart_stopbits_t stopbits;
uart_parity_t parity;
uint8_t fifo_threshold;
void *tx_dma;
void *rx_dma;
} uart_device_t;
#define UART_DEV(dev) ((uart_device_t *)dev)
int uart_register(enum uart_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

236
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_usb.h
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@@ -1,236 +0,0 @@
/**
* @file hal_usb.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_USB__H__
#define __HAL_USB__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "ring_buffer.h"
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_USB_DC_SET_ACK 0X10
#define DEVICE_CTRL_USB_DC_ENUM_ON 0X11
#define DEVICE_CTRL_USB_DC_ENUM_OFF 0X12
#define DEVICE_CTRL_USB_DC_GET_EP_TX_FIFO_CNT 0x13
#define DEVICE_CTRL_USB_DC_GET_EP_RX_FIFO_CNT 0x14
#define DEVICE_CTRL_USB_DC_SET_TX_DMA 0x15
#define DEVICE_CTRL_USB_DC_SET_RX_DMA 0x16
enum usb_index_type {
#ifdef BSP_USING_USB
USB_INDEX,
#endif
USB_MAX_INDEX
};
/**
* USB endpoint Transfer Type mask.
*/
#define USBD_EP_TYPE_CTRL 0
#define USBD_EP_TYPE_ISOC 1
#define USBD_EP_TYPE_BULK 2
#define USBD_EP_TYPE_INTR 3
#define USBD_EP_TYPE_MASK 3
/**
* USB endpoint direction and number.
*/
#define USB_EP_DIR_MASK 0x80U
#define USB_EP_DIR_IN 0x80U
#define USB_EP_DIR_OUT 0x00U
#define USB_EP_OUT_MSK 0x7FU
#define USB_EP_IN_MSK 0x80U
/** Get endpoint index (number) from endpoint address */
#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK)
/** Get direction from endpoint address */
#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK)
/** Get endpoint address from endpoint index and direction */
#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK))
/** True if the endpoint is an IN endpoint */
#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN)
/** True if the endpoint is an OUT endpoint */
#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT)
#define USB_SET_EP_OUT(ep) (ep & USB_EP_OUT_MSK)
#define USB_SET_EP_IN(ep) (ep | USB_EP_IN_MSK)
#define USB_OUT_EP_NUM 8
#define USB_IN_EP_NUM 8
#define USB_CTRL_EP_MPS 64 /**< maximum packet size (MPS) for EP 0 */
#define USB_FS_MAX_PACKET_SIZE 64 /**< full speed MPS for bulk EP */
/* Default USB control EP, always 0 and 0x80 */
#define USB_CONTROL_OUT_EP0 0
#define USB_CONTROL_IN_EP0 0x80
#define USB_DC_EP_TYPE_CTRL 0x5 /*0*/
#define USB_DC_EP_TYPE_ISOC 0x2 /*1*/
#define USB_DC_EP_TYPE_BULK 0x4 /*2*/
#define USB_DC_EP_TYPE_INTR 0x0 /*3*/
#define USB_DC_EP1_IN_DR (0x4000D800 + 0x118)
#define USB_DC_EP1_OUT_DR (0x4000D800 + 0x11c)
#define USB_DC_EP2_IN_DR (0x4000D800 + 0x128)
#define USB_DC_EP2_OUT_DR (0x4000D800 + 0x12c)
#define USB_DC_EP3_IN_DR (0x4000D800 + 0x138)
#define USB_DC_EP3_OUT_DR (0x4000D800 + 0x13c)
#define USB_DC_EP4_IN_DR (0x4000D800 + 0x148)
#define USB_DC_EP4_OUT_DR (0x4000D800 + 0x14c)
#define USB_DC_EP5_IN_DR (0x4000D800 + 0x158)
#define USB_DC_EP5_OUT_DR (0x4000D800 + 0x15c)
#define USB_DC_EP6_IN_DR (0x4000D800 + 0x168)
#define USB_DC_EP6_OUT_DR (0x4000D800 + 0x16c)
#define USB_DC_EP7_IN_DR (0x4000D800 + 0x178)
#define USB_DC_EP7_OUT_DR (0x4000D800 + 0x17c)
enum usb_dc_event_type {
/** USB error reported by the controller */
USB_DC_EVENT_ERROR,
/** USB reset */
USB_DC_EVENT_RESET,
/** Start of Frame received */
USB_DC_EVENT_SOF,
/** USB connection established, hardware enumeration is completed */
USB_DC_EVENT_CONNECTED,
/** USB configuration done */
USB_DC_EVENT_CONFIGURED,
/** USB connection suspended by the HOST */
USB_DC_EVENT_SUSPEND,
/** USB connection lost */
USB_DC_EVENT_DISCONNECTED,
/** USB connection resumed by the HOST */
USB_DC_EVENT_RESUME,
/** USB interface selected */
USB_DC_EVENT_SET_INTERFACE,
/** USB interface selected */
USB_DC_EVENT_SET_REMOTE_WAKEUP,
/** USB interface selected */
USB_DC_EVENT_CLEAR_REMOTE_WAKEUP,
/** Set Feature ENDPOINT_HALT received */
USB_DC_EVENT_SET_HALT,
/** Clear Feature ENDPOINT_HALT received */
USB_DC_EVENT_CLEAR_HALT,
/** setup packet received */
USB_DC_EVENT_SETUP_NOTIFY,
/** ep0 in packet received */
USB_DC_EVENT_EP0_IN_NOTIFY,
/** ep0 out packet received */
USB_DC_EVENT_EP0_OUT_NOTIFY,
/** ep in packet except ep0 received */
USB_DC_EVENT_EP_IN_NOTIFY,
/** ep out packet except ep0 received */
USB_DC_EVENT_EP_OUT_NOTIFY,
/** Initial USB connection status */
USB_DC_EVENT_UNKNOWN
};
enum usb_dc_ep_it_type {
USB_SOF_IT = 1 << 0,
USB_EP1_DATA_IN_IT = 1 << 10,
USB_EP1_DATA_OUT_IT = 1 << 11,
USB_EP2_DATA_IN_IT = 1 << 12,
USB_EP2_DATA_OUT_IT = 1 << 13,
USB_EP3_DATA_IN_IT = 1 << 14,
USB_EP3_DATA_OUT_IT = 1 << 15,
USB_EP4_DATA_IN_IT = 1 << 16,
USB_EP4_DATA_OUT_IT = 1 << 17,
USB_EP5_DATA_IN_IT = 1 << 18,
USB_EP5_DATA_OUT_IT = 1 << 19,
USB_EP6_DATA_IN_IT = 1 << 20,
USB_EP6_DATA_OUT_IT = 1 << 21,
USB_EP7_DATA_IN_IT = 1 << 22,
USB_EP7_DATA_OUT_IT = 1 << 23,
};
enum usb_error_type {
USB_DC_OK = 0,
USB_DC_EP_DIR_ERR = 1,
USB_DC_EP_EN_ERR = 2,
USB_DC_EP_TIMEOUT_ERR = 3,
USB_DC_ADDR_ERR = 4,
USB_DC_RB_SIZE_SMALL_ERR = 5,
USB_DC_ZLP_ERR = 6,
};
/**
* @brief USB Endpoint Configuration.
*
* Structure containing the USB endpoint configuration.
*/
struct usb_dc_ep_cfg {
/** The number associated with the EP in the device
* configuration structure
* IN EP = 0x80 | \<endpoint number\>
* OUT EP = 0x00 | \<endpoint number\>
*/
uint8_t ep_addr;
/** Endpoint max packet size */
uint16_t ep_mps;
/** Endpoint Transfer Type.
* May be Bulk, Interrupt, Control or Isochronous
*/
uint8_t ep_type;
};
/*
* USB endpoint structure.
*/
typedef struct
{
uint8_t ep_ena;
uint32_t is_stalled;
struct usb_dc_ep_cfg ep_cfg;
} usb_dc_ep_state_t;
typedef struct usb_dc_device {
struct device parent;
uint8_t id;
usb_dc_ep_state_t in_ep[8]; /*!< IN endpoint parameters */
usb_dc_ep_state_t out_ep[8]; /*!< OUT endpoint parameters */
void *tx_dma;
void *rx_dma;
} usb_dc_device_t;
int usb_dc_register(enum usb_index_type index, const char *name);
int usb_dc_set_dev_address(const uint8_t addr);
int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg);
int usb_dc_ep_close(const uint8_t ep);
int usb_dc_ep_set_stall(const uint8_t ep);
int usb_dc_ep_clear_stall(const uint8_t ep);
int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled);
int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes);
int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes);
int usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep);
int usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep);
#ifdef __cplusplus
}
#endif
#endif

64
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_wdt.h
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@@ -1,64 +0,0 @@
/**
* @file hal_wdt.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_WDT__H__
#define __HAL_WDT__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_GET_WDT_COUNTER (0x10)
#define DEVICE_CTRL_RST_WDT_COUNTER (0x11)
#define DEVICE_CTRL_GET_RST_STATUS (0x12)
#define DEVICE_CTRL_CLR_RST_STATUS (0x13)
enum wdt_index_type {
#ifdef BSP_USING_WDT
WDT_INDEX,
#endif
WDT_MAX_INDEX
};
enum wdt_event_type {
WDT_EVENT,
WDT_EVENT_UNKNOWN
};
typedef struct wdt_device {
struct device parent;
uint8_t id;
uint32_t wdt_timeout;
} wdt_device_t;
#define WDT_DEV(dev) ((wdt_device_t *)dev)
int wdt_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size);
int wdt_register(enum wdt_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

146
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_acomp.c
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@@ -1,146 +0,0 @@
#include "hal_acomp.h"
#include "bl702_acomp.h"
#include "hbn_reg.h"
void acomp_init(uint8_t idx, acomp_device_t *device)
{
uint32_t tmpVal;
if (idx == 0) {
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal &= ~(1 << 20);
tmpVal &= ~(1 << 21);
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
/* Disable ACOMP first */
tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN);
tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
/* Set ACOMP config */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_MUXEN, 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_POS_SEL, device->pos_ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_NEG_SEL, device->neg_ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_LEVEL_SEL, AON_ACOMP_LEVEL_FACTOR_1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_BIAS_PROG, AON_ACOMP_BIAS_POWER_MODE1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELP, device->pos_hysteresis_vol);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELN, device->neg_hysteresis_vol);
BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
} else {
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal &= ~(1 << 22);
tmpVal &= ~(1 << 23);
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
/* Disable ACOMP first */
tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN);
tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
/* Set ACOMP config */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_MUXEN, 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_POS_SEL, device->pos_ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_NEG_SEL, device->neg_ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_LEVEL_SEL, AON_ACOMP_LEVEL_FACTOR_1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_BIAS_PROG, AON_ACOMP_BIAS_POWER_MODE1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELP, device->pos_hysteresis_vol);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELN, device->neg_hysteresis_vol);
BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
}
}
void acomp_enable(uint8_t idx)
{
uint32_t tmpVal;
if (idx == 0) {
tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN);
BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
} else {
tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN);
BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
}
}
void acomp_disable(uint8_t idx)
{
uint32_t tmpVal;
if (idx == 0) {
tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN);
BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
} else {
tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN);
BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
}
}
void acomp_interrupt_mask(uint8_t idx, uint32_t flag)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
if (idx == 0) {
tmpVal &= ~(flag << 20);
} else {
tmpVal &= ~(flag << 22);
}
}
void acomp_interrupt_unmask(uint8_t idx, uint32_t flag)
{
uint32_t tmpVal;
if (idx == 0) {
/* set clear bit */
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
tmpVal |= (1 << 20);
BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
/* unset clear bit */
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
tmpVal &= (~(1 << 20));
BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal |= (flag << 20);
} else {
/* set clear bit */
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
tmpVal |= (1 << 22);
BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
/* unset clear bit */
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
tmpVal &= (~(1 << 22));
BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal |= (flag << 22);
}
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
}
int acomp_get_result(uint8_t idx)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL);
/* Disable ACOMP first */
if (idx == 0) {
if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP0_OUT_RAW)) {
return 1;
} else {
return 0;
}
} else {
if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP1_OUT_RAW)) {
return 1;
} else {
return 0;
}
}
}

427
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_adc.c
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@@ -1,427 +0,0 @@
/**
* @file hal_adc.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_adc.h"
#include "hal_clock.h"
#include "hal_dma.h"
#include "bl702_glb.h"
#include "bl702_dma.h"
#include "bl702_adc.h"
#include "adc_config.h"
#ifdef BSP_USING_ADC0
static void ADC_IRQ(void);
#endif
static adc_device_t adcx_device[ADC_MAX_INDEX] = {
#ifdef BSP_USING_ADC0
ADC0_CONFIG,
#endif
};
/**
* @brief Check whether Channel Corresponding IO is configed success by Board System
*
* @param pos_list pos channel list
* @param neg_list negative channel list
* @param channelNum channel number
*/
uint8_t adc_check_channel_status(uint8_t *pos_list, uint8_t *neg_list, uint16_t channelNum)
{
uint16_t i = 0;
uint8_t channel_io_reference_table[] = {
GLB_GPIO_PIN_8, /* CH0 IO */
GLB_GPIO_PIN_15, /* CH1 IO */
GLB_GPIO_PIN_17, /* CH2 IO */
GLB_GPIO_PIN_11, /* CH3 IO */
GLB_GPIO_PIN_12, /* CH4 IO */
GLB_GPIO_PIN_14, /* CH5 IO */
GLB_GPIO_PIN_7, /* CH6 IO */
GLB_GPIO_PIN_9, /* CH7 IO */
GLB_GPIO_PIN_18, /* CH8 IO */
GLB_GPIO_PIN_19, /* CH9 IO */
GLB_GPIO_PIN_20, /* CH10 IO */
GLB_GPIO_PIN_21, /* CH11 IO */
};
for (i = 0; i < channelNum; i++) {
if (pos_list[i] > ADC_CHANNEL11) {
continue;
}
if (GLB_GPIO_Get_Fun(channel_io_reference_table[pos_list[i]]) != GPIO_FUN_ANALOG) {
return ERROR;
}
}
return SUCCESS;
}
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int adc_open(struct device *dev, uint16_t oflag)
{
adc_device_t *adc_device = (adc_device_t *)dev;
ADC_CFG_Type adc_cfg = { 0 };
ADC_FIFO_Cfg_Type adc_fifo_cfg = { 0 };
CPU_Interrupt_Disable(GPADC_DMA_IRQn);
ADC_IntMask(ADC_INT_ALL, MASK);
adc_cfg.clkDiv = adc_device->clk_div;
adc_cfg.vref = adc_device->vref;
adc_cfg.resWidth = adc_device->data_width;
adc_cfg.inputMode = adc_device->differential_mode;
adc_cfg.v18Sel = ADC_V18_SELECT;
adc_cfg.v11Sel = ADC_V11_SELECT;
adc_cfg.gain1 = ADC_PGA_GAIN1;
adc_cfg.gain2 = ADC_PGA_GAIN2;
adc_cfg.chopMode = ADC_CHOP_MODE;
adc_cfg.biasSel = ADC_BIAS_SELECT;
adc_cfg.vcm = ADC_PGA_VCM;
adc_cfg.offsetCalibEn = ADC_OFFSET_CALIB_EN;
adc_cfg.offsetCalibVal = ADC_OFFSER_CALIB_VAL;
adc_fifo_cfg.dmaEn = DISABLE;
adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold;
if (oflag & DEVICE_OFLAG_STREAM_TX) {
}
if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) {
#ifdef BSP_USING_ADC0
Interrupt_Handler_Register(GPADC_DMA_IRQn, ADC_IRQ);
#endif
}
if (oflag & DEVICE_OFLAG_DMA_TX) {
}
if (oflag & DEVICE_OFLAG_DMA_RX) {
adc_fifo_cfg.dmaEn = ENABLE;
}
ADC_Disable();
ADC_Enable();
ADC_Reset();
ADC_Init(&adc_cfg);
ADC_FIFO_Cfg(&adc_fifo_cfg);
return 0;
}
/**
* @brief
*
* @param dev
* @return int
*/
int adc_close(struct device *dev)
{
uint32_t tmpVal;
ADC_IntMask(ADC_INT_ALL, MASK);
/* disable convert start */
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CONV_START);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
/*disable adc */
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
/*disable vbat */
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
ADC_Reset();
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int adc_control(struct device *dev, int cmd, void *args)
{
adc_device_t *adc_device = (adc_device_t *)dev;
adc_channel_cfg_t *adc_channel_cfg = (adc_channel_cfg_t *)args;
uint8_t rlt = 0;
switch (cmd) {
case DEVICE_CTRL_SET_INT: {
uint32_t offset = __builtin_ctz((uint32_t)args);
while ((2 <= offset) && (offset < 6)) {
if ((uint32_t)args & (1 << offset)) {
ADC_IntMask(offset, UNMASK);
}
offset++;
}
CPU_Interrupt_Enable(GPADC_DMA_IRQn);
break;
}
case DEVICE_CTRL_CLR_INT: {
uint32_t offset = __builtin_ctz((uint32_t)args);
while ((2 <= offset) && (offset < 6)) {
if ((uint32_t)args & (1 << offset)) {
ADC_IntMask(offset, UNMASK);
}
offset++;
}
CPU_Interrupt_Disable(GPADC_DMA_IRQn);
break;
}
case DEVICE_CTRL_GET_INT:
break;
case DEVICE_CTRL_CONFIG:
break;
case DEVICE_CTRL_ADC_CHANNEL_CONFIG:
if (adc_channel_cfg->num == 1) {
ADC_Channel_Config(*adc_channel_cfg->pos_channel, *adc_channel_cfg->neg_channel, adc_device->continuous_conv_mode);
rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, 1);
} else {
ADC_Scan_Channel_Config(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, adc_channel_cfg->num, adc_device->continuous_conv_mode);
rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, adc_channel_cfg->num);
}
break;
case DEVICE_CTRL_ADC_CHANNEL_START: {
uint32_t regCmd;
/* disable convert start */
regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);
BL702_Delay_US(100);
/* enable convert start */
regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);
} break;
case DEVICE_CTRL_ADC_CHANNEL_STOP: {
uint32_t tmpVal;
/* disable convert start */
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CONV_START);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
break;
}
case DEVICE_CTRL_ADC_VBAT_ON: {
uint32_t tmpVal;
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
break;
}
case DEVICE_CTRL_ADC_VBAT_OFF: {
uint32_t tmpVal;
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
break;
}
case DEVICE_CTRL_ADC_TSEN_ON:
ADC_Tsen_Init(ADC_TSEN_MOD_INTERNAL_DIODE);
break;
case DEVICE_CTRL_ADC_TSEN_OFF:
break;
case DEVICE_CTRL_ATTACH_RX_DMA:
adc_device->rx_dma = (struct device *)args;
break;
case DEVICE_CTRL_ADC_DATA_PARSE: {
adc_data_parse_t *parse = (adc_data_parse_t *)args;
ADC_Parse_Result(parse->input, parse->num, (ADC_Result_Type *)parse->output);
}
break;
default:
break;
}
return rlt;
}
// int adc_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
// {
// return 0;
// }
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
uint32_t adc_fifo_val[32];
int ret = -1;
adc_device_t *adc_device = (adc_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_STREAM_RX) {
if (size > 32)
return -1;
while (ADC_Get_FIFO_Count() < size) {
}
for (uint32_t i = 0; i < size; i++) {
adc_fifo_val[i] = ADC_Read_FIFO();
}
adc_channel_val_t *adc_parse_val = (adc_channel_val_t *)buffer;
ADC_Parse_Result(adc_fifo_val, size, (ADC_Result_Type *)adc_parse_val);
return size;
} else if (dev->oflag & DEVICE_OFLAG_DMA_RX) {
struct device *dma_ch = (struct device *)adc_device->rx_dma;
if (!dma_ch)
return -1;
ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_ADC_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
return ret;
}
return ret;
}
int adc_trim_tsen(uint16_t *tsen_offset)
{
return ADC_Trim_TSEN(tsen_offset);
}
float adc_get_tsen(uint16_t tsen_offset)
{
return TSEN_Get_Temp(tsen_offset);
}
/**
* @brief
*
* @param index
* @param name
* @return int
*/
int adc_register(enum adc_index_type index, const char *name)
{
struct device *dev;
if (ADC_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(adcx_device[index].parent);
dev->open = adc_open;
dev->close = adc_close;
dev->control = adc_control;
dev->write = NULL;
dev->read = adc_read;
dev->type = DEVICE_CLASS_ADC;
dev->handle = NULL;
return device_register(dev, name);
}
/**
* @brief
*
* @param handle
*/
void adc_isr(adc_device_t *handle)
{
if (!handle->parent.callback)
return;
if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET && ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK) {
//handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_POS_SATURATION);
ADC_IntClr(ADC_INT_POS_SATURATION);
}
if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET && ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK) {
//handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_NEG_SATURATION);
ADC_IntClr(ADC_INT_NEG_SATURATION);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) {
ADC_IntClr(ADC_INT_FIFO_UNDERRUN);
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_UNDERRUN);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) {
ADC_IntClr(ADC_INT_FIFO_OVERRUN);
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_OVERRUN);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET && ADC_IntGetMask(ADC_INT_FIFO_READY) == UNMASK) {
ADC_IntClr(ADC_INT_FIFO_READY);
uint32_t adc_count = ADC_Get_FIFO_Count();
uint32_t adc_fifo_val[32];
adc_channel_val_t adc_parse_val[32];
for (uint32_t i = 0; i < adc_count; i++) {
adc_fifo_val[i] = ADC_Read_FIFO();
}
ADC_Parse_Result(adc_fifo_val, adc_count, (ADC_Result_Type *)adc_parse_val);
handle->parent.callback(&handle->parent, (void *)adc_parse_val, adc_count, ADC_EVENT_FIFO);
}
}
#ifdef BSP_USING_ADC0
void ADC_IRQ(void)
{
adc_isr(&adcx_device[ADC0_INDEX]);
}
#endif

477
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_boot2.c
View File

@@ -1,477 +0,0 @@
#include "hal_boot2.h"
#include "hal_flash.h"
#include "bl702_ef_ctrl.h"
#include "bl702_hbn.h"
#include "bl702_glb.h"
#include "bl702_xip_sflash.h"
#include "tzc_sec_reg.h"
#include "hal_gpio.h"
#include "softcrc.h"
#include "hal_sec_hash.h"
/**
* @brief boot2 custom
*
* @param None
* @return uint32
*/
uint32_t hal_boot2_custom(void)
{
return 0;
}
/**
* @brief get efuse Boot2 config
*
* @param g_efuse_cfg
* @param
* @param
* @return None
*/
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg)
{
uint32_t tmp;
uint32_t rootClk;
uint8_t hdiv = 0, bdiv = 0;
/* save bclk fclk div and root clock sel */
bdiv = GLB_Get_BCLK_Div();
hdiv = GLB_Get_HCLK_Div();
rootClk = BL_RD_REG(HBN_BASE, HBN_GLB);
/* change root clock to rc32m for efuse operation */
HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
/* Get sign and aes type*/
EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted);
/* Get hash:aes key slot 0 and slot1*/
EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, 8);
EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id);
/* Get HBN check sign config */
EF_Ctrl_Read_Sw_Usage(0, &tmp);
efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01;
/* restore bclk fclk div and root clock sel */
GLB_Set_System_CLK_Div(hdiv, bdiv);
BL_WR_REG(HBN_BASE, HBN_GLB, rootClk);
__NOP();
__NOP();
__NOP();
__NOP();
}
/**
* @brief reset sec eng clock
*
* @return
*/
void hal_boot2_reset_sec_eng(void)
{
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SEC);
}
/**
* @brief system soft reset
*
* @return
*/
void hal_boot2_sw_system_reset(void)
{
GLB_SW_System_Reset();
}
/**
* @brief
*
* @param flag
* @param
* @param
* @return
*/
void hal_boot2_set_psmode_status(uint32_t flag)
{
HBN_Set_Status_Flag(flag);
}
/**
* @brief
*
* @param
* @param
* @param
* @return flag
*/
uint32_t hal_boot2_get_psmode_status(void)
{
return HBN_Get_Status_Flag();
}
/**
* @brief
*
* @param
* @param
* @param
* @return user define flag
*/
uint32_t hal_boot2_get_user_fw(void)
{
return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET);
}
/**
* @brief clr user define flag
*
* @param
* @param
* @param
* @return
*/
void hal_boot2_clr_user_fw(void)
{
uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET);
*p = 0;
}
/**
* @brief hal_boot2_sboot_finish
*
* @return
*/
void ATTR_TCM_SECTION hal_boot2_sboot_finish(void)
{
uint32_t tmp_val;
tmp_val = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TZC_SEC_TZC_SBOOT_DONE, 0xf);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmp_val);
}
/**
* @brief hal_boot2_uart_gpio_init
*
* @return
*/
void hal_boot2_uart_gpio_init(void)
{
GLB_GPIO_Type gpios[] = { GPIO_PIN_14, GPIO_PIN_15 };
GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 2);
GLB_UART_Fun_Sel((GPIO_PIN_14 % 8), GLB_UART_SIG_FUN_UART0_TXD); // GPIO_FUN_UART1_TX
GLB_UART_Fun_Sel((GPIO_PIN_15 % 8), GLB_UART_SIG_FUN_UART0_RXD);
}
/**
* @brief hal_boot2_pll_init
*
* @return
*/
void hal_boot2_debug_uart_gpio_init(void)
{
GLB_GPIO_Type gpios[] = { GPIO_PIN_17 };
GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 1);
GLB_UART_Fun_Sel((GPIO_PIN_17 % 8), GLB_UART_SIG_FUN_UART1_TXD);
}
/**
* @brief hal_boot2_debug_usb_port_init
*
* @return
*/
#if HAL_BOOT2_SUPPORT_USB_IAP
void hal_boot2_debug_usb_port_init(void)
{
/* must do this , or usb can not be recognized */
cpu_global_irq_disable();
cpu_global_irq_enable();
GLB_GPIO_Type gpios[] = { GPIO_PIN_7, GPIO_PIN_8 };
GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, gpios, 2);
}
#endif
/**
* @brief hal_boot2_debug_uart_gpio_deinit
*
* @return
*/
void hal_boot2_debug_uart_gpio_deinit(void)
{
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0);
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
}
/****************************************************************************/ /**
* @brief Check bootheader crc
*
* @param data: bootheader data pointer
*
* @return boot_error_code type
*
*******************************************************************************/
static uint32_t hal_boot_check_bootheader(struct hal_bootheader_t *header)
{
uint32_t crc_pass = 0;
uint32_t crc;
if (header->bootCfg.bval.crcIgnore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) {
//MSG("Crc ignored\r\n");
crc_pass = 1;
} else {
crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32));
if (header->crc32 == crc) {
crc_pass = 1;
}
}
return crc_pass;
}
/****************************************************************************/ /**
* @brief Check if the input public key is the same as burned in the efuse
*
* @param g_boot_img_cfg: Boot image config pointer
* @param data: Image data pointer
*
* @return boot_error_code type
*
*******************************************************************************/
int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data)
{
struct hal_bootheader_t *header = (struct hal_bootheader_t *)data;
uint32_t crc_pass = 0;
uint32_t i = 0;
uint32_t *phash = (uint32_t *)header->hash;
crc_pass=hal_boot_check_bootheader(header);
if (!crc_pass) {
//MSG_ERR("bootheader crc error\r\n");
//blsp_dump_data((uint8_t *)&crc, 4);
return 0x0204;
}
if (header->bootCfg.bval.notLoadInBoot) {
return 0x0202;
}
/* Get which CPU's img it is*/
for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) {
if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU0_MAGIC,
sizeof(header->magicCode))) {
break;
} else if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU1_MAGIC,
sizeof(header->magicCode))) {
break;
}
}
if (i == HAL_BOOT2_CPU_MAX) {
/* No cpu img magic match */
//MSG_ERR("Magic code error\r\n");
return 0x0203;
}
if(boot_img_cfg==NULL){
return 0;
}
boot_img_cfg->pk_src=i;
boot_img_cfg->img_valid=0;
/* Deal with pll config */
/* Encrypt and sign */
boot_img_cfg->basic_cfg.encrypt_type = header->bootCfg.bval.encrypt_type;
boot_img_cfg->basic_cfg.sign_type = header->bootCfg.bval.sign;
boot_img_cfg->basic_cfg.key_sel = header->bootCfg.bval.key_sel;
/* Xip relative */
boot_img_cfg->basic_cfg.no_segment = header->bootCfg.bval.no_segment;
boot_img_cfg->cpu_cfg[0].cache_enable = header->bootCfg.bval.cache_enable;
boot_img_cfg->basic_cfg.aes_region_lock = header->bootCfg.bval.aes_region_lock;
//boot_img_cfg->cpu_cfg[1].halt_cpu = header->bootCfg.bval.halt_cpu1;
boot_img_cfg->cpu_cfg[0].cache_way_dis = header->bootCfg.bval.cache_way_disable;
boot_img_cfg->basic_cfg.hash_ignore = header->bootCfg.bval.hash_ignore;
/* Firmware len*/
boot_img_cfg->basic_cfg.img_len_cnt= header->img_segment_info.img_len;
/* Boot entry and flash offset */
boot_img_cfg->cpu_cfg[0].boot_entry = header->bootEntry;
boot_img_cfg->basic_cfg.group_image_offset = header->img_start.flash_offset;
boot_img_cfg->cpu_cfg[0].config_enable=1;
boot_img_cfg->cpu_cfg[0].halt_cpu =0;
//MSG("sign %d,encrypt:%d\r\n", boot_img_cfg->sign_type,boot_img_cfg->encrypt_type);
/* Check encrypt and sign match*/
if (g_efuse_cfg.encrypted[i] != 0) {
if (boot_img_cfg->basic_cfg.encrypt_type == 0) {
//MSG_ERR("Encrypt not fit\r\n");
return 0x0205;
}
}
if (g_efuse_cfg.sign[i] !=boot_img_cfg->basic_cfg.sign_type) {
//MSG_ERR("sign not fit\r\n");
boot_img_cfg->basic_cfg.sign_type = g_efuse_cfg.sign[i];
return 0x0206;
}
if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) {
/* In HBN Mode, if user select to ignore hash and sign*/
boot_img_cfg->basic_cfg.hash_ignore = 1;
} else if ((boot_img_cfg->basic_cfg.hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) ||
g_efuse_cfg.sign[i] != 0) {
/* If signed or user not really want to ignore, hash can't be ignored*/
boot_img_cfg->basic_cfg.hash_ignore = 0;
}
if (g_user_hash_ignored) {
boot_img_cfg->basic_cfg.hash_ignore = 1;
}
ARCH_MemCpy_Fast(boot_img_cfg->basic_cfg.hash, header->hash, sizeof(header->hash));
if (boot_img_cfg->basic_cfg.img_len_cnt == 0) {
return 0x0207;
}
return 0;
}
void ATTR_TCM_SECTION hal_boot2_clean_cache(void)
{
/* no need clean again since hal_boot2_set_cache will also clean
unused way,and bl702 no data cache except psram */
}
BL_Err_Type ATTR_TCM_SECTION hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg)
{
return flash_set_cache(cont_read, boot_img_cfg->cpu_cfg[0].cache_enable,
boot_img_cfg->cpu_cfg[0].cache_way_dis,
boot_img_cfg->basic_cfg.group_image_offset);
}
/****************************************************************************/ /**
* @brief get the ram image name and count
*
* @param img_name: ram image name in partition
* @param ram_img_cnt: ram image count that support boot from flash
*
* @return None
*
*******************************************************************************/
void hal_boot2_get_ram_img_cnt(char* img_name[],uint32_t *ram_img_cnt )
{
*ram_img_cnt=0;
}
/****************************************************************************/ /**
* @brief get the ram image info
*
* @param data: bootheader information
* @param image_offset: ram image offset in flash(from of bootheader)
* @param img_len: ram image length
* @param hash: pointer to hash pointer
*
* @return None
*
*******************************************************************************/
void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len,uint8_t **hash)
{
*img_len=0;
}
/****************************************************************************/ /**
* @brief release other cpu to boot up
*
* @param core: core number
* @param boot_addr: boot address
*
* @return None
*
*******************************************************************************/
void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr)
{
}
/****************************************************************************/ /**
* @brief get xip address according to flash addr
*
* @param flash_addr: flash address
*
* @return XIP Address
*
*******************************************************************************/
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr)
{
uint32_t img_offset= SF_Ctrl_Get_Flash_Image_Offset();
if(flash_addr>=img_offset){
return BL702_FLASH_XIP_BASE+(flash_addr-img_offset);
}else{
return 0;
}
}
/****************************************************************************/ /**
* @brief get multi-group count
*
* @param None
*
* @return 1 for multi-group 0 for not
*
*******************************************************************************/
uint32_t hal_boot2_get_grp_count(void)
{
return 1;
}
/****************************************************************************/ /**
* @brief get cpu count
*
* @param None
*
* @return 1 for multi-group 0 for not
*
*******************************************************************************/
uint32_t hal_boot2_get_cpu_count(void)
{
return 1;
}
/****************************************************************************/ /**
* @brief get cpu count
*
* @param None
*
* @return 1 for multi-group 0 for not
*
*******************************************************************************/
uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void)
{
return HAL_BOOT2_SP_FLAG;
}
/****************************************************************************/ /**
* @brief get boot header offset
*
* @param None
*
* @return bootheader offset
*
*******************************************************************************/
uint32_t hal_boot2_get_bootheader_offset(void)
{
return 0x00;
}

342
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_cam.c
View File

@@ -1,342 +0,0 @@
/**
* @file hal_cam.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_cam.h"
#include "bl702_cam.h"
#include "bl702_glb.h"
#ifdef BSP_USING_CAM0
static void CAM0_IRQ(void);
#endif
static cam_device_t camx_device[CAM_MAX_INDEX] = {
#ifdef BSP_USING_CAM0
CAM0_CONFIG,
#endif
};
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int cam_open(struct device *dev, uint16_t oflag)
{
cam_device_t *cam_device = (cam_device_t *)dev;
CAM_CFG_Type camera_cfg = { 0 };
uint32_t tmpVal;
/* Disable camera module */
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
camera_cfg.swMode = cam_device->software_mode;
camera_cfg.frameMode = cam_device->frame_mode;
camera_cfg.yuvMode = cam_device->yuv_format;
camera_cfg.waitCount = 0x40;
camera_cfg.linePol = cam_device->hsp;
camera_cfg.framePol = cam_device->vsp;
camera_cfg.burstType = CAM_BURST_TYPE_INCR16;
camera_cfg.camSensorMode = CAM_SENSOR_MODE_V_AND_H;
camera_cfg.memStart0 = cam_device->cam_write_ram_addr;
camera_cfg.memSize0 = cam_device->cam_write_ram_size;
camera_cfg.frameSize0 = cam_device->cam_frame_size;
/* planar mode*/
camera_cfg.memStart1 = cam_device->cam_write_ram_addr1;
camera_cfg.memSize1 = cam_device->cam_write_ram_size1;
camera_cfg.frameSize1 = cam_device->cam_frame_size1;
CAM_Init(&camera_cfg);
if (oflag & DEVICE_OFLAG_INT_RX) {
#ifdef BSP_USING_CAM0
Interrupt_Handler_Register(CAM_IRQn, CAM0_IRQ);
#endif
}
return 0;
}
/**
* @brief
*
* @param dev
* @return int
*/
int cam_close(struct device *dev)
{
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_CAM);
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int cam_control(struct device *dev, int cmd, void *args)
{
cam_device_t *cam_device = (cam_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT:
if ((uint32_t)args == CAM_FRAME_IT) {
CAM_IntMask(CAM_INT_NORMAL_0, UNMASK);
CPU_Interrupt_Enable(CAM_IRQn);
}
break;
case DEVICE_CTRL_CLR_INT:
if ((uint32_t)args == CAM_FRAME_IT) {
CAM_IntMask(CAM_INT_NORMAL_0, MASK);
CPU_Interrupt_Disable(CAM_IRQn);
}
break;
case DEVICE_CTRL_RESUME: {
uint32_t tmpVal;
/* Enable camera module */
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
} break;
case DEVICE_CTRL_SUSPEND: {
uint32_t tmpVal;
/* Disable camera module */
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
} break;
case DEVICE_CTRL_CAM_FRAME_CUT: {
cam_frame_area_t *cfg = (cam_frame_area_t *)args;
BL_WR_REG(CAM_BASE, CAM_HSYNC_CONTROL, ((cfg->x0 * 2) << 16) + (cfg->x1 * 2));
BL_WR_REG(CAM_BASE, CAM_VSYNC_CONTROL, ((cfg->y0) << 16) + cfg->y1);
} break;
case DEVICE_CTRL_CAM_FRAME_DROP:
if (cam_device->frame_mode == CAM_FRAME_INTERLEAVE_MODE) {
/* Pop one frame */
BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 1);
} else {
/* Pop one frame */
BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 3);
}
break;
case DEVICE_CTRL_CAM_FRAME_WRAP: {
uint32_t tmpVal;
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HW_MODE_FWRAP, ((uint32_t)args) & 0x01);
BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
} break;
default:
break;
}
return 0;
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int cam_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
if (!BL_GET_REG_BITS_VAL(BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT_0)) {
return -1;
}
cam_frame_info_t *frame_info = (cam_frame_info_t *)buffer;
frame_info->frame_addr = BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR0_0);
frame_info->frame_count = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT0_0);
return 0;
}
/**
* @brief
*
* @param index
* @param name
* @return int
*/
int cam_register(enum cam_index_type index, const char *name)
{
struct device *dev;
if (CAM_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(camx_device[index].parent);
dev->open = cam_open;
dev->close = cam_close;
dev->control = cam_control;
dev->write = NULL;
dev->read = cam_read;
dev->type = DEVICE_CLASS_CAMERA;
dev->handle = NULL;
return device_register(dev, name);
}
void cam_isr(cam_device_t *handle)
{
uint32_t tmpVal;
if (!handle->parent.callback)
return;
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR);
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_0)) {
CAM_IntClr(CAM_INT_NORMAL_0);
handle->parent.callback(&handle->parent, NULL, 0, CAM_EVENT_FRAME);
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_1)) {
CAM_IntClr(CAM_INT_NORMAL_1);
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_0)) {
CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_0);
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_1)) {
CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_1);
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_0)) {
CAM_IntClr(CAM_INT_FRAME_OVERWRITE_0);
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_1)) {
CAM_IntClr(CAM_INT_FRAME_OVERWRITE_1);
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_0)) {
CAM_IntClr(CAM_INT_FIFO_OVERWRITE_0);
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_1)) {
CAM_IntClr(CAM_INT_FIFO_OVERWRITE_1);
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_HCNT_INT)) {
CAM_IntClr(CAM_INT_HSYNC_CNT_ERROR);
}
if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_VCNT_INT)) {
CAM_IntClr(CAM_INT_VSYNC_CNT_ERROR);
}
}
#ifdef BSP_USING_CAM0
void CAM0_IRQ(void)
{
cam_isr(&camx_device[CAM0_INDEX]);
}
#endif
/**
* @brief
*
*/
void cam_start(void)
{
uint32_t tmpVal;
/* Enable camera module */
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
}
/**
* @brief
*
*/
void cam_stop(void)
{
uint32_t tmpVal;
/* Disable camera module */
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
}
/**
* @brief
*
* @param pic
* @param len
*/
uint8_t cam_get_one_frame_interleave(uint8_t **pic, uint32_t *len)
{
if (!BL_GET_REG_BITS_VAL(BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT_0)) {
return -1;
}
*pic = (uint8_t *)BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR0_0);
*len = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT0_0);
return 0;
}
uint8_t cam_get_one_frame_planar(CAM_YUV_Mode_Type yuv, uint8_t **picYY, uint32_t *lenYY, uint8_t **picUV, uint32_t *lenUV)
{
CAM_Planar_Frame_Info info;
arch_memset(&info, 0, sizeof(info));
CAM_Planar_Get_Frame_Info(&info);
if (yuv == CAM_YUV400_EVEN || yuv == CAM_YUV400_ODD) {
if (info.validFrames0 == 0 && info.validFrames1 == 0) {
return ERROR;
}
} else {
if (info.validFrames0 == 0 || info.validFrames1 == 0) {
return ERROR;
}
}
*picYY = (uint8_t *)(info.curFrameAddr0);
*lenYY = info.curFrameBytes0;
*picUV = (uint8_t *)(info.curFrameAddr1);
*lenUV = info.curFrameBytes1;
return SUCCESS;
}
void cam_drop_one_frame_interleave(void)
{
/* Pop one frame */
BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 1);
}
void cam_drop_one_frame_planar(void)
{
/* Pop one frame */
BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 3);
}

673
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c
View File

@@ -1,673 +0,0 @@
/**
* @file hal_clock.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "bl702_glb.h"
#include "bl702_pwm.h"
#include "bl702_timer.h"
#include "hal_clock.h"
#if XTAL_TYPE != EXTERNAL_XTAL_32M
static void internal_rc32m_init(void)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, 0);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, 0);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_SEL_AON, 0);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_INT_SEL_AON, 0);
BL_WR_REG(AON_BASE, AON_TSEN, tmpVal);
for (uint32_t i = 0; i < 20000; i++) {
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
if (BL_IS_REG_BIT_SET(BL_RD_REG(GLB_BASE, GLB_CLK_CFG0), GLB_CHIP_RDY))
break;
}
}
#endif
static uint32_t mtimer_get_clk_src_div(void)
{
return (system_clock_get(SYSTEM_CLOCK_BCLK) / 1000 / 1000 - 1);
}
static void peripheral_clock_gate_all()
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
// tmpVal &= (~(1 << BL_AHB_SLAVE1_GPIP));
// tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC_DBG));
// tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC));
tmpVal &= (~(1 << BL_AHB_SLAVE1_TZ1));
tmpVal &= (~(1 << BL_AHB_SLAVE1_TZ2));
tmpVal &= (~(1 << BL_AHB_SLAVE1_DMA));
tmpVal &= (~(1 << BL_AHB_SLAVE1_EMAC));
tmpVal &= (~(1 << BL_AHB_SLAVE1_UART0));
tmpVal &= (~(1 << BL_AHB_SLAVE1_UART1));
tmpVal &= (~(1 << BL_AHB_SLAVE1_SPI));
tmpVal &= (~(1 << BL_AHB_SLAVE1_I2C));
tmpVal &= (~(1 << BL_AHB_SLAVE1_PWM));
tmpVal &= (~(1 << BL_AHB_SLAVE1_TMR));
tmpVal &= (~(1 << BL_AHB_SLAVE1_IRR));
tmpVal &= (~(1 << BL_AHB_SLAVE1_CKS));
tmpVal &= (~(1 << 24)); //QDEC0
tmpVal &= (~(1 << 25)); //QDEC1
tmpVal &= (~(1 << 26)); //QDEC2/I2S
tmpVal &= (~(1 << 27)); //KYS
tmpVal &= (~(1 << BL_AHB_SLAVE1_USB));
tmpVal &= (~(1 << BL_AHB_SLAVE1_CAM));
tmpVal &= (~(1 << BL_AHB_SLAVE1_MJPEG));
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
}
void system_clock_init(void)
{
#if XTAL_TYPE != EXTERNAL_XTAL_32M
internal_rc32m_init();
AON_Power_Off_XTAL();
#endif
/*select root clock*/
GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
#if BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_57P6M
/* fix 57.6M */
SystemCoreClockSet(57.6 * 1000 * 1000);
#endif
/*set fclk/hclk and bclk clock*/
GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV);
/* Set MTimer the same frequency as SystemCoreClock */
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
#ifndef FAST_WAKEUP
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE - ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ);
#endif
#endif
#if XTAL_32K_TYPE == INTERNAL_RC_32K
HBN_32K_Sel(HBN_32K_RC);
HBN_Power_Off_Xtal_32K();
#else
HBN_Power_On_Xtal_32K();
HBN_32K_Sel(HBN_32K_XTAL);
#endif
#if XTAL_TYPE == EXTERNAL_XTAL_32M
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL);
#else
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_RC32M);
#endif
}
void peripheral_clock_init(void)
{
uint32_t tmpVal = 0;
peripheral_clock_gate_all();
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
#if defined(BSP_USING_UART0)
tmpVal |= (1 << BL_AHB_SLAVE1_UART0);
#endif
#if defined(BSP_USING_UART1)
tmpVal |= (1 << BL_AHB_SLAVE1_UART1);
#endif
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, BSP_UART_CLOCK_DIV);
#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_FCLK, BSP_UART_CLOCK_DIV);
#else
#error "please select correct uart clock source"
#endif
#endif
#if defined(BSP_USING_I2C0)
#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
tmpVal |= (1 << BL_AHB_SLAVE1_I2C);
GLB_Set_I2C_CLK(ENABLE, BSP_I2C_CLOCK_DIV);
#else
#error "please select correct i2c clock source"
#endif
#endif
#if defined(BSP_USING_SPI0)
#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
tmpVal |= (1 << BL_AHB_SLAVE1_SPI);
GLB_Set_SPI_CLK(ENABLE, BSP_SPI_CLOCK_DIV);
#else
#error "please select correct spi clock source"
#endif
#endif
#if defined(BSP_USING_TIMER0)
tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
#if BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
/* Configure timer clock source */
uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_FCLK);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);
/* Configure timer clock division */
tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
/* Configure timer clock source */
uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_XTAL);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);
/* Configure timer clock division */
tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
/* Configure timer clock source */
uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_32K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);
/* Configure timer clock division */
tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
/* Configure timer clock source */
uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_1K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);
/* Configure timer clock division */
tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#else
#error "please select correct timer0 clock source"
#endif
#endif
#if defined(BSP_USING_TIMER1)
tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
#if BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
/* Configure timer clock source */
uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_FCLK);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);
/* Configure timer clock division */
tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
/* Configure timer clock source */
uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_XTAL);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);
/* Configure timer clock division */
tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
/* Configure timer clock source */
uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_32K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);
/* Configure timer clock division */
tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp1 = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
/* Configure timer clock source */
uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_1K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);
/* Configure timer clock division */
tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp1 = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#else
#error "please select correct timer1 clock source"
#endif
#endif
#if defined(BSP_USING_WDT)
tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
#if BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
/* Configure watchdog timer clock source */
uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_FCLK);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);
/* Configure watchdog timer clock division */
tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
/* Configure watchdog timer clock source */
uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_XTAL);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);
/* Configure watchdog timer clock division */
tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
/* Configure watchdog timer clock source */
uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_32K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);
/* Configure watchdog timer clock division */
tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
/* Configure watchdog timer clock source */
uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_1K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);
/* Configure watchdog timer clock division */
tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#else
#error "please select correct watchdog timer clock source"
#endif
#endif
#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5)
tmpVal |= (1 << BL_AHB_SLAVE1_PWM);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
uint32_t timeoutCnt = 160 * 1000;
uint32_t tmp_pwm;
uint32_t PWMx;
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
for (int i = 0; i < 5; i++) {
PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));
while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
timeoutCnt--;
if (timeoutCnt == 0) {
return;
}
}
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_32K);
BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
/* Config pwm division */
BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV + 1);
}
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
for (int i = 0; i < 5; i++) {
PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));
while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
timeoutCnt--;
if (timeoutCnt == 0) {
return;
}
}
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_BCLK);
BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
/* Config pwm division */
BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV + 1);
}
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
for (int i = 0; i < 5; i++) {
PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));
while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
timeoutCnt--;
if (timeoutCnt == 0) {
return;
}
}
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_XCLK);
BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
/* Config pwm division */
BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV + 1);
}
#else
#error "please select correct pwm clock source"
#endif
#endif
#if defined(BSP_USING_IR)
tmpVal |= (1 << BL_AHB_SLAVE1_IRR);
GLB_Set_IR_CLK(ENABLE, 0, BSP_IR_CLOCK_DIV);
#endif
#if defined(BSP_USING_I2S0)
tmpVal |= (1 << BL_AHB_SLAVE1_I2S);
GLB_Set_I2S_CLK(ENABLE, GLB_I2S_OUT_REF_CLK_NONE);
#endif
#if defined(BSP_USING_ADC0)
tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
#if BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_ADC_CLOCK_DIV);
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_ADC_CLOCK_DIV);
#else
#error "please select correct adc clock source"
#endif
#endif
#if defined(BSP_USING_DAC0)
tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
#if BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV + 1);
#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, BSP_DAC_CLOCK_DIV + 1);
#else
#error "please select correct dac clock source"
#endif
#endif
#if defined(BSP_USING_CAM0)
tmpVal |= (1 << BL_AHB_SLAVE1_CAM);
#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, BSP_CAM_CLOCK_DIV);
GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
#elif BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_XCLK, BSP_CAM_CLOCK_DIV);
GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
#else
#error "please select correct camera clock source"
#endif
#endif
#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || defined(BSP_USING_QDEC2) || defined(BSP_USING_KEYSCAN)
#ifdef BSP_USING_KEYSCAN
tmpVal |= (1 << 27);
#endif
#if defined(BSP_USING_QDEC0)
tmpVal |= (1 << 24);
#endif
#if defined(BSP_USING_QDEC1)
tmpVal |= (1 << 25);
#endif
#if defined(BSP_USING_QDEC2)
tmpVal |= (1 << 26);
#endif
#if BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
GLB_Set_QDEC_CLK(GLB_QDEC_CLK_F32K, BSP_QDEC_KEYSCAN_CLOCK_DIV);
#elif BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_QDEC_CLK(GLB_QDEC_CLK_XCLK, BSP_QDEC_KEYSCAN_CLOCK_DIV);
#else
#error "please select correct qdec or keyscan clock source"
#endif
#endif
#if defined(BSP_USING_USB)
tmpVal |= (1 << BL_AHB_SLAVE1_USB);
GLB_Set_USB_CLK(1);
#endif
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
}
uint32_t system_clock_get(enum system_clock_type type)
{
switch (type) {
case SYSTEM_CLOCK_ROOT_CLOCK:
if (GLB_Get_Root_CLK_Sel() == 0) {
return 32 * 1000 * 1000;
} else if (GLB_Get_Root_CLK_Sel() == 1)
return 32 * 1000 * 1000;
else {
uint32_t tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL);
if (tmpVal == 0) {
return 57.6 * 1000 * 1000;
} else if (tmpVal == 1) {
return 96 * 1000 * 1000;
} else if (tmpVal == 2) {
return 144 * 1000 * 1000;
} else {
return 0;
}
}
case SYSTEM_CLOCK_FCLK:
return system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / (GLB_Get_HCLK_Div() + 1);
case SYSTEM_CLOCK_BCLK:
return system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / (GLB_Get_HCLK_Div() + 1) / (GLB_Get_BCLK_Div() + 1);
case SYSTEM_CLOCK_XCLK:
return 32000000;
case SYSTEM_CLOCK_32K_CLK:
return 32000;
case SYSTEM_CLOCK_AUPLL:
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ) {
return 12288000;
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ) {
return 11289600;
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ) {
return 5644800;
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ) {
return 24576000;
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ) {
return 24000000;
}
#endif
default:
break;
}
return 0;
}
uint32_t peripheral_clock_get(enum peripheral_clock_type type)
{
uint32_t tmpVal;
uint32_t div;
switch (type) {
#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
case PERIPHERAL_CLOCK_UART:
tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL);
div = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
div = BL_GET_REG_BITS_VAL(div, GLB_UART_CLK_DIV);
if (tmpVal == HBN_UART_CLK_FCLK) {
return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
} else if (tmpVal == HBN_UART_CLK_96M) {
return 96000000 / (div + 1);
}
#endif
#if defined(BSP_USING_SPI0)
case PERIPHERAL_CLOCK_SPI:
tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1);
#endif
#if defined(BSP_USING_I2C0)
case PERIPHERAL_CLOCK_I2C:
tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1);
#endif
#if defined(BSP_USING_I2S0)
case PERIPHERAL_CLOCK_I2S:
return system_clock_get(SYSTEM_CLOCK_AUPLL);
#endif
#if defined(BSP_USING_ADC0)
case PERIPHERAL_CLOCK_ADC:
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
if (tmpVal == GLB_ADC_CLK_AUDIO_PLL) {
return system_clock_get(SYSTEM_CLOCK_AUPLL) / (div + 1);
} else if (tmpVal == GLB_ADC_CLK_XCLK) {
return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
}
#endif
#if defined(BSP_USING_DAC0)
case PERIPHERAL_CLOCK_DAC:
tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
if (tmpVal == GLB_DAC_CLK_AUDIO_PLL) {
return system_clock_get(SYSTEM_CLOCK_AUPLL) / div;
} else if (tmpVal == GLB_DAC_CLK_XCLK) {
return system_clock_get(SYSTEM_CLOCK_XCLK) / div;
}
#endif
#if defined(BSP_USING_TIMER0)
case PERIPHERAL_CLOCK_TIMER0:
tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_1);
div = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
div = BL_GET_REG_BITS_VAL(div, TIMER_TCDR2);
if (tmpVal == TIMER_CLKSRC_FCLK) {
return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
} else if (tmpVal == TIMER_CLKSRC_32K) {
return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
} else if (tmpVal == TIMER_CLKSRC_1K) {
return 1000 / (div + 1);
} else if (tmpVal == TIMER_CLKSRC_XTAL) {
return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
}
#endif
#if defined(BSP_USING_TIMER1)
case PERIPHERAL_CLOCK_TIMER1:
tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_2);
div = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
div = BL_GET_REG_BITS_VAL(div, TIMER_TCDR3);
if (tmpVal == TIMER_CLKSRC_FCLK) {
return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
} else if (tmpVal == TIMER_CLKSRC_32K) {
return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
} else if (tmpVal == TIMER_CLKSRC_1K) {
return 1000 / (div + 1);
} else if (tmpVal == TIMER_CLKSRC_XTAL) {
return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
}
#endif
#if defined(BSP_USING_WDT)
case PERIPHERAL_CLOCK_WDT:
tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT);
div = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
div = BL_GET_REG_BITS_VAL(div, TIMER_WCDR);
if (tmpVal == TIMER_CLKSRC_FCLK) {
return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
} else if (tmpVal == TIMER_CLKSRC_32K) {
return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
} else if (tmpVal == TIMER_CLKSRC_1K) {
return 1000 / (div + 1);
} else if (tmpVal == TIMER_CLKSRC_XTAL) {
return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
}
#endif
#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4)
case PERIPHERAL_CLOCK_PWM:
tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CONFIG);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL);
div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
if (tmpVal == PWM_CLK_XCLK) {
return system_clock_get(SYSTEM_CLOCK_XCLK) / div;
} else if (tmpVal == PWM_CLK_BCLK) {
return system_clock_get(SYSTEM_CLOCK_BCLK) / div;
} else if (tmpVal == PWM_CLK_32K) {
return system_clock_get(SYSTEM_CLOCK_32K_CLK) / div;
}
#endif
#if defined(BSP_USING_CAM)
case PERIPHERAL_CLOCK_CAM:
tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
if (tmpVal == GLB_CAM_CLK_XCLK) {
return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
} else if (tmpVal == GLB_CAM_CLK_DLL96M) {
return 96000000 / (div + 1);
}
#endif
default:
break;
}
(void)(tmpVal);
(void)(div);
return 0;
}
void system_mtimer_clock_init(void)
{
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
}
void system_mtimer_clock_reinit(void)
{
/* reinit clock to 10M */
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 7);
}

104
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_common.c
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@@ -1,104 +0,0 @@
/**
* @file hal_common.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_common.h"
#include "bl702_ef_ctrl.h"
#include "bl702_romdriver.h"
#include "bl702_sec_eng.h"
#include "bl702_l1c.h"
#include "hbn_reg.h"
volatile uint32_t nesting = 0;
void ATTR_TCM_SECTION cpu_global_irq_enable(void)
{
nesting--;
if (nesting == 0) {
__enable_irq();
}
}
void ATTR_TCM_SECTION cpu_global_irq_disable(void)
{
__disable_irq();
nesting++;
}
void hal_por_reset(void)
{
RomDriver_GLB_SW_POR_Reset();
}
void hal_system_reset(void)
{
RomDriver_GLB_SW_System_Reset();
}
void hal_cpu_reset(void)
{
RomDriver_GLB_SW_CPU_Reset();
}
void hal_get_chip_id(uint8_t chip_id[8])
{
EF_Ctrl_Read_MAC_Address(chip_id);
}
void hal_enter_usb_iap(void)
{
BL_WR_WORD(HBN_BASE + HBN_RSV0_OFFSET, 0x00425355); //"\0BSU"
arch_delay_ms(1000);
RomDriver_GLB_SW_POR_Reset();
}
void ATTR_TCM_SECTION hal_jump2app(uint32_t flash_offset)
{
/*flash_offset from 48K to 3.98M*/
if ((flash_offset >= 0xc000) && (flash_offset < (0x400000 - 20 * 1024))) {
void (*app_main)(void) = (void (*)(void))0x23000000;
BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, flash_offset);
L1C_Cache_Flush_Ext();
app_main();
} else {
while(1)
{}
}
}
int hal_get_trng_seed(void)
{
uint32_t seed[8];
uint32_t tmpVal;
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
tmpVal |= (1 << BL_AHB_SLAVE1_SEC);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
Sec_Eng_Trng_Enable();
Sec_Eng_Trng_Read((uint8_t *)seed);
Sec_Eng_Trng_Disable();
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC));
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
return seed[0];
}

329
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dac.c
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@@ -1,329 +0,0 @@
/**
* @file hal_dac.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_dac.h"
#include "hal_dma.h"
#include "hal_clock.h"
#include "bl702_dac.h"
#include "bl702_glb.h"
static dac_device_t dacx_device[] = {
#ifdef BSP_USING_DAC0
DAC_CONFIG,
#endif
};
static uint8_t dac_channel_enable_check = 0;
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int dac_open(struct device *dev, uint16_t oflag)
{
dac_device_t *dac_device = (dac_device_t *)dev;
uint8_t dac_div = 0;
uint32_t tmpVal;
uint32_t dac_clk = peripheral_clock_get(PERIPHERAL_CLOCK_DAC);
if ((GLB_GPIO_Get_Fun(GLB_GPIO_PIN_11) == GPIO_FUN_ANALOG) && (dac_device->channels & DAC_CHANNEL_0)) {
dac_channel_enable_check |= DAC_CHANNEL_0;
}
if ((GLB_GPIO_Get_Fun(GLB_GPIO_PIN_17) == GPIO_FUN_ANALOG) && (dac_device->channels & DAC_CHANNEL_1)) {
dac_channel_enable_check |= DAC_CHANNEL_1;
}
if (dac_channel_enable_check == 0) {
return -1;
}
switch (dac_device->sample_freq) {
case DAC_SAMPLE_FREQ_500KHZ:
dac_div = dac_clk / 500000;
break;
case DAC_SAMPLE_FREQ_8KHZ:
dac_div = dac_clk / 8000;
break;
case DAC_SAMPLE_FREQ_16KHZ:
dac_div = dac_clk / 16000;
break;
case DAC_SAMPLE_FREQ_44P1KHZ:
dac_div = dac_clk / 441000;
break;
default:
break;
}
if (dac_div == 1) {
dac_div = DAC_CLK_DIV_1;
} else if (dac_div == 16) {
dac_div = DAC_CLK_DIV_16;
} else if (dac_div == 32) {
dac_div = DAC_CLK_DIV_32;
} else if (dac_div == 64) {
dac_div = DAC_CLK_DIV_64;
} else
return -2;
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL);
/*dac vref select*/
if (dac_device->vref == DAC_VREF_EXTERNAL) {
if (GLB_GPIO_Get_Fun(GLB_GPIO_PIN_7) != GPIO_FUN_ANALOG)
return -1;
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_REF_SEL);
} else {
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDAC_REF_SEL);
}
BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
/*dac reset*/
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
__NOP();
__NOP();
__NOP();
__NOP();
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
__NOP();
__NOP();
__NOP();
__NOP();
/* dac clear reset */
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
/* Set DAC div */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, dac_div);
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
/* select source */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, GPIP_DAC_ChanA_SRC_REG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, GPIP_DAC_ChanB_SRC_REG);
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
/* GPIP enable or disable channel */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
if (dac_channel_enable_check & DAC_CHANNEL_0) {
tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN);
}
if (dac_channel_enable_check & DAC_CHANNEL_1) {
tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN2);
}
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
/* GLB enable or disable channel */
if (dac_channel_enable_check & DAC_CHANNEL_0) {
/* a channel */
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_IOA_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_A_EN);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_RNG, 0x03);
tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal);
}
if (dac_channel_enable_check & DAC_CHANNEL_1) {
/* b channel */
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_RNG, 0x03);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_IOB_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_B_EN);
tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal);
}
/* GPIP disable DMA */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN);
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
if (oflag & DEVICE_OFLAG_DMA_TX) {
/* GPIP select source */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, GPIP_DAC_ChanA_SRC_DMA);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, GPIP_DAC_ChanB_SRC_DMA);
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
/* GPIP enable DMA */
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
if (dac_channel_enable_check == 2) {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, GPIP_DAC_DMA_FORMAT_1);
} else {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, GPIP_DAC_DMA_FORMAT_0);
}
tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN);
BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
}
return 0;
}
/**
* @brief
*
* @param dev
* @return int
*/
int dac_close(struct device *dev)
{
GLB_GPIP_DAC_ChanA_Cfg_Type chCfg = { 0 };
GLB_GPIP_DAC_Cfg_Type dacCfg = { 0 };
GLB_GPIP_DAC_Init(&dacCfg);
GLB_GPIP_DAC_Set_ChanA_Config(&chCfg);
GLB_GPIP_DAC_Set_ChanB_Config((GLB_GPIP_DAC_ChanB_Cfg_Type *)&chCfg);
GPIP_Set_DAC_DMA_TX_Disable();
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int dac_control(struct device *dev, int cmd, void *args)
{
dac_device_t *dac_device = (dac_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT:
break;
case DEVICE_CTRL_CLR_INT:
break;
case DEVICE_CTRL_GET_INT:
/* code */
break;
case DEVICE_CTRL_CONFIG:
/* code */
break;
case DEVICE_CTRL_RESUME:
break;
case DEVICE_CTRL_SUSPEND:
break;
case DEVICE_CTRL_ATTACH_TX_DMA:
dac_device->tx_dma = (struct device *)args;
break;
default:
break;
}
return 0;
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int dac_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
int ret = 0;
enum dac_sample_frequence channel = (enum dac_sample_frequence)pos;
dac_device_t *dac_device = (dac_device_t *)dev;
uint32_t i = 0;
if (dev->oflag & DEVICE_OFLAG_DMA_TX) {
struct device *dma_ch = (struct device *)dac_device->tx_dma;
if (!dma_ch) {
return -1;
}
ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_DAC_TDR, size);
dma_channel_start(dma_ch);
return ret;
} else if (dev->oflag & DEVICE_OFLAG_STREAM_TX) {
if ((channel & DAC_CHANNEL_ALL) == DAC_CHANNEL_ALL) {
for (i = 0; i < size; i++) {
GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i));
GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i));
}
} else if (channel & DAC_CHANNEL_0) {
for (i = 0; i < size; i++) {
GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i));
}
} else if (channel & DAC_CHANNEL_1) {
for (i = 0; i < size; i++) {
GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i));
}
} else {
return -1;
}
return 0;
}
return -1;
}
/**
* @brief
*
* @param index
* @param name
* @return int
*/
int dac_register(enum dac_index_type index, const char *name)
{
struct device *dev;
if (DAC_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(dacx_device[index].parent);
dev->open = dac_open;
dev->close = dac_close;
dev->control = dac_control;
dev->write = dac_write;
dev->read = NULL;
dev->type = DEVICE_CLASS_DAC;
dev->handle = NULL;
device_register(dev, name);
return 0;
}

431
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c
View File

@@ -1,431 +0,0 @@
/**
* @file hal_dma.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_dma.h"
#include "bl702_dma.h"
#define DMA_CHANNEL_BASE(id_base, ch) ((id_base) + DMA_CHANNEL_OFFSET + (ch)*0x100)
static const uint32_t dma_channel_base[][8] = {
{
DMA_CHANNEL_BASE(DMA_BASE, 0),
DMA_CHANNEL_BASE(DMA_BASE, 1),
DMA_CHANNEL_BASE(DMA_BASE, 2),
DMA_CHANNEL_BASE(DMA_BASE, 3),
DMA_CHANNEL_BASE(DMA_BASE, 4),
DMA_CHANNEL_BASE(DMA_BASE, 5),
DMA_CHANNEL_BASE(DMA_BASE, 6),
DMA_CHANNEL_BASE(DMA_BASE, 7),
}
};
static void DMA0_IRQ(void);
static dma_device_t dmax_device[DMA_MAX_INDEX] = {
#ifdef BSP_USING_DMA0_CH0
DMA0_CH0_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH1
DMA0_CH1_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH2
DMA0_CH2_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH3
DMA0_CH3_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH4
DMA0_CH4_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH5
DMA0_CH5_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH6
DMA0_CH6_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH7
DMA0_CH7_CONFIG,
#endif
};
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int dma_open(struct device *dev, uint16_t oflag)
{
dma_device_t *dma_device = (dma_device_t *)dev;
DMA_Channel_Cfg_Type chCfg = { 0 };
/* Disable all interrupt */
DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
/* Enable uart interrupt*/
CPU_Interrupt_Disable(DMA_ALL_IRQn);
DMA_Disable();
DMA_Channel_Disable(dma_device->ch);
chCfg.ch = dma_device->ch;
chCfg.dir = dma_device->direction;
chCfg.srcPeriph = dma_device->src_req;
chCfg.dstPeriph = dma_device->dst_req;
chCfg.srcAddrInc = dma_device->src_addr_inc;
chCfg.destAddrInc = dma_device->dst_addr_inc;
chCfg.srcBurstSzie = dma_device->src_burst_size;
chCfg.dstBurstSzie = dma_device->dst_burst_size;
chCfg.srcTransfWidth = dma_device->src_width;
chCfg.dstTransfWidth = dma_device->dst_width;
DMA_Channel_Init(&chCfg);
DMA_Enable();
Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ);
/* Enable uart interrupt*/
CPU_Interrupt_Enable(DMA_ALL_IRQn);
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int dma_control(struct device *dev, int cmd, void *args)
{
dma_device_t *dma_device = (dma_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK);
break;
case DEVICE_CTRL_CLR_INT:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK);
break;
case DEVICE_CTRL_GET_INT:
break;
case DEVICE_CTRL_CONFIG:
break;
case DEVICE_CTRL_DMA_CHANNEL_UPDATE:
DMA_LLI_Update(dma_device->ch, (uint32_t)args);
break;
case DEVICE_CTRL_DMA_CHANNEL_GET_STATUS:
return DMA_Channel_Is_Busy(dma_device->ch);
case DEVICE_CTRL_DMA_CHANNEL_START:
DMA_Channel_Enable(dma_device->ch);
break;
case DEVICE_CTRL_DMA_CHANNEL_STOP:
DMA_Channel_Disable(dma_device->ch);
break;
case DEVICE_CTRL_DMA_CONFIG_SI: {
uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, ((uint32_t)args) & 0x01);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal);
} break;
case DEVICE_CTRL_DMA_CONFIG_DI: {
uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, ((uint32_t)args) & 0x01);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal);
} break;
default:
break;
}
return 0;
}
/**
* @brief
*
* @param dev
* @return int
*/
int dma_close(struct device *dev)
{
dma_device_t *dma_device = (dma_device_t *)dev;
DMA_Channel_Cfg_Type chCfg = { 0 };
DMA_Channel_Disable(dma_device->ch);
DMA_Channel_Init(&chCfg);
return 0;
}
int dma_register(enum dma_index_type index, const char *name)
{
struct device *dev;
if (DMA_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(dmax_device[index].parent);
dev->open = dma_open;
dev->close = dma_close;
dev->control = dma_control;
// dev->write = dma_write;
// dev->read = dma_read;
dev->type = DEVICE_CLASS_DMA;
dev->handle = NULL;
return device_register(dev, name);
}
static BL_Err_Type dma_scan_unregister_device(uint8_t *allocate_index)
{
struct device *dev;
dlist_t *node;
uint8_t dma_index = 0;
uint32_t dma_handle[DMA_MAX_INDEX];
for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
dma_handle[dma_index] = 0xff;
}
/* get registered dma handle list*/
dlist_for_each(node, device_get_list_header())
{
dev = dlist_entry(node, struct device, list);
if (dev->type == DEVICE_CLASS_DMA) {
dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET;
}
}
for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
if (dma_handle[dma_index] == 0xff) {
*allocate_index = dma_index;
return SUCCESS;
}
}
return ERROR;
}
int dma_allocate_register(const char *name)
{
struct device *dev;
uint8_t index;
if (DMA_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
if (dma_scan_unregister_device(&index) == ERROR) {
return -DEVICE_ENOSPACE;
}
dev = &(dmax_device[index].parent);
dev->open = dma_open;
dev->close = dma_close;
dev->control = dma_control;
// dev->write = dma_write;
// dev->read = dma_read;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_DMA;
dev->handle = NULL;
return device_register(dev, name);
}
/**
* @brief
*
* @param dev
* @param src_addr
* @param dst_addr
* @param transfer_size
* @return int
*/
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size)
{
#if defined(BSP_USING_DMA0_CH0) || defined(BSP_USING_DMA0_CH1) || defined(BSP_USING_DMA0_CH2) || defined(BSP_USING_DMA0_CH3) || \
defined(BSP_USING_DMA0_CH4) || defined(BSP_USING_DMA0_CH5) || defined(BSP_USING_DMA0_CH6) || defined(BSP_USING_DMA0_CH7)
uint32_t malloc_count;
uint32_t remain_len;
uint32_t actual_transfer_len = 0;
uint32_t actual_transfer_offset = 0;
dma_control_data_t dma_ctrl_cfg;
dma_device_t *dma_device = (dma_device_t *)dev;
DMA_Channel_Disable(dma_device->ch);
if (transfer_size == 0) {
return 0;
}
switch (dma_device->src_width) {
case DMA_TRANSFER_WIDTH_8BIT:
actual_transfer_offset = 4095;
actual_transfer_len = transfer_size;
break;
case DMA_TRANSFER_WIDTH_16BIT:
if (transfer_size % 2) {
return -1;
}
actual_transfer_offset = 4095 << 1;
actual_transfer_len = transfer_size >> 1;
break;
case DMA_TRANSFER_WIDTH_32BIT:
if (transfer_size % 4) {
return -1;
}
actual_transfer_offset = 4095 << 2;
actual_transfer_len = transfer_size >> 2;
break;
default:
return -3;
break;
}
dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL));
malloc_count = actual_transfer_len / 4095;
remain_len = actual_transfer_len % 4095;
if (remain_len) {
malloc_count++;
}
dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count);
if (dma_device->lli_cfg) {
/*transfer_size will be integer multiple of 4095*n or 4095*2*n or 4095*4*n,(n>0) */
for (uint32_t i = 0; i < malloc_count; i++) {
dma_device->lli_cfg[i].src_addr = src_addr;
dma_device->lli_cfg[i].dst_addr = dst_addr;
dma_device->lli_cfg[i].nextlli = 0;
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
if (dma_ctrl_cfg.bits.SI) {
src_addr += actual_transfer_offset;
}
if (dma_ctrl_cfg.bits.DI) {
dst_addr += actual_transfer_offset;
}
if (i == malloc_count - 1) {
if (remain_len) {
dma_ctrl_cfg.bits.TransferSize = remain_len;
}
dma_ctrl_cfg.bits.I = 1;
if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) {
dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0];
}
}
if (i) {
dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i];
}
dma_device->lli_cfg[i].cfg = dma_ctrl_cfg;
}
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_LLI, dma_device->lli_cfg[0].nextlli);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, dma_device->lli_cfg[0].cfg.WORD);
} else {
return -2;
}
#endif
return 0;
}
/**
* @brief
*
* @param handle
*/
void dma_channel_isr(dma_device_t *handle)
{
uint32_t tmpVal;
uint32_t intClr;
/* Get DMA register */
uint32_t DMAChs = DMA_BASE;
if (!handle->parent.callback) {
return;
}
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle->ch)) != 0) {
/* Clear interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);
intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);
intClr |= (1 << handle->ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);
BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);
handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_TCOMPLETED);
}
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle->ch)) != 0) {
/*Clear interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);
intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);
intClr |= (1 << handle->ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);
BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);
handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR);
}
}
/**
* @brief
*
*/
void DMA0_IRQ(void)
{
for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) {
dma_channel_isr(&dmax_device[i]);
}
}

569
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_emac.c
View File

@@ -1,569 +0,0 @@
/**
* @file hal_emac.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "bl702_emac.h"
#include "bl702_glb.h"
#include "hal_emac.h"
#ifndef MSG
#define MSG(a,...)
#endif
#define EMAC_USE_INSIDE_CLOCK (0)
#define TAG "EMAC_BD: "
static EMAC_Handle_Type ethHandle;
static EMAC_Handle_Type *thiz = NULL;
/**
* @brief
*
*/
static void emac_gpio_init(void)
{
uint8_t emacPins[] = { GLB_GPIO_PIN_0, GLB_GPIO_PIN_1, GLB_GPIO_PIN_2,
GLB_GPIO_PIN_7, GLB_GPIO_PIN_8,
GLB_GPIO_PIN_18, GLB_GPIO_PIN_19, GLB_GPIO_PIN_20, GLB_GPIO_PIN_21, GLB_GPIO_PIN_22 };
GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_EMAC);
GLB_GPIO_Func_Init(GPIO_FUN_ETHER_MAC, (GLB_GPIO_Type *)emacPins, sizeof(emacPins));
}
/**
* @brief
*
* @param bdt
* @return int
*/
static uint32_t emac_bd_get_cur_active(EMAC_BD_TYPE_e bdt)
{
uint32_t bd = 0;
bd = BL_RD_REG(EMAC_BASE, EMAC_TX_BD_NUM);
if (bdt == EMAC_BD_TYPE_TX) {
bd &= EMAC_TXBDPTR_MSK;
bd >>= EMAC_TXBDPTR_POS;
}
if (bdt == EMAC_BD_TYPE_RX) {
bd &= EMAC_RXBDPTR_MSK;
bd >>= EMAC_RXBDPTR_POS;
}
return bd;
}
/**
* @brief
*
* @param index
* @return int
*/
static int emac_bd_rx_enqueue(uint32_t index)
{
BL_Err_Type err = SUCCESS;
thiz->rxIndexEMAC = index;
return err;
}
/**
* @brief
*
* @param index
* @return int
*/
static void emac_bd_rx_on_err(uint32_t index)
{
/* to do index - 1 */
// uint32_t tmp_bd = 0;
// tmp_bd = BL_RD_REG(EMAC_BASE, EMAC_TX_BD_NUM);
// if (index == tmp_bd) {
// index += (tmp_bd - 1);
// } else {
// index -= 1;
// }
// MSG("i:%x,csl%x\r\n", 5, thiz->bd[5].C_S_L);
// MSG("i:%x,csl%x\r\n", 6, thiz->bd[6].C_S_L);
// MSG("i:%x,csl%x\r\n", 7, thiz->bd[7].C_S_L);
// MSG("i:%x,csl%x\r\n", 8, thiz->bd[8].C_S_L);
// MSG("i:%x,csl%x\r\n", 9, thiz->bd[9].C_S_L);
/* handle error */
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_OR)) {
MSG("EMAC RX OR Error at %s:%d\r\n", __func__, __LINE__);
}
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_RE)) {
MSG("MAC RX RE Error at %s:%d\r\n", __func__, __LINE__);
}
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_DN)) {
MSG("MAC RX DN Error at %s:%d\r\n", __func__, __LINE__);
}
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_TL)) {
MSG("MAC RX TL Error at %s:%d\r\n", __func__, __LINE__);
}
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_CRC)) {
MSG("MAC RX CRC Error at %s:%d\r\n", __func__, __LINE__);
}
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_LC)) {
MSG("MAC RX LC Error at %s:%d\r\n", __func__, __LINE__);
}
thiz->bd[index].C_S_L &= ~0xff;
/* RX BD is ready for RX */
thiz->bd[index].C_S_L |= EMAC_BD_FIELD_MSK(RX_E);
}
/**
* @brief this func will be called in ISR
*
* @param index
* @return int
*/
static int emac_bd_tx_dequeue(uint32_t index)
{
BL_Err_Type err = SUCCESS;
EMAC_BD_Desc_Type *DMADesc;
thiz->txIndexEMAC = index;
DMADesc = &thiz->bd[thiz->txIndexEMAC];
/* release this tx BD to SW (HW will do this) */
DMADesc->C_S_L &= EMAC_BD_FIELD_UMSK(TX_RD);
return err;
}
/**
* @brief
*
* @param index
* @return int
*/
static void emac_bd_tx_on_err(uint32_t index)
{
/* handle error */
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_UR)) {
MSG("%s:%d\r\n", __func__, __LINE__);
}
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RTRY)) {
MSG("%s:%d\r\n", __func__, __LINE__);
}
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RL)) {
MSG("%s:%d\r\n", __func__, __LINE__);
}
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_LC)) {
MSG("%s:%d\r\n", __func__, __LINE__);
}
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_DF)) {
MSG("%s:%d\r\n", __func__, __LINE__);
}
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_CS)) {
MSG("%s:%d\r\n", __func__, __LINE__);
}
thiz->bd[index].C_S_L &= ~0xff;
}
/**
* @brief
*
*/
__WEAK void emac_tx_done_callback_app(void)
{
}
/**
* @brief
*
*/
static void emac_tx_done_callback(void)
{
uint32_t index = 0;
index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX);
emac_bd_tx_dequeue(index);
emac_tx_done_callback_app();
}
/**
* @brief
*
*/
__WEAK void emac_tx_error_callback_app(void)
{
}
/**
* @brief
*
*/
static void emac_tx_error_callback(void)
{
uint32_t index = 0;
index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX);
emac_bd_tx_on_err(index);
}
/**
* @brief
*
*/
__WEAK void emac_rx_done_callback_app(void)
{
}
/**
* @brief
*
*/
static void emac_rx_done_callback(void)
{
uint32_t index = 0;
index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX);
emac_bd_rx_enqueue(index);
emac_rx_done_callback_app();
}
/**
* @brief
*
*/
__WEAK void emac_rx_error_callback_app(void)
{
}
/**
* @brief
*
*/
static void emac_rx_error_callback(void)
{
uint32_t index;
index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX);
emac_bd_rx_on_err(index);
emac_rx_error_callback_app();
}
/**
* @brief
*
*/
__WEAK void emac_rx_busy_callback_app(void)
{
}
/**
* @brief
*
*/
static void emac_rx_busy_callback(void)
{
MSG("EMAC Rx busy at %s:%d\r\n", __func__, __LINE__);
emac_rx_busy_callback_app();
}
/**
* @brief
*
* @param emac_cfg
* @return int
*/
int emac_init(emac_device_t *emac_cfg)
{
EMAC_CFG_Type emacCfg = {
.recvSmallFrame = ENABLE, /*!< Receive small frmae or not */
.recvHugeFrame = DISABLE, /*!< Receive huge frmae(>64K bytes) or not */
.padEnable = ENABLE, /*!< Enable padding for frame which is less than MINFL or not */
.crcEnable = ENABLE, /*!< Enable hardware CRC or not */
.noPreamble = DISABLE, /*!< Enable preamble or not */
.recvBroadCast = ENABLE, /*!< Receive broadcast frame or not */
.interFrameGapCheck = ENABLE, /*!< Check inter frame gap or not */
.miiNoPreamble = ENABLE, /*!< Enable MII interface preamble or not */
.miiClkDiv = 49, /*!< MII interface clock divider from bus clock */
.maxTxRetry = 16, /*!< Maximum tx retry count */
.interFrameGapValue = 24, /*!< Inter frame gap vaule in clock cycles(default 24)*/
.minFrameLen = 64, /*!< Minimum frame length */
.maxFrameLen = ETH_MAX_PACKET_SIZE, /*!< Maximum frame length */
.collisionValid = 16, /*!< Collision valid value */
.macAddr[0] = 0x18, /*!< MAC Address */
.macAddr[1] = 0xB0,
.macAddr[2] = 0x09,
.macAddr[3] = 0x00,
.macAddr[4] = 0x12,
.macAddr[5] = 0x34,
};
BL_Err_Type err = SUCCESS;
/* init emac giio */
emac_gpio_init();
memcpy(emacCfg.macAddr, emac_cfg->mac_addr, 6);
#if EMAC_USE_INSIDE_CLOCK
//enable audio clock */
PDS_Enable_PLL_Clk(PDS_PLL_CLK_48M);
PDS_Set_Audio_PLL_Freq(AUDIO_PLL_50000000_HZ);
GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_INSIDE_50M);
#else
GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_OUTSIDE_50M);
#endif
GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_EMAC);
//GLB_Invert_ETH_RX_CLK(0);
//GLB_Invert_ETH_TX_CLK(0);
EMAC_Init(&emacCfg);
EMAC_Int_Callback_Install(EMAC_INT_TX_DONE_IDX, emac_tx_done_callback);
EMAC_Int_Callback_Install(EMAC_INT_TX_ERROR_IDX, emac_tx_error_callback);
EMAC_Int_Callback_Install(EMAC_INT_RX_DONE_IDX, emac_rx_done_callback);
EMAC_Int_Callback_Install(EMAC_INT_RX_ERROR_IDX, emac_rx_error_callback);
EMAC_Int_Callback_Install(EMAC_INT_RX_BUSY_IDX, emac_rx_busy_callback);
CPU_Interrupt_Enable(EMAC_IRQn);
EMAC_ClrIntStatus(EMAC_INT_ALL);
EMAC_IntMask(EMAC_INT_ALL, UNMASK);
//EMAC_Enable();
return err;
}
/**
* @brief
*
* @param eth_tx_buff
* @param tx_buf_count
* @param eth_rx_buff
* @param rx_buf_count
* @return int
*/
int emac_bd_init(uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count)
{
BL_Err_Type err = SUCCESS;
thiz = &ethHandle;
/* init the BDs in emac with buffer address */
err = EMAC_DMADescListInit(thiz, (uint8_t *)eth_tx_buff, tx_buf_count,
(uint8_t *)eth_rx_buff, rx_buf_count);
return err;
}
/**
* @brief
*
* @param flags
* @param len
* @param data_in
* @return int
*/
int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in)
{
BL_Err_Type err = SUCCESS;
EMAC_BD_Desc_Type *DMADesc;
DMADesc = &thiz->bd[thiz->txIndexCPU];
if (FULL_PACKET == flags) {
// MSG("full packet,len:%d\r\n", len);
flags = (EMAC_TX_COMMON_FLAGS | EMAC_BD_FIELD_MSK(TX_EOF));
} else if (NOFULL_PACKET == flags) {
// MSG("nofull packet\r\n");
flags = EMAC_TX_COMMON_FLAGS;
}
if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(TX_RD)) {
/* no free BD, lost sync with DMA TX? */
err = NORESC;
// MSG_ERR(TAG"%s:%d\n", __func__, __LINE__);
} else {
DMADesc->Buffer = (uint32_t)data_in;
// MSG("tx q flags:%d,len:%d,data:0x%x\r\n", flags, len, data_in);
// ARCH_MemCpy_Fast((void *)DMADesc->Buffer, data_in, len);
DMADesc->C_S_L = flags | (len << BD_TX_LEN_POS);
/* move to next TX BD */
if ((++thiz->txIndexCPU) > thiz->txBuffLimit) {
/* the last BD */
DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(TX_WR);
/* wrap back */
thiz->txIndexCPU = 0;
}
}
return err;
}
/**
* @brief
*
* @param flags
* @param len
* @param data_out
* @return int
*/
int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out)
{
BL_Err_Type err = SUCCESS;
EMAC_BD_Desc_Type *DMADesc;
DMADesc = &thiz->bd[thiz->rxIndexCPU];
if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(RX_E)) {
/* current RX BD is empty */
err = NORESC;
*len = 0;
} else {
*len = (thiz->bd[thiz->rxIndexCPU].C_S_L & EMAC_BD_FIELD_MSK(RX_LEN)) >> BD_RX_LEN_POS;
if (data_out) {
ARCH_MemCpy_Fast(data_out, (const void *)DMADesc->Buffer, *len);
}
/* RX BD can be used for another receive */
DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_E);
/* move to next RX BD */
if ((++thiz->rxIndexCPU) > thiz->rxBuffLimit) {
/* the last BD */
DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_WR);
/* wrap back */
thiz->rxIndexCPU = thiz->txBuffLimit + 1;
}
}
return err;
}
/**
* @brief
*
* @param phyAddress
* @return int
*/
int emac_phy_set_address(uint16_t phyAddress)
{
EMAC_Phy_SetAddress(phyAddress);
return 0;
}
/**
* @brief
*
* @param fullDuplex
* @return int
*/
int emac_phy_config_full_duplex(uint8_t fullDuplex)
{
EMAC_Phy_Set_Full_Duplex(fullDuplex);
return 0;
}
/**
* @brief
*
* @param phyReg
* @param regValue
* @return int
*/
int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue)
{
if (EMAC_Phy_Read(phyReg, regValue) != SUCCESS) {
return -1;
}
return 0;
}
/**
* @brief
*
* @param phyReg
* @param regValue
* @return int
*/
int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue)
{
if (EMAC_Phy_Write(phyReg, regValue) != SUCCESS) {
return -1;
}
return 0;
}
int emac_stop(void)
{
return EMAC_Disable();
}
int emac_start(void)
{
EMAC_Enable();
return 0;
}
int emac_start_tx(void)
{
return EMAC_Enable_TX();
}
int emac_stop_tx(void)
{
return EMAC_Disable_TX();
}
int emac_start_rx(void)
{
return EMAC_Enable_RX();
}
int emac_stop_rx(void)
{
return EMAC_Disable_RX();
}

346
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_flash.c
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@@ -1,346 +0,0 @@
/**
* @file hal_flash.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "bl702_glb.h"
#include "bl702_xip_sflash.h"
#include "bl702_xip_sflash_ext.h"
#include "bl702_sf_cfg.h"
#include "bl702_sf_cfg_ext.h"
#include "hal_flash.h"
static uint32_t g_jedec_id = 0;
static SPI_Flash_Cfg_Type g_flash_cfg;
/**
* @brief flash_get_jedecid
*
* @return BL_Err_Type
*/
uint32_t flash_get_jedecid(void)
{
uint32_t jid = 0;
jid = ((g_jedec_id&0xff)<<16) + (g_jedec_id&0xff00) + ((g_jedec_id&0xff0000)>>16);
return jid;
}
/**
* @brief flash_get_cfg
*
* @return BL_Err_Type
*/
BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len)
{
*cfg_addr = (uint8_t *)&g_flash_cfg;
*len = sizeof(SPI_Flash_Cfg_Type);
return SUCCESS;
}
/**
* @brief flash_set_qspi_enable
*
* @return BL_Err_Type
*/
static BL_Err_Type ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg)
{
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
SFlash_Qspi_Enable(p_flash_cfg);
}
return SUCCESS;
}
/**
* @brief flash_set_l1c_wrap
*
* @return BL_Err_Type
*/
static BL_Err_Type ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg)
{
if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) {
L1C_Set_Wrap(DISABLE);
} else {
L1C_Set_Wrap(ENABLE);
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
SFlash_SetBurstWrap(p_flash_cfg);
}
}
return SUCCESS;
}
/**
* @brief flash_config_init
*
* @return BL_Err_Type
*/
static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id)
{
BL_Err_Type ret = ERROR;
uint32_t jid = 0;
uint32_t offset = 0;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
XIP_SFlash_State_Save(p_flash_cfg, &offset);
SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid);
arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
jid &= 0xFFFFFF;
g_jedec_id = jid;
ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg);
if (ret == SUCCESS) {
p_flash_cfg->mid = (jid & 0xff);
}
/* Set flash controler from p_flash_cfg */
flash_set_qspi_enable(p_flash_cfg);
flash_set_l1c_wrap(p_flash_cfg);
XIP_SFlash_State_Restore(p_flash_cfg, p_flash_cfg->ioMode & 0x0f, offset);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}
/**
* @brief multi flash adapter
*
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_init(void)
{
BL_Err_Type ret = ERROR;
uint8_t clkDelay = 1;
uint8_t clkInvert = 1;
uint32_t jedec_id = 0;
cpu_global_irq_disable();
L1C_Cache_Flush_Ext();
SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg);
L1C_Cache_Flush_Ext();
cpu_global_irq_enable();
if (g_flash_cfg.mid != 0xff) {
return SUCCESS;
}
clkDelay = g_flash_cfg.clkDelay;
clkInvert = g_flash_cfg.clkInvert;
g_flash_cfg.ioMode = g_flash_cfg.ioMode & 0x0f;
ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
#if 0
MSG("flash ID = %08x\r\n", jedec_id);
bflb_platform_dump((uint8_t *)&g_flash_cfg, sizeof(g_flash_cfg));
if (ret != SUCCESS) {
MSG("flash config init fail!\r\n");
}
#endif
g_flash_cfg.clkDelay = clkDelay;
g_flash_cfg.clkInvert = clkInvert;
return ret;
}
/**
* @brief read jedec id
*
* @param data
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_read_jedec_id(uint8_t *data)
{
uint32_t jid = 0;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
XIP_SFlash_GetJedecId_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, (uint8_t *)&jid);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
jid &= 0xFFFFFF;
arch_memcpy(data, (void *)&jid, 4);
return SUCCESS;
}
/**
* @brief read flash data via xip
*
* @param addr
* @param data
* @param len
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len)
{
cpu_global_irq_disable();
L1C_Cache_Flush_Ext();
XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
L1C_Cache_Flush_Ext();
cpu_global_irq_enable();
return SUCCESS;
}
/**
* @brief flash read data
*
* @param addr
* @param data
* @param len
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_read(uint32_t addr, uint8_t *data, uint32_t len)
{
BL_Err_Type ret = ERROR;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
ret = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}
/**
* @brief flash write data
*
* @param addr
* @param data
* @param len
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_write(uint32_t addr, uint8_t *data, uint32_t len)
{
BL_Err_Type ret = ERROR;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
ret = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}
/**
* @brief flash erase
*
* @param startaddr
* @param endaddr
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_erase(uint32_t startaddr, uint32_t len)
{
BL_Err_Type ret = ERROR;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
ret = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, startaddr, startaddr + len - 1);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}
/**
* @brief flash write protect set
*
* @param protect
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_write_protect_set(SFlash_Protect_Kh25v40_Type protect)
{
BL_Err_Type ret = ERROR;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
ret = XIP_SFlash_KH25V40_Write_Protect_Need_Lock(&g_flash_cfg, protect);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}
/**
* @brief flash clear status register
*
* @param None
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_clear_status_register(void)
{
BL_Err_Type ret = ERROR;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
ret = XIP_SFlash_Clear_Status_Register_Need_Lock(&g_flash_cfg);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}
/**
* @brief set flash cache
*
* @param cont_read
* @param cache_enable
* @param cache_way_disable
* @param flash_offset
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
{
uint32_t tmp[1];
BL_Err_Type stat;
SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
XIP_SFlash_Opt_Enter();
/* To make it simple, exit cont read anyway */
SFlash_Reset_Continue_Read(&g_flash_cfg);
if (g_flash_cfg.cReadSupport == 0) {
cont_read = 0;
}
if (cont_read == 1) {
stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
if (SUCCESS != stat) {
XIP_SFlash_Opt_Exit();
return ERROR;
}
}
/* Set default value */
L1C_Cache_Enable_Set(0xf);
if (cache_enable) {
SF_Ctrl_Set_Flash_Image_Offset(flash_offset);
SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable);
}
XIP_SFlash_Opt_Exit();
return SUCCESS;
}

234
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c
View File

@@ -1,234 +0,0 @@
/**
* @file hal_gpio.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "bl702_glb.h"
#include "bl702_gpio.h"
#include "hal_gpio.h"
static void GPIO_IRQ(void);
struct gpio_int_cfg_private {
slist_t list;
uint32_t pin;
void (*cbfun)(uint32_t pin);
};
static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head);
/**
* @brief
*
* @param pin
* @param mode
*/
void gpio_set_mode(uint32_t pin, uint32_t mode)
{
GLB_GPIO_Cfg_Type gpio_cfg;
gpio_cfg.gpioFun = GPIO_FUN_GPIO;
gpio_cfg.gpioPin = pin;
gpio_cfg.drive = 0;
gpio_cfg.smtCtrl = 1;
switch (mode) {
case GPIO_OUTPUT_MODE:
gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
gpio_cfg.pullType = GPIO_PULL_NONE;
break;
case GPIO_OUTPUT_PP_MODE:
gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
gpio_cfg.pullType = GPIO_PULL_UP;
break;
case GPIO_OUTPUT_PD_MODE:
gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
gpio_cfg.pullType = GPIO_PULL_DOWN;
break;
case GPIO_INPUT_MODE:
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
gpio_cfg.pullType = GPIO_PULL_NONE;
break;
case GPIO_INPUT_PP_MODE:
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
gpio_cfg.pullType = GPIO_PULL_UP;
break;
case GPIO_INPUT_PD_MODE:
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
gpio_cfg.pullType = GPIO_PULL_DOWN;
break;
case GPIO_HZ_MODE:
GLB_GPIO_Set_HZ(pin);
default:
CPU_Interrupt_Disable(GPIO_INT0_IRQn);
GLB_GPIO_IntMask(pin, MASK);
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) {
gpio_cfg.pullType = GPIO_PULL_DOWN;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
}
else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) {
gpio_cfg.pullType = GPIO_PULL_UP;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
}
else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) {
gpio_cfg.pullType = GPIO_PULL_DOWN;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_LEVEL);
}
else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) {
gpio_cfg.pullType = GPIO_PULL_UP;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL);
}
else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) {
gpio_cfg.pullType = GPIO_PULL_DOWN;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
}
else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) {
gpio_cfg.pullType = GPIO_PULL_UP;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
}
else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) {
gpio_cfg.pullType = GPIO_PULL_DOWN;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_LEVEL);
}
else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) {
gpio_cfg.pullType = GPIO_PULL_UP;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL);
}
else {
return;
}
break;
}
GLB_GPIO_Init(&gpio_cfg);
}
/**
* @brief
*
* @param pin
* @param value
*/
void gpio_write(uint32_t pin, uint32_t value)
{
uint32_t tmp = BL_RD_REG(GLB_BASE, GLB_GPIO_OUTPUT);
if (value)
tmp |= (1 << pin);
else
tmp &= ~(1 << pin);
BL_WR_REG(GLB_BASE, GLB_GPIO_OUTPUT, tmp);
}
/**
* @brief
*
* @param pin
*/
void gpio_toggle(uint32_t pin)
{
uint32_t tmp = BL_RD_REG(GLB_BASE, GLB_GPIO_OUTPUT);
tmp ^= (1 << pin);
BL_WR_REG(GLB_BASE, GLB_GPIO_OUTPUT, tmp);
}
/**
* @brief
*
* @param pin
* @return int
*/
int gpio_read(uint32_t pin)
{
return ((BL_RD_REG(GLB_BASE, GLB_GPIO_INPUT) & (1 << pin)) ? 1 : 0);
}
/**
* @brief
*
* @param pin
* @param cbFun
*/
void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin))
{
struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private));
int_cfg->cbfun = cbfun;
int_cfg->pin = pin;
slist_add_tail(&gpio_int_head, &int_cfg->list);
CPU_Interrupt_Disable(GPIO_INT0_IRQn);
Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_IRQ);
CPU_Interrupt_Enable(GPIO_INT0_IRQn);
}
/**
* @brief
*
* @param pin
* @param enabled
*/
void gpio_irq_enable(uint32_t pin, uint8_t enabled)
{
if (enabled) {
GLB_GPIO_IntMask(pin, UNMASK);
} else {
GLB_GPIO_IntMask(pin, MASK);
}
}
static void GPIO_IRQ(void)
{
slist_t *i;
uint32_t timeOut = 0;
#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
slist_for_each(i, &gpio_int_head)
{
struct gpio_int_cfg_private *int_cfg = slist_entry(i, struct gpio_int_cfg_private, list);
if (SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) {
int_cfg->cbfun(int_cfg->pin);
GLB_GPIO_IntClear(int_cfg->pin, SET);
/* timeout check */
timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
do {
timeOut--;
} while ((SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) && timeOut);
if (!timeOut) {
//MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
}
GLB_GPIO_IntClear(int_cfg->pin, RESET);
}
}
}

172
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2c.c
View File

@@ -1,172 +0,0 @@
/**
* @file hal_i2c.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_i2c.h"
#include "bl702_i2c.h"
#include "bl702_glb.h"
static i2c_device_t i2cx_device[I2C_MAX_INDEX] = {
#ifdef BSP_USING_I2C0
I2C0_CONFIG,
#endif
#ifdef BSP_USING_I2C1
I2C1_CONFIG,
#endif
};
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int i2c_open(struct device *dev, uint16_t oflag)
{
i2c_device_t *i2c_device = (i2c_device_t *)dev;
if (i2c_device->mode == I2C_HW_MODE) {
I2C_SetPrd(i2c_device->id, i2c_device->phase);
}
return 0;
}
// int i2c_close(struct device *dev)
// {
// return 0;
// }
// int i2c_control(struct device *dev, int cmd, void *args)
// {
// //i2c_device_t *i2c_device = (i2c_device_t *)dev;
// switch (cmd)
// {
// case DEVICE_CTRL_SET_INT /* constant-expression */:
// break;
// case DEVICE_CTRL_CLR_INT /* constant-expression */:
// /* code */
// /* Enable UART interrupt*/
// break;
// case DEVICE_CTRL_GET_INT /* constant-expression */:
// /* code */
// break;
// case DEVICE_CTRL_CONFIG /* constant-expression */:
// /* code */
// break;
// case 4 /* constant-expression */:
// /* code */
// break;
// case 5 /* constant-expression */:
// /* code */
// break;
// default:
// break;
// }
// return 0;
// }
// int i2c_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
// {
// return 0;
// }
// int i2c_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
// {
// return 0;
// }
/**
* @brief
*
* @param index
* @param name
* @param flag
* @return int
*/
int i2c_register(enum i2c_index_type index, const char *name)
{
struct device *dev;
if (I2C_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(i2cx_device[index].parent);
dev->open = i2c_open;
dev->close = NULL;
dev->control = NULL;
dev->write = NULL;
dev->read = NULL;
dev->type = DEVICE_CLASS_I2C;
dev->handle = NULL;
return device_register(dev, name);
}
/**
* @brief
*
* @param dev
* @param msgs
* @param num
* @return uint32_t
*/
int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num)
{
i2c_msg_t *msg;
I2C_Transfer_Cfg i2cCfg = { 0 };
i2c_device_t *i2c_device = (i2c_device_t *)dev;
if (i2c_device->mode == I2C_HW_MODE) {
for (uint32_t i = 0; i < num; i++) {
msg = &msgs[i];
i2cCfg.slaveAddr = msg->slaveaddr;
i2cCfg.stopEveryByte = DISABLE;
i2cCfg.subAddr = msg->subaddr;
i2cCfg.dataSize = msg->len;
i2cCfg.data = msg->buf;
if (msg->flags & SUB_ADDR_0BYTE) {
i2cCfg.subAddrSize = 0;
} else if (msg->flags & SUB_ADDR_1BYTE) {
i2cCfg.subAddrSize = 1;
} else if (msg->flags & SUB_ADDR_2BYTE) {
i2cCfg.subAddrSize = 2;
}
if ((msg->flags & I2C_RW_MASK) == I2C_WR) {
return I2C_MasterSendBlocking(i2c_device->id, &i2cCfg);
} else if ((msg->flags & I2C_RW_MASK) == I2C_RD) {
return I2C_MasterReceiveBlocking(i2c_device->id, &i2cCfg);
}
}
} else {
}
return 0;
}

379
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2s.c
View File

@@ -1,379 +0,0 @@
/**
* @file hal_i2s.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_i2s.h"
#include "hal_clock.h"
#include "hal_dma.h"
#include "bl702_i2s.h"
#include "bl702_glb.h"
#include "i2s_config.h"
static i2s_device_t i2sx_device[I2S_MAX_INDEX] = {
#ifdef BSP_USING_I2S0
I2S0_CONFIG,
#endif
};
int i2s_open(struct device *dev, uint16_t oflag)
{
i2s_device_t *i2s_device = (i2s_device_t *)dev;
I2S_CFG_Type i2sCfg = { 0 };
I2S_FifoCfg_Type fifoCfg = { 0 };
i2sCfg.audioFreqHz = system_clock_get(SYSTEM_CLOCK_AUPLL);
i2sCfg.sampleFreqHz = i2s_device->sampl_freq_hz;
/*!< default I2S msb first */
i2sCfg.endianType = I2S_DATA_ENDIAN;
/* Config the I2S type */
switch (i2s_device->interface_mode) {
case I2S_MODE_STD:
i2sCfg.modeType = I2S_MODE_I2S_LEFT;
i2sCfg.fsMode = I2S_FS_MODE_EVEN;
i2sCfg.dataOffset = 1;
break;
case I2S_MODE_LEFT:
i2sCfg.modeType = I2S_MODE_I2S_LEFT;
i2sCfg.fsMode = I2S_FS_MODE_EVEN;
i2sCfg.dataOffset = 0;
break;
case I2S_MODE_RIGHT:
i2sCfg.modeType = I2S_MODE_I2S_RIGHT;
i2sCfg.fsMode = I2S_FS_MODE_EVEN;
i2sCfg.dataOffset = 0;
break;
case I2S_MODE_DSP_A:
i2sCfg.modeType = I2S_MODE_I2S_DSP;
i2sCfg.fsMode = I2S_FS_MODE_1T;
i2sCfg.dataOffset = 1;
break;
case I2S_MODE_DSP_B:
i2sCfg.modeType = I2S_MODE_I2S_DSP;
i2sCfg.fsMode = I2S_FS_MODE_1T;
i2sCfg.dataOffset = 0;
break;
default:
return ERROR;
break;
}
/* Config the frame/data Size */
switch (i2s_device->frame_size) {
case I2S_FRAME_LEN_8:
i2sCfg.frameSize = I2S_SIZE_FRAME_8;
break;
case I2S_FRAME_LEN_16:
i2sCfg.frameSize = I2S_SIZE_FRAME_16;
break;
case I2S_FRAME_LEN_24:
i2sCfg.frameSize = I2S_SIZE_FRAME_24;
break;
case I2S_FRAME_LEN_32:
i2sCfg.frameSize = I2S_SIZE_FRAME_32;
break;
default:
return ERROR;
break;
}
switch (i2s_device->data_size) {
case I2S_DATA_LEN_8:
i2sCfg.dataSize = I2S_SIZE_DATA_8;
break;
case I2S_DATA_LEN_16:
i2sCfg.dataSize = I2S_SIZE_DATA_16;
break;
case I2S_DATA_LEN_24:
i2sCfg.dataSize = I2S_SIZE_DATA_24;
break;
case I2S_DATA_LEN_32:
i2sCfg.dataSize = I2S_SIZE_DATA_32;
break;
default:
return ERROR;
break;
}
fifoCfg.lRMerge = DISABLE;
fifoCfg.frameDataExchange = DISABLE;
/* Config the Channel number */
switch (i2s_device->channel_num) {
case I2S_FS_CHANNELS_NUM_MONO:
i2sCfg.monoMode = ENABLE;
i2sCfg.fsChannel = I2S_FS_CHANNELS_2;
i2sCfg.monoModeChannel = I2S_MONO_CHANNEL;
break;
case I2S_FS_CHANNELS_NUM_2:
i2sCfg.monoMode = DISABLE;
i2sCfg.fsChannel = I2S_FS_CHANNELS_2;
if (i2s_device->data_size == I2S_DATA_LEN_8 || i2s_device->data_size == I2S_DATA_LEN_16) {
fifoCfg.lRMerge = ENABLE;
fifoCfg.frameDataExchange = I2S_LR_EXCHANGE;
}
break;
case I2S_FS_CHANNELS_NUM_3:
if ((i2s_device->interface_mode != I2S_MODE_DSP_A) && (i2s_device->interface_mode != I2S_MODE_DSP_B)) {
return ERROR;
}
i2sCfg.monoMode = DISABLE;
i2sCfg.fsChannel = I2S_FS_CHANNELS_3;
break;
case I2S_FS_CHANNELS_NUM_4:
if ((i2s_device->interface_mode != I2S_MODE_DSP_A) && (i2s_device->interface_mode != I2S_MODE_DSP_B)) {
return ERROR;
}
i2sCfg.monoMode = DISABLE;
i2sCfg.fsChannel = I2S_FS_CHANNELS_4;
default:
return ERROR;
break;
}
/* Config the bclk/fs invert */
i2sCfg.bclkInvert = I2S_BCLK_INVERT;
i2sCfg.fsInvert = I2S_FS_INVERT;
if (oflag & DEVICE_OFLAG_INT_TX) {
}
if (oflag & DEVICE_OFLAG_INT_RX) {
}
fifoCfg.txfifoDmaEnable = (oflag & DEVICE_OFLAG_DMA_TX) ? ENABLE : DISABLE;
fifoCfg.rxfifoDmaEnable = (oflag & DEVICE_OFLAG_DMA_RX) ? ENABLE : DISABLE;
fifoCfg.txFifoLevel = i2s_device->fifo_threshold;
fifoCfg.rxFifoLevel = i2s_device->fifo_threshold;
/* I2S Init */
I2S_Disable();
I2S_Init(&i2sCfg);
I2S_FifoConfig(&fifoCfg);
if (i2s_device->iis_mode == I2S_MODE_MASTER)
I2S_Enable(I2S_ROLE_MASTER);
else if (i2s_device->iis_mode == I2S_MODE_SLAVE)
I2S_Enable(I2S_ROLE_SLAVE);
return 0;
}
int i2s_close(struct device *dev)
{
//i2s_device_t* uart_device = (i2s_device_t*)dev;
I2S_Disable();
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_I2S);
return 0;
}
int i2s_control(struct device *dev, int cmd, void *args)
{
i2s_device_t *i2s_device = (i2s_device_t *)dev;
I2S_CFG_Type i2sCfg;
switch (cmd) {
case DEVICE_CTRL_SET_INT:
for (uint16_t i = 0, j = 1; i < 8; i++, j <<= 1) {
if ((uint32_t)args & j) {
/* code */
}
}
break;
case DEVICE_CTRL_CLR_INT:
for (uint16_t i = 0, j = 1; i < 8; i++, j <<= 1) {
if ((uint32_t)args & j) {
/* code */
}
}
break;
case DEVICE_CTRL_GET_INT:
/* code */
break;
case DEVICE_CTRL_RESUME:
/* code */
break;
case DEVICE_CTRL_SUSPEND:
/* code */
break;
case DEVICE_CTRL_CONFIG:
/* code */
break;
case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
i2s_device->tx_dma = (struct device *)args;
break;
case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
i2s_device->rx_dma = (struct device *)args;
break;
case DEVICE_CTRL_I2S_GET_TX_FIFO:
return I2S_GetTxFIFO_AvlCnt();
case DEVICE_CTRL_I2S_GET_RX_FIFO:
return I2S_GetRxFIFO_AvlCnt();
case DEVICE_CTRL_I2S_SET_SAMPL_FREQ:
switch (i2s_device->frame_size) {
case I2S_FRAME_LEN_8:
i2sCfg.frameSize = I2S_SIZE_FRAME_8;
break;
case I2S_FRAME_LEN_16:
i2sCfg.frameSize = I2S_SIZE_FRAME_16;
break;
case I2S_FRAME_LEN_24:
i2sCfg.frameSize = I2S_SIZE_FRAME_24;
break;
case I2S_FRAME_LEN_32:
i2sCfg.frameSize = I2S_SIZE_FRAME_32;
break;
default:
return ERROR;
break;
}
i2sCfg.audioFreqHz = system_clock_get(SYSTEM_CLOCK_AUPLL);
i2sCfg.sampleFreqHz = (uint32_t)args;
I2S_SetBclkPeriod(&i2sCfg);
break;
default:
return ERROR;
break;
}
return SUCCESS;
}
int i2s_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
i2s_device_t *i2s_device = (i2s_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_TX) {
struct device *dma_ch = (struct device *)i2s_device->tx_dma;
if (!dma_ch) {
return -1;
}
if (i2s_device->id == 0) {
dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_I2S_TDR, size);
dma_channel_start(dma_ch);
} else if (i2s_device->id == 1) {
dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_I2S_TDR, size);
dma_channel_start(dma_ch);
}
return 0;
} else {
return 0;
}
}
int i2s_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
i2s_device_t *i2s_device = (i2s_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_RX) {
struct device *dma_ch = (struct device *)i2s_device->rx_dma;
if (!dma_ch) {
return -1;
}
if (i2s_device->id == 0) {
dma_reload(dma_ch, (uint32_t)DMA_ADDR_I2S_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
} else if (i2s_device->id == 1) {
dma_reload(dma_ch, (uint32_t)DMA_ADDR_I2S_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
}
return 0;
} else {
return 0;
}
}
int i2s_register(enum i2s_index_type index, const char *name)
{
struct device *dev;
if (I2S_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(i2sx_device[index].parent);
dev->open = i2s_open;
dev->close = i2s_close;
dev->control = i2s_control;
dev->write = i2s_write;
dev->read = i2s_read;
dev->type = DEVICE_CLASS_I2S;
dev->handle = NULL;
return device_register(dev, name);
}
void i2s_isr(i2s_device_t *handle)
{
return;
}
void I2S_IRQ(void)
{
i2s_isr(&i2sx_device[0]);
}

159
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_keyscan.c
View File

@@ -1,159 +0,0 @@
/**
* @file hal_keyscan.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_keyscan.h"
#include "kys_reg.h"
#include "bl702_glb.h"
#ifdef BSP_USING_KEYSCAN
static void KeyScan_IRQ(void);
#endif
static keyscan_device_t keyscan_device[KEYSCAN_MAX_INDEX] = {
#ifdef BSP_USING_KEYSCAN
KEYSCAN_CONFIG
#endif
};
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int keyscan_open(struct device *dev, uint16_t oflag)
{
uint32_t tmpVal;
keyscan_device_t *keyscan_device = (keyscan_device_t *)dev;
tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
/* Set col and row */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_COL_NUM, keyscan_device->col_num - 1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_ROW_NUM, keyscan_device->row_num - 1);
/* Set idle duration between column scans */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_RC_EXT, 0);
/* ghost key event detection not support*/
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_GHOST_EN, 0);
if (keyscan_device->deglitch_count) {
/* Enable or disable deglitch function */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_EN, 1);
/* Set deglitch count */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_CNT, keyscan_device->deglitch_count);
} else {
/* Enable or disable deglitch function */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_EN, 0);
/* Set deglitch count */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_CNT, 0);
}
/* Write back */
BL_WR_REG(KYS_BASE, KYS_KS_CTRL, tmpVal);
return 0;
}
int keyscan_control(struct device *dev, int cmd, void *args)
{
switch (cmd) {
case DEVICE_CTRL_SET_INT /* constant-expression */:
#ifdef BSP_USING_KEYSCAN
Interrupt_Handler_Register(KYS_IRQn, KeyScan_IRQ);
#endif
BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, 1);
CPU_Interrupt_Enable(KYS_IRQn);
break;
case DEVICE_CTRL_CLR_INT /* constant-expression */:
Interrupt_Handler_Register(KYS_IRQn, NULL);
BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, 0);
CPU_Interrupt_Disable(KYS_IRQn);
break;
case DEVICE_CTRL_GET_INT:
return (BL_RD_REG(KYS_BASE, KYS_KS_INT_STS) & 0xf);
case DEVICE_CTRL_RESUME: {
uint32_t tmpVal;
tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_SET_REG_BIT(tmpVal, KYS_KS_EN));
} break;
case DEVICE_CTRL_SUSPEND: {
uint32_t tmpVal;
tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_CLR_REG_BIT(tmpVal, KYS_KS_EN));
} break;
case DEVICE_CTRL_KEYSCAN_GET_KEYCODE: {
uint32_t *key_code = (uint32_t *)args;
*key_code = BL_RD_REG(KYS_BASE, KYS_KEYCODE_VALUE);
BL_WR_REG(KYS_BASE, KYS_KEYCODE_CLR, 0xf);
} break;
default:
break;
}
return 0;
}
/**
* @brief
*
* @param index
* @param name
* @param flag
* @return int
*/
int keyscan_register(enum keyscan_index_type index, const char *name)
{
struct device *dev;
if (KEYSCAN_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(keyscan_device[index].parent);
dev->open = keyscan_open;
dev->close = NULL;
dev->control = keyscan_control;
dev->write = NULL;
dev->read = NULL;
dev->type = DEVICE_CLASS_KEYSCAN;
dev->handle = NULL;
return device_register(dev, name);
}
#if defined(BSP_USING_KEYSCAN)
static void KeyScan_IRQ(void)
{
if (keyscan_device[KEYSCAN_INDEX].parent.callback) {
keyscan_device[KEYSCAN_INDEX].parent.callback(&keyscan_device[KEYSCAN_INDEX].parent, (void *)(BL_RD_REG(KYS_BASE, KYS_KEYCODE_VALUE)), 0, KEYSCAN_EVENT_TRIG);
}
BL_WR_REG(KYS_BASE, KYS_KEYCODE_CLR, 0xf);
}
#endif

131
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c
View File

@@ -1,131 +0,0 @@
/**
* @file hal_mjpeg.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "bl702_mjpeg.h"
#include "bl702_glb.h"
#include "hal_mjpeg.h"
void mjpeg_init(mjpeg_device_t *mjpeg_cfg)
{
MJPEG_Packet_Type packetCfg = { 0 };
MJPEG_CFG_Type mjpegCfg = {
.burst = MJPEG_BURST_INCR16,
.quality = mjpeg_cfg->quality,
.yuv = mjpeg_cfg->yuv_format,
.waitCount = 0x400,
.bufferMjpeg = mjpeg_cfg->write_buffer_addr,
.sizeMjpeg = mjpeg_cfg->write_buffer_size,
.bufferCamYY = mjpeg_cfg->read_buffer_addr,
.sizeCamYY = mjpeg_cfg->read_buffer_size,
.bufferCamUV = 0,
.sizeCamUV = 0,
.resolutionX = mjpeg_cfg->resolution_x,
.resolutionY = mjpeg_cfg->resolution_y,
.bitOrderEnable = ENABLE,
.evenOrderEnable = ENABLE,
.swapModeEnable = DISABLE,
.overStopEnable = ENABLE,
.reflectDmy = DISABLE,
.verticalDmy = DISABLE,
.horizationalDmy = DISABLE,
};
GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_MJPEG);
uint32_t tmpVal;
/* Disable mjpeg module */
tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
MJPEG_Init(&mjpegCfg);
if (mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_DEFAULT) {
packetCfg.packetEnable = ENABLE;
packetCfg.packetHead = mjpeg_cfg->packet_head_length;
packetCfg.packetBody = mjpeg_cfg->packet_body_length;
packetCfg.packetTail = mjpeg_cfg->packet_tail_length;
}
if (mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_FRAME_HEAD) {
packetCfg.frameHead = mjpeg_cfg->frame_head_length;
}
if (mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_FRAME_TAIL) {
packetCfg.frameTail = ENABLE;
}
if (mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_END_TAIL) {
packetCfg.endToTail = ENABLE;
}
MJPEG_Packet_Config(&packetCfg);
if (mjpeg_cfg->yuv_format == MJPEG_YUV_FORMAT_YUV422_INTERLEAVE) {
MJPEG_Set_YUYV_Order_Interleave(1, 0, 3, 2);
}
}
void mjpeg_start(void)
{
uint32_t tmpVal;
/* Enable mjpeg module */
tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
}
void mjpeg_stop(void)
{
uint32_t tmpVal;
/* Disable mjpeg module */
tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
}
uint8_t mjpeg_get_one_frame(uint8_t **pic, uint32_t *len, uint8_t *q)
{
MJPEG_Frame_Info info;
arch_memset(&info, 0, sizeof(info));
MJPEG_Get_Frame_Info(&info);
if (info.validFrames == 0) {
return ERROR;
}
*pic = (uint8_t *)(info.curFrameAddr);
*len = info.curFrameBytes;
*q = info.curFrameQ;
return SUCCESS;
}
void mjpeg_drop_one_frame(void)
{
MJPEG_Pop_Frame();
}

143
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mtimer.c
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@@ -1,143 +0,0 @@
/**
* @file hal_mtimer.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_mtimer.h"
#include "bl702_glb.h"
#include "risc-v/Core/Include/clic.h"
static void (*systick_callback)(void);
static uint64_t next_compare_tick = 0;
static uint64_t current_set_ticks = 0;
static void Systick_Handler(void)
{
*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick;
systick_callback();
next_compare_tick += current_set_ticks;
}
/**
* @brief
*
* @param time
* @param interruptFun
*/
void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void))
{
CPU_Interrupt_Disable(MTIME_IRQn);
uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
volatile uint32_t *const pulTimeHigh = (volatile uint32_t *const)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
volatile uint32_t *const pulTimeLow = (volatile uint32_t *const)(CLIC_CTRL_ADDR + CLIC_MTIME);
volatile uint32_t ulHartId = 0;
current_set_ticks = ticks;
systick_callback = interruptfun;
__asm volatile("csrr %0, mhartid"
: "=r"(ulHartId));
do {
ulCurrentTimeHigh = *pulTimeHigh;
ulCurrentTimeLow = *pulTimeLow;
} while (ulCurrentTimeHigh != *pulTimeHigh);
next_compare_tick = (uint64_t)ulCurrentTimeHigh;
next_compare_tick <<= 32ULL;
next_compare_tick |= (uint64_t)ulCurrentTimeLow;
next_compare_tick += (uint64_t)current_set_ticks;
*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick;
/* Prepare the time to use after the next tick interrupt. */
next_compare_tick += (uint64_t)current_set_ticks;
Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler);
CPU_Interrupt_Enable(MTIME_IRQn);
}
/**
* @brief
*
* @return uint64_t
*/
uint64_t mtimer_get_time_ms()
{
return mtimer_get_time_us() / 1000;
}
/**
* @brief
*
* @return uint64_t
*/
uint64_t mtimer_get_time_us()
{
uint32_t tmpValLow, tmpValHigh, tmpValHigh1;
do {
tmpValLow = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME);
tmpValHigh = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
tmpValHigh1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
} while (tmpValHigh != tmpValHigh1);
return (((uint64_t)tmpValHigh << 32) + tmpValLow);
}
/**
* @brief
*
* @param time
*/
void mtimer_delay_ms(uint32_t time)
{
uint64_t cnt = 0;
uint32_t clock = SystemCoreClockGet();
uint64_t startTime = mtimer_get_time_ms();
while (mtimer_get_time_ms() - startTime < time) {
cnt++;
/* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/
if (cnt > (time * (clock >> (10 + 5))) * 2) {
break;
}
}
}
/**
* @brief
*
* @param time
*/
void mtimer_delay_us(uint32_t time)
{
uint64_t cnt = 0;
uint32_t clock = SystemCoreClockGet();
uint64_t startTime = mtimer_get_time_us();
while (mtimer_get_time_us() - startTime < time) {
cnt++;
/* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/
if (cnt > (time * (clock >> (10 + 5))) * 2) {
break;
}
}
}

1366
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm.c
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321
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm_util.c
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@@ -1,321 +0,0 @@
/**
* @file hal_pm_util.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "bl702_romdriver.h"
#include "bl702_sf_ctrl.h"
#include "bl702_glb.h"
#include "hal_clock.h"
#include "hal_pm.h"
#include "hal_pm_util.h"
/* Cache Way Disable, will get from l1c register */
extern uint8_t cacheWayDisable;
/* PSRAM IO Configuration, will get from glb register */
extern uint32_t psramIoCfg;
/* Flash offset value, will get from sf_ctrl register */
extern uint32_t flash_offset;
extern void pm_pds31_fast_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time);
extern SPI_Flash_Cfg_Type *flash_cfg;
void ATTR_PDS_RAM_SECTION pm_pds_fastboot_entry(void);
void (*hardware_recovery)(void) = NULL;
/**
* @brief hal_pds_enter_with_time_compensation
*
* @param pdsLevel pds level support 0~3,31
* @param pdsSleepCycles user set sleep time, clock of pds_time is 32768hz
* @return uint32_t actual sleep time(ms)
*
* @note If necessary，please application layer call vTaskStepTick，
*/
uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles)
{
uint32_t rtcLowBeforeSleep = 0, rtcHighBeforeSleep = 0;
uint32_t rtcLowAfterSleep = 0, rtcHighAfterSleep = 0;
uint32_t actualSleepDuration_32768cycles = 0;
uint32_t actualSleepDuration_ms = 0;
pm_set_wakeup_callback(pm_pds_fastboot_entry);
HBN_Get_RTC_Timer_Val(&rtcLowBeforeSleep, &rtcHighBeforeSleep);
pm_pds31_fast_mode_enter(pdsLevel, pdsSleepCycles);
HBN_Get_RTC_Timer_Val(&rtcLowAfterSleep, &rtcHighAfterSleep);
CHECK_PARAM((rtcHighAfterSleep - rtcHighBeforeSleep) <= 1); // make sure sleep less than 1 hour (2^32 us > 1 hour)
actualSleepDuration_32768cycles = (rtcLowAfterSleep - rtcLowBeforeSleep);
actualSleepDuration_ms = (actualSleepDuration_32768cycles >> 5) - (actualSleepDuration_32768cycles >> 11) - (actualSleepDuration_32768cycles >> 12);
// vTaskStepTick(actualSleepDuration_ms);
return actualSleepDuration_ms;
}
/**
* @brief get delay value of spi flash init
*
* @param delay_index
* @return uint8_t
*/
static uint8_t ATTR_PDS_RAM_SECTION bflb_spi_flash_get_delay_val(uint8_t delay_index)
{
switch (delay_index) {
case 0:
return 0x00;
case 1:
return 0x80;
case 2:
return 0xc0;
case 3:
return 0xe0;
case 4:
return 0xf0;
case 5:
return 0xf8;
case 6:
return 0xfc;
case 7:
return 0xfe;
default:
return 0x00;
}
}
/**
* @brief config spi flash
*
* @param pFlashCfg flash parameter
*/
static void ATTR_PDS_RAM_SECTION bflb_spi_flash_set_sf_ctrl(SPI_Flash_Cfg_Type *pFlashCfg)
{
SF_Ctrl_Cfg_Type sfCtrlCfg;
uint8_t delay_index;
sfCtrlCfg.owner = SF_CTRL_OWNER_SAHB;
/* bit0-3 for clk delay */
sfCtrlCfg.clkDelay = (pFlashCfg->clkDelay & 0x0f);
/* bit0 for clk invert */
sfCtrlCfg.clkInvert = pFlashCfg->clkInvert & 0x01;
/* bit1 for rx clk invert */
sfCtrlCfg.rxClkInvert = (pFlashCfg->clkInvert >> 1) & 0x01;
/* bit4-6 for do delay */
delay_index = (pFlashCfg->clkDelay >> 4) & 0x07;
sfCtrlCfg.doDelay = bflb_spi_flash_get_delay_val(delay_index);
/* bit2-4 for di delay */
delay_index = (pFlashCfg->clkInvert >> 2) & 0x07;
sfCtrlCfg.diDelay = bflb_spi_flash_get_delay_val(delay_index);
/* bit5-7 for oe delay */
delay_index = (pFlashCfg->clkInvert >> 5) & 0x07;
sfCtrlCfg.oeDelay = bflb_spi_flash_get_delay_val(delay_index);
RomDriver_SFlash_Init(&sfCtrlCfg);
}
/**
* @brief
*
* @param media_boot
* @return int32_t
*/
int32_t ATTR_PDS_RAM_SECTION pm_spi_flash_init(uint8_t media_boot)
{
uint32_t stat;
uint32_t jdecId = 0;
uint32_t flash_read_try = 0;
/*use fclk as flash clok */
RomDriver_GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XCLK, 0); // 32M
RomDriver_SF_Ctrl_Set_Clock_Delay(0);
bflb_spi_flash_set_sf_ctrl(flash_cfg);
/* Wake flash up from power down */
RomDriver_SFlash_Releae_Powerdown(flash_cfg);
//ARCH_Delay_US(15*((pFlashCfg->pdDelay&0x7)+1));
RomDriver_BL702_Delay_US(120);
do {
if (flash_read_try > 4) {
// bflb_bootrom_printd("Flash read id TO\r\n");
break;
} else if (flash_read_try > 0) {
RomDriver_BL702_Delay_US(500);
}
// bflb_bootrom_printd("reset flash\r\n");
/* Exit form continous read for accepting command */
RomDriver_SFlash_Reset_Continue_Read(flash_cfg);
/* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */
RomDriver_SFlash_Software_Reset(flash_cfg);
/* Disable burst may be removed(except for 80BV) and only work with winbond,but just for make sure */
RomDriver_SFlash_Write_Enable(flash_cfg);
/* For disable command that is setting register instaed of send command, we need write enable */
RomDriver_SFlash_DisableBurstWrap(flash_cfg);
stat = RomDriver_SFlash_SetSPIMode(SF_CTRL_SPI_MODE);
if (SUCCESS != stat) {
// bflb_bootrom_printe("enter spi mode fail %d\r\n", stat);
// return BFLB_BOOTROM_FLASH_INIT_ERROR;
return -1;
}
RomDriver_SFlash_GetJedecId(flash_cfg, (uint8_t *)&jdecId);
/* Dummy disable burstwrap for make sure */
RomDriver_SFlash_Write_Enable(flash_cfg);
/* For disable command that is setting register instead of send command, we need write enable */
RomDriver_SFlash_DisableBurstWrap(flash_cfg);
jdecId = jdecId & 0xffffff;
// bflb_bootrom_printd("ID =%08x\r\n", jdecId);
flash_read_try++;
} while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00);
/*clear offset setting*/
// reset image offset
BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, flash_offset);
/* set read mode */
if ((flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
stat = RomDriver_SFlash_Qspi_Enable(flash_cfg);
}
if (media_boot) {
RomDriver_L1C_Set_Wrap(DISABLE);
RomDriver_SFlash_Cache_Read_Enable(flash_cfg, flash_cfg->ioMode & 0xf, 0, 0x00);
}
return jdecId;
}
// can be placed in flash, here placed in pds section to reduce fast boot time
static void ATTR_PDS_RAM_SECTION pm_pds_restore_cpu_reg(void)
{
__asm__ __volatile__(
"la a2, __ld_pds_bak_addr\n\t"
"lw ra, 0(a2)\n\t"
"lw sp, 1*4(a2)\n\t"
"lw tp, 2*4(a2)\n\t"
"lw t0, 3*4(a2)\n\t"
"lw t1, 4*4(a2)\n\t"
"lw t2, 5*4(a2)\n\t"
"lw fp, 6*4(a2)\n\t"
"lw s1, 7*4(a2)\n\t"
"lw a0, 8*4(a2)\n\t"
"lw a1, 9*4(a2)\n\t"
"lw a3, 10*4(a2)\n\t"
"lw a4, 11*4(a2)\n\t"
"lw a5, 12*4(a2)\n\t"
"lw a6, 13*4(a2)\n\t"
"lw a7, 14*4(a2)\n\t"
"lw s2, 15*4(a2)\n\t"
"lw s3, 16*4(a2)\n\t"
"lw s4, 17*4(a2)\n\t"
"lw s5, 18*4(a2)\n\t"
"lw s6, 19*4(a2)\n\t"
"lw s7, 20*4(a2)\n\t"
"lw s8, 21*4(a2)\n\t"
"lw s9, 22*4(a2)\n\t"
"lw s10, 23*4(a2)\n\t"
"lw s11, 24*4(a2)\n\t"
"lw t3, 25*4(a2)\n\t"
"lw t4, 26*4(a2)\n\t"
"lw t5, 27*4(a2)\n\t"
"lw t6, 28*4(a2)\n\t"
"csrw mtvec, a0\n\t"
"csrw mstatus,a1\n\t"
"ret\n\t");
}
void ATTR_PDS_RAM_SECTION sf_io_select(void)
{
uint32_t tmpVal = 0;
uint8_t flashCfg = 0;
uint8_t psramCfg = 0;
uint8_t isInternalFlash = 0;
uint8_t isInternalPsram = 0;
/* SF io select from efuse value */
tmpVal = BL_RD_WORD(0x40007074);
flashCfg = ((tmpVal >> 26) & 7);
psramCfg = ((tmpVal >> 24) & 3);
if (flashCfg == 1 || flashCfg == 2) {
isInternalFlash = 1;
} else {
isInternalFlash = 0;
}
if (psramCfg == 1) {
isInternalPsram = 1;
} else {
isInternalPsram = 0;
}
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
if (isInternalFlash == 1 && isInternalPsram == 0) {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
} else {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
}
BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
}
// must be placed in pds section
void ATTR_PDS_RAM_SECTION pm_pds_fastboot_entry(void)
{
// reload gp register
__asm__ __volatile__(
".option push\n\t"
".option norelax\n\t"
"la gp, __global_pointer$\n\t"
".option pop\n\t");
#if XTAL_TYPE != INTERNAL_RC_32M
/* power on Xtal_32M*/
(*(volatile uint32_t *)(AON_BASE + AON_RF_TOP_AON_OFFSET)) |= (3 << 4);
#endif
// recovery flash pad and param
RomDriver_SF_Cfg_Init_Flash_Gpio(0, 1);
pm_spi_flash_init(1);
sf_io_select();
/* Recovery hardware , include tcm , gpio and clock */
if (hardware_recovery) {
hardware_recovery();
}
// Restore cpu registers
pm_pds_restore_cpu_reg();
}
void pm_set_hardware_recovery_callback(void (*hardware_recovery_cb)(void))
{
hardware_recovery = hardware_recovery_cb;
}

203
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pwm.c
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@@ -1,203 +0,0 @@
/**
* @file hal_pwm.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_pwm.h"
#include "hal_clock.h"
#include "bl702_pwm.h"
#include "bl702_glb.h"
static pwm_device_t pwmx_device[PWM_MAX_INDEX] = {
#ifdef BSP_USING_PWM_CH0
PWM_CH0_CONFIG,
#endif
#ifdef BSP_USING_PWM_CH1
PWM_CH1_CONFIG,
#endif
#ifdef BSP_USING_PWM_CH2
PWM_CH2_CONFIG,
#endif
#ifdef BSP_USING_PWM_CH3
PWM_CH3_CONFIG,
#endif
#ifdef BSP_USING_PWM_CH4
PWM_CH4_CONFIG,
#endif
};
static void PWM_IRQ(void);
int pwm_open(struct device *dev, uint16_t oflag)
{
pwm_device_t *pwm_device = (pwm_device_t *)dev;
uint32_t tmpVal;
uint32_t PWMx;
CPU_Interrupt_Disable(PWM_IRQn);
PWM_IntMask(pwm_device->ch, PWM_INT_ALL, MASK);
PWM_Channel_Disable(pwm_device->ch);
uint32_t pwm_clk = peripheral_clock_get(PERIPHERAL_CLOCK_PWM);
if (pwm_device->period > pwm_clk)
return -1;
PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20;
tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, pwm_device->polarity_invert_mode);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, PWM_STOP_GRACEFUL);
BL_WR_REG(PWMx, PWM_CONFIG, tmpVal);
BL_WR_REG(PWMx, PWM_THRE1, pwm_device->threshold_low);
BL_WR_REG(PWMx, PWM_THRE2, pwm_device->threshold_high);
BL_WR_REG(PWMx, PWM_PERIOD, pwm_device->period);
if (oflag & DEVICE_OFLAG_INT_TX) {
tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT);
BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, pwm_device->it_pulse_count));
Interrupt_Handler_Register(PWM_IRQn, PWM_IRQ);
PWM_IntMask(pwm_device->ch, PWM_INT_PULSE_CNT, UNMASK);
CPU_Interrupt_Enable(PWM_IRQn);
}
return 0;
}
int pwm_close(struct device *dev)
{
pwm_device_t *pwm_device = (pwm_device_t *)dev;
PWM_Channel_Disable(pwm_device->ch);
return 0;
}
int pwm_control(struct device *dev, int cmd, void *args)
{
pwm_device_t *pwm_device = (pwm_device_t *)dev;
pwm_dutycycle_config_t *config = (pwm_dutycycle_config_t *)args;
switch (cmd) {
case DEVICE_CTRL_CONFIG /* constant-expression */:
break;
case DEVICE_CTRL_RESUME /* constant-expression */:
PWM_Channel_Enable(pwm_device->ch);
break;
case DEVICE_CTRL_SUSPEND /* constant-expression */:
PWM_Channel_Disable(pwm_device->ch);
break;
case DEVICE_CTRL_PWM_FREQUENCE_CONFIG:
if ((uint32_t)args > peripheral_clock_get(PERIPHERAL_CLOCK_PWM))
return -1;
pwm_device->period = (uint32_t)args;
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_PERIOD, (uint32_t)args);
break;
case DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG:
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE1, config->threshold_low);
BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE2, config->threshold_high);
break;
case DEVICE_CTRL_PWM_IT_PULSE_COUNT_CONFIG: {
/* Config interrupt pulse count */
uint32_t pwm_ch_addr = PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20;
uint32_t tmpVal = BL_RD_REG(pwm_ch_addr, PWM_INTERRUPT);
BL_WR_REG(pwm_ch_addr, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, (uint32_t)args));
if ((uint32_t)args) {
PWM_IntMask(pwm_device->ch, PWM_INT_PULSE_CNT, UNMASK);
CPU_Interrupt_Enable(PWM_IRQn);
} else {
PWM_IntMask(pwm_device->ch, PWM_INT_PULSE_CNT, MASK);
CPU_Interrupt_Disable(PWM_IRQn);
}
break;
}
default:
break;
}
return 0;
}
int pwm_register(enum pwm_index_type index, const char *name)
{
struct device *dev;
if (PWM_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(pwmx_device[index].parent);
dev->open = pwm_open;
dev->close = pwm_close;
dev->control = pwm_control;
dev->write = NULL;
dev->read = NULL;
dev->type = DEVICE_CLASS_PWM;
dev->handle = NULL;
return device_register(dev, name);
}
static void pwm_isr(pwm_device_t *handle)
{
uint32_t i;
uint32_t tmpVal;
uint32_t timeoutCnt = 160 * 1000;
/* Get channel register */
uint32_t PWMx = PWM_BASE;
for (i = 0; i < PWM_MAX_INDEX; i++) {
tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG);
if ((BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << handle[i].ch)) != 0) {
/* Clear interrupt */
tmpVal |= (1 << (handle[i].ch + PWM_INT_CLEAR_POS));
BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal);
/* FIXME: we need set pwm_int_clear to 0 by software and
before this,we must make sure pwm_interrupt_sts is 0*/
do {
tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG);
timeoutCnt--;
if (timeoutCnt == 0) {
break;
}
} while (BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << handle[i].ch));
tmpVal &= (~(1 << (handle[i].ch + PWM_INT_CLEAR_POS)));
BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal);
if (handle[i].parent.callback) {
handle[i].parent.callback(&handle[i].parent, NULL, 0, PWM_EVENT_COMPLETE);
}
}
}
}
static void PWM_IRQ(void)
{
pwm_isr(&pwmx_device[0]);
}

290
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_qdec.c
View File

@@ -1,290 +0,0 @@
/**
* @file hal_qdec.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_qdec.h"
#include "qdec_reg.h"
#include "bl702_qdec.h"
#include "bl702_gpio.h"
#include "bl702_glb.h"
static qdec_device_t qdecx_device[QDEC_MAX_INDEX] = {
#ifdef BSP_USING_QDEC0
QDEC0_CONFIG,
#endif
#ifdef BSP_USING_QDEC1
QDEC1_CONFIG,
#endif
#ifdef BSP_USING_QDEC2
QDEC2_CONFIG,
#endif
};
#ifdef BSP_USING_QDEC0
static void QDEC0_IRQ(void);
#endif
#ifdef BSP_USING_QDEC1
static void QDEC1_IRQ(void);
#endif
#ifdef BSP_USING_QDEC2
static void QDEC2_IRQ(void);
#endif
int qdec_open(struct device *dev, uint16_t oflag)
{
qdec_device_t *qdec_device = (qdec_device_t *)dev;
QDEC_CFG_Type qdec_cfg = { 0 };
QDEC_DeInit(qdec_device->id);
qdec_cfg.sampleCfg.sampleMod = qdec_device->sample_mode;
qdec_cfg.sampleCfg.samplePeriod = qdec_device->sample_period;
qdec_cfg.reportCfg.reportMod = qdec_device->report_mode;
qdec_cfg.reportCfg.reportPeriod = qdec_device->report_period;
qdec_cfg.ledCfg.ledEn = qdec_device->led_en;
qdec_cfg.ledCfg.ledSwap = qdec_device->led_swap;
qdec_cfg.ledCfg.ledPeriod = qdec_device->led_period;
qdec_cfg.deglitchCfg.deglitchEn = qdec_device->deglitch_en;
qdec_cfg.deglitchCfg.deglitchStrength = qdec_device->deglitch_strength;
qdec_cfg.accMod = qdec_device->acc_mode;
QDEC_Init(qdec_device->id, &qdec_cfg);
if (oflag & DEVICE_OFLAG_INT_RX) {
#ifdef BSP_USING_QDEC0
if (qdec_device->id == QDEC0_ID) {
Interrupt_Handler_Register(QDEC0_IRQn, QDEC0_IRQ);
}
#endif
#ifdef BSP_USING_QDEC1
if (qdec_device->id == QDEC1_ID) {
Interrupt_Handler_Register(QDEC1_IRQn, QDEC1_IRQ);
QDEC_SetIntMask(qdec_device->id, QDEC_INT_REPORT, MASK);
QDEC_SetIntMask(qdec_device->id, QDEC_INT_SAMPLE, MASK);
QDEC_SetIntMask(qdec_device->id, QDEC_INT_ERROR, MASK);
QDEC_SetIntMask(qdec_device->id, QDEC_INT_OVERFLOW, MASK);
// CPU_Interrupt_Enable(QDEC1_IRQn);
}
#endif
#ifdef BSP_USING_QDEC2
if (qdec_device->id == QDEC2_ID) {
Interrupt_Handler_Register(QDEC2_IRQn, QDEC2_IRQ);
QDEC_SetIntMask(qdec_device->id, QDEC_INT_REPORT, MASK);
QDEC_SetIntMask(qdec_device->id, QDEC_INT_SAMPLE, MASK);
QDEC_SetIntMask(qdec_device->id, QDEC_INT_ERROR, MASK);
QDEC_SetIntMask(qdec_device->id, QDEC_INT_OVERFLOW, MASK);
// CPU_Interrupt_Enable(QDEC2_IRQn);
}
#endif
}
return 0;
}
int qdec_close(struct device *dev)
{
qdec_device_t *qdec_device = (qdec_device_t *)dev;
QDEC_Disable(qdec_device->id);
return 0;
}
int qdec_control(struct device *dev, int cmd, void *args)
{
qdec_device_t *qdec_device = (qdec_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT: {
uint32_t offset = __builtin_ctz((uint32_t)args);
while (offset < 5) {
if ((uint32_t)args & (1 << offset)) {
QDEC_SetIntMask(qdec_device->id, offset, UNMASK);
}
offset++;
}
if (qdec_device->id == QDEC0_ID) {
CPU_Interrupt_Enable(QDEC0_IRQn);
} else if (qdec_device->id == QDEC1_ID) {
CPU_Interrupt_Enable(QDEC1_IRQn);
} else if (qdec_device->id == QDEC2_ID) {
CPU_Interrupt_Enable(QDEC2_IRQn);
}
break;
}
case DEVICE_CTRL_CLR_INT: {
uint32_t offset = __builtin_ctz((uint32_t)args);
while (offset < 5) {
if ((uint32_t)args & (1 << offset)) {
QDEC_SetIntMask(qdec_device->id, offset, MASK);
}
offset++;
}
if (qdec_device->id == QDEC0_ID) {
CPU_Interrupt_Disable(QDEC0_IRQn);
} else if (qdec_device->id == QDEC1_ID) {
CPU_Interrupt_Disable(QDEC1_IRQn);
} else if (qdec_device->id == QDEC2_ID) {
CPU_Interrupt_Disable(QDEC2_IRQn);
}
break;
}
case DEVICE_CTRL_GET_INT /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_CONFIG /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_RESUME /* constant-expression */: {
/* Enable timer */
QDEC_Enable(qdec_device->id);
break;
}
case DEVICE_CTRL_SUSPEND /* constant-expression */: {
QDEC_Disable(qdec_device->id);
break;
}
case DEVICE_CTRL_GET_SAMPLE_VAL: {
return QDEC_Get_Sample_Val(qdec_device->id);
}
case DEVICE_CTRL_GET_SAMPLE_DIR: {
return QDEC_Get_Sample_Direction(qdec_device->id);
}
case DEVICE_CTRL_GET_ERROR_CNT: {
return QDEC_Get_Err_Cnt(qdec_device->id);
}
default:
break;
}
return 0;
}
int qdec_register(enum qdec_index_type index, const char *name)
{
struct device *dev;
if (QDEC_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(qdecx_device[index].parent);
dev->open = qdec_open;
dev->close = qdec_close;
dev->control = qdec_control;
dev->write = NULL;
dev->read = NULL; //qdec_read;
dev->type = DEVICE_CLASS_QDEC;
dev->handle = NULL;
return device_register(dev, name);
}
void qdec_isr(qdec_device_t *handle)
{
uint32_t tmp_sts = 0;
uint32_t tmp_val = 0;
uint32_t tmp_clr = 0;
uint32_t tmp_clr_val = 0;
if (handle->id == QDEC0_ID) {
tmp_sts = BL_RD_WORD(QDEC0_BASE + QDEC0_INT_STS_OFFSET);
tmp_clr = QDEC0_BASE + QDEC0_INT_CLR_OFFSET;
tmp_clr_val = BL_RD_WORD(tmp_clr);
tmp_val = BL_RD_REG(QDEC0_BASE, QDEC0_INT_EN);
} else if (handle->id == QDEC1_ID) {
tmp_sts = BL_RD_WORD(QDEC0_BASE + QDEC1_INT_STS_OFFSET);
tmp_clr = QDEC0_BASE + QDEC1_INT_CLR_OFFSET;
tmp_clr_val = BL_RD_WORD(tmp_clr);
tmp_val = BL_RD_REG(QDEC1_BASE, QDEC0_INT_EN);
} else if (handle->id == QDEC2_ID) {
tmp_sts = BL_RD_WORD(QDEC0_BASE + QDEC2_INT_STS_OFFSET);
tmp_clr = QDEC0_BASE + QDEC2_INT_CLR_OFFSET;
tmp_clr_val = BL_RD_WORD(tmp_clr);
tmp_val = BL_RD_REG(QDEC2_BASE, QDEC0_INT_EN);
}
if (!handle->parent.callback) {
return;
}
/* qdec report intterupt */
if (!(BL_GET_REG_BITS_VAL(tmp_val, QDEC_RPT_RDY_EN) ? UNMASK : MASK)) {
if (BL_IS_REG_BIT_SET(tmp_sts, QDEC_RPT_RDY_STS)) {
BL_WR_WORD(tmp_clr, BL_SET_REG_BIT(tmp_clr_val, QDEC_RPT_RDY_CLR));
handle->parent.callback(&handle->parent, NULL, 0, QDEC_REPORT_EVENT);
}
}
/* qdec sample intterupt */
if (!(BL_GET_REG_BITS_VAL(tmp_val, QDEC_SPL_RDY_EN) ? UNMASK : MASK)) {
if (BL_IS_REG_BIT_SET(tmp_sts, QDEC_SPL_RDY_STS)) {
BL_WR_WORD(tmp_clr, BL_SET_REG_BIT(tmp_clr_val, QDEC_SPL_RDY_CLR));
handle->parent.callback(&handle->parent, NULL, 0, QDEC_SAMPLE_EVENT);
}
}
/* qdec error intterupt */
if (!(BL_GET_REG_BITS_VAL(tmp_val, QDEC_DBL_RDY_EN) ? UNMASK : MASK)) {
if (BL_IS_REG_BIT_SET(tmp_sts, QDEC_DBL_RDY_STS)) {
BL_WR_WORD(tmp_clr, BL_SET_REG_BIT(tmp_clr_val, QDEC_DBL_RDY_CLR));
handle->parent.callback(&handle->parent, NULL, 0, QDEC_ERROR_EVENT);
}
}
/* qdec overflow intterupt */
if (!(BL_GET_REG_BITS_VAL(tmp_val, QDEC_OVERFLOW_EN) ? UNMASK : MASK)) {
if (BL_IS_REG_BIT_SET(tmp_sts, QDEC_OVERFLOW_STS)) {
BL_WR_WORD(tmp_clr, BL_SET_REG_BIT(tmp_clr_val, QDEC_OVERFLOW_CLR));
handle->parent.callback(&handle->parent, NULL, 0, QDEC_OVERFLOW_EVENT);
}
}
}
#ifdef BSP_USING_QDEC0
static void QDEC0_IRQ(void)
{
qdec_isr(&qdecx_device[QDEC0_INDEX]);
}
#endif
#ifdef BSP_USING_QDEC1
static void QDEC1_IRQ(void)
{
qdec_isr(&qdecx_device[QDEC1_INDEX]);
}
#endif
#ifdef BSP_USING_QDEC2
static void QDEC2_IRQ(void)
{
qdec_isr(&qdecx_device[QDEC2_INDEX]);
}
#endif

101
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_rtc.c
View File

@@ -1,101 +0,0 @@
/**
* @file hal_rtc.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_rtc.h"
#include "bl702_hbn.h"
static uint64_t current_timestamp = 0;
/**
* @brief rtc init withc sleep time
*
* @param sleep_time
*/
void rtc_init(uint64_t sleep_time)
{
uint32_t tmpVal;
uint32_t comp_l, comp_h;
/* Clear & Disable RTC counter */
tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
/* Clear RTC control bit0 */
BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff0);
/* Get current RTC timer */
/* Tigger RTC val read */
tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
/* Read RTC val */
comp_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
comp_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);
/* calculate RTC Comp time */
comp_l += (uint32_t)((sleep_time * 32768) & 0xFFFFFFFF);
comp_h += (uint32_t)(((sleep_time * 32768) >> 32) & 0xFFFFFFFF);
/* Set RTC Comp time */
BL_WR_REG(HBN_BASE, HBN_TIME_L, comp_l);
BL_WR_REG(HBN_BASE, HBN_TIME_H, comp_h & 0xff);
tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
/* Set interrupt delay option */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, HBN_RTC_INT_DELAY_0T);
/* Set RTC compare mode */
tmpVal |= (HBN_RTC_COMP_BIT0_39 << 1);
BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
/* Enable RTC Counter */
tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
/* Set RTC control bit0 */
BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01);
}
void rtc_set_timestamp(uint64_t time_stamp)
{
current_timestamp = time_stamp;
}
/**
* @bref Get rtc value
*
*/
uint64_t rtc_get_timestamp(void)
{
uint32_t tmpVal;
uint64_t time_l;
uint64_t time_h;
/* Tigger RTC val read */
tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
/* Read RTC val */
time_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
time_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);
return (((time_h << 32 | time_l) >> 15) + current_timestamp);
}

119
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c
View File

@@ -1,119 +0,0 @@
/**
* @file hal_sec_aes.c
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_sec_aes.h"
#include "bl702_sec_eng.h"
static SEC_Eng_AES_Ctx aesCtx;
int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type)
{
handle->aes_type = aes_tye;
handle->key_type = key_type;
return 0;
}
static SEC_ENG_AES_Key_Type sec_aes_get_key_type(sec_aes_handle_t *handle)
{
SEC_ENG_AES_Key_Type type = 0;
switch (handle->key_type) {
case SEC_AES_KEY_128:
type = SEC_ENG_AES_KEY_128BITS;
break;
case SEC_AES_KEY_256:
type = SEC_ENG_AES_KEY_256BITS;
break;
case SEC_AES_KEY_192:
type = SEC_ENG_AES_KEY_192BITS;
break;
default:
return SEC_ENG_AES_KEY_128BITS;
}
return type;
}
int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir)
{
SEC_ENG_AES_Key_Type type = sec_aes_get_key_type(handle);
switch (handle->aes_type) {
case SEC_AES_CBC:
Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0);
Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CBC, type,
SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION);
break;
case SEC_AES_CTR:
Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0);
Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CTR, type,
SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION);
break;
case SEC_AES_ECB:
break;
default:
return -1;
}
/* if key len is 0, means key is from efuse and *key value is key_sel value */
if (key_len == 0) {
Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_HW, key, nonce);
} else {
Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_SW, key, nonce);
}
return 0;
}
int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out)
{
if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) {
return -1;
}
return 0;
}
int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out)
{
if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) {
return -1;
}
return 0;
}
int sec_aes_deinit(sec_aes_handle_t *handle)
{
Sec_Eng_AES_Finish(SEC_ENG_AES_ID0);
memset(handle, 0, sizeof(sec_aes_handle_t));
return 0;
}

389
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c
View File

@@ -1,389 +0,0 @@
/**
* @file hal_sec_dsa.c
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_sec_dsa.h"
#include "bl702_sec_eng.h"
//#define DSA_DBG 1
//#define DSA_DBG_DETAIL 1
void bflb_platform_dump(uint8_t *data, uint32_t len);
#if (defined(DSA_DBG) || defined(DSA_DBG_DETAIL))
uint32_t pka_tmp[64] = { 0 };
#endif
/*
n=p*q;
F(n)=(p-1)*(q-1)
e*d%F(n)=1[e is public key and d is private key]
dP=d%(p-1)
dQ=d%(q-1)
m1=c^(dP)%p
m2=c^(dQ)%q
h=qInv*(m1-m2)%p
m=m2+h*q
m=c^d
*/
static SEC_ENG_PKA_REG_SIZE_Type sec_dsa_get_reg_size(uint32_t size)
{
switch (size) {
case 64:
return SEC_ENG_PKA_REG_SIZE_8;
case 128:
return SEC_ENG_PKA_REG_SIZE_16;
case 256:
return SEC_ENG_PKA_REG_SIZE_32;
case 512:
return SEC_ENG_PKA_REG_SIZE_64;
case 768:
return SEC_ENG_PKA_REG_SIZE_96;
case 1024:
return SEC_ENG_PKA_REG_SIZE_128;
case 1536:
return SEC_ENG_PKA_REG_SIZE_192;
case 2048:
return SEC_ENG_PKA_REG_SIZE_256;
case 3072:
return SEC_ENG_PKA_REG_SIZE_384;
case 4096:
return SEC_ENG_PKA_REG_SIZE_512;
default:
return SEC_ENG_PKA_REG_SIZE_32;
}
return SEC_ENG_PKA_REG_SIZE_32;
}
/* c code:
number = 1
base = a
while b:
if b & 1:
number = number * base % c
b >>= 1
base = base * base % c
return number
*/
int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r)
{
uint32_t i, j, k;
uint32_t tmp;
uint32_t isOne = 0;
uint8_t *p = (uint8_t *)b;
SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size);
SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2);
uint32_t dataSize = (size >> 3) >> 2;
#if 1
uint8_t oneBuf[128] ALIGN4 = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 };
#endif
/* 0:c
* 4:a
* 5:number
* 6&7:temp
*/
/* base = a */
Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0);
/* number = 1 */
Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)oneBuf, sizeof(oneBuf) / 4, 0);
//Sec_Eng_PKA_Write_Immediate(nregType,5,0x01,1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize);
MSG("number:\r\n");
bflb_platform_dump(pka_tmp, dataSize * 4);
#endif
Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0);
Sec_Eng_PKA_CREG(nregType, 6, dataSize, 1);
Sec_Eng_PKA_CREG(nregType, 7, dataSize, 1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
MSG("base:\r\n");
bflb_platform_dump(pka_tmp, dataSize * 4);
#endif
/* Remove zeros bytes*/
k = 0;
while (p[k] == 0 && k < (size >> 3)) {
k++;
}
i = (size >> 3) - 1;
for (; i >= k; i--) {
tmp = p[i];
j = 0;
for (j = 0; j < 8; j++) {
isOne = tmp & (1 << j);
if (isOne) {
/* number = number * base % c */
Sec_Eng_PKA_LMUL(lregType, 3, nregType, 5, nregType, 4, 0);
Sec_Eng_PKA_MREM(nregType, 5, lregType, 3, nregType, 0, 1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize);
MSG("number:\r\n");
bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
#endif
}
/* base = base * base % c */
Sec_Eng_PKA_LSQR(lregType, 3, nregType, 4, 0);
Sec_Eng_PKA_MREM(nregType, 4, lregType, 3, nregType, 0, 1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
MSG("base:\r\n");
bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
#endif
}
}
Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)r, dataSize);
#ifdef DSA_DBG
MSG("r:\r\n");
bflb_platform_dump(r, dataSize * 4);
#endif
return 0;
}
/*r=a^b%c*/
int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r)
{
SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size);
SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2);
uint32_t dataSize = (size >> 3) >> 2;
/* 0:c
* 1:NPrime_c
* 2:invR_c
* 4:a(mont domain)
* 5:b
* 6:a^b%c(mont domain)
* 7:a^b%c(gf domain)
* 10&11:2^size for GF2Mont*/
Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0);
Sec_Eng_PKA_Write_Data(nregType, 1, (uint32_t *)primeN_c, dataSize, 1);
Sec_Eng_PKA_Write_Data(nregType, 2, (uint32_t *)invR_c, dataSize, 1);
/* change a into mont domain*/
Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0);
Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
Sec_Eng_PKA_GF2Mont(nregType, 4, nregType, 4, size, lregType, 5, nregType, 0);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
MSG("GF2Mont Result of a:\r\n");
bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
#endif
Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)b, dataSize, 0);
/* a^b%c*/
Sec_Eng_PKA_MEXP(nregType, 6, nregType, 4, nregType, 5, nregType, 0, 1);
/* change result into gf domain*/
Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
/*index 2 is invertR*/
Sec_Eng_PKA_Mont2GF(nregType, 7, nregType, 6, nregType, 2, lregType, 5, nregType, 0);
Sec_Eng_PKA_Read_Data(nregType, 7, (uint32_t *)r, dataSize);
#ifdef DSA_DBG
MSG("r:\r\n");
bflb_platform_dump(r, dataSize /*dataSize*4*/);
#endif
return 0;
}
/**
* dP=d%(p-1)
* dQ=d%(q-1)
* qInv=qp^(1-1):qInv*q%p=1
* invR_p*r%p=1(r is 1024/2048/256)
* invR_q*r%q=1(r is 1024/2048/256)
*/
int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r)
{
/*
* m1 = pow(c, dP, p)
* m2 = pow(c, dQ, q)
* h = (qInv * (m1 - m2)) % p
* m = m2 + h * q
* */
SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size);
SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2);
uint32_t dataSize = (size >> 3) >> 2;
#if 0
uint8_t m1[64] = {0x11, 0xdd, 0x19, 0x7e, 0x69, 0x1a, 0x40, 0x0a, 0x28, 0xfc, 0x3b, 0x31, 0x47, 0xa2, 0x6c, 0x14,
0x4e, 0xf6, 0xb0, 0xe6, 0xcd, 0x89, 0x0b, 0x4f, 0x02, 0xe4, 0x86, 0xe2, 0xe5, 0xbe, 0xe1, 0xaf,
0x91, 0xd1, 0x7b, 0x59, 0x8d, 0xdc, 0xb3, 0x57, 0x18, 0xcb, 0x80, 0x05, 0x1c, 0xb5, 0xa4, 0x07,
0xde, 0x31, 0x94, 0xa4, 0x2f, 0x45, 0xc7, 0x95, 0x75, 0x0f, 0x91, 0xf0, 0x37, 0x91, 0x85, 0xa5
};
uint8_t m2[64] = {0x63, 0x89, 0xa3, 0xbb, 0x64, 0x63, 0x87, 0x4f, 0x38, 0xbd, 0x9e, 0x0e, 0x93, 0x29, 0x58, 0xee,
0xf8, 0xe2, 0x20, 0x2d, 0xe5, 0x38, 0x0a, 0x7f, 0x18, 0x38, 0x2f, 0xa3, 0xf5, 0x48, 0xf8, 0xfd,
0xe5, 0x78, 0x4a, 0x10, 0x62, 0x01, 0x09, 0x29, 0xe3, 0xe3, 0x9f, 0xad, 0x9b, 0xbe, 0x20, 0xd2,
0x68, 0x90, 0x57, 0x97, 0xfc, 0x78, 0xd5, 0xdb, 0x07, 0x5b, 0xfe, 0x21, 0x0a, 0x2d, 0x7f, 0xc1
};
#else
uint32_t m1[32];
uint32_t m2[32];
#endif
/*
* 4:m1
* 5:m2
* 6:qInv
* 7:p
* 8:q
* 9:h
* 10&11:qInv*(m1-m2)
*/
sec_dsa_mexp_mont(size, c, crtCfg->dP, crtCfg->p, crtCfg->invR_p, crtCfg->primeN_p, m1);
sec_dsa_mexp_mont(size, c, crtCfg->dQ, crtCfg->q, crtCfg->invR_q, crtCfg->primeN_q, m2);
Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)m1, dataSize, 0);
Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)m2, dataSize, 0);
Sec_Eng_PKA_Write_Data(nregType, 6, (uint32_t *)crtCfg->qInv, dataSize, 0);
Sec_Eng_PKA_Write_Data(nregType, 7, (uint32_t *)crtCfg->p, dataSize, 0);
Sec_Eng_PKA_Write_Data(nregType, 8, (uint32_t *)crtCfg->q, dataSize, 0);
/*(m1 - m2)%p*/
Sec_Eng_PKA_MSUB(nregType, 4, nregType, 4, nregType, 5, nregType, 7, 1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
MSG("m1 - m2:\r\n");
bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
#endif
/* (qInv * (m1 - m2)) % p*/
Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
Sec_Eng_PKA_LMUL(lregType, 5, nregType, 6, nregType, 4, 1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2);
MSG("qInv * (m1 - m2):\r\n");
bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/);
#endif
Sec_Eng_PKA_MREM(nregType, 9, lregType, 5, nregType, 7, 1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType, 9, (uint32_t *)pka_tmp, dataSize);
MSG("h:\r\n");
bflb_platform_dump(pka_tmp, dataSize * 4);
#endif
/* h*q */
Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
Sec_Eng_PKA_LMUL(lregType, 5, nregType, 9, nregType, 8, 1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2);
MSG("h*q:\r\n");
bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/);
#endif
/* m2 + h*q*/
Sec_Eng_PKA_LADD(lregType, 5, lregType, 5, nregType, 5, 1);
Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)r, dataSize * 2);
#ifdef DSA_DBG
MSG("r:\r\n");
bflb_platform_dump(r, dataSize * 4 * 2);
#endif
return 0;
}
int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size)
{
Sec_Eng_PKA_Reset();
Sec_Eng_PKA_BigEndian_Enable();
memset(handle, 0, sizeof(sec_dsa_handle_t));
handle->size = size;
handle->crtSize = (size >> 1);
return 0;
}
int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s)
{
uint32_t dsa_tmp[64] = { 0 };
Sec_Eng_PKA_Reset();
Sec_Eng_PKA_BigEndian_Enable();
memcpy(dsa_tmp + ((handle->crtSize >> 3) >> 2) - hashLenInWord, hash, hashLenInWord * 4);
if (0 == sec_dsa_decrypt_crt(handle->crtSize, dsa_tmp, &handle->crtCfg, handle->d, s)) {
return 0;
} else {
return -1;
}
}
/**
*/
int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s)
{
uint32_t dsa_tmp[64];
uint8_t i = 0;
uint8_t resultOffset = 0;
Sec_Eng_PKA_Reset();
Sec_Eng_PKA_BigEndian_Enable();
if (0 == sec_dsa_mexp_binary(handle->size, s, handle->e, handle->n, dsa_tmp)) {
resultOffset = (handle->size >> 5) - hashLenInWord;
for (i = 0; i < hashLenInWord; i++) {
if (dsa_tmp[resultOffset + i] != hash[i]) {
return -1;
}
}
return 0;
} else {
return -1;
}
}

1450
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c
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File diff suppressed because it is too large Load Diff

387
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c
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@@ -1,387 +0,0 @@
/**
* @file hal_sec_hash.c
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_sec_hash.h"
#include "bl702_sec_eng.h"
void SEC_SHA_IRQHandler(void);
static sec_hash_device_t sec_hashx_device[SEC_HASH_MAX_INDEX] = {
0
};
static SEC_Eng_SHA256_Ctx shaCtx;
static SEC_Eng_SHA256_Ctx sha256Ctx;
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int sec_hash_open(struct device *dev, uint16_t oflag)
{
sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
int ret = 0;
switch (sec_hash_device->type) {
case SEC_HASH_SHA1:
ret = -1;
break;
case SEC_HASH_SHA224:
Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, sec_hash_device->shaBuf, sec_hash_device->shaPadding);
Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
break;
case SEC_HASH_SHA256:
Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, sec_hash_device->shaBuf, sec_hash_device->shaPadding);
Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
break;
case SEC_HASH_SHA384:
case SEC_HASH_SHA512:
ret = -1;
break;
default:
ret = -1;
break;
}
return ret;
}
/**
* @brief
*
* @param dev
* @return int
*/
int sec_hash_close(struct device *dev)
{
//sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
//memset(sec_hash_device, 0, sizeof(sec_hash_device_t)); //will cause crash
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int sec_hash_control(struct device *dev, int cmd, void *args)
{
return 0;
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int sec_hash_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
int ret = 0;
switch (sec_hash_device->type) {
case SEC_HASH_SHA1:
ret = -1;
break;
case SEC_HASH_SHA224:
Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
break;
case SEC_HASH_SHA256:
Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
break;
case SEC_HASH_SHA384:
case SEC_HASH_SHA512:
ret = -1;
break;
default:
ret = -1;
break;
}
return ret;
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int sec_hash_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
int ret = 0;
switch (sec_hash_device->type) {
case SEC_HASH_SHA1:
ret = -1;
break;
case SEC_HASH_SHA224:
Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
ret = 28;
break;
case SEC_HASH_SHA256:
Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
ret = 32;
break;
case SEC_HASH_SHA384:
case SEC_HASH_SHA512:
ret = -1;
break;
default:
ret = -1;
break;
}
return ret;
}
/**
* @brief
*
* @param handle
* @param type
* @return int
*/
int sec_hash_init(sec_hash_handle_t *handle, uint8_t type)
{
int ret = 0;
switch (type) {
case SEC_HASH_SHA1:
ret = -1;
break;
case SEC_HASH_SHA224:
handle->type = type;
Sec_Eng_SHA256_Init(&sha256Ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, handle->shaBuf, handle->shaPadding);
Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
break;
case SEC_HASH_SHA256:
handle->type = type;
Sec_Eng_SHA256_Init(&sha256Ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, handle->shaBuf, handle->shaPadding);
Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
break;
case SEC_HASH_SHA384:
case SEC_HASH_SHA512:
ret = -1;
break;
default:
ret = -1;
break;
}
return ret;
}
/**
* @brief
*
* @param handle
* @return int
*/
int sec_hash_deinit(sec_hash_handle_t *handle)
{
memset(handle->shaBuf, 0, sizeof(handle->shaBuf));
memset(handle->shaPadding, 0, sizeof(handle->shaPadding));
return 0;
}
/**
* @brief
*
* @param handle
* @param buffer
* @param size
* @return int
*/
int sec_hash_update(sec_hash_handle_t *handle, const void *buffer, uint32_t size)
{
int ret = 0;
switch (handle->type) {
case SEC_HASH_SHA1:
ret = -1;
break;
case SEC_HASH_SHA224:
Sec_Eng_SHA256_Update(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
break;
case SEC_HASH_SHA256:
Sec_Eng_SHA256_Update(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
break;
case SEC_HASH_SHA384:
case SEC_HASH_SHA512:
ret = -1;
break;
default:
ret = -1;
break;
}
return ret;
}
/**
* @brief
*
* @param handle
* @param buffer
* @return int
*/
int sec_hash_finish(sec_hash_handle_t *handle, void *buffer)
{
int ret = 0;
switch (handle->type) {
case SEC_HASH_SHA1:
ret = -1;
break;
case SEC_HASH_SHA224:
Sec_Eng_SHA256_Finish(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
ret = 28;
break;
case SEC_HASH_SHA256:
Sec_Eng_SHA256_Finish(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
ret = 32;
break;
case SEC_HASH_SHA384:
case SEC_HASH_SHA512:
ret = -1;
break;
default:
ret = -1;
break;
}
return ret;
}
/**
* @brief
*
* @param index
* @param type
* @param name
* @param flag
* @return int
*/
static int sec_hash_sha_register(enum sec_hash_index_type index, enum sec_hash_type type, const char *name)
{
struct device *dev;
if (SEC_HASH_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(sec_hashx_device[index].parent);
sec_hashx_device[index].type = type;
dev->open = sec_hash_open;
dev->close = sec_hash_close;
dev->control = sec_hash_control;
dev->write = sec_hash_write;
dev->read = sec_hash_read;
dev->type = DEVICE_CLASS_SEC_HASH;
dev->handle = NULL;
return device_register(dev, name);
}
/**
* @brief
*
* @param index
* @param name
* @param flag
* @return int
*/
int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name)
{
return sec_hash_sha_register(index, SEC_HASH_SHA256, name);
}
/**
* @brief
*
* @param index
* @param name
* @param flag
* @return int
*/
int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name)
{
return sec_hash_sha_register(index, SEC_HASH_SHA224, name);
}
/**
* @brief
*
* @param handle
*/
void sec_hash_isr(void)
{
}
/**
* @brief
*
*/
void SEC_SHA_IRQ(void)
{
sec_hash_isr();
}

537
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_spi.c
View File

@@ -1,537 +0,0 @@
/**
* @file hal_spi.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_spi.h"
#include "hal_dma.h"
#include "bl702_glb.h"
#include "bl702_spi.h"
#ifdef BSP_USING_SPI0
static void SPI0_IRQ(void);
#endif
static spi_device_t spix_device[SPI_MAX_INDEX] = {
#ifdef BSP_USING_SPI0
SPI0_CONFIG,
#endif
};
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int spi_open(struct device *dev, uint16_t oflag)
{
spi_device_t *spi_device = (spi_device_t *)dev;
SPI_CFG_Type spiCfg = { 0 };
SPI_FifoCfg_Type fifoCfg = { 0 };
if (spi_device->pin_swap_enable) {
GLB_Swap_SPI_0_MOSI_With_MISO(ENABLE);
}
/* Enable uart interrupt*/
CPU_Interrupt_Disable(SPI_IRQn);
SPI_IntMask(spi_device->id, SPI_INT_ALL, MASK);
SPI_Disable(spi_device->id, spi_device->mode);
GLB_Set_SPI_0_ACT_MOD_Sel(spi_device->mode);
/* Set SPI clock */
SPI_ClockCfg_Type clockCfg = {
2, /* Length of start condition */
2, /* Length of stop condition */
2, /* Length of data phase 0,affecting clock */
2, /* Length of data phase 1,affecting clock */
2 /* Length of interval between frame */
};
if (spi_device->clk > 72 * 1000000) {
return -1;
}
uint8_t length = 72 * 1000000 / spi_device->clk;
if (!(length % 2)) {
clockCfg.dataPhase0Len = length / 2;
clockCfg.dataPhase1Len = length / 2;
} else {
clockCfg.dataPhase0Len = length / 2;
clockCfg.dataPhase1Len = length / 2 + 1;
}
SPI_ClockConfig(spi_device->id, &clockCfg);
spiCfg.continuousEnable = 1;
if (spi_device->direction == SPI_LSB_BYTE0_DIRECTION_FIRST) {
spiCfg.bitSequence = SPI_BIT_INVERSE_LSB_FIRST;
spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE0_FIRST;
} else if (spi_device->direction == SPI_LSB_BYTE3_DIRECTION_FIRST) {
spiCfg.bitSequence = SPI_BIT_INVERSE_LSB_FIRST;
spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE3_FIRST;
} else if (spi_device->direction == SPI_MSB_BYTE0_DIRECTION_FIRST) {
spiCfg.bitSequence = SPI_BIT_INVERSE_MSB_FIRST;
spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE0_FIRST;
} else if (spi_device->direction == SPI_MSB_BYTE3_DIRECTION_FIRST) {
spiCfg.bitSequence = SPI_BIT_INVERSE_MSB_FIRST;
spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE3_FIRST;
}
spiCfg.clkPolarity = spi_device->clk_polaraity;
spiCfg.clkPhaseInv = spi_device->clk_phase;
spiCfg.frameSize = spi_device->datasize;
if (spi_device->delitch_cnt) {
spiCfg.deglitchEnable = 1;
}
/* SPI config */
SPI_Init(spi_device->id, &spiCfg);
SPI_SetDeglitchCount(spi_device->id, spi_device->delitch_cnt);
fifoCfg.txFifoThreshold = spi_device->fifo_threshold;
fifoCfg.txFifoDmaEnable = DISABLE;
fifoCfg.rxFifoThreshold = spi_device->fifo_threshold;
fifoCfg.rxFifoDmaEnable = DISABLE;
if (oflag & DEVICE_OFLAG_INT_TX || oflag & DEVICE_OFLAG_INT_RX) {
#ifdef BSP_USING_SPI0
Interrupt_Handler_Register(SPI_IRQn, SPI0_IRQ);
#endif
}
if (oflag & DEVICE_OFLAG_DMA_TX) {
fifoCfg.txFifoDmaEnable = ENABLE;
}
if (oflag & DEVICE_OFLAG_DMA_RX) {
fifoCfg.rxFifoDmaEnable = ENABLE;
}
SPI_FifoConfig(spi_device->id, &fifoCfg);
/* Enable spi master mode */
SPI_Enable(spi_device->id, spi_device->mode);
return 0;
}
/**
* @brief
*
* @param dev
* @return int
*/
int spi_close(struct device *dev)
{
spi_device_t *spi_device = (spi_device_t *)dev;
SPI_Disable(spi_device->id, spi_device->mode);
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SPI);
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int spi_control(struct device *dev, int cmd, void *args)
{
spi_device_t *spi_device = (spi_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT /* constant-expression */:
break;
case DEVICE_CTRL_CLR_INT /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_GET_INT /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_RESUME:
/* code */
SPI_Enable(spi_device->id, spi_device->mode);
break;
case DEVICE_CTRL_SUSPEND:
SPI_Disable(spi_device->id, spi_device->mode);
break;
case DEVICE_CTRL_CONFIG /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
spi_device->tx_dma = (struct device *)args;
break;
case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
spi_device->rx_dma = (struct device *)args;
break;
case DEVICE_CTRL_SPI_CONFIG_CLOCK /* constant-expression */:
SPI_SetClock(spi_device->id, (uint32_t)args);
break;
case DEVICE_CTRL_TX_DMA_SUSPEND: {
uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0);
tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_DMA_TX_EN);
BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal);
dev->oflag &= ~DEVICE_OFLAG_DMA_TX;
break;
}
case DEVICE_CTRL_RX_DMA_SUSPEND: {
uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0);
tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_DMA_RX_EN);
BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal);
dev->oflag &= ~DEVICE_OFLAG_DMA_RX;
break;
}
case DEVICE_CTRL_TX_DMA_RESUME: {
uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal, SPI_DMA_TX_EN);
BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal);
dev->oflag |= DEVICE_OFLAG_DMA_TX;
break;
}
case DEVICE_CTRL_RX_DMA_RESUME: {
uint32_t tmpVal = BL_RD_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal, SPI_DMA_RX_EN);
BL_WR_REG(SPI_BASE + spi_device->id * 0x100, SPI_FIFO_CONFIG_0, tmpVal);
dev->oflag |= DEVICE_OFLAG_DMA_RX;
break;
}
case DEVICE_CTRL_SPI_GET_TX_FIFO :
return SPI_GetTxFifoCount(spi_device->id);
case DEVICE_CTRL_SPI_GET_RX_FIFO :
return SPI_GetRxFifoCount(spi_device->id);
case DEVICE_CTRL_SPI_CLEAR_TX_FIFO :
return SPI_ClrTxFifo(spi_device->id);
case DEVICE_CTRL_SPI_CLEAR_RX_FIFO :
return SPI_ClrRxFifo(spi_device->id);
case DEVICE_CTRL_SPI_GET_BUS_BUSY_STATUS :
return SPI_GetBusyStatus(spi_device->id);
default:
break;
}
return 0;
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int spi_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
int ret = 0;
spi_device_t *spi_device = (spi_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_TX) {
struct device *dma_ch = (struct device *)spi_device->tx_dma;
if (!dma_ch) {
return -1;
}
if (spi_device->id == 0) {
/* Set valid width for each fifo entry */
uint32_t tmpVal;
uint32_t SPIx = SPI_BASE;
tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
switch (DMA_DEV(dma_ch)->dst_width) {
case DMA_TRANSFER_WIDTH_8BIT:
BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0));
break;
case DMA_TRANSFER_WIDTH_16BIT:
BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1));
break;
case DMA_TRANSFER_WIDTH_32BIT:
BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3));
break;
default:
break;
}
ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_SPI_TDR, size);
dma_channel_start(dma_ch);
}
return ret;
} else if (dev->oflag & DEVICE_OFLAG_INT_TX) {
return -2;
} else {
if (spi_device->datasize == SPI_DATASIZE_8BIT) {
return SPI_Send_8bits(spi_device->id, (uint8_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else if (spi_device->datasize == SPI_DATASIZE_16BIT) {
return SPI_Send_16bits(spi_device->id, (uint16_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else if (spi_device->datasize == SPI_DATASIZE_24BIT) {
return SPI_Send_24bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else {
return SPI_Send_32bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE);
}
}
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int spi_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
int ret = 0;
spi_device_t *spi_device = (spi_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_RX) {
struct device *dma_ch = (struct device *)spi_device->rx_dma;
if (!dma_ch) {
return -1;
}
if (spi_device->id == 0) {
/* Set valid width for each fifo entry */
uint32_t tmpVal;
uint32_t SPIx = SPI_BASE;
tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
switch (DMA_DEV(dma_ch)->src_width) {
case DMA_TRANSFER_WIDTH_8BIT:
BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0));
break;
case DMA_TRANSFER_WIDTH_16BIT:
BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1));
break;
case DMA_TRANSFER_WIDTH_32BIT:
BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3));
break;
default:
break;
}
ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_SPI_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
}
return ret;
} else if (dev->oflag & DEVICE_OFLAG_INT_TX) {
return -2;
} else {
if (spi_device->datasize == SPI_DATASIZE_8BIT) {
return SPI_Recv_8bits(spi_device->id, (uint8_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else if (spi_device->datasize == SPI_DATASIZE_16BIT) {
return SPI_Recv_16bits(spi_device->id, (uint16_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else if (spi_device->datasize == SPI_DATASIZE_24BIT) {
return SPI_Recv_24bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else {
return SPI_Recv_32bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE);
}
}
}
/**
* @brief
*
* @param index
* @param name
* @param flag
* @return int
*/
int spi_register(enum spi_index_type index, const char *name)
{
struct device *dev;
if (SPI_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(spix_device[index].parent);
dev->open = spi_open;
dev->close = spi_close;
dev->control = spi_control;
dev->write = spi_write;
dev->read = spi_read;
dev->type = DEVICE_CLASS_SPI;
dev->handle = NULL;
return device_register(dev, name);
}
/**
* @brief
*
* @param dev
* @param buffer
* @param size
* @param type
* @return int
*/
int spi_transmit(struct device *dev, void *buffer, uint32_t size, uint8_t type)
{
spi_device_t *spi_device = (spi_device_t *)dev;
if (type == 0) {
return SPI_Send_8bits(spi_device->id, (uint8_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else if (type == 1) {
return SPI_Send_16bits(spi_device->id, (uint16_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else if (type == 2) {
return SPI_Send_24bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else if (type == 3) {
return SPI_Send_32bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE);
}
return -1;
}
/**
* @brief
*
* @param dev
* @param buffer
* @param size
* @param type
* @return int
*/
int spi_receive(struct device *dev, void *buffer, uint32_t size, uint8_t type)
{
spi_device_t *spi_device = (spi_device_t *)dev;
if (type == 0) {
return SPI_Recv_8bits(spi_device->id, (uint8_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else if (type == 1) {
return SPI_Recv_16bits(spi_device->id, (uint16_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else if (type == 2) {
return SPI_Recv_24bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE);
} else if (type == 3) {
return SPI_Recv_32bits(spi_device->id, (uint32_t *)buffer, size, SPI_TIMEOUT_DISABLE);
}
return -1;
}
/**
* @brief
*
* @param dev
* @param send_buf
* @param recv_buf
* @param length
* @param type
* @return int
*/
int spi_transmit_receive(struct device *dev, const void *send_buf, void *recv_buf, uint32_t length, uint8_t type)
{
spi_device_t *spi_device = (spi_device_t *)dev;
if (type == 0) {
return SPI_SendRecv_8bits(spi_device->id, (uint8_t *)send_buf, (uint8_t *)recv_buf, length, SPI_TIMEOUT_DISABLE);
} else if (type == 1) {
return SPI_SendRecv_16bits(spi_device->id, (uint16_t *)send_buf, (uint16_t *)recv_buf, length, SPI_TIMEOUT_DISABLE);
} else if (type == 2) {
return SPI_SendRecv_24bits(spi_device->id, (uint32_t *)send_buf, (uint32_t *)recv_buf, length, SPI_TIMEOUT_DISABLE);
} else if (type == 3) {
return SPI_SendRecv_32bits(spi_device->id, (uint32_t *)send_buf, (uint32_t *)recv_buf, length, SPI_TIMEOUT_DISABLE);
}
return -1;
}
/**
* @brief
*
* @param handle
*/
void spi_isr(spi_device_t *handle)
{
uint32_t tmpVal;
uint32_t SPIx = SPI_BASE + handle->id * 0x100;
tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);
if (!handle->parent.callback) {
return;
}
/* Transfer end interrupt,shared by both master and slave mode */
if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) {
BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR));
handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_END);
}
/* TX fifo ready interrupt(fifo count > fifo threshold) */
if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) {
handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_TX_FIFO_REQ);
}
/* RX fifo ready interrupt(fifo count > fifo threshold) */
if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) {
handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_RX_FIFO_REQ);
}
/* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */
if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) {
BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR));
handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_SLAVE_TIMEOUT);
}
/* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */
if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) {
BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR));
handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_SLAVE_UNDERRUN);
}
/* TX/RX fifo overflow/underflow interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) {
handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_FIFO_ERROR);
}
}
#ifdef BSP_USING_SPI0
void SPI0_IRQ()
{
spi_isr(&spix_device[SPI0_INDEX]);
}
#endif

389
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_timer.c
View File

@@ -1,389 +0,0 @@
/**
* @file hal_timer.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_timer.h"
#include "hal_clock.h"
#include "bl702_glb.h"
#include "bl702_timer.h"
#ifdef BSP_USING_TIMER0
void TIMER0_IRQ(void);
#endif
#ifdef BSP_USING_TIMER1
void TIMER1_IRQ(void);
#endif
static timer_device_t timerx_device[TIMER_MAX_INDEX] = {
#ifdef BSP_USING_TIMER0
TIMER0_CONFIG,
#endif
#ifdef BSP_USING_TIMER1
TIMER1_CONFIG,
#endif
};
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int timer_open(struct device *dev, uint16_t oflag)
{
timer_device_t *timer_device = (timer_device_t *)dev;
uint32_t tmpval;
uint32_t compare_count1 = 0;
uint32_t compare_count2 = 0;
uint32_t compare_count3 = 0;
uint32_t reload_val = 0;
uint32_t clkval = 0;
uint32_t unit = 0;
/* Disable all interrupt */
TIMER_IntMask(timer_device->id, TIMER_INT_ALL, MASK);
/* Disable timer before config */
TIMER_Disable(timer_device->id);
/* Configure timer count mode: preload or free run */
tmpval = BL_RD_WORD(TIMER_BASE + TIMER_TCMR_OFFSET);
tmpval &= (~(1 << (timer_device->id + 1)));
tmpval |= (timer_device->cnt_mode << (timer_device->id + 1));
BL_WR_WORD(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval);
/* Configure timer preload trigger source */
BL_WR_WORD(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timer_device->id, timer_device->trigger);
if (timer_device->cnt_mode == TIMER_CNT_PRELOAD) {
BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_device->id, timer_device->reload);
reload_val = timer_device->reload;
}
if (timer_device->id == TIMER_CH0) {
clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0);
} else {
clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1);
}
if (clkval % 1000000 == 0) {
unit = 1000000; //1us
} else if (clkval % 100000 == 0) {
unit = 100000; //10us
} else if (clkval % 10000 == 0) {
unit = 10000; //100us
} else if (clkval % 1000 == 0) {
unit = 1000; //1ms
} else if (clkval % 100 == 0) {
unit = 100; //10ms
} else if (clkval % 10 == 0) {
unit = 10; //100ms
} else if (clkval % 1 == 0) {
unit = 1; //s
} else {
}
compare_count1 = timer_device->timeout1 / (1000000 / unit) * (clkval / unit) + reload_val;
compare_count2 = timer_device->timeout2 / (1000000 / unit) * (clkval / unit) + reload_val;
compare_count3 = timer_device->timeout3 / (1000000 / unit) * (clkval / unit) + reload_val;
/* Configure match compare values */
if ((compare_count1 < 1) || (compare_count2 < 1) || (compare_count3 < 1)) {
return -1;
}
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_0, compare_count1 - 2);
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_1, compare_count2 - 2);
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_2, compare_count3 - 2);
/* Clear interrupt status*/
TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_0);
TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_1);
TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_2);
if (oflag & DEVICE_OFLAG_STREAM_TX) {
/* Enable timer match interrupt */
/* Note: if not enable match interrupt, TIMER_GetMatchStatus will not work
and status bit will not set */
TIMER_IntMask(timer_device->id, TIMER_INT_COMP_0, UNMASK);
TIMER_IntMask(timer_device->id, TIMER_INT_COMP_1, UNMASK);
TIMER_IntMask(timer_device->id, TIMER_INT_COMP_2, UNMASK);
}
if (oflag & DEVICE_OFLAG_INT_TX) {
#ifdef BSP_USING_TIMER0
if (timer_device->id == TIMER_CH0) {
Interrupt_Handler_Register(TIMER_CH0_IRQn, TIMER0_IRQ);
}
#endif
#ifdef BSP_USING_TIMER1
if (timer_device->id == TIMER_CH1) {
Interrupt_Handler_Register(TIMER_CH1_IRQn, TIMER1_IRQ);
}
#endif
}
/* Enable timer */
TIMER_Enable(timer_device->id);
return 0;
}
/**
* @brief
*
* @param dev
* @return int
*/
int timer_close(struct device *dev)
{
timer_device_t *timer_device = (timer_device_t *)(dev);
TIMER_Disable(timer_device->id);
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int timer_control(struct device *dev, int cmd, void *args)
{
timer_device_t *timer_device = (timer_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT /* constant-expression */: {
uint32_t offset = __builtin_ctz((uint32_t)args);
while (offset < 3) {
if ((uint32_t)args & (1 << offset)) {
TIMER_IntMask(timer_device->id, offset, UNMASK);
}
offset++;
}
if (timer_device->id == TIMER_CH0) {
CPU_Interrupt_Pending_Clear(TIMER_CH0_IRQn);
CPU_Interrupt_Enable(TIMER_CH0_IRQn);
} else if (timer_device->id == TIMER_CH1) {
CPU_Interrupt_Pending_Clear(TIMER_CH1_IRQn);
CPU_Interrupt_Enable(TIMER_CH1_IRQn);
}
break;
}
case DEVICE_CTRL_CLR_INT /* constant-expression */: {
uint32_t offset = __builtin_ctz((uint32_t)args);
while (offset < 3) {
if ((uint32_t)args & (1 << offset)) {
TIMER_IntMask(timer_device->id, offset, MASK);
}
offset++;
}
if (timer_device->id == TIMER_CH0) {
CPU_Interrupt_Disable(TIMER_CH0_IRQn);
} else if (timer_device->id == TIMER_CH1) {
CPU_Interrupt_Disable(TIMER_CH1_IRQn);
}
break;
}
case DEVICE_CTRL_GET_INT /* constant-expression */: {
uint32_t offset = __builtin_ctz((uint32_t)args);
uint32_t intstatus = TIMER_GetMatchStatus(timer_device->id, offset);
/* Clear interrupt status*/
TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_0);
TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_1);
TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_2);
return intstatus;
}
case DEVICE_CTRL_CONFIG /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_RESUME /* constant-expression */: {
/* Enable timer */
TIMER_Enable(timer_device->id);
break;
}
case DEVICE_CTRL_SUSPEND /* constant-expression */: {
TIMER_Disable(timer_device->id);
break;
}
case DEVICE_CTRL_GET_CONFIG:
return TIMER_GetCounterValue(timer_device->id);
default:
break;
}
return 0;
}
int timer_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
timer_device_t *timer_device = (timer_device_t *)dev;
timer_timeout_cfg_t *timeout_cfg = (timer_timeout_cfg_t *)buffer;
uint32_t compare_count = 0;
uint32_t reload_val = 0;
uint32_t clkval = 0;
uint32_t unit = 0;
if (size % sizeof(timer_timeout_cfg_t)) {
return -1;
}
/* Disable timer before config */
TIMER_Disable(timer_device->id);
if (timer_device->cnt_mode == TIMER_CNT_PRELOAD) {
reload_val = timer_device->reload;
}
if (timer_device->id == TIMER_CH0) {
clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0);
} else {
clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1);
}
if (clkval % 1000000 == 0) {
unit = 1000000; //1us
} else if (clkval % 100000 == 0) {
unit = 100000; //10us
} else if (clkval % 10000 == 0) {
unit = 10000; //100us
} else if (clkval % 1000 == 0) {
unit = 1000; //1ms
} else if (clkval % 100 == 0) {
unit = 100; //10ms
} else if (clkval % 10 == 0) {
unit = 10; //100ms
} else if (clkval % 1 == 0) {
unit = 1; //s
} else {
}
for (uint32_t i = 0; i < size / sizeof(timer_timeout_cfg_t); i++) {
compare_count = timeout_cfg->timeout_val / (1000000 / unit) * (clkval / unit) + reload_val;
if (compare_count < 1) {
return -1;
}
TIMER_SetCompValue(timer_device->id, timeout_cfg->timeout_id, compare_count - 2);
}
TIMER_Enable(timer_device->id);
return 0;
}
int timer_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
return 0;
}
/**
* @brief
*
* @param index
* @param name
* @return int
*/
int timer_register(enum timer_index_type index, const char *name)
{
struct device *dev;
if (TIMER_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(timerx_device[index].parent);
dev->open = timer_open;
dev->close = timer_close;
dev->control = timer_control;
dev->write = timer_write;
// dev->read = NULL;
dev->type = DEVICE_CLASS_TIMER;
dev->handle = NULL;
return device_register(dev, name);
}
void timer_isr(timer_device_t *handle)
{
uint32_t intId = 0;
uint32_t tmpVal = 0;
uint32_t tmpAddr = 0;
if (!handle->parent.callback) {
return;
}
intId = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * handle->id);
tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * handle->id;
tmpVal = BL_RD_WORD(tmpAddr);
/* Comparator 0 match interrupt */
if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_0)) {
BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_0));
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP0);
}
/* Comparator 1 match interrupt */
if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_1)) {
BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_1));
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP1);
}
/* Comparator 2 match interrupt */
if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_2)) {
BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_2));
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP2);
}
}
#ifdef BSP_USING_TIMER0
/**
* @brief
*
*/
void TIMER0_IRQ(void)
{
timer_isr(&timerx_device[TIMER0_INDEX]);
}
#endif
#ifdef BSP_USING_TIMER1
/**
* @brief
*
*/
void TIMER1_IRQ(void)
{
timer_isr(&timerx_device[TIMER1_INDEX]);
}
#endif

442
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_uart.c
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@@ -1,442 +0,0 @@
/**
* @file hal_uart.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_uart.h"
#include "hal_dma.h"
#include "hal_clock.h"
#include "bl702_uart.h"
#include "bl702_glb.h"
#include "uart_config.h"
#ifdef BSP_USING_UART0
static void UART0_IRQ(void);
#endif
#ifdef BSP_USING_UART1
static void UART1_IRQ(void);
#endif
static uart_device_t uartx_device[UART_MAX_INDEX] = {
#ifdef BSP_USING_UART0
UART0_CONFIG,
#endif
#ifdef BSP_USING_UART1
UART1_CONFIG,
#endif
};
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int uart_open(struct device *dev, uint16_t oflag)
{
uart_device_t *uart_device = (uart_device_t *)dev;
UART_FifoCfg_Type fifoCfg = { 0 };
UART_CFG_Type uart_cfg = { 0 };
/* disable all interrupt */
UART_IntMask(uart_device->id, UART_INT_ALL, MASK);
/* disable uart before config */
UART_Disable(uart_device->id, UART_TXRX);
uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART);
uart_cfg.baudRate = uart_device->baudrate;
uart_cfg.dataBits = uart_device->databits;
uart_cfg.stopBits = uart_device->stopbits;
uart_cfg.parity = uart_device->parity;
uart_cfg.uartClk = uart_clk;
uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE;
uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE;
uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE;
uart_cfg.txSoftwareControl = UART_TX_SWCONTROL_ENABLE;
uart_cfg.txLinMode = UART_TX_LINMODE_ENABLE;
uart_cfg.rxLinMode = UART_RX_LINMODE_ENABLE;
uart_cfg.txBreakBitCnt = UART_TX_BREAKBIT_CNT;
uart_cfg.rxDeglitch = ENABLE;
/* uart init with default configuration */
UART_Init(uart_device->id, &uart_cfg);
/* Enable tx free run mode */
UART_TxFreeRun(uart_device->id, ENABLE);
/*set de-glitch function cycle count value*/
UART_SetDeglitchCount(uart_device->id, 2);
/* Set rx time-out value */
UART_SetRxTimeoutValue(uart_device->id, UART_DEFAULT_RTO_TIMEOUT);
fifoCfg.txFifoDmaThreshold = uart_device->fifo_threshold;
fifoCfg.txFifoDmaEnable = DISABLE;
fifoCfg.rxFifoDmaThreshold = uart_device->fifo_threshold;
fifoCfg.rxFifoDmaEnable = DISABLE;
if (oflag & DEVICE_OFLAG_STREAM_TX) {
}
if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) {
#ifdef BSP_USING_UART0
if (uart_device->id == UART0_ID)
Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ);
#endif
#ifdef BSP_USING_UART1
if (uart_device->id == UART1_ID)
Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ);
#endif
}
if (oflag & DEVICE_OFLAG_DMA_TX) {
fifoCfg.txFifoDmaEnable = ENABLE;
}
if (oflag & DEVICE_OFLAG_DMA_RX) {
fifoCfg.rxFifoDmaEnable = ENABLE;
}
UART_FifoConfig(uart_device->id, &fifoCfg);
/* enable uart */
UART_Enable(uart_device->id, UART_TXRX);
return 0;
}
/**
* @brief
*
* @param dev
* @return int
*/
int uart_close(struct device *dev)
{
uart_device_t *uart_device = (uart_device_t *)dev;
UART_Disable(uart_device->id, UART_TXRX);
if (uart_device->id == 0) {
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0);
} else if (uart_device->id == 1) {
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
}
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int uart_control(struct device *dev, int cmd, void *args)
{
uart_device_t *uart_device = (uart_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT /* constant-expression */: {
uint32_t offset = __builtin_ctz((uint32_t)args);
while (offset < 9) {
if ((uint32_t)args & (1 << offset)) {
UART_IntMask(uart_device->id, offset, UNMASK);
}
offset++;
}
if (uart_device->id == UART0_ID)
CPU_Interrupt_Enable(UART0_IRQn);
else if (uart_device->id == UART1_ID)
CPU_Interrupt_Enable(UART1_IRQn);
break;
}
case DEVICE_CTRL_CLR_INT /* constant-expression */: {
uint32_t offset = __builtin_ctz((uint32_t)args);
while (offset < 9) {
if ((uint32_t)args & (1 << offset)) {
UART_IntMask(uart_device->id, offset, MASK);
}
offset++;
}
if (uart_device->id == UART0_ID)
CPU_Interrupt_Disable(UART0_IRQn);
else if (uart_device->id == UART1_ID)
CPU_Interrupt_Disable(UART1_IRQn);
break;
}
case DEVICE_CTRL_GET_INT /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_RESUME /* constant-expression */:
UART_Enable(uart_device->id, UART_TXRX);
break;
case DEVICE_CTRL_SUSPEND /* constant-expression */:
UART_Disable(uart_device->id, UART_TXRX);
break;
case DEVICE_CTRL_CONFIG /* constant-expression */: {
uart_param_cfg_t *cfg = (uart_param_cfg_t *)args;
UART_CFG_Type uart_cfg;
uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART);
uart_cfg.uartClk = uart_clk;
uart_cfg.baudRate = cfg->baudrate;
uart_cfg.stopBits = cfg->stopbits;
uart_cfg.parity = cfg->parity;
uart_cfg.dataBits = cfg->databits;
uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE;
uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE;
uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE;
uart_cfg.txSoftwareControl = UART_TX_SWCONTROL_ENABLE;
uart_cfg.txLinMode = UART_TX_LINMODE_ENABLE;
uart_cfg.rxLinMode = UART_RX_LINMODE_ENABLE;
uart_cfg.txBreakBitCnt = UART_TX_BREAKBIT_CNT;
uart_cfg.rxDeglitch = ENABLE;
UART_Init(uart_device->id, &uart_cfg);
/*set de-glitch function cycle count value*/
UART_SetDeglitchCount(uart_device->id, 2);
break;
}
case DEVICE_CTRL_GET_CONFIG /* constant-expression */:
break;
case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
uart_device->tx_dma = (struct device *)args;
break;
case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
uart_device->rx_dma = (struct device *)args;
break;
case DEVICE_CTRL_TX_DMA_SUSPEND: {
uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN);
BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
dev->oflag &= ~DEVICE_OFLAG_DMA_TX;
break;
}
case DEVICE_CTRL_RX_DMA_SUSPEND: {
uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN);
BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
dev->oflag &= ~DEVICE_OFLAG_DMA_RX;
break;
}
case DEVICE_CTRL_TX_DMA_RESUME: {
uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN);
BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
dev->oflag |= DEVICE_OFLAG_DMA_TX;
break;
}
case DEVICE_CTRL_RX_DMA_RESUME: {
uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN);
BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
dev->oflag |= DEVICE_OFLAG_DMA_RX;
break;
}
case DEVICE_CTRL_UART_GET_TX_FIFO /* constant-expression */:
return UART_GetTxFifoCount(uart_device->id);
case DEVICE_CTRL_UART_GET_RX_FIFO /* constant-expression */:
return UART_GetRxFifoCount(uart_device->id);
case DEVICE_CTRL_UART_CLEAR_TX_FIFO /* constant-expression */:
return UART_TxFifoClear(uart_device->id);
case DEVICE_CTRL_UART_CLEAR_RX_FIFO /* constant-expression */:
return UART_RxFifoClear(uart_device->id);
default:
break;
}
return 0;
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
int ret = 0;
uart_device_t *uart_device = (uart_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_TX) {
struct device *dma_ch = (struct device *)uart_device->tx_dma;
if (!dma_ch)
return -1;
if (uart_device->id == 0) {
ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size);
dma_channel_start(dma_ch);
} else if (uart_device->id == 1) {
ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size);
dma_channel_start(dma_ch);
}
return ret;
} else if (dev->oflag & DEVICE_OFLAG_INT_TX) {
return -2;
} else
return UART_SendData(uart_device->id, (uint8_t *)buffer, size);
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
int ret = -1;
uart_device_t *uart_device = (uart_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_RX) {
struct device *dma_ch = (struct device *)uart_device->rx_dma;
if (!dma_ch)
return -1;
if (uart_device->id == 0) {
ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART0_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
} else if (uart_device->id == 1) {
ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART1_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
}
return ret;
} else if (dev->oflag & DEVICE_OFLAG_INT_RX) {
return -2;
} else {
return UART_ReceiveData(uart_device->id, (uint8_t *)buffer, size);
}
}
/**
* @brief
*
* @param index
* @param name
* @param flag
* @return int
*/
int uart_register(enum uart_index_type index, const char *name)
{
struct device *dev;
if (UART_MAX_INDEX == 0)
return -DEVICE_EINVAL;
dev = &(uartx_device[index].parent);
dev->open = uart_open;
dev->close = uart_close;
dev->control = uart_control;
dev->write = uart_write;
dev->read = uart_read;
dev->type = DEVICE_CLASS_UART;
dev->handle = NULL;
return device_register(dev, name);
}
/**
* @brief
*
* @param handle
*/
void uart_isr(uart_device_t *handle)
{
uint32_t tmpVal = 0;
uint32_t maskVal = 0;
uint32_t UARTx = (UART0_BASE + handle->id * 0x100);
tmpVal = BL_RD_REG(UARTx, UART_INT_STS);
maskVal = BL_RD_REG(UARTx, UART_INT_MASK);
if (!handle->parent.callback)
return;
/* Length of uart tx data transfer arrived interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) {
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1);
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_END);
}
/* Length of uart rx data transfer arrived interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) {
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2);
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_END);
}
/* Tx fifo ready interrupt,auto-cleared when data is pushed */
if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK)) {
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FIFO);
}
/* Rx fifo ready interrupt,auto-cleared when data is popped */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) {
uint8_t buffer[UART_FIFO_MAX_LEN];
uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
if (len) {
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO);
}
}
/* Rx time-out interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);
uint8_t buffer[UART_FIFO_MAX_LEN];
uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
if (len) {
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO);
}
}
/* Rx parity check error interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) {
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20);
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_PCE);
}
/* Tx fifo overflow/underflow error interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) {
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FER);
}
/* Rx fifo overflow/underflow error interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) {
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_FER);
}
}
#ifdef BSP_USING_UART0
/**
* @brief
*
*/
void UART0_IRQ(void)
{
uart_isr(&uartx_device[UART0_INDEX]);
}
#endif
#ifdef BSP_USING_UART1
/**
* @brief
*
*/
void UART1_IRQ(void)
{
uart_isr(&uartx_device[UART1_INDEX]);
}
#endif

1173
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c
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File diff suppressed because it is too large Load Diff

179
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_wdt.c
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@@ -1,179 +0,0 @@
/**
* @file hal_wdt.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_wdt.h"
#include "bl702_timer.h"
#ifdef BSP_USING_WDT
void WDT_IRQ(void);
#endif
static wdt_device_t wdtx_device[WDT_MAX_INDEX] = {
#ifdef BSP_USING_WDT
WDT_CONFIG,
#endif
};
int wdt_open(struct device *dev, uint16_t oflag)
{
// uint32_t tmpval;
/* watchdog timer disable*/
// tmpval = BL_RD_REG(TIMER_BASE, TIMER_WMER);
// BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpval, TIMER_WE));
// // MSG("wdt timeout %d \r\n", wdt_device->wdt_timeout);
// /* Set watchdog timer match register value */
// BL_WR_REG(TIMER_BASE, TIMER_WMR, (uint16_t)wdt_device->wdt_timeout);
if (oflag & DEVICE_OFLAG_INT_TX) {
#ifdef BSP_USING_WDT
wdt_device_t *wdt_device = (wdt_device_t *)dev;
// WDT_IntMask(WDT_INT, UNMASK);
if (wdt_device->id == 0) {
Interrupt_Handler_Register(TIMER_WDT_IRQn, WDT_IRQ);
}
#endif
} else {
WDT_IntMask(WDT_INT, MASK);
}
// /* enable watchdog timer */
WDT_Enable();
return 0;
}
int wdt_close(struct device *dev)
{
// wdt_device_t *wdt_device = (wdt_device_t *)(dev);
WDT_Disable();
return 0;
}
int wdt_control(struct device *dev, int cmd, void *args)
{
// wdt_device_t *wdt_device = (wdt_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT: {
WDT_IntMask(WDT_INT, UNMASK);
CPU_Interrupt_Pending_Clear(TIMER_WDT_IRQn);
CPU_Interrupt_Enable(TIMER_WDT_IRQn);
break;
}
case DEVICE_CTRL_CLR_INT: {
WDT_IntMask(WDT_INT, MASK);
CPU_Interrupt_Disable(TIMER_WDT_IRQn);
break;
}
case DEVICE_CTRL_CONFIG: {
break;
}
case DEVICE_CTRL_RESUME: {
WDT_Enable();
break;
}
case DEVICE_CTRL_SUSPEND: {
WDT_Disable();
break;
}
case DEVICE_CTRL_GET_WDT_COUNTER: {
return WDT_GetCounterValue();
break;
}
case DEVICE_CTRL_RST_WDT_COUNTER: {
WDT_ResetCounterValue();
break;
}
case DEVICE_CTRL_GET_RST_STATUS: {
return WDT_GetResetStatus();
break;
}
case DEVICE_CTRL_CLR_RST_STATUS: {
WDT_ClearResetStatus();
break;
}
default:
break;
}
return 0;
}
int wdt_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
// wdt_device_t *wdt_device = (wdt_device_t *)dev;
uint16_t wdt_timeout = (uint16_t)(uint32_t)buffer;
WDT_Disable();
WDT_SetCompValue(wdt_timeout);
WDT_Enable();
return 0;
}
int wdt_register(enum wdt_index_type index, const char *name)
{
struct device *dev;
if (WDT_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
dev = &(wdtx_device[index].parent);
dev->open = wdt_open;
dev->close = wdt_close;
dev->control = wdt_control;
dev->write = wdt_write;
// dev->read = NULL;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_TIMER;
dev->handle = NULL;
return device_register(dev, name);
}
void wdt_isr(wdt_device_t *handle)
{
uint32_t tmpval;
if (!handle->parent.callback) {
return;
}
tmpval = BL_RD_REG(TIMER_BASE, TIMER_WICR);
BL_WR_REG(TIMER_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpval, TIMER_WICLR));
handle->parent.callback(&handle->parent, NULL, 0, WDT_EVENT);
}
#ifdef BSP_USING_WDT
/**
* @brief
*
*/
void WDT_IRQ(void)
{
wdt_isr(&wdtx_device[WDT_INDEX]);
}
#endif

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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/aon_reg.h
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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/bl702.h
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#ifndef __BL702_H__
#define __BL702_H__
/* This file had been modified, add USB_IRQn=43 for temp test, the irq value 43 should be checked after all. */
/** @addtogroup Configuration_section_for_RISCV
* @{
*/
/**
* @brief Configuration of the Processor and Core Peripherals
*/
/* fix 57.6M */
#define SystemCoreClockSet(val) \
if (val == 57 * 6000 * 1000) { \
BL_WR_WORD(0x4000F108, 57.6 * 1000 * 1000); \
} else { \
BL_WR_WORD(0x4000F108, val); \
}
#define SystemCoreClockGet(val) BL_RD_WORD(0x4000F108)
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
#ifdef ARCH_ARM
#define IRQ_NUM_BASE 0
#endif
#ifdef ARCH_RISCV
#define IRQ_NUM_BASE 16
#endif
/**
* @brief BL702 Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum {
#ifdef ARCH_ARM
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
#endif
#ifdef ARCH_RISCV
MSOFT_IRQn = 3, /*!< 3 RISCV machine software Interrupt */
MTIME_IRQn = 7, /*!< 7 RISCV machine time Interrupt */
MEXT_IRQn = 11, /*!< 11 RISCV external Interrupt */
CLIC_SOFT_PEND_IRQn = 12, /*!< 12 RISCV CLIC software pending Interrupt */
#endif
/****** BL702 specific Interrupt Numbers **********************************************************************/
BMX_ERR_IRQn = IRQ_NUM_BASE + 0, /*!< BMX Error Interrupt */
BMX_TO_IRQn = IRQ_NUM_BASE + 1, /*!< BMX Timeout Interrupt */
L1C_BMX_ERR_IRQn = IRQ_NUM_BASE + 2, /*!< L1C BMX Error Interrupt */
L1C_BMX_TO_IRQn = IRQ_NUM_BASE + 3, /*!< L1C BMX Timeout Interrupt */
SEC_BMX_ERR_IRQn = IRQ_NUM_BASE + 4, /*!< SEC BMX Error Interrupt */
RF_TOP_INT0_IRQn = IRQ_NUM_BASE + 5, /*!< RF_TOP_INT0 Interrupt */
RF_TOP_INT1_IRQn = IRQ_NUM_BASE + 6, /*!< RF_TOP_INT1 Interrupt */
RESERVED0 = IRQ_NUM_BASE + 7, /*!< RESERVED Interrupt */
DMA_BMX_ERR_IRQn = IRQ_NUM_BASE + 8, /*!< DMA BMX Error Interrupt */
SEC_GMAC_IRQn = IRQ_NUM_BASE + 9, /*!< SEC_ENG_GMAC_INT Interrupt */
SEC_CDET_IRQn = IRQ_NUM_BASE + 10, /*!< SEC_ENG_CDET_INT Interrupt */
SEC_PKA_IRQn = IRQ_NUM_BASE + 11, /*!< SEC_ENG_PKA_INT Interrupt */
SEC_TRNG_IRQn = IRQ_NUM_BASE + 12, /*!< SEC_ENG_TRNG_INT Interrupt */
SEC_AES_IRQn = IRQ_NUM_BASE + 13, /*!< SEC_ENG_AES_INT Interrupt */
SEC_SHA_IRQn = IRQ_NUM_BASE + 14, /*!< SEC_ENG_SHA_INT Interrupt */
DMA_ALL_IRQn = IRQ_NUM_BASE + 15, /*!< DMA ALL Interrupt */
MJPEG_IRQn = IRQ_NUM_BASE + 16, /*!< MJPEG Interrupt */
CAM_IRQn = IRQ_NUM_BASE + 17, /*!< CAM Interrupt */
I2S_IRQn = IRQ_NUM_BASE + 18, /*!< I2S Interrupt */
IRTX_IRQn = IRQ_NUM_BASE + 19, /*!< IR TX Interrupt */
IRRX_IRQn = IRQ_NUM_BASE + 20, /*!< IR RX Interrupt */
USB_IRQn = IRQ_NUM_BASE + 21, /*!< USB Interrupt */
EMAC_IRQn = IRQ_NUM_BASE + 22, /*!< EMAC Interrupt */
SF_CTRL_IRQn = IRQ_NUM_BASE + 23, /*!< SF_CTRL Interrupt */
RESERVED1 = IRQ_NUM_BASE + 24, /*!< RESERVED Interrupt */
GPADC_DMA_IRQn = IRQ_NUM_BASE + 25, /*!< GPADC_DMA Interrupt */
EFUSE_IRQn = IRQ_NUM_BASE + 26, /*!< Efuse Interrupt */
SPI_IRQn = IRQ_NUM_BASE + 27, /*!< SPI Interrupt */
RESERVED2 = IRQ_NUM_BASE + 28, /*!< RESERVED Interrupt */
UART0_IRQn = IRQ_NUM_BASE + 29, /*!< UART Interrupt */
UART1_IRQn = IRQ_NUM_BASE + 30, /*!< UART1 Interrupt */
RESERVED3 = IRQ_NUM_BASE + 31, /*!< RESERVED Interrupt */
I2C_IRQn = IRQ_NUM_BASE + 32, /*!< I2C Interrupt */
RESERVED4 = IRQ_NUM_BASE + 33, /*!< RESERVED Interrupt */
PWM_IRQn = IRQ_NUM_BASE + 34, /*!< PWM Interrupt */
RESERVED5 = IRQ_NUM_BASE + 35, /*!< RESERVED Interrupt */
TIMER_CH0_IRQn = IRQ_NUM_BASE + 36, /*!< Timer Channel 0 Interrupt */
TIMER_CH1_IRQn = IRQ_NUM_BASE + 37, /*!< Timer Channel 1 Interrupt */
TIMER_WDT_IRQn = IRQ_NUM_BASE + 38, /*!< Timer Watch Dog Interrupt */
KYS_IRQn = IRQ_NUM_BASE + 39, /*!< KYS Interrupt */
QDEC0_IRQn = IRQ_NUM_BASE + 40, /*!< QDEC0 Interrupt */
QDEC1_IRQn = IRQ_NUM_BASE + 41, /*!< QDEC1 Interrupt */
QDEC2_IRQn = IRQ_NUM_BASE + 42, /*!< QDEC2 Interrupt */
RESERVED6 = IRQ_NUM_BASE + 43, /*!< RESERVED Interrupt */
GPIO_INT0_IRQn = IRQ_NUM_BASE + 44, /*!< GPIO_INT0 Interrupt */
TOUCH_IRQn = IRQ_NUM_BASE + 45, /*!< TOUCH Interrupt */
RESERVED7 = IRQ_NUM_BASE + 46, /*!< RESERVED Interrupt */
M154_REQ_ENH_ACK_IRQn = IRQ_NUM_BASE + 47, /*!< M154_REQ Interrupt */
M154_IRQn = IRQ_NUM_BASE + 48, /*!< M154 Interrupt */
M154_AES_IRQn = IRQ_NUM_BASE + 49, /*!< M154_AES Interrupt */
PDS_WAKEUP_IRQn = IRQ_NUM_BASE + 50, /*!< PDS Wakeup Interrupt */
HBN_OUT0_IRQn = IRQ_NUM_BASE + 51, /*!< Hibernate out 0 Interrupt */
HBN_OUT1_IRQn = IRQ_NUM_BASE + 52, /*!< Hibernate out 1 Interrupt */
BOR_IRQn = IRQ_NUM_BASE + 53, /*!< BOR Interrupt */
WIFI_IRQn = IRQ_NUM_BASE + 54, /*!< WIFI To CPU Interrupt */
BZ_PHY_IRQn = IRQ_NUM_BASE + 55, /*!< BZ_PHY Interrupt */
BLE_IRQn = IRQ_NUM_BASE + 56, /*!< BLE Interrupt */
MAC_TXRX_TIMER_IRQn = IRQ_NUM_BASE + 57, /*!< mac_int_tx_rx_timer Interrupt */
MAC_TXRX_MISC_IRQn = IRQ_NUM_BASE + 58, /*!< mac_int_tx_rx_misc Interrupt */
MAC_RX_TRG_IRQn = IRQ_NUM_BASE + 59, /*!< mac_int_rx_trigger Interrupt */
MAC_TX_TRG_IRQn = IRQ_NUM_BASE + 60, /*!< mac_int_tx_trigger Interrupt */
MAC_GEN_IRQn = IRQ_NUM_BASE + 61, /*!< mac_int_gen Interrupt */
MAC_PORT_TRG_IRQn = IRQ_NUM_BASE + 62, /*!< mac_int_port_trigger Interrupt */
WIFI_IPC_PUBLIC_IRQn = IRQ_NUM_BASE + 63, /*!< wifi IPC public Interrupt */
IRQn_LAST,
} IRQn_Type;
/**
* @brief BL702 Memory Map Definitions
*/
#define BL702_FLASH_XIP_BASE 0x23000000
#define BL702_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024)
#define BL702_FLASH_XIP_REMAP0_BASE 0x33000000
#define BL702_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024)
#define BL702_FLASH_XIP_REMAP1_BASE 0x43000000
#define BL702_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024)
#define BL702_FLASH_XIP_REMAP2_BASE 0x53000000
#define BL702_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024)
#define BL702_PSRAM_XIP_BASE 0x24000000
#define BL702_PSRAM_XIP_END (0x24000000 + 16 * 1024 * 1024)
#define BL702_PSRAM_XIP_REMAP0_BASE 0x34000000
#define BL702_PSRAM_XIP_REMAP0_END (0x34000000 + 16 * 1024 * 1024)
#define BL702_PSRAM_XIP_REMAP1_BASE 0x44000000
#define BL702_PSRAM_XIP_REMAP1_END (0x44000000 + 16 * 1024 * 1024)
#define BL702_PSRAM_XIP_REMAP2_BASE 0x54000000
#define BL702_PSRAM_XIP_REMAP2_END (0x54000000 + 16 * 1024 * 1024)
#define BL702_WRAM_BASE 0x42020000
#define BL702_WRAM_END (0x42020000 + 56 * 1024)
#define BL702_WRAM_REMAP0_BASE 0x22020000
#define BL702_WRAM_REMAP0_END (0x22020000 + 56 * 1024)
#define BL702_WRAM_REMAP1_BASE 0x32020000
#define BL702_WRAM_REMAP1_END (0x32020000 + 56 * 1024)
#define BL702_WRAM_REMAP2_BASE 0x52020000
#define BL702_WRAM_REMAP2_END (0x52020000 + 56 * 1024)
#define BL702_TCM_BASE 0x22010000
#define BL702_TCM_END (0x22010000 + (16 + 48) * 1024)
#define BL702_TCM_REMAP0_BASE 0x32010000
#define BL702_TCM_REMAP0_END (0x32010000 + (16 + 48) * 1024)
#define BL702_TCM_REMAP1_BASE 0x42010000
#define BL702_TCM_REMAP1_END (0x42010000 + (16 + 48) * 1024)
#define BL702_TCM_REMAP2_BASE 0x52010000
#define BL702_TCM_REMAP2_END (0x52010000 + (16 + 48) * 1024)
/*@} end of group Memory_Map_Section */
/* BL702 peripherals base address */
#define GLB_BASE ((uint32_t)0x40000000)
#define RF_BASE ((uint32_t)0x40001000)
#define BZ_PHY_BASE ((uint32_t)0x40001000)
#define BZ_PHY_AGC_BASE ((uint32_t)0x40001000)
#define GPIP_BASE ((uint32_t)0x40002000) /*!< AUX module base address */
#define SEC_DBG_BASE ((uint32_t)0x40003000) /*!< Security Debug module base address */
#define SEC_ENG_BASE ((uint32_t)0x40004000) /*!< Security Engine module base address */
#define TZC_SEC_BASE ((uint32_t)0x40005000) /*!< Trustzone control security base address */
#define TZC_NSEC_BASE ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */
#define EF_DATA_BASE ((uint32_t)0x40007000)
#define EF_CTRL_BASE ((uint32_t)0x40007000)
#define CCI_BASE ((uint32_t)0x40008000)
#define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */
#define UART0_BASE ((uint32_t)0x4000A000)
#define UART1_BASE ((uint32_t)0x4000A100)
#define SPI_BASE ((uint32_t)0x4000A200)
#define I2C_BASE ((uint32_t)0x4000A300)
#define PWM_BASE ((uint32_t)0x4000A400)
#define TIMER_BASE ((uint32_t)0x4000A500)
#define IR_BASE ((uint32_t)0x4000A600)
#define CKS_BASE ((uint32_t)0x4000A700)
#define QDEC0_BASE ((uint32_t)0x4000A800)
#define QDEC1_BASE ((uint32_t)0x4000A840)
#define QDEC2_BASE ((uint32_t)0x4000A880)
#define KYS_BASE ((uint32_t)0x4000A900)
#define I2S_BASE ((uint32_t)0x4000AA00)
#define CAM_BASE ((uint32_t)0x4000AD00)
#define MJPEG_BASE ((uint32_t)0x4000AE00)
#define SF_CTRL_BASE ((uint32_t)0x4000B000)
#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
#define DMA_BASE ((uint32_t)0x4000C000)
#define EMAC_BASE ((uint32_t)0x4000D000)
#define USB_BASE ((uint32_t)0x4000D800)
#define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */
#define HBN_BASE ((uint32_t)0x4000F000) /*!< Hibernate module base address */
#define AON_BASE ((uint32_t)0x4000F000) /*!< Always on module base address */
#define MAC154_BASE ((uint32_t)0x4C000000) /*!< MAC154 module base address */
#define HBN_RAM_BASE ((uint32_t)0x40010000)
typedef enum {
BL_AHB_SLAVE1_GLB = 0x00,
BL_AHB_SLAVE1_MIX = 0x01,
BL_AHB_SLAVE1_GPIP = 0x02,
BL_AHB_SLAVE1_SEC_DBG = 0x03,
BL_AHB_SLAVE1_SEC = 0x04,
BL_AHB_SLAVE1_TZ1 = 0x05,
BL_AHB_SLAVE1_TZ2 = 0x06,
BL_AHB_SLAVE1_EFUSE = 0x07,
BL_AHB_SLAVE1_CCI = 0x08,
BL_AHB_SLAVE1_L1C = 0x09,
BL_AHB_SLAVE1_S1A_ALL = 0x0A,
BL_AHB_SLAVE1_SFC = 0x0B,
BL_AHB_SLAVE1_DMA = 0x0C,
BL_AHB_SLAVE1_EMAC = 0x0D,
BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0E,
BL_AHB_SLAVE1_RSVD0F = 0x0F,
BL_AHB_SLAVE1_UART0 = 0x10,
BL_AHB_SLAVE1_UART1 = 0x11,
BL_AHB_SLAVE1_SPI = 0x12,
BL_AHB_SLAVE1_I2C = 0x13,
BL_AHB_SLAVE1_PWM = 0x14,
BL_AHB_SLAVE1_TMR = 0x15,
BL_AHB_SLAVE1_IRR = 0x16,
BL_AHB_SLAVE1_CKS = 0x17,
BL_AHB_SLAVE1_QDEC = 0x18,
BL_AHB_SLAVE1_KYS = 0x19,
BL_AHB_SLAVE1_I2S = 0x1A,
BL_AHB_SLAVE1_RSVD1B = 0x1B,
BL_AHB_SLAVE1_USB = 0x1C,
BL_AHB_SLAVE1_CAM = 0x1D,
BL_AHB_SLAVE1_MJPEG = 0x1E,
BL_AHB_SLAVE1_MAX = 0x1F,
} BL_AHB_Slave1_Type;
typedef enum {
BL_AHB_SEC_ENG_AES0 = 0,
BL_AHB_SEC_ENG_AES1,
BL_AHB_SEC_ENG_SHA0,
BL_AHB_SEC_ENG_SHA1,
} BL_AHB_Sec_Eng_Type;
typedef enum {
BL_AHB_DMA0_CH0 = 0,
BL_AHB_DMA0_CH1,
BL_AHB_DMA0_CH2,
BL_AHB_DMA0_CH3,
BL_AHB_DMA0_CH4,
BL_AHB_DMA0_CH5,
BL_AHB_DMA0_CH6,
BL_AHB_DMA0_CH7,
} BL_AHB_DMA0_CHNL_Type;
typedef enum {
BL_AHB_SLAVE2_WIFI_CFG = 0,
BL_AHB_SLAVE2_MAX,
} BL_AHB_Slave2_Type;
typedef enum {
BL_AHB_SLAVE3_BLE = 0,
BL_AHB_SLAVE3_MAX,
} BL_AHB_Slave3_Type;
typedef enum {
BL_CORE_MASTER_IBUS_CPU = 0,
BL_CORE_MASTER_DBUS_CPU,
BL_CORE_MASTER_BUS_S2F,
BL_CORE_MASTER_MAX,
} BL_Core_Master_Type;
typedef enum {
BL_CORE_SLAVE0_DTCM_CPU = 0,
BL_CORE_SLAVE0_MAX,
} BL_Core_Slave0_Type;
typedef enum {
BL_CORE_SLAVE1_XIP_CPU = 0,
BL_CORE_SLAVE1_ITCM_CPU,
BL_CORE_SLAVE1_ROM,
BL_CORE_SLAVE1_MAX,
} BL_Core_Slave1_Type;
typedef enum {
BL_CORE_SLAVE2_F2S = 0,
BL_CORE_SLAVE2_MAX,
} BL_Core_Slave2_Type;
/**
* @}
*/
#include <stdint.h>
#include <system_bl702.h>
/**
* @}
*/
#endif

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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/bl70x_reg.svc
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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/cam_reg.h
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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/cci_reg.h
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/**
******************************************************************************
* @file cci_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __CCI_REG_H__
#define __CCI_REG_H__
#include "bl702.h"
/* 0x0 : cci_cfg */
#define CCI_CFG_OFFSET (0x0)
#define CCI_EN CCI_EN
#define CCI_EN_POS (0U)
#define CCI_EN_LEN (1U)
#define CCI_EN_MSK (((1U << CCI_EN_LEN) - 1) << CCI_EN_POS)
#define CCI_EN_UMSK (~(((1U << CCI_EN_LEN) - 1) << CCI_EN_POS))
#define CCI_SLV_SEL_CCI2 CCI_SLV_SEL_CCI2
#define CCI_SLV_SEL_CCI2_POS (1U)
#define CCI_SLV_SEL_CCI2_LEN (1U)
#define CCI_SLV_SEL_CCI2_MSK (((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS)
#define CCI_SLV_SEL_CCI2_UMSK (~(((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS))
#define CCI_MAS_SEL_CCI2 CCI_MAS_SEL_CCI2
#define CCI_MAS_SEL_CCI2_POS (2U)
#define CCI_MAS_SEL_CCI2_LEN (1U)
#define CCI_MAS_SEL_CCI2_MSK (((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS)
#define CCI_MAS_SEL_CCI2_UMSK (~(((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS))
#define CCI_MAS_HW_MODE CCI_MAS_HW_MODE
#define CCI_MAS_HW_MODE_POS (3U)
#define CCI_MAS_HW_MODE_LEN (1U)
#define CCI_MAS_HW_MODE_MSK (((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS)
#define CCI_MAS_HW_MODE_UMSK (~(((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS))
#define CCI_REG_M_CCI_SCLK_EN CCI_REG_M_CCI_SCLK_EN
#define CCI_REG_M_CCI_SCLK_EN_POS (4U)
#define CCI_REG_M_CCI_SCLK_EN_LEN (1U)
#define CCI_REG_M_CCI_SCLK_EN_MSK (((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS)
#define CCI_REG_M_CCI_SCLK_EN_UMSK (~(((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS))
#define CCI_REG_DIV_M_CCI_SCLK CCI_REG_DIV_M_CCI_SCLK
#define CCI_REG_DIV_M_CCI_SCLK_POS (5U)
#define CCI_REG_DIV_M_CCI_SCLK_LEN (2U)
#define CCI_REG_DIV_M_CCI_SCLK_MSK (((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS)
#define CCI_REG_DIV_M_CCI_SCLK_UMSK (~(((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS))
#define CCI_CFG_CCI1_PRE_READ CCI_CFG_CCI1_PRE_READ
#define CCI_CFG_CCI1_PRE_READ_POS (7U)
#define CCI_CFG_CCI1_PRE_READ_LEN (1U)
#define CCI_CFG_CCI1_PRE_READ_MSK (((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS)
#define CCI_CFG_CCI1_PRE_READ_UMSK (~(((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS))
#define CCI_REG_SCCI_CLK_INV CCI_REG_SCCI_CLK_INV
#define CCI_REG_SCCI_CLK_INV_POS (8U)
#define CCI_REG_SCCI_CLK_INV_LEN (1U)
#define CCI_REG_SCCI_CLK_INV_MSK (((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS)
#define CCI_REG_SCCI_CLK_INV_UMSK (~(((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS))
#define CCI_REG_MCCI_CLK_INV CCI_REG_MCCI_CLK_INV
#define CCI_REG_MCCI_CLK_INV_POS (9U)
#define CCI_REG_MCCI_CLK_INV_LEN (1U)
#define CCI_REG_MCCI_CLK_INV_MSK (((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS)
#define CCI_REG_MCCI_CLK_INV_UMSK (~(((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS))
/* 0x4 : cci_addr */
#define CCI_ADDR_OFFSET (0x4)
#define CCI_APB_CCI_ADDR CCI_APB_CCI_ADDR
#define CCI_APB_CCI_ADDR_POS (0U)
#define CCI_APB_CCI_ADDR_LEN (32U)
#define CCI_APB_CCI_ADDR_MSK (((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS)
#define CCI_APB_CCI_ADDR_UMSK (~(((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS))
/* 0x8 : cci_wdata */
#define CCI_WDATA_OFFSET (0x8)
#define CCI_APB_CCI_WDATA CCI_APB_CCI_WDATA
#define CCI_APB_CCI_WDATA_POS (0U)
#define CCI_APB_CCI_WDATA_LEN (32U)
#define CCI_APB_CCI_WDATA_MSK (((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS)
#define CCI_APB_CCI_WDATA_UMSK (~(((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS))
/* 0xC : cci_rdata */
#define CCI_RDATA_OFFSET (0xC)
#define CCI_APB_CCI_RDATA CCI_APB_CCI_RDATA
#define CCI_APB_CCI_RDATA_POS (0U)
#define CCI_APB_CCI_RDATA_LEN (32U)
#define CCI_APB_CCI_RDATA_MSK (((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS)
#define CCI_APB_CCI_RDATA_UMSK (~(((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS))
/* 0x10 : cci_ctl */
#define CCI_CTL_OFFSET (0x10)
#define CCI_WRITE_FLAG CCI_WRITE_FLAG
#define CCI_WRITE_FLAG_POS (0U)
#define CCI_WRITE_FLAG_LEN (1U)
#define CCI_WRITE_FLAG_MSK (((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS)
#define CCI_WRITE_FLAG_UMSK (~(((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS))
#define CCI_READ_FLAG CCI_READ_FLAG
#define CCI_READ_FLAG_POS (1U)
#define CCI_READ_FLAG_LEN (1U)
#define CCI_READ_FLAG_MSK (((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS)
#define CCI_READ_FLAG_UMSK (~(((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS))
#define CCI_AHB_STATE CCI_AHB_STATE
#define CCI_AHB_STATE_POS (2U)
#define CCI_AHB_STATE_LEN (2U)
#define CCI_AHB_STATE_MSK (((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS)
#define CCI_AHB_STATE_UMSK (~(((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS))
struct cci_reg {
/* 0x0 : cci_cfg */
union {
struct
{
uint32_t cci_en : 1; /* [ 0], r/w, 0x1 */
uint32_t cci_slv_sel_cci2 : 1; /* [ 1], r/w, 0x0 */
uint32_t cci_mas_sel_cci2 : 1; /* [ 2], r/w, 0x0 */
uint32_t cci_mas_hw_mode : 1; /* [ 3], r/w, 0x0 */
uint32_t reg_m_cci_sclk_en : 1; /* [ 4], r/w, 0x0 */
uint32_t reg_div_m_cci_sclk : 2; /* [ 6: 5], r/w, 0x1 */
uint32_t cfg_cci1_pre_read : 1; /* [ 7], r/w, 0x0 */
uint32_t reg_scci_clk_inv : 1; /* [ 8], r/w, 0x0 */
uint32_t reg_mcci_clk_inv : 1; /* [ 9], r/w, 0x1 */
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
} BF;
uint32_t WORD;
} cci_cfg;
/* 0x4 : cci_addr */
union {
struct
{
uint32_t apb_cci_addr : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} cci_addr;
/* 0x8 : cci_wdata */
union {
struct
{
uint32_t apb_cci_wdata : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} cci_wdata;
/* 0xC : cci_rdata */
union {
struct
{
uint32_t apb_cci_rdata : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} cci_rdata;
/* 0x10 : cci_ctl */
union {
struct
{
uint32_t cci_write_flag : 1; /* [ 0], r, 0x0 */
uint32_t cci_read_flag : 1; /* [ 1], r, 0x0 */
uint32_t ahb_state : 2; /* [ 3: 2], r, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} cci_ctl;
};
typedef volatile struct cci_reg cci_reg_t;
#endif /* __CCI_REG_H__ */

105
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/cks_reg.h
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@@ -1,105 +0,0 @@
/**
******************************************************************************
* @file cks_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __CKS_REG_H__
#define __CKS_REG_H__
#include "bl702.h"
/* 0x0 : cks_config */
#define CKS_CONFIG_OFFSET (0x0)
#define CKS_CR_CKS_CLR CKS_CR_CKS_CLR
#define CKS_CR_CKS_CLR_POS (0U)
#define CKS_CR_CKS_CLR_LEN (1U)
#define CKS_CR_CKS_CLR_MSK (((1U << CKS_CR_CKS_CLR_LEN) - 1) << CKS_CR_CKS_CLR_POS)
#define CKS_CR_CKS_CLR_UMSK (~(((1U << CKS_CR_CKS_CLR_LEN) - 1) << CKS_CR_CKS_CLR_POS))
#define CKS_CR_CKS_BYTE_SWAP CKS_CR_CKS_BYTE_SWAP
#define CKS_CR_CKS_BYTE_SWAP_POS (1U)
#define CKS_CR_CKS_BYTE_SWAP_LEN (1U)
#define CKS_CR_CKS_BYTE_SWAP_MSK (((1U << CKS_CR_CKS_BYTE_SWAP_LEN) - 1) << CKS_CR_CKS_BYTE_SWAP_POS)
#define CKS_CR_CKS_BYTE_SWAP_UMSK (~(((1U << CKS_CR_CKS_BYTE_SWAP_LEN) - 1) << CKS_CR_CKS_BYTE_SWAP_POS))
/* 0x4 : data_in */
#define CKS_DATA_IN_OFFSET (0x4)
#define CKS_DATA_IN CKS_DATA_IN
#define CKS_DATA_IN_POS (0U)
#define CKS_DATA_IN_LEN (8U)
#define CKS_DATA_IN_MSK (((1U << CKS_DATA_IN_LEN) - 1) << CKS_DATA_IN_POS)
#define CKS_DATA_IN_UMSK (~(((1U << CKS_DATA_IN_LEN) - 1) << CKS_DATA_IN_POS))
/* 0x8 : cks_out */
#define CKS_OUT_OFFSET (0x8)
#define CKS_OUT CKS_OUT
#define CKS_OUT_POS (0U)
#define CKS_OUT_LEN (16U)
#define CKS_OUT_MSK (((1U << CKS_OUT_LEN) - 1) << CKS_OUT_POS)
#define CKS_OUT_UMSK (~(((1U << CKS_OUT_LEN) - 1) << CKS_OUT_POS))
struct cks_reg {
/* 0x0 : cks_config */
union {
struct
{
uint32_t cr_cks_clr : 1; /* [ 0], w1c, 0x0 */
uint32_t cr_cks_byte_swap : 1; /* [ 1], r/w, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
} BF;
uint32_t WORD;
} cks_config;
/* 0x4 : data_in */
union {
struct
{
uint32_t data_in : 8; /* [ 7: 0], w, x */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} data_in;
/* 0x8 : cks_out */
union {
struct
{
uint32_t cks_out : 16; /* [15: 0], r, 0xffff */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} cks_out;
};
typedef volatile struct cks_reg cks_reg_t;
#endif /* __CKS_REG_H__ */

2232
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/dma_reg.h
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File diff suppressed because it is too large Load Diff

812
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/ef_ctrl_reg.h
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@@ -1,812 +0,0 @@
/**
******************************************************************************
* @file ef_ctrl_reg.h
* @version V1.2
* @date 2020-04-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_CTRL_REG_H__
#define __EF_CTRL_REG_H__
#include "bl702.h"
/* 0x800 : ef_if_ctrl_0 */
#define EF_CTRL_EF_IF_CTRL_0_OFFSET (0x800)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS (0U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS))
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE EF_CTRL_EF_IF_0_AUTOLOAD_DONE
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS))
#define EF_CTRL_EF_IF_0_BUSY EF_CTRL_EF_IF_0_BUSY
#define EF_CTRL_EF_IF_0_BUSY_POS (2U)
#define EF_CTRL_EF_IF_0_BUSY_LEN (1U)
#define EF_CTRL_EF_IF_0_BUSY_MSK (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)
#define EF_CTRL_EF_IF_0_BUSY_UMSK (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS))
#define EF_CTRL_EF_IF_0_RW EF_CTRL_EF_IF_0_RW
#define EF_CTRL_EF_IF_0_RW_POS (3U)
#define EF_CTRL_EF_IF_0_RW_LEN (1U)
#define EF_CTRL_EF_IF_0_RW_MSK (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)
#define EF_CTRL_EF_IF_0_RW_UMSK (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS))
#define EF_CTRL_EF_IF_0_TRIG EF_CTRL_EF_IF_0_TRIG
#define EF_CTRL_EF_IF_0_TRIG_POS (4U)
#define EF_CTRL_EF_IF_0_TRIG_LEN (1U)
#define EF_CTRL_EF_IF_0_TRIG_MSK (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)
#define EF_CTRL_EF_IF_0_TRIG_UMSK (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS))
#define EF_CTRL_EF_IF_0_MANUAL_EN EF_CTRL_EF_IF_0_MANUAL_EN
#define EF_CTRL_EF_IF_0_MANUAL_EN_POS (5U)
#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN (1U)
#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS))
#define EF_CTRL_EF_IF_0_CYC_MODIFY EF_CTRL_EF_IF_0_CYC_MODIFY
#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS (6U)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN (1U)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS))
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL EF_CTRL_EF_CLK_SAHB_DATA_SEL
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS (7U)
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN (1U)
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MSK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMSK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS))
#define EF_CTRL_EF_IF_PROT_CODE_CTRL EF_CTRL_EF_IF_PROT_CODE_CTRL
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS))
#define EF_CTRL_EF_IF_POR_DIG EF_CTRL_EF_IF_POR_DIG
#define EF_CTRL_EF_IF_POR_DIG_POS (16U)
#define EF_CTRL_EF_IF_POR_DIG_LEN (1U)
#define EF_CTRL_EF_IF_POR_DIG_MSK (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)
#define EF_CTRL_EF_IF_POR_DIG_UMSK (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS))
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE EF_CTRL_EF_CLK_SAHB_DATA_GATE
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS (17U)
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN (1U)
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MSK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMSK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS))
#define EF_CTRL_EF_IF_AUTO_RD_EN EF_CTRL_EF_IF_AUTO_RD_EN
#define EF_CTRL_EF_IF_AUTO_RD_EN_POS (18U)
#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN (1U)
#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS))
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK EF_CTRL_EF_IF_CYC_MODIFY_LOCK
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS (19U)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN (1U)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS))
#define EF_CTRL_EF_IF_0_INT EF_CTRL_EF_IF_0_INT
#define EF_CTRL_EF_IF_0_INT_POS (20U)
#define EF_CTRL_EF_IF_0_INT_LEN (1U)
#define EF_CTRL_EF_IF_0_INT_MSK (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)
#define EF_CTRL_EF_IF_0_INT_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS))
#define EF_CTRL_EF_IF_0_INT_CLR EF_CTRL_EF_IF_0_INT_CLR
#define EF_CTRL_EF_IF_0_INT_CLR_POS (21U)
#define EF_CTRL_EF_IF_0_INT_CLR_LEN (1U)
#define EF_CTRL_EF_IF_0_INT_CLR_MSK (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)
#define EF_CTRL_EF_IF_0_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS))
#define EF_CTRL_EF_IF_0_INT_SET EF_CTRL_EF_IF_0_INT_SET
#define EF_CTRL_EF_IF_0_INT_SET_POS (22U)
#define EF_CTRL_EF_IF_0_INT_SET_LEN (1U)
#define EF_CTRL_EF_IF_0_INT_SET_MSK (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)
#define EF_CTRL_EF_IF_0_INT_SET_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS))
#define EF_CTRL_EF_IF_PROT_CODE_CYC EF_CTRL_EF_IF_PROT_CODE_CYC
#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS (24U)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS))
/* 0x804 : ef_if_cyc_0 */
#define EF_CTRL_EF_IF_CYC_0_OFFSET (0x804)
#define EF_CTRL_EF_IF_CYC_RD_DMY EF_CTRL_EF_IF_CYC_RD_DMY
#define EF_CTRL_EF_IF_CYC_RD_DMY_POS (0U)
#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN (6U)
#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)
#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS))
#define EF_CTRL_EF_IF_CYC_RD_DAT EF_CTRL_EF_IF_CYC_RD_DAT
#define EF_CTRL_EF_IF_CYC_RD_DAT_POS (6U)
#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN (6U)
#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)
#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS))
#define EF_CTRL_EF_IF_CYC_RD_ADR EF_CTRL_EF_IF_CYC_RD_ADR
#define EF_CTRL_EF_IF_CYC_RD_ADR_POS (12U)
#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN (6U)
#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)
#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS))
#define EF_CTRL_EF_IF_CYC_CS EF_CTRL_EF_IF_CYC_CS
#define EF_CTRL_EF_IF_CYC_CS_POS (18U)
#define EF_CTRL_EF_IF_CYC_CS_LEN (6U)
#define EF_CTRL_EF_IF_CYC_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)
#define EF_CTRL_EF_IF_CYC_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS))
#define EF_CTRL_EF_IF_CYC_PD_CS_S EF_CTRL_EF_IF_CYC_PD_CS_S
#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS (24U)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN (8U)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS))
/* 0x808 : ef_if_cyc_1 */
#define EF_CTRL_EF_IF_CYC_1_OFFSET (0x808)
#define EF_CTRL_EF_IF_CYC_PI EF_CTRL_EF_IF_CYC_PI
#define EF_CTRL_EF_IF_CYC_PI_POS (0U)
#define EF_CTRL_EF_IF_CYC_PI_LEN (6U)
#define EF_CTRL_EF_IF_CYC_PI_MSK (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)
#define EF_CTRL_EF_IF_CYC_PI_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS))
#define EF_CTRL_EF_IF_CYC_PP EF_CTRL_EF_IF_CYC_PP
#define EF_CTRL_EF_IF_CYC_PP_POS (6U)
#define EF_CTRL_EF_IF_CYC_PP_LEN (8U)
#define EF_CTRL_EF_IF_CYC_PP_MSK (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)
#define EF_CTRL_EF_IF_CYC_PP_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS))
#define EF_CTRL_EF_IF_CYC_WR_ADR EF_CTRL_EF_IF_CYC_WR_ADR
#define EF_CTRL_EF_IF_CYC_WR_ADR_POS (14U)
#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN (6U)
#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)
#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS))
#define EF_CTRL_EF_IF_CYC_PS_CS EF_CTRL_EF_IF_CYC_PS_CS
#define EF_CTRL_EF_IF_CYC_PS_CS_POS (20U)
#define EF_CTRL_EF_IF_CYC_PS_CS_LEN (6U)
#define EF_CTRL_EF_IF_CYC_PS_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)
#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS))
#define EF_CTRL_EF_IF_CYC_PD_CS_H EF_CTRL_EF_IF_CYC_PD_CS_H
#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS (26U)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN (6U)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS))
/* 0x80C : ef_if_0_manual */
#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C)
#define EF_CTRL_EF_IF_A EF_CTRL_EF_IF_A
#define EF_CTRL_EF_IF_A_POS (0U)
#define EF_CTRL_EF_IF_A_LEN (10U)
#define EF_CTRL_EF_IF_A_MSK (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
#define EF_CTRL_EF_IF_A_UMSK (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
#define EF_CTRL_EF_IF_PD EF_CTRL_EF_IF_PD
#define EF_CTRL_EF_IF_PD_POS (10U)
#define EF_CTRL_EF_IF_PD_LEN (1U)
#define EF_CTRL_EF_IF_PD_MSK (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
#define EF_CTRL_EF_IF_PD_UMSK (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
#define EF_CTRL_EF_IF_PS EF_CTRL_EF_IF_PS
#define EF_CTRL_EF_IF_PS_POS (11U)
#define EF_CTRL_EF_IF_PS_LEN (1U)
#define EF_CTRL_EF_IF_PS_MSK (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
#define EF_CTRL_EF_IF_PS_UMSK (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
#define EF_CTRL_EF_IF_STROBE EF_CTRL_EF_IF_STROBE
#define EF_CTRL_EF_IF_STROBE_POS (12U)
#define EF_CTRL_EF_IF_STROBE_LEN (1U)
#define EF_CTRL_EF_IF_STROBE_MSK (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
#define EF_CTRL_EF_IF_STROBE_UMSK (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
#define EF_CTRL_EF_IF_PGENB EF_CTRL_EF_IF_PGENB
#define EF_CTRL_EF_IF_PGENB_POS (13U)
#define EF_CTRL_EF_IF_PGENB_LEN (1U)
#define EF_CTRL_EF_IF_PGENB_MSK (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
#define EF_CTRL_EF_IF_PGENB_UMSK (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
#define EF_CTRL_EF_IF_LOAD EF_CTRL_EF_IF_LOAD
#define EF_CTRL_EF_IF_LOAD_POS (14U)
#define EF_CTRL_EF_IF_LOAD_LEN (1U)
#define EF_CTRL_EF_IF_LOAD_MSK (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
#define EF_CTRL_EF_IF_LOAD_UMSK (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
#define EF_CTRL_EF_IF_CSB EF_CTRL_EF_IF_CSB
#define EF_CTRL_EF_IF_CSB_POS (15U)
#define EF_CTRL_EF_IF_CSB_LEN (1U)
#define EF_CTRL_EF_IF_CSB_MSK (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
#define EF_CTRL_EF_IF_CSB_UMSK (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
#define EF_CTRL_EF_IF_0_Q EF_CTRL_EF_IF_0_Q
#define EF_CTRL_EF_IF_0_Q_POS (16U)
#define EF_CTRL_EF_IF_0_Q_LEN (8U)
#define EF_CTRL_EF_IF_0_Q_MSK (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)
#define EF_CTRL_EF_IF_0_Q_UMSK (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS))
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL EF_CTRL_EF_IF_PROT_CODE_MANUAL
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS (24U)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN (8U)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
/* 0x810 : ef_if_0_status */
#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810)
#define EF_CTRL_EF_IF_0_STATUS EF_CTRL_EF_IF_0_STATUS
#define EF_CTRL_EF_IF_0_STATUS_POS (0U)
#define EF_CTRL_EF_IF_0_STATUS_LEN (32U)
#define EF_CTRL_EF_IF_0_STATUS_MSK (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)
#define EF_CTRL_EF_IF_0_STATUS_UMSK (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS))
/* 0x814 : ef_if_cfg_0 */
#define EF_CTRL_EF_IF_CFG_0_OFFSET (0x814)
#define EF_CTRL_EF_IF_SF_AES_MODE EF_CTRL_EF_IF_SF_AES_MODE
#define EF_CTRL_EF_IF_SF_AES_MODE_POS (0U)
#define EF_CTRL_EF_IF_SF_AES_MODE_LEN (2U)
#define EF_CTRL_EF_IF_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)
#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS))
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE EF_CTRL_EF_IF_SBOOT_SIGN_MODE
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS (2U)
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN (2U)
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_MSK (((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS)
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS))
#define EF_CTRL_EF_IF_SBOOT_EN EF_CTRL_EF_IF_SBOOT_EN
#define EF_CTRL_EF_IF_SBOOT_EN_POS (4U)
#define EF_CTRL_EF_IF_SBOOT_EN_LEN (2U)
#define EF_CTRL_EF_IF_SBOOT_EN_MSK (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)
#define EF_CTRL_EF_IF_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS))
#define EF_CTRL_EF_IF_CPU1_ENC_EN EF_CTRL_EF_IF_CPU1_ENC_EN
#define EF_CTRL_EF_IF_CPU1_ENC_EN_POS (6U)
#define EF_CTRL_EF_IF_CPU1_ENC_EN_LEN (1U)
#define EF_CTRL_EF_IF_CPU1_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS)
#define EF_CTRL_EF_IF_CPU1_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS))
#define EF_CTRL_EF_IF_CPU0_ENC_EN EF_CTRL_EF_IF_CPU0_ENC_EN
#define EF_CTRL_EF_IF_CPU0_ENC_EN_POS (7U)
#define EF_CTRL_EF_IF_CPU0_ENC_EN_LEN (1U)
#define EF_CTRL_EF_IF_CPU0_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS)
#define EF_CTRL_EF_IF_CPU0_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS))
#define EF_CTRL_EF_IF_BOOT_SEL EF_CTRL_EF_IF_BOOT_SEL
#define EF_CTRL_EF_IF_BOOT_SEL_POS (8U)
#define EF_CTRL_EF_IF_BOOT_SEL_LEN (4U)
#define EF_CTRL_EF_IF_BOOT_SEL_MSK (((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS)
#define EF_CTRL_EF_IF_BOOT_SEL_UMSK (~(((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS))
#define EF_CTRL_EF_IF_SF_KEY_0_SEL EF_CTRL_EF_IF_SF_KEY_0_SEL
#define EF_CTRL_EF_IF_SF_KEY_0_SEL_POS (12U)
#define EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN (2U)
#define EF_CTRL_EF_IF_SF_KEY_0_SEL_MSK (((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS)
#define EF_CTRL_EF_IF_SF_KEY_0_SEL_UMSK (~(((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS))
#define EF_CTRL_EF_IF_SDU_DIS EF_CTRL_EF_IF_SDU_DIS
#define EF_CTRL_EF_IF_SDU_DIS_POS (14U)
#define EF_CTRL_EF_IF_SDU_DIS_LEN (1U)
#define EF_CTRL_EF_IF_SDU_DIS_MSK (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)
#define EF_CTRL_EF_IF_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS))
#define EF_CTRL_EF_IF_BLE_DIS EF_CTRL_EF_IF_BLE_DIS
#define EF_CTRL_EF_IF_BLE_DIS_POS (15U)
#define EF_CTRL_EF_IF_BLE_DIS_LEN (1U)
#define EF_CTRL_EF_IF_BLE_DIS_MSK (((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS)
#define EF_CTRL_EF_IF_BLE_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS))
#define EF_CTRL_EF_IF_WIFI_DIS EF_CTRL_EF_IF_WIFI_DIS
#define EF_CTRL_EF_IF_WIFI_DIS_POS (16U)
#define EF_CTRL_EF_IF_WIFI_DIS_LEN (1U)
#define EF_CTRL_EF_IF_WIFI_DIS_MSK (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)
#define EF_CTRL_EF_IF_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS))
#define EF_CTRL_EF_IF_0_KEY_ENC_EN EF_CTRL_EF_IF_0_KEY_ENC_EN
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS (17U)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN (1U)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS))
#define EF_CTRL_EF_IF_CAM_DIS EF_CTRL_EF_IF_CAM_DIS
#define EF_CTRL_EF_IF_CAM_DIS_POS (18U)
#define EF_CTRL_EF_IF_CAM_DIS_LEN (1U)
#define EF_CTRL_EF_IF_CAM_DIS_MSK (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)
#define EF_CTRL_EF_IF_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS))
#define EF_CTRL_EF_IF_M154_DIS EF_CTRL_EF_IF_M154_DIS
#define EF_CTRL_EF_IF_M154_DIS_POS (19U)
#define EF_CTRL_EF_IF_M154_DIS_LEN (1U)
#define EF_CTRL_EF_IF_M154_DIS_MSK (((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS)
#define EF_CTRL_EF_IF_M154_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS))
#define EF_CTRL_EF_IF_CPU1_DIS EF_CTRL_EF_IF_CPU1_DIS
#define EF_CTRL_EF_IF_CPU1_DIS_POS (20U)
#define EF_CTRL_EF_IF_CPU1_DIS_LEN (1U)
#define EF_CTRL_EF_IF_CPU1_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)
#define EF_CTRL_EF_IF_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS))
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS EF_CTRL_EF_IF_CPU_RST_DBG_DIS
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS (21U)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS))
#define EF_CTRL_EF_IF_SE_DBG_DIS EF_CTRL_EF_IF_SE_DBG_DIS
#define EF_CTRL_EF_IF_SE_DBG_DIS_POS (22U)
#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)
#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS))
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS EF_CTRL_EF_IF_EFUSE_DBG_DIS
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS (23U)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS))
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS EF_CTRL_EF_IF_DBG_JTAG_1_DIS
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS (24U)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN (2U)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS))
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS EF_CTRL_EF_IF_DBG_JTAG_0_DIS
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS (26U)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN (2U)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS))
#define EF_CTRL_EF_IF_DBG_MODE EF_CTRL_EF_IF_DBG_MODE
#define EF_CTRL_EF_IF_DBG_MODE_POS (28U)
#define EF_CTRL_EF_IF_DBG_MODE_LEN (4U)
#define EF_CTRL_EF_IF_DBG_MODE_MSK (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)
#define EF_CTRL_EF_IF_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS))
/* 0x818 : ef_sw_cfg_0 */
#define EF_CTRL_EF_SW_CFG_0_OFFSET (0x818)
#define EF_CTRL_EF_SW_SF_AES_MODE EF_CTRL_EF_SW_SF_AES_MODE
#define EF_CTRL_EF_SW_SF_AES_MODE_POS (0U)
#define EF_CTRL_EF_SW_SF_AES_MODE_LEN (2U)
#define EF_CTRL_EF_SW_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)
#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS))
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE EF_CTRL_EF_SW_SBOOT_SIGN_MODE
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS (2U)
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN (2U)
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_MSK (((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS)
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS))
#define EF_CTRL_EF_SW_SBOOT_EN EF_CTRL_EF_SW_SBOOT_EN
#define EF_CTRL_EF_SW_SBOOT_EN_POS (4U)
#define EF_CTRL_EF_SW_SBOOT_EN_LEN (2U)
#define EF_CTRL_EF_SW_SBOOT_EN_MSK (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)
#define EF_CTRL_EF_SW_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS))
#define EF_CTRL_EF_SW_CPU1_ENC_EN EF_CTRL_EF_SW_CPU1_ENC_EN
#define EF_CTRL_EF_SW_CPU1_ENC_EN_POS (6U)
#define EF_CTRL_EF_SW_CPU1_ENC_EN_LEN (1U)
#define EF_CTRL_EF_SW_CPU1_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS)
#define EF_CTRL_EF_SW_CPU1_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS))
#define EF_CTRL_EF_SW_CPU0_ENC_EN EF_CTRL_EF_SW_CPU0_ENC_EN
#define EF_CTRL_EF_SW_CPU0_ENC_EN_POS (7U)
#define EF_CTRL_EF_SW_CPU0_ENC_EN_LEN (1U)
#define EF_CTRL_EF_SW_CPU0_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS)
#define EF_CTRL_EF_SW_CPU0_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS))
#define EF_CTRL_EF_SW_SF_KEY_0_SEL EF_CTRL_EF_SW_SF_KEY_0_SEL
#define EF_CTRL_EF_SW_SF_KEY_0_SEL_POS (12U)
#define EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN (2U)
#define EF_CTRL_EF_SW_SF_KEY_0_SEL_MSK (((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS)
#define EF_CTRL_EF_SW_SF_KEY_0_SEL_UMSK (~(((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS))
#define EF_CTRL_EF_SW_SDU_DIS EF_CTRL_EF_SW_SDU_DIS
#define EF_CTRL_EF_SW_SDU_DIS_POS (14U)
#define EF_CTRL_EF_SW_SDU_DIS_LEN (1U)
#define EF_CTRL_EF_SW_SDU_DIS_MSK (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)
#define EF_CTRL_EF_SW_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS))
#define EF_CTRL_EF_SW_BLE_DIS EF_CTRL_EF_SW_BLE_DIS
#define EF_CTRL_EF_SW_BLE_DIS_POS (15U)
#define EF_CTRL_EF_SW_BLE_DIS_LEN (1U)
#define EF_CTRL_EF_SW_BLE_DIS_MSK (((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS)
#define EF_CTRL_EF_SW_BLE_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS))
#define EF_CTRL_EF_SW_WIFI_DIS EF_CTRL_EF_SW_WIFI_DIS
#define EF_CTRL_EF_SW_WIFI_DIS_POS (16U)
#define EF_CTRL_EF_SW_WIFI_DIS_LEN (1U)
#define EF_CTRL_EF_SW_WIFI_DIS_MSK (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)
#define EF_CTRL_EF_SW_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS))
#define EF_CTRL_EF_SW_0_KEY_ENC_EN EF_CTRL_EF_SW_0_KEY_ENC_EN
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS (17U)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN (1U)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS))
#define EF_CTRL_EF_SW_CAM_DIS EF_CTRL_EF_SW_CAM_DIS
#define EF_CTRL_EF_SW_CAM_DIS_POS (18U)
#define EF_CTRL_EF_SW_CAM_DIS_LEN (1U)
#define EF_CTRL_EF_SW_CAM_DIS_MSK (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)
#define EF_CTRL_EF_SW_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS))
#define EF_CTRL_EF_SW_M154_DIS EF_CTRL_EF_SW_M154_DIS
#define EF_CTRL_EF_SW_M154_DIS_POS (19U)
#define EF_CTRL_EF_SW_M154_DIS_LEN (1U)
#define EF_CTRL_EF_SW_M154_DIS_MSK (((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS)
#define EF_CTRL_EF_SW_M154_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS))
#define EF_CTRL_EF_SW_CPU1_DIS EF_CTRL_EF_SW_CPU1_DIS
#define EF_CTRL_EF_SW_CPU1_DIS_POS (20U)
#define EF_CTRL_EF_SW_CPU1_DIS_LEN (1U)
#define EF_CTRL_EF_SW_CPU1_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)
#define EF_CTRL_EF_SW_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS))
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS EF_CTRL_EF_SW_CPU_RST_DBG_DIS
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS (21U)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS))
#define EF_CTRL_EF_SW_SE_DBG_DIS EF_CTRL_EF_SW_SE_DBG_DIS
#define EF_CTRL_EF_SW_SE_DBG_DIS_POS (22U)
#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)
#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS))
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS EF_CTRL_EF_SW_EFUSE_DBG_DIS
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS (23U)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS))
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS EF_CTRL_EF_SW_DBG_JTAG_1_DIS
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS (24U)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN (2U)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS))
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS EF_CTRL_EF_SW_DBG_JTAG_0_DIS
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS (26U)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN (2U)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS))
#define EF_CTRL_EF_SW_DBG_MODE EF_CTRL_EF_SW_DBG_MODE
#define EF_CTRL_EF_SW_DBG_MODE_POS (28U)
#define EF_CTRL_EF_SW_DBG_MODE_LEN (4U)
#define EF_CTRL_EF_SW_DBG_MODE_MSK (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)
#define EF_CTRL_EF_SW_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS))
/* 0x81C : ef_reserved */
#define EF_CTRL_EF_RESERVED_OFFSET (0x81C)
#define EF_CTRL_EF_RESERVED EF_CTRL_EF_RESERVED
#define EF_CTRL_EF_RESERVED_POS (0U)
#define EF_CTRL_EF_RESERVED_LEN (32U)
#define EF_CTRL_EF_RESERVED_MSK (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)
#define EF_CTRL_EF_RESERVED_UMSK (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS))
/* 0x820 : ef_if_ana_trim_0 */
#define EF_CTRL_EF_IF_ANA_TRIM_0_OFFSET (0x820)
#define EF_CTRL_EF_IF_ANA_TRIM_0 EF_CTRL_EF_IF_ANA_TRIM_0
#define EF_CTRL_EF_IF_ANA_TRIM_0_POS (0U)
#define EF_CTRL_EF_IF_ANA_TRIM_0_LEN (32U)
#define EF_CTRL_EF_IF_ANA_TRIM_0_MSK (((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS)
#define EF_CTRL_EF_IF_ANA_TRIM_0_UMSK (~(((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS))
/* 0x824 : ef_if_sw_usage_0 */
#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x824)
#define EF_CTRL_EF_IF_SW_USAGE_0 EF_CTRL_EF_IF_SW_USAGE_0
#define EF_CTRL_EF_IF_SW_USAGE_0_POS (0U)
#define EF_CTRL_EF_IF_SW_USAGE_0_LEN (32U)
#define EF_CTRL_EF_IF_SW_USAGE_0_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)
#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS))
/* 0xA00 : ef_crc_ctrl_0 */
#define EF_CTRL_EF_CRC_CTRL_0_OFFSET (0xA00)
#define EF_CTRL_EF_CRC_BUSY EF_CTRL_EF_CRC_BUSY
#define EF_CTRL_EF_CRC_BUSY_POS (0U)
#define EF_CTRL_EF_CRC_BUSY_LEN (1U)
#define EF_CTRL_EF_CRC_BUSY_MSK (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)
#define EF_CTRL_EF_CRC_BUSY_UMSK (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS))
#define EF_CTRL_EF_CRC_TRIG EF_CTRL_EF_CRC_TRIG
#define EF_CTRL_EF_CRC_TRIG_POS (1U)
#define EF_CTRL_EF_CRC_TRIG_LEN (1U)
#define EF_CTRL_EF_CRC_TRIG_MSK (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)
#define EF_CTRL_EF_CRC_TRIG_UMSK (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS))
#define EF_CTRL_EF_CRC_EN EF_CTRL_EF_CRC_EN
#define EF_CTRL_EF_CRC_EN_POS (2U)
#define EF_CTRL_EF_CRC_EN_LEN (1U)
#define EF_CTRL_EF_CRC_EN_MSK (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)
#define EF_CTRL_EF_CRC_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS))
#define EF_CTRL_EF_CRC_MODE EF_CTRL_EF_CRC_MODE
#define EF_CTRL_EF_CRC_MODE_POS (3U)
#define EF_CTRL_EF_CRC_MODE_LEN (1U)
#define EF_CTRL_EF_CRC_MODE_MSK (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)
#define EF_CTRL_EF_CRC_MODE_UMSK (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS))
#define EF_CTRL_EF_CRC_ERROR EF_CTRL_EF_CRC_ERROR
#define EF_CTRL_EF_CRC_ERROR_POS (4U)
#define EF_CTRL_EF_CRC_ERROR_LEN (1U)
#define EF_CTRL_EF_CRC_ERROR_MSK (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)
#define EF_CTRL_EF_CRC_ERROR_UMSK (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS))
#define EF_CTRL_EF_CRC_DOUT_INV_EN EF_CTRL_EF_CRC_DOUT_INV_EN
#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS (5U)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN (1U)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS))
#define EF_CTRL_EF_CRC_DOUT_ENDIAN EF_CTRL_EF_CRC_DOUT_ENDIAN
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS (6U)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN (1U)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS))
#define EF_CTRL_EF_CRC_DIN_ENDIAN EF_CTRL_EF_CRC_DIN_ENDIAN
#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS (7U)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN (1U)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS))
#define EF_CTRL_EF_CRC_INT EF_CTRL_EF_CRC_INT
#define EF_CTRL_EF_CRC_INT_POS (8U)
#define EF_CTRL_EF_CRC_INT_LEN (1U)
#define EF_CTRL_EF_CRC_INT_MSK (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)
#define EF_CTRL_EF_CRC_INT_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS))
#define EF_CTRL_EF_CRC_INT_CLR EF_CTRL_EF_CRC_INT_CLR
#define EF_CTRL_EF_CRC_INT_CLR_POS (9U)
#define EF_CTRL_EF_CRC_INT_CLR_LEN (1U)
#define EF_CTRL_EF_CRC_INT_CLR_MSK (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)
#define EF_CTRL_EF_CRC_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS))
#define EF_CTRL_EF_CRC_INT_SET EF_CTRL_EF_CRC_INT_SET
#define EF_CTRL_EF_CRC_INT_SET_POS (10U)
#define EF_CTRL_EF_CRC_INT_SET_LEN (1U)
#define EF_CTRL_EF_CRC_INT_SET_MSK (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)
#define EF_CTRL_EF_CRC_INT_SET_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS))
#define EF_CTRL_EF_CRC_LOCK EF_CTRL_EF_CRC_LOCK
#define EF_CTRL_EF_CRC_LOCK_POS (11U)
#define EF_CTRL_EF_CRC_LOCK_LEN (1U)
#define EF_CTRL_EF_CRC_LOCK_MSK (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)
#define EF_CTRL_EF_CRC_LOCK_UMSK (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS))
#define EF_CTRL_EF_CRC_SLP_N EF_CTRL_EF_CRC_SLP_N
#define EF_CTRL_EF_CRC_SLP_N_POS (16U)
#define EF_CTRL_EF_CRC_SLP_N_LEN (16U)
#define EF_CTRL_EF_CRC_SLP_N_MSK (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)
#define EF_CTRL_EF_CRC_SLP_N_UMSK (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS))
/* 0xA04 : ef_crc_ctrl_1 */
#define EF_CTRL_EF_CRC_CTRL_1_OFFSET (0xA04)
#define EF_CTRL_EF_CRC_DATA_0_EN EF_CTRL_EF_CRC_DATA_0_EN
#define EF_CTRL_EF_CRC_DATA_0_EN_POS (0U)
#define EF_CTRL_EF_CRC_DATA_0_EN_LEN (32U)
#define EF_CTRL_EF_CRC_DATA_0_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)
#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS))
/* 0xA08 : ef_crc_ctrl_2 */
#define EF_CTRL_EF_CRC_CTRL_2_OFFSET (0xA08)
#define EF_CTRL_EF_CRC_DATA_1_EN EF_CTRL_EF_CRC_DATA_1_EN
#define EF_CTRL_EF_CRC_DATA_1_EN_POS (0U)
#define EF_CTRL_EF_CRC_DATA_1_EN_LEN (32U)
#define EF_CTRL_EF_CRC_DATA_1_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)
#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS))
/* 0xA0C : ef_crc_ctrl_3 */
#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C)
#define EF_CTRL_EF_CRC_IV EF_CTRL_EF_CRC_IV
#define EF_CTRL_EF_CRC_IV_POS (0U)
#define EF_CTRL_EF_CRC_IV_LEN (32U)
#define EF_CTRL_EF_CRC_IV_MSK (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)
#define EF_CTRL_EF_CRC_IV_UMSK (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS))
/* 0xA10 : ef_crc_ctrl_4 */
#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10)
#define EF_CTRL_EF_CRC_GOLDEN EF_CTRL_EF_CRC_GOLDEN
#define EF_CTRL_EF_CRC_GOLDEN_POS (0U)
#define EF_CTRL_EF_CRC_GOLDEN_LEN (32U)
#define EF_CTRL_EF_CRC_GOLDEN_MSK (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)
#define EF_CTRL_EF_CRC_GOLDEN_UMSK (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS))
/* 0xA14 : ef_crc_ctrl_5 */
#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14)
#define EF_CTRL_EF_CRC_DOUT EF_CTRL_EF_CRC_DOUT
#define EF_CTRL_EF_CRC_DOUT_POS (0U)
#define EF_CTRL_EF_CRC_DOUT_LEN (32U)
#define EF_CTRL_EF_CRC_DOUT_MSK (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)
#define EF_CTRL_EF_CRC_DOUT_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS))
struct ef_ctrl_reg {
/* 0x0 reserved */
uint8_t RESERVED0x0[2048];
/* 0x800 : ef_if_ctrl_0 */
union {
struct
{
uint32_t ef_if_0_autoload_p1_done : 1; /* [ 0], r, 0x1 */
uint32_t ef_if_0_autoload_done : 1; /* [ 1], r, 0x1 */
uint32_t ef_if_0_busy : 1; /* [ 2], r, 0x0 */
uint32_t ef_if_0_rw : 1; /* [ 3], r/w, 0x0 */
uint32_t ef_if_0_trig : 1; /* [ 4], r/w, 0x0 */
uint32_t ef_if_0_manual_en : 1; /* [ 5], r/w, 0x0 */
uint32_t ef_if_0_cyc_modify : 1; /* [ 6], r/w, 0x0 */
uint32_t ef_clk_sahb_data_sel : 1; /* [ 7], r/w, 0x0 */
uint32_t ef_if_prot_code_ctrl : 8; /* [15: 8], r/w, 0x0 */
uint32_t ef_if_por_dig : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_clk_sahb_data_gate : 1; /* [ 17], r/w, 0x0 */
uint32_t ef_if_auto_rd_en : 1; /* [ 18], r/w, 0x1 */
uint32_t ef_if_cyc_modify_lock : 1; /* [ 19], r/w, 0x0 */
uint32_t ef_if_0_int : 1; /* [ 20], r, 0x0 */
uint32_t ef_if_0_int_clr : 1; /* [ 21], r/w, 0x1 */
uint32_t ef_if_0_int_set : 1; /* [ 22], r/w, 0x0 */
uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
uint32_t ef_if_prot_code_cyc : 8; /* [31:24], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_if_ctrl_0;
/* 0x804 : ef_if_cyc_0 */
union {
struct
{
uint32_t ef_if_cyc_rd_dmy : 6; /* [ 5: 0], r/w, 0x0 */
uint32_t ef_if_cyc_rd_dat : 6; /* [11: 6], r/w, 0x1 */
uint32_t ef_if_cyc_rd_adr : 6; /* [17:12], r/w, 0x0 */
uint32_t ef_if_cyc_cs : 6; /* [23:18], r/w, 0x0 */
uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24], r/w, 0x16 */
} BF;
uint32_t WORD;
} ef_if_cyc_0;
/* 0x808 : ef_if_cyc_1 */
union {
struct
{
uint32_t ef_if_cyc_pi : 6; /* [ 5: 0], r/w, 0x9 */
uint32_t ef_if_cyc_pp : 8; /* [13: 6], r/w, 0x98 */
uint32_t ef_if_cyc_wr_adr : 6; /* [19:14], r/w, 0x1 */
uint32_t ef_if_cyc_ps_cs : 6; /* [25:20], r/w, 0x2 */
uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_if_cyc_1;
/* 0x80C : ef_if_0_manual */
union {
struct
{
uint32_t ef_if_a : 10; /* [ 9: 0], r/w, 0x0 */
uint32_t ef_if_pd : 1; /* [ 10], r/w, 0x1 */
uint32_t ef_if_ps : 1; /* [ 11], r/w, 0x0 */
uint32_t ef_if_strobe : 1; /* [ 12], r/w, 0x0 */
uint32_t ef_if_pgenb : 1; /* [ 13], r/w, 0x1 */
uint32_t ef_if_load : 1; /* [ 14], r/w, 0x1 */
uint32_t ef_if_csb : 1; /* [ 15], r/w, 0x1 */
uint32_t ef_if_0_q : 8; /* [23:16], r, 0x0 */
uint32_t ef_if_prot_code_manual : 8; /* [31:24], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_if_0_manual;
/* 0x810 : ef_if_0_status */
union {
struct
{
uint32_t ef_if_0_status : 32; /* [31: 0], r, 0xe400 */
} BF;
uint32_t WORD;
} ef_if_0_status;
/* 0x814 : ef_if_cfg_0 */
union {
struct
{
uint32_t ef_if_sf_aes_mode : 2; /* [ 1: 0], r, 0x0 */
uint32_t ef_if_sboot_sign_mode : 2; /* [ 3: 2], r, 0x0 */
uint32_t ef_if_sboot_en : 2; /* [ 5: 4], r, 0x0 */
uint32_t ef_if_cpu1_enc_en : 1; /* [ 6], r, 0x0 */
uint32_t ef_if_cpu0_enc_en : 1; /* [ 7], r, 0x0 */
uint32_t ef_if_boot_sel : 4; /* [11: 8], r, 0x0 */
uint32_t ef_if_sf_key_0_sel : 2; /* [13:12], r, 0x0 */
uint32_t ef_if_sdu_dis : 1; /* [ 14], r, 0x0 */
uint32_t ef_if_ble_dis : 1; /* [ 15], r, 0x0 */
uint32_t ef_if_wifi_dis : 1; /* [ 16], r, 0x0 */
uint32_t ef_if_0_key_enc_en : 1; /* [ 17], r, 0x0 */
uint32_t ef_if_cam_dis : 1; /* [ 18], r, 0x0 */
uint32_t ef_if_m154_dis : 1; /* [ 19], r, 0x0 */
uint32_t ef_if_cpu1_dis : 1; /* [ 20], r, 0x0 */
uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [ 21], r, 0x0 */
uint32_t ef_if_se_dbg_dis : 1; /* [ 22], r, 0x0 */
uint32_t ef_if_efuse_dbg_dis : 1; /* [ 23], r, 0x0 */
uint32_t ef_if_dbg_jtag_1_dis : 2; /* [25:24], r, 0x0 */
uint32_t ef_if_dbg_jtag_0_dis : 2; /* [27:26], r, 0x0 */
uint32_t ef_if_dbg_mode : 4; /* [31:28], r, 0x0 */
} BF;
uint32_t WORD;
} ef_if_cfg_0;
/* 0x818 : ef_sw_cfg_0 */
union {
struct
{
uint32_t ef_sw_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t ef_sw_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t ef_sw_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t ef_sw_cpu1_enc_en : 1; /* [ 6], r/w, 0x0 */
uint32_t ef_sw_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */
uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */
uint32_t ef_sw_sf_key_0_sel : 2; /* [13:12], r/w, 0x0 */
uint32_t ef_sw_sdu_dis : 1; /* [ 14], r/w, 0x0 */
uint32_t ef_sw_ble_dis : 1; /* [ 15], r/w, 0x0 */
uint32_t ef_sw_wifi_dis : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_sw_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
uint32_t ef_sw_cam_dis : 1; /* [ 18], r/w, 0x0 */
uint32_t ef_sw_m154_dis : 1; /* [ 19], r/w, 0x0 */
uint32_t ef_sw_cpu1_dis : 1; /* [ 20], r/w, 0x0 */
uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */
uint32_t ef_sw_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */
uint32_t ef_sw_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */
uint32_t ef_sw_dbg_jtag_1_dis : 2; /* [25:24], r/w, 0x0 */
uint32_t ef_sw_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
uint32_t ef_sw_dbg_mode : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_sw_cfg_0;
/* 0x81C : ef_reserved */
union {
struct
{
uint32_t ef_reserved : 32; /* [31: 0], r/w, 0xffff */
} BF;
uint32_t WORD;
} ef_reserved;
/* 0x820 : ef_if_ana_trim_0 */
union {
struct
{
uint32_t ef_if_ana_trim_0 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} ef_if_ana_trim_0;
/* 0x824 : ef_if_sw_usage_0 */
union {
struct
{
uint32_t ef_if_sw_usage_0 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} ef_if_sw_usage_0;
/* 0x828 reserved */
uint8_t RESERVED0x828[472];
/* 0xA00 : ef_crc_ctrl_0 */
union {
struct
{
uint32_t ef_crc_busy : 1; /* [ 0], r, 0x0 */
uint32_t ef_crc_trig : 1; /* [ 1], r/w, 0x0 */
uint32_t ef_crc_en : 1; /* [ 2], r/w, 0x1 */
uint32_t ef_crc_mode : 1; /* [ 3], r/w, 0x0 */
uint32_t ef_crc_error : 1; /* [ 4], r, 0x0 */
uint32_t ef_crc_dout_inv_en : 1; /* [ 5], r/w, 0x1 */
uint32_t ef_crc_dout_endian : 1; /* [ 6], r/w, 0x0 */
uint32_t ef_crc_din_endian : 1; /* [ 7], r/w, 0x0 */
uint32_t ef_crc_int : 1; /* [ 8], r, 0x0 */
uint32_t ef_crc_int_clr : 1; /* [ 9], r/w, 0x1 */
uint32_t ef_crc_int_set : 1; /* [ 10], r/w, 0x0 */
uint32_t ef_crc_lock : 1; /* [ 11], r/w, 0x0 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t ef_crc_slp_n : 16; /* [31:16], r/w, 0xff */
} BF;
uint32_t WORD;
} ef_crc_ctrl_0;
/* 0xA04 : ef_crc_ctrl_1 */
union {
struct
{
uint32_t ef_crc_data_0_en : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} ef_crc_ctrl_1;
/* 0xA08 : ef_crc_ctrl_2 */
union {
struct
{
uint32_t ef_crc_data_1_en : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} ef_crc_ctrl_2;
/* 0xA0C : ef_crc_ctrl_3 */
union {
struct
{
uint32_t ef_crc_iv : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} ef_crc_ctrl_3;
/* 0xA10 : ef_crc_ctrl_4 */
union {
struct
{
uint32_t ef_crc_golden : 32; /* [31: 0], r/w, 0xc2a8fa9dL */
} BF;
uint32_t WORD;
} ef_crc_ctrl_4;
/* 0xA14 : ef_crc_ctrl_5 */
union {
struct
{
uint32_t ef_crc_dout : 32; /* [31: 0], r, 0xffffffffL */
} BF;
uint32_t WORD;
} ef_crc_ctrl_5;
};
typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t;
#endif /* __EF_CTRL_REG_H__ */

762
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/ef_data_0_reg.h
View File

@@ -1,762 +0,0 @@
/**
******************************************************************************
* @file ef_data_0_reg.h
* @version V1.2
* @date 2020-04-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_DATA_0_REG_H__
#define __EF_DATA_0_REG_H__
#include "bl702.h"
/* 0x0 : ef_cfg_0 */
#define EF_DATA_0_EF_CFG_0_OFFSET (0x0)
#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE
#define EF_DATA_0_EF_SF_AES_MODE_POS (0U)
#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U)
#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)
#define EF_DATA_0_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS))
#define EF_DATA_0_EF_SBOOT_SIGN_MODE EF_DATA_0_EF_SBOOT_SIGN_MODE
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS (2U)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN (2U)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS))
#define EF_DATA_0_EF_SBOOT_EN EF_DATA_0_EF_SBOOT_EN
#define EF_DATA_0_EF_SBOOT_EN_POS (4U)
#define EF_DATA_0_EF_SBOOT_EN_LEN (2U)
#define EF_DATA_0_EF_SBOOT_EN_MSK (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)
#define EF_DATA_0_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS))
#define EF_DATA_0_EF_CPU0_ENC_EN EF_DATA_0_EF_CPU0_ENC_EN
#define EF_DATA_0_EF_CPU0_ENC_EN_POS (7U)
#define EF_DATA_0_EF_CPU0_ENC_EN_LEN (1U)
#define EF_DATA_0_EF_CPU0_ENC_EN_MSK (((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS)
#define EF_DATA_0_EF_CPU0_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS))
#define EF_DATA_0_EF_BOOT_SEL EF_DATA_0_EF_BOOT_SEL
#define EF_DATA_0_EF_BOOT_SEL_POS (8U)
#define EF_DATA_0_EF_BOOT_SEL_LEN (4U)
#define EF_DATA_0_EF_BOOT_SEL_MSK (((1U << EF_DATA_0_EF_BOOT_SEL_LEN) - 1) << EF_DATA_0_EF_BOOT_SEL_POS)
#define EF_DATA_0_EF_BOOT_SEL_UMSK (~(((1U << EF_DATA_0_EF_BOOT_SEL_LEN) - 1) << EF_DATA_0_EF_BOOT_SEL_POS))
#define EF_DATA_0_EF_SF_KEY_0_SEL EF_DATA_0_EF_SF_KEY_0_SEL
#define EF_DATA_0_EF_SF_KEY_0_SEL_POS (12U)
#define EF_DATA_0_EF_SF_KEY_0_SEL_LEN (2U)
#define EF_DATA_0_EF_SF_KEY_0_SEL_MSK (((1U << EF_DATA_0_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_0_SEL_POS)
#define EF_DATA_0_EF_SF_KEY_0_SEL_UMSK (~(((1U << EF_DATA_0_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_0_SEL_POS))
#define EF_DATA_0_EF_0_KEY_ENC_EN EF_DATA_0_EF_0_KEY_ENC_EN
#define EF_DATA_0_EF_0_KEY_ENC_EN_POS (17U)
#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN (1U)
#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)
#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS))
#define EF_DATA_0_EF_DBG_JTAG_0_DIS EF_DATA_0_EF_DBG_JTAG_0_DIS
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS (26U)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN (2U)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS))
#define EF_DATA_0_EF_DBG_MODE EF_DATA_0_EF_DBG_MODE
#define EF_DATA_0_EF_DBG_MODE_POS (28U)
#define EF_DATA_0_EF_DBG_MODE_LEN (4U)
#define EF_DATA_0_EF_DBG_MODE_MSK (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)
#define EF_DATA_0_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS))
/* 0x4 : ef_dbg_pwd_low */
#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4)
#define EF_DATA_0_EF_DBG_PWD_LOW EF_DATA_0_EF_DBG_PWD_LOW
#define EF_DATA_0_EF_DBG_PWD_LOW_POS (0U)
#define EF_DATA_0_EF_DBG_PWD_LOW_LEN (32U)
#define EF_DATA_0_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)
#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS))
/* 0x8 : ef_dbg_pwd_high */
#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8)
#define EF_DATA_0_EF_DBG_PWD_HIGH EF_DATA_0_EF_DBG_PWD_HIGH
#define EF_DATA_0_EF_DBG_PWD_HIGH_POS (0U)
#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN (32U)
#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)
#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS))
/* 0xC : ef_ana_trim_0 */
#define EF_DATA_0_EF_ANA_TRIM_0_OFFSET (0xC)
#define EF_DATA_0_EF_ANA_TRIM_0 EF_DATA_0_EF_ANA_TRIM_0
#define EF_DATA_0_EF_ANA_TRIM_0_POS (0U)
#define EF_DATA_0_EF_ANA_TRIM_0_LEN (32U)
#define EF_DATA_0_EF_ANA_TRIM_0_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS)
#define EF_DATA_0_EF_ANA_TRIM_0_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS))
/* 0x10 : ef_sw_usage_0 */
#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x10)
#define EF_DATA_0_EF_SW_USAGE_0 EF_DATA_0_EF_SW_USAGE_0
#define EF_DATA_0_EF_SW_USAGE_0_POS (0U)
#define EF_DATA_0_EF_SW_USAGE_0_LEN (32U)
#define EF_DATA_0_EF_SW_USAGE_0_MSK (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)
#define EF_DATA_0_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS))
/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14)
#define EF_DATA_0_EF_WIFI_MAC_LOW EF_DATA_0_EF_WIFI_MAC_LOW
#define EF_DATA_0_EF_WIFI_MAC_LOW_POS (0U)
#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN (32U)
#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)
#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS))
/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18)
#define EF_DATA_0_EF_WIFI_MAC_HIGH EF_DATA_0_EF_WIFI_MAC_HIGH
#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS (0U)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN (32U)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS))
/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
#define EF_DATA_0_EF_KEY_SLOT_0_W0 EF_DATA_0_EF_KEY_SLOT_0_W0
#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS))
/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20)
#define EF_DATA_0_EF_KEY_SLOT_0_W1 EF_DATA_0_EF_KEY_SLOT_0_W1
#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS))
/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24)
#define EF_DATA_0_EF_KEY_SLOT_0_W2 EF_DATA_0_EF_KEY_SLOT_0_W2
#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS))
/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28)
#define EF_DATA_0_EF_KEY_SLOT_0_W3 EF_DATA_0_EF_KEY_SLOT_0_W3
#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS))
/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
#define EF_DATA_0_EF_KEY_SLOT_1_W0 EF_DATA_0_EF_KEY_SLOT_1_W0
#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS))
/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30)
#define EF_DATA_0_EF_KEY_SLOT_1_W1 EF_DATA_0_EF_KEY_SLOT_1_W1
#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS))
/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34)
#define EF_DATA_0_EF_KEY_SLOT_1_W2 EF_DATA_0_EF_KEY_SLOT_1_W2
#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS))
/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38)
#define EF_DATA_0_EF_KEY_SLOT_1_W3 EF_DATA_0_EF_KEY_SLOT_1_W3
#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS))
/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
#define EF_DATA_0_EF_KEY_SLOT_2_W0 EF_DATA_0_EF_KEY_SLOT_2_W0
#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS))
/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40)
#define EF_DATA_0_EF_KEY_SLOT_2_W1 EF_DATA_0_EF_KEY_SLOT_2_W1
#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS))
/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44)
#define EF_DATA_0_EF_KEY_SLOT_2_W2 EF_DATA_0_EF_KEY_SLOT_2_W2
#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS))
/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48)
#define EF_DATA_0_EF_KEY_SLOT_2_W3 EF_DATA_0_EF_KEY_SLOT_2_W3
#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS))
/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
#define EF_DATA_0_EF_KEY_SLOT_3_W0 EF_DATA_0_EF_KEY_SLOT_3_W0
#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS))
/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50)
#define EF_DATA_0_EF_KEY_SLOT_3_W1 EF_DATA_0_EF_KEY_SLOT_3_W1
#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS))
/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54)
#define EF_DATA_0_EF_KEY_SLOT_3_W2 EF_DATA_0_EF_KEY_SLOT_3_W2
#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS))
/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58)
#define EF_DATA_0_EF_KEY_SLOT_3_W3 EF_DATA_0_EF_KEY_SLOT_3_W3
#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS))
/* 0x5C : ef_key_slot_4_w0 */
#define EF_DATA_0_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
#define EF_DATA_0_EF_KEY_SLOT_4_W0 EF_DATA_0_EF_KEY_SLOT_4_W0
#define EF_DATA_0_EF_KEY_SLOT_4_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS))
/* 0x60 : ef_key_slot_4_w1 */
#define EF_DATA_0_EF_KEY_SLOT_4_W1_OFFSET (0x60)
#define EF_DATA_0_EF_KEY_SLOT_4_W1 EF_DATA_0_EF_KEY_SLOT_4_W1
#define EF_DATA_0_EF_KEY_SLOT_4_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS))
/* 0x64 : ef_key_slot_4_w2 */
#define EF_DATA_0_EF_KEY_SLOT_4_W2_OFFSET (0x64)
#define EF_DATA_0_EF_KEY_SLOT_4_W2 EF_DATA_0_EF_KEY_SLOT_4_W2
#define EF_DATA_0_EF_KEY_SLOT_4_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS))
/* 0x68 : ef_key_slot_4_w3 */
#define EF_DATA_0_EF_KEY_SLOT_4_W3_OFFSET (0x68)
#define EF_DATA_0_EF_KEY_SLOT_4_W3 EF_DATA_0_EF_KEY_SLOT_4_W3
#define EF_DATA_0_EF_KEY_SLOT_4_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS))
/* 0x6C : ef_key_slot_5_w0 */
#define EF_DATA_0_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
#define EF_DATA_0_EF_KEY_SLOT_5_W0 EF_DATA_0_EF_KEY_SLOT_5_W0
#define EF_DATA_0_EF_KEY_SLOT_5_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS))
/* 0x70 : ef_key_slot_5_w1 */
#define EF_DATA_0_EF_KEY_SLOT_5_W1_OFFSET (0x70)
#define EF_DATA_0_EF_KEY_SLOT_5_W1 EF_DATA_0_EF_KEY_SLOT_5_W1
#define EF_DATA_0_EF_KEY_SLOT_5_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS))
/* 0x74 : ef_key_slot_5_w2 */
#define EF_DATA_0_EF_KEY_SLOT_5_W2_OFFSET (0x74)
#define EF_DATA_0_EF_KEY_SLOT_5_W2 EF_DATA_0_EF_KEY_SLOT_5_W2
#define EF_DATA_0_EF_KEY_SLOT_5_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS))
/* 0x78 : ef_key_slot_5_w3 */
#define EF_DATA_0_EF_KEY_SLOT_5_W3_OFFSET (0x78)
#define EF_DATA_0_EF_KEY_SLOT_5_W3 EF_DATA_0_EF_KEY_SLOT_5_W3
#define EF_DATA_0_EF_KEY_SLOT_5_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS))
/* 0x7C : ef_data_0_lock */
#define EF_DATA_0_LOCK_OFFSET (0x7C)
#define EF_DATA_0_EF_ANA_TRIM_1 EF_DATA_0_EF_ANA_TRIM_1
#define EF_DATA_0_EF_ANA_TRIM_1_POS (0U)
#define EF_DATA_0_EF_ANA_TRIM_1_LEN (13U)
#define EF_DATA_0_EF_ANA_TRIM_1_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS)
#define EF_DATA_0_EF_ANA_TRIM_1_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L EF_DATA_0_WR_LOCK_KEY_SLOT_4_L
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS (13U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L EF_DATA_0_WR_LOCK_KEY_SLOT_5_L
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS (14U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS))
#define EF_DATA_0_WR_LOCK_BOOT_MODE EF_DATA_0_WR_LOCK_BOOT_MODE
#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS (15U)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN (1U)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS))
#define EF_DATA_0_WR_LOCK_DBG_PWD EF_DATA_0_WR_LOCK_DBG_PWD
#define EF_DATA_0_WR_LOCK_DBG_PWD_POS (16U)
#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)
#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS))
#define EF_DATA_0_WR_LOCK_SW_USAGE_0 EF_DATA_0_WR_LOCK_SW_USAGE_0
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS (17U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN (1U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS))
#define EF_DATA_0_WR_LOCK_WIFI_MAC EF_DATA_0_WR_LOCK_WIFI_MAC
#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS (18U)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN (1U)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0 EF_DATA_0_WR_LOCK_KEY_SLOT_0
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS (19U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1 EF_DATA_0_WR_LOCK_KEY_SLOT_1
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS (20U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2 EF_DATA_0_WR_LOCK_KEY_SLOT_2
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS (21U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3 EF_DATA_0_WR_LOCK_KEY_SLOT_3
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS (22U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H EF_DATA_0_WR_LOCK_KEY_SLOT_4_H
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS (23U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H EF_DATA_0_WR_LOCK_KEY_SLOT_5_H
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS (24U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS))
#define EF_DATA_0_RD_LOCK_DBG_PWD EF_DATA_0_RD_LOCK_DBG_PWD
#define EF_DATA_0_RD_LOCK_DBG_PWD_POS (25U)
#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)
#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0 EF_DATA_0_RD_LOCK_KEY_SLOT_0
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS (26U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1 EF_DATA_0_RD_LOCK_KEY_SLOT_1
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS (27U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2 EF_DATA_0_RD_LOCK_KEY_SLOT_2
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS (28U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3 EF_DATA_0_RD_LOCK_KEY_SLOT_3
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS (29U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4 EF_DATA_0_RD_LOCK_KEY_SLOT_4
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS (30U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5 EF_DATA_0_RD_LOCK_KEY_SLOT_5
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS (31U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS))
struct ef_data_0_reg {
/* 0x0 : ef_cfg_0 */
union {
struct
{
uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t rsvd0 : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t rsvd1 : 1; /* [ 6], r/w, 0x0 */
uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */
uint32_t ef_boot_sel : 4; /* [11: 8], r/w, 0x0 */
uint32_t ef_sf_key_0_sel : 2; /* [13:12], r/w, 0x0 */
uint32_t rsvd2 : 1; /* [ 14], r/w, 0x0 */
uint32_t rsvd3 : 1; /* [ 15], r/w, 0x0 */
uint32_t rsvd4 : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
uint32_t rsvd5 : 1; /* [ 18], r/w, 0x0 */
uint32_t rsvd6 : 1; /* [ 19], r/w, 0x0 */
uint32_t rsvd7 : 1; /* [ 20], r/w, 0x0 */
uint32_t rsvd8 : 1; /* [ 21], r/w, 0x0 */
uint32_t rsvd9 : 1; /* [ 22], r/w, 0x0 */
uint32_t rsvd10 : 1; /* [ 23], r/w, 0x0 */
uint32_t rsvd11 : 2; /* [25:24], r/w, 0x0 */
uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_cfg_0;
/* 0x4 : ef_dbg_pwd_low */
union {
struct
{
uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd_low;
/* 0x8 : ef_dbg_pwd_high */
union {
struct
{
uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd_high;
/* 0xC : ef_ana_trim_0 */
union {
struct
{
uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_ana_trim_0;
/* 0x10 : ef_sw_usage_0 */
union {
struct
{
uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_sw_usage_0;
/* 0x14 : ef_wifi_mac_low */
union {
struct
{
uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_wifi_mac_low;
/* 0x18 : ef_wifi_mac_high */
union {
struct
{
uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_wifi_mac_high;
/* 0x1C : ef_key_slot_0_w0 */
union {
struct
{
uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w0;
/* 0x20 : ef_key_slot_0_w1 */
union {
struct
{
uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w1;
/* 0x24 : ef_key_slot_0_w2 */
union {
struct
{
uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w2;
/* 0x28 : ef_key_slot_0_w3 */
union {
struct
{
uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w3;
/* 0x2C : ef_key_slot_1_w0 */
union {
struct
{
uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w0;
/* 0x30 : ef_key_slot_1_w1 */
union {
struct
{
uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w1;
/* 0x34 : ef_key_slot_1_w2 */
union {
struct
{
uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w2;
/* 0x38 : ef_key_slot_1_w3 */
union {
struct
{
uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w3;
/* 0x3C : ef_key_slot_2_w0 */
union {
struct
{
uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w0;
/* 0x40 : ef_key_slot_2_w1 */
union {
struct
{
uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w1;
/* 0x44 : ef_key_slot_2_w2 */
union {
struct
{
uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w2;
/* 0x48 : ef_key_slot_2_w3 */
union {
struct
{
uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w3;
/* 0x4C : ef_key_slot_3_w0 */
union {
struct
{
uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w0;
/* 0x50 : ef_key_slot_3_w1 */
union {
struct
{
uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w1;
/* 0x54 : ef_key_slot_3_w2 */
union {
struct
{
uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w2;
/* 0x58 : ef_key_slot_3_w3 */
union {
struct
{
uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w3;
/* 0x5C : ef_key_slot_4_w0 */
union {
struct
{
uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w0;
/* 0x60 : ef_key_slot_4_w1 */
union {
struct
{
uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w1;
/* 0x64 : ef_key_slot_4_w2 */
union {
struct
{
uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w2;
/* 0x68 : ef_key_slot_4_w3 */
union {
struct
{
uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w3;
/* 0x6C : ef_key_slot_5_w0 */
union {
struct
{
uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w0;
/* 0x70 : ef_key_slot_5_w1 */
union {
struct
{
uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w1;
/* 0x74 : ef_key_slot_5_w2 */
union {
struct
{
uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w2;
/* 0x78 : ef_key_slot_5_w3 */
union {
struct
{
uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w3;
/* 0x7C : ef_data_0_lock */
union {
struct
{
uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */
uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */
uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */
uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */
uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */
uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */
uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */
uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */
uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */
uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */
uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */
uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */
uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */
uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */
uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */
uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */
uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */
uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */
uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */
uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_data_0_lock;
};
typedef volatile struct ef_data_0_reg ef_data_0_reg_t;
#endif /* __EF_DATA_0_REG_H__ */

601
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/emac_reg.h
View File

@@ -1,601 +0,0 @@
/**
******************************************************************************
* @file emac_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EMAC_REG_H__
#define __EMAC_REG_H__
#include "bl702.h"
/* 0x0 : MODE */
#define EMAC_MODE_OFFSET (0x0)
#define EMAC_RXEN EMAC_RXEN
#define EMAC_RXEN_POS (0U)
#define EMAC_RXEN_LEN (1U)
#define EMAC_RXEN_MSK (((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS)
#define EMAC_RXEN_UMSK (~(((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS))
#define EMAC_TXEN EMAC_TXEN
#define EMAC_TXEN_POS (1U)
#define EMAC_TXEN_LEN (1U)
#define EMAC_TXEN_MSK (((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS)
#define EMAC_TXEN_UMSK (~(((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS))
#define EMAC_NOPRE EMAC_NOPRE
#define EMAC_NOPRE_POS (2U)
#define EMAC_NOPRE_LEN (1U)
#define EMAC_NOPRE_MSK (((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS)
#define EMAC_NOPRE_UMSK (~(((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS))
#define EMAC_BRO EMAC_BRO
#define EMAC_BRO_POS (3U)
#define EMAC_BRO_LEN (1U)
#define EMAC_BRO_MSK (((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS)
#define EMAC_BRO_UMSK (~(((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS))
#define EMAC_PRO EMAC_PRO
#define EMAC_PRO_POS (5U)
#define EMAC_PRO_LEN (1U)
#define EMAC_PRO_MSK (((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS)
#define EMAC_PRO_UMSK (~(((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS))
#define EMAC_IFG EMAC_IFG
#define EMAC_IFG_POS (6U)
#define EMAC_IFG_LEN (1U)
#define EMAC_IFG_MSK (((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS)
#define EMAC_IFG_UMSK (~(((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS))
#define EMAC_FULLD EMAC_FULLD
#define EMAC_FULLD_POS (10U)
#define EMAC_FULLD_LEN (1U)
#define EMAC_FULLD_MSK (((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS)
#define EMAC_FULLD_UMSK (~(((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS))
#define EMAC_CRCEN EMAC_CRCEN
#define EMAC_CRCEN_POS (13U)
#define EMAC_CRCEN_LEN (1U)
#define EMAC_CRCEN_MSK (((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS)
#define EMAC_CRCEN_UMSK (~(((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS))
#define EMAC_HUGEN EMAC_HUGEN
#define EMAC_HUGEN_POS (14U)
#define EMAC_HUGEN_LEN (1U)
#define EMAC_HUGEN_MSK (((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS)
#define EMAC_HUGEN_UMSK (~(((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS))
#define EMAC_PAD EMAC_PAD
#define EMAC_PAD_POS (15U)
#define EMAC_PAD_LEN (1U)
#define EMAC_PAD_MSK (((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS)
#define EMAC_PAD_UMSK (~(((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS))
#define EMAC_RECSMALL EMAC_RECSMALL
#define EMAC_RECSMALL_POS (16U)
#define EMAC_RECSMALL_LEN (1U)
#define EMAC_RECSMALL_MSK (((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS)
#define EMAC_RECSMALL_UMSK (~(((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS))
#define EMAC_RMII_EN EMAC_RMII_EN
#define EMAC_RMII_EN_POS (17U)
#define EMAC_RMII_EN_LEN (1U)
#define EMAC_RMII_EN_MSK (((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS)
#define EMAC_RMII_EN_UMSK (~(((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS))
/* 0x4 : INT_SOURCE */
#define EMAC_INT_SOURCE_OFFSET (0x4)
#define EMAC_TXB EMAC_TXB
#define EMAC_TXB_POS (0U)
#define EMAC_TXB_LEN (1U)
#define EMAC_TXB_MSK (((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS)
#define EMAC_TXB_UMSK (~(((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS))
#define EMAC_TXE EMAC_TXE
#define EMAC_TXE_POS (1U)
#define EMAC_TXE_LEN (1U)
#define EMAC_TXE_MSK (((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS)
#define EMAC_TXE_UMSK (~(((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS))
#define EMAC_RXB EMAC_RXB
#define EMAC_RXB_POS (2U)
#define EMAC_RXB_LEN (1U)
#define EMAC_RXB_MSK (((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS)
#define EMAC_RXB_UMSK (~(((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS))
#define EMAC_RXE EMAC_RXE
#define EMAC_RXE_POS (3U)
#define EMAC_RXE_LEN (1U)
#define EMAC_RXE_MSK (((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS)
#define EMAC_RXE_UMSK (~(((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS))
#define EMAC_BUSY EMAC_BUSY
#define EMAC_BUSY_POS (4U)
#define EMAC_BUSY_LEN (1U)
#define EMAC_BUSY_MSK (((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS)
#define EMAC_BUSY_UMSK (~(((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS))
#define EMAC_TXC EMAC_TXC
#define EMAC_TXC_POS (5U)
#define EMAC_TXC_LEN (1U)
#define EMAC_TXC_MSK (((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS)
#define EMAC_TXC_UMSK (~(((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS))
#define EMAC_RXC EMAC_RXC
#define EMAC_RXC_POS (6U)
#define EMAC_RXC_LEN (1U)
#define EMAC_RXC_MSK (((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS)
#define EMAC_RXC_UMSK (~(((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS))
/* 0x8 : INT_MASK */
#define EMAC_INT_MASK_OFFSET (0x8)
#define EMAC_TXB_M EMAC_TXB_M
#define EMAC_TXB_M_POS (0U)
#define EMAC_TXB_M_LEN (1U)
#define EMAC_TXB_M_MSK (((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS)
#define EMAC_TXB_M_UMSK (~(((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS))
#define EMAC_TXE_M EMAC_TXE_M
#define EMAC_TXE_M_POS (1U)
#define EMAC_TXE_M_LEN (1U)
#define EMAC_TXE_M_MSK (((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS)
#define EMAC_TXE_M_UMSK (~(((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS))
#define EMAC_RXB_M EMAC_RXB_M
#define EMAC_RXB_M_POS (2U)
#define EMAC_RXB_M_LEN (1U)
#define EMAC_RXB_M_MSK (((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS)
#define EMAC_RXB_M_UMSK (~(((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS))
#define EMAC_RXE_M EMAC_RXE_M
#define EMAC_RXE_M_POS (3U)
#define EMAC_RXE_M_LEN (1U)
#define EMAC_RXE_M_MSK (((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS)
#define EMAC_RXE_M_UMSK (~(((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS))
#define EMAC_BUSY_M EMAC_BUSY_M
#define EMAC_BUSY_M_POS (4U)
#define EMAC_BUSY_M_LEN (1U)
#define EMAC_BUSY_M_MSK (((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS)
#define EMAC_BUSY_M_UMSK (~(((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS))
#define EMAC_TXC_M EMAC_TXC_M
#define EMAC_TXC_M_POS (5U)
#define EMAC_TXC_M_LEN (1U)
#define EMAC_TXC_M_MSK (((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS)
#define EMAC_TXC_M_UMSK (~(((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS))
#define EMAC_RXC_M EMAC_RXC_M
#define EMAC_RXC_M_POS (6U)
#define EMAC_RXC_M_LEN (1U)
#define EMAC_RXC_M_MSK (((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS)
#define EMAC_RXC_M_UMSK (~(((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS))
/* 0xC : IPGT */
#define EMAC_IPGT_OFFSET (0xC)
#define EMAC_IPGT EMAC_IPGT
#define EMAC_IPGT_POS (0U)
#define EMAC_IPGT_LEN (7U)
#define EMAC_IPGT_MSK (((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS)
#define EMAC_IPGT_UMSK (~(((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS))
/* 0x18 : PACKETLEN */
#define EMAC_PACKETLEN_OFFSET (0x18)
#define EMAC_MAXFL EMAC_MAXFL
#define EMAC_MAXFL_POS (0U)
#define EMAC_MAXFL_LEN (16U)
#define EMAC_MAXFL_MSK (((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS)
#define EMAC_MAXFL_UMSK (~(((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS))
#define EMAC_MINFL EMAC_MINFL
#define EMAC_MINFL_POS (16U)
#define EMAC_MINFL_LEN (16U)
#define EMAC_MINFL_MSK (((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS)
#define EMAC_MINFL_UMSK (~(((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS))
/* 0x1C : COLLCONFIG */
#define EMAC_COLLCONFIG_OFFSET (0x1C)
#define EMAC_COLLVALID EMAC_COLLVALID
#define EMAC_COLLVALID_POS (0U)
#define EMAC_COLLVALID_LEN (6U)
#define EMAC_COLLVALID_MSK (((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS)
#define EMAC_COLLVALID_UMSK (~(((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS))
#define EMAC_MAXRET EMAC_MAXRET
#define EMAC_MAXRET_POS (16U)
#define EMAC_MAXRET_LEN (4U)
#define EMAC_MAXRET_MSK (((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS)
#define EMAC_MAXRET_UMSK (~(((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS))
/* 0x20 : TX_BD_NUM */
#define EMAC_TX_BD_NUM_OFFSET (0x20)
#define EMAC_TXBDNUM EMAC_TXBDNUM
#define EMAC_TXBDNUM_POS (0U)
#define EMAC_TXBDNUM_LEN (8U)
#define EMAC_TXBDNUM_MSK (((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS)
#define EMAC_TXBDNUM_UMSK (~(((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS))
#define EMAC_TXBDPTR EMAC_TXBDPTR
#define EMAC_TXBDPTR_POS (16U)
#define EMAC_TXBDPTR_LEN (7U)
#define EMAC_TXBDPTR_MSK (((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS)
#define EMAC_TXBDPTR_UMSK (~(((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS))
#define EMAC_RXBDPTR EMAC_RXBDPTR
#define EMAC_RXBDPTR_POS (24U)
#define EMAC_RXBDPTR_LEN (7U)
#define EMAC_RXBDPTR_MSK (((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS)
#define EMAC_RXBDPTR_UMSK (~(((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS))
/* 0x28 : MIIMODE */
#define EMAC_MIIMODE_OFFSET (0x28)
#define EMAC_CLKDIV EMAC_CLKDIV
#define EMAC_CLKDIV_POS (0U)
#define EMAC_CLKDIV_LEN (8U)
#define EMAC_CLKDIV_MSK (((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS)
#define EMAC_CLKDIV_UMSK (~(((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS))
#define EMAC_MIINOPRE EMAC_MIINOPRE
#define EMAC_MIINOPRE_POS (8U)
#define EMAC_MIINOPRE_LEN (1U)
#define EMAC_MIINOPRE_MSK (((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS)
#define EMAC_MIINOPRE_UMSK (~(((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS))
/* 0x2C : MIICOMMAND */
#define EMAC_MIICOMMAND_OFFSET (0x2C)
#define EMAC_SCANSTAT EMAC_SCANSTAT
#define EMAC_SCANSTAT_POS (0U)
#define EMAC_SCANSTAT_LEN (1U)
#define EMAC_SCANSTAT_MSK (((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS)
#define EMAC_SCANSTAT_UMSK (~(((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS))
#define EMAC_RSTAT EMAC_RSTAT
#define EMAC_RSTAT_POS (1U)
#define EMAC_RSTAT_LEN (1U)
#define EMAC_RSTAT_MSK (((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS)
#define EMAC_RSTAT_UMSK (~(((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS))
#define EMAC_WCTRLDATA EMAC_WCTRLDATA
#define EMAC_WCTRLDATA_POS (2U)
#define EMAC_WCTRLDATA_LEN (1U)
#define EMAC_WCTRLDATA_MSK (((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS)
#define EMAC_WCTRLDATA_UMSK (~(((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS))
/* 0x30 : MIIADDRESS */
#define EMAC_MIIADDRESS_OFFSET (0x30)
#define EMAC_FIAD EMAC_FIAD
#define EMAC_FIAD_POS (0U)
#define EMAC_FIAD_LEN (5U)
#define EMAC_FIAD_MSK (((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS)
#define EMAC_FIAD_UMSK (~(((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS))
#define EMAC_RGAD EMAC_RGAD
#define EMAC_RGAD_POS (8U)
#define EMAC_RGAD_LEN (5U)
#define EMAC_RGAD_MSK (((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS)
#define EMAC_RGAD_UMSK (~(((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS))
/* 0x34 : MIITX_DATA */
#define EMAC_MIITX_DATA_OFFSET (0x34)
#define EMAC_CTRLDATA EMAC_CTRLDATA
#define EMAC_CTRLDATA_POS (0U)
#define EMAC_CTRLDATA_LEN (16U)
#define EMAC_CTRLDATA_MSK (((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS)
#define EMAC_CTRLDATA_UMSK (~(((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS))
/* 0x38 : MIIRX_DATA */
#define EMAC_MIIRX_DATA_OFFSET (0x38)
#define EMAC_PRSD EMAC_PRSD
#define EMAC_PRSD_POS (0U)
#define EMAC_PRSD_LEN (16U)
#define EMAC_PRSD_MSK (((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS)
#define EMAC_PRSD_UMSK (~(((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS))
/* 0x3C : MIISTATUS */
#define EMAC_MIISTATUS_OFFSET (0x3C)
#define EMAC_MIIM_LINKFAIL EMAC_MIIM_LINKFAIL
#define EMAC_MIIM_LINKFAIL_POS (0U)
#define EMAC_MIIM_LINKFAIL_LEN (1U)
#define EMAC_MIIM_LINKFAIL_MSK (((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS)
#define EMAC_MIIM_LINKFAIL_UMSK (~(((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS))
#define EMAC_MIIM_BUSY EMAC_MIIM_BUSY
#define EMAC_MIIM_BUSY_POS (1U)
#define EMAC_MIIM_BUSY_LEN (1U)
#define EMAC_MIIM_BUSY_MSK (((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS)
#define EMAC_MIIM_BUSY_UMSK (~(((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS))
/* 0x40 : MAC_ADDR0 */
#define EMAC_MAC_ADDR0_OFFSET (0x40)
#define EMAC_MAC_B5 EMAC_MAC_B5
#define EMAC_MAC_B5_POS (0U)
#define EMAC_MAC_B5_LEN (8U)
#define EMAC_MAC_B5_MSK (((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS)
#define EMAC_MAC_B5_UMSK (~(((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS))
#define EMAC_MAC_B4 EMAC_MAC_B4
#define EMAC_MAC_B4_POS (8U)
#define EMAC_MAC_B4_LEN (8U)
#define EMAC_MAC_B4_MSK (((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS)
#define EMAC_MAC_B4_UMSK (~(((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS))
#define EMAC_MAC_B3 EMAC_MAC_B3
#define EMAC_MAC_B3_POS (16U)
#define EMAC_MAC_B3_LEN (8U)
#define EMAC_MAC_B3_MSK (((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS)
#define EMAC_MAC_B3_UMSK (~(((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS))
#define EMAC_MAC_B2 EMAC_MAC_B2
#define EMAC_MAC_B2_POS (24U)
#define EMAC_MAC_B2_LEN (8U)
#define EMAC_MAC_B2_MSK (((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS)
#define EMAC_MAC_B2_UMSK (~(((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS))
/* 0x44 : MAC_ADDR1 */
#define EMAC_MAC_ADDR1_OFFSET (0x44)
#define EMAC_MAC_B1 EMAC_MAC_B1
#define EMAC_MAC_B1_POS (0U)
#define EMAC_MAC_B1_LEN (8U)
#define EMAC_MAC_B1_MSK (((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS)
#define EMAC_MAC_B1_UMSK (~(((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS))
#define EMAC_MAC_B0 EMAC_MAC_B0
#define EMAC_MAC_B0_POS (8U)
#define EMAC_MAC_B0_LEN (8U)
#define EMAC_MAC_B0_MSK (((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS)
#define EMAC_MAC_B0_UMSK (~(((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS))
/* 0x48 : HASH0_ADDR */
#define EMAC_HASH0_ADDR_OFFSET (0x48)
#define EMAC_HASH0 EMAC_HASH0
#define EMAC_HASH0_POS (0U)
#define EMAC_HASH0_LEN (32U)
#define EMAC_HASH0_MSK (((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS)
#define EMAC_HASH0_UMSK (~(((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS))
/* 0x4C : HASH1_ADDR */
#define EMAC_HASH1_ADDR_OFFSET (0x4C)
#define EMAC_HASH1 EMAC_HASH1
#define EMAC_HASH1_POS (0U)
#define EMAC_HASH1_LEN (32U)
#define EMAC_HASH1_MSK (((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS)
#define EMAC_HASH1_UMSK (~(((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS))
/* 0x50 : TXCTRL */
#define EMAC_TXCTRL_OFFSET (0x50)
#define EMAC_TXPAUSETV EMAC_TXPAUSETV
#define EMAC_TXPAUSETV_POS (0U)
#define EMAC_TXPAUSETV_LEN (16U)
#define EMAC_TXPAUSETV_MSK (((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS)
#define EMAC_TXPAUSETV_UMSK (~(((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS))
#define EMAC_TXPAUSERQ EMAC_TXPAUSERQ
#define EMAC_TXPAUSERQ_POS (16U)
#define EMAC_TXPAUSERQ_LEN (1U)
#define EMAC_TXPAUSERQ_MSK (((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS)
#define EMAC_TXPAUSERQ_UMSK (~(((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS))
struct emac_reg {
/* 0x0 : MODE */
union {
struct
{
uint32_t RXEN : 1; /* [ 0], r/w, 0x0 */
uint32_t TXEN : 1; /* [ 1], r/w, 0x0 */
uint32_t NOPRE : 1; /* [ 2], r/w, 0x0 */
uint32_t BRO : 1; /* [ 3], r/w, 0x1 */
uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */
uint32_t PRO : 1; /* [ 5], r/w, 0x0 */
uint32_t IFG : 1; /* [ 6], r/w, 0x0 */
uint32_t rsvd_9_7 : 3; /* [ 9: 7], rsvd, 0x0 */
uint32_t FULLD : 1; /* [ 10], r/w, 0x0 */
uint32_t rsvd_12_11 : 2; /* [12:11], rsvd, 0x0 */
uint32_t CRCEN : 1; /* [ 13], r/w, 0x1 */
uint32_t HUGEN : 1; /* [ 14], r/w, 0x0 */
uint32_t PAD : 1; /* [ 15], r/w, 0x1 */
uint32_t RECSMALL : 1; /* [ 16], r/w, 0x0 */
uint32_t RMII_EN : 1; /* [ 17], r/w, 0x0 */
uint32_t rsvd_23_18 : 6; /* [23:18], rsvd, 0x0 */
uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
} BF;
uint32_t WORD;
} MODE;
/* 0x4 : INT_SOURCE */
union {
struct
{
uint32_t TXB : 1; /* [ 0], r/w, 0x0 */
uint32_t TXE : 1; /* [ 1], r/w, 0x0 */
uint32_t RXB : 1; /* [ 2], r/w, 0x0 */
uint32_t RXE : 1; /* [ 3], r/w, 0x0 */
uint32_t BUSY : 1; /* [ 4], r/w, 0x0 */
uint32_t TXC : 1; /* [ 5], r/w, 0x0 */
uint32_t RXC : 1; /* [ 6], r/w, 0x0 */
uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */
} BF;
uint32_t WORD;
} INT_SOURCE;
/* 0x8 : INT_MASK */
union {
struct
{
uint32_t TXB_M : 1; /* [ 0], r/w, 0x1 */
uint32_t TXE_M : 1; /* [ 1], r/w, 0x1 */
uint32_t RXB_M : 1; /* [ 2], r/w, 0x1 */
uint32_t RXE_M : 1; /* [ 3], r/w, 0x1 */
uint32_t BUSY_M : 1; /* [ 4], r/w, 0x1 */
uint32_t TXC_M : 1; /* [ 5], r/w, 0x1 */
uint32_t RXC_M : 1; /* [ 6], r/w, 0x1 */
uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */
} BF;
uint32_t WORD;
} INT_MASK;
/* 0xC : IPGT */
union {
struct
{
uint32_t IPGT : 7; /* [ 6: 0], r/w, 0x18 */
uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */
} BF;
uint32_t WORD;
} IPGT;
/* 0x10 reserved */
uint8_t RESERVED0x10[8];
/* 0x18 : PACKETLEN */
union {
struct
{
uint32_t MAXFL : 16; /* [15: 0], r/w, 0x600 */
uint32_t MINFL : 16; /* [31:16], r/w, 0x40 */
} BF;
uint32_t WORD;
} PACKETLEN;
/* 0x1C : COLLCONFIG */
union {
struct
{
uint32_t COLLVALID : 6; /* [ 5: 0], r/w, 0x3f */
uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
uint32_t MAXRET : 4; /* [19:16], r/w, 0xf */
uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
} BF;
uint32_t WORD;
} COLLCONFIG;
/* 0x20 : TX_BD_NUM */
union {
struct
{
uint32_t TXBDNUM : 8; /* [ 7: 0], r/w, 0x40 */
uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */
uint32_t TXBDPTR : 7; /* [22:16], r, 0x0 */
uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
uint32_t RXBDPTR : 7; /* [30:24], r, 0x0 */
uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TX_BD_NUM;
/* 0x24 reserved */
uint8_t RESERVED0x24[4];
/* 0x28 : MIIMODE */
union {
struct
{
uint32_t CLKDIV : 8; /* [ 7: 0], r/w, 0x64 */
uint32_t MIINOPRE : 1; /* [ 8], r/w, 0x0 */
uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
} BF;
uint32_t WORD;
} MIIMODE;
/* 0x2C : MIICOMMAND */
union {
struct
{
uint32_t SCANSTAT : 1; /* [ 0], r/w, 0x0 */
uint32_t RSTAT : 1; /* [ 1], r/w, 0x0 */
uint32_t WCTRLDATA : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} MIICOMMAND;
/* 0x30 : MIIADDRESS */
union {
struct
{
uint32_t FIAD : 5; /* [ 4: 0], r/w, 0x0 */
uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
uint32_t RGAD : 5; /* [12: 8], r/w, 0x0 */
uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
} BF;
uint32_t WORD;
} MIIADDRESS;
/* 0x34 : MIITX_DATA */
union {
struct
{
uint32_t CTRLDATA : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} MIITX_DATA;
/* 0x38 : MIIRX_DATA */
union {
struct
{
uint32_t PRSD : 16; /* [15: 0], r, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} MIIRX_DATA;
/* 0x3C : MIISTATUS */
union {
struct
{
uint32_t MIIM_LINKFAIL : 1; /* [ 0], r, 0x0 */
uint32_t MIIM_BUSY : 1; /* [ 1], r, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
} BF;
uint32_t WORD;
} MIISTATUS;
/* 0x40 : MAC_ADDR0 */
union {
struct
{
uint32_t MAC_B5 : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t MAC_B4 : 8; /* [15: 8], r/w, 0x0 */
uint32_t MAC_B3 : 8; /* [23:16], r/w, 0x0 */
uint32_t MAC_B2 : 8; /* [31:24], r/w, 0x0 */
} BF;
uint32_t WORD;
} MAC_ADDR0;
/* 0x44 : MAC_ADDR1 */
union {
struct
{
uint32_t MAC_B1 : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t MAC_B0 : 8; /* [15: 8], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} MAC_ADDR1;
/* 0x48 : HASH0_ADDR */
union {
struct
{
uint32_t HASH0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} HASH0_ADDR;
/* 0x4C : HASH1_ADDR */
union {
struct
{
uint32_t HASH1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} HASH1_ADDR;
/* 0x50 : TXCTRL */
union {
struct
{
uint32_t TXPAUSETV : 16; /* [15: 0], r/w, 0x0 */
uint32_t TXPAUSERQ : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TXCTRL;
};
typedef volatile struct emac_reg emac_reg_t;
#endif /* __EMAC_REG_H__ */

5498
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/glb_reg.h
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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/gpip_reg.h
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@@ -1,317 +0,0 @@
/**
******************************************************************************
* @file gpip_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __GPIP_REG_H__
#define __GPIP_REG_H__
#include "bl702.h"
/* 0x0 : gpadc_config */
#define GPIP_GPADC_CONFIG_OFFSET (0x0)
#define GPIP_GPADC_DMA_EN GPIP_GPADC_DMA_EN
#define GPIP_GPADC_DMA_EN_POS (0U)
#define GPIP_GPADC_DMA_EN_LEN (1U)
#define GPIP_GPADC_DMA_EN_MSK (((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS)
#define GPIP_GPADC_DMA_EN_UMSK (~(((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS))
#define GPIP_GPADC_FIFO_CLR GPIP_GPADC_FIFO_CLR
#define GPIP_GPADC_FIFO_CLR_POS (1U)
#define GPIP_GPADC_FIFO_CLR_LEN (1U)
#define GPIP_GPADC_FIFO_CLR_MSK (((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS)
#define GPIP_GPADC_FIFO_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS))
#define GPIP_GPADC_FIFO_NE GPIP_GPADC_FIFO_NE
#define GPIP_GPADC_FIFO_NE_POS (2U)
#define GPIP_GPADC_FIFO_NE_LEN (1U)
#define GPIP_GPADC_FIFO_NE_MSK (((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS)
#define GPIP_GPADC_FIFO_NE_UMSK (~(((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS))
#define GPIP_GPADC_FIFO_FULL GPIP_GPADC_FIFO_FULL
#define GPIP_GPADC_FIFO_FULL_POS (3U)
#define GPIP_GPADC_FIFO_FULL_LEN (1U)
#define GPIP_GPADC_FIFO_FULL_MSK (((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS)
#define GPIP_GPADC_FIFO_FULL_UMSK (~(((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS))
#define GPIP_GPADC_RDY GPIP_GPADC_RDY
#define GPIP_GPADC_RDY_POS (4U)
#define GPIP_GPADC_RDY_LEN (1U)
#define GPIP_GPADC_RDY_MSK (((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS)
#define GPIP_GPADC_RDY_UMSK (~(((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS))
#define GPIP_GPADC_FIFO_OVERRUN GPIP_GPADC_FIFO_OVERRUN
#define GPIP_GPADC_FIFO_OVERRUN_POS (5U)
#define GPIP_GPADC_FIFO_OVERRUN_LEN (1U)
#define GPIP_GPADC_FIFO_OVERRUN_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS)
#define GPIP_GPADC_FIFO_OVERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS))
#define GPIP_GPADC_FIFO_UNDERRUN GPIP_GPADC_FIFO_UNDERRUN
#define GPIP_GPADC_FIFO_UNDERRUN_POS (6U)
#define GPIP_GPADC_FIFO_UNDERRUN_LEN (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS))
#define GPIP_GPADC_FIFO_RDY GPIP_GPADC_FIFO_RDY
#define GPIP_GPADC_FIFO_RDY_POS (7U)
#define GPIP_GPADC_FIFO_RDY_LEN (1U)
#define GPIP_GPADC_FIFO_RDY_MSK (((1U << GPIP_GPADC_FIFO_RDY_LEN) - 1) << GPIP_GPADC_FIFO_RDY_POS)
#define GPIP_GPADC_FIFO_RDY_UMSK (~(((1U << GPIP_GPADC_FIFO_RDY_LEN) - 1) << GPIP_GPADC_FIFO_RDY_POS))
#define GPIP_GPADC_RDY_CLR GPIP_GPADC_RDY_CLR
#define GPIP_GPADC_RDY_CLR_POS (8U)
#define GPIP_GPADC_RDY_CLR_LEN (1U)
#define GPIP_GPADC_RDY_CLR_MSK (((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS)
#define GPIP_GPADC_RDY_CLR_UMSK (~(((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS))
#define GPIP_GPADC_FIFO_OVERRUN_CLR GPIP_GPADC_FIFO_OVERRUN_CLR
#define GPIP_GPADC_FIFO_OVERRUN_CLR_POS (9U)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_LEN (1U)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS))
#define GPIP_GPADC_FIFO_UNDERRUN_CLR GPIP_GPADC_FIFO_UNDERRUN_CLR
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_POS (10U)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS))
#define GPIP_GPADC_RDY_MASK GPIP_GPADC_RDY_MASK
#define GPIP_GPADC_RDY_MASK_POS (12U)
#define GPIP_GPADC_RDY_MASK_LEN (1U)
#define GPIP_GPADC_RDY_MASK_MSK (((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS)
#define GPIP_GPADC_RDY_MASK_UMSK (~(((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS))
#define GPIP_GPADC_FIFO_OVERRUN_MASK GPIP_GPADC_FIFO_OVERRUN_MASK
#define GPIP_GPADC_FIFO_OVERRUN_MASK_POS (13U)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_LEN (1U)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS))
#define GPIP_GPADC_FIFO_UNDERRUN_MASK GPIP_GPADC_FIFO_UNDERRUN_MASK
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_POS (14U)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS))
#define GPIP_GPADC_FIFO_RDY_MASK GPIP_GPADC_FIFO_RDY_MASK
#define GPIP_GPADC_FIFO_RDY_MASK_POS (15U)
#define GPIP_GPADC_FIFO_RDY_MASK_LEN (1U)
#define GPIP_GPADC_FIFO_RDY_MASK_MSK (((1U << GPIP_GPADC_FIFO_RDY_MASK_LEN) - 1) << GPIP_GPADC_FIFO_RDY_MASK_POS)
#define GPIP_GPADC_FIFO_RDY_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_RDY_MASK_LEN) - 1) << GPIP_GPADC_FIFO_RDY_MASK_POS))
#define GPIP_GPADC_FIFO_DATA_COUNT GPIP_GPADC_FIFO_DATA_COUNT
#define GPIP_GPADC_FIFO_DATA_COUNT_POS (16U)
#define GPIP_GPADC_FIFO_DATA_COUNT_LEN (6U)
#define GPIP_GPADC_FIFO_DATA_COUNT_MSK (((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS)
#define GPIP_GPADC_FIFO_DATA_COUNT_UMSK (~(((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS))
#define GPIP_GPADC_FIFO_THL GPIP_GPADC_FIFO_THL
#define GPIP_GPADC_FIFO_THL_POS (22U)
#define GPIP_GPADC_FIFO_THL_LEN (2U)
#define GPIP_GPADC_FIFO_THL_MSK (((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS)
#define GPIP_GPADC_FIFO_THL_UMSK (~(((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS))
/* 0x4 : gpadc_dma_rdata */
#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4)
#define GPIP_GPADC_DMA_RDATA GPIP_GPADC_DMA_RDATA
#define GPIP_GPADC_DMA_RDATA_POS (0U)
#define GPIP_GPADC_DMA_RDATA_LEN (26U)
#define GPIP_GPADC_DMA_RDATA_MSK (((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS)
#define GPIP_GPADC_DMA_RDATA_UMSK (~(((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS))
/* 0x40 : gpdac_config */
#define GPIP_GPDAC_CONFIG_OFFSET (0x40)
#define GPIP_GPDAC_EN GPIP_GPDAC_EN
#define GPIP_GPDAC_EN_POS (0U)
#define GPIP_GPDAC_EN_LEN (1U)
#define GPIP_GPDAC_EN_MSK (((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS)
#define GPIP_GPDAC_EN_UMSK (~(((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS))
#define GPIP_GPDAC_EN2 GPIP_GPDAC_EN2
#define GPIP_GPDAC_EN2_POS (1U)
#define GPIP_GPDAC_EN2_LEN (1U)
#define GPIP_GPDAC_EN2_MSK (((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS)
#define GPIP_GPDAC_EN2_UMSK (~(((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS))
#define GPIP_DSM_MODE GPIP_DSM_MODE
#define GPIP_DSM_MODE_POS (4U)
#define GPIP_DSM_MODE_LEN (2U)
#define GPIP_DSM_MODE_MSK (((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS)
#define GPIP_DSM_MODE_UMSK (~(((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS))
#define GPIP_GPDAC_MODE GPIP_GPDAC_MODE
#define GPIP_GPDAC_MODE_POS (8U)
#define GPIP_GPDAC_MODE_LEN (3U)
#define GPIP_GPDAC_MODE_MSK (((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS)
#define GPIP_GPDAC_MODE_UMSK (~(((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS))
#define GPIP_GPDAC_CH_A_SEL GPIP_GPDAC_CH_A_SEL
#define GPIP_GPDAC_CH_A_SEL_POS (16U)
#define GPIP_GPDAC_CH_A_SEL_LEN (4U)
#define GPIP_GPDAC_CH_A_SEL_MSK (((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS)
#define GPIP_GPDAC_CH_A_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS))
#define GPIP_GPDAC_CH_B_SEL GPIP_GPDAC_CH_B_SEL
#define GPIP_GPDAC_CH_B_SEL_POS (20U)
#define GPIP_GPDAC_CH_B_SEL_LEN (4U)
#define GPIP_GPDAC_CH_B_SEL_MSK (((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS)
#define GPIP_GPDAC_CH_B_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS))
/* 0x44 : gpdac_dma_config */
#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44)
#define GPIP_GPDAC_DMA_TX_EN GPIP_GPDAC_DMA_TX_EN
#define GPIP_GPDAC_DMA_TX_EN_POS (0U)
#define GPIP_GPDAC_DMA_TX_EN_LEN (1U)
#define GPIP_GPDAC_DMA_TX_EN_MSK (((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS)
#define GPIP_GPDAC_DMA_TX_EN_UMSK (~(((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS))
#define GPIP_GPDAC_DMA_FORMAT GPIP_GPDAC_DMA_FORMAT
#define GPIP_GPDAC_DMA_FORMAT_POS (4U)
#define GPIP_GPDAC_DMA_FORMAT_LEN (2U)
#define GPIP_GPDAC_DMA_FORMAT_MSK (((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS)
#define GPIP_GPDAC_DMA_FORMAT_UMSK (~(((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS))
/* 0x48 : gpdac_dma_wdata */
#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48)
#define GPIP_GPDAC_DMA_WDATA GPIP_GPDAC_DMA_WDATA
#define GPIP_GPDAC_DMA_WDATA_POS (0U)
#define GPIP_GPDAC_DMA_WDATA_LEN (32U)
#define GPIP_GPDAC_DMA_WDATA_MSK (((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS)
#define GPIP_GPDAC_DMA_WDATA_UMSK (~(((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS))
/* 0x4C : gpdac_tx_fifo_status */
#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C)
#define GPIP_TX_FIFO_EMPTY GPIP_TX_FIFO_EMPTY
#define GPIP_TX_FIFO_EMPTY_POS (0U)
#define GPIP_TX_FIFO_EMPTY_LEN (1U)
#define GPIP_TX_FIFO_EMPTY_MSK (((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS)
#define GPIP_TX_FIFO_EMPTY_UMSK (~(((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS))
#define GPIP_TX_FIFO_FULL GPIP_TX_FIFO_FULL
#define GPIP_TX_FIFO_FULL_POS (1U)
#define GPIP_TX_FIFO_FULL_LEN (1U)
#define GPIP_TX_FIFO_FULL_MSK (((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS)
#define GPIP_TX_FIFO_FULL_UMSK (~(((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS))
#define GPIP_TX_CS GPIP_TX_CS
#define GPIP_TX_CS_POS (2U)
#define GPIP_TX_CS_LEN (2U)
#define GPIP_TX_CS_MSK (((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS)
#define GPIP_TX_CS_UMSK (~(((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS))
#define GPIP_TXFIFORDPTR GPIP_TXFIFORDPTR
#define GPIP_TXFIFORDPTR_POS (4U)
#define GPIP_TXFIFORDPTR_LEN (3U)
#define GPIP_TXFIFORDPTR_MSK (((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS)
#define GPIP_TXFIFORDPTR_UMSK (~(((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS))
#define GPIP_TXFIFOWRPTR GPIP_TXFIFOWRPTR
#define GPIP_TXFIFOWRPTR_POS (8U)
#define GPIP_TXFIFOWRPTR_LEN (2U)
#define GPIP_TXFIFOWRPTR_MSK (((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS)
#define GPIP_TXFIFOWRPTR_UMSK (~(((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS))
struct gpip_reg {
/* 0x0 : gpadc_config */
union {
struct
{
uint32_t gpadc_dma_en : 1; /* [ 0], r/w, 0x0 */
uint32_t gpadc_fifo_clr : 1; /* [ 1], w1c, 0x0 */
uint32_t gpadc_fifo_ne : 1; /* [ 2], r, 0x0 */
uint32_t gpadc_fifo_full : 1; /* [ 3], r, 0x0 */
uint32_t gpadc_rdy : 1; /* [ 4], r, 0x0 */
uint32_t gpadc_fifo_overrun : 1; /* [ 5], r, 0x0 */
uint32_t gpadc_fifo_underrun : 1; /* [ 6], r, 0x0 */
uint32_t gpadc_fifo_rdy : 1; /* [ 7], r, 0x0 */
uint32_t gpadc_rdy_clr : 1; /* [ 8], w1c, 0x0 */
uint32_t gpadc_fifo_overrun_clr : 1; /* [ 9], w1c, 0x0 */
uint32_t gpadc_fifo_underrun_clr : 1; /* [ 10], w1c, 0x0 */
uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
uint32_t gpadc_rdy_mask : 1; /* [ 12], r/w, 0x0 */
uint32_t gpadc_fifo_overrun_mask : 1; /* [ 13], r/w, 0x0 */
uint32_t gpadc_fifo_underrun_mask : 1; /* [ 14], r/w, 0x0 */
uint32_t gpadc_fifo_rdy_mask : 1; /* [ 15], r/w, 0x1 */
uint32_t gpadc_fifo_data_count : 6; /* [21:16], r, 0x0 */
uint32_t gpadc_fifo_thl : 2; /* [23:22], r/w, 0x0 */
uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0x0 */
} BF;
uint32_t WORD;
} gpadc_config;
/* 0x4 : gpadc_dma_rdata */
union {
struct
{
uint32_t gpadc_dma_rdata : 26; /* [25: 0], r, 0x0 */
uint32_t rsvd_31_26 : 6; /* [31:26], rsvd, 0x0 */
} BF;
uint32_t WORD;
} gpadc_dma_rdata;
/* 0x8 reserved */
uint8_t RESERVED0x8[56];
/* 0x40 : gpdac_config */
union {
struct
{
uint32_t gpdac_en : 1; /* [ 0], r/w, 0x0 */
uint32_t gpdac_en2 : 1; /* [ 1], r/w, 0x0 */
uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
uint32_t dsm_mode : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t gpdac_mode : 3; /* [10: 8], r/w, 0x0 */
uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
uint32_t gpdac_ch_a_sel : 4; /* [19:16], r/w, 0x0 */
uint32_t gpdac_ch_b_sel : 4; /* [23:20], r/w, 0x0 */
uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0xd */
} BF;
uint32_t WORD;
} gpdac_config;
/* 0x44 : gpdac_dma_config */
union {
struct
{
uint32_t gpdac_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
uint32_t gpdac_dma_format : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
} BF;
uint32_t WORD;
} gpdac_dma_config;
/* 0x48 : gpdac_dma_wdata */
union {
struct
{
uint32_t gpdac_dma_wdata : 32; /* [31: 0], w, x */
} BF;
uint32_t WORD;
} gpdac_dma_wdata;
/* 0x4C : gpdac_tx_fifo_status */
union {
struct
{
uint32_t tx_fifo_empty : 1; /* [ 0], r, 0x0 */
uint32_t tx_fifo_full : 1; /* [ 1], r, 0x0 */
uint32_t tx_cs : 2; /* [ 3: 2], r, 0x0 */
uint32_t TxFifoRdPtr : 3; /* [ 6: 4], r, 0x4 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t TxFifoWrPtr : 2; /* [ 9: 8], r, 0x0 */
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
} BF;
uint32_t WORD;
} gpdac_tx_fifo_status;
};
typedef volatile struct gpip_reg gpip_reg_t;
#endif /* __GPIP_REG_H__ */

814
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/hbn_reg.h
View File

@@ -1,814 +0,0 @@
/**
******************************************************************************
* @file hbn_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HBN_REG_H__
#define __HBN_REG_H__
#include "bl702.h"
/* 0x0 : HBN_CTL */
#define HBN_CTL_OFFSET (0x0)
#define HBN_RTC_CTL HBN_RTC_CTL
#define HBN_RTC_CTL_POS (0U)
#define HBN_RTC_CTL_LEN (7U)
#define HBN_RTC_CTL_MSK (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)
#define HBN_RTC_CTL_UMSK (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS))
#define HBN_MODE HBN_MODE
#define HBN_MODE_POS (7U)
#define HBN_MODE_LEN (1U)
#define HBN_MODE_MSK (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)
#define HBN_MODE_UMSK (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS))
#define HBN_TRAP_MODE HBN_TRAP_MODE
#define HBN_TRAP_MODE_POS (8U)
#define HBN_TRAP_MODE_LEN (1U)
#define HBN_TRAP_MODE_MSK (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)
#define HBN_TRAP_MODE_UMSK (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS))
#define HBN_PWRDN_HBN_CORE HBN_PWRDN_HBN_CORE
#define HBN_PWRDN_HBN_CORE_POS (9U)
#define HBN_PWRDN_HBN_CORE_LEN (1U)
#define HBN_PWRDN_HBN_CORE_MSK (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)
#define HBN_PWRDN_HBN_CORE_UMSK (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS))
#define HBN_PWRDN_HBN_RTC HBN_PWRDN_HBN_RTC
#define HBN_PWRDN_HBN_RTC_POS (11U)
#define HBN_PWRDN_HBN_RTC_LEN (1U)
#define HBN_PWRDN_HBN_RTC_MSK (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)
#define HBN_PWRDN_HBN_RTC_UMSK (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS))
#define HBN_SW_RST HBN_SW_RST
#define HBN_SW_RST_POS (12U)
#define HBN_SW_RST_LEN (1U)
#define HBN_SW_RST_MSK (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)
#define HBN_SW_RST_UMSK (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS))
#define HBN_DIS_PWR_OFF_LDO11 HBN_DIS_PWR_OFF_LDO11
#define HBN_DIS_PWR_OFF_LDO11_POS (13U)
#define HBN_DIS_PWR_OFF_LDO11_LEN (1U)
#define HBN_DIS_PWR_OFF_LDO11_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)
#define HBN_DIS_PWR_OFF_LDO11_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS))
#define HBN_DIS_PWR_OFF_LDO11_RT HBN_DIS_PWR_OFF_LDO11_RT
#define HBN_DIS_PWR_OFF_LDO11_RT_POS (14U)
#define HBN_DIS_PWR_OFF_LDO11_RT_LEN (1U)
#define HBN_DIS_PWR_OFF_LDO11_RT_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)
#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS))
#define HBN_LDO11_RT_VOUT_SEL HBN_LDO11_RT_VOUT_SEL
#define HBN_LDO11_RT_VOUT_SEL_POS (15U)
#define HBN_LDO11_RT_VOUT_SEL_LEN (4U)
#define HBN_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)
#define HBN_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS))
#define HBN_LDO11_AON_VOUT_SEL HBN_LDO11_AON_VOUT_SEL
#define HBN_LDO11_AON_VOUT_SEL_POS (19U)
#define HBN_LDO11_AON_VOUT_SEL_LEN (4U)
#define HBN_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)
#define HBN_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS))
#define HBN_PU_DCDC18_AON HBN_PU_DCDC18_AON
#define HBN_PU_DCDC18_AON_POS (23U)
#define HBN_PU_DCDC18_AON_LEN (1U)
#define HBN_PU_DCDC18_AON_MSK (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)
#define HBN_PU_DCDC18_AON_UMSK (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS))
#define HBN_RTC_DLY_OPTION HBN_RTC_DLY_OPTION
#define HBN_RTC_DLY_OPTION_POS (24U)
#define HBN_RTC_DLY_OPTION_LEN (1U)
#define HBN_RTC_DLY_OPTION_MSK (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)
#define HBN_RTC_DLY_OPTION_UMSK (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS))
#define HBN_PWR_ON_OPTION HBN_PWR_ON_OPTION
#define HBN_PWR_ON_OPTION_POS (25U)
#define HBN_PWR_ON_OPTION_LEN (1U)
#define HBN_PWR_ON_OPTION_MSK (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)
#define HBN_PWR_ON_OPTION_UMSK (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS))
#define HBN_SRAM_SLP_OPTION HBN_SRAM_SLP_OPTION
#define HBN_SRAM_SLP_OPTION_POS (26U)
#define HBN_SRAM_SLP_OPTION_LEN (1U)
#define HBN_SRAM_SLP_OPTION_MSK (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)
#define HBN_SRAM_SLP_OPTION_UMSK (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS))
#define HBN_SRAM_SLP HBN_SRAM_SLP
#define HBN_SRAM_SLP_POS (27U)
#define HBN_SRAM_SLP_LEN (1U)
#define HBN_SRAM_SLP_MSK (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)
#define HBN_SRAM_SLP_UMSK (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS))
#define HBN_STATE HBN_STATE
#define HBN_STATE_POS (28U)
#define HBN_STATE_LEN (4U)
#define HBN_STATE_MSK (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)
#define HBN_STATE_UMSK (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS))
/* 0x4 : HBN_TIME_L */
#define HBN_TIME_L_OFFSET (0x4)
#define HBN_TIME_L HBN_TIME_L
#define HBN_TIME_L_POS (0U)
#define HBN_TIME_L_LEN (32U)
#define HBN_TIME_L_MSK (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)
#define HBN_TIME_L_UMSK (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS))
/* 0x8 : HBN_TIME_H */
#define HBN_TIME_H_OFFSET (0x8)
#define HBN_TIME_H HBN_TIME_H
#define HBN_TIME_H_POS (0U)
#define HBN_TIME_H_LEN (8U)
#define HBN_TIME_H_MSK (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)
#define HBN_TIME_H_UMSK (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS))
/* 0xC : RTC_TIME_L */
#define HBN_RTC_TIME_L_OFFSET (0xC)
#define HBN_RTC_TIME_LATCH_L HBN_RTC_TIME_LATCH_L
#define HBN_RTC_TIME_LATCH_L_POS (0U)
#define HBN_RTC_TIME_LATCH_L_LEN (32U)
#define HBN_RTC_TIME_LATCH_L_MSK (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)
#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS))
/* 0x10 : RTC_TIME_H */
#define HBN_RTC_TIME_H_OFFSET (0x10)
#define HBN_RTC_TIME_LATCH_H HBN_RTC_TIME_LATCH_H
#define HBN_RTC_TIME_LATCH_H_POS (0U)
#define HBN_RTC_TIME_LATCH_H_LEN (8U)
#define HBN_RTC_TIME_LATCH_H_MSK (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)
#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS))
#define HBN_RTC_TIME_LATCH HBN_RTC_TIME_LATCH
#define HBN_RTC_TIME_LATCH_POS (31U)
#define HBN_RTC_TIME_LATCH_LEN (1U)
#define HBN_RTC_TIME_LATCH_MSK (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)
#define HBN_RTC_TIME_LATCH_UMSK (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS))
/* 0x14 : HBN_IRQ_MODE */
#define HBN_IRQ_MODE_OFFSET (0x14)
#define HBN_PIN_WAKEUP_MODE HBN_PIN_WAKEUP_MODE
#define HBN_PIN_WAKEUP_MODE_POS (0U)
#define HBN_PIN_WAKEUP_MODE_LEN (3U)
#define HBN_PIN_WAKEUP_MODE_MSK (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)
#define HBN_PIN_WAKEUP_MODE_UMSK (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS))
#define HBN_PIN_WAKEUP_MASK HBN_PIN_WAKEUP_MASK
#define HBN_PIN_WAKEUP_MASK_POS (3U)
#define HBN_PIN_WAKEUP_MASK_LEN (5U)
#define HBN_PIN_WAKEUP_MASK_MSK (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)
#define HBN_PIN_WAKEUP_MASK_UMSK (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS))
#define HBN_REG_AON_PAD_IE_SMT HBN_REG_AON_PAD_IE_SMT
#define HBN_REG_AON_PAD_IE_SMT_POS (8U)
#define HBN_REG_AON_PAD_IE_SMT_LEN (5U)
#define HBN_REG_AON_PAD_IE_SMT_MSK (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)
#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS))
#define HBN_REG_EN_HW_PU_PD HBN_REG_EN_HW_PU_PD
#define HBN_REG_EN_HW_PU_PD_POS (16U)
#define HBN_REG_EN_HW_PU_PD_LEN (1U)
#define HBN_REG_EN_HW_PU_PD_MSK (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)
#define HBN_REG_EN_HW_PU_PD_UMSK (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS))
#define HBN_IRQ_BOR_EN HBN_IRQ_BOR_EN
#define HBN_IRQ_BOR_EN_POS (18U)
#define HBN_IRQ_BOR_EN_LEN (1U)
#define HBN_IRQ_BOR_EN_MSK (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)
#define HBN_IRQ_BOR_EN_UMSK (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS))
#define HBN_IRQ_ACOMP0_EN HBN_IRQ_ACOMP0_EN
#define HBN_IRQ_ACOMP0_EN_POS (20U)
#define HBN_IRQ_ACOMP0_EN_LEN (2U)
#define HBN_IRQ_ACOMP0_EN_MSK (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)
#define HBN_IRQ_ACOMP0_EN_UMSK (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS))
#define HBN_IRQ_ACOMP1_EN HBN_IRQ_ACOMP1_EN
#define HBN_IRQ_ACOMP1_EN_POS (22U)
#define HBN_IRQ_ACOMP1_EN_LEN (2U)
#define HBN_IRQ_ACOMP1_EN_MSK (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)
#define HBN_IRQ_ACOMP1_EN_UMSK (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS))
#define HBN_PIN_WAKEUP_SEL HBN_PIN_WAKEUP_SEL
#define HBN_PIN_WAKEUP_SEL_POS (24U)
#define HBN_PIN_WAKEUP_SEL_LEN (3U)
#define HBN_PIN_WAKEUP_SEL_MSK (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)
#define HBN_PIN_WAKEUP_SEL_UMSK (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS))
#define HBN_PIN_WAKEUP_EN HBN_PIN_WAKEUP_EN
#define HBN_PIN_WAKEUP_EN_POS (27U)
#define HBN_PIN_WAKEUP_EN_LEN (1U)
#define HBN_PIN_WAKEUP_EN_MSK (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)
#define HBN_PIN_WAKEUP_EN_UMSK (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS))
/* 0x18 : HBN_IRQ_STAT */
#define HBN_IRQ_STAT_OFFSET (0x18)
#define HBN_IRQ_STAT HBN_IRQ_STAT
#define HBN_IRQ_STAT_POS (0U)
#define HBN_IRQ_STAT_LEN (32U)
#define HBN_IRQ_STAT_MSK (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)
#define HBN_IRQ_STAT_UMSK (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS))
/* 0x1C : HBN_IRQ_CLR */
#define HBN_IRQ_CLR_OFFSET (0x1C)
#define HBN_IRQ_CLR HBN_IRQ_CLR
#define HBN_IRQ_CLR_POS (0U)
#define HBN_IRQ_CLR_LEN (32U)
#define HBN_IRQ_CLR_MSK (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)
#define HBN_IRQ_CLR_UMSK (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS))
/* 0x20 : HBN_PIR_CFG */
#define HBN_PIR_CFG_OFFSET (0x20)
#define HBN_PIR_HPF_SEL HBN_PIR_HPF_SEL
#define HBN_PIR_HPF_SEL_POS (0U)
#define HBN_PIR_HPF_SEL_LEN (2U)
#define HBN_PIR_HPF_SEL_MSK (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)
#define HBN_PIR_HPF_SEL_UMSK (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS))
#define HBN_PIR_LPF_SEL HBN_PIR_LPF_SEL
#define HBN_PIR_LPF_SEL_POS (2U)
#define HBN_PIR_LPF_SEL_LEN (1U)
#define HBN_PIR_LPF_SEL_MSK (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)
#define HBN_PIR_LPF_SEL_UMSK (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS))
#define HBN_PIR_DIS HBN_PIR_DIS
#define HBN_PIR_DIS_POS (4U)
#define HBN_PIR_DIS_LEN (2U)
#define HBN_PIR_DIS_MSK (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)
#define HBN_PIR_DIS_UMSK (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS))
#define HBN_PIR_EN HBN_PIR_EN
#define HBN_PIR_EN_POS (7U)
#define HBN_PIR_EN_LEN (1U)
#define HBN_PIR_EN_MSK (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)
#define HBN_PIR_EN_UMSK (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS))
#define HBN_GPADC_CGEN HBN_GPADC_CGEN
#define HBN_GPADC_CGEN_POS (8U)
#define HBN_GPADC_CGEN_LEN (1U)
#define HBN_GPADC_CGEN_MSK (((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)
#define HBN_GPADC_CGEN_UMSK (~(((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS))
#define HBN_GPADC_NOSYNC HBN_GPADC_NOSYNC
#define HBN_GPADC_NOSYNC_POS (9U)
#define HBN_GPADC_NOSYNC_LEN (1U)
#define HBN_GPADC_NOSYNC_MSK (((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)
#define HBN_GPADC_NOSYNC_UMSK (~(((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS))
/* 0x24 : HBN_PIR_VTH */
#define HBN_PIR_VTH_OFFSET (0x24)
#define HBN_PIR_VTH HBN_PIR_VTH
#define HBN_PIR_VTH_POS (0U)
#define HBN_PIR_VTH_LEN (14U)
#define HBN_PIR_VTH_MSK (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)
#define HBN_PIR_VTH_UMSK (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS))
/* 0x28 : HBN_PIR_INTERVAL */
#define HBN_PIR_INTERVAL_OFFSET (0x28)
#define HBN_PIR_INTERVAL HBN_PIR_INTERVAL
#define HBN_PIR_INTERVAL_POS (0U)
#define HBN_PIR_INTERVAL_LEN (12U)
#define HBN_PIR_INTERVAL_MSK (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)
#define HBN_PIR_INTERVAL_UMSK (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS))
/* 0x2C : HBN_MISC */
#define HBN_MISC_OFFSET (0x2C)
#define HBN_BOR_SEL HBN_BOR_SEL
#define HBN_BOR_SEL_POS (0U)
#define HBN_BOR_SEL_LEN (1U)
#define HBN_BOR_SEL_MSK (((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)
#define HBN_BOR_SEL_UMSK (~(((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS))
#define HBN_BOR_VTH HBN_BOR_VTH
#define HBN_BOR_VTH_POS (1U)
#define HBN_BOR_VTH_LEN (1U)
#define HBN_BOR_VTH_MSK (((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)
#define HBN_BOR_VTH_UMSK (~(((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS))
#define HBN_PU_BOR HBN_PU_BOR
#define HBN_PU_BOR_POS (2U)
#define HBN_PU_BOR_LEN (1U)
#define HBN_PU_BOR_MSK (((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)
#define HBN_PU_BOR_UMSK (~(((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS))
#define HBN_R_BOR_OUT HBN_R_BOR_OUT
#define HBN_R_BOR_OUT_POS (3U)
#define HBN_R_BOR_OUT_LEN (1U)
#define HBN_R_BOR_OUT_MSK (((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)
#define HBN_R_BOR_OUT_UMSK (~(((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS))
#define HBN_FLASH_PULLUP_AON HBN_FLASH_PULLUP_AON
#define HBN_FLASH_PULLUP_AON_POS (16U)
#define HBN_FLASH_PULLUP_AON_LEN (6U)
#define HBN_FLASH_PULLUP_AON_MSK (((1U << HBN_FLASH_PULLUP_AON_LEN) - 1) << HBN_FLASH_PULLUP_AON_POS)
#define HBN_FLASH_PULLUP_AON_UMSK (~(((1U << HBN_FLASH_PULLUP_AON_LEN) - 1) << HBN_FLASH_PULLUP_AON_POS))
#define HBN_FLASH_PULLDOWN_AON HBN_FLASH_PULLDOWN_AON
#define HBN_FLASH_PULLDOWN_AON_POS (24U)
#define HBN_FLASH_PULLDOWN_AON_LEN (6U)
#define HBN_FLASH_PULLDOWN_AON_MSK (((1U << HBN_FLASH_PULLDOWN_AON_LEN) - 1) << HBN_FLASH_PULLDOWN_AON_POS)
#define HBN_FLASH_PULLDOWN_AON_UMSK (~(((1U << HBN_FLASH_PULLDOWN_AON_LEN) - 1) << HBN_FLASH_PULLDOWN_AON_POS))
/* 0x30 : HBN_GLB */
#define HBN_GLB_OFFSET (0x30)
#define HBN_ROOT_CLK_SEL HBN_ROOT_CLK_SEL
#define HBN_ROOT_CLK_SEL_POS (0U)
#define HBN_ROOT_CLK_SEL_LEN (2U)
#define HBN_ROOT_CLK_SEL_MSK (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)
#define HBN_ROOT_CLK_SEL_UMSK (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS))
#define HBN_UART_CLK_SEL HBN_UART_CLK_SEL
#define HBN_UART_CLK_SEL_POS (2U)
#define HBN_UART_CLK_SEL_LEN (1U)
#define HBN_UART_CLK_SEL_MSK (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)
#define HBN_UART_CLK_SEL_UMSK (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS))
#define HBN_F32K_SEL HBN_F32K_SEL
#define HBN_F32K_SEL_POS (3U)
#define HBN_F32K_SEL_LEN (2U)
#define HBN_F32K_SEL_MSK (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)
#define HBN_F32K_SEL_UMSK (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS))
#define HBN_PU_RC32K HBN_PU_RC32K
#define HBN_PU_RC32K_POS (5U)
#define HBN_PU_RC32K_LEN (1U)
#define HBN_PU_RC32K_MSK (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)
#define HBN_PU_RC32K_UMSK (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS))
#define HBN_LDO11_RT_ILOAD_SEL HBN_LDO11_RT_ILOAD_SEL
#define HBN_LDO11_RT_ILOAD_SEL_POS (6U)
#define HBN_LDO11_RT_ILOAD_SEL_LEN (2U)
#define HBN_LDO11_RT_ILOAD_SEL_MSK (((1U << HBN_LDO11_RT_ILOAD_SEL_LEN) - 1) << HBN_LDO11_RT_ILOAD_SEL_POS)
#define HBN_LDO11_RT_ILOAD_SEL_UMSK (~(((1U << HBN_LDO11_RT_ILOAD_SEL_LEN) - 1) << HBN_LDO11_RT_ILOAD_SEL_POS))
#define HBN_RESET_EVENT HBN_RESET_EVENT
#define HBN_RESET_EVENT_POS (8U)
#define HBN_RESET_EVENT_LEN (5U)
#define HBN_RESET_EVENT_MSK (((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS)
#define HBN_RESET_EVENT_UMSK (~(((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS))
#define HBN_CLEAR_RESET_EVENT HBN_CLEAR_RESET_EVENT
#define HBN_CLEAR_RESET_EVENT_POS (13U)
#define HBN_CLEAR_RESET_EVENT_LEN (1U)
#define HBN_CLEAR_RESET_EVENT_MSK (((1U << HBN_CLEAR_RESET_EVENT_LEN) - 1) << HBN_CLEAR_RESET_EVENT_POS)
#define HBN_CLEAR_RESET_EVENT_UMSK (~(((1U << HBN_CLEAR_RESET_EVENT_LEN) - 1) << HBN_CLEAR_RESET_EVENT_POS))
#define HBN_SW_LDO11SOC_VOUT_SEL_AON HBN_SW_LDO11SOC_VOUT_SEL_AON
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS (16U)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN (4U)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS))
#define HBN_SW_LDO11_RT_VOUT_SEL HBN_SW_LDO11_RT_VOUT_SEL
#define HBN_SW_LDO11_RT_VOUT_SEL_POS (24U)
#define HBN_SW_LDO11_RT_VOUT_SEL_LEN (4U)
#define HBN_SW_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)
#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS))
#define HBN_SW_LDO11_AON_VOUT_SEL HBN_SW_LDO11_AON_VOUT_SEL
#define HBN_SW_LDO11_AON_VOUT_SEL_POS (28U)
#define HBN_SW_LDO11_AON_VOUT_SEL_LEN (4U)
#define HBN_SW_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)
#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS))
/* 0x34 : HBN_SRAM */
#define HBN_SRAM_OFFSET (0x34)
#define HBN_RETRAM_EMA HBN_RETRAM_EMA
#define HBN_RETRAM_EMA_POS (0U)
#define HBN_RETRAM_EMA_LEN (3U)
#define HBN_RETRAM_EMA_MSK (((1U << HBN_RETRAM_EMA_LEN) - 1) << HBN_RETRAM_EMA_POS)
#define HBN_RETRAM_EMA_UMSK (~(((1U << HBN_RETRAM_EMA_LEN) - 1) << HBN_RETRAM_EMA_POS))
#define HBN_RETRAM_EMAW HBN_RETRAM_EMAW
#define HBN_RETRAM_EMAW_POS (3U)
#define HBN_RETRAM_EMAW_LEN (2U)
#define HBN_RETRAM_EMAW_MSK (((1U << HBN_RETRAM_EMAW_LEN) - 1) << HBN_RETRAM_EMAW_POS)
#define HBN_RETRAM_EMAW_UMSK (~(((1U << HBN_RETRAM_EMAW_LEN) - 1) << HBN_RETRAM_EMAW_POS))
#define HBN_RETRAM_RET HBN_RETRAM_RET
#define HBN_RETRAM_RET_POS (6U)
#define HBN_RETRAM_RET_LEN (1U)
#define HBN_RETRAM_RET_MSK (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)
#define HBN_RETRAM_RET_UMSK (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS))
#define HBN_RETRAM_SLP HBN_RETRAM_SLP
#define HBN_RETRAM_SLP_POS (7U)
#define HBN_RETRAM_SLP_LEN (1U)
#define HBN_RETRAM_SLP_MSK (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)
#define HBN_RETRAM_SLP_UMSK (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS))
/* 0x100 : HBN_RSV0 */
#define HBN_RSV0_OFFSET (0x100)
#define HBN_RSV0 HBN_RSV0
#define HBN_RSV0_POS (0U)
#define HBN_RSV0_LEN (32U)
#define HBN_RSV0_MSK (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)
#define HBN_RSV0_UMSK (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS))
/* 0x104 : HBN_RSV1 */
#define HBN_RSV1_OFFSET (0x104)
#define HBN_RSV1 HBN_RSV1
#define HBN_RSV1_POS (0U)
#define HBN_RSV1_LEN (32U)
#define HBN_RSV1_MSK (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)
#define HBN_RSV1_UMSK (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS))
/* 0x108 : HBN_RSV2 */
#define HBN_RSV2_OFFSET (0x108)
#define HBN_RSV2 HBN_RSV2
#define HBN_RSV2_POS (0U)
#define HBN_RSV2_LEN (32U)
#define HBN_RSV2_MSK (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)
#define HBN_RSV2_UMSK (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS))
/* 0x10C : HBN_RSV3 */
#define HBN_RSV3_OFFSET (0x10C)
#define HBN_RSV3 HBN_RSV3
#define HBN_RSV3_POS (0U)
#define HBN_RSV3_LEN (32U)
#define HBN_RSV3_MSK (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)
#define HBN_RSV3_UMSK (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS))
/* 0x200 : rc32k_ctrl0 */
#define HBN_RC32K_CTRL0_OFFSET (0x200)
#define HBN_RC32K_CAL_DONE HBN_RC32K_CAL_DONE
#define HBN_RC32K_CAL_DONE_POS (0U)
#define HBN_RC32K_CAL_DONE_LEN (1U)
#define HBN_RC32K_CAL_DONE_MSK (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)
#define HBN_RC32K_CAL_DONE_UMSK (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS))
#define HBN_RC32K_RDY HBN_RC32K_RDY
#define HBN_RC32K_RDY_POS (1U)
#define HBN_RC32K_RDY_LEN (1U)
#define HBN_RC32K_RDY_MSK (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)
#define HBN_RC32K_RDY_UMSK (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS))
#define HBN_RC32K_CAL_INPROGRESS HBN_RC32K_CAL_INPROGRESS
#define HBN_RC32K_CAL_INPROGRESS_POS (2U)
#define HBN_RC32K_CAL_INPROGRESS_LEN (1U)
#define HBN_RC32K_CAL_INPROGRESS_MSK (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)
#define HBN_RC32K_CAL_INPROGRESS_UMSK (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS))
#define HBN_RC32K_CAL_DIV HBN_RC32K_CAL_DIV
#define HBN_RC32K_CAL_DIV_POS (3U)
#define HBN_RC32K_CAL_DIV_LEN (2U)
#define HBN_RC32K_CAL_DIV_MSK (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)
#define HBN_RC32K_CAL_DIV_UMSK (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS))
#define HBN_RC32K_CAL_PRECHARGE HBN_RC32K_CAL_PRECHARGE
#define HBN_RC32K_CAL_PRECHARGE_POS (5U)
#define HBN_RC32K_CAL_PRECHARGE_LEN (1U)
#define HBN_RC32K_CAL_PRECHARGE_MSK (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)
#define HBN_RC32K_CAL_PRECHARGE_UMSK (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS))
#define HBN_RC32K_DIG_CODE_FR_CAL HBN_RC32K_DIG_CODE_FR_CAL
#define HBN_RC32K_DIG_CODE_FR_CAL_POS (6U)
#define HBN_RC32K_DIG_CODE_FR_CAL_LEN (10U)
#define HBN_RC32K_DIG_CODE_FR_CAL_MSK (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)
#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS))
#define HBN_RC32K_VREF_DLY HBN_RC32K_VREF_DLY
#define HBN_RC32K_VREF_DLY_POS (16U)
#define HBN_RC32K_VREF_DLY_LEN (2U)
#define HBN_RC32K_VREF_DLY_MSK (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)
#define HBN_RC32K_VREF_DLY_UMSK (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS))
#define HBN_RC32K_ALLOW_CAL HBN_RC32K_ALLOW_CAL
#define HBN_RC32K_ALLOW_CAL_POS (18U)
#define HBN_RC32K_ALLOW_CAL_LEN (1U)
#define HBN_RC32K_ALLOW_CAL_MSK (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)
#define HBN_RC32K_ALLOW_CAL_UMSK (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS))
#define HBN_RC32K_EXT_CODE_EN HBN_RC32K_EXT_CODE_EN
#define HBN_RC32K_EXT_CODE_EN_POS (19U)
#define HBN_RC32K_EXT_CODE_EN_LEN (1U)
#define HBN_RC32K_EXT_CODE_EN_MSK (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)
#define HBN_RC32K_EXT_CODE_EN_UMSK (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS))
#define HBN_RC32K_CAL_EN HBN_RC32K_CAL_EN
#define HBN_RC32K_CAL_EN_POS (20U)
#define HBN_RC32K_CAL_EN_LEN (1U)
#define HBN_RC32K_CAL_EN_MSK (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)
#define HBN_RC32K_CAL_EN_UMSK (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS))
#define HBN_RC32K_CODE_FR_EXT HBN_RC32K_CODE_FR_EXT
#define HBN_RC32K_CODE_FR_EXT_POS (22U)
#define HBN_RC32K_CODE_FR_EXT_LEN (10U)
#define HBN_RC32K_CODE_FR_EXT_MSK (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)
#define HBN_RC32K_CODE_FR_EXT_UMSK (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS))
/* 0x204 : xtal32k */
#define HBN_XTAL32K_OFFSET (0x204)
#define HBN_XTAL32K_HIZ_EN HBN_XTAL32K_HIZ_EN
#define HBN_XTAL32K_HIZ_EN_POS (0U)
#define HBN_XTAL32K_HIZ_EN_LEN (1U)
#define HBN_XTAL32K_HIZ_EN_MSK (((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS)
#define HBN_XTAL32K_HIZ_EN_UMSK (~(((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS))
#define HBN_XTAL32K_LOWV_EN HBN_XTAL32K_LOWV_EN
#define HBN_XTAL32K_LOWV_EN_POS (1U)
#define HBN_XTAL32K_LOWV_EN_LEN (1U)
#define HBN_XTAL32K_LOWV_EN_MSK (((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS)
#define HBN_XTAL32K_LOWV_EN_UMSK (~(((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS))
#define HBN_XTAL32K_EXT_SEL HBN_XTAL32K_EXT_SEL
#define HBN_XTAL32K_EXT_SEL_POS (2U)
#define HBN_XTAL32K_EXT_SEL_LEN (1U)
#define HBN_XTAL32K_EXT_SEL_MSK (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)
#define HBN_XTAL32K_EXT_SEL_UMSK (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS))
#define HBN_XTAL32K_AMP_CTRL HBN_XTAL32K_AMP_CTRL
#define HBN_XTAL32K_AMP_CTRL_POS (3U)
#define HBN_XTAL32K_AMP_CTRL_LEN (2U)
#define HBN_XTAL32K_AMP_CTRL_MSK (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)
#define HBN_XTAL32K_AMP_CTRL_UMSK (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS))
#define HBN_XTAL32K_REG HBN_XTAL32K_REG
#define HBN_XTAL32K_REG_POS (5U)
#define HBN_XTAL32K_REG_LEN (2U)
#define HBN_XTAL32K_REG_MSK (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)
#define HBN_XTAL32K_REG_UMSK (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS))
#define HBN_XTAL32K_OUTBUF_STRE HBN_XTAL32K_OUTBUF_STRE
#define HBN_XTAL32K_OUTBUF_STRE_POS (7U)
#define HBN_XTAL32K_OUTBUF_STRE_LEN (1U)
#define HBN_XTAL32K_OUTBUF_STRE_MSK (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)
#define HBN_XTAL32K_OUTBUF_STRE_UMSK (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS))
#define HBN_XTAL32K_OTF_SHORT HBN_XTAL32K_OTF_SHORT
#define HBN_XTAL32K_OTF_SHORT_POS (8U)
#define HBN_XTAL32K_OTF_SHORT_LEN (1U)
#define HBN_XTAL32K_OTF_SHORT_MSK (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)
#define HBN_XTAL32K_OTF_SHORT_UMSK (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS))
#define HBN_XTAL32K_INV_STRE HBN_XTAL32K_INV_STRE
#define HBN_XTAL32K_INV_STRE_POS (9U)
#define HBN_XTAL32K_INV_STRE_LEN (2U)
#define HBN_XTAL32K_INV_STRE_MSK (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)
#define HBN_XTAL32K_INV_STRE_UMSK (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS))
#define HBN_XTAL32K_CAPBANK HBN_XTAL32K_CAPBANK
#define HBN_XTAL32K_CAPBANK_POS (11U)
#define HBN_XTAL32K_CAPBANK_LEN (6U)
#define HBN_XTAL32K_CAPBANK_MSK (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)
#define HBN_XTAL32K_CAPBANK_UMSK (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS))
#define HBN_XTAL32K_AC_CAP_SHORT HBN_XTAL32K_AC_CAP_SHORT
#define HBN_XTAL32K_AC_CAP_SHORT_POS (17U)
#define HBN_XTAL32K_AC_CAP_SHORT_LEN (1U)
#define HBN_XTAL32K_AC_CAP_SHORT_MSK (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)
#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS))
#define HBN_PU_XTAL32K_BUF HBN_PU_XTAL32K_BUF
#define HBN_PU_XTAL32K_BUF_POS (18U)
#define HBN_PU_XTAL32K_BUF_LEN (1U)
#define HBN_PU_XTAL32K_BUF_MSK (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)
#define HBN_PU_XTAL32K_BUF_UMSK (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS))
#define HBN_PU_XTAL32K HBN_PU_XTAL32K
#define HBN_PU_XTAL32K_POS (19U)
#define HBN_PU_XTAL32K_LEN (1U)
#define HBN_PU_XTAL32K_MSK (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)
#define HBN_PU_XTAL32K_UMSK (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS))
struct hbn_reg {
/* 0x0 : HBN_CTL */
union {
struct
{
uint32_t rtc_ctl : 7; /* [ 6: 0], r/w, 0x0 */
uint32_t hbn_mode : 1; /* [ 7], w, 0x0 */
uint32_t trap_mode : 1; /* [ 8], r, 0x0 */
uint32_t pwrdn_hbn_core : 1; /* [ 9], r/w, 0x0 */
uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */
uint32_t pwrdn_hbn_rtc : 1; /* [ 11], r/w, 0x0 */
uint32_t sw_rst : 1; /* [ 12], r/w, 0x0 */
uint32_t hbn_dis_pwr_off_ldo11 : 1; /* [ 13], r/w, 0x0 */
uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [ 14], r/w, 0x0 */
uint32_t hbn_ldo11_rt_vout_sel : 4; /* [18:15], r/w, 0xa */
uint32_t hbn_ldo11_aon_vout_sel : 4; /* [22:19], r/w, 0xa */
uint32_t pu_dcdc18_aon : 1; /* [ 23], r/w, 0x1 */
uint32_t rtc_dly_option : 1; /* [ 24], r/w, 0x0 */
uint32_t pwr_on_option : 1; /* [ 25], r/w, 0x0 */
uint32_t sram_slp_option : 1; /* [ 26], r/w, 0x0 */
uint32_t sram_slp : 1; /* [ 27], r, 0x0 */
uint32_t hbn_state : 4; /* [31:28], r, 0x0 */
} BF;
uint32_t WORD;
} HBN_CTL;
/* 0x4 : HBN_TIME_L */
union {
struct
{
uint32_t hbn_time_l : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} HBN_TIME_L;
/* 0x8 : HBN_TIME_H */
union {
struct
{
uint32_t hbn_time_h : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_TIME_H;
/* 0xC : RTC_TIME_L */
union {
struct
{
uint32_t rtc_time_latch_l : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} RTC_TIME_L;
/* 0x10 : RTC_TIME_H */
union {
struct
{
uint32_t rtc_time_latch_h : 8; /* [ 7: 0], r, 0x0 */
uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */
uint32_t rtc_time_latch : 1; /* [ 31], w, 0x0 */
} BF;
uint32_t WORD;
} RTC_TIME_H;
/* 0x14 : HBN_IRQ_MODE */
union {
struct
{
uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0], r/w, 0x5 */
uint32_t hbn_pin_wakeup_mask : 5; /* [ 7: 3], r/w, 0x0 */
uint32_t reg_aon_pad_ie_smt : 5; /* [12: 8], r/w, 0x1f */
uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
uint32_t reg_en_hw_pu_pd : 1; /* [ 16], r/w, 0x1 */
uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */
uint32_t irq_bor_en : 1; /* [ 18], r/w, 0x0 */
uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
uint32_t irq_acomp0_en : 2; /* [21:20], r/w, 0x0 */
uint32_t irq_acomp1_en : 2; /* [23:22], r/w, 0x0 */
uint32_t pin_wakeup_sel : 3; /* [26:24], r/w, 0x3 */
uint32_t pin_wakeup_en : 1; /* [ 27], r/w, 0x0 */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_IRQ_MODE;
/* 0x18 : HBN_IRQ_STAT */
union {
struct
{
uint32_t irq_stat : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} HBN_IRQ_STAT;
/* 0x1C : HBN_IRQ_CLR */
union {
struct
{
uint32_t irq_clr : 32; /* [31: 0], w, 0x0 */
} BF;
uint32_t WORD;
} HBN_IRQ_CLR;
/* 0x20 : HBN_PIR_CFG */
union {
struct
{
uint32_t pir_hpf_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pir_lpf_sel : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
uint32_t pir_dis : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
uint32_t pir_en : 1; /* [ 7], r/w, 0x0 */
uint32_t gpadc_cgen : 1; /* [ 8], r/w, 0x0 */
uint32_t gpadc_nosync : 1; /* [ 9], r/w, 0x0 */
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_PIR_CFG;
/* 0x24 : HBN_PIR_VTH */
union {
struct
{
uint32_t pir_vth : 14; /* [13: 0], r/w, 0x3ff */
uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_PIR_VTH;
/* 0x28 : HBN_PIR_INTERVAL */
union {
struct
{
uint32_t pir_interval : 12; /* [11: 0], r/w, 0xa3d */
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_PIR_INTERVAL;
/* 0x2C : HBN_MISC */
union {
struct
{
uint32_t bor_sel : 1; /* [ 0], r/w, 0x0 */
uint32_t bor_vth : 1; /* [ 1], r/w, 0x1 */
uint32_t pu_bor : 1; /* [ 2], r/w, 0x0 */
uint32_t r_bor_out : 1; /* [ 3], r, 0x0 */
uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */
uint32_t hbn_flash_pullup_aon : 6; /* [21:16], r/w, 0x0 */
uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
uint32_t hbn_flash_pulldown_aon : 6; /* [29:24], r/w, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_MISC;
/* 0x30 : HBN_GLB */
union {
struct
{
uint32_t hbn_root_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t hbn_uart_clk_sel : 1; /* [ 2], r/w, 0x0 */
uint32_t hbn_f32k_sel : 2; /* [ 4: 3], r/w, 0x0 */
uint32_t hbn_pu_rc32k : 1; /* [ 5], r/w, 0x1 */
uint32_t ldo11_rt_iload_sel : 2; /* [ 7: 6], r/w, 0x1 */
uint32_t hbn_reset_event : 5; /* [12: 8], r, 0x0 */
uint32_t hbn_clear_reset_event : 1; /* [ 13], r/w, 0x0 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16], r/w, 0xa */
uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
uint32_t sw_ldo11_rt_vout_sel : 4; /* [27:24], r/w, 0xa */
uint32_t sw_ldo11_aon_vout_sel : 4; /* [31:28], r/w, 0xa */
} BF;
uint32_t WORD;
} HBN_GLB;
/* 0x34 : HBN_SRAM */
union {
struct
{
uint32_t retram_ema : 3; /* [ 2: 0], r/w, 0x3 */
uint32_t retram_emaw : 2; /* [ 4: 3], r/w, 0x1 */
uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */
uint32_t retram_ret : 1; /* [ 6], r/w, 0x0 */
uint32_t retram_slp : 1; /* [ 7], r/w, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_SRAM;
/* 0x38 reserved */
uint8_t RESERVED0x38[200];
/* 0x100 : HBN_RSV0 */
union {
struct
{
uint32_t HBN_RSV0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} HBN_RSV0;
/* 0x104 : HBN_RSV1 */
union {
struct
{
uint32_t HBN_RSV1 : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} HBN_RSV1;
/* 0x108 : HBN_RSV2 */
union {
struct
{
uint32_t HBN_RSV2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} HBN_RSV2;
/* 0x10C : HBN_RSV3 */
union {
struct
{
uint32_t HBN_RSV3 : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} HBN_RSV3;
/* 0x110 reserved */
uint8_t RESERVED0x110[240];
/* 0x200 : rc32k_ctrl0 */
union {
struct
{
uint32_t rc32k_cal_done : 1; /* [ 0], r, 0x1 */
uint32_t rc32k_rdy : 1; /* [ 1], r, 0x1 */
uint32_t rc32k_cal_inprogress : 1; /* [ 2], r, 0x0 */
uint32_t rc32k_cal_div : 2; /* [ 4: 3], r/w, 0x3 */
uint32_t rc32k_cal_precharge : 1; /* [ 5], r, 0x0 */
uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6], r, 0x200 */
uint32_t rc32k_vref_dly : 2; /* [17:16], r/w, 0x0 */
uint32_t rc32k_allow_cal : 1; /* [ 18], r/w, 0x0 */
uint32_t rc32k_ext_code_en : 1; /* [ 19], r/w, 0x1 */
uint32_t rc32k_cal_en : 1; /* [ 20], r/w, 0x0 */
uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */
uint32_t rc32k_code_fr_ext : 10; /* [31:22], r/w, 0x12c */
} BF;
uint32_t WORD;
} rc32k_ctrl0;
/* 0x204 : xtal32k */
union {
struct
{
uint32_t xtal32k_hiz_en : 1; /* [ 0], r/w, 0x0 */
uint32_t xtal32k_lowv_en : 1; /* [ 1], r/w, 0x0 */
uint32_t xtal32k_ext_sel : 1; /* [ 2], r/w, 0x0 */
uint32_t xtal32k_amp_ctrl : 2; /* [ 4: 3], r/w, 0x1 */
uint32_t xtal32k_reg : 2; /* [ 6: 5], r/w, 0x1 */
uint32_t xtal32k_outbuf_stre : 1; /* [ 7], r/w, 0x0 */
uint32_t xtal32k_otf_short : 1; /* [ 8], r/w, 0x0 */
uint32_t xtal32k_inv_stre : 2; /* [10: 9], r/w, 0x1 */
uint32_t xtal32k_capbank : 6; /* [16:11], r/w, 0x20 */
uint32_t xtal32k_ac_cap_short : 1; /* [ 17], r/w, 0x1 */
uint32_t pu_xtal32k_buf : 1; /* [ 18], r/w, 0x1 */
uint32_t pu_xtal32k : 1; /* [ 19], r/w, 0x1 */
uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
} BF;
uint32_t WORD;
} xtal32k;
};
typedef volatile struct hbn_reg hbn_reg_t;
#endif /* __HBN_REG_H__ */

557
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/i2c_reg.h
View File

@@ -1,557 +0,0 @@
/**
******************************************************************************
* @file i2c_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __I2C_REG_H__
#define __I2C_REG_H__
#include "bl702.h"
/* 0x0 : i2c_config */
#define I2C_CONFIG_OFFSET (0x0)
#define I2C_CR_I2C_M_EN I2C_CR_I2C_M_EN
#define I2C_CR_I2C_M_EN_POS (0U)
#define I2C_CR_I2C_M_EN_LEN (1U)
#define I2C_CR_I2C_M_EN_MSK (((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS)
#define I2C_CR_I2C_M_EN_UMSK (~(((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS))
#define I2C_CR_I2C_PKT_DIR I2C_CR_I2C_PKT_DIR
#define I2C_CR_I2C_PKT_DIR_POS (1U)
#define I2C_CR_I2C_PKT_DIR_LEN (1U)
#define I2C_CR_I2C_PKT_DIR_MSK (((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS)
#define I2C_CR_I2C_PKT_DIR_UMSK (~(((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS))
#define I2C_CR_I2C_DEG_EN I2C_CR_I2C_DEG_EN
#define I2C_CR_I2C_DEG_EN_POS (2U)
#define I2C_CR_I2C_DEG_EN_LEN (1U)
#define I2C_CR_I2C_DEG_EN_MSK (((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS)
#define I2C_CR_I2C_DEG_EN_UMSK (~(((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS))
#define I2C_CR_I2C_SCL_SYNC_EN I2C_CR_I2C_SCL_SYNC_EN
#define I2C_CR_I2C_SCL_SYNC_EN_POS (3U)
#define I2C_CR_I2C_SCL_SYNC_EN_LEN (1U)
#define I2C_CR_I2C_SCL_SYNC_EN_MSK (((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS)
#define I2C_CR_I2C_SCL_SYNC_EN_UMSK (~(((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS))
#define I2C_CR_I2C_SUB_ADDR_EN I2C_CR_I2C_SUB_ADDR_EN
#define I2C_CR_I2C_SUB_ADDR_EN_POS (4U)
#define I2C_CR_I2C_SUB_ADDR_EN_LEN (1U)
#define I2C_CR_I2C_SUB_ADDR_EN_MSK (((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS)
#define I2C_CR_I2C_SUB_ADDR_EN_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS))
#define I2C_CR_I2C_SUB_ADDR_BC I2C_CR_I2C_SUB_ADDR_BC
#define I2C_CR_I2C_SUB_ADDR_BC_POS (5U)
#define I2C_CR_I2C_SUB_ADDR_BC_LEN (2U)
#define I2C_CR_I2C_SUB_ADDR_BC_MSK (((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS)
#define I2C_CR_I2C_SUB_ADDR_BC_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS))
#define I2C_CR_I2C_SLV_ADDR I2C_CR_I2C_SLV_ADDR
#define I2C_CR_I2C_SLV_ADDR_POS (8U)
#define I2C_CR_I2C_SLV_ADDR_LEN (7U)
#define I2C_CR_I2C_SLV_ADDR_MSK (((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS)
#define I2C_CR_I2C_SLV_ADDR_UMSK (~(((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS))
#define I2C_CR_I2C_PKT_LEN I2C_CR_I2C_PKT_LEN
#define I2C_CR_I2C_PKT_LEN_POS (16U)
#define I2C_CR_I2C_PKT_LEN_LEN (8U)
#define I2C_CR_I2C_PKT_LEN_MSK (((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS)
#define I2C_CR_I2C_PKT_LEN_UMSK (~(((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS))
#define I2C_CR_I2C_DEG_CNT I2C_CR_I2C_DEG_CNT
#define I2C_CR_I2C_DEG_CNT_POS (28U)
#define I2C_CR_I2C_DEG_CNT_LEN (4U)
#define I2C_CR_I2C_DEG_CNT_MSK (((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS)
#define I2C_CR_I2C_DEG_CNT_UMSK (~(((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS))
/* 0x4 : i2c_int_sts */
#define I2C_INT_STS_OFFSET (0x4)
#define I2C_END_INT I2C_END_INT
#define I2C_END_INT_POS (0U)
#define I2C_END_INT_LEN (1U)
#define I2C_END_INT_MSK (((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS)
#define I2C_END_INT_UMSK (~(((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS))
#define I2C_TXF_INT I2C_TXF_INT
#define I2C_TXF_INT_POS (1U)
#define I2C_TXF_INT_LEN (1U)
#define I2C_TXF_INT_MSK (((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS)
#define I2C_TXF_INT_UMSK (~(((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS))
#define I2C_RXF_INT I2C_RXF_INT
#define I2C_RXF_INT_POS (2U)
#define I2C_RXF_INT_LEN (1U)
#define I2C_RXF_INT_MSK (((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS)
#define I2C_RXF_INT_UMSK (~(((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS))
#define I2C_NAK_INT I2C_NAK_INT
#define I2C_NAK_INT_POS (3U)
#define I2C_NAK_INT_LEN (1U)
#define I2C_NAK_INT_MSK (((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS)
#define I2C_NAK_INT_UMSK (~(((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS))
#define I2C_ARB_INT I2C_ARB_INT
#define I2C_ARB_INT_POS (4U)
#define I2C_ARB_INT_LEN (1U)
#define I2C_ARB_INT_MSK (((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS)
#define I2C_ARB_INT_UMSK (~(((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS))
#define I2C_FER_INT I2C_FER_INT
#define I2C_FER_INT_POS (5U)
#define I2C_FER_INT_LEN (1U)
#define I2C_FER_INT_MSK (((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS)
#define I2C_FER_INT_UMSK (~(((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS))
#define I2C_CR_I2C_END_MASK I2C_CR_I2C_END_MASK
#define I2C_CR_I2C_END_MASK_POS (8U)
#define I2C_CR_I2C_END_MASK_LEN (1U)
#define I2C_CR_I2C_END_MASK_MSK (((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS)
#define I2C_CR_I2C_END_MASK_UMSK (~(((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS))
#define I2C_CR_I2C_TXF_MASK I2C_CR_I2C_TXF_MASK
#define I2C_CR_I2C_TXF_MASK_POS (9U)
#define I2C_CR_I2C_TXF_MASK_LEN (1U)
#define I2C_CR_I2C_TXF_MASK_MSK (((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS)
#define I2C_CR_I2C_TXF_MASK_UMSK (~(((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS))
#define I2C_CR_I2C_RXF_MASK I2C_CR_I2C_RXF_MASK
#define I2C_CR_I2C_RXF_MASK_POS (10U)
#define I2C_CR_I2C_RXF_MASK_LEN (1U)
#define I2C_CR_I2C_RXF_MASK_MSK (((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS)
#define I2C_CR_I2C_RXF_MASK_UMSK (~(((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS))
#define I2C_CR_I2C_NAK_MASK I2C_CR_I2C_NAK_MASK
#define I2C_CR_I2C_NAK_MASK_POS (11U)
#define I2C_CR_I2C_NAK_MASK_LEN (1U)
#define I2C_CR_I2C_NAK_MASK_MSK (((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS)
#define I2C_CR_I2C_NAK_MASK_UMSK (~(((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS))
#define I2C_CR_I2C_ARB_MASK I2C_CR_I2C_ARB_MASK
#define I2C_CR_I2C_ARB_MASK_POS (12U)
#define I2C_CR_I2C_ARB_MASK_LEN (1U)
#define I2C_CR_I2C_ARB_MASK_MSK (((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS)
#define I2C_CR_I2C_ARB_MASK_UMSK (~(((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS))
#define I2C_CR_I2C_FER_MASK I2C_CR_I2C_FER_MASK
#define I2C_CR_I2C_FER_MASK_POS (13U)
#define I2C_CR_I2C_FER_MASK_LEN (1U)
#define I2C_CR_I2C_FER_MASK_MSK (((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS)
#define I2C_CR_I2C_FER_MASK_UMSK (~(((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS))
#define I2C_CR_I2C_END_CLR I2C_CR_I2C_END_CLR
#define I2C_CR_I2C_END_CLR_POS (16U)
#define I2C_CR_I2C_END_CLR_LEN (1U)
#define I2C_CR_I2C_END_CLR_MSK (((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS)
#define I2C_CR_I2C_END_CLR_UMSK (~(((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS))
#define I2C_CR_I2C_NAK_CLR I2C_CR_I2C_NAK_CLR
#define I2C_CR_I2C_NAK_CLR_POS (19U)
#define I2C_CR_I2C_NAK_CLR_LEN (1U)
#define I2C_CR_I2C_NAK_CLR_MSK (((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS)
#define I2C_CR_I2C_NAK_CLR_UMSK (~(((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS))
#define I2C_CR_I2C_ARB_CLR I2C_CR_I2C_ARB_CLR
#define I2C_CR_I2C_ARB_CLR_POS (20U)
#define I2C_CR_I2C_ARB_CLR_LEN (1U)
#define I2C_CR_I2C_ARB_CLR_MSK (((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS)
#define I2C_CR_I2C_ARB_CLR_UMSK (~(((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS))
#define I2C_CR_I2C_END_EN I2C_CR_I2C_END_EN
#define I2C_CR_I2C_END_EN_POS (24U)
#define I2C_CR_I2C_END_EN_LEN (1U)
#define I2C_CR_I2C_END_EN_MSK (((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS)
#define I2C_CR_I2C_END_EN_UMSK (~(((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS))
#define I2C_CR_I2C_TXF_EN I2C_CR_I2C_TXF_EN
#define I2C_CR_I2C_TXF_EN_POS (25U)
#define I2C_CR_I2C_TXF_EN_LEN (1U)
#define I2C_CR_I2C_TXF_EN_MSK (((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS)
#define I2C_CR_I2C_TXF_EN_UMSK (~(((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS))
#define I2C_CR_I2C_RXF_EN I2C_CR_I2C_RXF_EN
#define I2C_CR_I2C_RXF_EN_POS (26U)
#define I2C_CR_I2C_RXF_EN_LEN (1U)
#define I2C_CR_I2C_RXF_EN_MSK (((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS)
#define I2C_CR_I2C_RXF_EN_UMSK (~(((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS))
#define I2C_CR_I2C_NAK_EN I2C_CR_I2C_NAK_EN
#define I2C_CR_I2C_NAK_EN_POS (27U)
#define I2C_CR_I2C_NAK_EN_LEN (1U)
#define I2C_CR_I2C_NAK_EN_MSK (((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS)
#define I2C_CR_I2C_NAK_EN_UMSK (~(((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS))
#define I2C_CR_I2C_ARB_EN I2C_CR_I2C_ARB_EN
#define I2C_CR_I2C_ARB_EN_POS (28U)
#define I2C_CR_I2C_ARB_EN_LEN (1U)
#define I2C_CR_I2C_ARB_EN_MSK (((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS)
#define I2C_CR_I2C_ARB_EN_UMSK (~(((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS))
#define I2C_CR_I2C_FER_EN I2C_CR_I2C_FER_EN
#define I2C_CR_I2C_FER_EN_POS (29U)
#define I2C_CR_I2C_FER_EN_LEN (1U)
#define I2C_CR_I2C_FER_EN_MSK (((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS)
#define I2C_CR_I2C_FER_EN_UMSK (~(((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS))
/* 0x8 : i2c_sub_addr */
#define I2C_SUB_ADDR_OFFSET (0x8)
#define I2C_CR_I2C_SUB_ADDR_B0 I2C_CR_I2C_SUB_ADDR_B0
#define I2C_CR_I2C_SUB_ADDR_B0_POS (0U)
#define I2C_CR_I2C_SUB_ADDR_B0_LEN (8U)
#define I2C_CR_I2C_SUB_ADDR_B0_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS)
#define I2C_CR_I2C_SUB_ADDR_B0_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS))
#define I2C_CR_I2C_SUB_ADDR_B1 I2C_CR_I2C_SUB_ADDR_B1
#define I2C_CR_I2C_SUB_ADDR_B1_POS (8U)
#define I2C_CR_I2C_SUB_ADDR_B1_LEN (8U)
#define I2C_CR_I2C_SUB_ADDR_B1_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS)
#define I2C_CR_I2C_SUB_ADDR_B1_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS))
#define I2C_CR_I2C_SUB_ADDR_B2 I2C_CR_I2C_SUB_ADDR_B2
#define I2C_CR_I2C_SUB_ADDR_B2_POS (16U)
#define I2C_CR_I2C_SUB_ADDR_B2_LEN (8U)
#define I2C_CR_I2C_SUB_ADDR_B2_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS)
#define I2C_CR_I2C_SUB_ADDR_B2_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS))
#define I2C_CR_I2C_SUB_ADDR_B3 I2C_CR_I2C_SUB_ADDR_B3
#define I2C_CR_I2C_SUB_ADDR_B3_POS (24U)
#define I2C_CR_I2C_SUB_ADDR_B3_LEN (8U)
#define I2C_CR_I2C_SUB_ADDR_B3_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS)
#define I2C_CR_I2C_SUB_ADDR_B3_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS))
/* 0xC : i2c_bus_busy */
#define I2C_BUS_BUSY_OFFSET (0xC)
#define I2C_STS_I2C_BUS_BUSY I2C_STS_I2C_BUS_BUSY
#define I2C_STS_I2C_BUS_BUSY_POS (0U)
#define I2C_STS_I2C_BUS_BUSY_LEN (1U)
#define I2C_STS_I2C_BUS_BUSY_MSK (((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS)
#define I2C_STS_I2C_BUS_BUSY_UMSK (~(((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS))
#define I2C_CR_I2C_BUS_BUSY_CLR I2C_CR_I2C_BUS_BUSY_CLR
#define I2C_CR_I2C_BUS_BUSY_CLR_POS (1U)
#define I2C_CR_I2C_BUS_BUSY_CLR_LEN (1U)
#define I2C_CR_I2C_BUS_BUSY_CLR_MSK (((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS)
#define I2C_CR_I2C_BUS_BUSY_CLR_UMSK (~(((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS))
/* 0x10 : i2c_prd_start */
#define I2C_PRD_START_OFFSET (0x10)
#define I2C_CR_I2C_PRD_S_PH_0 I2C_CR_I2C_PRD_S_PH_0
#define I2C_CR_I2C_PRD_S_PH_0_POS (0U)
#define I2C_CR_I2C_PRD_S_PH_0_LEN (8U)
#define I2C_CR_I2C_PRD_S_PH_0_MSK (((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS)
#define I2C_CR_I2C_PRD_S_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS))
#define I2C_CR_I2C_PRD_S_PH_1 I2C_CR_I2C_PRD_S_PH_1
#define I2C_CR_I2C_PRD_S_PH_1_POS (8U)
#define I2C_CR_I2C_PRD_S_PH_1_LEN (8U)
#define I2C_CR_I2C_PRD_S_PH_1_MSK (((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS)
#define I2C_CR_I2C_PRD_S_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS))
#define I2C_CR_I2C_PRD_S_PH_2 I2C_CR_I2C_PRD_S_PH_2
#define I2C_CR_I2C_PRD_S_PH_2_POS (16U)
#define I2C_CR_I2C_PRD_S_PH_2_LEN (8U)
#define I2C_CR_I2C_PRD_S_PH_2_MSK (((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS)
#define I2C_CR_I2C_PRD_S_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS))
#define I2C_CR_I2C_PRD_S_PH_3 I2C_CR_I2C_PRD_S_PH_3
#define I2C_CR_I2C_PRD_S_PH_3_POS (24U)
#define I2C_CR_I2C_PRD_S_PH_3_LEN (8U)
#define I2C_CR_I2C_PRD_S_PH_3_MSK (((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS)
#define I2C_CR_I2C_PRD_S_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS))
/* 0x14 : i2c_prd_stop */
#define I2C_PRD_STOP_OFFSET (0x14)
#define I2C_CR_I2C_PRD_P_PH_0 I2C_CR_I2C_PRD_P_PH_0
#define I2C_CR_I2C_PRD_P_PH_0_POS (0U)
#define I2C_CR_I2C_PRD_P_PH_0_LEN (8U)
#define I2C_CR_I2C_PRD_P_PH_0_MSK (((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS)
#define I2C_CR_I2C_PRD_P_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS))
#define I2C_CR_I2C_PRD_P_PH_1 I2C_CR_I2C_PRD_P_PH_1
#define I2C_CR_I2C_PRD_P_PH_1_POS (8U)
#define I2C_CR_I2C_PRD_P_PH_1_LEN (8U)
#define I2C_CR_I2C_PRD_P_PH_1_MSK (((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS)
#define I2C_CR_I2C_PRD_P_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS))
#define I2C_CR_I2C_PRD_P_PH_2 I2C_CR_I2C_PRD_P_PH_2
#define I2C_CR_I2C_PRD_P_PH_2_POS (16U)
#define I2C_CR_I2C_PRD_P_PH_2_LEN (8U)
#define I2C_CR_I2C_PRD_P_PH_2_MSK (((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS)
#define I2C_CR_I2C_PRD_P_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS))
#define I2C_CR_I2C_PRD_P_PH_3 I2C_CR_I2C_PRD_P_PH_3
#define I2C_CR_I2C_PRD_P_PH_3_POS (24U)
#define I2C_CR_I2C_PRD_P_PH_3_LEN (8U)
#define I2C_CR_I2C_PRD_P_PH_3_MSK (((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS)
#define I2C_CR_I2C_PRD_P_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS))
/* 0x18 : i2c_prd_data */
#define I2C_PRD_DATA_OFFSET (0x18)
#define I2C_CR_I2C_PRD_D_PH_0 I2C_CR_I2C_PRD_D_PH_0
#define I2C_CR_I2C_PRD_D_PH_0_POS (0U)
#define I2C_CR_I2C_PRD_D_PH_0_LEN (8U)
#define I2C_CR_I2C_PRD_D_PH_0_MSK (((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS)
#define I2C_CR_I2C_PRD_D_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS))
#define I2C_CR_I2C_PRD_D_PH_1 I2C_CR_I2C_PRD_D_PH_1
#define I2C_CR_I2C_PRD_D_PH_1_POS (8U)
#define I2C_CR_I2C_PRD_D_PH_1_LEN (8U)
#define I2C_CR_I2C_PRD_D_PH_1_MSK (((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS)
#define I2C_CR_I2C_PRD_D_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS))
#define I2C_CR_I2C_PRD_D_PH_2 I2C_CR_I2C_PRD_D_PH_2
#define I2C_CR_I2C_PRD_D_PH_2_POS (16U)
#define I2C_CR_I2C_PRD_D_PH_2_LEN (8U)
#define I2C_CR_I2C_PRD_D_PH_2_MSK (((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS)
#define I2C_CR_I2C_PRD_D_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS))
#define I2C_CR_I2C_PRD_D_PH_3 I2C_CR_I2C_PRD_D_PH_3
#define I2C_CR_I2C_PRD_D_PH_3_POS (24U)
#define I2C_CR_I2C_PRD_D_PH_3_LEN (8U)
#define I2C_CR_I2C_PRD_D_PH_3_MSK (((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS)
#define I2C_CR_I2C_PRD_D_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS))
/* 0x80 : i2c_fifo_config_0 */
#define I2C_FIFO_CONFIG_0_OFFSET (0x80)
#define I2C_DMA_TX_EN I2C_DMA_TX_EN
#define I2C_DMA_TX_EN_POS (0U)
#define I2C_DMA_TX_EN_LEN (1U)
#define I2C_DMA_TX_EN_MSK (((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS)
#define I2C_DMA_TX_EN_UMSK (~(((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS))
#define I2C_DMA_RX_EN I2C_DMA_RX_EN
#define I2C_DMA_RX_EN_POS (1U)
#define I2C_DMA_RX_EN_LEN (1U)
#define I2C_DMA_RX_EN_MSK (((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS)
#define I2C_DMA_RX_EN_UMSK (~(((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS))
#define I2C_TX_FIFO_CLR I2C_TX_FIFO_CLR
#define I2C_TX_FIFO_CLR_POS (2U)
#define I2C_TX_FIFO_CLR_LEN (1U)
#define I2C_TX_FIFO_CLR_MSK (((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS)
#define I2C_TX_FIFO_CLR_UMSK (~(((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS))
#define I2C_RX_FIFO_CLR I2C_RX_FIFO_CLR
#define I2C_RX_FIFO_CLR_POS (3U)
#define I2C_RX_FIFO_CLR_LEN (1U)
#define I2C_RX_FIFO_CLR_MSK (((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS)
#define I2C_RX_FIFO_CLR_UMSK (~(((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS))
#define I2C_TX_FIFO_OVERFLOW I2C_TX_FIFO_OVERFLOW
#define I2C_TX_FIFO_OVERFLOW_POS (4U)
#define I2C_TX_FIFO_OVERFLOW_LEN (1U)
#define I2C_TX_FIFO_OVERFLOW_MSK (((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS)
#define I2C_TX_FIFO_OVERFLOW_UMSK (~(((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS))
#define I2C_TX_FIFO_UNDERFLOW I2C_TX_FIFO_UNDERFLOW
#define I2C_TX_FIFO_UNDERFLOW_POS (5U)
#define I2C_TX_FIFO_UNDERFLOW_LEN (1U)
#define I2C_TX_FIFO_UNDERFLOW_MSK (((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS)
#define I2C_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS))
#define I2C_RX_FIFO_OVERFLOW I2C_RX_FIFO_OVERFLOW
#define I2C_RX_FIFO_OVERFLOW_POS (6U)
#define I2C_RX_FIFO_OVERFLOW_LEN (1U)
#define I2C_RX_FIFO_OVERFLOW_MSK (((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS)
#define I2C_RX_FIFO_OVERFLOW_UMSK (~(((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS))
#define I2C_RX_FIFO_UNDERFLOW I2C_RX_FIFO_UNDERFLOW
#define I2C_RX_FIFO_UNDERFLOW_POS (7U)
#define I2C_RX_FIFO_UNDERFLOW_LEN (1U)
#define I2C_RX_FIFO_UNDERFLOW_MSK (((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS)
#define I2C_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS))
/* 0x84 : i2c_fifo_config_1 */
#define I2C_FIFO_CONFIG_1_OFFSET (0x84)
#define I2C_TX_FIFO_CNT I2C_TX_FIFO_CNT
#define I2C_TX_FIFO_CNT_POS (0U)
#define I2C_TX_FIFO_CNT_LEN (2U)
#define I2C_TX_FIFO_CNT_MSK (((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS)
#define I2C_TX_FIFO_CNT_UMSK (~(((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS))
#define I2C_RX_FIFO_CNT I2C_RX_FIFO_CNT
#define I2C_RX_FIFO_CNT_POS (8U)
#define I2C_RX_FIFO_CNT_LEN (2U)
#define I2C_RX_FIFO_CNT_MSK (((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS)
#define I2C_RX_FIFO_CNT_UMSK (~(((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS))
#define I2C_TX_FIFO_TH I2C_TX_FIFO_TH
#define I2C_TX_FIFO_TH_POS (16U)
#define I2C_TX_FIFO_TH_LEN (1U)
#define I2C_TX_FIFO_TH_MSK (((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS)
#define I2C_TX_FIFO_TH_UMSK (~(((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS))
#define I2C_RX_FIFO_TH I2C_RX_FIFO_TH
#define I2C_RX_FIFO_TH_POS (24U)
#define I2C_RX_FIFO_TH_LEN (1U)
#define I2C_RX_FIFO_TH_MSK (((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS)
#define I2C_RX_FIFO_TH_UMSK (~(((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS))
/* 0x88 : i2c_fifo_wdata */
#define I2C_FIFO_WDATA_OFFSET (0x88)
#define I2C_FIFO_WDATA I2C_FIFO_WDATA
#define I2C_FIFO_WDATA_POS (0U)
#define I2C_FIFO_WDATA_LEN (32U)
#define I2C_FIFO_WDATA_MSK (((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS)
#define I2C_FIFO_WDATA_UMSK (~(((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS))
/* 0x8C : i2c_fifo_rdata */
#define I2C_FIFO_RDATA_OFFSET (0x8C)
#define I2C_FIFO_RDATA I2C_FIFO_RDATA
#define I2C_FIFO_RDATA_POS (0U)
#define I2C_FIFO_RDATA_LEN (32U)
#define I2C_FIFO_RDATA_MSK (((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS)
#define I2C_FIFO_RDATA_UMSK (~(((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS))
struct i2c_reg {
/* 0x0 : i2c_config */
union {
struct
{
uint32_t cr_i2c_m_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_i2c_pkt_dir : 1; /* [ 1], r/w, 0x1 */
uint32_t cr_i2c_deg_en : 1; /* [ 2], r/w, 0x0 */
uint32_t cr_i2c_scl_sync_en : 1; /* [ 3], r/w, 0x1 */
uint32_t cr_i2c_sub_addr_en : 1; /* [ 4], r/w, 0x0 */
uint32_t cr_i2c_sub_addr_bc : 2; /* [ 6: 5], r/w, 0x0 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t cr_i2c_slv_addr : 7; /* [14: 8], r/w, 0x0 */
uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
uint32_t cr_i2c_pkt_len : 8; /* [23:16], r/w, 0x0 */
uint32_t reserved_24_27 : 4; /* [27:24], rsvd, 0x0 */
uint32_t cr_i2c_deg_cnt : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} i2c_config;
/* 0x4 : i2c_int_sts */
union {
struct
{
uint32_t i2c_end_int : 1; /* [ 0], r, 0x0 */
uint32_t i2c_txf_int : 1; /* [ 1], r, 0x0 */
uint32_t i2c_rxf_int : 1; /* [ 2], r, 0x0 */
uint32_t i2c_nak_int : 1; /* [ 3], r, 0x0 */
uint32_t i2c_arb_int : 1; /* [ 4], r, 0x0 */
uint32_t i2c_fer_int : 1; /* [ 5], r, 0x0 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t cr_i2c_end_mask : 1; /* [ 8], r/w, 0x1 */
uint32_t cr_i2c_txf_mask : 1; /* [ 9], r/w, 0x1 */
uint32_t cr_i2c_rxf_mask : 1; /* [ 10], r/w, 0x1 */
uint32_t cr_i2c_nak_mask : 1; /* [ 11], r/w, 0x1 */
uint32_t cr_i2c_arb_mask : 1; /* [ 12], r/w, 0x1 */
uint32_t cr_i2c_fer_mask : 1; /* [ 13], r/w, 0x1 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t cr_i2c_end_clr : 1; /* [ 16], w1c, 0x0 */
uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */
uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */
uint32_t cr_i2c_nak_clr : 1; /* [ 19], w1c, 0x0 */
uint32_t cr_i2c_arb_clr : 1; /* [ 20], w1c, 0x0 */
uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */
uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
uint32_t cr_i2c_end_en : 1; /* [ 24], r/w, 0x1 */
uint32_t cr_i2c_txf_en : 1; /* [ 25], r/w, 0x1 */
uint32_t cr_i2c_rxf_en : 1; /* [ 26], r/w, 0x1 */
uint32_t cr_i2c_nak_en : 1; /* [ 27], r/w, 0x1 */
uint32_t cr_i2c_arb_en : 1; /* [ 28], r/w, 0x1 */
uint32_t cr_i2c_fer_en : 1; /* [ 29], r/w, 0x1 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} i2c_int_sts;
/* 0x8 : i2c_sub_addr */
union {
struct
{
uint32_t cr_i2c_sub_addr_b0 : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t cr_i2c_sub_addr_b1 : 8; /* [15: 8], r/w, 0x0 */
uint32_t cr_i2c_sub_addr_b2 : 8; /* [23:16], r/w, 0x0 */
uint32_t cr_i2c_sub_addr_b3 : 8; /* [31:24], r/w, 0x0 */
} BF;
uint32_t WORD;
} i2c_sub_addr;
/* 0xC : i2c_bus_busy */
union {
struct
{
uint32_t sts_i2c_bus_busy : 1; /* [ 0], r, 0x0 */
uint32_t cr_i2c_bus_busy_clr : 1; /* [ 1], w1c, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
} BF;
uint32_t WORD;
} i2c_bus_busy;
/* 0x10 : i2c_prd_start */
union {
struct
{
uint32_t cr_i2c_prd_s_ph_0 : 8; /* [ 7: 0], r/w, 0xf */
uint32_t cr_i2c_prd_s_ph_1 : 8; /* [15: 8], r/w, 0xf */
uint32_t cr_i2c_prd_s_ph_2 : 8; /* [23:16], r/w, 0xf */
uint32_t cr_i2c_prd_s_ph_3 : 8; /* [31:24], r/w, 0xf */
} BF;
uint32_t WORD;
} i2c_prd_start;
/* 0x14 : i2c_prd_stop */
union {
struct
{
uint32_t cr_i2c_prd_p_ph_0 : 8; /* [ 7: 0], r/w, 0xf */
uint32_t cr_i2c_prd_p_ph_1 : 8; /* [15: 8], r/w, 0xf */
uint32_t cr_i2c_prd_p_ph_2 : 8; /* [23:16], r/w, 0xf */
uint32_t cr_i2c_prd_p_ph_3 : 8; /* [31:24], r/w, 0xf */
} BF;
uint32_t WORD;
} i2c_prd_stop;
/* 0x18 : i2c_prd_data */
union {
struct
{
uint32_t cr_i2c_prd_d_ph_0 : 8; /* [ 7: 0], r/w, 0xf */
uint32_t cr_i2c_prd_d_ph_1 : 8; /* [15: 8], r/w, 0xf */
uint32_t cr_i2c_prd_d_ph_2 : 8; /* [23:16], r/w, 0xf */
uint32_t cr_i2c_prd_d_ph_3 : 8; /* [31:24], r/w, 0xf */
} BF;
uint32_t WORD;
} i2c_prd_data;
/* 0x1c reserved */
uint8_t RESERVED0x1c[100];
/* 0x80 : i2c_fifo_config_0 */
union {
struct
{
uint32_t i2c_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t i2c_dma_rx_en : 1; /* [ 1], r/w, 0x0 */
uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */
uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */
uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */
uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */
uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */
uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} i2c_fifo_config_0;
/* 0x84 : i2c_fifo_config_1 */
union {
struct
{
uint32_t tx_fifo_cnt : 2; /* [ 1: 0], r, 0x2 */
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
uint32_t rx_fifo_cnt : 2; /* [ 9: 8], r, 0x0 */
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
uint32_t tx_fifo_th : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */
uint32_t rx_fifo_th : 1; /* [ 24], r/w, 0x0 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
} BF;
uint32_t WORD;
} i2c_fifo_config_1;
/* 0x88 : i2c_fifo_wdata */
union {
struct
{
uint32_t i2c_fifo_wdata : 32; /* [31: 0], w, x */
} BF;
uint32_t WORD;
} i2c_fifo_wdata;
/* 0x8C : i2c_fifo_rdata */
union {
struct
{
uint32_t i2c_fifo_rdata : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} i2c_fifo_rdata;
};
typedef volatile struct i2c_reg i2c_reg_t;
#endif /* __I2C_REG_H__ */

455
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/i2s_reg.h
View File

@@ -1,455 +0,0 @@
/**
******************************************************************************
* @file i2s_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __I2S_REG_H__
#define __I2S_REG_H__
#include "bl702.h"
/* 0x0 : i2s_config */
#define I2S_CONFIG_OFFSET (0x0)
#define I2S_CR_I2S_M_EN I2S_CR_I2S_M_EN
#define I2S_CR_I2S_M_EN_POS (0U)
#define I2S_CR_I2S_M_EN_LEN (1U)
#define I2S_CR_I2S_M_EN_MSK (((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS)
#define I2S_CR_I2S_M_EN_UMSK (~(((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS))
#define I2S_CR_I2S_S_EN I2S_CR_I2S_S_EN
#define I2S_CR_I2S_S_EN_POS (1U)
#define I2S_CR_I2S_S_EN_LEN (1U)
#define I2S_CR_I2S_S_EN_MSK (((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS)
#define I2S_CR_I2S_S_EN_UMSK (~(((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS))
#define I2S_CR_I2S_TXD_EN I2S_CR_I2S_TXD_EN
#define I2S_CR_I2S_TXD_EN_POS (2U)
#define I2S_CR_I2S_TXD_EN_LEN (1U)
#define I2S_CR_I2S_TXD_EN_MSK (((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS)
#define I2S_CR_I2S_TXD_EN_UMSK (~(((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS))
#define I2S_CR_I2S_RXD_EN I2S_CR_I2S_RXD_EN
#define I2S_CR_I2S_RXD_EN_POS (3U)
#define I2S_CR_I2S_RXD_EN_LEN (1U)
#define I2S_CR_I2S_RXD_EN_MSK (((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS)
#define I2S_CR_I2S_RXD_EN_UMSK (~(((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS))
#define I2S_CR_MONO_MODE I2S_CR_MONO_MODE
#define I2S_CR_MONO_MODE_POS (4U)
#define I2S_CR_MONO_MODE_LEN (1U)
#define I2S_CR_MONO_MODE_MSK (((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS)
#define I2S_CR_MONO_MODE_UMSK (~(((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS))
#define I2S_CR_MUTE_MODE I2S_CR_MUTE_MODE
#define I2S_CR_MUTE_MODE_POS (5U)
#define I2S_CR_MUTE_MODE_LEN (1U)
#define I2S_CR_MUTE_MODE_MSK (((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS)
#define I2S_CR_MUTE_MODE_UMSK (~(((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS))
#define I2S_CR_FS_1T_MODE I2S_CR_FS_1T_MODE
#define I2S_CR_FS_1T_MODE_POS (6U)
#define I2S_CR_FS_1T_MODE_LEN (1U)
#define I2S_CR_FS_1T_MODE_MSK (((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS)
#define I2S_CR_FS_1T_MODE_UMSK (~(((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS))
#define I2S_CR_FS_4CH_MODE I2S_CR_FS_4CH_MODE
#define I2S_CR_FS_4CH_MODE_POS (7U)
#define I2S_CR_FS_4CH_MODE_LEN (1U)
#define I2S_CR_FS_4CH_MODE_MSK (((1U << I2S_CR_FS_4CH_MODE_LEN) - 1) << I2S_CR_FS_4CH_MODE_POS)
#define I2S_CR_FS_4CH_MODE_UMSK (~(((1U << I2S_CR_FS_4CH_MODE_LEN) - 1) << I2S_CR_FS_4CH_MODE_POS))
#define I2S_CR_FS_3CH_MODE I2S_CR_FS_3CH_MODE
#define I2S_CR_FS_3CH_MODE_POS (8U)
#define I2S_CR_FS_3CH_MODE_LEN (1U)
#define I2S_CR_FS_3CH_MODE_MSK (((1U << I2S_CR_FS_3CH_MODE_LEN) - 1) << I2S_CR_FS_3CH_MODE_POS)
#define I2S_CR_FS_3CH_MODE_UMSK (~(((1U << I2S_CR_FS_3CH_MODE_LEN) - 1) << I2S_CR_FS_3CH_MODE_POS))
#define I2S_CR_FRAME_SIZE I2S_CR_FRAME_SIZE
#define I2S_CR_FRAME_SIZE_POS (12U)
#define I2S_CR_FRAME_SIZE_LEN (2U)
#define I2S_CR_FRAME_SIZE_MSK (((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS)
#define I2S_CR_FRAME_SIZE_UMSK (~(((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS))
#define I2S_CR_DATA_SIZE I2S_CR_DATA_SIZE
#define I2S_CR_DATA_SIZE_POS (14U)
#define I2S_CR_DATA_SIZE_LEN (2U)
#define I2S_CR_DATA_SIZE_MSK (((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS)
#define I2S_CR_DATA_SIZE_UMSK (~(((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS))
#define I2S_CR_I2S_MODE I2S_CR_I2S_MODE
#define I2S_CR_I2S_MODE_POS (16U)
#define I2S_CR_I2S_MODE_LEN (2U)
#define I2S_CR_I2S_MODE_MSK (((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS)
#define I2S_CR_I2S_MODE_UMSK (~(((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS))
#define I2S_CR_ENDIAN I2S_CR_ENDIAN
#define I2S_CR_ENDIAN_POS (18U)
#define I2S_CR_ENDIAN_LEN (1U)
#define I2S_CR_ENDIAN_MSK (((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS)
#define I2S_CR_ENDIAN_UMSK (~(((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS))
#define I2S_CR_MONO_RX_CH I2S_CR_MONO_RX_CH
#define I2S_CR_MONO_RX_CH_POS (19U)
#define I2S_CR_MONO_RX_CH_LEN (1U)
#define I2S_CR_MONO_RX_CH_MSK (((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS)
#define I2S_CR_MONO_RX_CH_UMSK (~(((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS))
#define I2S_CR_OFS_CNT I2S_CR_OFS_CNT
#define I2S_CR_OFS_CNT_POS (20U)
#define I2S_CR_OFS_CNT_LEN (5U)
#define I2S_CR_OFS_CNT_MSK (((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS)
#define I2S_CR_OFS_CNT_UMSK (~(((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS))
#define I2S_CR_OFS_EN I2S_CR_OFS_EN
#define I2S_CR_OFS_EN_POS (25U)
#define I2S_CR_OFS_EN_LEN (1U)
#define I2S_CR_OFS_EN_MSK (((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS)
#define I2S_CR_OFS_EN_UMSK (~(((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS))
/* 0x4 : i2s_int_sts */
#define I2S_INT_STS_OFFSET (0x4)
#define I2S_TXF_INT I2S_TXF_INT
#define I2S_TXF_INT_POS (0U)
#define I2S_TXF_INT_LEN (1U)
#define I2S_TXF_INT_MSK (((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS)
#define I2S_TXF_INT_UMSK (~(((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS))
#define I2S_RXF_INT I2S_RXF_INT
#define I2S_RXF_INT_POS (1U)
#define I2S_RXF_INT_LEN (1U)
#define I2S_RXF_INT_MSK (((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS)
#define I2S_RXF_INT_UMSK (~(((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS))
#define I2S_FER_INT I2S_FER_INT
#define I2S_FER_INT_POS (2U)
#define I2S_FER_INT_LEN (1U)
#define I2S_FER_INT_MSK (((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS)
#define I2S_FER_INT_UMSK (~(((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS))
#define I2S_CR_I2S_TXF_MASK I2S_CR_I2S_TXF_MASK
#define I2S_CR_I2S_TXF_MASK_POS (8U)
#define I2S_CR_I2S_TXF_MASK_LEN (1U)
#define I2S_CR_I2S_TXF_MASK_MSK (((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS)
#define I2S_CR_I2S_TXF_MASK_UMSK (~(((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS))
#define I2S_CR_I2S_RXF_MASK I2S_CR_I2S_RXF_MASK
#define I2S_CR_I2S_RXF_MASK_POS (9U)
#define I2S_CR_I2S_RXF_MASK_LEN (1U)
#define I2S_CR_I2S_RXF_MASK_MSK (((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS)
#define I2S_CR_I2S_RXF_MASK_UMSK (~(((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS))
#define I2S_CR_I2S_FER_MASK I2S_CR_I2S_FER_MASK
#define I2S_CR_I2S_FER_MASK_POS (10U)
#define I2S_CR_I2S_FER_MASK_LEN (1U)
#define I2S_CR_I2S_FER_MASK_MSK (((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS)
#define I2S_CR_I2S_FER_MASK_UMSK (~(((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS))
#define I2S_CR_I2S_TXF_EN I2S_CR_I2S_TXF_EN
#define I2S_CR_I2S_TXF_EN_POS (24U)
#define I2S_CR_I2S_TXF_EN_LEN (1U)
#define I2S_CR_I2S_TXF_EN_MSK (((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS)
#define I2S_CR_I2S_TXF_EN_UMSK (~(((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS))
#define I2S_CR_I2S_RXF_EN I2S_CR_I2S_RXF_EN
#define I2S_CR_I2S_RXF_EN_POS (25U)
#define I2S_CR_I2S_RXF_EN_LEN (1U)
#define I2S_CR_I2S_RXF_EN_MSK (((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS)
#define I2S_CR_I2S_RXF_EN_UMSK (~(((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS))
#define I2S_CR_I2S_FER_EN I2S_CR_I2S_FER_EN
#define I2S_CR_I2S_FER_EN_POS (26U)
#define I2S_CR_I2S_FER_EN_LEN (1U)
#define I2S_CR_I2S_FER_EN_MSK (((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS)
#define I2S_CR_I2S_FER_EN_UMSK (~(((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS))
/* 0x10 : i2s_bclk_config */
#define I2S_BCLK_CONFIG_OFFSET (0x10)
#define I2S_CR_BCLK_DIV_L I2S_CR_BCLK_DIV_L
#define I2S_CR_BCLK_DIV_L_POS (0U)
#define I2S_CR_BCLK_DIV_L_LEN (12U)
#define I2S_CR_BCLK_DIV_L_MSK (((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS)
#define I2S_CR_BCLK_DIV_L_UMSK (~(((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS))
#define I2S_CR_BCLK_DIV_H I2S_CR_BCLK_DIV_H
#define I2S_CR_BCLK_DIV_H_POS (16U)
#define I2S_CR_BCLK_DIV_H_LEN (12U)
#define I2S_CR_BCLK_DIV_H_MSK (((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS)
#define I2S_CR_BCLK_DIV_H_UMSK (~(((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS))
/* 0x80 : i2s_fifo_config_0 */
#define I2S_FIFO_CONFIG_0_OFFSET (0x80)
#define I2S_DMA_TX_EN I2S_DMA_TX_EN
#define I2S_DMA_TX_EN_POS (0U)
#define I2S_DMA_TX_EN_LEN (1U)
#define I2S_DMA_TX_EN_MSK (((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS)
#define I2S_DMA_TX_EN_UMSK (~(((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS))
#define I2S_DMA_RX_EN I2S_DMA_RX_EN
#define I2S_DMA_RX_EN_POS (1U)
#define I2S_DMA_RX_EN_LEN (1U)
#define I2S_DMA_RX_EN_MSK (((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS)
#define I2S_DMA_RX_EN_UMSK (~(((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS))
#define I2S_TX_FIFO_CLR I2S_TX_FIFO_CLR
#define I2S_TX_FIFO_CLR_POS (2U)
#define I2S_TX_FIFO_CLR_LEN (1U)
#define I2S_TX_FIFO_CLR_MSK (((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS)
#define I2S_TX_FIFO_CLR_UMSK (~(((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS))
#define I2S_RX_FIFO_CLR I2S_RX_FIFO_CLR
#define I2S_RX_FIFO_CLR_POS (3U)
#define I2S_RX_FIFO_CLR_LEN (1U)
#define I2S_RX_FIFO_CLR_MSK (((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS)
#define I2S_RX_FIFO_CLR_UMSK (~(((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS))
#define I2S_TX_FIFO_OVERFLOW I2S_TX_FIFO_OVERFLOW
#define I2S_TX_FIFO_OVERFLOW_POS (4U)
#define I2S_TX_FIFO_OVERFLOW_LEN (1U)
#define I2S_TX_FIFO_OVERFLOW_MSK (((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS)
#define I2S_TX_FIFO_OVERFLOW_UMSK (~(((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS))
#define I2S_TX_FIFO_UNDERFLOW I2S_TX_FIFO_UNDERFLOW
#define I2S_TX_FIFO_UNDERFLOW_POS (5U)
#define I2S_TX_FIFO_UNDERFLOW_LEN (1U)
#define I2S_TX_FIFO_UNDERFLOW_MSK (((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS)
#define I2S_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS))
#define I2S_RX_FIFO_OVERFLOW I2S_RX_FIFO_OVERFLOW
#define I2S_RX_FIFO_OVERFLOW_POS (6U)
#define I2S_RX_FIFO_OVERFLOW_LEN (1U)
#define I2S_RX_FIFO_OVERFLOW_MSK (((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS)
#define I2S_RX_FIFO_OVERFLOW_UMSK (~(((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS))
#define I2S_RX_FIFO_UNDERFLOW I2S_RX_FIFO_UNDERFLOW
#define I2S_RX_FIFO_UNDERFLOW_POS (7U)
#define I2S_RX_FIFO_UNDERFLOW_LEN (1U)
#define I2S_RX_FIFO_UNDERFLOW_MSK (((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS)
#define I2S_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS))
#define I2S_CR_FIFO_LR_MERGE I2S_CR_FIFO_LR_MERGE
#define I2S_CR_FIFO_LR_MERGE_POS (8U)
#define I2S_CR_FIFO_LR_MERGE_LEN (1U)
#define I2S_CR_FIFO_LR_MERGE_MSK (((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS)
#define I2S_CR_FIFO_LR_MERGE_UMSK (~(((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS))
#define I2S_CR_FIFO_LR_EXCHG I2S_CR_FIFO_LR_EXCHG
#define I2S_CR_FIFO_LR_EXCHG_POS (9U)
#define I2S_CR_FIFO_LR_EXCHG_LEN (1U)
#define I2S_CR_FIFO_LR_EXCHG_MSK (((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS)
#define I2S_CR_FIFO_LR_EXCHG_UMSK (~(((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS))
#define I2S_CR_FIFO_24B_LJ I2S_CR_FIFO_24B_LJ
#define I2S_CR_FIFO_24B_LJ_POS (10U)
#define I2S_CR_FIFO_24B_LJ_LEN (1U)
#define I2S_CR_FIFO_24B_LJ_MSK (((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS)
#define I2S_CR_FIFO_24B_LJ_UMSK (~(((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS))
/* 0x84 : i2s_fifo_config_1 */
#define I2S_FIFO_CONFIG_1_OFFSET (0x84)
#define I2S_TX_FIFO_CNT I2S_TX_FIFO_CNT
#define I2S_TX_FIFO_CNT_POS (0U)
#define I2S_TX_FIFO_CNT_LEN (5U)
#define I2S_TX_FIFO_CNT_MSK (((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS)
#define I2S_TX_FIFO_CNT_UMSK (~(((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS))
#define I2S_RX_FIFO_CNT I2S_RX_FIFO_CNT
#define I2S_RX_FIFO_CNT_POS (8U)
#define I2S_RX_FIFO_CNT_LEN (5U)
#define I2S_RX_FIFO_CNT_MSK (((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS)
#define I2S_RX_FIFO_CNT_UMSK (~(((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS))
#define I2S_TX_FIFO_TH I2S_TX_FIFO_TH
#define I2S_TX_FIFO_TH_POS (16U)
#define I2S_TX_FIFO_TH_LEN (4U)
#define I2S_TX_FIFO_TH_MSK (((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS)
#define I2S_TX_FIFO_TH_UMSK (~(((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS))
#define I2S_RX_FIFO_TH I2S_RX_FIFO_TH
#define I2S_RX_FIFO_TH_POS (24U)
#define I2S_RX_FIFO_TH_LEN (4U)
#define I2S_RX_FIFO_TH_MSK (((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS)
#define I2S_RX_FIFO_TH_UMSK (~(((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS))
/* 0x88 : i2s_fifo_wdata */
#define I2S_FIFO_WDATA_OFFSET (0x88)
#define I2S_FIFO_WDATA I2S_FIFO_WDATA
#define I2S_FIFO_WDATA_POS (0U)
#define I2S_FIFO_WDATA_LEN (32U)
#define I2S_FIFO_WDATA_MSK (((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS)
#define I2S_FIFO_WDATA_UMSK (~(((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS))
/* 0x8C : i2s_fifo_rdata */
#define I2S_FIFO_RDATA_OFFSET (0x8C)
#define I2S_FIFO_RDATA I2S_FIFO_RDATA
#define I2S_FIFO_RDATA_POS (0U)
#define I2S_FIFO_RDATA_LEN (32U)
#define I2S_FIFO_RDATA_MSK (((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS)
#define I2S_FIFO_RDATA_UMSK (~(((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS))
/* 0xFC : i2s_io_config */
#define I2S_IO_CONFIG_OFFSET (0xFC)
#define I2S_CR_I2S_TXD_INV I2S_CR_I2S_TXD_INV
#define I2S_CR_I2S_TXD_INV_POS (0U)
#define I2S_CR_I2S_TXD_INV_LEN (1U)
#define I2S_CR_I2S_TXD_INV_MSK (((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS)
#define I2S_CR_I2S_TXD_INV_UMSK (~(((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS))
#define I2S_CR_I2S_RXD_INV I2S_CR_I2S_RXD_INV
#define I2S_CR_I2S_RXD_INV_POS (1U)
#define I2S_CR_I2S_RXD_INV_LEN (1U)
#define I2S_CR_I2S_RXD_INV_MSK (((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS)
#define I2S_CR_I2S_RXD_INV_UMSK (~(((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS))
#define I2S_CR_I2S_FS_INV I2S_CR_I2S_FS_INV
#define I2S_CR_I2S_FS_INV_POS (2U)
#define I2S_CR_I2S_FS_INV_LEN (1U)
#define I2S_CR_I2S_FS_INV_MSK (((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS)
#define I2S_CR_I2S_FS_INV_UMSK (~(((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS))
#define I2S_CR_I2S_BCLK_INV I2S_CR_I2S_BCLK_INV
#define I2S_CR_I2S_BCLK_INV_POS (3U)
#define I2S_CR_I2S_BCLK_INV_LEN (1U)
#define I2S_CR_I2S_BCLK_INV_MSK (((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS)
#define I2S_CR_I2S_BCLK_INV_UMSK (~(((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS))
#define I2S_CR_DEG_CNT I2S_CR_DEG_CNT
#define I2S_CR_DEG_CNT_POS (4U)
#define I2S_CR_DEG_CNT_LEN (3U)
#define I2S_CR_DEG_CNT_MSK (((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS)
#define I2S_CR_DEG_CNT_UMSK (~(((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS))
#define I2S_CR_DEG_EN I2S_CR_DEG_EN
#define I2S_CR_DEG_EN_POS (7U)
#define I2S_CR_DEG_EN_LEN (1U)
#define I2S_CR_DEG_EN_MSK (((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS)
#define I2S_CR_DEG_EN_UMSK (~(((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS))
struct i2s_reg {
/* 0x0 : i2s_config */
union {
struct
{
uint32_t cr_i2s_m_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_i2s_s_en : 1; /* [ 1], r/w, 0x0 */
uint32_t cr_i2s_txd_en : 1; /* [ 2], r/w, 0x0 */
uint32_t cr_i2s_rxd_en : 1; /* [ 3], r/w, 0x0 */
uint32_t cr_mono_mode : 1; /* [ 4], r/w, 0x0 */
uint32_t cr_mute_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t cr_fs_1t_mode : 1; /* [ 6], r/w, 0x0 */
uint32_t cr_fs_4ch_mode : 1; /* [ 7], r/w, 0x0 */
uint32_t cr_fs_3ch_mode : 1; /* [ 8], r/w, 0x0 */
uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
uint32_t cr_frame_size : 2; /* [13:12], r/w, 0x1 */
uint32_t cr_data_size : 2; /* [15:14], r/w, 0x1 */
uint32_t cr_i2s_mode : 2; /* [17:16], r/w, 0x0 */
uint32_t cr_endian : 1; /* [ 18], r/w, 0x0 */
uint32_t cr_mono_rx_ch : 1; /* [ 19], r/w, 0x0 */
uint32_t cr_ofs_cnt : 5; /* [24:20], r/w, 0x0 */
uint32_t cr_ofs_en : 1; /* [ 25], r/w, 0x0 */
uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
} BF;
uint32_t WORD;
} i2s_config;
/* 0x4 : i2s_int_sts */
union {
struct
{
uint32_t i2s_txf_int : 1; /* [ 0], r, 0x0 */
uint32_t i2s_rxf_int : 1; /* [ 1], r, 0x0 */
uint32_t i2s_fer_int : 1; /* [ 2], r, 0x0 */
uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
uint32_t cr_i2s_txf_mask : 1; /* [ 8], r/w, 0x1 */
uint32_t cr_i2s_rxf_mask : 1; /* [ 9], r/w, 0x1 */
uint32_t cr_i2s_fer_mask : 1; /* [ 10], r/w, 0x1 */
uint32_t reserved_11_23 : 13; /* [23:11], rsvd, 0x0 */
uint32_t cr_i2s_txf_en : 1; /* [ 24], r/w, 0x1 */
uint32_t cr_i2s_rxf_en : 1; /* [ 25], r/w, 0x1 */
uint32_t cr_i2s_fer_en : 1; /* [ 26], r/w, 0x1 */
uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
} BF;
uint32_t WORD;
} i2s_int_sts;
/* 0x8 reserved */
uint8_t RESERVED0x8[8];
/* 0x10 : i2s_bclk_config */
union {
struct
{
uint32_t cr_bclk_div_l : 12; /* [11: 0], r/w, 0x1 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t cr_bclk_div_h : 12; /* [27:16], r/w, 0x1 */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
} BF;
uint32_t WORD;
} i2s_bclk_config;
/* 0x14 reserved */
uint8_t RESERVED0x14[108];
/* 0x80 : i2s_fifo_config_0 */
union {
struct
{
uint32_t i2s_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t i2s_dma_rx_en : 1; /* [ 1], r/w, 0x0 */
uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */
uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */
uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */
uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */
uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */
uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */
uint32_t cr_fifo_lr_merge : 1; /* [ 8], r/w, 0x0 */
uint32_t cr_fifo_lr_exchg : 1; /* [ 9], r/w, 0x0 */
uint32_t cr_fifo_24b_lj : 1; /* [ 10], r/w, 0x0 */
uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
} BF;
uint32_t WORD;
} i2s_fifo_config_0;
/* 0x84 : i2s_fifo_config_1 */
union {
struct
{
uint32_t tx_fifo_cnt : 5; /* [ 4: 0], r, 0x10 */
uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
uint32_t rx_fifo_cnt : 5; /* [12: 8], r, 0x0 */
uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
uint32_t tx_fifo_th : 4; /* [19:16], r/w, 0x0 */
uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
uint32_t rx_fifo_th : 4; /* [27:24], r/w, 0x0 */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
} BF;
uint32_t WORD;
} i2s_fifo_config_1;
/* 0x88 : i2s_fifo_wdata */
union {
struct
{
uint32_t i2s_fifo_wdata : 32; /* [31: 0], w, x */
} BF;
uint32_t WORD;
} i2s_fifo_wdata;
/* 0x8C : i2s_fifo_rdata */
union {
struct
{
uint32_t i2s_fifo_rdata : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} i2s_fifo_rdata;
/* 0x90 reserved */
uint8_t RESERVED0x90[108];
/* 0xFC : i2s_io_config */
union {
struct
{
uint32_t cr_i2s_txd_inv : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_i2s_rxd_inv : 1; /* [ 1], r/w, 0x0 */
uint32_t cr_i2s_fs_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t cr_i2s_bclk_inv : 1; /* [ 3], r/w, 0x0 */
uint32_t cr_deg_cnt : 3; /* [ 6: 4], r/w, 0x0 */
uint32_t cr_deg_en : 1; /* [ 7], r/w, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} i2s_io_config;
};
typedef volatile struct i2s_reg i2s_reg_t;
#endif /* __I2S_REG_H__ */

652
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/ir_reg.h
View File

@@ -1,652 +0,0 @@
/**
******************************************************************************
* @file ir_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __IR_REG_H__
#define __IR_REG_H__
#include "bl702.h"
/* 0x0 : irtx_config */
#define IRTX_CONFIG_OFFSET (0x0)
#define IR_CR_IRTX_EN IR_CR_IRTX_EN
#define IR_CR_IRTX_EN_POS (0U)
#define IR_CR_IRTX_EN_LEN (1U)
#define IR_CR_IRTX_EN_MSK (((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS)
#define IR_CR_IRTX_EN_UMSK (~(((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS))
#define IR_CR_IRTX_OUT_INV IR_CR_IRTX_OUT_INV
#define IR_CR_IRTX_OUT_INV_POS (1U)
#define IR_CR_IRTX_OUT_INV_LEN (1U)
#define IR_CR_IRTX_OUT_INV_MSK (((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS)
#define IR_CR_IRTX_OUT_INV_UMSK (~(((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS))
#define IR_CR_IRTX_MOD_EN IR_CR_IRTX_MOD_EN
#define IR_CR_IRTX_MOD_EN_POS (2U)
#define IR_CR_IRTX_MOD_EN_LEN (1U)
#define IR_CR_IRTX_MOD_EN_MSK (((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS)
#define IR_CR_IRTX_MOD_EN_UMSK (~(((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS))
#define IR_CR_IRTX_SWM_EN IR_CR_IRTX_SWM_EN
#define IR_CR_IRTX_SWM_EN_POS (3U)
#define IR_CR_IRTX_SWM_EN_LEN (1U)
#define IR_CR_IRTX_SWM_EN_MSK (((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS)
#define IR_CR_IRTX_SWM_EN_UMSK (~(((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS))
#define IR_CR_IRTX_DATA_EN IR_CR_IRTX_DATA_EN
#define IR_CR_IRTX_DATA_EN_POS (4U)
#define IR_CR_IRTX_DATA_EN_LEN (1U)
#define IR_CR_IRTX_DATA_EN_MSK (((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS)
#define IR_CR_IRTX_DATA_EN_UMSK (~(((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS))
#define IR_CR_IRTX_LOGIC0_HL_INV IR_CR_IRTX_LOGIC0_HL_INV
#define IR_CR_IRTX_LOGIC0_HL_INV_POS (5U)
#define IR_CR_IRTX_LOGIC0_HL_INV_LEN (1U)
#define IR_CR_IRTX_LOGIC0_HL_INV_MSK (((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS)
#define IR_CR_IRTX_LOGIC0_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS))
#define IR_CR_IRTX_LOGIC1_HL_INV IR_CR_IRTX_LOGIC1_HL_INV
#define IR_CR_IRTX_LOGIC1_HL_INV_POS (6U)
#define IR_CR_IRTX_LOGIC1_HL_INV_LEN (1U)
#define IR_CR_IRTX_LOGIC1_HL_INV_MSK (((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS)
#define IR_CR_IRTX_LOGIC1_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS))
#define IR_CR_IRTX_HEAD_EN IR_CR_IRTX_HEAD_EN
#define IR_CR_IRTX_HEAD_EN_POS (8U)
#define IR_CR_IRTX_HEAD_EN_LEN (1U)
#define IR_CR_IRTX_HEAD_EN_MSK (((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS)
#define IR_CR_IRTX_HEAD_EN_UMSK (~(((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS))
#define IR_CR_IRTX_HEAD_HL_INV IR_CR_IRTX_HEAD_HL_INV
#define IR_CR_IRTX_HEAD_HL_INV_POS (9U)
#define IR_CR_IRTX_HEAD_HL_INV_LEN (1U)
#define IR_CR_IRTX_HEAD_HL_INV_MSK (((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS)
#define IR_CR_IRTX_HEAD_HL_INV_UMSK (~(((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS))
#define IR_CR_IRTX_TAIL_EN IR_CR_IRTX_TAIL_EN
#define IR_CR_IRTX_TAIL_EN_POS (10U)
#define IR_CR_IRTX_TAIL_EN_LEN (1U)
#define IR_CR_IRTX_TAIL_EN_MSK (((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS)
#define IR_CR_IRTX_TAIL_EN_UMSK (~(((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS))
#define IR_CR_IRTX_TAIL_HL_INV IR_CR_IRTX_TAIL_HL_INV
#define IR_CR_IRTX_TAIL_HL_INV_POS (11U)
#define IR_CR_IRTX_TAIL_HL_INV_LEN (1U)
#define IR_CR_IRTX_TAIL_HL_INV_MSK (((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS)
#define IR_CR_IRTX_TAIL_HL_INV_UMSK (~(((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS))
#define IR_CR_IRTX_DATA_NUM IR_CR_IRTX_DATA_NUM
#define IR_CR_IRTX_DATA_NUM_POS (12U)
#define IR_CR_IRTX_DATA_NUM_LEN (6U)
#define IR_CR_IRTX_DATA_NUM_MSK (((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS)
#define IR_CR_IRTX_DATA_NUM_UMSK (~(((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS))
/* 0x4 : irtx_int_sts */
#define IRTX_INT_STS_OFFSET (0x4)
#define IRTX_END_INT IRTX_END_INT
#define IRTX_END_INT_POS (0U)
#define IRTX_END_INT_LEN (1U)
#define IRTX_END_INT_MSK (((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS)
#define IRTX_END_INT_UMSK (~(((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS))
#define IR_CR_IRTX_END_MASK IR_CR_IRTX_END_MASK
#define IR_CR_IRTX_END_MASK_POS (8U)
#define IR_CR_IRTX_END_MASK_LEN (1U)
#define IR_CR_IRTX_END_MASK_MSK (((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS)
#define IR_CR_IRTX_END_MASK_UMSK (~(((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS))
#define IR_CR_IRTX_END_CLR IR_CR_IRTX_END_CLR
#define IR_CR_IRTX_END_CLR_POS (16U)
#define IR_CR_IRTX_END_CLR_LEN (1U)
#define IR_CR_IRTX_END_CLR_MSK (((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS)
#define IR_CR_IRTX_END_CLR_UMSK (~(((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS))
#define IR_CR_IRTX_END_EN IR_CR_IRTX_END_EN
#define IR_CR_IRTX_END_EN_POS (24U)
#define IR_CR_IRTX_END_EN_LEN (1U)
#define IR_CR_IRTX_END_EN_MSK (((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS)
#define IR_CR_IRTX_END_EN_UMSK (~(((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS))
/* 0x8 : irtx_data_word0 */
#define IRTX_DATA_WORD0_OFFSET (0x8)
#define IR_CR_IRTX_DATA_WORD0 IR_CR_IRTX_DATA_WORD0
#define IR_CR_IRTX_DATA_WORD0_POS (0U)
#define IR_CR_IRTX_DATA_WORD0_LEN (32U)
#define IR_CR_IRTX_DATA_WORD0_MSK (((1U << IR_CR_IRTX_DATA_WORD0_LEN) - 1) << IR_CR_IRTX_DATA_WORD0_POS)
#define IR_CR_IRTX_DATA_WORD0_UMSK (~(((1U << IR_CR_IRTX_DATA_WORD0_LEN) - 1) << IR_CR_IRTX_DATA_WORD0_POS))
/* 0xC : irtx_data_word1 */
#define IRTX_DATA_WORD1_OFFSET (0xC)
#define IR_CR_IRTX_DATA_WORD1 IR_CR_IRTX_DATA_WORD1
#define IR_CR_IRTX_DATA_WORD1_POS (0U)
#define IR_CR_IRTX_DATA_WORD1_LEN (32U)
#define IR_CR_IRTX_DATA_WORD1_MSK (((1U << IR_CR_IRTX_DATA_WORD1_LEN) - 1) << IR_CR_IRTX_DATA_WORD1_POS)
#define IR_CR_IRTX_DATA_WORD1_UMSK (~(((1U << IR_CR_IRTX_DATA_WORD1_LEN) - 1) << IR_CR_IRTX_DATA_WORD1_POS))
/* 0x10 : irtx_pulse_width */
#define IRTX_PULSE_WIDTH_OFFSET (0x10)
#define IR_CR_IRTX_PW_UNIT IR_CR_IRTX_PW_UNIT
#define IR_CR_IRTX_PW_UNIT_POS (0U)
#define IR_CR_IRTX_PW_UNIT_LEN (12U)
#define IR_CR_IRTX_PW_UNIT_MSK (((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS)
#define IR_CR_IRTX_PW_UNIT_UMSK (~(((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS))
#define IR_CR_IRTX_MOD_PH0_W IR_CR_IRTX_MOD_PH0_W
#define IR_CR_IRTX_MOD_PH0_W_POS (16U)
#define IR_CR_IRTX_MOD_PH0_W_LEN (8U)
#define IR_CR_IRTX_MOD_PH0_W_MSK (((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS)
#define IR_CR_IRTX_MOD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS))
#define IR_CR_IRTX_MOD_PH1_W IR_CR_IRTX_MOD_PH1_W
#define IR_CR_IRTX_MOD_PH1_W_POS (24U)
#define IR_CR_IRTX_MOD_PH1_W_LEN (8U)
#define IR_CR_IRTX_MOD_PH1_W_MSK (((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS)
#define IR_CR_IRTX_MOD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS))
/* 0x14 : irtx_pw */
#define IRTX_PW_OFFSET (0x14)
#define IR_CR_IRTX_LOGIC0_PH0_W IR_CR_IRTX_LOGIC0_PH0_W
#define IR_CR_IRTX_LOGIC0_PH0_W_POS (0U)
#define IR_CR_IRTX_LOGIC0_PH0_W_LEN (4U)
#define IR_CR_IRTX_LOGIC0_PH0_W_MSK (((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS)
#define IR_CR_IRTX_LOGIC0_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS))
#define IR_CR_IRTX_LOGIC0_PH1_W IR_CR_IRTX_LOGIC0_PH1_W
#define IR_CR_IRTX_LOGIC0_PH1_W_POS (4U)
#define IR_CR_IRTX_LOGIC0_PH1_W_LEN (4U)
#define IR_CR_IRTX_LOGIC0_PH1_W_MSK (((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS)
#define IR_CR_IRTX_LOGIC0_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS))
#define IR_CR_IRTX_LOGIC1_PH0_W IR_CR_IRTX_LOGIC1_PH0_W
#define IR_CR_IRTX_LOGIC1_PH0_W_POS (8U)
#define IR_CR_IRTX_LOGIC1_PH0_W_LEN (4U)
#define IR_CR_IRTX_LOGIC1_PH0_W_MSK (((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS)
#define IR_CR_IRTX_LOGIC1_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS))
#define IR_CR_IRTX_LOGIC1_PH1_W IR_CR_IRTX_LOGIC1_PH1_W
#define IR_CR_IRTX_LOGIC1_PH1_W_POS (12U)
#define IR_CR_IRTX_LOGIC1_PH1_W_LEN (4U)
#define IR_CR_IRTX_LOGIC1_PH1_W_MSK (((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS)
#define IR_CR_IRTX_LOGIC1_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS))
#define IR_CR_IRTX_HEAD_PH0_W IR_CR_IRTX_HEAD_PH0_W
#define IR_CR_IRTX_HEAD_PH0_W_POS (16U)
#define IR_CR_IRTX_HEAD_PH0_W_LEN (4U)
#define IR_CR_IRTX_HEAD_PH0_W_MSK (((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS)
#define IR_CR_IRTX_HEAD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS))
#define IR_CR_IRTX_HEAD_PH1_W IR_CR_IRTX_HEAD_PH1_W
#define IR_CR_IRTX_HEAD_PH1_W_POS (20U)
#define IR_CR_IRTX_HEAD_PH1_W_LEN (4U)
#define IR_CR_IRTX_HEAD_PH1_W_MSK (((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS)
#define IR_CR_IRTX_HEAD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS))
#define IR_CR_IRTX_TAIL_PH0_W IR_CR_IRTX_TAIL_PH0_W
#define IR_CR_IRTX_TAIL_PH0_W_POS (24U)
#define IR_CR_IRTX_TAIL_PH0_W_LEN (4U)
#define IR_CR_IRTX_TAIL_PH0_W_MSK (((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS)
#define IR_CR_IRTX_TAIL_PH0_W_UMSK (~(((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS))
#define IR_CR_IRTX_TAIL_PH1_W IR_CR_IRTX_TAIL_PH1_W
#define IR_CR_IRTX_TAIL_PH1_W_POS (28U)
#define IR_CR_IRTX_TAIL_PH1_W_LEN (4U)
#define IR_CR_IRTX_TAIL_PH1_W_MSK (((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS)
#define IR_CR_IRTX_TAIL_PH1_W_UMSK (~(((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS))
/* 0x40 : irtx_swm_pw_0 */
#define IRTX_SWM_PW_0_OFFSET (0x40)
#define IR_CR_IRTX_SWM_PW_0 IR_CR_IRTX_SWM_PW_0
#define IR_CR_IRTX_SWM_PW_0_POS (0U)
#define IR_CR_IRTX_SWM_PW_0_LEN (32U)
#define IR_CR_IRTX_SWM_PW_0_MSK (((1U << IR_CR_IRTX_SWM_PW_0_LEN) - 1) << IR_CR_IRTX_SWM_PW_0_POS)
#define IR_CR_IRTX_SWM_PW_0_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_0_LEN) - 1) << IR_CR_IRTX_SWM_PW_0_POS))
/* 0x44 : irtx_swm_pw_1 */
#define IRTX_SWM_PW_1_OFFSET (0x44)
#define IR_CR_IRTX_SWM_PW_1 IR_CR_IRTX_SWM_PW_1
#define IR_CR_IRTX_SWM_PW_1_POS (0U)
#define IR_CR_IRTX_SWM_PW_1_LEN (32U)
#define IR_CR_IRTX_SWM_PW_1_MSK (((1U << IR_CR_IRTX_SWM_PW_1_LEN) - 1) << IR_CR_IRTX_SWM_PW_1_POS)
#define IR_CR_IRTX_SWM_PW_1_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_1_LEN) - 1) << IR_CR_IRTX_SWM_PW_1_POS))
/* 0x48 : irtx_swm_pw_2 */
#define IRTX_SWM_PW_2_OFFSET (0x48)
#define IR_CR_IRTX_SWM_PW_2 IR_CR_IRTX_SWM_PW_2
#define IR_CR_IRTX_SWM_PW_2_POS (0U)
#define IR_CR_IRTX_SWM_PW_2_LEN (32U)
#define IR_CR_IRTX_SWM_PW_2_MSK (((1U << IR_CR_IRTX_SWM_PW_2_LEN) - 1) << IR_CR_IRTX_SWM_PW_2_POS)
#define IR_CR_IRTX_SWM_PW_2_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_2_LEN) - 1) << IR_CR_IRTX_SWM_PW_2_POS))
/* 0x4C : irtx_swm_pw_3 */
#define IRTX_SWM_PW_3_OFFSET (0x4C)
#define IR_CR_IRTX_SWM_PW_3 IR_CR_IRTX_SWM_PW_3
#define IR_CR_IRTX_SWM_PW_3_POS (0U)
#define IR_CR_IRTX_SWM_PW_3_LEN (32U)
#define IR_CR_IRTX_SWM_PW_3_MSK (((1U << IR_CR_IRTX_SWM_PW_3_LEN) - 1) << IR_CR_IRTX_SWM_PW_3_POS)
#define IR_CR_IRTX_SWM_PW_3_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_3_LEN) - 1) << IR_CR_IRTX_SWM_PW_3_POS))
/* 0x50 : irtx_swm_pw_4 */
#define IRTX_SWM_PW_4_OFFSET (0x50)
#define IR_CR_IRTX_SWM_PW_4 IR_CR_IRTX_SWM_PW_4
#define IR_CR_IRTX_SWM_PW_4_POS (0U)
#define IR_CR_IRTX_SWM_PW_4_LEN (32U)
#define IR_CR_IRTX_SWM_PW_4_MSK (((1U << IR_CR_IRTX_SWM_PW_4_LEN) - 1) << IR_CR_IRTX_SWM_PW_4_POS)
#define IR_CR_IRTX_SWM_PW_4_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_4_LEN) - 1) << IR_CR_IRTX_SWM_PW_4_POS))
/* 0x54 : irtx_swm_pw_5 */
#define IRTX_SWM_PW_5_OFFSET (0x54)
#define IR_CR_IRTX_SWM_PW_5 IR_CR_IRTX_SWM_PW_5
#define IR_CR_IRTX_SWM_PW_5_POS (0U)
#define IR_CR_IRTX_SWM_PW_5_LEN (32U)
#define IR_CR_IRTX_SWM_PW_5_MSK (((1U << IR_CR_IRTX_SWM_PW_5_LEN) - 1) << IR_CR_IRTX_SWM_PW_5_POS)
#define IR_CR_IRTX_SWM_PW_5_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_5_LEN) - 1) << IR_CR_IRTX_SWM_PW_5_POS))
/* 0x58 : irtx_swm_pw_6 */
#define IRTX_SWM_PW_6_OFFSET (0x58)
#define IR_CR_IRTX_SWM_PW_6 IR_CR_IRTX_SWM_PW_6
#define IR_CR_IRTX_SWM_PW_6_POS (0U)
#define IR_CR_IRTX_SWM_PW_6_LEN (32U)
#define IR_CR_IRTX_SWM_PW_6_MSK (((1U << IR_CR_IRTX_SWM_PW_6_LEN) - 1) << IR_CR_IRTX_SWM_PW_6_POS)
#define IR_CR_IRTX_SWM_PW_6_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_6_LEN) - 1) << IR_CR_IRTX_SWM_PW_6_POS))
/* 0x5C : irtx_swm_pw_7 */
#define IRTX_SWM_PW_7_OFFSET (0x5C)
#define IR_CR_IRTX_SWM_PW_7 IR_CR_IRTX_SWM_PW_7
#define IR_CR_IRTX_SWM_PW_7_POS (0U)
#define IR_CR_IRTX_SWM_PW_7_LEN (32U)
#define IR_CR_IRTX_SWM_PW_7_MSK (((1U << IR_CR_IRTX_SWM_PW_7_LEN) - 1) << IR_CR_IRTX_SWM_PW_7_POS)
#define IR_CR_IRTX_SWM_PW_7_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_7_LEN) - 1) << IR_CR_IRTX_SWM_PW_7_POS))
/* 0x80 : irrx_config */
#define IRRX_CONFIG_OFFSET (0x80)
#define IR_CR_IRRX_EN IR_CR_IRRX_EN
#define IR_CR_IRRX_EN_POS (0U)
#define IR_CR_IRRX_EN_LEN (1U)
#define IR_CR_IRRX_EN_MSK (((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS)
#define IR_CR_IRRX_EN_UMSK (~(((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS))
#define IR_CR_IRRX_IN_INV IR_CR_IRRX_IN_INV
#define IR_CR_IRRX_IN_INV_POS (1U)
#define IR_CR_IRRX_IN_INV_LEN (1U)
#define IR_CR_IRRX_IN_INV_MSK (((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS)
#define IR_CR_IRRX_IN_INV_UMSK (~(((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS))
#define IR_CR_IRRX_MODE IR_CR_IRRX_MODE
#define IR_CR_IRRX_MODE_POS (2U)
#define IR_CR_IRRX_MODE_LEN (2U)
#define IR_CR_IRRX_MODE_MSK (((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS)
#define IR_CR_IRRX_MODE_UMSK (~(((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS))
#define IR_CR_IRRX_DEG_EN IR_CR_IRRX_DEG_EN
#define IR_CR_IRRX_DEG_EN_POS (4U)
#define IR_CR_IRRX_DEG_EN_LEN (1U)
#define IR_CR_IRRX_DEG_EN_MSK (((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS)
#define IR_CR_IRRX_DEG_EN_UMSK (~(((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS))
#define IR_CR_IRRX_DEG_CNT IR_CR_IRRX_DEG_CNT
#define IR_CR_IRRX_DEG_CNT_POS (8U)
#define IR_CR_IRRX_DEG_CNT_LEN (4U)
#define IR_CR_IRRX_DEG_CNT_MSK (((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS)
#define IR_CR_IRRX_DEG_CNT_UMSK (~(((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS))
/* 0x84 : irrx_int_sts */
#define IRRX_INT_STS_OFFSET (0x84)
#define IRRX_END_INT IRRX_END_INT
#define IRRX_END_INT_POS (0U)
#define IRRX_END_INT_LEN (1U)
#define IRRX_END_INT_MSK (((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS)
#define IRRX_END_INT_UMSK (~(((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS))
#define IR_CR_IRRX_END_MASK IR_CR_IRRX_END_MASK
#define IR_CR_IRRX_END_MASK_POS (8U)
#define IR_CR_IRRX_END_MASK_LEN (1U)
#define IR_CR_IRRX_END_MASK_MSK (((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS)
#define IR_CR_IRRX_END_MASK_UMSK (~(((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS))
#define IR_CR_IRRX_END_CLR IR_CR_IRRX_END_CLR
#define IR_CR_IRRX_END_CLR_POS (16U)
#define IR_CR_IRRX_END_CLR_LEN (1U)
#define IR_CR_IRRX_END_CLR_MSK (((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS)
#define IR_CR_IRRX_END_CLR_UMSK (~(((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS))
#define IR_CR_IRRX_END_EN IR_CR_IRRX_END_EN
#define IR_CR_IRRX_END_EN_POS (24U)
#define IR_CR_IRRX_END_EN_LEN (1U)
#define IR_CR_IRRX_END_EN_MSK (((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS)
#define IR_CR_IRRX_END_EN_UMSK (~(((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS))
/* 0x88 : irrx_pw_config */
#define IRRX_PW_CONFIG_OFFSET (0x88)
#define IR_CR_IRRX_DATA_TH IR_CR_IRRX_DATA_TH
#define IR_CR_IRRX_DATA_TH_POS (0U)
#define IR_CR_IRRX_DATA_TH_LEN (16U)
#define IR_CR_IRRX_DATA_TH_MSK (((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS)
#define IR_CR_IRRX_DATA_TH_UMSK (~(((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS))
#define IR_CR_IRRX_END_TH IR_CR_IRRX_END_TH
#define IR_CR_IRRX_END_TH_POS (16U)
#define IR_CR_IRRX_END_TH_LEN (16U)
#define IR_CR_IRRX_END_TH_MSK (((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS)
#define IR_CR_IRRX_END_TH_UMSK (~(((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS))
/* 0x90 : irrx_data_count */
#define IRRX_DATA_COUNT_OFFSET (0x90)
#define IR_STS_IRRX_DATA_CNT IR_STS_IRRX_DATA_CNT
#define IR_STS_IRRX_DATA_CNT_POS (0U)
#define IR_STS_IRRX_DATA_CNT_LEN (7U)
#define IR_STS_IRRX_DATA_CNT_MSK (((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS)
#define IR_STS_IRRX_DATA_CNT_UMSK (~(((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS))
/* 0x94 : irrx_data_word0 */
#define IRRX_DATA_WORD0_OFFSET (0x94)
#define IR_STS_IRRX_DATA_WORD0 IR_STS_IRRX_DATA_WORD0
#define IR_STS_IRRX_DATA_WORD0_POS (0U)
#define IR_STS_IRRX_DATA_WORD0_LEN (32U)
#define IR_STS_IRRX_DATA_WORD0_MSK (((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS)
#define IR_STS_IRRX_DATA_WORD0_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS))
/* 0x98 : irrx_data_word1 */
#define IRRX_DATA_WORD1_OFFSET (0x98)
#define IR_STS_IRRX_DATA_WORD1 IR_STS_IRRX_DATA_WORD1
#define IR_STS_IRRX_DATA_WORD1_POS (0U)
#define IR_STS_IRRX_DATA_WORD1_LEN (32U)
#define IR_STS_IRRX_DATA_WORD1_MSK (((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS)
#define IR_STS_IRRX_DATA_WORD1_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS))
/* 0xC0 : irrx_swm_fifo_config_0 */
#define IRRX_SWM_FIFO_CONFIG_0_OFFSET (0xC0)
#define IR_RX_FIFO_CLR IR_RX_FIFO_CLR
#define IR_RX_FIFO_CLR_POS (0U)
#define IR_RX_FIFO_CLR_LEN (1U)
#define IR_RX_FIFO_CLR_MSK (((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS)
#define IR_RX_FIFO_CLR_UMSK (~(((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS))
#define IR_RX_FIFO_OVERFLOW IR_RX_FIFO_OVERFLOW
#define IR_RX_FIFO_OVERFLOW_POS (2U)
#define IR_RX_FIFO_OVERFLOW_LEN (1U)
#define IR_RX_FIFO_OVERFLOW_MSK (((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS)
#define IR_RX_FIFO_OVERFLOW_UMSK (~(((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS))
#define IR_RX_FIFO_UNDERFLOW IR_RX_FIFO_UNDERFLOW
#define IR_RX_FIFO_UNDERFLOW_POS (3U)
#define IR_RX_FIFO_UNDERFLOW_LEN (1U)
#define IR_RX_FIFO_UNDERFLOW_MSK (((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS)
#define IR_RX_FIFO_UNDERFLOW_UMSK (~(((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS))
#define IR_RX_FIFO_CNT IR_RX_FIFO_CNT
#define IR_RX_FIFO_CNT_POS (4U)
#define IR_RX_FIFO_CNT_LEN (7U)
#define IR_RX_FIFO_CNT_MSK (((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS)
#define IR_RX_FIFO_CNT_UMSK (~(((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS))
/* 0xC4 : irrx_swm_fifo_rdata */
#define IRRX_SWM_FIFO_RDATA_OFFSET (0xC4)
#define IR_RX_FIFO_RDATA IR_RX_FIFO_RDATA
#define IR_RX_FIFO_RDATA_POS (0U)
#define IR_RX_FIFO_RDATA_LEN (16U)
#define IR_RX_FIFO_RDATA_MSK (((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS)
#define IR_RX_FIFO_RDATA_UMSK (~(((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS))
struct ir_reg {
/* 0x0 : irtx_config */
union {
struct
{
uint32_t cr_irtx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_irtx_out_inv : 1; /* [ 1], r/w, 0x0 */
uint32_t cr_irtx_mod_en : 1; /* [ 2], r/w, 0x0 */
uint32_t cr_irtx_swm_en : 1; /* [ 3], r/w, 0x0 */
uint32_t cr_irtx_data_en : 1; /* [ 4], r/w, 0x1 */
uint32_t cr_irtx_logic0_hl_inv : 1; /* [ 5], r/w, 0x0 */
uint32_t cr_irtx_logic1_hl_inv : 1; /* [ 6], r/w, 0x0 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t cr_irtx_head_en : 1; /* [ 8], r/w, 0x1 */
uint32_t cr_irtx_head_hl_inv : 1; /* [ 9], r/w, 0x0 */
uint32_t cr_irtx_tail_en : 1; /* [ 10], r/w, 0x1 */
uint32_t cr_irtx_tail_hl_inv : 1; /* [ 11], r/w, 0x0 */
uint32_t cr_irtx_data_num : 6; /* [17:12], r/w, 0x1f */
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
} BF;
uint32_t WORD;
} irtx_config;
/* 0x4 : irtx_int_sts */
union {
struct
{
uint32_t irtx_end_int : 1; /* [ 0], r, 0x0 */
uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */
uint32_t cr_irtx_end_mask : 1; /* [ 8], r/w, 0x1 */
uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
uint32_t cr_irtx_end_clr : 1; /* [ 16], w1c, 0x0 */
uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */
uint32_t cr_irtx_end_en : 1; /* [ 24], r/w, 0x1 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
} BF;
uint32_t WORD;
} irtx_int_sts;
/* 0x8 : irtx_data_word0 */
union {
struct
{
uint32_t cr_irtx_data_word0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_data_word0;
/* 0xC : irtx_data_word1 */
union {
struct
{
uint32_t cr_irtx_data_word1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_data_word1;
/* 0x10 : irtx_pulse_width */
union {
struct
{
uint32_t cr_irtx_pw_unit : 12; /* [11: 0], r/w, 0x464 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t cr_irtx_mod_ph0_w : 8; /* [23:16], r/w, 0x11 */
uint32_t cr_irtx_mod_ph1_w : 8; /* [31:24], r/w, 0x22 */
} BF;
uint32_t WORD;
} irtx_pulse_width;
/* 0x14 : irtx_pw */
union {
struct
{
uint32_t cr_irtx_logic0_ph0_w : 4; /* [ 3: 0], r/w, 0x0 */
uint32_t cr_irtx_logic0_ph1_w : 4; /* [ 7: 4], r/w, 0x0 */
uint32_t cr_irtx_logic1_ph0_w : 4; /* [11: 8], r/w, 0x0 */
uint32_t cr_irtx_logic1_ph1_w : 4; /* [15:12], r/w, 0x2 */
uint32_t cr_irtx_head_ph0_w : 4; /* [19:16], r/w, 0xf */
uint32_t cr_irtx_head_ph1_w : 4; /* [23:20], r/w, 0x7 */
uint32_t cr_irtx_tail_ph0_w : 4; /* [27:24], r/w, 0x0 */
uint32_t cr_irtx_tail_ph1_w : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_pw;
/* 0x18 reserved */
uint8_t RESERVED0x18[40];
/* 0x40 : irtx_swm_pw_0 */
union {
struct
{
uint32_t cr_irtx_swm_pw_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_swm_pw_0;
/* 0x44 : irtx_swm_pw_1 */
union {
struct
{
uint32_t cr_irtx_swm_pw_1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_swm_pw_1;
/* 0x48 : irtx_swm_pw_2 */
union {
struct
{
uint32_t cr_irtx_swm_pw_2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_swm_pw_2;
/* 0x4C : irtx_swm_pw_3 */
union {
struct
{
uint32_t cr_irtx_swm_pw_3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_swm_pw_3;
/* 0x50 : irtx_swm_pw_4 */
union {
struct
{
uint32_t cr_irtx_swm_pw_4 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_swm_pw_4;
/* 0x54 : irtx_swm_pw_5 */
union {
struct
{
uint32_t cr_irtx_swm_pw_5 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_swm_pw_5;
/* 0x58 : irtx_swm_pw_6 */
union {
struct
{
uint32_t cr_irtx_swm_pw_6 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_swm_pw_6;
/* 0x5C : irtx_swm_pw_7 */
union {
struct
{
uint32_t cr_irtx_swm_pw_7 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} irtx_swm_pw_7;
/* 0x60 reserved */
uint8_t RESERVED0x60[32];
/* 0x80 : irrx_config */
union {
struct
{
uint32_t cr_irrx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_irrx_in_inv : 1; /* [ 1], r/w, 0x1 */
uint32_t cr_irrx_mode : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t cr_irrx_deg_en : 1; /* [ 4], r/w, 0x0 */
uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
uint32_t cr_irrx_deg_cnt : 4; /* [11: 8], r/w, 0x0 */
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
} BF;
uint32_t WORD;
} irrx_config;
/* 0x84 : irrx_int_sts */
union {
struct
{
uint32_t irrx_end_int : 1; /* [ 0], r, 0x0 */
uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */
uint32_t cr_irrx_end_mask : 1; /* [ 8], r/w, 0x1 */
uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
uint32_t cr_irrx_end_clr : 1; /* [ 16], w1c, 0x0 */
uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */
uint32_t cr_irrx_end_en : 1; /* [ 24], r/w, 0x1 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
} BF;
uint32_t WORD;
} irrx_int_sts;
/* 0x88 : irrx_pw_config */
union {
struct
{
uint32_t cr_irrx_data_th : 16; /* [15: 0], r/w, 0xd47 */
uint32_t cr_irrx_end_th : 16; /* [31:16], r/w, 0x2327 */
} BF;
uint32_t WORD;
} irrx_pw_config;
/* 0x8c reserved */
uint8_t RESERVED0x8c[4];
/* 0x90 : irrx_data_count */
union {
struct
{
uint32_t sts_irrx_data_cnt : 7; /* [ 6: 0], r, 0x0 */
uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */
} BF;
uint32_t WORD;
} irrx_data_count;
/* 0x94 : irrx_data_word0 */
union {
struct
{
uint32_t sts_irrx_data_word0 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} irrx_data_word0;
/* 0x98 : irrx_data_word1 */
union {
struct
{
uint32_t sts_irrx_data_word1 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} irrx_data_word1;
/* 0x9c reserved */
uint8_t RESERVED0x9c[36];
/* 0xC0 : irrx_swm_fifo_config_0 */
union {
struct
{
uint32_t rx_fifo_clr : 1; /* [ 0], w1c, 0x0 */
uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
uint32_t rx_fifo_overflow : 1; /* [ 2], r, 0x0 */
uint32_t rx_fifo_underflow : 1; /* [ 3], r, 0x0 */
uint32_t rx_fifo_cnt : 7; /* [10: 4], r, 0x0 */
uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
} BF;
uint32_t WORD;
} irrx_swm_fifo_config_0;
/* 0xC4 : irrx_swm_fifo_rdata */
union {
struct
{
uint32_t rx_fifo_rdata : 16; /* [15: 0], r, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} irrx_swm_fifo_rdata;
};
typedef volatile struct ir_reg ir_reg_t;
#endif /* __IR_REG_H__ */

194
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/kys_reg.h
View File

@@ -1,194 +0,0 @@
/**
******************************************************************************
* @file kys_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __KYS_REG_H__
#define __KYS_REG_H__
#include "bl702.h"
/* 0x0 : ks_ctrl */
#define KYS_KS_CTRL_OFFSET (0x0)
#define KYS_KS_EN KYS_KS_EN
#define KYS_KS_EN_POS (0U)
#define KYS_KS_EN_LEN (1U)
#define KYS_KS_EN_MSK (((1U << KYS_KS_EN_LEN) - 1) << KYS_KS_EN_POS)
#define KYS_KS_EN_UMSK (~(((1U << KYS_KS_EN_LEN) - 1) << KYS_KS_EN_POS))
#define KYS_GHOST_EN KYS_GHOST_EN
#define KYS_GHOST_EN_POS (2U)
#define KYS_GHOST_EN_LEN (1U)
#define KYS_GHOST_EN_MSK (((1U << KYS_GHOST_EN_LEN) - 1) << KYS_GHOST_EN_POS)
#define KYS_GHOST_EN_UMSK (~(((1U << KYS_GHOST_EN_LEN) - 1) << KYS_GHOST_EN_POS))
#define KYS_DEG_EN KYS_DEG_EN
#define KYS_DEG_EN_POS (3U)
#define KYS_DEG_EN_LEN (1U)
#define KYS_DEG_EN_MSK (((1U << KYS_DEG_EN_LEN) - 1) << KYS_DEG_EN_POS)
#define KYS_DEG_EN_UMSK (~(((1U << KYS_DEG_EN_LEN) - 1) << KYS_DEG_EN_POS))
#define KYS_DEG_CNT KYS_DEG_CNT
#define KYS_DEG_CNT_POS (4U)
#define KYS_DEG_CNT_LEN (4U)
#define KYS_DEG_CNT_MSK (((1U << KYS_DEG_CNT_LEN) - 1) << KYS_DEG_CNT_POS)
#define KYS_DEG_CNT_UMSK (~(((1U << KYS_DEG_CNT_LEN) - 1) << KYS_DEG_CNT_POS))
#define KYS_RC_EXT KYS_RC_EXT
#define KYS_RC_EXT_POS (8U)
#define KYS_RC_EXT_LEN (2U)
#define KYS_RC_EXT_MSK (((1U << KYS_RC_EXT_LEN) - 1) << KYS_RC_EXT_POS)
#define KYS_RC_EXT_UMSK (~(((1U << KYS_RC_EXT_LEN) - 1) << KYS_RC_EXT_POS))
#define KYS_ROW_NUM KYS_ROW_NUM
#define KYS_ROW_NUM_POS (16U)
#define KYS_ROW_NUM_LEN (3U)
#define KYS_ROW_NUM_MSK (((1U << KYS_ROW_NUM_LEN) - 1) << KYS_ROW_NUM_POS)
#define KYS_ROW_NUM_UMSK (~(((1U << KYS_ROW_NUM_LEN) - 1) << KYS_ROW_NUM_POS))
#define KYS_COL_NUM KYS_COL_NUM
#define KYS_COL_NUM_POS (20U)
#define KYS_COL_NUM_LEN (5U)
#define KYS_COL_NUM_MSK (((1U << KYS_COL_NUM_LEN) - 1) << KYS_COL_NUM_POS)
#define KYS_COL_NUM_UMSK (~(((1U << KYS_COL_NUM_LEN) - 1) << KYS_COL_NUM_POS))
/* 0x10 : ks_int_en */
#define KYS_KS_INT_EN_OFFSET (0x10)
#define KYS_KS_INT_EN KYS_KS_INT_EN
#define KYS_KS_INT_EN_POS (0U)
#define KYS_KS_INT_EN_LEN (1U)
#define KYS_KS_INT_EN_MSK (((1U << KYS_KS_INT_EN_LEN) - 1) << KYS_KS_INT_EN_POS)
#define KYS_KS_INT_EN_UMSK (~(((1U << KYS_KS_INT_EN_LEN) - 1) << KYS_KS_INT_EN_POS))
/* 0x14 : ks_int_sts */
#define KYS_KS_INT_STS_OFFSET (0x14)
#define KYS_KEYCODE_VALID KYS_KEYCODE_VALID
#define KYS_KEYCODE_VALID_POS (0U)
#define KYS_KEYCODE_VALID_LEN (4U)
#define KYS_KEYCODE_VALID_MSK (((1U << KYS_KEYCODE_VALID_LEN) - 1) << KYS_KEYCODE_VALID_POS)
#define KYS_KEYCODE_VALID_UMSK (~(((1U << KYS_KEYCODE_VALID_LEN) - 1) << KYS_KEYCODE_VALID_POS))
/* 0x18 : keycode_clr */
#define KYS_KEYCODE_CLR_OFFSET (0x18)
#define KYS_KEYCODE_CLR KYS_KEYCODE_CLR
#define KYS_KEYCODE_CLR_POS (0U)
#define KYS_KEYCODE_CLR_LEN (4U)
#define KYS_KEYCODE_CLR_MSK (((1U << KYS_KEYCODE_CLR_LEN) - 1) << KYS_KEYCODE_CLR_POS)
#define KYS_KEYCODE_CLR_UMSK (~(((1U << KYS_KEYCODE_CLR_LEN) - 1) << KYS_KEYCODE_CLR_POS))
/* 0x1C : keycode_value */
#define KYS_KEYCODE_VALUE_OFFSET (0x1C)
#define KYS_KEYCODE0 KYS_KEYCODE0
#define KYS_KEYCODE0_POS (0U)
#define KYS_KEYCODE0_LEN (8U)
#define KYS_KEYCODE0_MSK (((1U << KYS_KEYCODE0_LEN) - 1) << KYS_KEYCODE0_POS)
#define KYS_KEYCODE0_UMSK (~(((1U << KYS_KEYCODE0_LEN) - 1) << KYS_KEYCODE0_POS))
#define KYS_KEYCODE1 KYS_KEYCODE1
#define KYS_KEYCODE1_POS (8U)
#define KYS_KEYCODE1_LEN (8U)
#define KYS_KEYCODE1_MSK (((1U << KYS_KEYCODE1_LEN) - 1) << KYS_KEYCODE1_POS)
#define KYS_KEYCODE1_UMSK (~(((1U << KYS_KEYCODE1_LEN) - 1) << KYS_KEYCODE1_POS))
#define KYS_KEYCODE2 KYS_KEYCODE2
#define KYS_KEYCODE2_POS (16U)
#define KYS_KEYCODE2_LEN (8U)
#define KYS_KEYCODE2_MSK (((1U << KYS_KEYCODE2_LEN) - 1) << KYS_KEYCODE2_POS)
#define KYS_KEYCODE2_UMSK (~(((1U << KYS_KEYCODE2_LEN) - 1) << KYS_KEYCODE2_POS))
#define KYS_KEYCODE3 KYS_KEYCODE3
#define KYS_KEYCODE3_POS (24U)
#define KYS_KEYCODE3_LEN (8U)
#define KYS_KEYCODE3_MSK (((1U << KYS_KEYCODE3_LEN) - 1) << KYS_KEYCODE3_POS)
#define KYS_KEYCODE3_UMSK (~(((1U << KYS_KEYCODE3_LEN) - 1) << KYS_KEYCODE3_POS))
struct kys_reg {
/* 0x0 : ks_ctrl */
union {
struct
{
uint32_t ks_en : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
uint32_t ghost_en : 1; /* [ 2], r/w, 0x0 */
uint32_t deg_en : 1; /* [ 3], r/w, 0x0 */
uint32_t deg_cnt : 4; /* [ 7: 4], r/w, 0x0 */
uint32_t rc_ext : 2; /* [ 9: 8], r/w, 0x3 */
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
uint32_t row_num : 3; /* [18:16], r/w, 0x7 */
uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
uint32_t col_num : 5; /* [24:20], r/w, 0x13 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
} BF;
uint32_t WORD;
} ks_ctrl;
/* 0x4 reserved */
uint8_t RESERVED0x4[12];
/* 0x10 : ks_int_en */
union {
struct
{
uint32_t ks_int_en : 1; /* [ 0], r/w, 0x1 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
} BF;
uint32_t WORD;
} ks_int_en;
/* 0x14 : ks_int_sts */
union {
struct
{
uint32_t keycode_valid : 4; /* [ 3: 0], r, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} ks_int_sts;
/* 0x18 : keycode_clr */
union {
struct
{
uint32_t keycode_clr : 4; /* [ 3: 0], w1c, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} keycode_clr;
/* 0x1C : keycode_value */
union {
struct
{
uint32_t keycode0 : 8; /* [ 7: 0], r, 0xff */
uint32_t keycode1 : 8; /* [15: 8], r, 0xff */
uint32_t keycode2 : 8; /* [23:16], r, 0xff */
uint32_t keycode3 : 8; /* [31:24], r, 0xff */
} BF;
uint32_t WORD;
} keycode_value;
};
typedef volatile struct kys_reg kys_reg_t;
#endif /* __KYS_REG_H__ */

366
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/l1c_reg.h
View File

@@ -1,366 +0,0 @@
/**
******************************************************************************
* @file l1c_reg.h
* @version V1.2
* @date 2020-07-08
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __L1C_REG_H__
#define __L1C_REG_H__
#include "bl702.h"
/* 0x0 : l1c_config */
#define L1C_CONFIG_OFFSET (0x0)
#define L1C_CACHEABLE L1C_CACHEABLE
#define L1C_CACHEABLE_POS (0U)
#define L1C_CACHEABLE_LEN (1U)
#define L1C_CACHEABLE_MSK (((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS)
#define L1C_CACHEABLE_UMSK (~(((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS))
#define L1C_CNT_EN L1C_CNT_EN
#define L1C_CNT_EN_POS (1U)
#define L1C_CNT_EN_LEN (1U)
#define L1C_CNT_EN_MSK (((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS)
#define L1C_CNT_EN_UMSK (~(((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS))
#define L1C_INVALID_EN L1C_INVALID_EN
#define L1C_INVALID_EN_POS (2U)
#define L1C_INVALID_EN_LEN (1U)
#define L1C_INVALID_EN_MSK (((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS)
#define L1C_INVALID_EN_UMSK (~(((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS))
#define L1C_INVALID_DONE L1C_INVALID_DONE
#define L1C_INVALID_DONE_POS (3U)
#define L1C_INVALID_DONE_LEN (1U)
#define L1C_INVALID_DONE_MSK (((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS)
#define L1C_INVALID_DONE_UMSK (~(((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS))
#define L1C_WT_EN L1C_WT_EN
#define L1C_WT_EN_POS (4U)
#define L1C_WT_EN_LEN (1U)
#define L1C_WT_EN_MSK (((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS)
#define L1C_WT_EN_UMSK (~(((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS))
#define L1C_WB_EN L1C_WB_EN
#define L1C_WB_EN_POS (5U)
#define L1C_WB_EN_LEN (1U)
#define L1C_WB_EN_MSK (((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS)
#define L1C_WB_EN_UMSK (~(((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS))
#define L1C_WA_EN L1C_WA_EN
#define L1C_WA_EN_POS (6U)
#define L1C_WA_EN_LEN (1U)
#define L1C_WA_EN_MSK (((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS)
#define L1C_WA_EN_UMSK (~(((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS))
#define L1C_RANDOM_REPLACE L1C_RANDOM_REPLACE
#define L1C_RANDOM_REPLACE_POS (7U)
#define L1C_RANDOM_REPLACE_LEN (1U)
#define L1C_RANDOM_REPLACE_MSK (((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS)
#define L1C_RANDOM_REPLACE_UMSK (~(((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS))
#define L1C_WAY_DIS L1C_WAY_DIS
#define L1C_WAY_DIS_POS (8U)
#define L1C_WAY_DIS_LEN (4U)
#define L1C_WAY_DIS_MSK (((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS)
#define L1C_WAY_DIS_UMSK (~(((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS))
#define L1C_IROM_2T_ACCESS L1C_IROM_2T_ACCESS
#define L1C_IROM_2T_ACCESS_POS (12U)
#define L1C_IROM_2T_ACCESS_LEN (1U)
#define L1C_IROM_2T_ACCESS_MSK (((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS)
#define L1C_IROM_2T_ACCESS_UMSK (~(((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS))
#define L1C_BYPASS L1C_BYPASS
#define L1C_BYPASS_POS (14U)
#define L1C_BYPASS_LEN (1U)
#define L1C_BYPASS_MSK (((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS)
#define L1C_BYPASS_UMSK (~(((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS))
#define L1C_BMX_ERR_EN L1C_BMX_ERR_EN
#define L1C_BMX_ERR_EN_POS (15U)
#define L1C_BMX_ERR_EN_LEN (1U)
#define L1C_BMX_ERR_EN_MSK (((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS)
#define L1C_BMX_ERR_EN_UMSK (~(((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS))
#define L1C_BMX_ARB_MODE L1C_BMX_ARB_MODE
#define L1C_BMX_ARB_MODE_POS (16U)
#define L1C_BMX_ARB_MODE_LEN (2U)
#define L1C_BMX_ARB_MODE_MSK (((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS)
#define L1C_BMX_ARB_MODE_UMSK (~(((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS))
#define L1C_BMX_TIMEOUT_EN L1C_BMX_TIMEOUT_EN
#define L1C_BMX_TIMEOUT_EN_POS (20U)
#define L1C_BMX_TIMEOUT_EN_LEN (4U)
#define L1C_BMX_TIMEOUT_EN_MSK (((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS)
#define L1C_BMX_TIMEOUT_EN_UMSK (~(((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS))
#define L1C_BMX_BUSY_OPTION_DIS L1C_BMX_BUSY_OPTION_DIS
#define L1C_BMX_BUSY_OPTION_DIS_POS (24U)
#define L1C_BMX_BUSY_OPTION_DIS_LEN (1U)
#define L1C_BMX_BUSY_OPTION_DIS_MSK (((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS)
#define L1C_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS))
#define L1C_EARLY_RESP_DIS L1C_EARLY_RESP_DIS
#define L1C_EARLY_RESP_DIS_POS (25U)
#define L1C_EARLY_RESP_DIS_LEN (1U)
#define L1C_EARLY_RESP_DIS_MSK (((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS)
#define L1C_EARLY_RESP_DIS_UMSK (~(((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS))
#define L1C_WRAP_DIS L1C_WRAP_DIS
#define L1C_WRAP_DIS_POS (26U)
#define L1C_WRAP_DIS_LEN (1U)
#define L1C_WRAP_DIS_MSK (((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS)
#define L1C_WRAP_DIS_UMSK (~(((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS))
#define L1C_FLUSH_EN L1C_FLUSH_EN
#define L1C_FLUSH_EN_POS (28U)
#define L1C_FLUSH_EN_LEN (1U)
#define L1C_FLUSH_EN_MSK (((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS)
#define L1C_FLUSH_EN_UMSK (~(((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS))
#define L1C_FLUSH_DONE L1C_FLUSH_DONE
#define L1C_FLUSH_DONE_POS (29U)
#define L1C_FLUSH_DONE_LEN (1U)
#define L1C_FLUSH_DONE_MSK (((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS)
#define L1C_FLUSH_DONE_UMSK (~(((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS))
/* 0x4 : hit_cnt_lsb */
#define L1C_HIT_CNT_LSB_OFFSET (0x4)
#define L1C_HIT_CNT_LSB L1C_HIT_CNT_LSB
#define L1C_HIT_CNT_LSB_POS (0U)
#define L1C_HIT_CNT_LSB_LEN (32U)
#define L1C_HIT_CNT_LSB_MSK (((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS)
#define L1C_HIT_CNT_LSB_UMSK (~(((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS))
/* 0x8 : hit_cnt_msb */
#define L1C_HIT_CNT_MSB_OFFSET (0x8)
#define L1C_HIT_CNT_MSB L1C_HIT_CNT_MSB
#define L1C_HIT_CNT_MSB_POS (0U)
#define L1C_HIT_CNT_MSB_LEN (32U)
#define L1C_HIT_CNT_MSB_MSK (((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS)
#define L1C_HIT_CNT_MSB_UMSK (~(((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS))
/* 0xC : miss_cnt */
#define L1C_MISS_CNT_OFFSET (0xC)
#define L1C_MISS_CNT L1C_MISS_CNT
#define L1C_MISS_CNT_POS (0U)
#define L1C_MISS_CNT_LEN (32U)
#define L1C_MISS_CNT_MSK (((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS)
#define L1C_MISS_CNT_UMSK (~(((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS))
/* 0x10 : l1c_misc */
#define L1C_MISC_OFFSET (0x10)
#define L1C_FSM L1C_FSM
#define L1C_FSM_POS (28U)
#define L1C_FSM_LEN (3U)
#define L1C_FSM_MSK (((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS)
#define L1C_FSM_UMSK (~(((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS))
/* 0x200 : l1c_bmx_err_addr_en */
#define L1C_BMX_ERR_ADDR_EN_OFFSET (0x200)
#define L1C_BMX_ERR_ADDR_DIS L1C_BMX_ERR_ADDR_DIS
#define L1C_BMX_ERR_ADDR_DIS_POS (0U)
#define L1C_BMX_ERR_ADDR_DIS_LEN (1U)
#define L1C_BMX_ERR_ADDR_DIS_MSK (((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS)
#define L1C_BMX_ERR_ADDR_DIS_UMSK (~(((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS))
#define L1C_BMX_ERR_DEC L1C_BMX_ERR_DEC
#define L1C_BMX_ERR_DEC_POS (4U)
#define L1C_BMX_ERR_DEC_LEN (1U)
#define L1C_BMX_ERR_DEC_MSK (((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS)
#define L1C_BMX_ERR_DEC_UMSK (~(((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS))
#define L1C_BMX_ERR_TZ L1C_BMX_ERR_TZ
#define L1C_BMX_ERR_TZ_POS (5U)
#define L1C_BMX_ERR_TZ_LEN (1U)
#define L1C_BMX_ERR_TZ_MSK (((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS)
#define L1C_BMX_ERR_TZ_UMSK (~(((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS))
#define L1C_HSEL_OPTION L1C_HSEL_OPTION
#define L1C_HSEL_OPTION_POS (16U)
#define L1C_HSEL_OPTION_LEN (4U)
#define L1C_HSEL_OPTION_MSK (((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS)
#define L1C_HSEL_OPTION_UMSK (~(((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS))
/* 0x204 : l1c_bmx_err_addr */
#define L1C_BMX_ERR_ADDR_OFFSET (0x204)
#define L1C_BMX_ERR_ADDR L1C_BMX_ERR_ADDR
#define L1C_BMX_ERR_ADDR_POS (0U)
#define L1C_BMX_ERR_ADDR_LEN (32U)
#define L1C_BMX_ERR_ADDR_MSK (((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS)
#define L1C_BMX_ERR_ADDR_UMSK (~(((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS))
/* 0x208 : irom1_misr_dataout_0 */
#define L1C_IROM1_MISR_DATAOUT_0_OFFSET (0x208)
#define L1C_IROM1_MISR_DATAOUT_0 L1C_IROM1_MISR_DATAOUT_0
#define L1C_IROM1_MISR_DATAOUT_0_POS (0U)
#define L1C_IROM1_MISR_DATAOUT_0_LEN (32U)
#define L1C_IROM1_MISR_DATAOUT_0_MSK (((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS)
#define L1C_IROM1_MISR_DATAOUT_0_UMSK (~(((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS))
/* 0x20C : irom1_misr_dataout_1 */
#define L1C_IROM1_MISR_DATAOUT_1_OFFSET (0x20C)
#define L1C_IROM1_MISR_DATAOUT_1 L1C_IROM1_MISR_DATAOUT_1
#define L1C_IROM1_MISR_DATAOUT_1_POS (0U)
#define L1C_IROM1_MISR_DATAOUT_1_LEN (32U)
#define L1C_IROM1_MISR_DATAOUT_1_MSK (((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS)
#define L1C_IROM1_MISR_DATAOUT_1_UMSK (~(((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS))
/* 0x210 : cpu_clk_gate */
#define L1C_CPU_CLK_GATE_OFFSET (0x210)
#define L1C_FORCE_E21_CLOCK_ON_0 L1C_FORCE_E21_CLOCK_ON_0
#define L1C_FORCE_E21_CLOCK_ON_0_POS (0U)
#define L1C_FORCE_E21_CLOCK_ON_0_LEN (1U)
#define L1C_FORCE_E21_CLOCK_ON_0_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS)
#define L1C_FORCE_E21_CLOCK_ON_0_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS))
#define L1C_FORCE_E21_CLOCK_ON_1 L1C_FORCE_E21_CLOCK_ON_1
#define L1C_FORCE_E21_CLOCK_ON_1_POS (1U)
#define L1C_FORCE_E21_CLOCK_ON_1_LEN (1U)
#define L1C_FORCE_E21_CLOCK_ON_1_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS)
#define L1C_FORCE_E21_CLOCK_ON_1_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS))
#define L1C_FORCE_E21_CLOCK_ON_2 L1C_FORCE_E21_CLOCK_ON_2
#define L1C_FORCE_E21_CLOCK_ON_2_POS (2U)
#define L1C_FORCE_E21_CLOCK_ON_2_LEN (1U)
#define L1C_FORCE_E21_CLOCK_ON_2_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS)
#define L1C_FORCE_E21_CLOCK_ON_2_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS))
struct l1c_reg {
/* 0x0 : l1c_config */
union {
struct
{
uint32_t l1c_cacheable : 1; /* [ 0], r/w, 0x0 */
uint32_t l1c_cnt_en : 1; /* [ 1], r/w, 0x0 */
uint32_t l1c_invalid_en : 1; /* [ 2], r/w, 0x0 */
uint32_t l1c_invalid_done : 1; /* [ 3], r, 0x0 */
uint32_t l1c_wt_en : 1; /* [ 4], r/w, 0x0 */
uint32_t l1c_wb_en : 1; /* [ 5], r/w, 0x1 */
uint32_t l1c_wa_en : 1; /* [ 6], r/w, 0x1 */
uint32_t l1c_random_replace : 1; /* [ 7], r/w, 0x0 */
uint32_t l1c_way_dis : 4; /* [11: 8], r/w, 0xf */
uint32_t irom_2t_access : 1; /* [ 12], r/w, 0x0 */
uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */
uint32_t l1c_bypass : 1; /* [ 14], r/w, 0x0 */
uint32_t l1c_bmx_err_en : 1; /* [ 15], r/w, 0x0 */
uint32_t l1c_bmx_arb_mode : 2; /* [17:16], r/w, 0x0 */
uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
uint32_t l1c_bmx_timeout_en : 4; /* [23:20], r/w, 0x0 */
uint32_t l1c_bmx_busy_option_dis : 1; /* [ 24], r/w, 0x0 */
uint32_t early_resp_dis : 1; /* [ 25], r/w, 0x1 */
uint32_t wrap_dis : 1; /* [ 26], r/w, 0x1 */
uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */
uint32_t l1c_flush_en : 1; /* [ 28], r/w, 0x0 */
uint32_t l1c_flush_done : 1; /* [ 29], r, 0x0 */
uint32_t reserved_31_30 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} l1c_config;
/* 0x4 : hit_cnt_lsb */
union {
struct
{
uint32_t hit_cnt_lsb : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} hit_cnt_lsb;
/* 0x8 : hit_cnt_msb */
union {
struct
{
uint32_t hit_cnt_msb : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} hit_cnt_msb;
/* 0xC : miss_cnt */
union {
struct
{
uint32_t miss_cnt : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} miss_cnt;
/* 0x10 : l1c_misc */
union {
struct
{
uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */
uint32_t l1c_fsm : 3; /* [30:28], r, 0x0 */
uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
} BF;
uint32_t WORD;
} l1c_misc;
/* 0x14 reserved */
uint8_t RESERVED0x14[492];
/* 0x200 : l1c_bmx_err_addr_en */
union {
struct
{
uint32_t l1c_bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
uint32_t l1c_bmx_err_dec : 1; /* [ 4], r, 0x0 */
uint32_t l1c_bmx_err_tz : 1; /* [ 5], r, 0x0 */
uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
uint32_t l1c_hsel_option : 4; /* [19:16], r/w, 0x0 */
uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
} BF;
uint32_t WORD;
} l1c_bmx_err_addr_en;
/* 0x204 : l1c_bmx_err_addr */
union {
struct
{
uint32_t l1c_bmx_err_addr : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} l1c_bmx_err_addr;
/* 0x208 : irom1_misr_dataout_0 */
union {
struct
{
uint32_t irom1_misr_dataout_0 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} irom1_misr_dataout_0;
/* 0x20C : irom1_misr_dataout_1 */
union {
struct
{
uint32_t irom1_misr_dataout_1 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} irom1_misr_dataout_1;
/* 0x210 : cpu_clk_gate */
union {
struct
{
uint32_t force_e21_clock_on_0 : 1; /* [ 0], r/w, 0x0 */
uint32_t force_e21_clock_on_1 : 1; /* [ 1], r/w, 0x0 */
uint32_t force_e21_clock_on_2 : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} cpu_clk_gate;
};
typedef volatile struct l1c_reg l1c_reg_t;
#endif /* __L1C_REG_H__ */

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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/mjpeg_reg.h
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351
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/pdm_reg.h
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@@ -1,351 +0,0 @@
/**
******************************************************************************
* @file pdm_reg.h
* @version V1.2
* @date 2020-02-13
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __PDM_REG_H__
#define __PDM_REG_H__
#include "bl702.h"
/* 0x0 : pdm_datapath_config */
#define PDM_DATAPATH_CONFIG_OFFSET (0x0)
#define PDM_EN PDM_EN
#define PDM_EN_POS (0U)
#define PDM_EN_LEN (1U)
#define PDM_EN_MSK (((1U << PDM_EN_LEN) - 1) << PDM_EN_POS)
#define PDM_EN_UMSK (~(((1U << PDM_EN_LEN) - 1) << PDM_EN_POS))
#define PDM_RX_SEL_128FS PDM_RX_SEL_128FS
#define PDM_RX_SEL_128FS_POS (2U)
#define PDM_RX_SEL_128FS_LEN (1U)
#define PDM_RX_SEL_128FS_MSK (((1U << PDM_RX_SEL_128FS_LEN) - 1) << PDM_RX_SEL_128FS_POS)
#define PDM_RX_SEL_128FS_UMSK (~(((1U << PDM_RX_SEL_128FS_LEN) - 1) << PDM_RX_SEL_128FS_POS))
#define PDM_TX_SEL_128FS PDM_TX_SEL_128FS
#define PDM_TX_SEL_128FS_POS (3U)
#define PDM_TX_SEL_128FS_LEN (1U)
#define PDM_TX_SEL_128FS_MSK (((1U << PDM_TX_SEL_128FS_LEN) - 1) << PDM_TX_SEL_128FS_POS)
#define PDM_TX_SEL_128FS_UMSK (~(((1U << PDM_TX_SEL_128FS_LEN) - 1) << PDM_TX_SEL_128FS_POS))
#define PDM_DC_MUL PDM_DC_MUL
#define PDM_DC_MUL_POS (4U)
#define PDM_DC_MUL_LEN (8U)
#define PDM_DC_MUL_MSK (((1U << PDM_DC_MUL_LEN) - 1) << PDM_DC_MUL_POS)
#define PDM_DC_MUL_UMSK (~(((1U << PDM_DC_MUL_LEN) - 1) << PDM_DC_MUL_POS))
#define PDM_SCALE_SEL PDM_SCALE_SEL
#define PDM_SCALE_SEL_POS (12U)
#define PDM_SCALE_SEL_LEN (3U)
#define PDM_SCALE_SEL_MSK (((1U << PDM_SCALE_SEL_LEN) - 1) << PDM_SCALE_SEL_POS)
#define PDM_SCALE_SEL_UMSK (~(((1U << PDM_SCALE_SEL_LEN) - 1) << PDM_SCALE_SEL_POS))
#define PDM_DITHER_SEL PDM_DITHER_SEL
#define PDM_DITHER_SEL_POS (16U)
#define PDM_DITHER_SEL_LEN (2U)
#define PDM_DITHER_SEL_MSK (((1U << PDM_DITHER_SEL_LEN) - 1) << PDM_DITHER_SEL_POS)
#define PDM_DITHER_SEL_UMSK (~(((1U << PDM_DITHER_SEL_LEN) - 1) << PDM_DITHER_SEL_POS))
#define PDM_FORCE_LR PDM_FORCE_LR
#define PDM_FORCE_LR_POS (20U)
#define PDM_FORCE_LR_LEN (1U)
#define PDM_FORCE_LR_MSK (((1U << PDM_FORCE_LR_LEN) - 1) << PDM_FORCE_LR_POS)
#define PDM_FORCE_LR_UMSK (~(((1U << PDM_FORCE_LR_LEN) - 1) << PDM_FORCE_LR_POS))
#define PDM_FORCE_SEL PDM_FORCE_SEL
#define PDM_FORCE_SEL_POS (21U)
#define PDM_FORCE_SEL_LEN (1U)
#define PDM_FORCE_SEL_MSK (((1U << PDM_FORCE_SEL_LEN) - 1) << PDM_FORCE_SEL_POS)
#define PDM_FORCE_SEL_UMSK (~(((1U << PDM_FORCE_SEL_LEN) - 1) << PDM_FORCE_SEL_POS))
#define PDM_DSD_SWAP PDM_DSD_SWAP
#define PDM_DSD_SWAP_POS (22U)
#define PDM_DSD_SWAP_LEN (1U)
#define PDM_DSD_SWAP_MSK (((1U << PDM_DSD_SWAP_LEN) - 1) << PDM_DSD_SWAP_POS)
#define PDM_DSD_SWAP_UMSK (~(((1U << PDM_DSD_SWAP_LEN) - 1) << PDM_DSD_SWAP_POS))
#define PDM_OUT_DAT_DLY PDM_OUT_DAT_DLY
#define PDM_OUT_DAT_DLY_POS (24U)
#define PDM_OUT_DAT_DLY_LEN (2U)
#define PDM_OUT_DAT_DLY_MSK (((1U << PDM_OUT_DAT_DLY_LEN) - 1) << PDM_OUT_DAT_DLY_POS)
#define PDM_OUT_DAT_DLY_UMSK (~(((1U << PDM_OUT_DAT_DLY_LEN) - 1) << PDM_OUT_DAT_DLY_POS))
#define PDM_OUT_SEL_DLY PDM_OUT_SEL_DLY
#define PDM_OUT_SEL_DLY_POS (26U)
#define PDM_OUT_SEL_DLY_LEN (2U)
#define PDM_OUT_SEL_DLY_MSK (((1U << PDM_OUT_SEL_DLY_LEN) - 1) << PDM_OUT_SEL_DLY_POS)
#define PDM_OUT_SEL_DLY_UMSK (~(((1U << PDM_OUT_SEL_DLY_LEN) - 1) << PDM_OUT_SEL_DLY_POS))
#define PDM_OUT_SEL_INV PDM_OUT_SEL_INV
#define PDM_OUT_SEL_INV_POS (28U)
#define PDM_OUT_SEL_INV_LEN (1U)
#define PDM_OUT_SEL_INV_MSK (((1U << PDM_OUT_SEL_INV_LEN) - 1) << PDM_OUT_SEL_INV_POS)
#define PDM_OUT_SEL_INV_UMSK (~(((1U << PDM_OUT_SEL_INV_LEN) - 1) << PDM_OUT_SEL_INV_POS))
/* 0x4 : pdm_dma_config */
#define PDM_DMA_CONFIG_OFFSET (0x4)
#define PDM_DMA_RX_EN PDM_DMA_RX_EN
#define PDM_DMA_RX_EN_POS (0U)
#define PDM_DMA_RX_EN_LEN (1U)
#define PDM_DMA_RX_EN_MSK (((1U << PDM_DMA_RX_EN_LEN) - 1) << PDM_DMA_RX_EN_POS)
#define PDM_DMA_RX_EN_UMSK (~(((1U << PDM_DMA_RX_EN_LEN) - 1) << PDM_DMA_RX_EN_POS))
#define PDM_RX_FORMAT PDM_RX_FORMAT
#define PDM_RX_FORMAT_POS (4U)
#define PDM_RX_FORMAT_LEN (3U)
#define PDM_RX_FORMAT_MSK (((1U << PDM_RX_FORMAT_LEN) - 1) << PDM_RX_FORMAT_POS)
#define PDM_RX_FORMAT_UMSK (~(((1U << PDM_RX_FORMAT_LEN) - 1) << PDM_RX_FORMAT_POS))
#define PDM_DMA_TX_EN PDM_DMA_TX_EN
#define PDM_DMA_TX_EN_POS (8U)
#define PDM_DMA_TX_EN_LEN (1U)
#define PDM_DMA_TX_EN_MSK (((1U << PDM_DMA_TX_EN_LEN) - 1) << PDM_DMA_TX_EN_POS)
#define PDM_DMA_TX_EN_UMSK (~(((1U << PDM_DMA_TX_EN_LEN) - 1) << PDM_DMA_TX_EN_POS))
#define PDM_TX_FORMAT PDM_TX_FORMAT
#define PDM_TX_FORMAT_POS (12U)
#define PDM_TX_FORMAT_LEN (3U)
#define PDM_TX_FORMAT_MSK (((1U << PDM_TX_FORMAT_LEN) - 1) << PDM_TX_FORMAT_POS)
#define PDM_TX_FORMAT_UMSK (~(((1U << PDM_TX_FORMAT_LEN) - 1) << PDM_TX_FORMAT_POS))
#define PDM_TX_DATA_SHIFT PDM_TX_DATA_SHIFT
#define PDM_TX_DATA_SHIFT_POS (16U)
#define PDM_TX_DATA_SHIFT_LEN (5U)
#define PDM_TX_DATA_SHIFT_MSK (((1U << PDM_TX_DATA_SHIFT_LEN) - 1) << PDM_TX_DATA_SHIFT_POS)
#define PDM_TX_DATA_SHIFT_UMSK (~(((1U << PDM_TX_DATA_SHIFT_LEN) - 1) << PDM_TX_DATA_SHIFT_POS))
/* 0x8 : pdm_dma_wdata2 */
#define PDM_DMA_WDATA2_OFFSET (0x8)
#define PDM_DMA_WDATA2 PDM_DMA_WDATA2
#define PDM_DMA_WDATA2_POS (0U)
#define PDM_DMA_WDATA2_LEN (32U)
#define PDM_DMA_WDATA2_MSK (((1U << PDM_DMA_WDATA2_LEN) - 1) << PDM_DMA_WDATA2_POS)
#define PDM_DMA_WDATA2_UMSK (~(((1U << PDM_DMA_WDATA2_LEN) - 1) << PDM_DMA_WDATA2_POS))
/* 0x10 : pdm_dma_wdata */
#define PDM_DMA_WDATA_OFFSET (0x10)
#define PDM_DMA_WDATA PDM_DMA_WDATA
#define PDM_DMA_WDATA_POS (0U)
#define PDM_DMA_WDATA_LEN (32U)
#define PDM_DMA_WDATA_MSK (((1U << PDM_DMA_WDATA_LEN) - 1) << PDM_DMA_WDATA_POS)
#define PDM_DMA_WDATA_UMSK (~(((1U << PDM_DMA_WDATA_LEN) - 1) << PDM_DMA_WDATA_POS))
/* 0x14 : pdm_dma_rdata */
#define PDM_DMA_RDATA_OFFSET (0x14)
#define PDM_DMA_RDATA PDM_DMA_RDATA
#define PDM_DMA_RDATA_POS (0U)
#define PDM_DMA_RDATA_LEN (32U)
#define PDM_DMA_RDATA_MSK (((1U << PDM_DMA_RDATA_LEN) - 1) << PDM_DMA_RDATA_POS)
#define PDM_DMA_RDATA_UMSK (~(((1U << PDM_DMA_RDATA_LEN) - 1) << PDM_DMA_RDATA_POS))
/* 0x18 : pdm_tx_fifo_status */
#define PDM_TX_FIFO_STATUS_OFFSET (0x18)
#define PDM_TX_FIFO_EMPTY PDM_TX_FIFO_EMPTY
#define PDM_TX_FIFO_EMPTY_POS (0U)
#define PDM_TX_FIFO_EMPTY_LEN (1U)
#define PDM_TX_FIFO_EMPTY_MSK (((1U << PDM_TX_FIFO_EMPTY_LEN) - 1) << PDM_TX_FIFO_EMPTY_POS)
#define PDM_TX_FIFO_EMPTY_UMSK (~(((1U << PDM_TX_FIFO_EMPTY_LEN) - 1) << PDM_TX_FIFO_EMPTY_POS))
#define PDM_TX_FIFO_FULL PDM_TX_FIFO_FULL
#define PDM_TX_FIFO_FULL_POS (1U)
#define PDM_TX_FIFO_FULL_LEN (1U)
#define PDM_TX_FIFO_FULL_MSK (((1U << PDM_TX_FIFO_FULL_LEN) - 1) << PDM_TX_FIFO_FULL_POS)
#define PDM_TX_FIFO_FULL_UMSK (~(((1U << PDM_TX_FIFO_FULL_LEN) - 1) << PDM_TX_FIFO_FULL_POS))
#define PDM_TX_CS PDM_TX_CS
#define PDM_TX_CS_POS (2U)
#define PDM_TX_CS_LEN (2U)
#define PDM_TX_CS_MSK (((1U << PDM_TX_CS_LEN) - 1) << PDM_TX_CS_POS)
#define PDM_TX_CS_UMSK (~(((1U << PDM_TX_CS_LEN) - 1) << PDM_TX_CS_POS))
#define PDM_TXFIFORDPTR PDM_TXFIFORDPTR
#define PDM_TXFIFORDPTR_POS (4U)
#define PDM_TXFIFORDPTR_LEN (3U)
#define PDM_TXFIFORDPTR_MSK (((1U << PDM_TXFIFORDPTR_LEN) - 1) << PDM_TXFIFORDPTR_POS)
#define PDM_TXFIFORDPTR_UMSK (~(((1U << PDM_TXFIFORDPTR_LEN) - 1) << PDM_TXFIFORDPTR_POS))
#define PDM_TXFIFOWRPTR PDM_TXFIFOWRPTR
#define PDM_TXFIFOWRPTR_POS (8U)
#define PDM_TXFIFOWRPTR_LEN (2U)
#define PDM_TXFIFOWRPTR_MSK (((1U << PDM_TXFIFOWRPTR_LEN) - 1) << PDM_TXFIFOWRPTR_POS)
#define PDM_TXFIFOWRPTR_UMSK (~(((1U << PDM_TXFIFOWRPTR_LEN) - 1) << PDM_TXFIFOWRPTR_POS))
#define PDM_TX2_FIFO_EMPTY PDM_TX2_FIFO_EMPTY
#define PDM_TX2_FIFO_EMPTY_POS (16U)
#define PDM_TX2_FIFO_EMPTY_LEN (1U)
#define PDM_TX2_FIFO_EMPTY_MSK (((1U << PDM_TX2_FIFO_EMPTY_LEN) - 1) << PDM_TX2_FIFO_EMPTY_POS)
#define PDM_TX2_FIFO_EMPTY_UMSK (~(((1U << PDM_TX2_FIFO_EMPTY_LEN) - 1) << PDM_TX2_FIFO_EMPTY_POS))
#define PDM_TX2_FIFO_FULL PDM_TX2_FIFO_FULL
#define PDM_TX2_FIFO_FULL_POS (17U)
#define PDM_TX2_FIFO_FULL_LEN (1U)
#define PDM_TX2_FIFO_FULL_MSK (((1U << PDM_TX2_FIFO_FULL_LEN) - 1) << PDM_TX2_FIFO_FULL_POS)
#define PDM_TX2_FIFO_FULL_UMSK (~(((1U << PDM_TX2_FIFO_FULL_LEN) - 1) << PDM_TX2_FIFO_FULL_POS))
#define PDM_TX2_CS PDM_TX2_CS
#define PDM_TX2_CS_POS (18U)
#define PDM_TX2_CS_LEN (2U)
#define PDM_TX2_CS_MSK (((1U << PDM_TX2_CS_LEN) - 1) << PDM_TX2_CS_POS)
#define PDM_TX2_CS_UMSK (~(((1U << PDM_TX2_CS_LEN) - 1) << PDM_TX2_CS_POS))
#define PDM_TX2FIFORDPTR PDM_TX2FIFORDPTR
#define PDM_TX2FIFORDPTR_POS (20U)
#define PDM_TX2FIFORDPTR_LEN (3U)
#define PDM_TX2FIFORDPTR_MSK (((1U << PDM_TX2FIFORDPTR_LEN) - 1) << PDM_TX2FIFORDPTR_POS)
#define PDM_TX2FIFORDPTR_UMSK (~(((1U << PDM_TX2FIFORDPTR_LEN) - 1) << PDM_TX2FIFORDPTR_POS))
#define PDM_TX2FIFOWRPTR PDM_TX2FIFOWRPTR
#define PDM_TX2FIFOWRPTR_POS (24U)
#define PDM_TX2FIFOWRPTR_LEN (2U)
#define PDM_TX2FIFOWRPTR_MSK (((1U << PDM_TX2FIFOWRPTR_LEN) - 1) << PDM_TX2FIFOWRPTR_POS)
#define PDM_TX2FIFOWRPTR_UMSK (~(((1U << PDM_TX2FIFOWRPTR_LEN) - 1) << PDM_TX2FIFOWRPTR_POS))
/* 0x1C : pdm_rx_fifo_status */
#define PDM_RX_FIFO_STATUS_OFFSET (0x1C)
#define PDM_RX_FIFO_EMPTY PDM_RX_FIFO_EMPTY
#define PDM_RX_FIFO_EMPTY_POS (0U)
#define PDM_RX_FIFO_EMPTY_LEN (1U)
#define PDM_RX_FIFO_EMPTY_MSK (((1U << PDM_RX_FIFO_EMPTY_LEN) - 1) << PDM_RX_FIFO_EMPTY_POS)
#define PDM_RX_FIFO_EMPTY_UMSK (~(((1U << PDM_RX_FIFO_EMPTY_LEN) - 1) << PDM_RX_FIFO_EMPTY_POS))
#define PDM_RX_FIFO_FULL PDM_RX_FIFO_FULL
#define PDM_RX_FIFO_FULL_POS (1U)
#define PDM_RX_FIFO_FULL_LEN (1U)
#define PDM_RX_FIFO_FULL_MSK (((1U << PDM_RX_FIFO_FULL_LEN) - 1) << PDM_RX_FIFO_FULL_POS)
#define PDM_RX_FIFO_FULL_UMSK (~(((1U << PDM_RX_FIFO_FULL_LEN) - 1) << PDM_RX_FIFO_FULL_POS))
#define PDM_RX_CS PDM_RX_CS
#define PDM_RX_CS_POS (2U)
#define PDM_RX_CS_LEN (2U)
#define PDM_RX_CS_MSK (((1U << PDM_RX_CS_LEN) - 1) << PDM_RX_CS_POS)
#define PDM_RX_CS_UMSK (~(((1U << PDM_RX_CS_LEN) - 1) << PDM_RX_CS_POS))
#define PDM_RXFIFORDPTR PDM_RXFIFORDPTR
#define PDM_RXFIFORDPTR_POS (4U)
#define PDM_RXFIFORDPTR_LEN (2U)
#define PDM_RXFIFORDPTR_MSK (((1U << PDM_RXFIFORDPTR_LEN) - 1) << PDM_RXFIFORDPTR_POS)
#define PDM_RXFIFORDPTR_UMSK (~(((1U << PDM_RXFIFORDPTR_LEN) - 1) << PDM_RXFIFORDPTR_POS))
#define PDM_RXFIFOWRPTR PDM_RXFIFOWRPTR
#define PDM_RXFIFOWRPTR_POS (8U)
#define PDM_RXFIFOWRPTR_LEN (3U)
#define PDM_RXFIFOWRPTR_MSK (((1U << PDM_RXFIFOWRPTR_LEN) - 1) << PDM_RXFIFOWRPTR_POS)
#define PDM_RXFIFOWRPTR_UMSK (~(((1U << PDM_RXFIFOWRPTR_LEN) - 1) << PDM_RXFIFOWRPTR_POS))
struct pdm_reg {
/* 0x0 : pdm_datapath_config */
union {
struct
{
uint32_t pdm_en : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
uint32_t rx_sel_128fs : 1; /* [ 2], r/w, 0x0 */
uint32_t tx_sel_128fs : 1; /* [ 3], r/w, 0x0 */
uint32_t dc_mul : 8; /* [11: 4], r/w, 0x64 */
uint32_t scale_sel : 3; /* [14:12], r/w, 0x5 */
uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
uint32_t dither_sel : 2; /* [17:16], r/w, 0x1 */
uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
uint32_t force_lr : 1; /* [ 20], r/w, 0x0 */
uint32_t force_sel : 1; /* [ 21], r/w, 0x0 */
uint32_t dsd_swap : 1; /* [ 22], r/w, 0x0 */
uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
uint32_t out_dat_dly : 2; /* [25:24], r/w, 0x0 */
uint32_t out_sel_dly : 2; /* [27:26], r/w, 0x0 */
uint32_t out_sel_inv : 1; /* [ 28], r/w, 0x0 */
uint32_t rsvd_31_29 : 3; /* [31:29], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pdm_datapath_config;
/* 0x4 : pdm_dma_config */
union {
struct
{
uint32_t pdm_dma_rx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
uint32_t rx_format : 3; /* [ 6: 4], r/w, 0x3 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t pdm_dma_tx_en : 1; /* [ 8], r/w, 0x0 */
uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
uint32_t tx_format : 3; /* [14:12], r/w, 0x3 */
uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
uint32_t tx_data_shift : 5; /* [20:16], r/w, 0x0 */
uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pdm_dma_config;
/* 0x8 : pdm_dma_wdata2 */
union {
struct
{
uint32_t pdm_dma_wdata2 : 32; /* [31: 0], w, x */
} BF;
uint32_t WORD;
} pdm_dma_wdata2;
/* 0xc reserved */
uint8_t RESERVED0xc[4];
/* 0x10 : pdm_dma_wdata */
union {
struct
{
uint32_t pdm_dma_wdata : 32; /* [31: 0], w, x */
} BF;
uint32_t WORD;
} pdm_dma_wdata;
/* 0x14 : pdm_dma_rdata */
union {
struct
{
uint32_t pdm_dma_rdata : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} pdm_dma_rdata;
/* 0x18 : pdm_tx_fifo_status */
union {
struct
{
uint32_t tx_fifo_empty : 1; /* [ 0], r, 0x0 */
uint32_t tx_fifo_full : 1; /* [ 1], r, 0x0 */
uint32_t tx_cs : 2; /* [ 3: 2], r, 0x0 */
uint32_t TxFifoRdPtr : 3; /* [ 6: 4], r, 0x4 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t TxFifoWrPtr : 2; /* [ 9: 8], r, 0x0 */
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
uint32_t tx2_fifo_empty : 1; /* [ 16], r, 0x0 */
uint32_t tx2_fifo_full : 1; /* [ 17], r, 0x0 */
uint32_t tx2_cs : 2; /* [19:18], r, 0x0 */
uint32_t Tx2FifoRdPtr : 3; /* [22:20], r, 0x4 */
uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
uint32_t Tx2FifoWrPtr : 2; /* [25:24], r, 0x0 */
uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pdm_tx_fifo_status;
/* 0x1C : pdm_rx_fifo_status */
union {
struct
{
uint32_t rx_fifo_empty : 1; /* [ 0], r, 0x1 */
uint32_t rx_fifo_full : 1; /* [ 1], r, 0x0 */
uint32_t rx_cs : 2; /* [ 3: 2], r, 0x0 */
uint32_t RxFifoRdPtr : 2; /* [ 5: 4], r, 0x3 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t RxFifoWrPtr : 3; /* [10: 8], r, 0x0 */
uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pdm_rx_fifo_status;
};
typedef volatile struct pdm_reg pdm_reg_t;
#endif /* __PDM_REG_H__ */

1411
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/pds_reg.h
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993
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/pwm_reg.h
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@@ -1,993 +0,0 @@
/**
******************************************************************************
* @file pwm_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __PWM_REG_H__
#define __PWM_REG_H__
#include "bl702.h"
/* 0x0 : pwm_int_config */
#define PWM_INT_CONFIG_OFFSET (0x0)
#define PWM_INTERRUPT_STS PWM_INTERRUPT_STS
#define PWM_INTERRUPT_STS_POS (0U)
#define PWM_INTERRUPT_STS_LEN (6U)
#define PWM_INTERRUPT_STS_MSK (((1U << PWM_INTERRUPT_STS_LEN) - 1) << PWM_INTERRUPT_STS_POS)
#define PWM_INTERRUPT_STS_UMSK (~(((1U << PWM_INTERRUPT_STS_LEN) - 1) << PWM_INTERRUPT_STS_POS))
#define PWM_INT_CLEAR PWM_INT_CLEAR
#define PWM_INT_CLEAR_POS (8U)
#define PWM_INT_CLEAR_LEN (6U)
#define PWM_INT_CLEAR_MSK (((1U << PWM_INT_CLEAR_LEN) - 1) << PWM_INT_CLEAR_POS)
#define PWM_INT_CLEAR_UMSK (~(((1U << PWM_INT_CLEAR_LEN) - 1) << PWM_INT_CLEAR_POS))
/* 0x20 : pwm0_clkdiv */
#define PWM0_CLKDIV_OFFSET (0x20)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
/* 0x24 : pwm0_thre1 */
#define PWM0_THRE1_OFFSET (0x24)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
/* 0x28 : pwm0_thre2 */
#define PWM0_THRE2_OFFSET (0x28)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
/* 0x2C : pwm0_period */
#define PWM0_PERIOD_OFFSET (0x2C)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
/* 0x30 : pwm0_config */
#define PWM0_CONFIG_OFFSET (0x30)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
/* 0x34 : pwm0_interrupt */
#define PWM0_INTERRUPT_OFFSET (0x34)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
/* 0x40 : pwm1_clkdiv */
#define PWM1_CLKDIV_OFFSET (0x40)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
/* 0x44 : pwm1_thre1 */
#define PWM1_THRE1_OFFSET (0x44)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
/* 0x48 : pwm1_thre2 */
#define PWM1_THRE2_OFFSET (0x48)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
/* 0x4C : pwm1_period */
#define PWM1_PERIOD_OFFSET (0x4C)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
/* 0x50 : pwm1_config */
#define PWM1_CONFIG_OFFSET (0x50)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
/* 0x54 : pwm1_interrupt */
#define PWM1_INTERRUPT_OFFSET (0x54)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
/* 0x60 : pwm2_clkdiv */
#define PWM2_CLKDIV_OFFSET (0x60)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
/* 0x64 : pwm2_thre1 */
#define PWM2_THRE1_OFFSET (0x64)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
/* 0x68 : pwm2_thre2 */
#define PWM2_THRE2_OFFSET (0x68)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
/* 0x6C : pwm2_period */
#define PWM2_PERIOD_OFFSET (0x6C)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
/* 0x70 : pwm2_config */
#define PWM2_CONFIG_OFFSET (0x70)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
/* 0x74 : pwm2_interrupt */
#define PWM2_INTERRUPT_OFFSET (0x74)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
/* 0x80 : pwm3_clkdiv */
#define PWM3_CLKDIV_OFFSET (0x80)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
/* 0x84 : pwm3_thre1 */
#define PWM3_THRE1_OFFSET (0x84)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
/* 0x88 : pwm3_thre2 */
#define PWM3_THRE2_OFFSET (0x88)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
/* 0x8C : pwm3_period */
#define PWM3_PERIOD_OFFSET (0x8C)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
/* 0x90 : pwm3_config */
#define PWM3_CONFIG_OFFSET (0x90)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
/* 0x94 : pwm3_interrupt */
#define PWM3_INTERRUPT_OFFSET (0x94)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
/* 0xA0 : pwm4_clkdiv */
#define PWM4_CLKDIV_OFFSET (0xA0)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
/* 0xA4 : pwm4_thre1 */
#define PWM4_THRE1_OFFSET (0xA4)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
/* 0xA8 : pwm4_thre2 */
#define PWM4_THRE2_OFFSET (0xA8)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
/* 0xAC : pwm4_period */
#define PWM4_PERIOD_OFFSET (0xAC)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
/* 0xB0 : pwm4_config */
#define PWM4_CONFIG_OFFSET (0xB0)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
/* 0xB4 : pwm4_interrupt */
#define PWM4_INTERRUPT_OFFSET (0xB4)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
struct pwm_reg {
/* 0x0 : pwm_int_config */
union {
struct
{
uint32_t pwm_interrupt_sts : 6; /* [ 5: 0], r, 0x0 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t pwm_int_clear : 6; /* [13: 8], w, 0x0 */
uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm_int_config;
/* 0x4 reserved */
uint8_t RESERVED0x4[28];
/* 0x20 : pwm0_clkdiv */
union {
struct
{
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm0_clkdiv;
/* 0x24 : pwm0_thre1 */
union {
struct
{
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm0_thre1;
/* 0x28 : pwm0_thre2 */
union {
struct
{
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm0_thre2;
/* 0x2C : pwm0_period */
union {
struct
{
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm0_period;
/* 0x30 : pwm0_config */
union {
struct
{
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm0_config;
/* 0x34 : pwm0_interrupt */
union {
struct
{
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm0_interrupt;
/* 0x38 reserved */
uint8_t RESERVED0x38[8];
/* 0x40 : pwm1_clkdiv */
union {
struct
{
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm1_clkdiv;
/* 0x44 : pwm1_thre1 */
union {
struct
{
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm1_thre1;
/* 0x48 : pwm1_thre2 */
union {
struct
{
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm1_thre2;
/* 0x4C : pwm1_period */
union {
struct
{
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm1_period;
/* 0x50 : pwm1_config */
union {
struct
{
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm1_config;
/* 0x54 : pwm1_interrupt */
union {
struct
{
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm1_interrupt;
/* 0x58 reserved */
uint8_t RESERVED0x58[8];
/* 0x60 : pwm2_clkdiv */
union {
struct
{
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm2_clkdiv;
/* 0x64 : pwm2_thre1 */
union {
struct
{
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm2_thre1;
/* 0x68 : pwm2_thre2 */
union {
struct
{
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm2_thre2;
/* 0x6C : pwm2_period */
union {
struct
{
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm2_period;
/* 0x70 : pwm2_config */
union {
struct
{
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm2_config;
/* 0x74 : pwm2_interrupt */
union {
struct
{
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm2_interrupt;
/* 0x78 reserved */
uint8_t RESERVED0x78[8];
/* 0x80 : pwm3_clkdiv */
union {
struct
{
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm3_clkdiv;
/* 0x84 : pwm3_thre1 */
union {
struct
{
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm3_thre1;
/* 0x88 : pwm3_thre2 */
union {
struct
{
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm3_thre2;
/* 0x8C : pwm3_period */
union {
struct
{
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm3_period;
/* 0x90 : pwm3_config */
union {
struct
{
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm3_config;
/* 0x94 : pwm3_interrupt */
union {
struct
{
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm3_interrupt;
/* 0x98 reserved */
uint8_t RESERVED0x98[8];
/* 0xA0 : pwm4_clkdiv */
union {
struct
{
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm4_clkdiv;
/* 0xA4 : pwm4_thre1 */
union {
struct
{
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm4_thre1;
/* 0xA8 : pwm4_thre2 */
union {
struct
{
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm4_thre2;
/* 0xAC : pwm4_period */
union {
struct
{
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm4_period;
/* 0xB0 : pwm4_config */
union {
struct
{
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm4_config;
/* 0xB4 : pwm4_interrupt */
union {
struct
{
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm4_interrupt;
};
typedef volatile struct pwm_reg pwm_reg_t;
/*Following is reg patch*/
/* 0x0 : pwm_clkdiv */
#define PWM_CLKDIV_OFFSET (0x0)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))
/* 0x4 : pwm_thre1 */
#define PWM_THRE1_OFFSET (0x4)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))
/* 0x8 : pwm_thre2 */
#define PWM_THRE2_OFFSET (0x8)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))
/* 0xc : pwm_period */
#define PWM_PERIOD_OFFSET (0xc)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))
/* 0x10 : pwm_config */
#define PWM_CONFIG_OFFSET (0x10)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))
/* 0x14 : pwm_interrupt */
#define PWM_INTERRUPT_OFFSET (0x14)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))
struct pwm_channel_reg {
/* 0x0 : pwm_clkdiv */
union {
struct
{
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm_clkdiv;
/* 0x4 : pwm_thre1 */
union {
struct
{
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm_thre1;
/* 0x8 : pwm_thre2 */
union {
struct
{
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm_thre2;
/* 0xc : pwm_period */
union {
struct
{
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm_period;
/* 0x10 : pwm_config */
union {
struct
{
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm_config;
/* 0x14 : pwm_interrupt */
union {
struct
{
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pwm_interrupt;
};
typedef volatile struct pwm_channel_reg pwm_channel_reg_t;
#define PWM_CHANNEL_OFFSET 0x20
#endif /* __PWM_REG_H__ */

768
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/qdec_reg.h
View File

@@ -1,768 +0,0 @@
/**
******************************************************************************
* @file qdec_reg.h
* @version V1.2
* @date 2020-04-08
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __QDEC_REG_H__
#define __QDEC_REG_H__
#include "bl702.h"
/* 0x0 : qdec0_ctrl0 */
#define QDEC0_CTRL0_OFFSET (0x0)
#define QDEC_EN QDEC_EN
#define QDEC_EN_POS (0U)
#define QDEC_EN_LEN (1U)
#define QDEC_EN_MSK (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)
#define QDEC_EN_UMSK (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS))
#define QDEC_LED_EN QDEC_LED_EN
#define QDEC_LED_EN_POS (1U)
#define QDEC_LED_EN_LEN (1U)
#define QDEC_LED_EN_MSK (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)
#define QDEC_LED_EN_UMSK (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS))
#define QDEC_LED_POL QDEC_LED_POL
#define QDEC_LED_POL_POS (2U)
#define QDEC_LED_POL_LEN (1U)
#define QDEC_LED_POL_MSK (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)
#define QDEC_LED_POL_UMSK (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS))
#define QDEC_DEG_EN QDEC_DEG_EN
#define QDEC_DEG_EN_POS (3U)
#define QDEC_DEG_EN_LEN (1U)
#define QDEC_DEG_EN_MSK (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)
#define QDEC_DEG_EN_UMSK (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS))
#define QDEC_DEG_CNT QDEC_DEG_CNT
#define QDEC_DEG_CNT_POS (4U)
#define QDEC_DEG_CNT_LEN (4U)
#define QDEC_DEG_CNT_MSK (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)
#define QDEC_DEG_CNT_UMSK (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS))
#define QDEC_SPL_PERIOD QDEC_SPL_PERIOD
#define QDEC_SPL_PERIOD_POS (8U)
#define QDEC_SPL_PERIOD_LEN (4U)
#define QDEC_SPL_PERIOD_MSK (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)
#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS))
#define QDEC_RPT_PERIOD QDEC_RPT_PERIOD
#define QDEC_RPT_PERIOD_POS (12U)
#define QDEC_RPT_PERIOD_LEN (16U)
#define QDEC_RPT_PERIOD_MSK (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)
#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS))
/* 0x4 : qdec0_ctrl1 */
#define QDEC0_CTRL1_OFFSET (0x4)
#define QDEC_ACC_MODE QDEC_ACC_MODE
#define QDEC_ACC_MODE_POS (0U)
#define QDEC_ACC_MODE_LEN (1U)
#define QDEC_ACC_MODE_MSK (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)
#define QDEC_ACC_MODE_UMSK (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS))
#define QDEC_SPL_MODE QDEC_SPL_MODE
#define QDEC_SPL_MODE_POS (1U)
#define QDEC_SPL_MODE_LEN (1U)
#define QDEC_SPL_MODE_MSK (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)
#define QDEC_SPL_MODE_UMSK (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS))
#define QDEC_RPT_MODE QDEC_RPT_MODE
#define QDEC_RPT_MODE_POS (2U)
#define QDEC_RPT_MODE_LEN (1U)
#define QDEC_RPT_MODE_MSK (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)
#define QDEC_RPT_MODE_UMSK (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS))
#define QDEC_INPUT_SWAP QDEC_INPUT_SWAP
#define QDEC_INPUT_SWAP_POS (3U)
#define QDEC_INPUT_SWAP_LEN (1U)
#define QDEC_INPUT_SWAP_MSK (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)
#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS))
#define QDEC_LED_PERIOD QDEC_LED_PERIOD
#define QDEC_LED_PERIOD_POS (16U)
#define QDEC_LED_PERIOD_LEN (9U)
#define QDEC_LED_PERIOD_MSK (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)
#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS))
/* 0x8 : qdec0_value */
#define QDEC0_VALUE_OFFSET (0x8)
#define QDEC_ACC1_VAL QDEC_ACC1_VAL
#define QDEC_ACC1_VAL_POS (0U)
#define QDEC_ACC1_VAL_LEN (16U)
#define QDEC_ACC1_VAL_MSK (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)
#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS))
#define QDEC_ACC2_VAL QDEC_ACC2_VAL
#define QDEC_ACC2_VAL_POS (16U)
#define QDEC_ACC2_VAL_LEN (4U)
#define QDEC_ACC2_VAL_MSK (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)
#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS))
#define QDEC_SPL_VAL QDEC_SPL_VAL
#define QDEC_SPL_VAL_POS (28U)
#define QDEC_SPL_VAL_LEN (2U)
#define QDEC_SPL_VAL_MSK (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)
#define QDEC_SPL_VAL_UMSK (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS))
/* 0x10 : qdec0_int_en */
#define QDEC0_INT_EN_OFFSET (0x10)
#define QDEC_RPT_RDY_EN QDEC_RPT_RDY_EN
#define QDEC_RPT_RDY_EN_POS (0U)
#define QDEC_RPT_RDY_EN_LEN (1U)
#define QDEC_RPT_RDY_EN_MSK (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)
#define QDEC_RPT_RDY_EN_UMSK (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS))
#define QDEC_SPL_RDY_EN QDEC_SPL_RDY_EN
#define QDEC_SPL_RDY_EN_POS (1U)
#define QDEC_SPL_RDY_EN_LEN (1U)
#define QDEC_SPL_RDY_EN_MSK (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)
#define QDEC_SPL_RDY_EN_UMSK (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS))
#define QDEC_DBL_RDY_EN QDEC_DBL_RDY_EN
#define QDEC_DBL_RDY_EN_POS (2U)
#define QDEC_DBL_RDY_EN_LEN (1U)
#define QDEC_DBL_RDY_EN_MSK (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)
#define QDEC_DBL_RDY_EN_UMSK (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS))
#define QDEC_OVERFLOW_EN QDEC_OVERFLOW_EN
#define QDEC_OVERFLOW_EN_POS (3U)
#define QDEC_OVERFLOW_EN_LEN (1U)
#define QDEC_OVERFLOW_EN_MSK (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)
#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS))
/* 0x14 : qdec0_int_sts */
#define QDEC0_INT_STS_OFFSET (0x14)
#define QDEC_RPT_RDY_STS QDEC_RPT_RDY_STS
#define QDEC_RPT_RDY_STS_POS (0U)
#define QDEC_RPT_RDY_STS_LEN (1U)
#define QDEC_RPT_RDY_STS_MSK (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)
#define QDEC_RPT_RDY_STS_UMSK (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS))
#define QDEC_SPL_RDY_STS QDEC_SPL_RDY_STS
#define QDEC_SPL_RDY_STS_POS (1U)
#define QDEC_SPL_RDY_STS_LEN (1U)
#define QDEC_SPL_RDY_STS_MSK (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)
#define QDEC_SPL_RDY_STS_UMSK (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS))
#define QDEC_DBL_RDY_STS QDEC_DBL_RDY_STS
#define QDEC_DBL_RDY_STS_POS (2U)
#define QDEC_DBL_RDY_STS_LEN (1U)
#define QDEC_DBL_RDY_STS_MSK (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)
#define QDEC_DBL_RDY_STS_UMSK (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS))
#define QDEC_OVERFLOW_STS QDEC_OVERFLOW_STS
#define QDEC_OVERFLOW_STS_POS (3U)
#define QDEC_OVERFLOW_STS_LEN (1U)
#define QDEC_OVERFLOW_STS_MSK (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)
#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS))
/* 0x18 : qdec0_int_clr */
#define QDEC0_INT_CLR_OFFSET (0x18)
#define QDEC_RPT_RDY_CLR QDEC_RPT_RDY_CLR
#define QDEC_RPT_RDY_CLR_POS (0U)
#define QDEC_RPT_RDY_CLR_LEN (1U)
#define QDEC_RPT_RDY_CLR_MSK (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)
#define QDEC_RPT_RDY_CLR_UMSK (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS))
#define QDEC_SPL_RDY_CLR QDEC_SPL_RDY_CLR
#define QDEC_SPL_RDY_CLR_POS (1U)
#define QDEC_SPL_RDY_CLR_LEN (1U)
#define QDEC_SPL_RDY_CLR_MSK (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)
#define QDEC_SPL_RDY_CLR_UMSK (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS))
#define QDEC_DBL_RDY_CLR QDEC_DBL_RDY_CLR
#define QDEC_DBL_RDY_CLR_POS (2U)
#define QDEC_DBL_RDY_CLR_LEN (1U)
#define QDEC_DBL_RDY_CLR_MSK (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)
#define QDEC_DBL_RDY_CLR_UMSK (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS))
#define QDEC_OVERFLOW_CLR QDEC_OVERFLOW_CLR
#define QDEC_OVERFLOW_CLR_POS (3U)
#define QDEC_OVERFLOW_CLR_LEN (1U)
#define QDEC_OVERFLOW_CLR_MSK (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)
#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS))
/* 0x40 : qdec1_ctrl0 */
#define QDEC1_CTRL0_OFFSET (0x40)
#define QDEC_EN QDEC_EN
#define QDEC_EN_POS (0U)
#define QDEC_EN_LEN (1U)
#define QDEC_EN_MSK (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)
#define QDEC_EN_UMSK (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS))
#define QDEC_LED_EN QDEC_LED_EN
#define QDEC_LED_EN_POS (1U)
#define QDEC_LED_EN_LEN (1U)
#define QDEC_LED_EN_MSK (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)
#define QDEC_LED_EN_UMSK (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS))
#define QDEC_LED_POL QDEC_LED_POL
#define QDEC_LED_POL_POS (2U)
#define QDEC_LED_POL_LEN (1U)
#define QDEC_LED_POL_MSK (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)
#define QDEC_LED_POL_UMSK (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS))
#define QDEC_DEG_EN QDEC_DEG_EN
#define QDEC_DEG_EN_POS (3U)
#define QDEC_DEG_EN_LEN (1U)
#define QDEC_DEG_EN_MSK (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)
#define QDEC_DEG_EN_UMSK (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS))
#define QDEC_DEG_CNT QDEC_DEG_CNT
#define QDEC_DEG_CNT_POS (4U)
#define QDEC_DEG_CNT_LEN (4U)
#define QDEC_DEG_CNT_MSK (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)
#define QDEC_DEG_CNT_UMSK (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS))
#define QDEC_SPL_PERIOD QDEC_SPL_PERIOD
#define QDEC_SPL_PERIOD_POS (8U)
#define QDEC_SPL_PERIOD_LEN (4U)
#define QDEC_SPL_PERIOD_MSK (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)
#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS))
#define QDEC_RPT_PERIOD QDEC_RPT_PERIOD
#define QDEC_RPT_PERIOD_POS (12U)
#define QDEC_RPT_PERIOD_LEN (16U)
#define QDEC_RPT_PERIOD_MSK (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)
#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS))
/* 0x44 : qdec1_ctrl1 */
#define QDEC1_CTRL1_OFFSET (0x44)
#define QDEC_ACC_MODE QDEC_ACC_MODE
#define QDEC_ACC_MODE_POS (0U)
#define QDEC_ACC_MODE_LEN (1U)
#define QDEC_ACC_MODE_MSK (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)
#define QDEC_ACC_MODE_UMSK (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS))
#define QDEC_SPL_MODE QDEC_SPL_MODE
#define QDEC_SPL_MODE_POS (1U)
#define QDEC_SPL_MODE_LEN (1U)
#define QDEC_SPL_MODE_MSK (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)
#define QDEC_SPL_MODE_UMSK (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS))
#define QDEC_RPT_MODE QDEC_RPT_MODE
#define QDEC_RPT_MODE_POS (2U)
#define QDEC_RPT_MODE_LEN (1U)
#define QDEC_RPT_MODE_MSK (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)
#define QDEC_RPT_MODE_UMSK (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS))
#define QDEC_INPUT_SWAP QDEC_INPUT_SWAP
#define QDEC_INPUT_SWAP_POS (3U)
#define QDEC_INPUT_SWAP_LEN (1U)
#define QDEC_INPUT_SWAP_MSK (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)
#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS))
#define QDEC_LED_PERIOD QDEC_LED_PERIOD
#define QDEC_LED_PERIOD_POS (16U)
#define QDEC_LED_PERIOD_LEN (9U)
#define QDEC_LED_PERIOD_MSK (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)
#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS))
/* 0x48 : qdec1_value */
#define QDEC1_VALUE_OFFSET (0x48)
#define QDEC_ACC1_VAL QDEC_ACC1_VAL
#define QDEC_ACC1_VAL_POS (0U)
#define QDEC_ACC1_VAL_LEN (16U)
#define QDEC_ACC1_VAL_MSK (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)
#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS))
#define QDEC_ACC2_VAL QDEC_ACC2_VAL
#define QDEC_ACC2_VAL_POS (16U)
#define QDEC_ACC2_VAL_LEN (4U)
#define QDEC_ACC2_VAL_MSK (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)
#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS))
#define QDEC_SPL_VAL QDEC_SPL_VAL
#define QDEC_SPL_VAL_POS (28U)
#define QDEC_SPL_VAL_LEN (2U)
#define QDEC_SPL_VAL_MSK (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)
#define QDEC_SPL_VAL_UMSK (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS))
/* 0x50 : qdec1_int_en */
#define QDEC1_INT_EN_OFFSET (0x50)
#define QDEC_RPT_RDY_EN QDEC_RPT_RDY_EN
#define QDEC_RPT_RDY_EN_POS (0U)
#define QDEC_RPT_RDY_EN_LEN (1U)
#define QDEC_RPT_RDY_EN_MSK (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)
#define QDEC_RPT_RDY_EN_UMSK (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS))
#define QDEC_SPL_RDY_EN QDEC_SPL_RDY_EN
#define QDEC_SPL_RDY_EN_POS (1U)
#define QDEC_SPL_RDY_EN_LEN (1U)
#define QDEC_SPL_RDY_EN_MSK (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)
#define QDEC_SPL_RDY_EN_UMSK (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS))
#define QDEC_DBL_RDY_EN QDEC_DBL_RDY_EN
#define QDEC_DBL_RDY_EN_POS (2U)
#define QDEC_DBL_RDY_EN_LEN (1U)
#define QDEC_DBL_RDY_EN_MSK (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)
#define QDEC_DBL_RDY_EN_UMSK (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS))
#define QDEC_OVERFLOW_EN QDEC_OVERFLOW_EN
#define QDEC_OVERFLOW_EN_POS (3U)
#define QDEC_OVERFLOW_EN_LEN (1U)
#define QDEC_OVERFLOW_EN_MSK (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)
#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS))
/* 0x54 : qdec1_int_sts */
#define QDEC1_INT_STS_OFFSET (0x54)
#define QDEC_RPT_RDY_STS QDEC_RPT_RDY_STS
#define QDEC_RPT_RDY_STS_POS (0U)
#define QDEC_RPT_RDY_STS_LEN (1U)
#define QDEC_RPT_RDY_STS_MSK (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)
#define QDEC_RPT_RDY_STS_UMSK (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS))
#define QDEC_SPL_RDY_STS QDEC_SPL_RDY_STS
#define QDEC_SPL_RDY_STS_POS (1U)
#define QDEC_SPL_RDY_STS_LEN (1U)
#define QDEC_SPL_RDY_STS_MSK (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)
#define QDEC_SPL_RDY_STS_UMSK (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS))
#define QDEC_DBL_RDY_STS QDEC_DBL_RDY_STS
#define QDEC_DBL_RDY_STS_POS (2U)
#define QDEC_DBL_RDY_STS_LEN (1U)
#define QDEC_DBL_RDY_STS_MSK (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)
#define QDEC_DBL_RDY_STS_UMSK (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS))
#define QDEC_OVERFLOW_STS QDEC_OVERFLOW_STS
#define QDEC_OVERFLOW_STS_POS (3U)
#define QDEC_OVERFLOW_STS_LEN (1U)
#define QDEC_OVERFLOW_STS_MSK (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)
#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS))
/* 0x58 : qdec1_int_clr */
#define QDEC1_INT_CLR_OFFSET (0x58)
#define QDEC_RPT_RDY_CLR QDEC_RPT_RDY_CLR
#define QDEC_RPT_RDY_CLR_POS (0U)
#define QDEC_RPT_RDY_CLR_LEN (1U)
#define QDEC_RPT_RDY_CLR_MSK (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)
#define QDEC_RPT_RDY_CLR_UMSK (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS))
#define QDEC_SPL_RDY_CLR QDEC_SPL_RDY_CLR
#define QDEC_SPL_RDY_CLR_POS (1U)
#define QDEC_SPL_RDY_CLR_LEN (1U)
#define QDEC_SPL_RDY_CLR_MSK (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)
#define QDEC_SPL_RDY_CLR_UMSK (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS))
#define QDEC_DBL_RDY_CLR QDEC_DBL_RDY_CLR
#define QDEC_DBL_RDY_CLR_POS (2U)
#define QDEC_DBL_RDY_CLR_LEN (1U)
#define QDEC_DBL_RDY_CLR_MSK (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)
#define QDEC_DBL_RDY_CLR_UMSK (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS))
#define QDEC_OVERFLOW_CLR QDEC_OVERFLOW_CLR
#define QDEC_OVERFLOW_CLR_POS (3U)
#define QDEC_OVERFLOW_CLR_LEN (1U)
#define QDEC_OVERFLOW_CLR_MSK (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)
#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS))
/* 0x80 : qdec2_ctrl0 */
#define QDEC2_CTRL0_OFFSET (0x80)
#define QDEC_EN QDEC_EN
#define QDEC_EN_POS (0U)
#define QDEC_EN_LEN (1U)
#define QDEC_EN_MSK (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)
#define QDEC_EN_UMSK (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS))
#define QDEC_LED_EN QDEC_LED_EN
#define QDEC_LED_EN_POS (1U)
#define QDEC_LED_EN_LEN (1U)
#define QDEC_LED_EN_MSK (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)
#define QDEC_LED_EN_UMSK (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS))
#define QDEC_LED_POL QDEC_LED_POL
#define QDEC_LED_POL_POS (2U)
#define QDEC_LED_POL_LEN (1U)
#define QDEC_LED_POL_MSK (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)
#define QDEC_LED_POL_UMSK (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS))
#define QDEC_DEG_EN QDEC_DEG_EN
#define QDEC_DEG_EN_POS (3U)
#define QDEC_DEG_EN_LEN (1U)
#define QDEC_DEG_EN_MSK (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)
#define QDEC_DEG_EN_UMSK (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS))
#define QDEC_DEG_CNT QDEC_DEG_CNT
#define QDEC_DEG_CNT_POS (4U)
#define QDEC_DEG_CNT_LEN (4U)
#define QDEC_DEG_CNT_MSK (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)
#define QDEC_DEG_CNT_UMSK (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS))
#define QDEC_SPL_PERIOD QDEC_SPL_PERIOD
#define QDEC_SPL_PERIOD_POS (8U)
#define QDEC_SPL_PERIOD_LEN (4U)
#define QDEC_SPL_PERIOD_MSK (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)
#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS))
#define QDEC_RPT_PERIOD QDEC_RPT_PERIOD
#define QDEC_RPT_PERIOD_POS (12U)
#define QDEC_RPT_PERIOD_LEN (16U)
#define QDEC_RPT_PERIOD_MSK (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)
#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS))
/* 0x84 : qdec2_ctrl1 */
#define QDEC2_CTRL1_OFFSET (0x84)
#define QDEC_ACC_MODE QDEC_ACC_MODE
#define QDEC_ACC_MODE_POS (0U)
#define QDEC_ACC_MODE_LEN (1U)
#define QDEC_ACC_MODE_MSK (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)
#define QDEC_ACC_MODE_UMSK (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS))
#define QDEC_SPL_MODE QDEC_SPL_MODE
#define QDEC_SPL_MODE_POS (1U)
#define QDEC_SPL_MODE_LEN (1U)
#define QDEC_SPL_MODE_MSK (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)
#define QDEC_SPL_MODE_UMSK (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS))
#define QDEC_RPT_MODE QDEC_RPT_MODE
#define QDEC_RPT_MODE_POS (2U)
#define QDEC_RPT_MODE_LEN (1U)
#define QDEC_RPT_MODE_MSK (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)
#define QDEC_RPT_MODE_UMSK (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS))
#define QDEC_INPUT_SWAP QDEC_INPUT_SWAP
#define QDEC_INPUT_SWAP_POS (3U)
#define QDEC_INPUT_SWAP_LEN (1U)
#define QDEC_INPUT_SWAP_MSK (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)
#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS))
#define QDEC_LED_PERIOD QDEC_LED_PERIOD
#define QDEC_LED_PERIOD_POS (16U)
#define QDEC_LED_PERIOD_LEN (9U)
#define QDEC_LED_PERIOD_MSK (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)
#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS))
/* 0x88 : qdec2_value */
#define QDEC2_VALUE_OFFSET (0x88)
#define QDEC_ACC1_VAL QDEC_ACC1_VAL
#define QDEC_ACC1_VAL_POS (0U)
#define QDEC_ACC1_VAL_LEN (16U)
#define QDEC_ACC1_VAL_MSK (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)
#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS))
#define QDEC_ACC2_VAL QDEC_ACC2_VAL
#define QDEC_ACC2_VAL_POS (16U)
#define QDEC_ACC2_VAL_LEN (4U)
#define QDEC_ACC2_VAL_MSK (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)
#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS))
#define QDEC_SPL_VAL QDEC_SPL_VAL
#define QDEC_SPL_VAL_POS (28U)
#define QDEC_SPL_VAL_LEN (2U)
#define QDEC_SPL_VAL_MSK (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)
#define QDEC_SPL_VAL_UMSK (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS))
/* 0x90 : qdec2_int_en */
#define QDEC2_INT_EN_OFFSET (0x90)
#define QDEC_RPT_RDY_EN QDEC_RPT_RDY_EN
#define QDEC_RPT_RDY_EN_POS (0U)
#define QDEC_RPT_RDY_EN_LEN (1U)
#define QDEC_RPT_RDY_EN_MSK (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)
#define QDEC_RPT_RDY_EN_UMSK (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS))
#define QDEC_SPL_RDY_EN QDEC_SPL_RDY_EN
#define QDEC_SPL_RDY_EN_POS (1U)
#define QDEC_SPL_RDY_EN_LEN (1U)
#define QDEC_SPL_RDY_EN_MSK (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)
#define QDEC_SPL_RDY_EN_UMSK (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS))
#define QDEC_DBL_RDY_EN QDEC_DBL_RDY_EN
#define QDEC_DBL_RDY_EN_POS (2U)
#define QDEC_DBL_RDY_EN_LEN (1U)
#define QDEC_DBL_RDY_EN_MSK (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)
#define QDEC_DBL_RDY_EN_UMSK (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS))
#define QDEC_OVERFLOW_EN QDEC_OVERFLOW_EN
#define QDEC_OVERFLOW_EN_POS (3U)
#define QDEC_OVERFLOW_EN_LEN (1U)
#define QDEC_OVERFLOW_EN_MSK (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)
#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS))
/* 0x94 : qdec2_int_sts */
#define QDEC2_INT_STS_OFFSET (0x94)
#define QDEC_RPT_RDY_STS QDEC_RPT_RDY_STS
#define QDEC_RPT_RDY_STS_POS (0U)
#define QDEC_RPT_RDY_STS_LEN (1U)
#define QDEC_RPT_RDY_STS_MSK (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)
#define QDEC_RPT_RDY_STS_UMSK (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS))
#define QDEC_SPL_RDY_STS QDEC_SPL_RDY_STS
#define QDEC_SPL_RDY_STS_POS (1U)
#define QDEC_SPL_RDY_STS_LEN (1U)
#define QDEC_SPL_RDY_STS_MSK (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)
#define QDEC_SPL_RDY_STS_UMSK (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS))
#define QDEC_DBL_RDY_STS QDEC_DBL_RDY_STS
#define QDEC_DBL_RDY_STS_POS (2U)
#define QDEC_DBL_RDY_STS_LEN (1U)
#define QDEC_DBL_RDY_STS_MSK (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)
#define QDEC_DBL_RDY_STS_UMSK (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS))
#define QDEC_OVERFLOW_STS QDEC_OVERFLOW_STS
#define QDEC_OVERFLOW_STS_POS (3U)
#define QDEC_OVERFLOW_STS_LEN (1U)
#define QDEC_OVERFLOW_STS_MSK (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)
#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS))
/* 0x98 : qdec2_int_clr */
#define QDEC2_INT_CLR_OFFSET (0x98)
#define QDEC_RPT_RDY_CLR QDEC_RPT_RDY_CLR
#define QDEC_RPT_RDY_CLR_POS (0U)
#define QDEC_RPT_RDY_CLR_LEN (1U)
#define QDEC_RPT_RDY_CLR_MSK (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)
#define QDEC_RPT_RDY_CLR_UMSK (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS))
#define QDEC_SPL_RDY_CLR QDEC_SPL_RDY_CLR
#define QDEC_SPL_RDY_CLR_POS (1U)
#define QDEC_SPL_RDY_CLR_LEN (1U)
#define QDEC_SPL_RDY_CLR_MSK (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)
#define QDEC_SPL_RDY_CLR_UMSK (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS))
#define QDEC_DBL_RDY_CLR QDEC_DBL_RDY_CLR
#define QDEC_DBL_RDY_CLR_POS (2U)
#define QDEC_DBL_RDY_CLR_LEN (1U)
#define QDEC_DBL_RDY_CLR_MSK (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)
#define QDEC_DBL_RDY_CLR_UMSK (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS))
#define QDEC_OVERFLOW_CLR QDEC_OVERFLOW_CLR
#define QDEC_OVERFLOW_CLR_POS (3U)
#define QDEC_OVERFLOW_CLR_LEN (1U)
#define QDEC_OVERFLOW_CLR_MSK (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)
#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS))
struct qdec_reg {
/* 0x0 : qdec0_ctrl0 */
union {
struct
{
uint32_t qdec_en : 1; /* [ 0], r/w, 0x0 */
uint32_t led_en : 1; /* [ 1], r/w, 0x0 */
uint32_t led_pol : 1; /* [ 2], r/w, 0x1 */
uint32_t deg_en : 1; /* [ 3], r/w, 0x0 */
uint32_t deg_cnt : 4; /* [ 7: 4], r/w, 0x0 */
uint32_t spl_period : 4; /* [11: 8], r/w, 0x2 */
uint32_t rpt_period : 16; /* [27:12], r/w, 0xa */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec0_ctrl0;
/* 0x4 : qdec0_ctrl1 */
union {
struct
{
uint32_t acc_mode : 1; /* [ 0], r/w, 0x1 */
uint32_t spl_mode : 1; /* [ 1], r/w, 0x0 */
uint32_t rpt_mode : 1; /* [ 2], r/w, 0x0 */
uint32_t input_swap : 1; /* [ 3], r/w, 0x0 */
uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */
uint32_t led_period : 9; /* [24:16], r/w, 0x0 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec0_ctrl1;
/* 0x8 : qdec0_value */
union {
struct
{
uint32_t acc1_val : 16; /* [15: 0], r, 0x0 */
uint32_t acc2_val : 4; /* [19:16], r, 0x0 */
uint32_t reserved_20_27 : 8; /* [27:20], rsvd, 0x0 */
uint32_t spl_val : 2; /* [29:28], r, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec0_value;
/* 0xc reserved */
uint8_t RESERVED0xc[4];
/* 0x10 : qdec0_int_en */
union {
struct
{
uint32_t rpt_rdy_en : 1; /* [ 0], r/w, 0x1 */
uint32_t spl_rdy_en : 1; /* [ 1], r/w, 0x0 */
uint32_t dbl_rdy_en : 1; /* [ 2], r/w, 0x0 */
uint32_t overflow_en : 1; /* [ 3], r/w, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec0_int_en;
/* 0x14 : qdec0_int_sts */
union {
struct
{
uint32_t rpt_rdy_sts : 1; /* [ 0], r, 0x0 */
uint32_t spl_rdy_sts : 1; /* [ 1], r, 0x0 */
uint32_t dbl_rdy_sts : 1; /* [ 2], r, 0x0 */
uint32_t overflow_sts : 1; /* [ 3], r, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec0_int_sts;
/* 0x18 : qdec0_int_clr */
union {
struct
{
uint32_t rpt_rdy_clr : 1; /* [ 0], w1c, 0x0 */
uint32_t spl_rdy_clr : 1; /* [ 1], w1c, 0x0 */
uint32_t dbl_rdy_clr : 1; /* [ 2], w1c, 0x0 */
uint32_t overflow_clr : 1; /* [ 3], w1c, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec0_int_clr;
/* 0x1c reserved */
uint8_t RESERVED0x1c[36];
/* 0x40 : qdec1_ctrl0 */
union {
struct
{
uint32_t qdec_en : 1; /* [ 0], r/w, 0x0 */
uint32_t led_en : 1; /* [ 1], r/w, 0x0 */
uint32_t led_pol : 1; /* [ 2], r/w, 0x1 */
uint32_t deg_en : 1; /* [ 3], r/w, 0x0 */
uint32_t deg_cnt : 4; /* [ 7: 4], r/w, 0x0 */
uint32_t spl_period : 4; /* [11: 8], r/w, 0x2 */
uint32_t rpt_period : 16; /* [27:12], r/w, 0xa */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec1_ctrl0;
/* 0x44 : qdec1_ctrl1 */
union {
struct
{
uint32_t acc_mode : 1; /* [ 0], r/w, 0x1 */
uint32_t spl_mode : 1; /* [ 1], r/w, 0x0 */
uint32_t rpt_mode : 1; /* [ 2], r/w, 0x0 */
uint32_t input_swap : 1; /* [ 3], r/w, 0x0 */
uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */
uint32_t led_period : 9; /* [24:16], r/w, 0x0 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec1_ctrl1;
/* 0x48 : qdec1_value */
union {
struct
{
uint32_t acc1_val : 16; /* [15: 0], r, 0x0 */
uint32_t acc2_val : 4; /* [19:16], r, 0x0 */
uint32_t reserved_20_27 : 8; /* [27:20], rsvd, 0x0 */
uint32_t spl_val : 2; /* [29:28], r, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec1_value;
/* 0x4c reserved */
uint8_t RESERVED0x4c[4];
/* 0x50 : qdec1_int_en */
union {
struct
{
uint32_t rpt_rdy_en : 1; /* [ 0], r/w, 0x1 */
uint32_t spl_rdy_en : 1; /* [ 1], r/w, 0x0 */
uint32_t dbl_rdy_en : 1; /* [ 2], r/w, 0x0 */
uint32_t overflow_en : 1; /* [ 3], r/w, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec1_int_en;
/* 0x54 : qdec1_int_sts */
union {
struct
{
uint32_t rpt_rdy_sts : 1; /* [ 0], r, 0x0 */
uint32_t spl_rdy_sts : 1; /* [ 1], r, 0x0 */
uint32_t dbl_rdy_sts : 1; /* [ 2], r, 0x0 */
uint32_t overflow_sts : 1; /* [ 3], r, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec1_int_sts;
/* 0x58 : qdec1_int_clr */
union {
struct
{
uint32_t rpt_rdy_clr : 1; /* [ 0], w1c, 0x0 */
uint32_t spl_rdy_clr : 1; /* [ 1], w1c, 0x0 */
uint32_t dbl_rdy_clr : 1; /* [ 2], w1c, 0x0 */
uint32_t overflow_clr : 1; /* [ 3], w1c, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec1_int_clr;
/* 0x5c reserved */
uint8_t RESERVED0x5c[36];
/* 0x80 : qdec2_ctrl0 */
union {
struct
{
uint32_t qdec_en : 1; /* [ 0], r/w, 0x0 */
uint32_t led_en : 1; /* [ 1], r/w, 0x0 */
uint32_t led_pol : 1; /* [ 2], r/w, 0x1 */
uint32_t deg_en : 1; /* [ 3], r/w, 0x0 */
uint32_t deg_cnt : 4; /* [ 7: 4], r/w, 0x0 */
uint32_t spl_period : 4; /* [11: 8], r/w, 0x2 */
uint32_t rpt_period : 16; /* [27:12], r/w, 0xa */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec2_ctrl0;
/* 0x84 : qdec2_ctrl1 */
union {
struct
{
uint32_t acc_mode : 1; /* [ 0], r/w, 0x1 */
uint32_t spl_mode : 1; /* [ 1], r/w, 0x0 */
uint32_t rpt_mode : 1; /* [ 2], r/w, 0x0 */
uint32_t input_swap : 1; /* [ 3], r/w, 0x0 */
uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */
uint32_t led_period : 9; /* [24:16], r/w, 0x0 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec2_ctrl1;
/* 0x88 : qdec2_value */
union {
struct
{
uint32_t acc1_val : 16; /* [15: 0], r, 0x0 */
uint32_t acc2_val : 4; /* [19:16], r, 0x0 */
uint32_t reserved_20_27 : 8; /* [27:20], rsvd, 0x0 */
uint32_t spl_val : 2; /* [29:28], r, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec2_value;
/* 0x8c reserved */
uint8_t RESERVED0x8c[4];
/* 0x90 : qdec2_int_en */
union {
struct
{
uint32_t rpt_rdy_en : 1; /* [ 0], r/w, 0x1 */
uint32_t spl_rdy_en : 1; /* [ 1], r/w, 0x0 */
uint32_t dbl_rdy_en : 1; /* [ 2], r/w, 0x0 */
uint32_t overflow_en : 1; /* [ 3], r/w, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec2_int_en;
/* 0x94 : qdec2_int_sts */
union {
struct
{
uint32_t rpt_rdy_sts : 1; /* [ 0], r, 0x0 */
uint32_t spl_rdy_sts : 1; /* [ 1], r, 0x0 */
uint32_t dbl_rdy_sts : 1; /* [ 2], r, 0x0 */
uint32_t overflow_sts : 1; /* [ 3], r, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec2_int_sts;
/* 0x98 : qdec2_int_clr */
union {
struct
{
uint32_t rpt_rdy_clr : 1; /* [ 0], w1c, 0x0 */
uint32_t spl_rdy_clr : 1; /* [ 1], w1c, 0x0 */
uint32_t dbl_rdy_clr : 1; /* [ 2], w1c, 0x0 */
uint32_t overflow_clr : 1; /* [ 3], w1c, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} qdec2_int_clr;
};
typedef volatile struct qdec_reg qdec_reg_t;
#endif /* __QDEC_REG_H__ */

217
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/sec_dbg_reg.h
View File

@@ -1,217 +0,0 @@
/**
******************************************************************************
* @file sec_dbg_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __SEC_DBG_REG_H__
#define __SEC_DBG_REG_H__
#include "bl702.h"
/* 0x0 : sd_chip_id_low */
#define SEC_DBG_SD_CHIP_ID_LOW_OFFSET (0x0)
#define SEC_DBG_SD_CHIP_ID_LOW SEC_DBG_SD_CHIP_ID_LOW
#define SEC_DBG_SD_CHIP_ID_LOW_POS (0U)
#define SEC_DBG_SD_CHIP_ID_LOW_LEN (32U)
#define SEC_DBG_SD_CHIP_ID_LOW_MSK (((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS)
#define SEC_DBG_SD_CHIP_ID_LOW_UMSK (~(((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS))
/* 0x4 : sd_chip_id_high */
#define SEC_DBG_SD_CHIP_ID_HIGH_OFFSET (0x4)
#define SEC_DBG_SD_CHIP_ID_HIGH SEC_DBG_SD_CHIP_ID_HIGH
#define SEC_DBG_SD_CHIP_ID_HIGH_POS (0U)
#define SEC_DBG_SD_CHIP_ID_HIGH_LEN (32U)
#define SEC_DBG_SD_CHIP_ID_HIGH_MSK (((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS)
#define SEC_DBG_SD_CHIP_ID_HIGH_UMSK (~(((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS))
/* 0x8 : sd_wifi_mac_low */
#define SEC_DBG_SD_WIFI_MAC_LOW_OFFSET (0x8)
#define SEC_DBG_SD_WIFI_MAC_LOW SEC_DBG_SD_WIFI_MAC_LOW
#define SEC_DBG_SD_WIFI_MAC_LOW_POS (0U)
#define SEC_DBG_SD_WIFI_MAC_LOW_LEN (32U)
#define SEC_DBG_SD_WIFI_MAC_LOW_MSK (((1U << SEC_DBG_SD_WIFI_MAC_LOW_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_LOW_POS)
#define SEC_DBG_SD_WIFI_MAC_LOW_UMSK (~(((1U << SEC_DBG_SD_WIFI_MAC_LOW_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_LOW_POS))
/* 0xC : sd_wifi_mac_high */
#define SEC_DBG_SD_WIFI_MAC_HIGH_OFFSET (0xC)
#define SEC_DBG_SD_WIFI_MAC_HIGH SEC_DBG_SD_WIFI_MAC_HIGH
#define SEC_DBG_SD_WIFI_MAC_HIGH_POS (0U)
#define SEC_DBG_SD_WIFI_MAC_HIGH_LEN (32U)
#define SEC_DBG_SD_WIFI_MAC_HIGH_MSK (((1U << SEC_DBG_SD_WIFI_MAC_HIGH_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_HIGH_POS)
#define SEC_DBG_SD_WIFI_MAC_HIGH_UMSK (~(((1U << SEC_DBG_SD_WIFI_MAC_HIGH_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_HIGH_POS))
/* 0x10 : sd_dbg_pwd_low */
#define SEC_DBG_SD_DBG_PWD_LOW_OFFSET (0x10)
#define SEC_DBG_SD_DBG_PWD_LOW SEC_DBG_SD_DBG_PWD_LOW
#define SEC_DBG_SD_DBG_PWD_LOW_POS (0U)
#define SEC_DBG_SD_DBG_PWD_LOW_LEN (32U)
#define SEC_DBG_SD_DBG_PWD_LOW_MSK (((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS)
#define SEC_DBG_SD_DBG_PWD_LOW_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS))
/* 0x14 : sd_dbg_pwd_high */
#define SEC_DBG_SD_DBG_PWD_HIGH_OFFSET (0x14)
#define SEC_DBG_SD_DBG_PWD_HIGH SEC_DBG_SD_DBG_PWD_HIGH
#define SEC_DBG_SD_DBG_PWD_HIGH_POS (0U)
#define SEC_DBG_SD_DBG_PWD_HIGH_LEN (32U)
#define SEC_DBG_SD_DBG_PWD_HIGH_MSK (((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS)
#define SEC_DBG_SD_DBG_PWD_HIGH_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS))
/* 0x18 : sd_status */
#define SEC_DBG_SD_STATUS_OFFSET (0x18)
#define SEC_DBG_SD_DBG_PWD_BUSY SEC_DBG_SD_DBG_PWD_BUSY
#define SEC_DBG_SD_DBG_PWD_BUSY_POS (0U)
#define SEC_DBG_SD_DBG_PWD_BUSY_LEN (1U)
#define SEC_DBG_SD_DBG_PWD_BUSY_MSK (((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS)
#define SEC_DBG_SD_DBG_PWD_BUSY_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS))
#define SEC_DBG_SD_DBG_PWD_TRIG SEC_DBG_SD_DBG_PWD_TRIG
#define SEC_DBG_SD_DBG_PWD_TRIG_POS (1U)
#define SEC_DBG_SD_DBG_PWD_TRIG_LEN (1U)
#define SEC_DBG_SD_DBG_PWD_TRIG_MSK (((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS)
#define SEC_DBG_SD_DBG_PWD_TRIG_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS))
#define SEC_DBG_SD_DBG_CCI_READ_EN SEC_DBG_SD_DBG_CCI_READ_EN
#define SEC_DBG_SD_DBG_CCI_READ_EN_POS (2U)
#define SEC_DBG_SD_DBG_CCI_READ_EN_LEN (1U)
#define SEC_DBG_SD_DBG_CCI_READ_EN_MSK (((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS)
#define SEC_DBG_SD_DBG_CCI_READ_EN_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS))
#define SEC_DBG_SD_DBG_CCI_CLK_SEL SEC_DBG_SD_DBG_CCI_CLK_SEL
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_POS (3U)
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN (1U)
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_MSK (((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS)
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS))
#define SEC_DBG_SD_DBG_PWD_CNT SEC_DBG_SD_DBG_PWD_CNT
#define SEC_DBG_SD_DBG_PWD_CNT_POS (4U)
#define SEC_DBG_SD_DBG_PWD_CNT_LEN (20U)
#define SEC_DBG_SD_DBG_PWD_CNT_MSK (((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS)
#define SEC_DBG_SD_DBG_PWD_CNT_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS))
#define SEC_DBG_SD_DBG_MODE SEC_DBG_SD_DBG_MODE
#define SEC_DBG_SD_DBG_MODE_POS (24U)
#define SEC_DBG_SD_DBG_MODE_LEN (4U)
#define SEC_DBG_SD_DBG_MODE_MSK (((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS)
#define SEC_DBG_SD_DBG_MODE_UMSK (~(((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS))
#define SEC_DBG_SD_DBG_ENA SEC_DBG_SD_DBG_ENA
#define SEC_DBG_SD_DBG_ENA_POS (28U)
#define SEC_DBG_SD_DBG_ENA_LEN (4U)
#define SEC_DBG_SD_DBG_ENA_MSK (((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS)
#define SEC_DBG_SD_DBG_ENA_UMSK (~(((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS))
/* 0x1C : sd_dbg_reserved */
#define SEC_DBG_SD_DBG_RESERVED_OFFSET (0x1C)
#define SEC_DBG_SD_DBG_RESERVED SEC_DBG_SD_DBG_RESERVED
#define SEC_DBG_SD_DBG_RESERVED_POS (0U)
#define SEC_DBG_SD_DBG_RESERVED_LEN (32U)
#define SEC_DBG_SD_DBG_RESERVED_MSK (((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS)
#define SEC_DBG_SD_DBG_RESERVED_UMSK (~(((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS))
struct sec_dbg_reg {
/* 0x0 : sd_chip_id_low */
union {
struct
{
uint32_t sd_chip_id_low : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} sd_chip_id_low;
/* 0x4 : sd_chip_id_high */
union {
struct
{
uint32_t sd_chip_id_high : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} sd_chip_id_high;
/* 0x8 : sd_wifi_mac_low */
union {
struct
{
uint32_t sd_wifi_mac_low : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} sd_wifi_mac_low;
/* 0xC : sd_wifi_mac_high */
union {
struct
{
uint32_t sd_wifi_mac_high : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} sd_wifi_mac_high;
/* 0x10 : sd_dbg_pwd_low */
union {
struct
{
uint32_t sd_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} sd_dbg_pwd_low;
/* 0x14 : sd_dbg_pwd_high */
union {
struct
{
uint32_t sd_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} sd_dbg_pwd_high;
/* 0x18 : sd_status */
union {
struct
{
uint32_t sd_dbg_pwd_busy : 1; /* [ 0], r, 0x0 */
uint32_t sd_dbg_pwd_trig : 1; /* [ 1], r/w, 0x0 */
uint32_t sd_dbg_cci_read_en : 1; /* [ 2], r/w, 0x0 */
uint32_t sd_dbg_cci_clk_sel : 1; /* [ 3], r/w, 0x0 */
uint32_t sd_dbg_pwd_cnt : 20; /* [23: 4], r, 0x0 */
uint32_t sd_dbg_mode : 4; /* [27:24], r, 0x0 */
uint32_t sd_dbg_ena : 4; /* [31:28], r, 0x0 */
} BF;
uint32_t WORD;
} sd_status;
/* 0x1C : sd_dbg_reserved */
union {
struct
{
uint32_t sd_dbg_reserved : 32; /* [31: 0], r/w, 0xffff */
} BF;
uint32_t WORD;
} sd_dbg_reserved;
};
typedef volatile struct sec_dbg_reg sec_dbg_reg_t;
#endif /* __SEC_DBG_REG_H__ */

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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/sec_eng_reg.h
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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/sf_ctrl_reg.h
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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/soc702_reg.svd
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source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/spi_reg.h
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@@ -1,521 +0,0 @@
/**
******************************************************************************
* @file spi_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __SPI_REG_H__
#define __SPI_REG_H__
#include "bl702.h"
/* 0x0 : spi_config */
#define SPI_CONFIG_OFFSET (0x0)
#define SPI_CR_SPI_M_EN SPI_CR_SPI_M_EN
#define SPI_CR_SPI_M_EN_POS (0U)
#define SPI_CR_SPI_M_EN_LEN (1U)
#define SPI_CR_SPI_M_EN_MSK (((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS)
#define SPI_CR_SPI_M_EN_UMSK (~(((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS))
#define SPI_CR_SPI_S_EN SPI_CR_SPI_S_EN
#define SPI_CR_SPI_S_EN_POS (1U)
#define SPI_CR_SPI_S_EN_LEN (1U)
#define SPI_CR_SPI_S_EN_MSK (((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS)
#define SPI_CR_SPI_S_EN_UMSK (~(((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS))
#define SPI_CR_SPI_FRAME_SIZE SPI_CR_SPI_FRAME_SIZE
#define SPI_CR_SPI_FRAME_SIZE_POS (2U)
#define SPI_CR_SPI_FRAME_SIZE_LEN (2U)
#define SPI_CR_SPI_FRAME_SIZE_MSK (((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS)
#define SPI_CR_SPI_FRAME_SIZE_UMSK (~(((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS))
#define SPI_CR_SPI_SCLK_POL SPI_CR_SPI_SCLK_POL
#define SPI_CR_SPI_SCLK_POL_POS (4U)
#define SPI_CR_SPI_SCLK_POL_LEN (1U)
#define SPI_CR_SPI_SCLK_POL_MSK (((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS)
#define SPI_CR_SPI_SCLK_POL_UMSK (~(((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS))
#define SPI_CR_SPI_SCLK_PH SPI_CR_SPI_SCLK_PH
#define SPI_CR_SPI_SCLK_PH_POS (5U)
#define SPI_CR_SPI_SCLK_PH_LEN (1U)
#define SPI_CR_SPI_SCLK_PH_MSK (((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS)
#define SPI_CR_SPI_SCLK_PH_UMSK (~(((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS))
#define SPI_CR_SPI_BIT_INV SPI_CR_SPI_BIT_INV
#define SPI_CR_SPI_BIT_INV_POS (6U)
#define SPI_CR_SPI_BIT_INV_LEN (1U)
#define SPI_CR_SPI_BIT_INV_MSK (((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS)
#define SPI_CR_SPI_BIT_INV_UMSK (~(((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS))
#define SPI_CR_SPI_BYTE_INV SPI_CR_SPI_BYTE_INV
#define SPI_CR_SPI_BYTE_INV_POS (7U)
#define SPI_CR_SPI_BYTE_INV_LEN (1U)
#define SPI_CR_SPI_BYTE_INV_MSK (((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS)
#define SPI_CR_SPI_BYTE_INV_UMSK (~(((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS))
#define SPI_CR_SPI_RXD_IGNR_EN SPI_CR_SPI_RXD_IGNR_EN
#define SPI_CR_SPI_RXD_IGNR_EN_POS (8U)
#define SPI_CR_SPI_RXD_IGNR_EN_LEN (1U)
#define SPI_CR_SPI_RXD_IGNR_EN_MSK (((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS)
#define SPI_CR_SPI_RXD_IGNR_EN_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS))
#define SPI_CR_SPI_M_CONT_EN SPI_CR_SPI_M_CONT_EN
#define SPI_CR_SPI_M_CONT_EN_POS (9U)
#define SPI_CR_SPI_M_CONT_EN_LEN (1U)
#define SPI_CR_SPI_M_CONT_EN_MSK (((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS)
#define SPI_CR_SPI_M_CONT_EN_UMSK (~(((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS))
#define SPI_CR_SPI_DEG_EN SPI_CR_SPI_DEG_EN
#define SPI_CR_SPI_DEG_EN_POS (11U)
#define SPI_CR_SPI_DEG_EN_LEN (1U)
#define SPI_CR_SPI_DEG_EN_MSK (((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS)
#define SPI_CR_SPI_DEG_EN_UMSK (~(((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS))
#define SPI_CR_SPI_DEG_CNT SPI_CR_SPI_DEG_CNT
#define SPI_CR_SPI_DEG_CNT_POS (12U)
#define SPI_CR_SPI_DEG_CNT_LEN (4U)
#define SPI_CR_SPI_DEG_CNT_MSK (((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS)
#define SPI_CR_SPI_DEG_CNT_UMSK (~(((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS))
/* 0x4 : spi_int_sts */
#define SPI_INT_STS_OFFSET (0x4)
#define SPI_END_INT SPI_END_INT
#define SPI_END_INT_POS (0U)
#define SPI_END_INT_LEN (1U)
#define SPI_END_INT_MSK (((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS)
#define SPI_END_INT_UMSK (~(((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS))
#define SPI_TXF_INT SPI_TXF_INT
#define SPI_TXF_INT_POS (1U)
#define SPI_TXF_INT_LEN (1U)
#define SPI_TXF_INT_MSK (((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS)
#define SPI_TXF_INT_UMSK (~(((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS))
#define SPI_RXF_INT SPI_RXF_INT
#define SPI_RXF_INT_POS (2U)
#define SPI_RXF_INT_LEN (1U)
#define SPI_RXF_INT_MSK (((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS)
#define SPI_RXF_INT_UMSK (~(((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS))
#define SPI_STO_INT SPI_STO_INT
#define SPI_STO_INT_POS (3U)
#define SPI_STO_INT_LEN (1U)
#define SPI_STO_INT_MSK (((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS)
#define SPI_STO_INT_UMSK (~(((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS))
#define SPI_TXU_INT SPI_TXU_INT
#define SPI_TXU_INT_POS (4U)
#define SPI_TXU_INT_LEN (1U)
#define SPI_TXU_INT_MSK (((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS)
#define SPI_TXU_INT_UMSK (~(((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS))
#define SPI_FER_INT SPI_FER_INT
#define SPI_FER_INT_POS (5U)
#define SPI_FER_INT_LEN (1U)
#define SPI_FER_INT_MSK (((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS)
#define SPI_FER_INT_UMSK (~(((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS))
#define SPI_CR_SPI_END_MASK SPI_CR_SPI_END_MASK
#define SPI_CR_SPI_END_MASK_POS (8U)
#define SPI_CR_SPI_END_MASK_LEN (1U)
#define SPI_CR_SPI_END_MASK_MSK (((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS)
#define SPI_CR_SPI_END_MASK_UMSK (~(((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS))
#define SPI_CR_SPI_TXF_MASK SPI_CR_SPI_TXF_MASK
#define SPI_CR_SPI_TXF_MASK_POS (9U)
#define SPI_CR_SPI_TXF_MASK_LEN (1U)
#define SPI_CR_SPI_TXF_MASK_MSK (((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS)
#define SPI_CR_SPI_TXF_MASK_UMSK (~(((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS))
#define SPI_CR_SPI_RXF_MASK SPI_CR_SPI_RXF_MASK
#define SPI_CR_SPI_RXF_MASK_POS (10U)
#define SPI_CR_SPI_RXF_MASK_LEN (1U)
#define SPI_CR_SPI_RXF_MASK_MSK (((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS)
#define SPI_CR_SPI_RXF_MASK_UMSK (~(((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS))
#define SPI_CR_SPI_STO_MASK SPI_CR_SPI_STO_MASK
#define SPI_CR_SPI_STO_MASK_POS (11U)
#define SPI_CR_SPI_STO_MASK_LEN (1U)
#define SPI_CR_SPI_STO_MASK_MSK (((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS)
#define SPI_CR_SPI_STO_MASK_UMSK (~(((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS))
#define SPI_CR_SPI_TXU_MASK SPI_CR_SPI_TXU_MASK
#define SPI_CR_SPI_TXU_MASK_POS (12U)
#define SPI_CR_SPI_TXU_MASK_LEN (1U)
#define SPI_CR_SPI_TXU_MASK_MSK (((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS)
#define SPI_CR_SPI_TXU_MASK_UMSK (~(((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS))
#define SPI_CR_SPI_FER_MASK SPI_CR_SPI_FER_MASK
#define SPI_CR_SPI_FER_MASK_POS (13U)
#define SPI_CR_SPI_FER_MASK_LEN (1U)
#define SPI_CR_SPI_FER_MASK_MSK (((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS)
#define SPI_CR_SPI_FER_MASK_UMSK (~(((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS))
#define SPI_CR_SPI_END_CLR SPI_CR_SPI_END_CLR
#define SPI_CR_SPI_END_CLR_POS (16U)
#define SPI_CR_SPI_END_CLR_LEN (1U)
#define SPI_CR_SPI_END_CLR_MSK (((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS)
#define SPI_CR_SPI_END_CLR_UMSK (~(((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS))
#define SPI_CR_SPI_STO_CLR SPI_CR_SPI_STO_CLR
#define SPI_CR_SPI_STO_CLR_POS (19U)
#define SPI_CR_SPI_STO_CLR_LEN (1U)
#define SPI_CR_SPI_STO_CLR_MSK (((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS)
#define SPI_CR_SPI_STO_CLR_UMSK (~(((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS))
#define SPI_CR_SPI_TXU_CLR SPI_CR_SPI_TXU_CLR
#define SPI_CR_SPI_TXU_CLR_POS (20U)
#define SPI_CR_SPI_TXU_CLR_LEN (1U)
#define SPI_CR_SPI_TXU_CLR_MSK (((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS)
#define SPI_CR_SPI_TXU_CLR_UMSK (~(((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS))
#define SPI_CR_SPI_END_EN SPI_CR_SPI_END_EN
#define SPI_CR_SPI_END_EN_POS (24U)
#define SPI_CR_SPI_END_EN_LEN (1U)
#define SPI_CR_SPI_END_EN_MSK (((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS)
#define SPI_CR_SPI_END_EN_UMSK (~(((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS))
#define SPI_CR_SPI_TXF_EN SPI_CR_SPI_TXF_EN
#define SPI_CR_SPI_TXF_EN_POS (25U)
#define SPI_CR_SPI_TXF_EN_LEN (1U)
#define SPI_CR_SPI_TXF_EN_MSK (((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS)
#define SPI_CR_SPI_TXF_EN_UMSK (~(((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS))
#define SPI_CR_SPI_RXF_EN SPI_CR_SPI_RXF_EN
#define SPI_CR_SPI_RXF_EN_POS (26U)
#define SPI_CR_SPI_RXF_EN_LEN (1U)
#define SPI_CR_SPI_RXF_EN_MSK (((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS)
#define SPI_CR_SPI_RXF_EN_UMSK (~(((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS))
#define SPI_CR_SPI_STO_EN SPI_CR_SPI_STO_EN
#define SPI_CR_SPI_STO_EN_POS (27U)
#define SPI_CR_SPI_STO_EN_LEN (1U)
#define SPI_CR_SPI_STO_EN_MSK (((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS)
#define SPI_CR_SPI_STO_EN_UMSK (~(((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS))
#define SPI_CR_SPI_TXU_EN SPI_CR_SPI_TXU_EN
#define SPI_CR_SPI_TXU_EN_POS (28U)
#define SPI_CR_SPI_TXU_EN_LEN (1U)
#define SPI_CR_SPI_TXU_EN_MSK (((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS)
#define SPI_CR_SPI_TXU_EN_UMSK (~(((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS))
#define SPI_CR_SPI_FER_EN SPI_CR_SPI_FER_EN
#define SPI_CR_SPI_FER_EN_POS (29U)
#define SPI_CR_SPI_FER_EN_LEN (1U)
#define SPI_CR_SPI_FER_EN_MSK (((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS)
#define SPI_CR_SPI_FER_EN_UMSK (~(((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS))
/* 0x8 : spi_bus_busy */
#define SPI_BUS_BUSY_OFFSET (0x8)
#define SPI_STS_SPI_BUS_BUSY SPI_STS_SPI_BUS_BUSY
#define SPI_STS_SPI_BUS_BUSY_POS (0U)
#define SPI_STS_SPI_BUS_BUSY_LEN (1U)
#define SPI_STS_SPI_BUS_BUSY_MSK (((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS)
#define SPI_STS_SPI_BUS_BUSY_UMSK (~(((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS))
/* 0x10 : spi_prd_0 */
#define SPI_PRD_0_OFFSET (0x10)
#define SPI_CR_SPI_PRD_S SPI_CR_SPI_PRD_S
#define SPI_CR_SPI_PRD_S_POS (0U)
#define SPI_CR_SPI_PRD_S_LEN (8U)
#define SPI_CR_SPI_PRD_S_MSK (((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS)
#define SPI_CR_SPI_PRD_S_UMSK (~(((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS))
#define SPI_CR_SPI_PRD_P SPI_CR_SPI_PRD_P
#define SPI_CR_SPI_PRD_P_POS (8U)
#define SPI_CR_SPI_PRD_P_LEN (8U)
#define SPI_CR_SPI_PRD_P_MSK (((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS)
#define SPI_CR_SPI_PRD_P_UMSK (~(((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS))
#define SPI_CR_SPI_PRD_D_PH_0 SPI_CR_SPI_PRD_D_PH_0
#define SPI_CR_SPI_PRD_D_PH_0_POS (16U)
#define SPI_CR_SPI_PRD_D_PH_0_LEN (8U)
#define SPI_CR_SPI_PRD_D_PH_0_MSK (((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS)
#define SPI_CR_SPI_PRD_D_PH_0_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS))
#define SPI_CR_SPI_PRD_D_PH_1 SPI_CR_SPI_PRD_D_PH_1
#define SPI_CR_SPI_PRD_D_PH_1_POS (24U)
#define SPI_CR_SPI_PRD_D_PH_1_LEN (8U)
#define SPI_CR_SPI_PRD_D_PH_1_MSK (((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS)
#define SPI_CR_SPI_PRD_D_PH_1_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS))
/* 0x14 : spi_prd_1 */
#define SPI_PRD_1_OFFSET (0x14)
#define SPI_CR_SPI_PRD_I SPI_CR_SPI_PRD_I
#define SPI_CR_SPI_PRD_I_POS (0U)
#define SPI_CR_SPI_PRD_I_LEN (8U)
#define SPI_CR_SPI_PRD_I_MSK (((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS)
#define SPI_CR_SPI_PRD_I_UMSK (~(((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS))
/* 0x18 : spi_rxd_ignr */
#define SPI_RXD_IGNR_OFFSET (0x18)
#define SPI_CR_SPI_RXD_IGNR_P SPI_CR_SPI_RXD_IGNR_P
#define SPI_CR_SPI_RXD_IGNR_P_POS (0U)
#define SPI_CR_SPI_RXD_IGNR_P_LEN (5U)
#define SPI_CR_SPI_RXD_IGNR_P_MSK (((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS)
#define SPI_CR_SPI_RXD_IGNR_P_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS))
#define SPI_CR_SPI_RXD_IGNR_S SPI_CR_SPI_RXD_IGNR_S
#define SPI_CR_SPI_RXD_IGNR_S_POS (16U)
#define SPI_CR_SPI_RXD_IGNR_S_LEN (5U)
#define SPI_CR_SPI_RXD_IGNR_S_MSK (((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS)
#define SPI_CR_SPI_RXD_IGNR_S_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS))
/* 0x1C : spi_sto_value */
#define SPI_STO_VALUE_OFFSET (0x1C)
#define SPI_CR_SPI_STO_VALUE SPI_CR_SPI_STO_VALUE
#define SPI_CR_SPI_STO_VALUE_POS (0U)
#define SPI_CR_SPI_STO_VALUE_LEN (12U)
#define SPI_CR_SPI_STO_VALUE_MSK (((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS)
#define SPI_CR_SPI_STO_VALUE_UMSK (~(((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS))
/* 0x80 : spi_fifo_config_0 */
#define SPI_FIFO_CONFIG_0_OFFSET (0x80)
#define SPI_DMA_TX_EN SPI_DMA_TX_EN
#define SPI_DMA_TX_EN_POS (0U)
#define SPI_DMA_TX_EN_LEN (1U)
#define SPI_DMA_TX_EN_MSK (((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS)
#define SPI_DMA_TX_EN_UMSK (~(((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS))
#define SPI_DMA_RX_EN SPI_DMA_RX_EN
#define SPI_DMA_RX_EN_POS (1U)
#define SPI_DMA_RX_EN_LEN (1U)
#define SPI_DMA_RX_EN_MSK (((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS)
#define SPI_DMA_RX_EN_UMSK (~(((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS))
#define SPI_TX_FIFO_CLR SPI_TX_FIFO_CLR
#define SPI_TX_FIFO_CLR_POS (2U)
#define SPI_TX_FIFO_CLR_LEN (1U)
#define SPI_TX_FIFO_CLR_MSK (((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS)
#define SPI_TX_FIFO_CLR_UMSK (~(((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS))
#define SPI_RX_FIFO_CLR SPI_RX_FIFO_CLR
#define SPI_RX_FIFO_CLR_POS (3U)
#define SPI_RX_FIFO_CLR_LEN (1U)
#define SPI_RX_FIFO_CLR_MSK (((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS)
#define SPI_RX_FIFO_CLR_UMSK (~(((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS))
#define SPI_TX_FIFO_OVERFLOW SPI_TX_FIFO_OVERFLOW
#define SPI_TX_FIFO_OVERFLOW_POS (4U)
#define SPI_TX_FIFO_OVERFLOW_LEN (1U)
#define SPI_TX_FIFO_OVERFLOW_MSK (((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS)
#define SPI_TX_FIFO_OVERFLOW_UMSK (~(((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS))
#define SPI_TX_FIFO_UNDERFLOW SPI_TX_FIFO_UNDERFLOW
#define SPI_TX_FIFO_UNDERFLOW_POS (5U)
#define SPI_TX_FIFO_UNDERFLOW_LEN (1U)
#define SPI_TX_FIFO_UNDERFLOW_MSK (((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS)
#define SPI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS))
#define SPI_RX_FIFO_OVERFLOW SPI_RX_FIFO_OVERFLOW
#define SPI_RX_FIFO_OVERFLOW_POS (6U)
#define SPI_RX_FIFO_OVERFLOW_LEN (1U)
#define SPI_RX_FIFO_OVERFLOW_MSK (((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS)
#define SPI_RX_FIFO_OVERFLOW_UMSK (~(((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS))
#define SPI_RX_FIFO_UNDERFLOW SPI_RX_FIFO_UNDERFLOW
#define SPI_RX_FIFO_UNDERFLOW_POS (7U)
#define SPI_RX_FIFO_UNDERFLOW_LEN (1U)
#define SPI_RX_FIFO_UNDERFLOW_MSK (((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS)
#define SPI_RX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS))
/* 0x84 : spi_fifo_config_1 */
#define SPI_FIFO_CONFIG_1_OFFSET (0x84)
#define SPI_TX_FIFO_CNT SPI_TX_FIFO_CNT
#define SPI_TX_FIFO_CNT_POS (0U)
#define SPI_TX_FIFO_CNT_LEN (3U)
#define SPI_TX_FIFO_CNT_MSK (((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS)
#define SPI_TX_FIFO_CNT_UMSK (~(((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS))
#define SPI_RX_FIFO_CNT SPI_RX_FIFO_CNT
#define SPI_RX_FIFO_CNT_POS (8U)
#define SPI_RX_FIFO_CNT_LEN (3U)
#define SPI_RX_FIFO_CNT_MSK (((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS)
#define SPI_RX_FIFO_CNT_UMSK (~(((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS))
#define SPI_TX_FIFO_TH SPI_TX_FIFO_TH
#define SPI_TX_FIFO_TH_POS (16U)
#define SPI_TX_FIFO_TH_LEN (2U)
#define SPI_TX_FIFO_TH_MSK (((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS)
#define SPI_TX_FIFO_TH_UMSK (~(((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS))
#define SPI_RX_FIFO_TH SPI_RX_FIFO_TH
#define SPI_RX_FIFO_TH_POS (24U)
#define SPI_RX_FIFO_TH_LEN (2U)
#define SPI_RX_FIFO_TH_MSK (((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS)
#define SPI_RX_FIFO_TH_UMSK (~(((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS))
/* 0x88 : spi_fifo_wdata */
#define SPI_FIFO_WDATA_OFFSET (0x88)
#define SPI_FIFO_WDATA SPI_FIFO_WDATA
#define SPI_FIFO_WDATA_POS (0U)
#define SPI_FIFO_WDATA_LEN (32U)
#define SPI_FIFO_WDATA_MSK (((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS)
#define SPI_FIFO_WDATA_UMSK (~(((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS))
/* 0x8C : spi_fifo_rdata */
#define SPI_FIFO_RDATA_OFFSET (0x8C)
#define SPI_FIFO_RDATA SPI_FIFO_RDATA
#define SPI_FIFO_RDATA_POS (0U)
#define SPI_FIFO_RDATA_LEN (32U)
#define SPI_FIFO_RDATA_MSK (((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS)
#define SPI_FIFO_RDATA_UMSK (~(((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS))
struct spi_reg {
/* 0x0 : spi_config */
union {
struct
{
uint32_t cr_spi_m_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_spi_s_en : 1; /* [ 1], r/w, 0x0 */
uint32_t cr_spi_frame_size : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t cr_spi_sclk_pol : 1; /* [ 4], r/w, 0x0 */
uint32_t cr_spi_sclk_ph : 1; /* [ 5], r/w, 0x0 */
uint32_t cr_spi_bit_inv : 1; /* [ 6], r/w, 0x0 */
uint32_t cr_spi_byte_inv : 1; /* [ 7], r/w, 0x0 */
uint32_t cr_spi_rxd_ignr_en : 1; /* [ 8], r/w, 0x0 */
uint32_t cr_spi_m_cont_en : 1; /* [ 9], r/w, 0x0 */
uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */
uint32_t cr_spi_deg_en : 1; /* [ 11], r/w, 0x0 */
uint32_t cr_spi_deg_cnt : 4; /* [15:12], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} spi_config;
/* 0x4 : spi_int_sts */
union {
struct
{
uint32_t spi_end_int : 1; /* [ 0], r, 0x0 */
uint32_t spi_txf_int : 1; /* [ 1], r, 0x0 */
uint32_t spi_rxf_int : 1; /* [ 2], r, 0x0 */
uint32_t spi_sto_int : 1; /* [ 3], r, 0x0 */
uint32_t spi_txu_int : 1; /* [ 4], r, 0x0 */
uint32_t spi_fer_int : 1; /* [ 5], r, 0x0 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t cr_spi_end_mask : 1; /* [ 8], r/w, 0x1 */
uint32_t cr_spi_txf_mask : 1; /* [ 9], r/w, 0x1 */
uint32_t cr_spi_rxf_mask : 1; /* [ 10], r/w, 0x1 */
uint32_t cr_spi_sto_mask : 1; /* [ 11], r/w, 0x1 */
uint32_t cr_spi_txu_mask : 1; /* [ 12], r/w, 0x1 */
uint32_t cr_spi_fer_mask : 1; /* [ 13], r/w, 0x1 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t cr_spi_end_clr : 1; /* [ 16], w1c, 0x0 */
uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */
uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */
uint32_t cr_spi_sto_clr : 1; /* [ 19], w1c, 0x0 */
uint32_t cr_spi_txu_clr : 1; /* [ 20], w1c, 0x0 */
uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */
uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
uint32_t cr_spi_end_en : 1; /* [ 24], r/w, 0x1 */
uint32_t cr_spi_txf_en : 1; /* [ 25], r/w, 0x1 */
uint32_t cr_spi_rxf_en : 1; /* [ 26], r/w, 0x1 */
uint32_t cr_spi_sto_en : 1; /* [ 27], r/w, 0x1 */
uint32_t cr_spi_txu_en : 1; /* [ 28], r/w, 0x1 */
uint32_t cr_spi_fer_en : 1; /* [ 29], r/w, 0x1 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} spi_int_sts;
/* 0x8 : spi_bus_busy */
union {
struct
{
uint32_t sts_spi_bus_busy : 1; /* [ 0], r, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
} BF;
uint32_t WORD;
} spi_bus_busy;
/* 0xc reserved */
uint8_t RESERVED0xc[4];
/* 0x10 : spi_prd_0 */
union {
struct
{
uint32_t cr_spi_prd_s : 8; /* [ 7: 0], r/w, 0xf */
uint32_t cr_spi_prd_p : 8; /* [15: 8], r/w, 0xf */
uint32_t cr_spi_prd_d_ph_0 : 8; /* [23:16], r/w, 0xf */
uint32_t cr_spi_prd_d_ph_1 : 8; /* [31:24], r/w, 0xf */
} BF;
uint32_t WORD;
} spi_prd_0;
/* 0x14 : spi_prd_1 */
union {
struct
{
uint32_t cr_spi_prd_i : 8; /* [ 7: 0], r/w, 0xf */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} spi_prd_1;
/* 0x18 : spi_rxd_ignr */
union {
struct
{
uint32_t cr_spi_rxd_ignr_p : 5; /* [ 4: 0], r/w, 0x0 */
uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */
uint32_t cr_spi_rxd_ignr_s : 5; /* [20:16], r/w, 0x0 */
uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
} BF;
uint32_t WORD;
} spi_rxd_ignr;
/* 0x1C : spi_sto_value */
union {
struct
{
uint32_t cr_spi_sto_value : 12; /* [11: 0], r/w, 0xfff */
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
} BF;
uint32_t WORD;
} spi_sto_value;
/* 0x20 reserved */
uint8_t RESERVED0x20[96];
/* 0x80 : spi_fifo_config_0 */
union {
struct
{
uint32_t spi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t spi_dma_rx_en : 1; /* [ 1], r/w, 0x0 */
uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */
uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */
uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */
uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */
uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */
uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} spi_fifo_config_0;
/* 0x84 : spi_fifo_config_1 */
union {
struct
{
uint32_t tx_fifo_cnt : 3; /* [ 2: 0], r, 0x4 */
uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
uint32_t rx_fifo_cnt : 3; /* [10: 8], r, 0x0 */
uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
uint32_t tx_fifo_th : 2; /* [17:16], r/w, 0x0 */
uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
uint32_t rx_fifo_th : 2; /* [25:24], r/w, 0x0 */
uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
} BF;
uint32_t WORD;
} spi_fifo_config_1;
/* 0x88 : spi_fifo_wdata */
union {
struct
{
uint32_t spi_fifo_wdata : 32; /* [31: 0], w, x */
} BF;
uint32_t WORD;
} spi_fifo_wdata;
/* 0x8C : spi_fifo_rdata */
union {
struct
{
uint32_t spi_fifo_rdata : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} spi_fifo_rdata;
};
typedef volatile struct spi_reg spi_reg_t;
#endif /* __SPI_REG_H__ */

852
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/regs/timer_reg.h
View File

@@ -1,852 +0,0 @@
/**
******************************************************************************
* @file timer_reg.h
* @version V1.2
* @date 2020-03-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __TIMER_REG_H__
#define __TIMER_REG_H__
#include "bl702.h"
/* 0x0 : TCCR */
#define TIMER_TCCR_OFFSET (0x0)
#define TIMER_CS_1 TIMER_CS_1
#define TIMER_CS_1_POS (2U)
#define TIMER_CS_1_LEN (2U)
#define TIMER_CS_1_MSK (((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS)
#define TIMER_CS_1_UMSK (~(((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS))
#define TIMER_CS_2 TIMER_CS_2
#define TIMER_CS_2_POS (5U)
#define TIMER_CS_2_LEN (2U)
#define TIMER_CS_2_MSK (((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS)
#define TIMER_CS_2_UMSK (~(((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS))
#define TIMER_CS_WDT TIMER_CS_WDT
#define TIMER_CS_WDT_POS (8U)
#define TIMER_CS_WDT_LEN (2U)
#define TIMER_CS_WDT_MSK (((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS)
#define TIMER_CS_WDT_UMSK (~(((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS))
/* 0x10 : TMR2_0 */
#define TIMER_TMR2_0_OFFSET (0x10)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x14 : TMR2_1 */
#define TIMER_TMR2_1_OFFSET (0x14)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x18 : TMR2_2 */
#define TIMER_TMR2_2_OFFSET (0x18)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x1C : TMR3_0 */
#define TIMER_TMR3_0_OFFSET (0x1C)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x20 : TMR3_1 */
#define TIMER_TMR3_1_OFFSET (0x20)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x24 : TMR3_2 */
#define TIMER_TMR3_2_OFFSET (0x24)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
/* 0x2C : TCR2 */
#define TIMER_TCR2_OFFSET (0x2C)
#define TIMER_TCR TIMER_TCR
#define TIMER_TCR_POS (0U)
#define TIMER_TCR_LEN (32U)
#define TIMER_TCR_MSK (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)
#define TIMER_TCR_UMSK (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS))
/* 0x30 : TCR3 */
#define TIMER_TCR3_OFFSET (0x30)
#define TIMER_TCR TIMER_TCR
#define TIMER_TCR_POS (0U)
#define TIMER_TCR_LEN (32U)
#define TIMER_TCR_MSK (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)
#define TIMER_TCR_UMSK (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS))
/* 0x38 : TMSR2 */
#define TIMER_TMSR2_OFFSET (0x38)
#define TIMER_TMSR_0 TIMER_TMSR_0
#define TIMER_TMSR_0_POS (0U)
#define TIMER_TMSR_0_LEN (1U)
#define TIMER_TMSR_0_MSK (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)
#define TIMER_TMSR_0_UMSK (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS))
#define TIMER_TMSR_1 TIMER_TMSR_1
#define TIMER_TMSR_1_POS (1U)
#define TIMER_TMSR_1_LEN (1U)
#define TIMER_TMSR_1_MSK (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)
#define TIMER_TMSR_1_UMSK (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS))
#define TIMER_TMSR_2 TIMER_TMSR_2
#define TIMER_TMSR_2_POS (2U)
#define TIMER_TMSR_2_LEN (1U)
#define TIMER_TMSR_2_MSK (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)
#define TIMER_TMSR_2_UMSK (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS))
/* 0x3C : TMSR3 */
#define TIMER_TMSR3_OFFSET (0x3C)
#define TIMER_TMSR_0 TIMER_TMSR_0
#define TIMER_TMSR_0_POS (0U)
#define TIMER_TMSR_0_LEN (1U)
#define TIMER_TMSR_0_MSK (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)
#define TIMER_TMSR_0_UMSK (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS))
#define TIMER_TMSR_1 TIMER_TMSR_1
#define TIMER_TMSR_1_POS (1U)
#define TIMER_TMSR_1_LEN (1U)
#define TIMER_TMSR_1_MSK (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)
#define TIMER_TMSR_1_UMSK (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS))
#define TIMER_TMSR_2 TIMER_TMSR_2
#define TIMER_TMSR_2_POS (2U)
#define TIMER_TMSR_2_LEN (1U)
#define TIMER_TMSR_2_MSK (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)
#define TIMER_TMSR_2_UMSK (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS))
/* 0x44 : TIER2 */
#define TIMER_TIER2_OFFSET (0x44)
#define TIMER_TIER_0 TIMER_TIER_0
#define TIMER_TIER_0_POS (0U)
#define TIMER_TIER_0_LEN (1U)
#define TIMER_TIER_0_MSK (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)
#define TIMER_TIER_0_UMSK (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS))
#define TIMER_TIER_1 TIMER_TIER_1
#define TIMER_TIER_1_POS (1U)
#define TIMER_TIER_1_LEN (1U)
#define TIMER_TIER_1_MSK (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)
#define TIMER_TIER_1_UMSK (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS))
#define TIMER_TIER_2 TIMER_TIER_2
#define TIMER_TIER_2_POS (2U)
#define TIMER_TIER_2_LEN (1U)
#define TIMER_TIER_2_MSK (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)
#define TIMER_TIER_2_UMSK (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS))
/* 0x48 : TIER3 */
#define TIMER_TIER3_OFFSET (0x48)
#define TIMER_TIER_0 TIMER_TIER_0
#define TIMER_TIER_0_POS (0U)
#define TIMER_TIER_0_LEN (1U)
#define TIMER_TIER_0_MSK (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)
#define TIMER_TIER_0_UMSK (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS))
#define TIMER_TIER_1 TIMER_TIER_1
#define TIMER_TIER_1_POS (1U)
#define TIMER_TIER_1_LEN (1U)
#define TIMER_TIER_1_MSK (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)
#define TIMER_TIER_1_UMSK (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS))
#define TIMER_TIER_2 TIMER_TIER_2
#define TIMER_TIER_2_POS (2U)
#define TIMER_TIER_2_LEN (1U)
#define TIMER_TIER_2_MSK (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)
#define TIMER_TIER_2_UMSK (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS))
/* 0x50 : TPLVR2 */
#define TIMER_TPLVR2_OFFSET (0x50)
#define TIMER_TPLVR TIMER_TPLVR
#define TIMER_TPLVR_POS (0U)
#define TIMER_TPLVR_LEN (32U)
#define TIMER_TPLVR_MSK (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)
#define TIMER_TPLVR_UMSK (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS))
/* 0x54 : TPLVR3 */
#define TIMER_TPLVR3_OFFSET (0x54)
#define TIMER_TPLVR TIMER_TPLVR
#define TIMER_TPLVR_POS (0U)
#define TIMER_TPLVR_LEN (32U)
#define TIMER_TPLVR_MSK (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)
#define TIMER_TPLVR_UMSK (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS))
/* 0x5C : TPLCR2 */
#define TIMER_TPLCR2_OFFSET (0x5C)
#define TIMER_TPLCR TIMER_TPLCR
#define TIMER_TPLCR_POS (0U)
#define TIMER_TPLCR_LEN (2U)
#define TIMER_TPLCR_MSK (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)
#define TIMER_TPLCR_UMSK (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS))
/* 0x60 : TPLCR3 */
#define TIMER_TPLCR3_OFFSET (0x60)
#define TIMER_TPLCR TIMER_TPLCR
#define TIMER_TPLCR_POS (0U)
#define TIMER_TPLCR_LEN (2U)
#define TIMER_TPLCR_MSK (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)
#define TIMER_TPLCR_UMSK (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS))
/* 0x64 : WMER */
#define TIMER_WMER_OFFSET (0x64)
#define TIMER_WE TIMER_WE
#define TIMER_WE_POS (0U)
#define TIMER_WE_LEN (1U)
#define TIMER_WE_MSK (((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS)
#define TIMER_WE_UMSK (~(((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS))
#define TIMER_WRIE TIMER_WRIE
#define TIMER_WRIE_POS (1U)
#define TIMER_WRIE_LEN (1U)
#define TIMER_WRIE_MSK (((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS)
#define TIMER_WRIE_UMSK (~(((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS))
/* 0x68 : WMR */
#define TIMER_WMR_OFFSET (0x68)
#define TIMER_WMR TIMER_WMR
#define TIMER_WMR_POS (0U)
#define TIMER_WMR_LEN (16U)
#define TIMER_WMR_MSK (((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS)
#define TIMER_WMR_UMSK (~(((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS))
/* 0x6C : WVR */
#define TIMER_WVR_OFFSET (0x6C)
#define TIMER_WVR TIMER_WVR
#define TIMER_WVR_POS (0U)
#define TIMER_WVR_LEN (16U)
#define TIMER_WVR_MSK (((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS)
#define TIMER_WVR_UMSK (~(((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS))
/* 0x70 : WSR */
#define TIMER_WSR_OFFSET (0x70)
#define TIMER_WTS TIMER_WTS
#define TIMER_WTS_POS (0U)
#define TIMER_WTS_LEN (1U)
#define TIMER_WTS_MSK (((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS)
#define TIMER_WTS_UMSK (~(((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS))
/* 0x78 : TICR2 */
#define TIMER_TICR2_OFFSET (0x78)
#define TIMER_TCLR_0 TIMER_TCLR_0
#define TIMER_TCLR_0_POS (0U)
#define TIMER_TCLR_0_LEN (1U)
#define TIMER_TCLR_0_MSK (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)
#define TIMER_TCLR_0_UMSK (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS))
#define TIMER_TCLR_1 TIMER_TCLR_1
#define TIMER_TCLR_1_POS (1U)
#define TIMER_TCLR_1_LEN (1U)
#define TIMER_TCLR_1_MSK (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)
#define TIMER_TCLR_1_UMSK (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS))
#define TIMER_TCLR_2 TIMER_TCLR_2
#define TIMER_TCLR_2_POS (2U)
#define TIMER_TCLR_2_LEN (1U)
#define TIMER_TCLR_2_MSK (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)
#define TIMER_TCLR_2_UMSK (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS))
/* 0x7C : TICR3 */
#define TIMER_TICR3_OFFSET (0x7C)
#define TIMER_TCLR_0 TIMER_TCLR_0
#define TIMER_TCLR_0_POS (0U)
#define TIMER_TCLR_0_LEN (1U)
#define TIMER_TCLR_0_MSK (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)
#define TIMER_TCLR_0_UMSK (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS))
#define TIMER_TCLR_1 TIMER_TCLR_1
#define TIMER_TCLR_1_POS (1U)
#define TIMER_TCLR_1_LEN (1U)
#define TIMER_TCLR_1_MSK (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)
#define TIMER_TCLR_1_UMSK (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS))
#define TIMER_TCLR_2 TIMER_TCLR_2
#define TIMER_TCLR_2_POS (2U)
#define TIMER_TCLR_2_LEN (1U)
#define TIMER_TCLR_2_MSK (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)
#define TIMER_TCLR_2_UMSK (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS))
/* 0x80 : WICR */
#define TIMER_WICR_OFFSET (0x80)
#define TIMER_WICLR TIMER_WICLR
#define TIMER_WICLR_POS (0U)
#define TIMER_WICLR_LEN (1U)
#define TIMER_WICLR_MSK (((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS)
#define TIMER_WICLR_UMSK (~(((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS))
/* 0x84 : TCER */
#define TIMER_TCER_OFFSET (0x84)
#define TIMER2_EN TIMER2_EN
#define TIMER2_EN_POS (1U)
#define TIMER2_EN_LEN (1U)
#define TIMER2_EN_MSK (((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS)
#define TIMER2_EN_UMSK (~(((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS))
#define TIMER3_EN TIMER3_EN
#define TIMER3_EN_POS (2U)
#define TIMER3_EN_LEN (1U)
#define TIMER3_EN_MSK (((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS)
#define TIMER3_EN_UMSK (~(((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS))
/* 0x88 : TCMR */
#define TIMER_TCMR_OFFSET (0x88)
#define TIMER2_MODE TIMER2_MODE
#define TIMER2_MODE_POS (1U)
#define TIMER2_MODE_LEN (1U)
#define TIMER2_MODE_MSK (((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS)
#define TIMER2_MODE_UMSK (~(((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS))
#define TIMER3_MODE TIMER3_MODE
#define TIMER3_MODE_POS (2U)
#define TIMER3_MODE_LEN (1U)
#define TIMER3_MODE_MSK (((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS)
#define TIMER3_MODE_UMSK (~(((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS))
/* 0x90 : TILR2 */
#define TIMER_TILR2_OFFSET (0x90)
#define TIMER_TILR_0 TIMER_TILR_0
#define TIMER_TILR_0_POS (0U)
#define TIMER_TILR_0_LEN (1U)
#define TIMER_TILR_0_MSK (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)
#define TIMER_TILR_0_UMSK (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS))
#define TIMER_TILR_1 TIMER_TILR_1
#define TIMER_TILR_1_POS (1U)
#define TIMER_TILR_1_LEN (1U)
#define TIMER_TILR_1_MSK (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)
#define TIMER_TILR_1_UMSK (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS))
#define TIMER_TILR_2 TIMER_TILR_2
#define TIMER_TILR_2_POS (2U)
#define TIMER_TILR_2_LEN (1U)
#define TIMER_TILR_2_MSK (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)
#define TIMER_TILR_2_UMSK (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS))
/* 0x94 : TILR3 */
#define TIMER_TILR3_OFFSET (0x94)
#define TIMER_TILR_0 TIMER_TILR_0
#define TIMER_TILR_0_POS (0U)
#define TIMER_TILR_0_LEN (1U)
#define TIMER_TILR_0_MSK (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)
#define TIMER_TILR_0_UMSK (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS))
#define TIMER_TILR_1 TIMER_TILR_1
#define TIMER_TILR_1_POS (1U)
#define TIMER_TILR_1_LEN (1U)
#define TIMER_TILR_1_MSK (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)
#define TIMER_TILR_1_UMSK (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS))
#define TIMER_TILR_2 TIMER_TILR_2
#define TIMER_TILR_2_POS (2U)
#define TIMER_TILR_2_LEN (1U)
#define TIMER_TILR_2_MSK (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)
#define TIMER_TILR_2_UMSK (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS))
/* 0x98 : WCR */
#define TIMER_WCR_OFFSET (0x98)
#define TIMER_WCR TIMER_WCR
#define TIMER_WCR_POS (0U)
#define TIMER_WCR_LEN (1U)
#define TIMER_WCR_MSK (((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS)
#define TIMER_WCR_UMSK (~(((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS))
/* 0x9C : WFAR */
#define TIMER_WFAR_OFFSET (0x9C)
#define TIMER_WFAR TIMER_WFAR
#define TIMER_WFAR_POS (0U)
#define TIMER_WFAR_LEN (16U)
#define TIMER_WFAR_MSK (((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS)
#define TIMER_WFAR_UMSK (~(((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS))
/* 0xA0 : WSAR */
#define TIMER_WSAR_OFFSET (0xA0)
#define TIMER_WSAR TIMER_WSAR
#define TIMER_WSAR_POS (0U)
#define TIMER_WSAR_LEN (16U)
#define TIMER_WSAR_MSK (((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS)
#define TIMER_WSAR_UMSK (~(((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS))
/* 0xA8 : TCVWR2 */
#define TIMER_TCVWR2_OFFSET (0xA8)
#define TIMER_TCVWR TIMER_TCVWR
#define TIMER_TCVWR_POS (0U)
#define TIMER_TCVWR_LEN (32U)
#define TIMER_TCVWR_MSK (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)
#define TIMER_TCVWR_UMSK (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS))
/* 0xAC : TCVWR3 */
#define TIMER_TCVWR3_OFFSET (0xAC)
#define TIMER_TCVWR TIMER_TCVWR
#define TIMER_TCVWR_POS (0U)
#define TIMER_TCVWR_LEN (32U)
#define TIMER_TCVWR_MSK (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)
#define TIMER_TCVWR_UMSK (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS))
/* 0xB4 : TCVSYN2 */
#define TIMER_TCVSYN2_OFFSET (0xB4)
#define TIMER_TCVSYN2 TIMER_TCVSYN2
#define TIMER_TCVSYN2_POS (0U)
#define TIMER_TCVSYN2_LEN (32U)
#define TIMER_TCVSYN2_MSK (((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS)
#define TIMER_TCVSYN2_UMSK (~(((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS))
/* 0xB8 : TCVSYN3 */
#define TIMER_TCVSYN3_OFFSET (0xB8)
#define TIMER_TCVSYN3 TIMER_TCVSYN3
#define TIMER_TCVSYN3_POS (0U)
#define TIMER_TCVSYN3_LEN (32U)
#define TIMER_TCVSYN3_MSK (((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS)
#define TIMER_TCVSYN3_UMSK (~(((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS))
/* 0xBC : TCDR */
#define TIMER_TCDR_OFFSET (0xBC)
#define TIMER_TCDR2 TIMER_TCDR2
#define TIMER_TCDR2_POS (8U)
#define TIMER_TCDR2_LEN (8U)
#define TIMER_TCDR2_MSK (((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS)
#define TIMER_TCDR2_UMSK (~(((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS))
#define TIMER_TCDR3 TIMER_TCDR3
#define TIMER_TCDR3_POS (16U)
#define TIMER_TCDR3_LEN (8U)
#define TIMER_TCDR3_MSK (((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS)
#define TIMER_TCDR3_UMSK (~(((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS))
#define TIMER_WCDR TIMER_WCDR
#define TIMER_WCDR_POS (24U)
#define TIMER_WCDR_LEN (8U)
#define TIMER_WCDR_MSK (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)
#define TIMER_WCDR_UMSK (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS))
struct timer_reg {
/* 0x0 : TCCR */
union {
struct
{
uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
uint32_t cs_1 : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t RESERVED_4 : 1; /* [ 4], rsvd, 0x0 */
uint32_t cs_2 : 2; /* [ 6: 5], r/w, 0x0 */
uint32_t RESERVED_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t cs_wdt : 2; /* [ 9: 8], r/w, 0x0 */
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TCCR;
/* 0x4 reserved */
uint8_t RESERVED0x4[12];
/* 0x10 : TMR2_0 */
union {
struct
{
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} TMR2_0;
/* 0x14 : TMR2_1 */
union {
struct
{
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} TMR2_1;
/* 0x18 : TMR2_2 */
union {
struct
{
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} TMR2_2;
/* 0x1C : TMR3_0 */
union {
struct
{
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} TMR3_0;
/* 0x20 : TMR3_1 */
union {
struct
{
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} TMR3_1;
/* 0x24 : TMR3_2 */
union {
struct
{
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} TMR3_2;
/* 0x28 reserved */
uint8_t RESERVED0x28[4];
/* 0x2C : TCR2 */
union {
struct
{
uint32_t tcr : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} TCR2;
/* 0x30 : TCR3 */
union {
struct
{
uint32_t tcr : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} TCR3;
/* 0x34 reserved */
uint8_t RESERVED0x34[4];
/* 0x38 : TMSR2 */
union {
struct
{
uint32_t tmsr_0 : 1; /* [ 0], r, 0x0 */
uint32_t tmsr_1 : 1; /* [ 1], r, 0x0 */
uint32_t tmsr_2 : 1; /* [ 2], r, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TMSR2;
/* 0x3C : TMSR3 */
union {
struct
{
uint32_t tmsr_0 : 1; /* [ 0], r, 0x0 */
uint32_t tmsr_1 : 1; /* [ 1], r, 0x0 */
uint32_t tmsr_2 : 1; /* [ 2], r, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TMSR3;
/* 0x40 reserved */
uint8_t RESERVED0x40[4];
/* 0x44 : TIER2 */
union {
struct
{
uint32_t tier_0 : 1; /* [ 0], r/w, 0x0 */
uint32_t tier_1 : 1; /* [ 1], r/w, 0x0 */
uint32_t tier_2 : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TIER2;
/* 0x48 : TIER3 */
union {
struct
{
uint32_t tier_0 : 1; /* [ 0], r/w, 0x0 */
uint32_t tier_1 : 1; /* [ 1], r/w, 0x0 */
uint32_t tier_2 : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TIER3;
/* 0x4c reserved */
uint8_t RESERVED0x4c[4];
/* 0x50 : TPLVR2 */
union {
struct
{
uint32_t tplvr : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} TPLVR2;
/* 0x54 : TPLVR3 */
union {
struct
{
uint32_t tplvr : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} TPLVR3;
/* 0x58 reserved */
uint8_t RESERVED0x58[4];
/* 0x5C : TPLCR2 */
union {
struct
{
uint32_t tplcr : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TPLCR2;
/* 0x60 : TPLCR3 */
union {
struct
{
uint32_t tplcr : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TPLCR3;
/* 0x64 : WMER */
union {
struct
{
uint32_t we : 1; /* [ 0], r/w, 0x0 */
uint32_t wrie : 1; /* [ 1], r/w, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
} BF;
uint32_t WORD;
} WMER;
/* 0x68 : WMR */
union {
struct
{
uint32_t wmr : 16; /* [15: 0], r/w, 0xffff */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} WMR;
/* 0x6C : WVR */
union {
struct
{
uint32_t wvr : 16; /* [15: 0], r, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} WVR;
/* 0x70 : WSR */
union {
struct
{
uint32_t wts : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
} BF;
uint32_t WORD;
} WSR;
/* 0x74 reserved */
uint8_t RESERVED0x74[4];
/* 0x78 : TICR2 */
union {
struct
{
uint32_t tclr_0 : 1; /* [ 0], w, 0x0 */
uint32_t tclr_1 : 1; /* [ 1], w, 0x0 */
uint32_t tclr_2 : 1; /* [ 2], w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TICR2;
/* 0x7C : TICR3 */
union {
struct
{
uint32_t tclr_0 : 1; /* [ 0], w, 0x0 */
uint32_t tclr_1 : 1; /* [ 1], w, 0x0 */
uint32_t tclr_2 : 1; /* [ 2], w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TICR3;
/* 0x80 : WICR */
union {
struct
{
uint32_t wiclr : 1; /* [ 0], w, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
} BF;
uint32_t WORD;
} WICR;
/* 0x84 : TCER */
union {
struct
{
uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
uint32_t timer2_en : 1; /* [ 1], r/w, 0x0 */
uint32_t timer3_en : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TCER;
/* 0x88 : TCMR */
union {
struct
{
uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
uint32_t timer2_mode : 1; /* [ 1], r/w, 0x0 */
uint32_t timer3_mode : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TCMR;
/* 0x8c reserved */
uint8_t RESERVED0x8c[4];
/* 0x90 : TILR2 */
union {
struct
{
uint32_t tilr_0 : 1; /* [ 0], r/w, 0x0 */
uint32_t tilr_1 : 1; /* [ 1], r/w, 0x0 */
uint32_t tilr_2 : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TILR2;
/* 0x94 : TILR3 */
union {
struct
{
uint32_t tilr_0 : 1; /* [ 0], r/w, 0x0 */
uint32_t tilr_1 : 1; /* [ 1], r/w, 0x0 */
uint32_t tilr_2 : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} TILR3;
/* 0x98 : WCR */
union {
struct
{
uint32_t wcr : 1; /* [ 0], w, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
} BF;
uint32_t WORD;
} WCR;
/* 0x9C : WFAR */
union {
struct
{
uint32_t wfar : 16; /* [15: 0], w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} WFAR;
/* 0xA0 : WSAR */
union {
struct
{
uint32_t wsar : 16; /* [15: 0], w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} WSAR;
/* 0xa4 reserved */
uint8_t RESERVED0xa4[4];
/* 0xA8 : TCVWR2 */
union {
struct
{
uint32_t tcvwr : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} TCVWR2;
/* 0xAC : TCVWR3 */
union {
struct
{
uint32_t tcvwr : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} TCVWR3;
/* 0xb0 reserved */
uint8_t RESERVED0xb0[4];
/* 0xB4 : TCVSYN2 */
union {
struct
{
uint32_t tcvsyn2 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} TCVSYN2;
/* 0xB8 : TCVSYN3 */
union {
struct
{
uint32_t tcvsyn3 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} TCVSYN3;
/* 0xBC : TCDR */
union {
struct
{
uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */
uint32_t tcdr2 : 8; /* [15: 8], r/w, 0x0 */
uint32_t tcdr3 : 8; /* [23:16], r/w, 0x0 */
uint32_t wcdr : 8; /* [31:24], r/w, 0x0 */
} BF;
uint32_t WORD;
} TCDR;
};
typedef volatile struct timer_reg timer_reg_t;
#endif /* __TIMER_REG_H__ */

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