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Merge pull request #991 from Ralim/fix-ci-formatter

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Fix ci formatter
This commit is contained in:
Ben V. Brown
2021-06-06 07:43:37 +10:00
committed by GitHub
parent 27c7166922 5a0f3e13d8
commit 3bee1411a3
10 changed files with 576 additions and 697 deletions
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5
.github/workflows/push.yml vendored
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@@ -134,9 +134,8 @@ jobs:
- name: setup
run: ./setup.sh
# Disabled until I can sort it out
# - name: Check formatting with clang-format
# run: cd source && make clean && make check-style
- name: Check formatting with clang-format
run: cd source && make clean && make check-style
- name: Check python formatting with black
run: black --check Translations

258
source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h vendored
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@@ -1897,18 +1897,22 @@ extern "C" {
#define COMP_LOCK __HAL_COMP_LOCK
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
: __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
: __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
: __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
: __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
@@ -1919,134 +1923,112 @@ extern "C" {
(((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#endif
#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
: __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
: __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
: __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
: __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
: __HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
: __HAL_COMP_COMP6_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
: __HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
: __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#endif
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \
: __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \
: __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \
: __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \
: __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : __HAL_COMP_COMP7_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : __HAL_COMP_COMP7_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : __HAL_COMP_COMP7_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \
: __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \
: __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \
: __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \
: __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() \
: __HAL_COMP_COMP7_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() \
: __HAL_COMP_COMP7_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() \
: __HAL_COMP_COMP7_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() \
: __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
#endif
#if defined(STM32F373xC) || defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())

216
source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h vendored
View File

@@ -53,112 +53,76 @@ extern "C" {
* @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
? DMA_FLAG_TC6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_TC7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 : DMA_FLAG_TC5)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_TC7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 \
: DMA_FLAG_TC5)
/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
? DMA_FLAG_HT6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_HT7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 : DMA_FLAG_HT5)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_HT7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 \
: DMA_FLAG_HT5)
/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
? DMA_FLAG_TE6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_TE7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 : DMA_FLAG_TE5)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_TE7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 \
: DMA_FLAG_TE5)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
? DMA_FLAG_GL6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_GL7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 : DMA_FLAG_GL5)
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_GL7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 \
: DMA_FLAG_GL5)
/**
* @brief Get the DMA Channel pending flags.
@@ -200,68 +164,56 @@ extern "C" {
* @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 : DMA_FLAG_TC7)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 \
: DMA_FLAG_TC7)
/**
* @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 : DMA_FLAG_HT7)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 \
: DMA_FLAG_HT7)
/**
* @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 : DMA_FLAG_TE7)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 \
: DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 : DMA_FLAG_GL7)
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 \
: DMA_FLAG_GL7)
/**
* @brief Get the DMA Channel pending flags.

12
source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h vendored
View File

@@ -799,10 +799,14 @@ extern "C" {
#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0uL : ((__GPIOx__) == (GPIOB)) ? 1uL : ((__GPIOx__) == (GPIOC)) ? 2uL : ((__GPIOx__) == (GPIOD)) ? 3uL : 4uL)
#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#define GPIO_GET_INDEX(__GPIOx__) \
(((__GPIOx__) == (GPIOA)) \
? 0uL \
: ((__GPIOx__) == (GPIOB)) ? 1uL : ((__GPIOx__) == (GPIOC)) ? 2uL : ((__GPIOx__) == (GPIOD)) ? 3uL : ((__GPIOx__) == (GPIOE)) ? 4uL : ((__GPIOx__) == (GPIOF)) ? 5uL : 6uL)
#define GPIO_GET_INDEX(__GPIOx__) \
(((__GPIOx__) == (GPIOA)) ? 0uL \
: ((__GPIOx__) == (GPIOB)) ? 1uL \
: ((__GPIOx__) == (GPIOC)) ? 2uL \
: ((__GPIOx__) == (GPIOD)) ? 3uL \
: ((__GPIOx__) == (GPIOE)) ? 4uL \
: ((__GPIOx__) == (GPIOF)) ? 5uL \
: 6uL)
#endif
#define AFIO_REMAP_ENABLE(REMAP_PIN) \

7
source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h vendored
View File

@@ -659,9 +659,10 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U) ? 4U : I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) \
(((__DUTYCYCLE__) == I2C_DUTYCYCLE_2) ? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) \
(((__SPEED__) <= 100000U) ? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) \
: ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U) ? 1U : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) \
(((__SPEED__) <= 100000U) ? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) \
: ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U) ? 1U \
: ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))

147
source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h vendored
View File

@@ -1374,11 +1374,11 @@ mode.
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
*/
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) \
: (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
/**
* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
@@ -1392,11 +1392,11 @@ mode.
* @param __COMPARE__ specifies the Capture Compare register new value.
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) : ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) \
: ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
/**
* @brief Get the TIM Capture Compare Register value on runtime.
@@ -1409,10 +1409,11 @@ mode.
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCR1) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) : ((__HANDLE__)->Instance->CCR4))
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) \
: ((__HANDLE__)->Instance->CCR4))
/**
* @brief Set the TIM Output compare preload.
@@ -1425,11 +1426,11 @@ mode.
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) \
: ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
/**
* @brief Reset the TIM Output compare preload.
@@ -1442,11 +1443,11 @@ mode.
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) \
: ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
/**
* @brief Enable fast mode for a given channel.
@@ -1463,11 +1464,11 @@ mode.
* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) \
: ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
/**
* @brief Disable fast mode for a given channel.
@@ -1484,11 +1485,11 @@ mode.
* trigger input is 5 clock cycles.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) \
: ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@@ -1691,40 +1692,41 @@ mode.
#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) \
: ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) \
: ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) \
: ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) : ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) \
: ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? (__HANDLE__)->ChannelState[0] \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] : (__HANDLE__)->ChannelState[3])
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] \
: (__HANDLE__)->ChannelState[3])
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) : ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) \
: ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \
do { \
@@ -1734,16 +1736,17 @@ mode.
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
} while (0)
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? (__HANDLE__)->ChannelNState[0] \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] : (__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] \
: (__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) : ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) \
: ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \
do { \

258
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h vendored
View File

@@ -1422,18 +1422,22 @@ extern "C" {
#define COMP_LOCK __HAL_COMP_LOCK
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
: __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
: __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
: __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
: __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
@@ -1444,134 +1448,112 @@ extern "C" {
(((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#endif
#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
: __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
: __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
: __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
: __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
: __HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
: __HAL_COMP_COMP6_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
: __HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
: __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#endif
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \
: __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \
: __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \
: __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \
: __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : __HAL_COMP_COMP7_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : __HAL_COMP_COMP7_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : __HAL_COMP_COMP7_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \
: __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \
: __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \
: __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \
: __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() \
: __HAL_COMP_COMP7_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() \
: __HAL_COMP_COMP7_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() \
: __HAL_COMP_COMP7_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() \
: __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
#endif
#if defined(STM32F373xC) || defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())

216
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h vendored
View File

@@ -69,112 +69,76 @@ extern "C" {
* @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
? DMA_FLAG_TC6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_TC7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 : DMA_FLAG_TC5)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_TC7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 \
: DMA_FLAG_TC5)
/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
? DMA_FLAG_HT6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_HT7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 : DMA_FLAG_HT5)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_HT7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 \
: DMA_FLAG_HT5)
/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
? DMA_FLAG_TE6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_TE7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 : DMA_FLAG_TE5)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_TE7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 \
: DMA_FLAG_TE5)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
? DMA_FLAG_GL6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_GL7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 : DMA_FLAG_GL5)
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_GL7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 \
: DMA_FLAG_GL5)
/**
* @brief Get the DMA Channel pending flags.
@@ -216,68 +180,56 @@ extern "C" {
* @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 : DMA_FLAG_TC7)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 \
: DMA_FLAG_TC7)
/**
* @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 : DMA_FLAG_HT7)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 \
: DMA_FLAG_HT7)
/**
* @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 : DMA_FLAG_TE7)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 \
: DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 : DMA_FLAG_GL7)
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 \
: DMA_FLAG_GL7)
/**
* @brief Get the DMA Channel pending flags.

7
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h vendored
View File

@@ -577,9 +577,10 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U) ? 4U : I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) \
(((__DUTYCYCLE__) == I2C_DUTYCYCLE_2) ? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) \
(((__SPEED__) <= 100000U) ? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) \
: ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U) ? 1U : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) \
(((__SPEED__) <= 100000U) ? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) \
: ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U) ? 1U \
: ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))

147
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h vendored
View File

@@ -1376,11 +1376,11 @@ mode.
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
*/
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) \
: (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
/**
* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
@@ -1394,11 +1394,11 @@ mode.
* @param __COMPARE__ specifies the Capture Compare register new value.
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) : ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) \
: ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
/**
* @brief Get the TIM Capture Compare Register value on runtime.
@@ -1411,10 +1411,11 @@ mode.
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCR1) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) : ((__HANDLE__)->Instance->CCR4))
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) \
: ((__HANDLE__)->Instance->CCR4))
/**
* @brief Set the TIM Output compare preload.
@@ -1427,11 +1428,11 @@ mode.
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) \
: ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
/**
* @brief Reset the TIM Output compare preload.
@@ -1444,11 +1445,11 @@ mode.
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) \
: ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
/**
* @brief Enable fast mode for a given channel.
@@ -1465,11 +1466,11 @@ mode.
* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) \
: ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
/**
* @brief Disable fast mode for a given channel.
@@ -1486,11 +1487,11 @@ mode.
* trigger input is 5 clock cycles.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) \
: ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@@ -1693,40 +1694,41 @@ mode.
#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) \
: ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) \
: ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) \
: ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) : ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) \
: ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? (__HANDLE__)->ChannelState[0] \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] : (__HANDLE__)->ChannelState[3])
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] \
: (__HANDLE__)->ChannelState[3])
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) : ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) \
: ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \
do { \
@@ -1736,16 +1738,17 @@ mode.
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
} while (0)
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? (__HANDLE__)->ChannelNState[0] \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] : (__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] \
: (__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) \
? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) : ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) \
: ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) \
: ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \
do { \