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Import updated hal_drv

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This commit is contained in:
Ben V. Brown
2024-06-04 21:54:12 +10:00
parent 453cbb2db8
commit 30c7bea3c7
6 changed files with 44 additions and 92 deletions
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16
source/Core/BSP/Pinecilv2/peripheral_config.h
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@@ -123,7 +123,7 @@
#define DMA0_CH0_CONFIG \
{ \
.id = 0, .ch = 0, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_4BYTE, .dst_burst_size = DMA_BURST_4BYTE, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_4, .dst_burst_size = DMA_BURST_SIZE_4, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
@@ -133,7 +133,7 @@
#define DMA0_CH1_CONFIG \
{ \
.id = 0, .ch = 1, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_4BYTE, .dst_burst_size = DMA_BURST_4BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_4, .dst_burst_size = DMA_BURST_SIZE_4, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
@@ -143,7 +143,7 @@
#define DMA0_CH2_CONFIG \
{ \
.id = 0, .ch = 2, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_UART1_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
@@ -153,7 +153,7 @@
#define DMA0_CH3_CONFIG \
{ \
.id = 0, .ch = 3, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_SPI0_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
@@ -163,7 +163,7 @@
#define DMA0_CH4_CONFIG \
{ \
.id = 0, .ch = 4, .direction = DMA_PERIPH_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_SPI0_RX, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
@@ -173,7 +173,7 @@
#define DMA0_CH5_CONFIG \
{ \
.id = 0, .ch = 5, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
@@ -183,7 +183,7 @@
#define DMA0_CH6_CONFIG \
{ \
.id = 0, .ch = 6, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
@@ -193,7 +193,7 @@
#define DMA0_CH7_CONFIG \
{ \
.id = 0, .ch = 7, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif