diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h index dda00291..9d51c162 100644 --- a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h @@ -81,10 +81,10 @@ enum dma_index_type { #define DMA_TRANSFER_WIDTH_16BIT 1 #define DMA_TRANSFER_WIDTH_32BIT 2 -#define DMA_BURST_1BYTE 0 -#define DMA_BURST_4BYTE 1 -#define DMA_BURST_8BYTE 2 -#define DMA_BURST_16BYTE 3 +#define DMA_BURST_INCR1 0 +#define DMA_BURST_INCR4 1 +#define DMA_BURST_INCR8 2 +#define DMA_BURST_INCR16 3 #define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88) #define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C) @@ -174,13 +174,13 @@ typedef struct dma_device { uint8_t dst_burst_size; uint8_t src_width; uint8_t dst_width; - dma_lli_ctrl_t *lli_cfg; + uint8_t intr; /* private param */ + dma_lli_ctrl_t *lli_cfg;/* private param*/ } dma_device_t; #define DMA_DEV(dev) ((dma_device_t *)dev) int dma_register(enum dma_index_type index, const char *name); -int dma_allocate_register(const char *name); int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size); #ifdef __cplusplus diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c index 595784a6..f2581e01 100644 --- a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c @@ -56,9 +56,8 @@ static void internal_rc32m_init(void) { tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON); BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal); - if (BL_IS_REG_BIT_SET(BL_RD_REG(GLB_BASE, GLB_CLK_CFG0), GLB_CHIP_RDY)) { + if (BL_IS_REG_BIT_SET(BL_RD_REG(GLB_BASE, GLB_CLK_CFG0), GLB_CHIP_RDY)) break; - } } } #endif @@ -457,6 +456,11 @@ void peripheral_clock_init(void) { tmpVal |= (1 << BL_AHB_SLAVE1_USB); GLB_Set_USB_CLK(1); #endif + +#if defined(BSP_USING_DMA) + tmpVal |= (1 << BL_AHB_SLAVE1_DMA); +#endif + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); } @@ -465,9 +469,9 @@ uint32_t system_clock_get(enum system_clock_type type) { case SYSTEM_CLOCK_ROOT_CLOCK: if (GLB_Get_Root_CLK_Sel() == 0) { return 32 * 1000 * 1000; - } else if (GLB_Get_Root_CLK_Sel() == 1) { + } else if (GLB_Get_Root_CLK_Sel() == 1) return 32 * 1000 * 1000; - } else { + else { uint32_t tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL); if (tmpVal == 0) { diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c index 1bd85630..2eaea527 100644 --- a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c @@ -79,13 +79,13 @@ int dma_open(struct device *dev, uint16_t oflag) { /* Disable all interrupt */ DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK); - /* Enable uart interrupt*/ CPU_Interrupt_Disable(DMA_ALL_IRQn); DMA_Disable(); DMA_Channel_Disable(dma_device->ch); + dma_device->intr = 0; chCfg.ch = dma_device->ch; chCfg.dir = dma_device->direction; chCfg.srcPeriph = dma_device->src_req; @@ -101,7 +101,7 @@ int dma_open(struct device *dev, uint16_t oflag) { DMA_Enable(); Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ); - /* Enable uart interrupt*/ + /* Enable dma interrupt*/ CPU_Interrupt_Enable(DMA_ALL_IRQn); return 0; } @@ -121,14 +121,14 @@ int dma_control(struct device *dev, int cmd, void *args) { /* Dma interrupt configuration */ DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK); DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK); - + dma_device->intr = 1; break; case DEVICE_CTRL_CLR_INT: /* Dma interrupt configuration */ DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK); DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK); - + dma_device->intr = 0; break; case DEVICE_CTRL_GET_INT: @@ -181,6 +181,7 @@ int dma_close(struct device *dev) { DMA_Channel_Disable(dma_device->ch); DMA_Channel_Init(&chCfg); + dma_device->intr = 0; return 0; } @@ -205,62 +206,6 @@ int dma_register(enum dma_index_type index, const char *name) { return device_register(dev, name); } -static BL_Err_Type dma_scan_unregister_device(uint8_t *allocate_index) { - struct device *dev; - dlist_t *node; - uint8_t dma_index = 0; - uint32_t dma_handle[DMA_MAX_INDEX]; - - for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) { - dma_handle[dma_index] = 0xff; - } - - /* get registered dma handle list*/ - dlist_for_each(node, device_get_list_header()) { - dev = dlist_entry(node, struct device, list); - - if (dev->type == DEVICE_CLASS_DMA) { - dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET; - } - } - - for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) { - if (dma_handle[dma_index] == 0xff) { - *allocate_index = dma_index; - return SUCCESS; - } - } - - return ERROR; -} - -int dma_allocate_register(const char *name) { - struct device *dev; - uint8_t index; - - if (DMA_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - if (dma_scan_unregister_device(&index) == ERROR) { - return -DEVICE_ENOSPACE; - } - - dev = &(dmax_device[index].parent); - - dev->open = dma_open; - dev->close = dma_close; - dev->control = dma_control; - // dev->write = dma_write; - // dev->read = dma_read; - - dev->status = DEVICE_UNREGISTER; - dev->type = DEVICE_CLASS_DMA; - dev->handle = NULL; - - return device_register(dev, name); -} - /** * @brief * @@ -271,14 +216,13 @@ int dma_allocate_register(const char *name) { * @return int */ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size) { -#if defined(BSP_USING_DMA0_CH0) || defined(BSP_USING_DMA0_CH1) || defined(BSP_USING_DMA0_CH2) || defined(BSP_USING_DMA0_CH3) || defined(BSP_USING_DMA0_CH4) || defined(BSP_USING_DMA0_CH5) || \ - defined(BSP_USING_DMA0_CH6) || defined(BSP_USING_DMA0_CH7) - +#ifdef BSP_USING_DMA uint32_t malloc_count; uint32_t remain_len; uint32_t actual_transfer_len = 0; uint32_t actual_transfer_offset = 0; dma_control_data_t dma_ctrl_cfg; + bool intr = false; dma_device_t *dma_device = (dma_device_t *)dev; @@ -315,6 +259,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_ } dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL)); + intr = dma_device->intr; malloc_count = actual_transfer_len / 4095; remain_len = actual_transfer_len % 4095; @@ -326,15 +271,14 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_ dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count); if (dma_device->lli_cfg) { + dma_ctrl_cfg.bits.TransferSize = 4095; + dma_ctrl_cfg.bits.I = 0; /*transfer_size will be integer multiple of 4095*n or 4095*2*n or 4095*4*n,(n>0) */ for (uint32_t i = 0; i < malloc_count; i++) { dma_device->lli_cfg[i].src_addr = src_addr; dma_device->lli_cfg[i].dst_addr = dst_addr; dma_device->lli_cfg[i].nextlli = 0; - dma_ctrl_cfg.bits.TransferSize = 4095; - dma_ctrl_cfg.bits.I = 0; - if (dma_ctrl_cfg.bits.SI) { src_addr += actual_transfer_offset; } @@ -347,7 +291,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_ if (remain_len) { dma_ctrl_cfg.bits.TransferSize = remain_len; } - dma_ctrl_cfg.bits.I = 1; + dma_ctrl_cfg.bits.I = intr; if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) { dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0]; diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c index 0491bc71..6212b7ef 100644 --- a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c @@ -21,11 +21,13 @@ * */ #include "hal_usb.h" +#include "bl702_dma.h" #include "bl702_glb.h" #include "bl702_usb.h" #include "hal_dma.h" #include "hal_mtimer.h" + #define USE_INTERNAL_TRANSCEIVER // #define ENABLE_LPM_INT // #define ENABLE_SOF3MS_INT @@ -396,8 +398,8 @@ int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz usb_lli_list.cfg.bits.TransferSize = size; usb_lli_list.cfg.bits.DI = 0; usb_lli_list.cfg.bits.SI = 1; - usb_lli_list.cfg.bits.SBSize = DMA_BURST_16BYTE; - usb_lli_list.cfg.bits.DBSize = DMA_BURST_1BYTE; + usb_lli_list.cfg.bits.SBSize = DMA_BURST_SIZE_16; + usb_lli_list.cfg.bits.DBSize = DMA_BURST_SIZE_1; dma_channel_update(usb_device->tx_dma, (void *)((uint32_t)&usb_lli_list)); dma_channel_start(usb_device->tx_dma); return 0; @@ -420,8 +422,8 @@ int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) { usb_lli_list.cfg.bits.TransferSize = size; usb_lli_list.cfg.bits.DI = 1; usb_lli_list.cfg.bits.SI = 0; - usb_lli_list.cfg.bits.SBSize = DMA_BURST_1BYTE; - usb_lli_list.cfg.bits.DBSize = DMA_BURST_16BYTE; + usb_lli_list.cfg.bits.SBSize = DMA_BURST_SIZE_1; + usb_lli_list.cfg.bits.DBSize = DMA_BURST_SIZE_16; dma_channel_update(usb_device->rx_dma, (void *)((uint32_t)&usb_lli_list)); dma_channel_start(usb_device->rx_dma); return 0; @@ -817,9 +819,8 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u memcopy_to_fifo((void *)ep_tx_fifo_addr, (uint8_t *)data, data_len); /* Clear NAK and enable ep */ - if (USB_EP_GET_IDX(ep) != 0) { + if (USB_EP_GET_IDX(ep) != 0) USB_Set_EPx_Rdy(USB_EP_GET_IDX(ep)); - } USB_DC_LOG_DBG("EP%d write %u bytes\r\n", ep_idx, data_len); if (ret_bytes) { diff --git a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c index c030a559..19c7d072 100644 --- a/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c +++ b/source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c @@ -41,6 +41,9 @@ void USB_DoNothing_IRQHandler(void) { /*---------------------------------------------------------------------------- Vector Table *----------------------------------------------------------------------------*/ +#define VECT_TAB_OFFSET \ + 0x00 /*!< Vector Table base offset field. \ + This value must be a multiple of 0x200. */ /*---------------------------------------------------------------------------- System initialization function @@ -124,7 +127,7 @@ void SystemInit(void) { #ifdef BFLB_EFLASH_LOADER Interrupt_Handler_Register(USB_IRQn, USB_DoNothing_IRQHandler); #endif - /* init for for all platform */ + /* init bor for all platform */ system_bor_init(); /* global IRQ enable */ __enable_irq(); diff --git a/source/Core/BSP/Pinecilv2/peripheral_config.h b/source/Core/BSP/Pinecilv2/peripheral_config.h index 21b56915..375de426 100644 --- a/source/Core/BSP/Pinecilv2/peripheral_config.h +++ b/source/Core/BSP/Pinecilv2/peripheral_config.h @@ -123,7 +123,7 @@ #define DMA0_CH0_CONFIG \ { \ .id = 0, .ch = 0, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \ - .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_4BYTE, .dst_burst_size = DMA_BURST_4BYTE, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \ + .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_4, .dst_burst_size = DMA_BURST_SIZE_4, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \ } #endif #endif @@ -133,7 +133,7 @@ #define DMA0_CH1_CONFIG \ { \ .id = 0, .ch = 1, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \ - .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_4BYTE, .dst_burst_size = DMA_BURST_4BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ + .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_4, .dst_burst_size = DMA_BURST_SIZE_4, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ } #endif #endif @@ -143,7 +143,7 @@ #define DMA0_CH2_CONFIG \ { \ .id = 0, .ch = 2, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_UART1_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \ - .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ + .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ } #endif #endif @@ -153,7 +153,7 @@ #define DMA0_CH3_CONFIG \ { \ .id = 0, .ch = 3, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_SPI0_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \ - .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ + .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ } #endif #endif @@ -163,7 +163,7 @@ #define DMA0_CH4_CONFIG \ { \ .id = 0, .ch = 4, .direction = DMA_PERIPH_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_SPI0_RX, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \ - .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ + .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \ } #endif #endif @@ -173,7 +173,7 @@ #define DMA0_CH5_CONFIG \ { \ .id = 0, .ch = 5, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \ - .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ + .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ } #endif #endif @@ -183,7 +183,7 @@ #define DMA0_CH6_CONFIG \ { \ .id = 0, .ch = 6, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \ - .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ + .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \ } #endif #endif @@ -193,7 +193,7 @@ #define DMA0_CH7_CONFIG \ { \ .id = 0, .ch = 7, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \ - .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \ + .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \ } #endif #endif