244 lines
8.8 KiB
C
244 lines
8.8 KiB
C
/**
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* @file peripheral_config.h
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* @brief
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*
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* Copyright (c) 2021 Bouffalolab team
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*/
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#ifndef _PERIPHERAL_CONFIG_H_
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#define _PERIPHERAL_CONFIG_H_
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/* PERIPHERAL USING LIST */
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#define BSP_USING_UART0
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/* ----------------------*/
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/* PERIPHERAL With DMA LIST */
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#define BSP_USING_DAC0
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#define BSP_USING_DMA0_CH0
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#define BSP_USING_DMA0_CH1
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#define BSP_USING_DMA0_CH2
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#define BSP_USING_DMA0_CH3
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#define BSP_USING_DMA0_CH4
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#define BSP_USING_DMA0_CH5
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#define BSP_USING_DMA0_CH6
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#define BSP_USING_DMA0_CH7
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/* PERIPHERAL CONFIG */
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#if defined(BSP_USING_DAC0)
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#ifndef DAC_CONFIG
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#define DAC_CONFIG \
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{ \
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.channels = DAC_CHANNEL_0, \
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.sample_freq = DAC_SAMPLE_FREQ_500KHZ, \
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.vref = DAC_VREF_INTERNAL, \
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}
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#endif
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#endif
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#if defined(BSP_USING_UART0)
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#ifndef UART0_CONFIG
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#define UART0_CONFIG \
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{ \
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.id = 0, \
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.baudrate = 2000000, \
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.databits = UART_DATA_LEN_8, \
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.stopbits = UART_STOP_ONE, \
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.parity = UART_PAR_NONE, \
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.fifo_threshold = 0, \
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}
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#endif
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#endif
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#if defined(BSP_USING_UART1)
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#ifndef UART1_CONFIG
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#define UART1_CONFIG \
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{ \
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.id = 1, \
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.baudrate = 2000000, \
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.databits = UART_DATA_LEN_8, \
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.stopbits = UART_STOP_ONE, \
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.parity = UART_PAR_NONE, \
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.fifo_threshold = 63, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH0)
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#ifndef DMA0_CH0_CONFIG
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#define DMA0_CH0_CONFIG \
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{ \
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.id = 0, \
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.ch = 0, \
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.direction = DMA_MEMORY_TO_MEMORY, \
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_NONE, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.src_burst_size = DMA_BURST_1BYTE, \
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.dst_burst_size = DMA_BURST_1BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_32BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH1)
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#ifndef DMA0_CH1_CONFIG
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#define DMA0_CH1_CONFIG \
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{ \
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.id = 0, \
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.ch = 1, \
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.direction = DMA_MEMORY_TO_MEMORY, \
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_NONE, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.src_burst_size = DMA_BURST_1BYTE, \
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.dst_burst_size = DMA_BURST_1BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_16BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH2)
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#ifndef DMA0_CH2_CONFIG
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#define DMA0_CH2_CONFIG \
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{ \
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.id = 0, \
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.ch = 2, \
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.direction = DMA_MEMORY_TO_PERIPH, \
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_UART1_TX, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
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.src_burst_size = DMA_BURST_1BYTE, \
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.dst_burst_size = DMA_BURST_1BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_8BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH3)
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#ifndef DMA0_CH3_CONFIG
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#define DMA0_CH3_CONFIG \
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{ \
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.id = 0, \
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.ch = 3, \
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.direction = DMA_MEMORY_TO_PERIPH, \
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_SPI0_TX, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
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.src_burst_size = DMA_BURST_1BYTE, \
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.dst_burst_size = DMA_BURST_1BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_8BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH4)
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#ifndef DMA0_CH4_CONFIG
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#define DMA0_CH4_CONFIG \
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{ \
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.id = 0, \
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.ch = 4, \
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.direction = DMA_PERIPH_TO_MEMORY, \
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_SPI0_RX, \
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.dst_req = DMA_REQUEST_NONE, \
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.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.src_burst_size = DMA_BURST_1BYTE, \
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.dst_burst_size = DMA_BURST_1BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_8BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH5)
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#ifndef DMA0_CH5_CONFIG
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#define DMA0_CH5_CONFIG \
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{ \
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.id = 0, \
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.ch = 5, \
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.direction = DMA_MEMORY_TO_PERIPH, \
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.transfer_mode = DMA_LLI_CYCLE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_I2S_TX, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
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.src_burst_size = DMA_BURST_1BYTE, \
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.dst_burst_size = DMA_BURST_1BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_16BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH6)
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#ifndef DMA0_CH6_CONFIG
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#define DMA0_CH6_CONFIG \
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{ \
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.id = 0, \
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.ch = 6, \
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.direction = DMA_MEMORY_TO_PERIPH, \
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.transfer_mode = DMA_LLI_CYCLE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_I2S_TX, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
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.src_burst_size = DMA_BURST_1BYTE, \
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.dst_burst_size = DMA_BURST_1BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_16BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH7)
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#ifndef DMA0_CH7_CONFIG
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#define DMA0_CH7_CONFIG \
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{ \
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.id = 0, \
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.ch = 7, \
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.direction = DMA_MEMORY_TO_MEMORY, \
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_NONE, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.src_burst_size = DMA_BURST_1BYTE, \
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.dst_burst_size = DMA_BURST_1BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_32BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
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}
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#endif
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#endif
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#endif
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