1cbcba924f
Adds auto rotation support using the proper orientation detection. (Not using raw values). Should Fix and close #29
295 lines
7.8 KiB
C
295 lines
7.8 KiB
C
/*
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* I2C.h hardware interface class
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* Based on the STM32 app note AN2824
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*/
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#include "I2C.h"
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/* I2C STOP mask */
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#define CR1_STOP_Set ((uint16_t)0x0200)
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#define CR1_STOP_Reset ((uint16_t)0xFDFF)
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/* I2C ACK mask */
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#define CR1_ACK_Set ((uint16_t)0x0400)
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#define CR1_ACK_Reset ((uint16_t)0xFBFF)
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/* I2C POS mask */
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#define CR1_POS_Set ((uint16_t)0x0800)
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#define CR1_POS_Reset ((uint16_t)0xF7FF)
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#define NULL ((void *)0)
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/*
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* Configure the I2C port hardware
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*/
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void I2C_Configuration(void) {
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GPIO_InitTypeDef GPIO_InitStructure;
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I2C_InitTypeDef I2C_InitStructure;
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/* PB6,7 SCL and SDA */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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/* I2C1 configuration ------------------------------------------------------*/
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I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
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I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
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I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
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I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
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I2C_InitStructure.I2C_ClockSpeed = 400000; //400k
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I2C_Init(I2C1, &I2C_InitStructure);
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I2C_Cmd(I2C1, ENABLE);
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}
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/*
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* Writes a page of data over I2C using the I2C1 peripheral in the stm32
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*
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*/
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void I2C_PageWrite(u8* buf, u8 nbyte, u8 deviceaddr) {
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while (I2C_GetFlagStatus(I2C1, I2C_FLAG_BUSY)) {
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}
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// Intiate Start Sequence
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I2C_GenerateSTART(I2C1, ENABLE);
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while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)) {
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}
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// Send Address
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I2C_Send7bitAddress(I2C1, deviceaddr << 1, I2C_Direction_Transmitter);
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while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) {
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}
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// Write first byte EV8_1
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I2C_SendData(I2C1, *buf++);
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while (--nbyte) {
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// wait on BTF
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while (!I2C_GetFlagStatus(I2C1, I2C_FLAG_BTF)) {
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}
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I2C_SendData(I2C1, *buf++);
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}
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while (!I2C_GetFlagStatus(I2C1, I2C_FLAG_BTF)) {
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}
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I2C_GenerateSTOP(I2C1, ENABLE);
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while (I2C_GetFlagStatus(I2C1, I2C_FLAG_STOPF)) {
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}
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}
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//Based on code from http://iamjustinwang.blogspot.com.au/2016/03/stm32f103-i2c-master-driver.html
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int I2C_Master_Read(uint8_t deviceAddr, uint8_t readAddr, uint8_t* pBuffer,
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uint16_t numByteToRead) {
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__IO uint32_t temp = 0;
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volatile int I2C_TimeOut = 0;
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// /* While the bus is busy * /
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I2C_TimeOut = 3000;
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while (I2C_GetFlagStatus(I2C1, I2C_FLAG_BUSY)) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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// * Send START condition * /
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I2C_GenerateSTART(I2C1, ENABLE);
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// / * Test on EV5 and clear it * /
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I2C_TimeOut = 3000;
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while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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// / * Send address for write * /
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I2C_Send7bitAddress(I2C1, deviceAddr, I2C_Direction_Transmitter);
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// / * Test on EV6 and clear it * /
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I2C_TimeOut = 3000;
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while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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// / * Send the internal address to read from: Only one byte address * /
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I2C_SendData(I2C1, readAddr);
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/// * Test on EV8 and clear it * /
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I2C_TimeOut = 3000;
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while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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/// * Send STRAT condition a second time * /
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I2C_GenerateSTART(I2C1, ENABLE);
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/// * Test on EV5 and clear it * /
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I2C_TimeOut = 3000;
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while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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// * Send address for read * /
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I2C_Send7bitAddress(I2C1, deviceAddr, I2C_Direction_Receiver);
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if (numByteToRead == 1) {
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/* Wait until ADDR is set */
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I2C_TimeOut = 3000;
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while ((I2C1->SR1 & 0x0002) != 0x0002) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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/* Clear ACK bit */
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I2C1->CR1 &= CR1_ACK_Reset;
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/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
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software sequence must complete before the current byte end of transfer */
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__disable_irq();
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/* Clear ADDR flag */
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temp = I2C1->SR2;
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/* Program the STOP */
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I2C_GenerateSTOP(I2C1, ENABLE);
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/* Re-enable IRQs */
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__enable_irq();
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/* Wait until a data is received in DR register (RXNE = 1) EV7 */
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I2C_TimeOut = 3000;
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while ((I2C1->SR1 & 0x00040) != 0x000040) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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/* Read the data */
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*pBuffer = I2C1->DR;
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} else if (numByteToRead == 2) {
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/* Set POS bit */
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I2C1->CR1 |= CR1_POS_Set;
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/* Wait until ADDR is set: EV6 */
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I2C_TimeOut = 3000;
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while ((I2C1->SR1 & 0x0002) != 0x0002) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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/* EV6_1: The acknowledge disable should be done just after EV6,
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that is after ADDR is cleared, so disable all active IRQs around ADDR clearing and
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ACK clearing */
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__disable_irq();
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/* Clear ADDR by reading SR2 register */
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temp = I2C1->SR2;
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/* Clear ACK */
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I2C1->CR1 &= CR1_ACK_Reset;
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/*Re-enable IRQs */
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__enable_irq();
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/* Wait until BTF is set */
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I2C_TimeOut = 3000;
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while ((I2C1->SR1 & 0x00004) != 0x000004) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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/* Disable IRQs around STOP programming and data reading */
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__disable_irq();
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/* Program the STOP */
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I2C_GenerateSTOP(I2C1, ENABLE);
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/* Read first data */
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*pBuffer = I2C1->DR;
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/* Re-enable IRQs */
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__enable_irq();
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/**/
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pBuffer++;
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/* Read second data */
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*pBuffer = I2C1->DR;
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/* Clear POS bit */
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I2C1->CR1 &= CR1_POS_Reset;
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}
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else { //numByteToRead > 2
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// * Test on EV6 and clear it * /
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I2C_TimeOut = 3000;
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while (!I2C_CheckEvent(I2C1,
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I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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// * While there is data to be read * /
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while (numByteToRead) {
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/* Receive bytes from first byte until byte N-3 */
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if (numByteToRead != 3) {
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/* Poll on BTF to receive data because in polling mode we can not guarantee the
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EV7 software sequence is managed before the current byte transfer completes */
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I2C_TimeOut = 3000;
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while ((I2C1->SR1 & 0x00004) != 0x000004) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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/* Read data */
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*pBuffer = I2C1->DR;
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pBuffer++;
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/* Decrement the read bytes counter */
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numByteToRead--;
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}
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/* it remains to read three data: data N-2, data N-1, Data N */
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if (numByteToRead == 3) {
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/* Wait until BTF is set: Data N-2 in DR and data N -1 in shift register */
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I2C_TimeOut = 3000;
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while ((I2C1->SR1 & 0x00004) != 0x000004) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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/* Clear ACK */
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I2C1->CR1 &= CR1_ACK_Reset;
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/* Disable IRQs around data reading and STOP programming */
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__disable_irq();
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/* Read Data N-2 */
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*pBuffer = I2C1->DR;
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/* Increment */
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pBuffer++;
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/* Program the STOP */
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I2C1->CR1 |= CR1_STOP_Set;
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/* Read DataN-1 */
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*pBuffer = I2C1->DR;
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/* Re-enable IRQs */
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__enable_irq();
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/* Increment */
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pBuffer++;
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/* Wait until RXNE is set (DR contains the last data) */
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I2C_TimeOut = 3000;
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while ((I2C1->SR1 & 0x00040) != 0x000040) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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/* Read DataN */
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*pBuffer = I2C1->DR;
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/* Reset the number of bytes to be read by master */
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numByteToRead = 0;
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}
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}
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}
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/* Make sure that the STOP bit is cleared by Hardware before CR1 write access */
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I2C_TimeOut = 3000;
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while ((I2C1->CR1 & 0x200) == 0x200) {
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if (I2C_TimeOut-- <= 0) {
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return 1;
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}
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}
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// * Enable Acknowledgment to be ready for another reception * /
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I2C_AcknowledgeConfig(I2C1, ENABLE);
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return 0;
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}
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