60 lines
2.5 KiB
C
60 lines
2.5 KiB
C
/**
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* @file clock_config.h
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* @brief
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*
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* Copyright (c) 2021 Bouffalolab team
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*/
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#ifndef _CLOCK_CONFIG_H
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#define _CLOCK_CONFIG_H
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#define XTAL_TYPE EXTERNAL_XTAL_32M
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#define XTAL_32K_TYPE INTERNAL_RC_32K
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#define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_144M
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#define BSP_AUDIO_PLL_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
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#define BSP_FCLK_DIV 0
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#define BSP_BCLK_DIV 1
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#define BSP_UART_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
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#define BSP_UART_CLOCK_DIV 0
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#define BSP_I2C_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK
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#define BSP_I2C_CLOCK_DIV 0
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#define BSP_SPI_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK
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#define BSP_SPI_CLOCK_DIV 0
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#define BSP_TIMER0_CLOCK_SOURCE ROOT_CLOCK_SOURCE_32K_CLK
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#define BSP_TIMER0_CLOCK_DIV 22
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#define BSP_TIMER1_CLOCK_SOURCE ROOT_CLOCK_SOURCE_32K_CLK
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#define BSP_TIMER1_CLOCK_DIV 31
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#define BSP_WDT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_FCLK
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#define BSP_WDT_CLOCK_DIV 0
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#define BSP_PWM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_32K_CLK
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#define BSP_PWM_CLOCK_DIV 31
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#define BSP_IR_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
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#define BSP_IR_CLOCK_DIV 0
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#define BSP_ADC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
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#define BSP_ADC_CLOCK_DIV 0
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#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
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#define BSP_DAC_CLOCK_DIV 2
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#define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
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#define BSP_CAM_CLOCK_DIV 3
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#define BSP_QDEC_KEYSCAN_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
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#define BSP_QDEC_KEYSCAN_CLOCK_DIV 31
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#endif |