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forked from me/IronOS

Update PD to support awareness of having inductor for DCDC op

+ fix voltage divider to be more on point
+ Create adjustment for thermal mass causes overshoot
This commit is contained in:
Ben V. Brown
2021-05-03 22:36:25 +10:00
parent dd5daf51e3
commit ee12c99d9e
7 changed files with 54 additions and 25 deletions

View File

@@ -19,7 +19,7 @@ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) {
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
if (hadc == &hadc1) {
counter++;
if (counter % 64 == 0) {
if (counter % 32 == 0) { // 64 = 128ms, 32 = 64ms
if (pidTaskNotification) {
vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);

View File

@@ -58,8 +58,8 @@ typedef struct {
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with
injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata
sheet of these devices for more details. */
injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
Refer to errata sheet of these devices for more details. */
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
This parameter must be a value of @ref ADCEx_injected_rank
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel