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Finishing up file cleanup

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Ben V. Brown
2020-05-30 00:10:23 +10:00
parent 42ebd37bc8
commit ed8e5232b6
3 changed files with 345 additions and 480 deletions
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634
workspace/TS100/Core/Src/system_stm32f1xx.c → workspace/TS100/Core/BSP/Miniware/system_stm32f1xx.c
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@@ -1,317 +1,317 @@
// This file was automatically generated by the STM Cube software // This file was automatically generated by the STM Cube software
// And as such, is BSD licneced from STM // And as such, is BSD licneced from STM
#include "stm32f1xx.h" #include "stm32f1xx.h"
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */ This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
/*!< Uncomment the following line if you need to use external SRAM */ /*!< Uncomment the following line if you need to use external SRAM */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/* #define DATA_IN_ExtSRAM */ /* #define DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
#ifndef LOCAL_BUILD #ifndef LOCAL_BUILD
#define VECT_TAB_OFFSET 0x00004000U /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00004000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#else #else
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#warning LOCAL_BUILD SETUP #warning LOCAL_BUILD SETUP
#endif #endif
//We offset this by 0x4000 to because of the bootloader //We offset this by 0x4000 to because of the bootloader
/******************************************************************************* /*******************************************************************************
* Clock Definitions * Clock Definitions
*******************************************************************************/ *******************************************************************************/
#if defined(STM32F100xB) ||defined(STM32F100xE) #if defined(STM32F100xB) ||defined(STM32F100xE)
uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */ uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */
#else /*!< HSI Selected as System Clock source */ #else /*!< HSI Selected as System Clock source */
uint32_t SystemCoreClock = 64000000U; /*!< System Clock Frequency (Core Clock) */ uint32_t SystemCoreClock = 64000000U; /*!< System Clock Frequency (Core Clock) */
#endif #endif
const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
/** /**
* @brief Setup the microcontroller system * @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the * Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable. * SystemCoreClock variable.
* @note This function should be used only after reset. * @note This function should be used only after reset.
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemInit (void) void SystemInit (void)
{ {
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */ /* Set HSION bit */
RCC->CR |= 0x00000001U; RCC->CR |= 0x00000001U;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC) #if !defined(STM32F105xC) && !defined(STM32F107xC)
RCC->CFGR &= 0xF8FF0000U; RCC->CFGR &= 0xF8FF0000U;
#else #else
RCC->CFGR &= 0xF0FF0000U; RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */ #endif /* STM32F105xC */
/* Reset HSEON, CSSON and PLLON bits */ /* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= 0xFEF6FFFFU; RCC->CR &= 0xFEF6FFFFU;
/* Reset HSEBYP bit */ /* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU; RCC->CR &= 0xFFFBFFFFU;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= 0xFF80FFFFU; RCC->CFGR &= 0xFF80FFFFU;
#if defined(STM32F105xC) || defined(STM32F107xC) #if defined(STM32F105xC) || defined(STM32F107xC)
/* Reset PLL2ON and PLL3ON bits */ /* Reset PLL2ON and PLL3ON bits */
RCC->CR &= 0xEBFFFFFFU; RCC->CR &= 0xEBFFFFFFU;
/* Disable all interrupts and clear pending bits */ /* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000U; RCC->CIR = 0x00FF0000U;
/* Reset CFGR2 register */ /* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000U; RCC->CFGR2 = 0x00000000U;
#elif defined(STM32F100xB) || defined(STM32F100xE) #elif defined(STM32F100xB) || defined(STM32F100xE)
/* Disable all interrupts and clear pending bits */ /* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000U; RCC->CIR = 0x009F0000U;
/* Reset CFGR2 register */ /* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000U; RCC->CFGR2 = 0x00000000U;
#else #else
/* Disable all interrupts and clear pending bits */ /* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000U; RCC->CIR = 0x009F0000U;
#endif /* STM32F105xC */ #endif /* STM32F105xC */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM #ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl(); SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
#endif #endif
#ifdef VECT_TAB_SRAM #ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else #else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif #endif
} }
/** /**
* @brief Update SystemCoreClock variable according to Clock Register Values. * @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can * The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure * be used by the user application to setup the SysTick timer or configure
* other parameters. * other parameters.
* *
* @note Each time the core clock (HCLK) changes, this function must be called * @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration * to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect. * based on this variable will be incorrect.
* *
* @note - The system frequency computed by this function is not the real * @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source: * constant and the selected clock source:
* *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
* *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
* *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied by the PLL factors. * or HSI_VALUE(*) multiplied by the PLL factors.
* *
* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz) but the real value may vary depending on the variations * 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature. * in voltage and temperature.
* *
* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz or 25 MHz, depending on the product used), user has to ensure * 8 MHz or 25 MHz, depending on the product used), user has to ensure
* that HSE_VALUE is same as the real frequency of the crystal used. * that HSE_VALUE is same as the real frequency of the crystal used.
* Otherwise, this function may have wrong result. * Otherwise, this function may have wrong result.
* *
* - The result of this function could be not correct when using fractional * - The result of this function could be not correct when using fractional
* value for HSE crystal. * value for HSE crystal.
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate (void)
{ {
uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
#if defined(STM32F105xC) || defined(STM32F107xC) #if defined(STM32F105xC) || defined(STM32F107xC)
uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
#endif /* STM32F105xC */ #endif /* STM32F105xC */
#if defined(STM32F100xB) || defined(STM32F100xE) #if defined(STM32F100xB) || defined(STM32F100xE)
uint32_t prediv1factor = 0U; uint32_t prediv1factor = 0U;
#endif /* STM32F100xB or STM32F100xE */ #endif /* STM32F100xB or STM32F100xE */
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp) switch (tmp)
{ {
case 0x00U: /* HSI used as system clock */ case 0x00U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
case 0x04U: /* HSE used as system clock */ case 0x04U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE; SystemCoreClock = HSE_VALUE;
break; break;
case 0x08U: /* PLL used as system clock */ case 0x08U: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/ /* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
#if !defined(STM32F105xC) && !defined(STM32F107xC) #if !defined(STM32F105xC) && !defined(STM32F107xC)
pllmull = ( pllmull >> 18U) + 2U; pllmull = ( pllmull >> 18U) + 2U;
if (pllsource == 0x00U) if (pllsource == 0x00U)
{ {
/* HSI oscillator clock divided by 2 selected as PLL clock entry */ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
} }
else else
{ {
#if defined(STM32F100xB) || defined(STM32F100xE) #if defined(STM32F100xB) || defined(STM32F100xE)
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
/* HSE oscillator clock selected as PREDIV1 clock entry */ /* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else #else
/* HSE selected as PLL clock entry */ /* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */ {/* HSE oscillator clock divided by 2 */
SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
} }
else else
{ {
SystemCoreClock = HSE_VALUE * pllmull; SystemCoreClock = HSE_VALUE * pllmull;
} }
#endif #endif
} }
#else #else
pllmull = pllmull >> 18U; pllmull = pllmull >> 18U;
if (pllmull != 0x0DU) if (pllmull != 0x0DU)
{ {
pllmull += 2U; pllmull += 2U;
} }
else else
{ /* PLL multiplication factor = PLL input clock * 6.5 */ { /* PLL multiplication factor = PLL input clock * 6.5 */
pllmull = 13U / 2U; pllmull = 13U / 2U;
} }
if (pllsource == 0x00U) if (pllsource == 0x00U)
{ {
/* HSI oscillator clock divided by 2 selected as PLL clock entry */ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
} }
else else
{/* PREDIV1 selected as PLL clock entry */ {/* PREDIV1 selected as PLL clock entry */
/* Get PREDIV1 clock source and division factor */ /* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
if (prediv1source == 0U) if (prediv1source == 0U)
{ {
/* HSE oscillator clock selected as PREDIV1 clock entry */ /* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
} }
else else
{/* PLL2 clock selected as PREDIV1 clock entry */ {/* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */ /* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
} }
} }
#endif /* STM32F105xC */ #endif /* STM32F105xC */
break; break;
default: default:
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
} }
/* Compute HCLK clock frequency ----------------*/ /* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */ /* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */ /* HCLK clock frequency */
SystemCoreClock >>= tmp; SystemCoreClock >>= tmp;
} }
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/** /**
* @brief Setup the external memory controller. Called in startup_stm32f1xx.s * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
* before jump to __main * before jump to __main
* @param None * @param None
* @retval None * @retval None
*/ */
#ifdef DATA_IN_ExtSRAM #ifdef DATA_IN_ExtSRAM
/** /**
* @brief Setup the external memory controller. * @brief Setup the external memory controller.
* Called in startup_stm32f1xx_xx.s/.c before jump to main. * Called in startup_stm32f1xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted on STM3210E-EVAL * This function configures the external SRAM mounted on STM3210E-EVAL
* board (STM32 High density devices). This SRAM will be used as program * board (STM32 High density devices). This SRAM will be used as program
* data memory (including heap and stack). * data memory (including heap and stack).
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemInit_ExtMemCtl(void) void SystemInit_ExtMemCtl(void)
{ {
__IO uint32_t tmpreg; __IO uint32_t tmpreg;
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */ required, then adjust the Register Addresses */
/* Enable FSMC clock */ /* Enable FSMC clock */
RCC->AHBENR = 0x00000114U; RCC->AHBENR = 0x00000114U;
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0U; RCC->APB2ENR = 0x000001E0U;
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
(void)(tmpreg); (void)(tmpreg);
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/ /*---------------- SRAM Address lines configuration -------------------------*/
/*---------------- NOE and NWE configuration --------------------------------*/ /*---------------- NOE and NWE configuration --------------------------------*/
/*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/
GPIOD->CRL = 0x44BB44BBU; GPIOD->CRL = 0x44BB44BBU;
GPIOD->CRH = 0xBBBBBBBBU; GPIOD->CRH = 0xBBBBBBBBU;
GPIOE->CRL = 0xB44444BBU; GPIOE->CRL = 0xB44444BBU;
GPIOE->CRH = 0xBBBBBBBBU; GPIOE->CRH = 0xBBBBBBBBU;
GPIOF->CRL = 0x44BBBBBBU; GPIOF->CRL = 0x44BBBBBBU;
GPIOF->CRH = 0xBBBB4444U; GPIOF->CRH = 0xBBBB4444U;
GPIOG->CRL = 0x44BBBBBBU; GPIOG->CRL = 0x44BBBBBBU;
GPIOG->CRH = 0x444B4B44U; GPIOG->CRH = 0x444B4B44U;
/*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
FSMC_Bank1->BTCR[4U] = 0x00001091U; FSMC_Bank1->BTCR[4U] = 0x00001091U;
FSMC_Bank1->BTCR[5U] = 0x00110212U; FSMC_Bank1->BTCR[5U] = 0x00110212U;
} }
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

118
workspace/TS100/Core/Src/syscalls.c
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@@ -1,51 +1,3 @@
/**
*****************************************************************************
**
** File : syscalls.c
**
** Author : Auto-generated by STM32CubeIDE
**
** Abstract : STM32CubeIDE Minimal System calls file
**
** For more information about which c-functions
** need which of these lowlevel functions
** please consult the Newlib libc-manual
**
** Environment : STM32CubeIDE MCU
**
** Distribution: The file is distributed as is, without any warranty
** of any kind.
**
*****************************************************************************
**
** <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
**
*****************************************************************************
*/
/* Includes */ /* Includes */
#include <sys/stat.h> #include <sys/stat.h>
#include <stdlib.h> #include <stdlib.h>
@@ -56,129 +8,107 @@
#include <sys/time.h> #include <sys/time.h>
#include <sys/times.h> #include <sys/times.h>
/* Variables */ /* Variables */
//#undef errno //#undef errno
extern int errno; extern int errno;
extern int __io_putchar(int ch) __attribute__((weak)); extern int __io_putchar(int ch) __attribute__((weak));
extern int __io_getchar(void) __attribute__((weak)); extern int __io_getchar(void) __attribute__((weak));
register char * stack_ptr asm("sp"); register char *stack_ptr asm("sp");
char *__env[1] = { 0 }; char *__env[1] = { 0 };
char **environ = __env; char **environ = __env;
/* Functions */ /* Functions */
void initialise_monitor_handles() void initialise_monitor_handles() {
{
} }
int _getpid(void) int _getpid(void) {
{
return 1; return 1;
} }
int _kill(int pid, int sig) int _kill(int pid, int sig) {
{
errno = EINVAL; errno = EINVAL;
return -1; return -1;
} }
void _exit (int status) void _exit(int status) {
{
_kill(status, -1); _kill(status, -1);
while (1) {} /* Make sure we hang here */ while (1) {
} /* Make sure we hang here */
} }
__attribute__((weak)) int _read(int file, char *ptr, int len) __attribute__((weak)) int _read(int file, char *ptr, int len) {
{
int DataIdx; int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++) for (DataIdx = 0; DataIdx < len; DataIdx++) {
{
*ptr++ = __io_getchar(); *ptr++ = __io_getchar();
} }
return len; return len;
} }
__attribute__((weak)) int _write(int file, char *ptr, int len) __attribute__((weak)) int _write(int file, char *ptr, int len) {
{
int DataIdx; int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++) for (DataIdx = 0; DataIdx < len; DataIdx++) {
{
__io_putchar(*ptr++); __io_putchar(*ptr++);
} }
return len; return len;
} }
int _close(int file) int _close(int file) {
{
return -1; return -1;
} }
int _fstat(int file, struct stat *st) {
int _fstat(int file, struct stat *st)
{
st->st_mode = S_IFCHR; st->st_mode = S_IFCHR;
return 0; return 0;
} }
int _isatty(int file) int _isatty(int file) {
{
return 1; return 1;
} }
int _lseek(int file, int ptr, int dir) int _lseek(int file, int ptr, int dir) {
{
return 0; return 0;
} }
int _open(char *path, int flags, ...) int _open(char *path, int flags, ...) {
{
/* Pretend like we always fail */ /* Pretend like we always fail */
return -1; return -1;
} }
int _wait(int *status) int _wait(int *status) {
{
errno = ECHILD; errno = ECHILD;
return -1; return -1;
} }
int _unlink(char *name) int _unlink(char *name) {
{
errno = ENOENT; errno = ENOENT;
return -1; return -1;
} }
int _times(struct tms *buf) int _times(struct tms *buf) {
{
return -1; return -1;
} }
int _stat(char *file, struct stat *st) int _stat(char *file, struct stat *st) {
{
st->st_mode = S_IFCHR; st->st_mode = S_IFCHR;
return 0; return 0;
} }
int _link(char *old, char *new) int _link(char *old, char *new) {
{
errno = EMLINK; errno = EMLINK;
return -1; return -1;
} }
int _fork(void) int _fork(void) {
{
errno = EAGAIN; errno = EAGAIN;
return -1; return -1;
} }
int _execve(char *name, char **argv, char **env) int _execve(char *name, char **argv, char **env) {
{
errno = ENOMEM; errno = ENOMEM;
return -1; return -1;
} }

73
workspace/TS100/Core/Src/sysmem.c
View File

@@ -1,83 +1,18 @@
/**
*****************************************************************************
**
** File : sysmem.c
**
** Author : Auto-generated by STM32CubeIDE
**
** Abstract : STM32CubeIDE Minimal System Memory calls file
**
** For more information about which c-functions
** need which of these lowlevel functions
** please consult the Newlib libc-manual
**
** Environment : STM32CubeIDE MCU
**
** Distribution: The file is distributed as is, without any warranty
** of any kind.
**
*****************************************************************************
**
** <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
**
*****************************************************************************
*/
/* Includes */ /* Includes */
#include <errno.h> #include <errno.h>
#include <stdio.h> #include <stdio.h>
/* Variables */ /* Variables */
extern int errno; extern int errno;
register char * stack_ptr asm("sp"); register char *stack_ptr asm("sp");
/* Functions */ /* Functions */
/** /**
_sbrk _sbrk
Increase program data space. Malloc and related functions depend on this Increase program data space. Malloc and related functions depend on this
**/ **/
caddr_t _sbrk(int incr) caddr_t _sbrk(int incr) {
{ return (void*) -1;
extern char end asm("end");
static char *heap_end;
char *prev_heap_end;
if (heap_end == 0)
heap_end = &end;
prev_heap_end = heap_end;
if (heap_end + incr > stack_ptr)
{
errno = ENOMEM;
return (caddr_t) -1;
}
heap_end += incr;
return (caddr_t) prev_heap_end;
} }