|
|
|
|
@@ -46,7 +46,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
|
|
|
|
|
if (tries > 64) {
|
|
|
|
|
i2c_stop_on_bus(I2C0);
|
|
|
|
|
/* i2c master sends STOP signal successfully */
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
unlock();
|
|
|
|
|
@@ -61,8 +61,8 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
|
|
|
|
|
/* enable acknowledge */
|
|
|
|
|
i2c_ack_config(I2C0, I2C_ACK_ENABLE);
|
|
|
|
|
/* i2c master sends start signal only when the bus is idle */
|
|
|
|
|
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) &&
|
|
|
|
|
(timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -83,8 +83,8 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
|
|
|
|
|
break;
|
|
|
|
|
case I2C_SEND_ADDRESS:
|
|
|
|
|
/* i2c master sends START signal successfully */
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) &&
|
|
|
|
|
(timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND))
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -104,14 +104,15 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
|
|
|
|
|
break;
|
|
|
|
|
case I2C_CLEAR_ADDRESS_FLAG:
|
|
|
|
|
/* address flag set means i2c slave sends ACK */
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) &&
|
|
|
|
|
(timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND))
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
|
|
|
|
|
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
|
|
|
|
|
i2c_stop_on_bus(I2C0);
|
|
|
|
|
/* i2c master sends STOP signal successfully */
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200)
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
// Address NACK'd
|
|
|
|
|
@@ -126,7 +127,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
|
|
|
|
|
} else {
|
|
|
|
|
i2c_stop_on_bus(I2C0);
|
|
|
|
|
/* i2c master sends STOP signal successfully */
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
// Address NACK'd
|
|
|
|
|
@@ -137,8 +138,8 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
|
|
|
|
|
case I2C_TRANSMIT_DATA:
|
|
|
|
|
if (0 == in_rx_cycle) {
|
|
|
|
|
/* wait until the transmit data buffer is empty */
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) &&
|
|
|
|
|
(timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE))
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -151,8 +152,8 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
|
|
|
|
|
in_rx_cycle = 0;
|
|
|
|
|
}
|
|
|
|
|
/* wait until BTC bit is set */
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) &&
|
|
|
|
|
(timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC))
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -185,11 +186,11 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
|
|
|
|
|
} else { /* more than one byte master reception procedure (DMA) */
|
|
|
|
|
dma_deinit(DMA0, DMA_CH6);
|
|
|
|
|
dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
|
|
|
|
|
dma_init_struct.memory_addr = (uint32_t)p_buffer;
|
|
|
|
|
dma_init_struct.memory_addr = (uint32_t) p_buffer;
|
|
|
|
|
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
|
|
|
|
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
|
|
|
|
|
dma_init_struct.number = number_of_byte;
|
|
|
|
|
dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0);
|
|
|
|
|
dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0);
|
|
|
|
|
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
|
|
|
|
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
|
|
|
|
|
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
|
|
|
|
@@ -202,7 +203,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
|
|
|
|
|
dma_channel_enable(DMA0, DMA_CH6);
|
|
|
|
|
/* wait until BTC bit is set */
|
|
|
|
|
while (!dma_flag_get(DMA0, DMA_CH6, DMA_FLAG_FTF)) {
|
|
|
|
|
osDelay(1);
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
/* send a stop condition to I2C bus*/
|
|
|
|
|
i2c_stop_on_bus(I2C0);
|
|
|
|
|
@@ -213,7 +214,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
|
|
|
|
|
break;
|
|
|
|
|
case I2C_STOP:
|
|
|
|
|
/* i2c master sends STOP signal successfully */
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -256,7 +257,8 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
|
|
|
|
|
switch (state) {
|
|
|
|
|
case I2C_START:
|
|
|
|
|
/* i2c master sends start signal only when the bus is idle */
|
|
|
|
|
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -271,8 +273,8 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
|
|
|
|
|
break;
|
|
|
|
|
case I2C_SEND_ADDRESS:
|
|
|
|
|
/* i2c master sends START signal successfully */
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) &&
|
|
|
|
|
(timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND))
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -288,14 +290,15 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
|
|
|
|
|
break;
|
|
|
|
|
case I2C_CLEAR_ADDRESS_FLAG:
|
|
|
|
|
/* address flag set means i2c slave sends ACK */
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) &&
|
|
|
|
|
(timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND))
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
|
|
|
|
|
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
|
|
|
|
|
i2c_stop_on_bus(I2C0);
|
|
|
|
|
/* i2c master sends STOP signal successfully */
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200)
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
// Address NACK'd
|
|
|
|
|
@@ -311,7 +314,7 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
|
|
|
|
|
// Dont retry as this means a NAK
|
|
|
|
|
i2c_stop_on_bus(I2C0);
|
|
|
|
|
/* i2c master sends STOP signal successfully */
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
unlock();
|
|
|
|
|
@@ -320,7 +323,8 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
|
|
|
|
|
break;
|
|
|
|
|
case I2C_TRANSMIT_DATA:
|
|
|
|
|
/* wait until the transmit data buffer is empty */
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE))
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -338,11 +342,11 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
|
|
|
|
|
;
|
|
|
|
|
dma_deinit(DMA0, DMA_CH5);
|
|
|
|
|
dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
|
|
|
|
|
dma_init_struct.memory_addr = (uint32_t)p_buffer;
|
|
|
|
|
dma_init_struct.memory_addr = (uint32_t) p_buffer;
|
|
|
|
|
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
|
|
|
|
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
|
|
|
|
|
dma_init_struct.number = number_of_byte;
|
|
|
|
|
dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0);
|
|
|
|
|
dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0);
|
|
|
|
|
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
|
|
|
|
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
|
|
|
|
|
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
|
|
|
|
@@ -353,18 +357,18 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
|
|
|
|
|
dma_channel_enable(DMA0, DMA_CH5);
|
|
|
|
|
/* wait until BTC bit is set */
|
|
|
|
|
while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {
|
|
|
|
|
osDelay(2);
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
/* wait until BTC bit is set */
|
|
|
|
|
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC))
|
|
|
|
|
;
|
|
|
|
|
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) {
|
|
|
|
|
}
|
|
|
|
|
state = I2C_STOP;
|
|
|
|
|
break;
|
|
|
|
|
case I2C_STOP:
|
|
|
|
|
/* send a stop condition to I2C bus */
|
|
|
|
|
i2c_stop_on_bus(I2C0);
|
|
|
|
|
/* i2c master sends STOP signal successfully */
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -397,20 +401,23 @@ bool FRToSI2C::probe(uint16_t DevAddress) {
|
|
|
|
|
return Mem_Read(DevAddress, 0x00, temp, sizeof(temp));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
|
|
|
|
|
void FRToSI2C::I2C_Unstick() {
|
|
|
|
|
unstick_I2C();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool FRToSI2C::lock() {
|
|
|
|
|
if (I2CSemaphore == nullptr) {
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
return xSemaphoreTake(I2CSemaphore, 1000) == pdTRUE;
|
|
|
|
|
return xSemaphoreTake(I2CSemaphore, TICKS_SECOND) == pdTRUE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); }
|
|
|
|
|
void FRToSI2C::unlock() {
|
|
|
|
|
xSemaphoreGive(I2CSemaphore);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool FRToSI2C::writeRegistersBulk(const uint8_t address,
|
|
|
|
|
const I2C_REG *registers,
|
|
|
|
|
const uint8_t registersLength) {
|
|
|
|
|
const I2C_REG *registers, const uint8_t registersLength) {
|
|
|
|
|
for (int index = 0; index < registersLength; index++) {
|
|
|
|
|
if (!I2C_RegisterWrite(address, registers[index].reg,
|
|
|
|
|
registers[index].val)) {
|
|
|
|
|
@@ -440,7 +447,8 @@ bool FRToSI2C::wakePart(uint16_t DevAddress) {
|
|
|
|
|
switch (state) {
|
|
|
|
|
case I2C_START:
|
|
|
|
|
/* i2c master sends start signal only when the bus is idle */
|
|
|
|
|
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -455,8 +463,8 @@ bool FRToSI2C::wakePart(uint16_t DevAddress) {
|
|
|
|
|
break;
|
|
|
|
|
case I2C_SEND_ADDRESS:
|
|
|
|
|
/* i2c master sends START signal successfully */
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) &&
|
|
|
|
|
(timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND))
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
@@ -472,14 +480,15 @@ bool FRToSI2C::wakePart(uint16_t DevAddress) {
|
|
|
|
|
break;
|
|
|
|
|
case I2C_CLEAR_ADDRESS_FLAG:
|
|
|
|
|
/* address flag set means i2c slave sends ACK */
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) &&
|
|
|
|
|
(timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND))
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
|
|
|
|
|
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
|
|
|
|
|
i2c_stop_on_bus(I2C0);
|
|
|
|
|
/* i2c master sends STOP signal successfully */
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200)
|
|
|
|
|
&& (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
// Address NACK'd
|
|
|
|
|
@@ -495,7 +504,7 @@ bool FRToSI2C::wakePart(uint16_t DevAddress) {
|
|
|
|
|
// Dont retry as this means a NAK
|
|
|
|
|
i2c_stop_on_bus(I2C0);
|
|
|
|
|
/* i2c master sends STOP signal successfully */
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
unlock();
|
|
|
|
|
@@ -507,7 +516,7 @@ bool FRToSI2C::wakePart(uint16_t DevAddress) {
|
|
|
|
|
/* send a stop condition to I2C bus */
|
|
|
|
|
i2c_stop_on_bus(I2C0);
|
|
|
|
|
/* i2c master sends STOP signal successfully */
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
|
|
|
|
|
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
|
|
|
|
|
timeout++;
|
|
|
|
|
}
|
|
|
|
|
if (timeout < I2C_TIME_OUT) {
|
|
|
|
|
|