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This commit is contained in:
Ben V. Brown
2021-02-24 19:38:51 +11:00
parent 8d39ff1cbc
commit c210bf983c
1 changed files with 175 additions and 164 deletions
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159
source/Core/BSP/Pine64/I2C_Wrapper.cpp
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@@ -47,83 +47,37 @@ struct i2c_state {
i2c_step currentStep;
bool isMemoryWrite;
bool wakePart;
uint8_t deviceAddress;
uint8_t memoryAddress;
uint8_t * buffer;
uint16_t numberOfBytes;
dma_parameter_struct dma_init_struct;
};
volatile i2c_state currentState;
bool perform_i2c_transaction(uint16_t DevAddress, uint16_t memory_address, uint8_t *p_buffer, uint16_t number_of_byte, bool isWrite, bool isWakeOnly) {
{
//TODO is this required
/* disable I2C0 */
i2c_disable(I2C0);
/* enable I2C0 */
i2c_enable(I2C0);
void perform_i2c_step() {
//Performs next step of the i2c state machine
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
//Arb error - we lost the bus / nacked
currentState.currentStep = Error_occured;
} else if (i2c_flag_get(I2C0, I2C_FLAG_BERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_BERR);
// Bus Error
currentState.currentStep = Error_occured;
} else if (i2c_flag_get(I2C0, I2C_FLAG_LOSTARB)) {
i2c_flag_clear(I2C0, I2C_FLAG_LOSTARB);
// Bus Error
currentState.currentStep = Error_occured;
} else if (i2c_flag_get(I2C0, I2C_FLAG_PECERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_PECERR);
// Bus Error
currentState.currentStep = Error_occured;
}
i2c_interrupt_disable(I2C0, I2C_INT_ERR);
i2c_interrupt_disable(I2C0, I2C_INT_BUF);
i2c_interrupt_disable(I2C0, I2C_INT_EV);
currentState.isMemoryWrite = isWrite;
currentState.wakePart = isWakeOnly;
if (!isWakeOnly) {
//Setup DMA
currentState.dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
currentState.dma_init_struct.memory_addr = (uint32_t) p_buffer;
currentState.dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
currentState.dma_init_struct.number = number_of_byte;
currentState.dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0);
currentState.dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
currentState.dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
currentState.dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
if (currentState.isMemoryWrite) {
dma_deinit(DMA0, DMA_CH5);
currentState.dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
dma_init(DMA0, DMA_CH5, (dma_parameter_struct*) &currentState.dma_init_struct);
} else {
dma_deinit(DMA0, DMA_CH6);
currentState.dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
dma_init(DMA0, DMA_CH6, (dma_parameter_struct*) &currentState.dma_init_struct);
}
if (!currentState.isMemoryWrite) {
i2c_dma_last_transfer_config(I2C0, I2C_DMALST_ON);
}
}
//Clear flags
I2C_STAT0(I2C0) = 0;
I2C_STAT1(I2C0) = 0;
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
currentState.currentStep = Write_start; //Always start in write mode
TickType_t timeout = xTaskGetTickCount() + TICKS_SECOND;
while ((currentState.currentStep != Done) && (currentState.currentStep != Error_occured)) {
if (xTaskGetTickCount() > timeout) {
i2c_stop_on_bus(I2C0);
return false;
}
// if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
// i2c_flag_clear(I2C0, I2C_FLAG_AERR);
// //Arb error - we lost the bus / nacked
// currentState.currentStep = Error_occured;
// } else if (i2c_flag_get(I2C0, I2C_FLAG_BERR)) {
// i2c_flag_clear(I2C0, I2C_FLAG_BERR);
// // Bus Error
// currentState.currentStep = Error_occured;
// } else if (i2c_flag_get(I2C0, I2C_FLAG_LOSTARB)) {
// i2c_flag_clear(I2C0, I2C_FLAG_LOSTARB);
// // Bus Error
// currentState.currentStep = Error_occured;
// } else if (i2c_flag_get(I2C0, I2C_FLAG_PECERR)) {
// i2c_flag_clear(I2C0, I2C_FLAG_PECERR);
// // Bus Error
// currentState.currentStep = Error_occured;
// }
switch (currentState.currentStep) {
case Error_occured:
i2c_stop_on_bus(I2C0);
return false;
break;
case Write_start:
@@ -141,7 +95,7 @@ bool perform_i2c_transaction(uint16_t DevAddress, uint16_t memory_address, uint8
/* i2c master sends START signal successfully */
if (i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) {
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
i2c_master_addressing(I2C0, currentState.deviceAddress, I2C_TRANSMITTER);
currentState.currentStep = Write_device_memory_address;
}
break;
@@ -164,7 +118,7 @@ bool perform_i2c_transaction(uint16_t DevAddress, uint16_t memory_address, uint8
currentState.currentStep = Send_stop;
} else if (i2c_flag_get(I2C0, I2C_FLAG_TBE)) {
// Write out the 8 byte address
i2c_data_transmit(I2C0, memory_address);
i2c_data_transmit(I2C0, currentState.memoryAddress);
if (currentState.isMemoryWrite) {
currentState.currentStep = Write_device_data_start;
@@ -206,7 +160,7 @@ bool perform_i2c_transaction(uint16_t DevAddress, uint16_t memory_address, uint8
case Read_device_address:
if (i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) {
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
i2c_master_addressing(I2C0, DevAddress, I2C_RECEIVER);
i2c_master_addressing(I2C0, currentState.deviceAddress, I2C_RECEIVER);
currentState.currentStep = Read_device_data_start;
}
break;
@@ -218,9 +172,9 @@ bool perform_i2c_transaction(uint16_t DevAddress, uint16_t memory_address, uint8
currentState.currentStep = Error_occured;
}
/* one byte master reception procedure (polling) */
if (number_of_byte == 0) {
if (currentState.numberOfBytes == 0) {
currentState.currentStep = Send_stop;
} else if (number_of_byte == 1) {
} else if (currentState.numberOfBytes == 1) {
/* disable acknowledge */
i2c_ack_config(I2C0, I2C_ACK_DISABLE);
/* clear ADDSEND register by reading I2C_STAT0 then I2C_STAT1 register
@@ -233,7 +187,7 @@ bool perform_i2c_transaction(uint16_t DevAddress, uint16_t memory_address, uint8
while (!i2c_flag_get(I2C0, I2C_FLAG_RBNE))
;
/* read the byte received from the EEPROM */
*p_buffer = i2c_data_receive(I2C0);
*currentState.buffer = i2c_data_receive(I2C0);
currentState.currentStep = Wait_stop;
} else { /* more than one byte master reception procedure (DMA) */
/* enable I2C0 DMA */
@@ -264,8 +218,65 @@ bool perform_i2c_transaction(uint16_t DevAddress, uint16_t memory_address, uint8
break;
default:
//If we get here something is amiss
return;
}
}
bool perform_i2c_transaction(uint16_t DevAddress, uint16_t memory_address, uint8_t *p_buffer, uint16_t number_of_byte, bool isWrite, bool isWakeOnly) {
{
//TODO is this required
/* disable I2C0 */
i2c_disable(I2C0);
/* enable I2C0 */
i2c_enable(I2C0);
}
i2c_interrupt_disable(I2C0, I2C_INT_ERR);
i2c_interrupt_disable(I2C0, I2C_INT_BUF);
i2c_interrupt_disable(I2C0, I2C_INT_EV);
currentState.isMemoryWrite = isWrite;
currentState.wakePart = isWakeOnly;
currentState.deviceAddress = DevAddress;
currentState.memoryAddress = memory_address;
currentState.numberOfBytes = number_of_byte;
currentState.buffer = p_buffer;
if (!isWakeOnly) {
//Setup DMA
currentState.dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
currentState.dma_init_struct.memory_addr = (uint32_t) p_buffer;
currentState.dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
currentState.dma_init_struct.number = number_of_byte;
currentState.dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0);
currentState.dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
currentState.dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
currentState.dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
if (currentState.isMemoryWrite) {
dma_deinit(DMA0, DMA_CH5);
currentState.dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
dma_init(DMA0, DMA_CH5, (dma_parameter_struct*) &currentState.dma_init_struct);
} else {
dma_deinit(DMA0, DMA_CH6);
currentState.dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
dma_init(DMA0, DMA_CH6, (dma_parameter_struct*) &currentState.dma_init_struct);
}
if (!currentState.isMemoryWrite) {
i2c_dma_last_transfer_config(I2C0, I2C_DMALST_ON);
}
}
//Clear flags
I2C_STAT0(I2C0) = 0;
I2C_STAT1(I2C0) = 0;
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
currentState.currentStep = Write_start; //Always start in write mode
TickType_t timeout = xTaskGetTickCount() + TICKS_SECOND;
while ((currentState.currentStep != Done) && (currentState.currentStep != Error_occured)) {
if (xTaskGetTickCount() > timeout) {
i2c_stop_on_bus(I2C0);
return false;
}
perform_i2c_step();
}
return true;
}