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Format headers

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This commit is contained in:
Ben V. Brown
2021-01-17 10:53:49 +11:00
parent f786901da0
commit bf5055edaa
173 changed files with 42831 additions and 47623 deletions
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98
source/Core/Drivers/Si7210_defines.h
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@@ -8,31 +8,31 @@
#ifndef CORE_DRIVERS_SI7210_DEFINES_H_
#define CORE_DRIVERS_SI7210_DEFINES_H_
#define SI7210_ADDRESS (0x30<<1)
#define SI7210_REG_ID 0xC0
#define SI7210_ADDRESS (0x30 << 1)
#define SI7210_REG_ID 0xC0
/* Si7210 Register addresses */
#define SI7210_HREVID 0xC0U
#define SI7210_DSPSIGM 0xC1U
#define SI7210_DSPSIGL 0xC2U
#define SI7210_DSPSIGSEL 0xC3U
#define SI7210_POWER_CTRL 0xC4U
#define SI7210_ARAUTOINC 0xC5U
#define SI7210_CTRL1 0xC6U
#define SI7210_CTRL2 0xC7U
#define SI7210_SLTIME 0xC8U
#define SI7210_CTRL3 0xC9U
#define SI7210_A0 0xCAU
#define SI7210_A1 0xCBU
#define SI7210_A2 0xCCU
#define SI7210_CTRL4 0xCDU
#define SI7210_A3 0xCEU
#define SI7210_A4 0xCFU
#define SI7210_A5 0xD0U
#define SI7210_OTP_ADDR 0xE1U
#define SI7210_OTP_DATA 0xE2U
#define SI7210_OTP_CTRL 0xE3U
#define SI7210_TM_FG 0xE4U
#define SI7210_HREVID 0xC0U
#define SI7210_DSPSIGM 0xC1U
#define SI7210_DSPSIGL 0xC2U
#define SI7210_DSPSIGSEL 0xC3U
#define SI7210_POWER_CTRL 0xC4U
#define SI7210_ARAUTOINC 0xC5U
#define SI7210_CTRL1 0xC6U
#define SI7210_CTRL2 0xC7U
#define SI7210_SLTIME 0xC8U
#define SI7210_CTRL3 0xC9U
#define SI7210_A0 0xCAU
#define SI7210_A1 0xCBU
#define SI7210_A2 0xCCU
#define SI7210_CTRL4 0xCDU
#define SI7210_A3 0xCEU
#define SI7210_A4 0xCFU
#define SI7210_A5 0xD0U
#define SI7210_OTP_ADDR 0xE1U
#define SI7210_OTP_DATA 0xE2U
#define SI7210_OTP_CTRL 0xE3U
#define SI7210_TM_FG 0xE4U
/* Si7210 Register bit masks */
#define CHIP_ID_MASK 0xF0U
@@ -58,34 +58,32 @@
#define OTP_BUSY_MASK 0x01U
#define TM_FG_MASK 0x03U
#define DSP_SIGM_DATA_FLAG 0x80U
#define DSP_SIGM_DATA_MASK 0x7FU
#define DSP_SIGSEL_TEMP_MASK 0x01U
#define DSP_SIGSEL_FIELD_MASK 0x04U
#define DSP_SIGM_DATA_FLAG 0x80U
#define DSP_SIGM_DATA_MASK 0x7FU
#define DSP_SIGSEL_TEMP_MASK 0x01U
#define DSP_SIGSEL_FIELD_MASK 0x04U
/* Burst sizes */
#define DF_BW_1 0x0U << 1
#define DF_BW_2 0x1U << 1
#define DF_BW_4 0x2U << 1
#define DF_BW_8 0x3U << 1
#define DF_BW_16 0x4U << 1
#define DF_BW_32 0x5U << 1
#define DF_BW_64 0x6U << 1
#define DF_BW_128 0x7U << 1
#define DF_BW_256 0x8U << 1
#define DF_BW_512 0x9U << 1
#define DF_BW_1024 0xAU << 1
#define DF_BW_2048 0xBU << 1
#define DF_BW_4096 0xCU << 1
#define DF_BURSTSIZE_1 0x0U << 5
#define DF_BURSTSIZE_2 0x1U << 5
#define DF_BURSTSIZE_4 0x2U << 5
#define DF_BURSTSIZE_8 0x3U << 5
#define DF_BURSTSIZE_16 0x4U << 5
#define DF_BURSTSIZE_32 0x5U << 5
#define DF_BURSTSIZE_64 0x6U << 5
#define DF_BURSTSIZE_128 0x7U << 5
#define DF_BW_1 0x0U << 1
#define DF_BW_2 0x1U << 1
#define DF_BW_4 0x2U << 1
#define DF_BW_8 0x3U << 1
#define DF_BW_16 0x4U << 1
#define DF_BW_32 0x5U << 1
#define DF_BW_64 0x6U << 1
#define DF_BW_128 0x7U << 1
#define DF_BW_256 0x8U << 1
#define DF_BW_512 0x9U << 1
#define DF_BW_1024 0xAU << 1
#define DF_BW_2048 0xBU << 1
#define DF_BW_4096 0xCU << 1
#define DF_BURSTSIZE_1 0x0U << 5
#define DF_BURSTSIZE_2 0x1U << 5
#define DF_BURSTSIZE_4 0x2U << 5
#define DF_BURSTSIZE_8 0x3U << 5
#define DF_BURSTSIZE_16 0x4U << 5
#define DF_BURSTSIZE_32 0x5U << 5
#define DF_BURSTSIZE_64 0x6U << 5
#define DF_BURSTSIZE_128 0x7U << 5
#endif /* CORE_DRIVERS_SI7210_DEFINES_H_ */