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Merge pull request #801 from Ralim/formatting

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Formatting; creates clang format spec and re-formats everything to be the same.
This commit is contained in:
Ben V. Brown
2021-01-17 11:47:40 +11:00
committed by GitHub
parent 9bedfdf3df 67a0640f71
commit 31cbbc4489
275 changed files with 63286 additions and 71983 deletions
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138
source/.clang-format Normal file
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@@ -0,0 +1,138 @@
# Roughly based on LLVM, tweaked a tad for readability on wide screens
---
Language: Cpp
# BasedOnStyle: LLVM
AccessModifierOffset: -2
AlignAfterOpenBracket: Align
AlignConsecutiveMacros: true
AlignConsecutiveAssignments: true
AlignConsecutiveDeclarations: true
AlignEscapedNewlines: Left
AlignOperands: true
AlignTrailingComments: true
AllowAllArgumentsOnNextLine: true
AllowAllConstructorInitializersOnNextLine: true
AllowAllParametersOfDeclarationOnNextLine: true
AllowShortBlocksOnASingleLine: Empty
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: All
AllowShortLambdasOnASingleLine: All
AllowShortIfStatementsOnASingleLine: Never
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: MultiLine
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterCaseLabel: false
AfterClass: false
AfterControlStatement: false
AfterEnum: false
AfterFunction: false
AfterNamespace: false
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
AfterExternBlock: false
BeforeCatch: false
BeforeElse: false
IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakBeforeBinaryOperators: true
BreakBeforeBraces: Attach
BreakBeforeInheritanceComma: false
BreakInheritanceList: BeforeColon
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: false
BreakConstructorInitializers: BeforeColon
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 200
CommentPragmas: '^ IWYU pragma:'
CompactNamespaces: false
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: true
DeriveLineEnding: true
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
FixNamespaceComments: true
ForEachMacros:
- foreach
- Q_FOREACH
- BOOST_FOREACH
IncludeBlocks: Preserve
IncludeCategories:
- Regex: '^"(llvm|llvm-c|clang|clang-c)/'
Priority: 2
SortPriority: 0
- Regex: '^(<|"(gtest|gmock|isl|json)/)'
Priority: 3
SortPriority: 0
- Regex: '.*'
Priority: 1
SortPriority: 0
IncludeIsMainRegex: '(Test)?$'
IncludeIsMainSourceRegex: ''
IndentCaseLabels: false
IndentGotoLabels: true
IndentPPDirectives: None
IndentWidth: 2
IndentWrappedFunctionNames: false
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: true
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBinPackProtocolList: Auto
ObjCBlockIndentWidth: 2
ObjCSpaceAfterProperty: false
ObjCSpaceBeforeProtocolList: true
PenaltyBreakAssignment: 2
PenaltyBreakBeforeFirstCallParameter: 19
PenaltyBreakComment: 300
PenaltyBreakFirstLessLess: 120
PenaltyBreakString: 1000
PenaltyBreakTemplateDeclaration: 10
PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
ReflowComments: true
SortIncludes: true
SortUsingDeclarations: true
SpaceAfterCStyleCast: false
SpaceAfterLogicalNot: false
SpaceAfterTemplateKeyword: true
SpaceBeforeAssignmentOperators: true
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: true
SpaceBeforeInheritanceColon: true
SpaceBeforeParens: ControlStatements
SpaceBeforeRangeBasedForLoopColon: true
SpaceInEmptyBlock: false
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false
SpacesInConditionalStatement: false
SpacesInContainerLiterals: true
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
SpacesInSquareBrackets: false
SpaceBeforeSquareBrackets: false
Standard: Latest
StatementMacros:
- Q_UNUSED
- QT_REQUIRE_VERSION
TabWidth: 8
UseCRLF: false
UseTab: Never
...

14
source/Core/BSP/BSP.h
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@@ -1,10 +1,10 @@
#include <stdint.h>
#include <stdbool.h>
#include "BSP_Flash.h" #include "BSP_Flash.h"
#include "BSP_Power.h" #include "BSP_Power.h"
#include "BSP_QC.h" #include "BSP_QC.h"
#include "Defines.h" #include "Defines.h"
#include "Model_Config.h" #include "Model_Config.h"
#include <stdbool.h>
#include <stdint.h>
/* /*
* BSP.h -- Board Support * BSP.h -- Board Support
* *
@@ -59,16 +59,16 @@ void reboot();
// If the user has programmed in a bootup logo, draw it to the screen from flash // If the user has programmed in a bootup logo, draw it to the screen from flash
// Returns 1 if the logo was printed so that the unit waits for the timeout or button // Returns 1 if the logo was printed so that the unit waits for the timeout or button
uint8_t showBootLogoIfavailable(); uint8_t showBootLogoIfavailable();
//delay wrapper for delay using the hardware timer (used before RTOS) // delay wrapper for delay using the hardware timer (used before RTOS)
void delay_ms(uint16_t count) ; void delay_ms(uint16_t count);
//Used to allow knowledge of if usb_pd is being used // Used to allow knowledge of if usb_pd is being used
uint8_t usb_pd_detect(); uint8_t usb_pd_detect();
bool getHallSensorFitted(); bool getHallSensorFitted();
// If the iron has a hall effect sensor in the handle, return an signed count of the reading // If the iron has a hall effect sensor in the handle, return an signed count of the reading
// If the sensor is single polarity (or polarity insensitive) just return 0..32768 // If the sensor is single polarity (or polarity insensitive) just return 0..32768
int16_t getRawHallEffect(); int16_t getRawHallEffect();
//Returns true if power is from dumb "DC" input rather than "smart" QC or PD // Returns true if power is from dumb "DC" input rather than "smart" QC or PD
bool getIsPoweredByDCIN(); bool getIsPoweredByDCIN();
#ifdef __cplusplus #ifdef __cplusplus

2
source/Core/BSP/BSP_Flash.h
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@@ -16,7 +16,7 @@ extern "C" {
* Should allow reading and writing to the flash * Should allow reading and writing to the flash
*/ */
//Erase the flash, then save the buffer. Returns 1 if worked // Erase the flash, then save the buffer. Returns 1 if worked
uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length); uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length);
void flash_read_buffer(uint8_t *buffer, const uint16_t length); void flash_read_buffer(uint8_t *buffer, const uint16_t length);

2
source/Core/BSP/BSP_PD.h
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@@ -12,5 +12,5 @@
* An array of all of the desired voltages & minimum currents in preferred order * An array of all of the desired voltages & minimum currents in preferred order
*/ */
extern const uint16_t USB_PD_Desired_Levels[]; extern const uint16_t USB_PD_Desired_Levels[];
extern const uint8_t USB_PD_Desired_Levels_Len; extern const uint8_t USB_PD_Desired_Levels_Len;
#endif /* USER_BSP_PD_H_ */ #endif /* USER_BSP_PD_H_ */

1
source/Core/BSP/BSP_Power.h
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@@ -12,7 +12,6 @@
extern "C" { extern "C" {
#endif #endif
// Called periodically in the movement handling thread // Called periodically in the movement handling thread
// Can be used to check any details for the power system // Can be used to check any details for the power system
void power_check(); void power_check();

13
source/Core/BSP/Defines.h
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@@ -8,14 +8,11 @@
#ifndef BSP_DEFINES_H_ #ifndef BSP_DEFINES_H_
#define BSP_DEFINES_H_ #define BSP_DEFINES_H_
enum Orientation { ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3 };
enum Orientation { // It is assumed that all hardware implements an 8Hz update period at this time
ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3 #define PID_TIM_HZ (8)
};
//It is assumed that all hardware implements an 8Hz update period at this time
#define PID_TIM_HZ (8)
#define TICKS_SECOND configTICK_RATE_HZ #define TICKS_SECOND configTICK_RATE_HZ
#define TICKS_MIN (60*TICKS_SECOND) #define TICKS_MIN (60 * TICKS_SECOND)
#define TICKS_100MS (TICKS_SECOND/10) #define TICKS_100MS (TICKS_SECOND / 10)
#endif /* BSP_DEFINES_H_ */ #endif /* BSP_DEFINES_H_ */

519
source/Core/BSP/Miniware/BSP.cpp
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@@ -1,159 +1,156 @@
//BSP mapping functions // BSP mapping functions
#include <IRQ.h>
#include "BSP.h" #include "BSP.h"
#include "I2C_Wrapper.hpp"
#include "Model_Config.h"
#include "Pins.h"
#include "Setup.h" #include "Setup.h"
#include "history.hpp" #include "history.hpp"
#include "Pins.h"
#include "main.hpp" #include "main.hpp"
#include "history.hpp" #include <IRQ.h>
#include "Model_Config.h"
#include "I2C_Wrapper.hpp"
volatile uint16_t PWMSafetyTimer = 0; volatile uint16_t PWMSafetyTimer = 0;
volatile uint8_t pendingPWM = 0; volatile uint8_t pendingPWM = 0;
const uint16_t powerPWM = 255; const uint16_t powerPWM = 255;
static const uint8_t holdoffTicks = 14; // delay of 8 ms static const uint8_t holdoffTicks = 14; // delay of 8 ms
static const uint8_t tempMeasureTicks = 14; static const uint8_t tempMeasureTicks = 14;
uint16_t totalPWM; //htim2.Init.Period, the full PWM cycle uint16_t totalPWM; // htim2.Init.Period, the full PWM cycle
static bool fastPWM; static bool fastPWM;
//2 second filter (ADC is PID_TIM_HZ Hz) // 2 second filter (ADC is PID_TIM_HZ Hz)
history<uint16_t, PID_TIM_HZ> rawTempFilter = { { 0 }, 0, 0 }; history<uint16_t, PID_TIM_HZ> rawTempFilter = {{0}, 0, 0};
void resetWatchdog() { void resetWatchdog() { HAL_IWDG_Refresh(&hiwdg); }
HAL_IWDG_Refresh(&hiwdg);
}
#ifdef TEMP_NTC #ifdef TEMP_NTC
//Lookup table for the NTC // Lookup table for the NTC
//Stored as ADCReading,Temp in degC // Stored as ADCReading,Temp in degC
static const uint16_t NTCHandleLookup[] = { static const uint16_t NTCHandleLookup[] = {
//ADC Reading , Temp in C // ADC Reading , Temp in C
29189, 0, // 29189, 0, //
29014, 1, // 29014, 1, //
28832, 2, // 28832, 2, //
28644, 3, // 28644, 3, //
28450, 4, // 28450, 4, //
28249, 5, // 28249, 5, //
28042, 6, // 28042, 6, //
27828, 7, // 27828, 7, //
27607, 8, // 27607, 8, //
27380, 9, // 27380, 9, //
27146, 10, // 27146, 10, //
26906, 11, // 26906, 11, //
26660, 12, // 26660, 12, //
26407, 13, // 26407, 13, //
26147, 14, // 26147, 14, //
25882, 15, // 25882, 15, //
25610, 16, // 25610, 16, //
25332, 17, // 25332, 17, //
25049, 18, // 25049, 18, //
24759, 19, // 24759, 19, //
24465, 20, // 24465, 20, //
24164, 21, // 24164, 21, //
23859, 22, // 23859, 22, //
23549, 23, // 23549, 23, //
23234, 24, // 23234, 24, //
22915, 25, // 22915, 25, //
22591, 26, // 22591, 26, //
22264, 27, // 22264, 27, //
21933, 28, // 21933, 28, //
21599, 29, // 21599, 29, //
21261, 30, // 21261, 30, //
20921, 31, // 20921, 31, //
20579, 32, // 20579, 32, //
20234, 33, // 20234, 33, //
19888, 34, // 19888, 34, //
19541, 35, // 19541, 35, //
19192, 36, // 19192, 36, //
18843, 37, // 18843, 37, //
18493, 38, // 18493, 38, //
18143, 39, // 18143, 39, //
17793, 40, // 17793, 40, //
17444, 41, // 17444, 41, //
17096, 42, // 17096, 42, //
16750, 43, // 16750, 43, //
16404, 44, // 16404, 44, //
16061, 45, // 16061, 45, //
// 15719, 46, // // 15719, 46, //
// 15380, 47, // // 15380, 47, //
// 15044, 48, // // 15044, 48, //
// 14710, 49, // // 14710, 49, //
// 14380, 50, // // 14380, 50, //
// 14053, 51, // // 14053, 51, //
// 13729, 52, // // 13729, 52, //
// 13410, 53, // // 13410, 53, //
// 13094, 54, // // 13094, 54, //
// 12782, 55, // // 12782, 55, //
// 12475, 56, // // 12475, 56, //
// 12172, 57, // // 12172, 57, //
// 11874, 58, // // 11874, 58, //
// 11580, 59, // // 11580, 59, //
// 11292, 60, // // 11292, 60, //
}; };
#endif #endif
uint16_t getHandleTemperature() { uint16_t getHandleTemperature() {
#ifdef TEMP_NTC #ifdef TEMP_NTC
//TS80P uses 100k NTC resistors instead // TS80P uses 100k NTC resistors instead
//NTCG104EF104FT1X from TDK // NTCG104EF104FT1X from TDK
//For now not doing interpolation // For now not doing interpolation
int32_t result = getADC(0); int32_t result = getADC(0);
for (uint32_t i = 0; i < (sizeof(NTCHandleLookup) / (2 * sizeof(uint16_t))); i++) { for (uint32_t i = 0; i < (sizeof(NTCHandleLookup) / (2 * sizeof(uint16_t))); i++) {
if (result > NTCHandleLookup[(i * 2) + 0]) { if (result > NTCHandleLookup[(i * 2) + 0]) {
return NTCHandleLookup[(i * 2) + 1] * 10; return NTCHandleLookup[(i * 2) + 1] * 10;
} }
} }
return 45 * 10; return 45 * 10;
#endif #endif
#ifdef TEMP_TMP36 #ifdef TEMP_TMP36
// We return the current handle temperature in X10 C // We return the current handle temperature in X10 C
// TMP36 in handle, 0.5V offset and then 10mV per deg C (0.75V @ 25C for // TMP36 in handle, 0.5V offset and then 10mV per deg C (0.75V @ 25C for
// example) STM32 = 4096 count @ 3.3V input -> But We oversample by 32/(2^2) = // example) STM32 = 4096 count @ 3.3V input -> But We oversample by 32/(2^2) =
// 8 times oversampling Therefore 32768 is the 3.3V input, so 0.1007080078125 // 8 times oversampling Therefore 32768 is the 3.3V input, so 0.1007080078125
// mV per count So we need to subtract an offset of 0.5V to center on 0C // mV per count So we need to subtract an offset of 0.5V to center on 0C
// (4964.8 counts) // (4964.8 counts)
// //
int32_t result = getADC(0); int32_t result = getADC(0);
result -= 4965; // remove 0.5V offset result -= 4965; // remove 0.5V offset
// 10mV per C // 10mV per C
// 99.29 counts per Deg C above 0C. Tends to read a tad over across all of my sample units // 99.29 counts per Deg C above 0C. Tends to read a tad over across all of my sample units
result *= 100; result *= 100;
result /= 994; result /= 994;
return result; return result;
#endif #endif
} }
uint16_t getTipInstantTemperature() { uint16_t getTipInstantTemperature() {
uint16_t sum = 0; // 12 bit readings * 8 -> 15 bits uint16_t sum = 0; // 12 bit readings * 8 -> 15 bits
uint16_t readings[8]; uint16_t readings[8];
//Looking to reject the highest outlier readings. // Looking to reject the highest outlier readings.
//As on some hardware these samples can run into the op-amp recovery time // As on some hardware these samples can run into the op-amp recovery time
//Once this time is up the signal stabilises quickly, so no need to reject minimums // Once this time is up the signal stabilises quickly, so no need to reject minimums
readings[0] = hadc1.Instance->JDR1; readings[0] = hadc1.Instance->JDR1;
readings[1] = hadc1.Instance->JDR2; readings[1] = hadc1.Instance->JDR2;
readings[2] = hadc1.Instance->JDR3; readings[2] = hadc1.Instance->JDR3;
readings[3] = hadc1.Instance->JDR4; readings[3] = hadc1.Instance->JDR4;
readings[4] = hadc2.Instance->JDR1; readings[4] = hadc2.Instance->JDR1;
readings[5] = hadc2.Instance->JDR2; readings[5] = hadc2.Instance->JDR2;
readings[6] = hadc2.Instance->JDR3; readings[6] = hadc2.Instance->JDR3;
readings[7] = hadc2.Instance->JDR4; readings[7] = hadc2.Instance->JDR4;
for (int i = 0; i < 8; i++) { for (int i = 0; i < 8; i++) {
sum += readings[i]; sum += readings[i];
} }
return sum; // 8x over sample return sum; // 8x over sample
} }
uint16_t getTipRawTemp(uint8_t refresh) { uint16_t getTipRawTemp(uint8_t refresh) {
if (refresh) { if (refresh) {
uint16_t lastSample = getTipInstantTemperature(); uint16_t lastSample = getTipInstantTemperature();
rawTempFilter.update(lastSample); rawTempFilter.update(lastSample);
return lastSample; return lastSample;
} else { } else {
return rawTempFilter.average(); return rawTempFilter.average();
} }
} }
uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) { uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) {
@@ -167,187 +164,177 @@ uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) {
#define BATTFILTERDEPTH 8 #define BATTFILTERDEPTH 8
#endif #endif
static uint8_t preFillneeded = 10; static uint8_t preFillneeded = 10;
static uint32_t samples[BATTFILTERDEPTH]; static uint32_t samples[BATTFILTERDEPTH];
static uint8_t index = 0; static uint8_t index = 0;
if (preFillneeded) { if (preFillneeded) {
for (uint8_t i = 0; i < BATTFILTERDEPTH; i++) for (uint8_t i = 0; i < BATTFILTERDEPTH; i++)
samples[i] = getADC(1); samples[i] = getADC(1);
preFillneeded--; preFillneeded--;
} }
if (sample) { if (sample) {
samples[index] = getADC(1); samples[index] = getADC(1);
index = (index + 1) % BATTFILTERDEPTH; index = (index + 1) % BATTFILTERDEPTH;
} }
uint32_t sum = 0; uint32_t sum = 0;
for (uint8_t i = 0; i < BATTFILTERDEPTH; i++) for (uint8_t i = 0; i < BATTFILTERDEPTH; i++)
sum += samples[i]; sum += samples[i];
sum /= BATTFILTERDEPTH; sum /= BATTFILTERDEPTH;
if (divisor == 0) { if (divisor == 0) {
divisor = 1; divisor = 1;
} }
return sum * 4 / divisor; return sum * 4 / divisor;
} }
void setTipPWM(uint8_t pulse) { void setTipPWM(uint8_t pulse) {
PWMSafetyTimer = 10; // This is decremented in the handler for PWM so that the tip pwm is PWMSafetyTimer = 10; // This is decremented in the handler for PWM so that the tip pwm is
// disabled if the PID task is not scheduled often enough. // disabled if the PID task is not scheduled often enough.
pendingPWM = pulse; pendingPWM = pulse;
} }
static void switchToFastPWM(void) { static void switchToFastPWM(void) {
fastPWM = true; fastPWM = true;
totalPWM = powerPWM + tempMeasureTicks * 2 + holdoffTicks; totalPWM = powerPWM + tempMeasureTicks * 2 + holdoffTicks;
htim2.Instance->ARR = totalPWM; htim2.Instance->ARR = totalPWM;
// ~3.5 Hz rate // ~3.5 Hz rate
htim2.Instance->CCR1 = powerPWM + holdoffTicks * 2; htim2.Instance->CCR1 = powerPWM + holdoffTicks * 2;
// 2 MHz timer clock/2000 = 1 kHz tick rate // 2 MHz timer clock/2000 = 1 kHz tick rate
htim2.Instance->PSC = 2000; htim2.Instance->PSC = 2000;
} }
static void switchToSlowPWM(void) { static void switchToSlowPWM(void) {
fastPWM = false; fastPWM = false;
totalPWM = powerPWM + tempMeasureTicks + holdoffTicks; totalPWM = powerPWM + tempMeasureTicks + holdoffTicks;
htim2.Instance->ARR = totalPWM; htim2.Instance->ARR = totalPWM;
// ~1.84 Hz rate // ~1.84 Hz rate
htim2.Instance->CCR1 = powerPWM + holdoffTicks; htim2.Instance->CCR1 = powerPWM + holdoffTicks;
// 2 MHz timer clock/4000 = 500 Hz tick rate // 2 MHz timer clock/4000 = 500 Hz tick rate
htim2.Instance->PSC = 4000; htim2.Instance->PSC = 4000;
} }
bool tryBetterPWM(uint8_t pwm) { bool tryBetterPWM(uint8_t pwm) {
if (fastPWM && pwm == powerPWM) { if (fastPWM && pwm == powerPWM) {
// maximum power for fast PWM reached, need to go slower to get more // maximum power for fast PWM reached, need to go slower to get more
switchToSlowPWM(); switchToSlowPWM();
return true; return true;
} else if (!fastPWM && pwm < 230) { } else if (!fastPWM && pwm < 230) {
// 254 in fast PWM mode gives the same power as 239 in slow // 254 in fast PWM mode gives the same power as 239 in slow
// allow for some reasonable hysteresis by switching only when it goes // allow for some reasonable hysteresis by switching only when it goes
// below 230 (equivalent to 245 in fast mode) // below 230 (equivalent to 245 in fast mode)
switchToFastPWM(); switchToFastPWM();
return true; return true;
} }
return false; return false;
} }
// These are called by the HAL after the corresponding events from the system // These are called by the HAL after the corresponding events from the system
// timers. // timers.
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
// Period has elapsed // Period has elapsed
if (htim->Instance == TIM2) { if (htim->Instance == TIM2) {
// we want to turn on the output again // we want to turn on the output again
PWMSafetyTimer--; PWMSafetyTimer--;
// We decrement this safety value so that lockups in the // We decrement this safety value so that lockups in the
// scheduler will not cause the PWM to become locked in an // scheduler will not cause the PWM to become locked in an
// active driving state. // active driving state.
// While we could assume this could never happen, its a small price for // While we could assume this could never happen, its a small price for
// increased safety // increased safety
htim2.Instance->CCR4 = pendingPWM; htim2.Instance->CCR4 = pendingPWM;
if (htim2.Instance->CCR4 && PWMSafetyTimer) { if (htim2.Instance->CCR4 && PWMSafetyTimer) {
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1); HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1);
} else { } else {
HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1);
} }
} else if (htim->Instance == TIM1) { } else if (htim->Instance == TIM1) {
// STM uses this for internal functions as a counter for timeouts // STM uses this for internal functions as a counter for timeouts
HAL_IncTick(); HAL_IncTick();
} }
} }
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) {
// This was a when the PWM for the output has timed out // This was a when the PWM for the output has timed out
if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) { if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) {
HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1);
} }
} }
void unstick_I2C() { void unstick_I2C() {
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
int timeout = 100; int timeout = 100;
int timeout_cnt = 0; int timeout_cnt = 0;
// 1. Clear PE bit. // 1. Clear PE bit.
hi2c1.Instance->CR1 &= ~(0x0001); hi2c1.Instance->CR1 &= ~(0x0001);
/**I2C1 GPIO Configuration /**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL PB6 ------> I2C1_SCL
PB7 ------> I2C1_SDA PB7 ------> I2C1_SDA
*/ */
// 2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR). // 2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Pin = SCL_Pin; GPIO_InitStruct.Pin = SCL_Pin;
HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct);
HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
GPIO_InitStruct.Pin = SDA_Pin; GPIO_InitStruct.Pin = SDA_Pin;
HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct);
HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET);
while (GPIO_PIN_SET != HAL_GPIO_ReadPin(SDA_GPIO_Port, SDA_Pin)) { while (GPIO_PIN_SET != HAL_GPIO_ReadPin(SDA_GPIO_Port, SDA_Pin)) {
//Move clock to release I2C // Move clock to release I2C
HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_RESET);
asm("nop"); asm("nop");
asm("nop"); asm("nop");
asm("nop"); asm("nop");
asm("nop"); asm("nop");
HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
timeout_cnt++; timeout_cnt++;
if (timeout_cnt > timeout) if (timeout_cnt > timeout)
return; return;
} }
// 12. Configure the SCL and SDA I/Os as Alternate function Open-Drain. // 12. Configure the SCL and SDA I/Os as Alternate function Open-Drain.
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Pin = SCL_Pin; GPIO_InitStruct.Pin = SCL_Pin;
HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Pin = SDA_Pin; GPIO_InitStruct.Pin = SDA_Pin;
HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct);
HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET);
// 13. Set SWRST bit in I2Cx_CR1 register. // 13. Set SWRST bit in I2Cx_CR1 register.
hi2c1.Instance->CR1 |= 0x8000; hi2c1.Instance->CR1 |= 0x8000;
asm("nop"); asm("nop");
// 14. Clear SWRST bit in I2Cx_CR1 register. // 14. Clear SWRST bit in I2Cx_CR1 register.
hi2c1.Instance->CR1 &= ~0x8000; hi2c1.Instance->CR1 &= ~0x8000;
asm("nop"); asm("nop");
// 15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register // 15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register
hi2c1.Instance->CR1 |= 0x0001; hi2c1.Instance->CR1 |= 0x0001;
// Call initialization function. // Call initialization function.
HAL_I2C_Init(&hi2c1); HAL_I2C_Init(&hi2c1);
} }
uint8_t getButtonA() { uint8_t getButtonA() { return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ? 1 : 0; }
return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ? 1 : 0; uint8_t getButtonB() { return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ? 1 : 0; }
}
uint8_t getButtonB() {
return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ? 1 : 0;
}
void BSPInit(void) { void BSPInit(void) { switchToFastPWM(); }
switchToFastPWM();
}
void reboot() { void reboot() { NVIC_SystemReset(); }
NVIC_SystemReset();
}
void delay_ms(uint16_t count) { void delay_ms(uint16_t count) { HAL_Delay(count); }
HAL_Delay(count);
}

10
source/Core/BSP/Miniware/BSP_PD.c
View File

@@ -12,11 +12,11 @@
* An array of all of the desired voltages & minimum currents in preferred order * An array of all of the desired voltages & minimum currents in preferred order
*/ */
const uint16_t USB_PD_Desired_Levels[] = { const uint16_t USB_PD_Desired_Levels[] = {
//mV desired input, mA minimum required current // mV desired input, mA minimum required current
12000, 2400, //12V @ 2.4A 12000, 2400, // 12V @ 2.4A
9000, 2000, //9V @ 2A 9000, 2000, // 9V @ 2A
5000, 100, //5V @ whatever 5000, 100, // 5V @ whatever
}; };
const uint8_t USB_PD_Desired_Levels_Len = 3; const uint8_t USB_PD_Desired_Levels_Len = 3;
#endif #endif

63
source/Core/BSP/Miniware/FreeRTOSConfig.h
View File

@@ -92,27 +92,27 @@
extern uint32_t SystemCoreClock; extern uint32_t SystemCoreClock;
#endif #endif
#define configUSE_PREEMPTION 1 #define configUSE_PREEMPTION 1
#define configSUPPORT_STATIC_ALLOCATION 1 #define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 0 #define configSUPPORT_DYNAMIC_ALLOCATION 0
#define configUSE_IDLE_HOOK 1 #define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0 #define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock ) #define configCPU_CLOCK_HZ (SystemCoreClock)
#define configTICK_RATE_HZ ((TickType_t)1000) #define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES ( 6 ) #define configMAX_PRIORITIES (6)
#define configMINIMAL_STACK_SIZE ((uint16_t)256) #define configMINIMAL_STACK_SIZE ((uint16_t)256)
#define configTOTAL_HEAP_SIZE ((size_t)1024*14) /*Currently use about 9000*/ #define configTOTAL_HEAP_SIZE ((size_t)1024 * 14) /*Currently use about 9000*/
#define configMAX_TASK_NAME_LEN ( 32 ) #define configMAX_TASK_NAME_LEN (32)
#define configUSE_16_BIT_TICKS 0 #define configUSE_16_BIT_TICKS 0
#define configUSE_MUTEXES 1 #define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8 #define configQUEUE_REGISTRY_SIZE 8
#define configUSE_TIMERS 0 #define configUSE_TIMERS 0
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configCHECK_FOR_STACK_OVERFLOW 2 /*Bump this to 2 during development and bug hunting*/ #define configCHECK_FOR_STACK_OVERFLOW 2 /*Bump this to 2 during development and bug hunting*/
/* Co-routine definitions. */ /* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0 #define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) #define configMAX_CO_ROUTINE_PRIORITIES (2)
/* Set the following definitions to 1 to include the API function, or zero /* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */ to exclude the API function. */
@@ -128,15 +128,15 @@ extern uint32_t SystemCoreClock;
/* Cortex-M specific definitions. */ /* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS #define configPRIO_BITS __NVIC_PRIO_BITS
#else #else
#define configPRIO_BITS 4 #define configPRIO_BITS 4
#endif #endif
/* The lowest interrupt priority that can be used in a call to a "set priority" /* The lowest interrupt priority that can be used in a call to a "set priority"
function. */ function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
/* The highest interrupt priority that can be used by any interrupt service /* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
@@ -146,15 +146,20 @@ extern uint32_t SystemCoreClock;
/* Interrupt priorities used by the kernel port layer itself. These are generic /* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */ to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) #define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) #define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* Normal assert() semantics without relying on the provision of an assert.h /* Normal assert() semantics without relying on the provision of an assert.h
header file. */ header file. */
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} #define configASSERT(x) \
if ((x) == 0) { \
taskDISABLE_INTERRUPTS(); \
for (;;) \
; \
}
/* USER CODE END 1 */ /* USER CODE END 1 */
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
@@ -163,9 +168,9 @@ extern uint32_t SystemCoreClock;
#define xPortPendSVHandler PendSV_Handler #define xPortPendSVHandler PendSV_Handler
#if configUSE_TIMERS #if configUSE_TIMERS
#define configTIMER_TASK_PRIORITY 2 #define configTIMER_TASK_PRIORITY 2
#define configTIMER_QUEUE_LENGTH 8 #define configTIMER_QUEUE_LENGTH 8
#define configTIMER_TASK_STACK_DEPTH (512/4) #define configTIMER_TASK_STACK_DEPTH (512 / 4)
#endif #endif
#endif /* FREERTOS_CONFIG_H */ #endif /* FREERTOS_CONFIG_H */

124
source/Core/BSP/Miniware/I2C_Wrapper.cpp
View File

@@ -11,97 +11,81 @@ SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr;
StaticSemaphore_t FRToSI2C::xSemaphoreBuffer; StaticSemaphore_t FRToSI2C::xSemaphoreBuffer;
void FRToSI2C::CpltCallback() { void FRToSI2C::CpltCallback() {
hi2c1.State = HAL_I2C_STATE_READY; // Force state reset (even if tx error) hi2c1.State = HAL_I2C_STATE_READY; // Force state reset (even if tx error)
if (I2CSemaphore) { if (I2CSemaphore) {
xSemaphoreGiveFromISR(I2CSemaphore, NULL); xSemaphoreGiveFromISR(I2CSemaphore, NULL);
} }
} }
bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t MemAddress, bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size) {
uint8_t *pData, uint16_t Size) {
if (!lock()) if (!lock())
return false; return false;
if (HAL_I2C_Mem_Read(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT, if (HAL_I2C_Mem_Read(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT, pData, Size, 500) != HAL_OK) {
pData, Size, 500) != HAL_OK) {
I2C_Unstick(); I2C_Unstick();
unlock(); unlock();
return false; return false;
} }
unlock(); unlock();
return true; return true;
}
bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) {
return Mem_Write(address, reg, &data, 1);
} }
bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }
uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) { uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) {
uint8_t tx_data[1]; uint8_t tx_data[1];
Mem_Read(add, reg, tx_data, 1); Mem_Read(add, reg, tx_data, 1);
return tx_data[0]; return tx_data[0];
} }
bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size) {
uint8_t *pData, uint16_t Size) {
if (!lock()) if (!lock())
return false; return false;
if (HAL_I2C_Mem_Write(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT, if (HAL_I2C_Mem_Write(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT, pData, Size, 500) != HAL_OK) {
pData, Size, 500) != HAL_OK) {
I2C_Unstick(); I2C_Unstick();
unlock(); unlock();
return false; return false;
} }
unlock(); unlock();
return true; return true;
} }
bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) { bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
if (!lock()) if (!lock())
return false; return false;
if (HAL_I2C_Master_Transmit_DMA(&hi2c1, DevAddress, pData, Size) if (HAL_I2C_Master_Transmit_DMA(&hi2c1, DevAddress, pData, Size) != HAL_OK) {
!= HAL_OK) { I2C_Unstick();
I2C_Unstick(); unlock();
unlock(); return false;
return false; }
} return true;
return true;
} }
bool FRToSI2C::probe(uint16_t DevAddress) { bool FRToSI2C::probe(uint16_t DevAddress) {
if (!lock()) if (!lock())
return false; return false;
uint8_t buffer[1]; uint8_t buffer[1];
bool worked = HAL_I2C_Mem_Read(&hi2c1, DevAddress, 0x0F, bool worked = HAL_I2C_Mem_Read(&hi2c1, DevAddress, 0x0F, I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000) == HAL_OK;
I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000) == HAL_OK; unlock();
unlock(); return worked;
return worked;
} }
void FRToSI2C::I2C_Unstick() { void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
unstick_I2C();
}
void FRToSI2C::unlock() { void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); }
xSemaphoreGive(I2CSemaphore);
}
bool FRToSI2C::lock() { bool FRToSI2C::lock() { return xSemaphoreTake(I2CSemaphore, (TickType_t)50) == pdTRUE; }
return xSemaphoreTake(I2CSemaphore, (TickType_t)50) == pdTRUE;
}
bool FRToSI2C::writeRegistersBulk(const uint8_t address, bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) {
const I2C_REG *registers, const uint8_t registersLength) { for (int index = 0; index < registersLength; index++) {
for (int index = 0; index < registersLength; index++) { if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) {
if (!I2C_RegisterWrite(address, registers[index].reg, return false;
registers[index].val)) { }
return false; if (registers[index].pause_ms)
} delay_ms(registers[index].pause_ms);
if (registers[index].pause_ms) }
delay_ms(registers[index].pause_ms); return true;
}
return true;
} }

45
source/Core/BSP/Miniware/IRQ.cpp
View File

@@ -13,37 +13,22 @@
* runs again * runs again
*/ */
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) {
BaseType_t xHigherPriorityTaskWoken = pdFALSE; BaseType_t xHigherPriorityTaskWoken = pdFALSE;
if (hadc == &hadc1) { if (hadc == &hadc1) {
if (pidTaskNotification) { if (pidTaskNotification) {
vTaskNotifyGiveFromISR(pidTaskNotification, vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken);
&xHigherPriorityTaskWoken); portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken); }
} }
}
}
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
FRToSI2C::CpltCallback();
}
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
FRToSI2C::CpltCallback();
}
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
FRToSI2C::CpltCallback();
}
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c __unused) {
FRToSI2C::CpltCallback();
}
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
FRToSI2C::CpltCallback();
}
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
FRToSI2C::CpltCallback();
} }
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
(void) GPIO_Pin; (void)GPIO_Pin;
InterruptHandler::irqCallback(); InterruptHandler::irqCallback();
} }

2
source/Core/BSP/Miniware/IRQ.h
View File

@@ -9,10 +9,10 @@
#define BSP_MINIWARE_IRQ_H_ #define BSP_MINIWARE_IRQ_H_
#include "BSP.h" #include "BSP.h"
#include "stm32f1xx_hal.h"
#include "I2C_Wrapper.hpp" #include "I2C_Wrapper.hpp"
#include "Setup.h" #include "Setup.h"
#include "main.hpp" #include "main.hpp"
#include "stm32f1xx_hal.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

4
source/Core/BSP/Miniware/Model_Config.h
View File

@@ -11,9 +11,9 @@
* Lookup for mapping features <-> Models * Lookup for mapping features <-> Models
*/ */
#if defined(MODEL_TS100) + defined(MODEL_TS80)+defined(MODEL_TS80P) > 1 #if defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) > 1
#error "Multiple models defined!" #error "Multiple models defined!"
#elif defined(MODEL_TS100) + defined(MODEL_TS80)+ defined(MODEL_TS80P) == 0 #elif defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) == 0
#error "No model defined!" #error "No model defined!"
#endif #endif

178
source/Core/BSP/Miniware/Pins.h
View File

@@ -11,115 +11,115 @@
#ifdef MODEL_TS100 #ifdef MODEL_TS100
#define KEY_B_Pin GPIO_PIN_6 #define KEY_B_Pin GPIO_PIN_6
#define KEY_B_GPIO_Port GPIOA #define KEY_B_GPIO_Port GPIOA
#define TMP36_INPUT_Pin GPIO_PIN_7 #define TMP36_INPUT_Pin GPIO_PIN_7
#define TMP36_INPUT_GPIO_Port GPIOA #define TMP36_INPUT_GPIO_Port GPIOA
#define TMP36_ADC1_CHANNEL ADC_CHANNEL_7 #define TMP36_ADC1_CHANNEL ADC_CHANNEL_7
#define TMP36_ADC2_CHANNEL ADC_CHANNEL_7 #define TMP36_ADC2_CHANNEL ADC_CHANNEL_7
#define TIP_TEMP_Pin GPIO_PIN_0 #define TIP_TEMP_Pin GPIO_PIN_0
#define TIP_TEMP_GPIO_Port GPIOB #define TIP_TEMP_GPIO_Port GPIOB
#define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_8 #define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_8
#define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_8 #define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_8
#define VIN_Pin GPIO_PIN_1 #define VIN_Pin GPIO_PIN_1
#define VIN_GPIO_Port GPIOB #define VIN_GPIO_Port GPIOB
#define VIN_ADC1_CHANNEL ADC_CHANNEL_9 #define VIN_ADC1_CHANNEL ADC_CHANNEL_9
#define VIN_ADC2_CHANNEL ADC_CHANNEL_9 #define VIN_ADC2_CHANNEL ADC_CHANNEL_9
#define OLED_RESET_Pin GPIO_PIN_8 #define OLED_RESET_Pin GPIO_PIN_8
#define OLED_RESET_GPIO_Port GPIOA #define OLED_RESET_GPIO_Port GPIOA
#define KEY_A_Pin GPIO_PIN_9 #define KEY_A_Pin GPIO_PIN_9
#define KEY_A_GPIO_Port GPIOA #define KEY_A_GPIO_Port GPIOA
#define INT_Orientation_Pin GPIO_PIN_3 #define INT_Orientation_Pin GPIO_PIN_3
#define INT_Orientation_GPIO_Port GPIOB #define INT_Orientation_GPIO_Port GPIOB
#define PWM_Out_Pin GPIO_PIN_4 #define PWM_Out_Pin GPIO_PIN_4
#define PWM_Out_GPIO_Port GPIOB #define PWM_Out_GPIO_Port GPIOB
#define PWM_Out_CHANNEL TIM_CHANNEL_1 #define PWM_Out_CHANNEL TIM_CHANNEL_1
#define PWM_Out_CCR #define PWM_Out_CCR
#define INT_Movement_Pin GPIO_PIN_5 #define INT_Movement_Pin GPIO_PIN_5
#define INT_Movement_GPIO_Port GPIOB #define INT_Movement_GPIO_Port GPIOB
#define SCL_Pin GPIO_PIN_6 #define SCL_Pin GPIO_PIN_6
#define SCL_GPIO_Port GPIOB #define SCL_GPIO_Port GPIOB
#define SDA_Pin GPIO_PIN_7 #define SDA_Pin GPIO_PIN_7
#define SDA_GPIO_Port GPIOB #define SDA_GPIO_Port GPIOB
#endif #endif
#ifdef MODEL_TS80 #ifdef MODEL_TS80
// TS80 pin map // TS80 pin map
#define KEY_B_Pin GPIO_PIN_0 #define KEY_B_Pin GPIO_PIN_0
#define KEY_B_GPIO_Port GPIOB #define KEY_B_GPIO_Port GPIOB
#define TMP36_INPUT_Pin GPIO_PIN_4 #define TMP36_INPUT_Pin GPIO_PIN_4
#define TMP36_INPUT_GPIO_Port GPIOA #define TMP36_INPUT_GPIO_Port GPIOA
#define TMP36_ADC1_CHANNEL ADC_CHANNEL_4 #define TMP36_ADC1_CHANNEL ADC_CHANNEL_4
#define TMP36_ADC2_CHANNEL ADC_CHANNEL_4 #define TMP36_ADC2_CHANNEL ADC_CHANNEL_4
#define TIP_TEMP_Pin GPIO_PIN_3 #define TIP_TEMP_Pin GPIO_PIN_3
#define TIP_TEMP_GPIO_Port GPIOA #define TIP_TEMP_GPIO_Port GPIOA
#define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_3 #define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_3
#define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_3 #define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_3
#define VIN_Pin GPIO_PIN_2 #define VIN_Pin GPIO_PIN_2
#define VIN_GPIO_Port GPIOA #define VIN_GPIO_Port GPIOA
#define VIN_ADC1_CHANNEL ADC_CHANNEL_2 #define VIN_ADC1_CHANNEL ADC_CHANNEL_2
#define VIN_ADC2_CHANNEL ADC_CHANNEL_2 #define VIN_ADC2_CHANNEL ADC_CHANNEL_2
#define OLED_RESET_Pin GPIO_PIN_15 #define OLED_RESET_Pin GPIO_PIN_15
#define OLED_RESET_GPIO_Port GPIOA #define OLED_RESET_GPIO_Port GPIOA
#define KEY_A_Pin GPIO_PIN_1 #define KEY_A_Pin GPIO_PIN_1
#define KEY_A_GPIO_Port GPIOB #define KEY_A_GPIO_Port GPIOB
#define INT_Orientation_Pin GPIO_PIN_4 #define INT_Orientation_Pin GPIO_PIN_4
#define INT_Orientation_GPIO_Port GPIOB #define INT_Orientation_GPIO_Port GPIOB
#define PWM_Out_Pin GPIO_PIN_6 #define PWM_Out_Pin GPIO_PIN_6
#define PWM_Out_GPIO_Port GPIOA #define PWM_Out_GPIO_Port GPIOA
#define PWM_Out_CHANNEL TIM_CHANNEL_1 #define PWM_Out_CHANNEL TIM_CHANNEL_1
#define INT_Movement_Pin GPIO_PIN_5 #define INT_Movement_Pin GPIO_PIN_5
#define INT_Movement_GPIO_Port GPIOB #define INT_Movement_GPIO_Port GPIOB
#define SCL_Pin GPIO_PIN_6 #define SCL_Pin GPIO_PIN_6
#define SCL_GPIO_Port GPIOB #define SCL_GPIO_Port GPIOB
#define SDA_Pin GPIO_PIN_7 #define SDA_Pin GPIO_PIN_7
#define SDA_GPIO_Port GPIOB #define SDA_GPIO_Port GPIOB
#define SCL2_Pin GPIO_PIN_5 #define SCL2_Pin GPIO_PIN_5
#define SCL2_GPIO_Port GPIOA #define SCL2_GPIO_Port GPIOA
#define SDA2_Pin GPIO_PIN_1 #define SDA2_Pin GPIO_PIN_1
#define SDA2_GPIO_Port GPIOA #define SDA2_GPIO_Port GPIOA
#define INT_PD_Pin GPIO_PIN_9 #define INT_PD_Pin GPIO_PIN_9
#define INT_PD_GPIO_Port GPIOA #define INT_PD_GPIO_Port GPIOA
#endif #endif
#ifdef MODEL_TS80P #ifdef MODEL_TS80P
// TS80P pin map // TS80P pin map
#define KEY_B_Pin GPIO_PIN_0 #define KEY_B_Pin GPIO_PIN_0
#define KEY_B_GPIO_Port GPIOB #define KEY_B_GPIO_Port GPIOB
#define TMP36_INPUT_Pin GPIO_PIN_4 #define TMP36_INPUT_Pin GPIO_PIN_4
#define TMP36_INPUT_GPIO_Port GPIOA #define TMP36_INPUT_GPIO_Port GPIOA
#define TMP36_ADC1_CHANNEL ADC_CHANNEL_4 #define TMP36_ADC1_CHANNEL ADC_CHANNEL_4
#define TMP36_ADC2_CHANNEL ADC_CHANNEL_4 #define TMP36_ADC2_CHANNEL ADC_CHANNEL_4
#define TIP_TEMP_Pin GPIO_PIN_3 #define TIP_TEMP_Pin GPIO_PIN_3
#define TIP_TEMP_GPIO_Port GPIOA #define TIP_TEMP_GPIO_Port GPIOA
#define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_3 #define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_3
#define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_3 #define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_3
#define VIN_Pin GPIO_PIN_2 #define VIN_Pin GPIO_PIN_2
#define VIN_GPIO_Port GPIOA #define VIN_GPIO_Port GPIOA
#define VIN_ADC1_CHANNEL ADC_CHANNEL_2 #define VIN_ADC1_CHANNEL ADC_CHANNEL_2
#define VIN_ADC2_CHANNEL ADC_CHANNEL_2 #define VIN_ADC2_CHANNEL ADC_CHANNEL_2
#define OLED_RESET_Pin GPIO_PIN_15 #define OLED_RESET_Pin GPIO_PIN_15
#define OLED_RESET_GPIO_Port GPIOA #define OLED_RESET_GPIO_Port GPIOA
#define KEY_A_Pin GPIO_PIN_1 #define KEY_A_Pin GPIO_PIN_1
#define KEY_A_GPIO_Port GPIOB #define KEY_A_GPIO_Port GPIOB
#define INT_Orientation_Pin GPIO_PIN_4 #define INT_Orientation_Pin GPIO_PIN_4
#define INT_Orientation_GPIO_Port GPIOB #define INT_Orientation_GPIO_Port GPIOB
#define PWM_Out_Pin GPIO_PIN_6 #define PWM_Out_Pin GPIO_PIN_6
#define PWM_Out_GPIO_Port GPIOA #define PWM_Out_GPIO_Port GPIOA
#define PWM_Out_CHANNEL TIM_CHANNEL_1 #define PWM_Out_CHANNEL TIM_CHANNEL_1
#define INT_Movement_Pin GPIO_PIN_5 #define INT_Movement_Pin GPIO_PIN_5
#define INT_Movement_GPIO_Port GPIOB #define INT_Movement_GPIO_Port GPIOB
#define SCL_Pin GPIO_PIN_6 #define SCL_Pin GPIO_PIN_6
#define SCL_GPIO_Port GPIOB #define SCL_GPIO_Port GPIOB
#define SDA_Pin GPIO_PIN_7 #define SDA_Pin GPIO_PIN_7
#define SDA_GPIO_Port GPIOB #define SDA_GPIO_Port GPIOB
#define SCL2_Pin GPIO_PIN_5 #define SCL2_Pin GPIO_PIN_5
#define SCL2_GPIO_Port GPIOA #define SCL2_GPIO_Port GPIOA
#define SDA2_Pin GPIO_PIN_1 #define SDA2_Pin GPIO_PIN_1
#define SDA2_GPIO_Port GPIOA #define SDA2_GPIO_Port GPIOA
#define INT_PD_Pin GPIO_PIN_9 #define INT_PD_Pin GPIO_PIN_9
#define INT_PD_GPIO_Port GPIOA #define INT_PD_GPIO_Port GPIOA
#endif #endif

39
source/Core/BSP/Miniware/Power.cpp
View File

@@ -1,49 +1,48 @@
#include "BSP.h" #include "BSP.h"
#include "BSP_Power.h" #include "BSP_Power.h"
#include "Model_Config.h"
#include "Pins.h"
#include "QC3.h" #include "QC3.h"
#include "Settings.h" #include "Settings.h"
#include "Pins.h"
#include "fusbpd.h" #include "fusbpd.h"
#include "Model_Config.h"
#include "policy_engine.h"
#include "int_n.h" #include "int_n.h"
#include "policy_engine.h"
bool FUSB302_present = false; bool FUSB302_present = false;
void power_check() { void power_check() {
#ifdef POW_PD #ifdef POW_PD
if (FUSB302_present) { if (FUSB302_present) {
//Cant start QC until either PD works or fails // Cant start QC until either PD works or fails
if (PolicyEngine::setupCompleteOrTimedOut() == false) { if (PolicyEngine::setupCompleteOrTimedOut() == false) {
return; return;
} }
if (PolicyEngine::pdHasNegotiated()) { if (PolicyEngine::pdHasNegotiated()) {
return; return;
} }
} }
#endif #endif
#ifdef POW_QC #ifdef POW_QC
QC_resync(); QC_resync();
#endif #endif
} }
uint8_t usb_pd_detect() { uint8_t usb_pd_detect() {
#ifdef POW_PD #ifdef POW_PD
FUSB302_present = fusb302_detect(); FUSB302_present = fusb302_detect();
return FUSB302_present; return FUSB302_present;
#endif #endif
return false; return false;
} }
bool getIsPoweredByDCIN() { bool getIsPoweredByDCIN() {
#ifdef MODEL_TS80 #ifdef MODEL_TS80
return false; return false;
#endif #endif
#ifdef MODEL_TS80P #ifdef MODEL_TS80P
return false; return false;
#endif #endif
#ifdef MODEL_TS100 #ifdef MODEL_TS100
return true; return true;
#endif #endif
} }

86
source/Core/BSP/Miniware/QC_GPIO.cpp
View File

@@ -5,74 +5,72 @@
* Author: Ralim * Author: Ralim
*/ */
#include "BSP.h" #include "BSP.h"
#include "Model_Config.h"
#include "Pins.h" #include "Pins.h"
#include "QC3.h" #include "QC3.h"
#include "Settings.h" #include "Settings.h"
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
#include "Model_Config.h"
#ifdef POW_QC #ifdef POW_QC
void QC_DPlusZero_Six() { void QC_DPlusZero_Six() {
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_RESET); // pull down D+ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_RESET); // pull down D+
} }
void QC_DNegZero_Six() { void QC_DNegZero_Six() {
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET);
} }
void QC_DPlusThree_Three() { void QC_DPlusThree_Three() {
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_SET); // pull up D+ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_SET); // pull up D+
} }
void QC_DNegThree_Three() { void QC_DNegThree_Three() {
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_SET);
} }
void QC_DM_PullDown() { void QC_DM_PullDown() {
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_PULLDOWN; GPIO_InitStruct.Pull = GPIO_PULLDOWN;
GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Pin = GPIO_PIN_11;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
} }
void QC_DM_No_PullDown() { void QC_DM_No_PullDown() {
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Pin = GPIO_PIN_11; GPIO_InitStruct.Pin = GPIO_PIN_11;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
} }
void QC_Init_GPIO() { void QC_Init_GPIO() {
// Setup any GPIO into the right states for QC // Setup any GPIO into the right states for QC
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Pin = GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10; GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
// Turn off output mode on pins that we can // Turn off output mode on pins that we can
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_13; GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_13;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
} }
void QC_Post_Probe_En() { void QC_Post_Probe_En() {
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10; GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
} }
uint8_t QC_DM_PulledDown() { uint8_t QC_DM_PulledDown() { return HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11) == GPIO_PIN_RESET ? 1 : 0; }
return HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11) == GPIO_PIN_RESET ? 1 : 0;
}
#endif #endif
void QC_resync() { void QC_resync() {
#ifdef POW_QC #ifdef POW_QC
seekQC((systemSettings.QCIdealVoltage) ? 120 : 90, seekQC((systemSettings.QCIdealVoltage) ? 120 : 90,
systemSettings.voltageDiv); // Run the QC seek again if we have drifted too much systemSettings.voltageDiv); // Run the QC seek again if we have drifted too much
#endif #endif
} }

666
source/Core/BSP/Miniware/Setup.c
View File

@@ -15,11 +15,11 @@ DMA_HandleTypeDef hdma_i2c1_rx;
DMA_HandleTypeDef hdma_i2c1_tx; DMA_HandleTypeDef hdma_i2c1_tx;
IWDG_HandleTypeDef hiwdg; IWDG_HandleTypeDef hiwdg;
TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim2;
TIM_HandleTypeDef htim3; TIM_HandleTypeDef htim3;
#define ADC_CHANNELS 2 #define ADC_CHANNELS 2
#define ADC_SAMPLES 16 #define ADC_SAMPLES 16
uint32_t ADCReadings[ADC_SAMPLES * ADC_CHANNELS]; // room for 32 lots of the pair of readings uint32_t ADCReadings[ADC_SAMPLES * ADC_CHANNELS]; // room for 32 lots of the pair of readings
// Functions // Functions
static void SystemClock_Config(void); static void SystemClock_Config(void);
@@ -31,358 +31,352 @@ static void MX_TIM2_Init(void);
static void MX_DMA_Init(void); static void MX_DMA_Init(void);
static void MX_GPIO_Init(void); static void MX_GPIO_Init(void);
static void MX_ADC2_Init(void); static void MX_ADC2_Init(void);
void Setup_HAL() { void Setup_HAL() {
SystemClock_Config(); SystemClock_Config();
#ifndef SWD_ENABLE #ifndef SWD_ENABLE
__HAL_AFIO_REMAP_SWJ_DISABLE(); __HAL_AFIO_REMAP_SWJ_DISABLE();
#else #else
__HAL_AFIO_REMAP_SWJ_NOJTAG(); __HAL_AFIO_REMAP_SWJ_NOJTAG();
#endif #endif
MX_GPIO_Init(); MX_GPIO_Init();
MX_DMA_Init(); MX_DMA_Init();
MX_I2C1_Init(); MX_I2C1_Init();
MX_ADC1_Init(); MX_ADC1_Init();
MX_ADC2_Init(); MX_ADC2_Init();
MX_TIM3_Init(); MX_TIM3_Init();
MX_TIM2_Init(); MX_TIM2_Init();
MX_IWDG_Init(); MX_IWDG_Init();
HAL_ADC_Start(&hadc2); HAL_ADC_Start(&hadc2);
HAL_ADCEx_MultiModeStart_DMA(&hadc1, ADCReadings, (ADC_SAMPLES * ADC_CHANNELS)); // start DMA of normal readings HAL_ADCEx_MultiModeStart_DMA(&hadc1, ADCReadings, (ADC_SAMPLES * ADC_CHANNELS)); // start DMA of normal readings
HAL_ADCEx_InjectedStart(&hadc1); // enable injected readings HAL_ADCEx_InjectedStart(&hadc1); // enable injected readings
HAL_ADCEx_InjectedStart(&hadc2); // enable injected readings HAL_ADCEx_InjectedStart(&hadc2); // enable injected readings
} }
// channel 0 -> temperature sensor, 1-> VIN // channel 0 -> temperature sensor, 1-> VIN
uint16_t getADC(uint8_t channel) { uint16_t getADC(uint8_t channel) {
uint32_t sum = 0; uint32_t sum = 0;
for (uint8_t i = 0; i < ADC_SAMPLES; i++) { for (uint8_t i = 0; i < ADC_SAMPLES; i++) {
uint16_t adc1Sample = ADCReadings[channel + (i * ADC_CHANNELS)]; uint16_t adc1Sample = ADCReadings[channel + (i * ADC_CHANNELS)];
uint16_t adc2Sample = ADCReadings[channel + (i * ADC_CHANNELS)] >> 16; uint16_t adc2Sample = ADCReadings[channel + (i * ADC_CHANNELS)] >> 16;
sum += (adc1Sample + adc2Sample); sum += (adc1Sample + adc2Sample);
} }
return sum >> 2; return sum >> 2;
} }
/** System Clock Configuration /** System Clock Configuration
*/ */
void SystemClock_Config(void) { void SystemClock_Config(void) {
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInit; RCC_PeriphCLKInitTypeDef PeriphClkInit;
/**Initializes the CPU, AHB and APB busses clocks /**Initializes the CPU, AHB and APB busses clocks
*/ */
RCC_OscInitStruct.OscillatorType = RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI;
RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = 16;
RCC_OscInitStruct.HSICalibrationValue = 16; RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64MHz
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64MHz HAL_RCC_OscConfig(&RCC_OscInitStruct);
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/**Initializes the CPU, AHB and APB busses clocks /**Initializes the CPU, AHB and APB busses clocks
*/ */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV16; // TIM
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV16; // TIM // 2,3,4,5,6,7,12,13,14
// 2,3,4,5,6,7,12,13,14 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 mhz to some peripherals and adc
RCC_ClkInitStruct.APB2CLKDivider =
RCC_HCLK_DIV1; // 64 mhz to some peripherals and adc
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2); HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
PeriphClkInit.AdcClockSelection = PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; // 6 or 8 are the only non overclocked options
RCC_ADCPCLK2_DIV6; // 6 or 8 are the only non overclocked options HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
/**Configure the Systick interrupt time /**Configure the Systick interrupt time
*/ */
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000); HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
/**Configure the Systick /**Configure the Systick
*/ */
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
/* SysTick_IRQn interrupt configuration */ /* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0); HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
} }
/* ADC1 init function */ /* ADC1 init function */
static void MX_ADC1_Init(void) { static void MX_ADC1_Init(void) {
ADC_MultiModeTypeDef multimode; ADC_MultiModeTypeDef multimode;
ADC_ChannelConfTypeDef sConfig; ADC_ChannelConfTypeDef sConfig;
ADC_InjectionConfTypeDef sConfigInjected; ADC_InjectionConfTypeDef sConfigInjected;
/**Common config /**Common config
*/ */
hadc1.Instance = ADC1; hadc1.Instance = ADC1;
hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
hadc1.Init.ContinuousConvMode = ENABLE; hadc1.Init.ContinuousConvMode = ENABLE;
hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.NbrOfConversion = ADC_CHANNELS; hadc1.Init.NbrOfConversion = ADC_CHANNELS;
HAL_ADC_Init(&hadc1); HAL_ADC_Init(&hadc1);
/**Configure the ADC multi-mode /**Configure the ADC multi-mode
*/ */
multimode.Mode = ADC_DUALMODE_REGSIMULT_INJECSIMULT; multimode.Mode = ADC_DUALMODE_REGSIMULT_INJECSIMULT;
HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode); HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode);
/**Configure Regular Channel /**Configure Regular Channel
*/ */
sConfig.Channel = TMP36_ADC1_CHANNEL; sConfig.Channel = TMP36_ADC1_CHANNEL;
sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_71CYCLES_5; sConfig.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
HAL_ADC_ConfigChannel(&hadc1, &sConfig); HAL_ADC_ConfigChannel(&hadc1, &sConfig);
/**Configure Regular Channel /**Configure Regular Channel
*/ */
sConfig.Channel = VIN_ADC1_CHANNEL; sConfig.Channel = VIN_ADC1_CHANNEL;
sConfig.Rank = ADC_REGULAR_RANK_2; sConfig.Rank = ADC_REGULAR_RANK_2;
HAL_ADC_ConfigChannel(&hadc1, &sConfig); HAL_ADC_ConfigChannel(&hadc1, &sConfig);
/**Configure Injected Channel /**Configure Injected Channel
*/ */
// F in = 10.66 MHz // F in = 10.66 MHz
/* /*
* Injected time is 1 delay clock + (12 adc cycles*4)+4*sampletime =~217 * Injected time is 1 delay clock + (12 adc cycles*4)+4*sampletime =~217
* clocks = 0.2ms Charge time is 0.016 uS ideally So Sampling time must be >= * clocks = 0.2ms Charge time is 0.016 uS ideally So Sampling time must be >=
* 0.016uS 1/10.66MHz is 0.09uS, so 1 CLK is *should* be enough * 0.016uS 1/10.66MHz is 0.09uS, so 1 CLK is *should* be enough
* */ * */
sConfigInjected.InjectedChannel = TIP_TEMP_ADC1_CHANNEL; sConfigInjected.InjectedChannel = TIP_TEMP_ADC1_CHANNEL;
sConfigInjected.InjectedRank = 1; sConfigInjected.InjectedRank = 1;
sConfigInjected.InjectedNbrOfConversion = 4; sConfigInjected.InjectedNbrOfConversion = 4;
sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_1CYCLE_5; sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_1CYCLE_5;
sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJECCONV_T2_CC1; sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJECCONV_T2_CC1;
sConfigInjected.AutoInjectedConv = DISABLE; sConfigInjected.AutoInjectedConv = DISABLE;
sConfigInjected.InjectedDiscontinuousConvMode = DISABLE; sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
sConfigInjected.InjectedOffset = 0; sConfigInjected.InjectedOffset = 0;
HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected); HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_1CYCLE_5; sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_1CYCLE_5;
sConfigInjected.InjectedRank = 2; sConfigInjected.InjectedRank = 2;
HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected); HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
sConfigInjected.InjectedRank = 3; sConfigInjected.InjectedRank = 3;
HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected); HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
sConfigInjected.InjectedRank = 4; sConfigInjected.InjectedRank = 4;
HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected); HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
SET_BIT(hadc1.Instance->CR1, (ADC_CR1_JEOCIE)); // Enable end of injected conv irq SET_BIT(hadc1.Instance->CR1, (ADC_CR1_JEOCIE)); // Enable end of injected conv irq
// Run ADC internal calibration // Run ADC internal calibration
while (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK) while (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK)
; ;
} }
/* ADC2 init function */ /* ADC2 init function */
static void MX_ADC2_Init(void) { static void MX_ADC2_Init(void) {
ADC_ChannelConfTypeDef sConfig; ADC_ChannelConfTypeDef sConfig;
ADC_InjectionConfTypeDef sConfigInjected; ADC_InjectionConfTypeDef sConfigInjected;
/**Common config /**Common config
*/ */
hadc2.Instance = ADC2; hadc2.Instance = ADC2;
hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
hadc2.Init.ContinuousConvMode = ENABLE; hadc2.Init.ContinuousConvMode = ENABLE;
hadc2.Init.DiscontinuousConvMode = DISABLE; hadc2.Init.DiscontinuousConvMode = DISABLE;
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc2.Init.NbrOfConversion = ADC_CHANNELS; hadc2.Init.NbrOfConversion = ADC_CHANNELS;
HAL_ADC_Init(&hadc2); HAL_ADC_Init(&hadc2);
/**Configure Regular Channel /**Configure Regular Channel
*/ */
sConfig.Channel = TMP36_ADC2_CHANNEL; sConfig.Channel = TMP36_ADC2_CHANNEL;
sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_71CYCLES_5; sConfig.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
HAL_ADC_ConfigChannel(&hadc2, &sConfig); HAL_ADC_ConfigChannel(&hadc2, &sConfig);
sConfig.Channel = VIN_ADC2_CHANNEL; sConfig.Channel = VIN_ADC2_CHANNEL;
sConfig.Rank = ADC_REGULAR_RANK_2; sConfig.Rank = ADC_REGULAR_RANK_2;
HAL_ADC_ConfigChannel(&hadc2, &sConfig); HAL_ADC_ConfigChannel(&hadc2, &sConfig);
/**Configure Injected Channel /**Configure Injected Channel
*/ */
sConfigInjected.InjectedChannel = TIP_TEMP_ADC2_CHANNEL; sConfigInjected.InjectedChannel = TIP_TEMP_ADC2_CHANNEL;
sConfigInjected.InjectedRank = ADC_INJECTED_RANK_1; sConfigInjected.InjectedRank = ADC_INJECTED_RANK_1;
sConfigInjected.InjectedNbrOfConversion = 4; sConfigInjected.InjectedNbrOfConversion = 4;
sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_1CYCLE_5; sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_1CYCLE_5;
sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJECCONV_T2_CC1; sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJECCONV_T2_CC1;
sConfigInjected.AutoInjectedConv = DISABLE; sConfigInjected.AutoInjectedConv = DISABLE;
sConfigInjected.InjectedDiscontinuousConvMode = DISABLE; sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
sConfigInjected.InjectedOffset = 0; sConfigInjected.InjectedOffset = 0;
HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected); HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_1CYCLE_5; sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_1CYCLE_5;
sConfigInjected.InjectedRank = ADC_INJECTED_RANK_2; sConfigInjected.InjectedRank = ADC_INJECTED_RANK_2;
HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected); HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
sConfigInjected.InjectedRank = ADC_INJECTED_RANK_3; sConfigInjected.InjectedRank = ADC_INJECTED_RANK_3;
HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected); HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
sConfigInjected.InjectedRank = ADC_INJECTED_RANK_4; sConfigInjected.InjectedRank = ADC_INJECTED_RANK_4;
HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected); HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
// Run ADC internal calibration // Run ADC internal calibration
while (HAL_ADCEx_Calibration_Start(&hadc2) != HAL_OK) while (HAL_ADCEx_Calibration_Start(&hadc2) != HAL_OK)
; ;
} }
/* I2C1 init function */ /* I2C1 init function */
static void MX_I2C1_Init(void) { static void MX_I2C1_Init(void) {
hi2c1.Instance = I2C1; hi2c1.Instance = I2C1;
hi2c1.Init.ClockSpeed = 75000; hi2c1.Init.ClockSpeed = 75000;
// OLED doesnt handle >100k when its asleep (off). // OLED doesnt handle >100k when its asleep (off).
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
hi2c1.Init.OwnAddress1 = 0; hi2c1.Init.OwnAddress1 = 0;
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
hi2c1.Init.OwnAddress2 = 0; hi2c1.Init.OwnAddress2 = 0;
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
HAL_I2C_Init(&hi2c1); HAL_I2C_Init(&hi2c1);
} }
/* IWDG init function */ /* IWDG init function */
static void MX_IWDG_Init(void) { static void MX_IWDG_Init(void) {
hiwdg.Instance = IWDG; hiwdg.Instance = IWDG;
hiwdg.Init.Prescaler = IWDG_PRESCALER_256; hiwdg.Init.Prescaler = IWDG_PRESCALER_256;
hiwdg.Init.Reload = 100; hiwdg.Init.Reload = 100;
#ifndef SWD_ENABLE #ifndef SWD_ENABLE
HAL_IWDG_Init(&hiwdg); HAL_IWDG_Init(&hiwdg);
#endif #endif
} }
/* TIM3 init function */ /* TIM3 init function */
static void MX_TIM3_Init(void) { static void MX_TIM3_Init(void) {
TIM_ClockConfigTypeDef sClockSourceConfig; TIM_ClockConfigTypeDef sClockSourceConfig;
TIM_MasterConfigTypeDef sMasterConfig; TIM_MasterConfigTypeDef sMasterConfig;
TIM_OC_InitTypeDef sConfigOC; TIM_OC_InitTypeDef sConfigOC;
htim3.Instance = TIM3; htim3.Instance = TIM3;
htim3.Init.Prescaler = 8; htim3.Init.Prescaler = 8;
htim3.Init.CounterMode = TIM_COUNTERMODE_UP; htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
htim3.Init.Period = 100; // 5 Khz PWM freq htim3.Init.Period = 100; // 5 Khz PWM freq
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4; // 4mhz before div htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4; // 4mhz before div
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; //Preload the ARR register (though we dont use this) htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; // Preload the ARR register (though we dont use this)
HAL_TIM_Base_Init(&htim3); HAL_TIM_Base_Init(&htim3);
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig); HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig);
HAL_TIM_PWM_Init(&htim3); HAL_TIM_PWM_Init(&htim3);
HAL_TIM_OC_Init(&htim3); HAL_TIM_OC_Init(&htim3);
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig); HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig);
sConfigOC.OCMode = TIM_OCMODE_PWM1; sConfigOC.OCMode = TIM_OCMODE_PWM1;
sConfigOC.Pulse = 50; //50% duty cycle, that is AC coupled through the cap sConfigOC.Pulse = 50; // 50% duty cycle, that is AC coupled through the cap
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, PWM_Out_CHANNEL); HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, PWM_Out_CHANNEL);
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
/**TIM3 GPIO Configuration /**TIM3 GPIO Configuration
PWM_Out_Pin ------> TIM3_CH1 PWM_Out_Pin ------> TIM3_CH1
*/ */
GPIO_InitStruct.Pin = PWM_Out_Pin; GPIO_InitStruct.Pin = PWM_Out_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; //We would like sharp rising edges GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // We would like sharp rising edges
HAL_GPIO_Init(PWM_Out_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(PWM_Out_GPIO_Port, &GPIO_InitStruct);
#ifdef MODEL_TS100 #ifdef MODEL_TS100
// Remap TIM3_CH1 to be on PB4 // Remap TIM3_CH1 to be on PB4
__HAL_AFIO_REMAP_TIM3_PARTIAL() __HAL_AFIO_REMAP_TIM3_PARTIAL();
;
#else #else
// No re-map required // No re-map required
#endif #endif
HAL_TIM_PWM_Start(&htim3, PWM_Out_CHANNEL); HAL_TIM_PWM_Start(&htim3, PWM_Out_CHANNEL);
} }
/* TIM3 init function */ /* TIM3 init function */
static void MX_TIM2_Init(void) { static void MX_TIM2_Init(void) {
/* /*
* We use the channel 1 to trigger the ADC at end of PWM period * We use the channel 1 to trigger the ADC at end of PWM period
* And we use the channel 4 as the PWM modulation source using Interrupts * And we use the channel 4 as the PWM modulation source using Interrupts
* */ * */
TIM_ClockConfigTypeDef sClockSourceConfig; TIM_ClockConfigTypeDef sClockSourceConfig;
TIM_MasterConfigTypeDef sMasterConfig; TIM_MasterConfigTypeDef sMasterConfig;
TIM_OC_InitTypeDef sConfigOC; TIM_OC_InitTypeDef sConfigOC;
// Timer 2 is fairly slow as its being used to run the PWM and trigger the ADC // Timer 2 is fairly slow as its being used to run the PWM and trigger the ADC
// in the PWM off time. // in the PWM off time.
htim2.Instance = TIM2; htim2.Instance = TIM2;
// dummy value, will be reconfigured by BSPInit() // dummy value, will be reconfigured by BSPInit()
htim2.Init.Prescaler = 2000; // 2 MHz timer clock/2000 = 1 kHz tick rate htim2.Init.Prescaler = 2000; // 2 MHz timer clock/2000 = 1 kHz tick rate
// pwm out is 10k from tim3, we want to run our PWM at around 10hz or slower on the output stage // pwm out is 10k from tim3, we want to run our PWM at around 10hz or slower on the output stage
// These values give a rate of around 3.5 Hz for "fast" mode and 1.84 Hz for "slow" // These values give a rate of around 3.5 Hz for "fast" mode and 1.84 Hz for "slow"
htim2.Init.CounterMode = TIM_COUNTERMODE_UP; htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
// dummy value, will be reconfigured by BSPInit() // dummy value, will be reconfigured by BSPInit()
htim2.Init.Period = 255 + 17 * 2; htim2.Init.Period = 255 + 17 * 2;
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4; // 8 MHz (x2 APB1) before divide htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4; // 8 MHz (x2 APB1) before divide
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
htim2.Init.RepetitionCounter = 0; htim2.Init.RepetitionCounter = 0;
HAL_TIM_Base_Init(&htim2); HAL_TIM_Base_Init(&htim2);
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig); HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig);
HAL_TIM_PWM_Init(&htim2); HAL_TIM_PWM_Init(&htim2);
HAL_TIM_OC_Init(&htim2); HAL_TIM_OC_Init(&htim2);
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig); HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig);
sConfigOC.OCMode = TIM_OCMODE_PWM1; sConfigOC.OCMode = TIM_OCMODE_PWM1;
// dummy value, will be reconfigured by BSPInit() in the BSP.cpp // dummy value, will be reconfigured by BSPInit() in the BSP.cpp
sConfigOC.Pulse = 255 + 13 * 2; // 13 -> Delay of 7 ms sConfigOC.Pulse = 255 + 13 * 2; // 13 -> Delay of 7 ms
//255 is the largest time period of the drive signal, and then offset ADC sample to be a bit delayed after this // 255 is the largest time period of the drive signal, and then offset ADC sample to be a bit delayed after this
/* /*
* It takes 4 milliseconds for output to be stable after PWM turns off. * It takes 4 milliseconds for output to be stable after PWM turns off.
* Assume ADC samples in 0.5ms * Assume ADC samples in 0.5ms
* We need to set this to 100% + 4.5ms * We need to set this to 100% + 4.5ms
* */ * */
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1); HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1);
sConfigOC.Pulse = 0; //default to entirely off sConfigOC.Pulse = 0; // default to entirely off
HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4); HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4);
HAL_TIM_Base_Start_IT(&htim2); HAL_TIM_Base_Start_IT(&htim2);
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
HAL_TIM_PWM_Start_IT(&htim2, TIM_CHANNEL_4); HAL_TIM_PWM_Start_IT(&htim2, TIM_CHANNEL_4);
HAL_NVIC_SetPriority(TIM2_IRQn, 15, 0); HAL_NVIC_SetPriority(TIM2_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(TIM2_IRQn); HAL_NVIC_EnableIRQ(TIM2_IRQn);
} }
/** /**
* Enable DMA controller clock * Enable DMA controller clock
*/ */
static void MX_DMA_Init(void) { static void MX_DMA_Init(void) {
/* DMA controller clock enable */ /* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE();
;
/* DMA interrupt init */ /* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */ /* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
/* DMA1_Channel6_IRQn interrupt configuration */ /* DMA1_Channel6_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn); HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn);
/* DMA1_Channel7_IRQn interrupt configuration */ /* DMA1_Channel7_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn); HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
} }
/** Configure pins as /** Configure pins as
@@ -396,90 +390,80 @@ static void MX_DMA_Init(void) {
PB1 ------> ADCx_IN9 PB1 ------> ADCx_IN9
*/ */
static void MX_GPIO_Init(void) { static void MX_GPIO_Init(void) {
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
/* GPIO Ports Clock Enable */ /* GPIO Ports Clock Enable */
__HAL_RCC_GPIOD_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE();
; __HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE();
;
__HAL_RCC_GPIOB_CLK_ENABLE()
;
/*Configure GPIO pin Output Level */ /*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET);
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
/*Configure GPIO pins : PD0 PD1 */ /*Configure GPIO pins : PD0 PD1 */
GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1; GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/*Configure peripheral I/O remapping */ /*Configure peripheral I/O remapping */
__HAL_AFIO_REMAP_PD01_ENABLE() __HAL_AFIO_REMAP_PD01_ENABLE();
; //^ remap XTAL so that pins can be analog (all input buffers off).
//^ remap XTAL so that pins can be analog (all input buffers off). // reduces power consumption
// reduces power consumption
/* /*
* Configure All pins as analog by default * Configure All pins as analog by default
*/ */
GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_15;
GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_15; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
#ifdef MODEL_TS100 #ifdef MODEL_TS100
GPIO_PIN_3 | GPIO_PIN_3 |
#endif #endif
GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
#ifdef MODEL_TS100 #ifdef MODEL_TS100
#ifndef SWD_ENABLE #ifndef SWD_ENABLE
/* Pull USB and SWD lines low to prevent enumeration attempts and EMI affecting /* Pull USB and SWD lines low to prevent enumeration attempts and EMI affecting
* the debug core */ * the debug core */
GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14; GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_11, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_11, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_13, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_13, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_14, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_14, GPIO_PIN_RESET);
#else #else
/* Make all lines affecting SWD floating to allow debugging */ /* Make all lines affecting SWD floating to allow debugging */
GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_13; GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
#endif #endif
#else #else
/* TS80 */ /* TS80 */
/* Leave USB lines open circuit*/ /* Leave USB lines open circuit*/
#endif #endif
/*Configure GPIO pins : KEY_B_Pin KEY_A_Pin */ /*Configure GPIO pins : KEY_B_Pin KEY_A_Pin */
GPIO_InitStruct.Pin = KEY_B_Pin | KEY_A_Pin; GPIO_InitStruct.Pin = KEY_B_Pin | KEY_A_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Pull = GPIO_PULLUP;
HAL_GPIO_Init(KEY_B_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(KEY_B_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : OLED_RESET_Pin */ /*Configure GPIO pin : OLED_RESET_Pin */
GPIO_InitStruct.Pin = OLED_RESET_Pin; GPIO_InitStruct.Pin = OLED_RESET_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(OLED_RESET_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(OLED_RESET_GPIO_Port, &GPIO_InitStruct);
HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET);
// Pull down LCD reset // Pull down LCD reset
HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET);
HAL_Delay(30); HAL_Delay(30);
HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_SET);
}
#ifdef USE_FULL_ASSERT
void assert_failed(uint8_t* file, uint32_t line){
asm("bkpt");
} }
#ifdef USE_FULL_ASSERT
void assert_failed(uint8_t *file, uint32_t line) { asm("bkpt"); }
#endif #endif

6
source/Core/BSP/Miniware/Setup.h
View File

@@ -26,10 +26,10 @@ extern IWDG_HandleTypeDef hiwdg;
extern TIM_HandleTypeDef htim2; extern TIM_HandleTypeDef htim2;
extern TIM_HandleTypeDef htim3; extern TIM_HandleTypeDef htim3;
void Setup_HAL(); void Setup_HAL();
uint16_t getADC(uint8_t channel); uint16_t getADC(uint8_t channel);
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); //Since the hal header file does not define this one void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); // Since the hal header file does not define this one
#ifdef __cplusplus #ifdef __cplusplus
} }

21
source/Core/BSP/Miniware/Software_I2C.h
View File

@@ -7,18 +7,23 @@
#ifndef BSP_MINIWARE_SOFTWARE_I2C_H_ #ifndef BSP_MINIWARE_SOFTWARE_I2C_H_
#define BSP_MINIWARE_SOFTWARE_I2C_H_ #define BSP_MINIWARE_SOFTWARE_I2C_H_
#include "Model_Config.h"
#include "BSP.h" #include "BSP.h"
#include "Model_Config.h"
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
#ifdef I2C_SOFT #ifdef I2C_SOFT
#define SOFT_SCL_HIGH() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_SET) #define SOFT_SCL_HIGH() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_SET)
#define SOFT_SCL_LOW() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_RESET) #define SOFT_SCL_LOW() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_RESET)
#define SOFT_SDA_HIGH() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_SET) #define SOFT_SDA_HIGH() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_SET)
#define SOFT_SDA_LOW() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET) #define SOFT_SDA_LOW() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET)
#define SOFT_SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port,SDA2_Pin)==GPIO_PIN_SET?1:0) #define SOFT_SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port, SDA2_Pin) == GPIO_PIN_SET ? 1 : 0)
#define SOFT_SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port,SCL2_Pin)==GPIO_PIN_SET?1:0) #define SOFT_SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port, SCL2_Pin) == GPIO_PIN_SET ? 1 : 0)
#define SOFT_I2C_DELAY() {for(int xx=0;xx<40;xx++){asm("nop");}} #define SOFT_I2C_DELAY() \
{ \
for (int xx = 0; xx < 40; xx++) { \
asm("nop"); \
} \
}
#endif #endif

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source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h vendored
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source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h vendored
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@@ -1,238 +1,216 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx.h * @file stm32f1xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V4.2.0 * @version V4.2.0
* @date 31-March-2017 * @date 31-March-2017
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains: * is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select: * - Configuration section that allows to select:
* - The STM32F1xx device used in the target application * - The STM32F1xx device used in the target application
* - To use or not the peripheral<61>s drivers in application code(i.e. * - To use or not the peripheral<61>s drivers in application code(i.e.
* code will be based on direct access to peripheral<61>s registers * code will be based on direct access to peripheral<61>s registers
* rather than drivers API), this option is controlled by * rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER" * "#define USE_HAL_DRIVER"
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
/** @addtogroup stm32f1xx /** @addtogroup stm32f1xx
* @{ * @{
*/ */
#ifndef __STM32F1XX_H #ifndef __STM32F1XX_H
#define __STM32F1XX_H #define __STM32F1XX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif /* __cplusplus */ #endif /* __cplusplus */
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/** /**
* @brief STM32 Family * @brief STM32 Family
*/ */
#if !defined (STM32F1) #if !defined(STM32F1)
#define STM32F1 #define STM32F1
#endif /* STM32F1 */ #endif /* STM32F1 */
/* Uncomment the line below according to the target STM32L device used in your /* Uncomment the line below according to the target STM32L device used in your
application application
*/ */
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ #if !defined(STM32F100xB) && !defined(STM32F100xE) && !defined(STM32F101x6) && !defined(STM32F101xB) && !defined(STM32F101xE) && !defined(STM32F101xG) && !defined(STM32F102x6) \
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ && !defined(STM32F102xB) && !defined(STM32F103x6) && !defined(STM32F103xB) && !defined(STM32F103xE) && !defined(STM32F103xG) && !defined(STM32F105xC) && !defined(STM32F107xC)
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor. devices, you can define the device in your toolchain compiler preprocessor.
*/ */
#if !defined (USE_HAL_DRIVER) #if !defined(USE_HAL_DRIVER)
/** /**
* @brief Comment the line below if you will not use the peripherals drivers. * @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
/*#define USE_HAL_DRIVER */ /*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V4.2.0 * @brief CMSIS Device version number V4.2.0
*/ */
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ #define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) | (__STM32F1_CMSIS_VERSION_SUB1 << 16) | (__STM32F1_CMSIS_VERSION_SUB2 << 8) | (__STM32F1_CMSIS_VERSION_RC))
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
/** /**
* @} * @}
*/ */
/** @addtogroup Device_Included /** @addtogroup Device_Included
* @{ * @{
*/ */
#if defined(STM32F100xB) #if defined(STM32F100xB)
#include "stm32f100xb.h" #include "stm32f100xb.h"
#elif defined(STM32F100xE) #elif defined(STM32F100xE)
#include "stm32f100xe.h" #include "stm32f100xe.h"
#elif defined(STM32F101x6) #elif defined(STM32F101x6)
#include "stm32f101x6.h" #include "stm32f101x6.h"
#elif defined(STM32F101xB) #elif defined(STM32F101xB)
#include "stm32f101xb.h" #include "stm32f101xb.h"
#elif defined(STM32F101xE) #elif defined(STM32F101xE)
#include "stm32f101xe.h" #include "stm32f101xe.h"
#elif defined(STM32F101xG) #elif defined(STM32F101xG)
#include "stm32f101xg.h" #include "stm32f101xg.h"
#elif defined(STM32F102x6) #elif defined(STM32F102x6)
#include "stm32f102x6.h" #include "stm32f102x6.h"
#elif defined(STM32F102xB) #elif defined(STM32F102xB)
#include "stm32f102xb.h" #include "stm32f102xb.h"
#elif defined(STM32F103x6) #elif defined(STM32F103x6)
#include "stm32f103x6.h" #include "stm32f103x6.h"
#elif defined(STM32F103xB) #elif defined(STM32F103xB)
#include "stm32f103xb.h" #include "stm32f103xb.h"
#elif defined(STM32F103xE) #elif defined(STM32F103xE)
#include "stm32f103xe.h" #include "stm32f103xe.h"
#elif defined(STM32F103xG) #elif defined(STM32F103xG)
#include "stm32f103xg.h" #include "stm32f103xg.h"
#elif defined(STM32F105xC) #elif defined(STM32F105xC)
#include "stm32f105xc.h" #include "stm32f105xc.h"
#elif defined(STM32F107xC) #elif defined(STM32F107xC)
#include "stm32f107xc.h" #include "stm32f107xc.h"
#else #else
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
#endif #endif
/** /**
* @} * @}
*/ */
/** @addtogroup Exported_types /** @addtogroup Exported_types
* @{ * @{
*/ */
typedef enum typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState;
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrorStatus;
{
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
/** /**
* @} * @}
*/ */
/** @addtogroup Exported_macros /** @addtogroup Exported_macros
* @{ * @{
*/ */
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) #define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT)) #define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0)) #define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) #define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG)) #define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/** /**
* @} * @}
*/ */
#if defined (USE_HAL_DRIVER) #if defined(USE_HAL_DRIVER)
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */
#endif /* __STM32F1xx_H */ #endif /* __STM32F1xx_H */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -1,104 +1,103 @@
/** /**
****************************************************************************** ******************************************************************************
* @file system_stm32f10x.h * @file system_stm32f10x.h
* @author MCD Application Team * @author MCD Application Team
* @version V4.2.0 * @version V4.2.0
* @date 31-March-2017 * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
/** @addtogroup stm32f10x_system /** @addtogroup stm32f10x_system
* @{ * @{
*/ */
/** /**
* @brief Define to prevent recursive inclusion * @brief Define to prevent recursive inclusion
*/ */
#ifndef __SYSTEM_STM32F10X_H #ifndef __SYSTEM_STM32F10X_H
#define __SYSTEM_STM32F10X_H #define __SYSTEM_STM32F10X_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** @addtogroup STM32F10x_System_Includes /** @addtogroup STM32F10x_System_Includes
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F10x_System_Exported_types /** @addtogroup STM32F10x_System_Exported_types
* @{ * @{
*/ */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F10x_System_Exported_Constants /** @addtogroup STM32F10x_System_Exported_Constants
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F10x_System_Exported_Macros /** @addtogroup STM32F10x_System_Exported_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F10x_System_Exported_Functions /** @addtogroup STM32F10x_System_Exported_Functions
* @{ * @{
*/ */
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -107,10 +106,10 @@ extern void SystemCoreClockUpdate(void);
#endif /*__SYSTEM_STM32F10X_H */ #endif /*__SYSTEM_STM32F10X_H */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

147
source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_common_tables.h vendored
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@@ -1,42 +1,42 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
* *
* $Date: 19. October 2015 * $Date: 19. October 2015
* $Revision: V.1.4.5 a * $Revision: V.1.4.5 a
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_common_tables.h * Title: arm_common_tables.h
* *
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
* *
* Target Processor: Cortex-M4/Cortex-M3 * Target Processor: Cortex-M4/Cortex-M3
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
* are met: * are met:
* - Redistributions of source code must retain the above copyright * - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer. * notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright * - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in * notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the * the documentation and/or other materials provided with the
* distribution. * distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors * - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this * may be used to endorse or promote products derived from this
* software without specific prior written permission. * software without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H #ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H #define _ARM_COMMON_TABLES_H
@@ -44,8 +44,8 @@
#include "arm_math.h" #include "arm_math.h"
extern const uint16_t armBitRevTable[1024]; extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64]; extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64]; extern const q31_t armRecipTableQ31[64];
/* extern const q31_t realCoefAQ31[1024]; */ /* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */ /* extern const q31_t realCoefBQ31[1024]; */
extern const float32_t twiddleCoef_16[32]; extern const float32_t twiddleCoef_16[32];
@@ -58,24 +58,24 @@ extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096]; extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192]; extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096 #define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24]; extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48]; extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96]; extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192]; extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384]; extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768]; extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536]; extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072]; extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144]; extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24]; extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48]; extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96]; extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192]; extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384]; extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768]; extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536]; extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072]; extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144]; extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32]; extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64]; extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128]; extern const float32_t twiddleCoef_rfft_128[128];
@@ -85,14 +85,13 @@ extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048]; extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096]; extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */ /* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) #define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
@@ -108,13 +107,13 @@ extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENG
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */ /* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) #define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) #define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) #define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) #define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) #define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) #define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
@@ -130,7 +129,7 @@ extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4
/* Tables for Fast Math Sine and Cosine */ /* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */ #endif /* ARM_COMMON_TABLES_H */

136
source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_const_structs.h vendored
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@@ -1,79 +1,79 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
* *
* $Date: 19. March 2015 * $Date: 19. March 2015
* $Revision: V.1.4.5 * $Revision: V.1.4.5
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_const_structs.h * Title: arm_const_structs.h
* *
* Description: This file has constant structs that are initialized for * Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as * user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function. * arguments to the arm_cfft_f32() function.
* *
* Target Processor: Cortex-M4/Cortex-M3 * Target Processor: Cortex-M4/Cortex-M3
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
* are met: * are met:
* - Redistributions of source code must retain the above copyright * - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer. * notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright * - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in * notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the * the documentation and/or other materials provided with the
* distribution. * distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors * - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this * may be used to endorse or promote products derived from this
* software without specific prior written permission. * software without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H #ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H #define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h" #include "arm_common_tables.h"
#include "arm_math.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif #endif

10999
source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_math.h vendored
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443
source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_armcc.h vendored
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@@ -1,9 +1,9 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file cmsis_armcc.h * @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File * @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30 * @version V4.30
* @date 20. October 2015 * @date 20. October 2015
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved. All rights reserved.
@@ -31,13 +31,11 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H #ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!" #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif #endif
/* ########################### Core Function Access ########################### */ /* ########################### Core Function Access ########################### */
@@ -54,252 +52,212 @@
\details Returns the content of the Control Register. \details Returns the content of the Control Register.
\return Control Register value \return Control Register value
*/ */
__STATIC_INLINE uint32_t __get_CONTROL(void) __STATIC_INLINE uint32_t __get_CONTROL(void) {
{ register uint32_t __regControl __ASM("control");
register uint32_t __regControl __ASM("control"); return (__regControl);
return(__regControl);
} }
/** /**
\brief Set Control Register \brief Set Control Register
\details Writes the given value to the Control Register. \details Writes the given value to the Control Register.
\param [in] control Control Register value to set \param [in] control Control Register value to set
*/ */
__STATIC_INLINE void __set_CONTROL(uint32_t control) __STATIC_INLINE void __set_CONTROL(uint32_t control) {
{ register uint32_t __regControl __ASM("control");
register uint32_t __regControl __ASM("control");
__regControl = control; __regControl = control;
} }
/** /**
\brief Get IPSR Register \brief Get IPSR Register
\details Returns the content of the IPSR Register. \details Returns the content of the IPSR Register.
\return IPSR Register value \return IPSR Register value
*/ */
__STATIC_INLINE uint32_t __get_IPSR(void) __STATIC_INLINE uint32_t __get_IPSR(void) {
{ register uint32_t __regIPSR __ASM("ipsr");
register uint32_t __regIPSR __ASM("ipsr"); return (__regIPSR);
return(__regIPSR);
} }
/** /**
\brief Get APSR Register \brief Get APSR Register
\details Returns the content of the APSR Register. \details Returns the content of the APSR Register.
\return APSR Register value \return APSR Register value
*/ */
__STATIC_INLINE uint32_t __get_APSR(void) __STATIC_INLINE uint32_t __get_APSR(void) {
{ register uint32_t __regAPSR __ASM("apsr");
register uint32_t __regAPSR __ASM("apsr"); return (__regAPSR);
return(__regAPSR);
} }
/** /**
\brief Get xPSR Register \brief Get xPSR Register
\details Returns the content of the xPSR Register. \details Returns the content of the xPSR Register.
\return xPSR Register value \return xPSR Register value
*/ */
__STATIC_INLINE uint32_t __get_xPSR(void) __STATIC_INLINE uint32_t __get_xPSR(void) {
{ register uint32_t __regXPSR __ASM("xpsr");
register uint32_t __regXPSR __ASM("xpsr"); return (__regXPSR);
return(__regXPSR);
} }
/** /**
\brief Get Process Stack Pointer \brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP). \details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value \return PSP Register value
*/ */
__STATIC_INLINE uint32_t __get_PSP(void) __STATIC_INLINE uint32_t __get_PSP(void) {
{ register uint32_t __regProcessStackPointer __ASM("psp");
register uint32_t __regProcessStackPointer __ASM("psp"); return (__regProcessStackPointer);
return(__regProcessStackPointer);
} }
/** /**
\brief Set Process Stack Pointer \brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP). \details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set \param [in] topOfProcStack Process Stack Pointer value to set
*/ */
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) {
{ register uint32_t __regProcessStackPointer __ASM("psp");
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack; __regProcessStackPointer = topOfProcStack;
} }
/** /**
\brief Get Main Stack Pointer \brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP). \details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value \return MSP Register value
*/ */
__STATIC_INLINE uint32_t __get_MSP(void) __STATIC_INLINE uint32_t __get_MSP(void) {
{ register uint32_t __regMainStackPointer __ASM("msp");
register uint32_t __regMainStackPointer __ASM("msp"); return (__regMainStackPointer);
return(__regMainStackPointer);
} }
/** /**
\brief Set Main Stack Pointer \brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP). \details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set \param [in] topOfMainStack Main Stack Pointer value to set
*/ */
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) {
{ register uint32_t __regMainStackPointer __ASM("msp");
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack; __regMainStackPointer = topOfMainStack;
} }
/** /**
\brief Get Priority Mask \brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register. \details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value \return Priority Mask value
*/ */
__STATIC_INLINE uint32_t __get_PRIMASK(void) __STATIC_INLINE uint32_t __get_PRIMASK(void) {
{ register uint32_t __regPriMask __ASM("primask");
register uint32_t __regPriMask __ASM("primask"); return (__regPriMask);
return(__regPriMask);
} }
/** /**
\brief Set Priority Mask \brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register. \details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask \param [in] priMask Priority Mask
*/ */
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) {
{ register uint32_t __regPriMask __ASM("primask");
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask); __regPriMask = (priMask);
} }
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/** /**
\brief Enable FIQ \brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR. \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes. Can only be executed in Privileged modes.
*/ */
#define __enable_fault_irq __enable_fiq #define __enable_fault_irq __enable_fiq
/** /**
\brief Disable FIQ \brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR. \details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes. Can only be executed in Privileged modes.
*/ */
#define __disable_fault_irq __disable_fiq #define __disable_fault_irq __disable_fiq
/** /**
\brief Get Base Priority \brief Get Base Priority
\details Returns the current value of the Base Priority register. \details Returns the current value of the Base Priority register.
\return Base Priority register value \return Base Priority register value
*/ */
__STATIC_INLINE uint32_t __get_BASEPRI(void) __STATIC_INLINE uint32_t __get_BASEPRI(void) {
{ register uint32_t __regBasePri __ASM("basepri");
register uint32_t __regBasePri __ASM("basepri"); return (__regBasePri);
return(__regBasePri);
} }
/** /**
\brief Set Base Priority \brief Set Base Priority
\details Assigns the given value to the Base Priority register. \details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set \param [in] basePri Base Priority value to set
*/ */
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) {
{ register uint32_t __regBasePri __ASM("basepri");
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU); __regBasePri = (basePri & 0xFFU);
} }
/** /**
\brief Set Base Priority with condition \brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level. or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set \param [in] basePri Base Priority value to set
*/ */
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) {
{ register uint32_t __regBasePriMax __ASM("basepri_max");
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU); __regBasePriMax = (basePri & 0xFFU);
} }
/** /**
\brief Get Fault Mask \brief Get Fault Mask
\details Returns the current value of the Fault Mask register. \details Returns the current value of the Fault Mask register.
\return Fault Mask register value \return Fault Mask register value
*/ */
__STATIC_INLINE uint32_t __get_FAULTMASK(void) __STATIC_INLINE uint32_t __get_FAULTMASK(void) {
{ register uint32_t __regFaultMask __ASM("faultmask");
register uint32_t __regFaultMask __ASM("faultmask"); return (__regFaultMask);
return(__regFaultMask);
} }
/** /**
\brief Set Fault Mask \brief Set Fault Mask
\details Assigns the given value to the Fault Mask register. \details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set \param [in] faultMask Fault Mask value to set
*/ */
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) {
{ register uint32_t __regFaultMask __ASM("faultmask");
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1); __regFaultMask = (faultMask & (uint32_t)1);
} }
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/** /**
\brief Get FPSCR \brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register. \details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value \return Floating Point Status/Control register value
*/ */
__STATIC_INLINE uint32_t __get_FPSCR(void) __STATIC_INLINE uint32_t __get_FPSCR(void) {
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr"); register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr); return (__regfpscr);
#else #else
return(0U); return (0U);
#endif #endif
} }
/** /**
\brief Set FPSCR \brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register. \details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set \param [in] fpscr Floating Point Status/Control value to set
*/ */
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) {
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr"); register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr); __regfpscr = (fpscr);
#endif #endif
} }
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */ /*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */ /* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions Access to dedicated instructions
@@ -310,30 +268,26 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\brief No Operation \brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes. \details No Operation does nothing. This instruction can be used for code alignment purposes.
*/ */
#define __NOP __nop #define __NOP __nop
/** /**
\brief Wait For Interrupt \brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/ */
#define __WFI __wfi #define __WFI __wfi
/** /**
\brief Wait For Event \brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter \details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs. a low-power state until one of a number of events occurs.
*/ */
#define __WFE __wfe #define __WFE __wfe
/** /**
\brief Send Event \brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU. \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/ */
#define __SEV __sev #define __SEV __sev
/** /**
\brief Instruction Synchronization Barrier \brief Instruction Synchronization Barrier
@@ -341,33 +295,36 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
so that all instructions following the ISB are fetched from cache or memory, so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed. after the instruction has been completed.
*/ */
#define __ISB() do {\ #define __ISB() \
__schedule_barrier();\ do { \
__isb(0xF);\ __schedule_barrier(); \
__schedule_barrier();\ __isb(0xF); \
} while (0U) __schedule_barrier(); \
} while (0U)
/** /**
\brief Data Synchronization Barrier \brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier. \details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete. It completes when all explicit memory accesses before this instruction complete.
*/ */
#define __DSB() do {\ #define __DSB() \
__schedule_barrier();\ do { \
__dsb(0xF);\ __schedule_barrier(); \
__schedule_barrier();\ __dsb(0xF); \
} while (0U) __schedule_barrier(); \
} while (0U)
/** /**
\brief Data Memory Barrier \brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before \details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion. and after the instruction, without ensuring their completion.
*/ */
#define __DMB() do {\ #define __DMB() \
__schedule_barrier();\ do { \
__dmb(0xF);\ __schedule_barrier(); \
__schedule_barrier();\ __dmb(0xF); \
} while (0U) __schedule_barrier(); \
} while (0U)
/** /**
\brief Reverse byte order (32 bit) \brief Reverse byte order (32 bit)
@@ -375,8 +332,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
#define __REV __rev #define __REV __rev
/** /**
\brief Reverse byte order (16 bit) \brief Reverse byte order (16 bit)
@@ -385,11 +341,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\return Reversed value \return Reversed value
*/ */
#ifndef __NO_EMBEDDED_ASM #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr }
{
rev16 r0, r0
bx lr
}
#endif #endif
/** /**
@@ -399,14 +351,9 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
\return Reversed value \return Reversed value
*/ */
#ifndef __NO_EMBEDDED_ASM #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr }
{
revsh r0, r0
bx lr
}
#endif #endif
/** /**
\brief Rotate Right in unsigned value (32 bit) \brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@@ -414,8 +361,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value Number of Bits to rotate \param [in] value Number of Bits to rotate
\return Rotated value \return Rotated value
*/ */
#define __ROR __ror #define __ROR __ror
/** /**
\brief Breakpoint \brief Breakpoint
@@ -424,8 +370,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value is ignored by the processor. \param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint. If required, a debugger can use it to store additional information about the breakpoint.
*/ */
#define __BKPT(value) __breakpoint(value) #define __BKPT(value) __breakpoint(value)
/** /**
\brief Reverse bit order of value \brief Reverse bit order of value
@@ -433,37 +378,33 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit #define __RBIT __rbit
#else #else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
{
uint32_t result; uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */ result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) for (value >>= 1U; value; value >>= 1U) {
{
result <<= 1U; result <<= 1U;
result |= value & 1U; result |= value & 1U;
s--; s--;
} }
result <<= s; /* shift when v's highest bits are zero */ result <<= s; /* shift when v's highest bits are zero */
return(result); return (result);
} }
#endif #endif
/** /**
\brief Count leading zeros \brief Count leading zeros
\details Counts the number of leading zeros of a data value. \details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros \param [in] value Value to count the leading zeros
\return number of leading zeros in value \return number of leading zeros in value
*/ */
#define __CLZ __clz #define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/** /**
\brief LDR Exclusive (8 bit) \brief LDR Exclusive (8 bit)
@@ -472,12 +413,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return value of type uint8_t at (*ptr) \return value of type uint8_t at (*ptr)
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) #define __LDREXB(ptr) ((uint8_t)__ldrex(ptr))
#else #else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop")
#endif #endif
/** /**
\brief LDR Exclusive (16 bit) \brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values. \details Executes a exclusive LDR instruction for 16 bit values.
@@ -485,12 +425,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return value of type uint16_t at (*ptr) \return value of type uint16_t at (*ptr)
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) #define __LDREXH(ptr) ((uint16_t)__ldrex(ptr))
#else #else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop")
#endif #endif
/** /**
\brief LDR Exclusive (32 bit) \brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values. \details Executes a exclusive LDR instruction for 32 bit values.
@@ -498,12 +437,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return value of type uint32_t at (*ptr) \return value of type uint32_t at (*ptr)
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) #define __LDREXW(ptr) ((uint32_t)__ldrex(ptr))
#else #else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop")
#endif #endif
/** /**
\brief STR Exclusive (8 bit) \brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values. \details Executes a exclusive STR instruction for 8 bit values.
@@ -513,12 +451,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return 1 Function failed \return 1 Function failed
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr) #define __STREXB(value, ptr) __strex(value, ptr)
#else #else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif #endif
/** /**
\brief STR Exclusive (16 bit) \brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values. \details Executes a exclusive STR instruction for 16 bit values.
@@ -528,12 +465,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return 1 Function failed \return 1 Function failed
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr) #define __STREXH(value, ptr) __strex(value, ptr)
#else #else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif #endif
/** /**
\brief STR Exclusive (32 bit) \brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values. \details Executes a exclusive STR instruction for 32 bit values.
@@ -543,18 +479,16 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return 1 Function failed \return 1 Function failed
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr) #define __STREXW(value, ptr) __strex(value, ptr)
#else #else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif #endif
/** /**
\brief Remove the exclusive lock \brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX. \details Removes the exclusive lock which is created by LDREX.
*/ */
#define __CLREX __clrex #define __CLREX __clrex
/** /**
\brief Signed Saturate \brief Signed Saturate
@@ -563,8 +497,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\param [in] sat Bit position to saturate to (1..32) \param [in] sat Bit position to saturate to (1..32)
\return Saturated value \return Saturated value
*/ */
#define __SSAT __ssat #define __SSAT __ssat
/** /**
\brief Unsigned Saturate \brief Unsigned Saturate
@@ -573,8 +506,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\param [in] sat Bit position to saturate to (0..31) \param [in] sat Bit position to saturate to (0..31)
\return Saturated value \return Saturated value
*/ */
#define __USAT __usat #define __USAT __usat
/** /**
\brief Rotate Right with Extend (32 bit) \brief Rotate Right with Extend (32 bit)
@@ -584,22 +516,16 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return Rotated value \return Rotated value
*/ */
#ifndef __NO_EMBEDDED_ASM #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr }
{
rrx r0, r0
bx lr
}
#endif #endif
/** /**
\brief LDRT Unprivileged (8 bit) \brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value. \details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data \param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr) \return value of type uint8_t at (*ptr)
*/ */
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) #define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
/** /**
\brief LDRT Unprivileged (16 bit) \brief LDRT Unprivileged (16 bit)
@@ -607,8 +533,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] ptr Pointer to data \param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr) \return value of type uint16_t at (*ptr)
*/ */
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) #define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
/** /**
\brief LDRT Unprivileged (32 bit) \brief LDRT Unprivileged (32 bit)
@@ -616,8 +541,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] ptr Pointer to data \param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr) \return value of type uint32_t at (*ptr)
*/ */
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) #define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
/** /**
\brief STRT Unprivileged (8 bit) \brief STRT Unprivileged (8 bit)
@@ -625,8 +549,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] value Value to store \param [in] value Value to store
\param [in] ptr Pointer to location \param [in] ptr Pointer to location
*/ */
#define __STRBT(value, ptr) __strt(value, ptr) #define __STRBT(value, ptr) __strt(value, ptr)
/** /**
\brief STRT Unprivileged (16 bit) \brief STRT Unprivileged (16 bit)
@@ -634,8 +557,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] value Value to store \param [in] value Value to store
\param [in] ptr Pointer to location \param [in] ptr Pointer to location
*/ */
#define __STRHT(value, ptr) __strt(value, ptr) #define __STRHT(value, ptr) __strt(value, ptr)
/** /**
\brief STRT Unprivileged (32 bit) \brief STRT Unprivileged (32 bit)
@@ -643,92 +565,87 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] value Value to store \param [in] value Value to store
\param [in] ptr Pointer to location \param [in] ptr Pointer to location
*/ */
#define __STRT(value, ptr) __strt(value, ptr) #define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */ /* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions Access to dedicated SIMD instructions
@{ @{
*/ */
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ #if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
#define __SADD8 __sadd8 #define __SADD8 __sadd8
#define __QADD8 __qadd8 #define __QADD8 __qadd8
#define __SHADD8 __shadd8 #define __SHADD8 __shadd8
#define __UADD8 __uadd8 #define __UADD8 __uadd8
#define __UQADD8 __uqadd8 #define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8 #define __UHADD8 __uhadd8
#define __SSUB8 __ssub8 #define __SSUB8 __ssub8
#define __QSUB8 __qsub8 #define __QSUB8 __qsub8
#define __SHSUB8 __shsub8 #define __SHSUB8 __shsub8
#define __USUB8 __usub8 #define __USUB8 __usub8
#define __UQSUB8 __uqsub8 #define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8 #define __UHSUB8 __uhsub8
#define __SADD16 __sadd16 #define __SADD16 __sadd16
#define __QADD16 __qadd16 #define __QADD16 __qadd16
#define __SHADD16 __shadd16 #define __SHADD16 __shadd16
#define __UADD16 __uadd16 #define __UADD16 __uadd16
#define __UQADD16 __uqadd16 #define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16 #define __UHADD16 __uhadd16
#define __SSUB16 __ssub16 #define __SSUB16 __ssub16
#define __QSUB16 __qsub16 #define __QSUB16 __qsub16
#define __SHSUB16 __shsub16 #define __SHSUB16 __shsub16
#define __USUB16 __usub16 #define __USUB16 __usub16
#define __UQSUB16 __uqsub16 #define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16 #define __UHSUB16 __uhsub16
#define __SASX __sasx #define __SASX __sasx
#define __QASX __qasx #define __QASX __qasx
#define __SHASX __shasx #define __SHASX __shasx
#define __UASX __uasx #define __UASX __uasx
#define __UQASX __uqasx #define __UQASX __uqasx
#define __UHASX __uhasx #define __UHASX __uhasx
#define __SSAX __ssax #define __SSAX __ssax
#define __QSAX __qsax #define __QSAX __qsax
#define __SHSAX __shsax #define __SHSAX __shsax
#define __USAX __usax #define __USAX __usax
#define __UQSAX __uqsax #define __UQSAX __uqsax
#define __UHSAX __uhsax #define __UHSAX __uhsax
#define __USAD8 __usad8 #define __USAD8 __usad8
#define __USADA8 __usada8 #define __USADA8 __usada8
#define __SSAT16 __ssat16 #define __SSAT16 __ssat16
#define __USAT16 __usat16 #define __USAT16 __usat16
#define __UXTB16 __uxtb16 #define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16 #define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16 #define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16 #define __SXTAB16 __sxtab16
#define __SMUAD __smuad #define __SMUAD __smuad
#define __SMUADX __smuadx #define __SMUADX __smuadx
#define __SMLAD __smlad #define __SMLAD __smlad
#define __SMLADX __smladx #define __SMLADX __smladx
#define __SMLALD __smlald #define __SMLALD __smlald
#define __SMLALDX __smlaldx #define __SMLALDX __smlaldx
#define __SMUSD __smusd #define __SMUSD __smusd
#define __SMUSDX __smusdx #define __SMUSDX __smusdx
#define __SMLSD __smlsd #define __SMLSD __smlsd
#define __SMLSDX __smlsdx #define __SMLSDX __smlsdx
#define __SMLSLD __smlsld #define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx #define __SMLSLDX __smlsldx
#define __SEL __sel #define __SEL __sel
#define __QADD __qadd #define __QADD __qadd
#define __QSUB __qsub #define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ #define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ #define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ #define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U)) >> 32U))
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */ #endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */ /*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */ #endif /* __CMSIS_ARMCC_H */

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source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_armcc_V6.h vendored
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source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_gcc.h vendored
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647
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0.h vendored
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@@ -1,9 +1,9 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_cm0.h * @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.30 * @version V4.30
* @date 20. October 2015 * @date 20. October 2015
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved. All rights reserved.
@@ -31,11 +31,10 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CM0_H_GENERIC #ifndef __CORE_CM0_H_GENERIC
@@ -44,7 +43,7 @@
#include <stdint.h> #include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** /**
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -71,97 +69,95 @@
*/ */
/* CMSIS CM0 definitions */ /* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ #define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined(__CC_ARM)
#if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline #define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#define __packed #define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#else #else
#error Unknown compiler #error Unknown compiler
#endif #endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all This core does not support an FPU at all
*/ */
#define __FPU_USED 0U #define __FPU_USED 0U
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP #if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#if defined __ARMVFP__ #if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#if defined __FPU_VFP__ #if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#if ( __CSMC__ & 0x400U) #if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -175,25 +171,25 @@
#define __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* check device defines and use defaults */ /* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES #if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV #ifndef __CM0_REV
#define __CM0_REV 0x0000U #define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!" #warning "__CM0_REV not defined in device header file; using default!"
#endif #endif
#ifndef __NVIC_PRIO_BITS #ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U #define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif #endif
#ifndef __Vendor_SysTickConfig #ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U #define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif #endif
#endif #endif
/* IO definitions (access restrictions to peripheral registers) */ /* IO definitions (access restrictions to peripheral registers) */
@@ -205,22 +201,20 @@
\li for automatic generation of peripheral register debug information. \li for automatic generation of peripheral register debug information.
*/ */
#ifdef __cplusplus #ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */ #define __I volatile /*!< Defines 'read only' permissions */
#else #else
#define __I volatile const /*!< Defines 'read only' permissions */ #define __I volatile const /*!< Defines 'read only' permissions */
#endif #endif
#define __O volatile /*!< Defines 'write only' permissions */ #define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */ /* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */ /*@} end of group Cortex_M0 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -244,111 +238,99 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */
{ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ } b; /*!< Structure used for bit access */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ uint32_t w; /*!< Type used for word access */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type; } APSR_Type;
/* APSR Register Definitions */ /* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ } b; /*!< Structure used for bit access */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ uint32_t w; /*!< Type used for word access */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type; } IPSR_Type;
/* IPSR Register Definitions */ /* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t _reserved1 : 3; /*!< bit: 25..27 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ } b; /*!< Structure used for bit access */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ uint32_t w; /*!< Type used for word access */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type; } xPSR_Type;
/* xPSR Register Definitions */ /* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */
{ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ } b; /*!< Structure used for bit access */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ uint32_t w; /*!< Type used for word access */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type; } CONTROL_Type;
/* CONTROL Register Definitions */ /* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -359,23 +341,21 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U];
uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U];
uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U];
uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U];
uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U];
uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type;
} NVIC_Type;
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -386,103 +366,101 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0;
uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1;
uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type; } SCB_Type;
/* SCB CPUID Register Definitions */ /* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */ /* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */ /* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */ /* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */ /* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */ /* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -493,48 +471,46 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type; } SysTick_Type;
/* SysTick Control / Status Register Definitions */ /* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */ /* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */ /* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */ /* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -544,7 +520,6 @@ typedef struct
*/ */
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -558,7 +533,7 @@ typedef struct
\param[in] value Value of the bit field. \param[in] value Value of the bit field.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
@@ -566,11 +541,10 @@ typedef struct
\param[in] value Value of register. \param[in] value Value of register.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -579,20 +553,17 @@ typedef struct
*/ */
/* Memory mapping of Cortex-M0 Hardware */ /* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -604,8 +575,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -616,32 +585,23 @@ typedef struct
/* Interrupt Priorities are WORD accessible only under ARMv6M */ /* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */ /* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -650,33 +610,21 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -685,21 +633,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0) SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
{ } else {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -709,33 +650,26 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{ return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else {
} return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{ __DSB(); /* Ensure all outstanding memory accesses included
__DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */
buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | __DSB(); /* Ensure completion of memory access */
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */ for (;;) /* wait until reset */
{ {
__NOP(); __NOP();
} }
@@ -743,8 +677,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -766,29 +698,22 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) return (1UL); /* Reload value impossible */
{
return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk | return (0UL); /* Function successful */
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
} }
#endif #endif
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

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source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmFunc.h vendored
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@@ -1,9 +1,9 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_cmFunc.h * @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File * @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30 * @version V4.30
* @date 20. October 2015 * @date 20. October 2015
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved. All rights reserved.
@@ -31,17 +31,15 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CMFUNC_H #ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H #define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */ /* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface /** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@@ -49,36 +47,36 @@
*/ */
/*------------------ RealView Compiler -----------------*/ /*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#include "cmsis_armcc.h" #include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/ /*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h" #include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/ /*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#include "cmsis_gcc.h" #include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/ /*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#include <cmsis_iar.h> #include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/ /*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/ /*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
/*------------------ COSMIC Compiler -------------------*/ /*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#include <cmsis_csm.h> #include <cmsis_csm.h>
#endif #endif

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@@ -1,9 +1,9 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_cmInstr.h * @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File * @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30 * @version V4.30
* @date 20. October 2015 * @date 20. October 2015
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved. All rights reserved.
@@ -31,17 +31,15 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CMINSTR_H #ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H #define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */ /* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions Access to dedicated instructions
@@ -49,36 +47,36 @@
*/ */
/*------------------ RealView Compiler -----------------*/ /*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#include "cmsis_armcc.h" #include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/ /*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h" #include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/ /*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#include "cmsis_gcc.h" #include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/ /*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#include <cmsis_iar.h> #include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/ /*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/ /*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
/*------------------ COSMIC Compiler -------------------*/ /*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#include <cmsis_csm.h> #include <cmsis_csm.h>
#endif #endif

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@@ -1,9 +1,9 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_cmSimd.h * @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File * @brief CMSIS Cortex-M SIMD Header File
* @version V4.30 * @version V4.30
* @date 20. October 2015 * @date 20. October 2015
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved. All rights reserved.
@@ -31,21 +31,19 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CMSIMD_H #ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H #define __CORE_CMSIMD_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ################### Compiler specific Intrinsics ########################### */ /* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions Access to dedicated SIMD instructions
@@ -53,42 +51,41 @@
*/ */
/*------------------ RealView Compiler -----------------*/ /*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#include "cmsis_armcc.h" #include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/ /*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h" #include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/ /*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#include "cmsis_gcc.h" #include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/ /*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#include <cmsis_iar.h> #include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/ /*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/ /*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
/*------------------ COSMIC Compiler -------------------*/ /*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#include <cmsis_csm.h> #include <cmsis_csm.h>
#endif #endif
/*@} end of group CMSIS_SIMD_intrinsics */ /*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h vendored
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@@ -1,38 +1,38 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal.h * @file stm32f1xx_hal.h
* @author MCD Application Team * @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL * @brief This file contains all the functions prototypes for the HAL
* module driver. * module driver.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_H #ifndef __STM32F1xx_HAL_H
@@ -46,317 +46,308 @@ extern "C" {
#include "stm32f1xx_hal_conf.h" #include "stm32f1xx_hal_conf.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup HAL /** @addtogroup HAL
* @{ * @{
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants /** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{ * @{
*/ */
/** @defgroup HAL_TICK_FREQ Tick Frequency /** @defgroup HAL_TICK_FREQ Tick Frequency
* @{ * @{
*/ */
typedef enum typedef enum { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef;
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/** /**
* @} * @}
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
extern uint32_t uwTickPrio; extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq; extern HAL_TickFreqTypeDef uwTickFreq;
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros /** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{ * @{
*/ */
/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
* @brief Freeze/Unfreeze Peripherals in Debug mode * @brief Freeze/Unfreeze Peripherals in Debug mode
* Note: On devices STM32F10xx8 and STM32F10xxB, * Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G * STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6 * STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode). * debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* @{ * @{
*/ */
/* Peripherals on APB1 */ /* Peripherals on APB1 */
/** /**
* @brief TIM2 Peripherals Debug mode * @brief TIM2 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
/** /**
* @brief TIM3 Peripherals Debug mode * @brief TIM3 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
#if defined (DBGMCU_CR_DBG_TIM4_STOP) #if defined(DBGMCU_CR_DBG_TIM4_STOP)
/** /**
* @brief TIM4 Peripherals Debug mode * @brief TIM4 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM5_STOP) #if defined(DBGMCU_CR_DBG_TIM5_STOP)
/** /**
* @brief TIM5 Peripherals Debug mode * @brief TIM5 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM6_STOP) #if defined(DBGMCU_CR_DBG_TIM6_STOP)
/** /**
* @brief TIM6 Peripherals Debug mode * @brief TIM6 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM7_STOP) #if defined(DBGMCU_CR_DBG_TIM7_STOP)
/** /**
* @brief TIM7 Peripherals Debug mode * @brief TIM7 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM12_STOP) #if defined(DBGMCU_CR_DBG_TIM12_STOP)
/** /**
* @brief TIM12 Peripherals Debug mode * @brief TIM12 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM13_STOP) #if defined(DBGMCU_CR_DBG_TIM13_STOP)
/** /**
* @brief TIM13 Peripherals Debug mode * @brief TIM13 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM14_STOP) #if defined(DBGMCU_CR_DBG_TIM14_STOP)
/** /**
* @brief TIM14 Peripherals Debug mode * @brief TIM14 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
#endif #endif
/** /**
* @brief WWDG Peripherals Debug mode * @brief WWDG Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
/** /**
* @brief IWDG Peripherals Debug mode * @brief IWDG Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
/** /**
* @brief I2C1 Peripherals Debug mode * @brief I2C1 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
/** /**
* @brief I2C2 Peripherals Debug mode * @brief I2C2 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#endif #endif
#if defined (DBGMCU_CR_DBG_CAN1_STOP) #if defined(DBGMCU_CR_DBG_CAN1_STOP)
/** /**
* @brief CAN1 Peripherals Debug mode * @brief CAN1 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_CAN2_STOP) #if defined(DBGMCU_CR_DBG_CAN2_STOP)
/** /**
* @brief CAN2 Peripherals Debug mode * @brief CAN2 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
#endif #endif
/* Peripherals on APB2 */ /* Peripherals on APB2 */
#if defined (DBGMCU_CR_DBG_TIM1_STOP) #if defined(DBGMCU_CR_DBG_TIM1_STOP)
/** /**
* @brief TIM1 Peripherals Debug mode * @brief TIM1 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM8_STOP) #if defined(DBGMCU_CR_DBG_TIM8_STOP)
/** /**
* @brief TIM8 Peripherals Debug mode * @brief TIM8 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM9_STOP) #if defined(DBGMCU_CR_DBG_TIM9_STOP)
/** /**
* @brief TIM9 Peripherals Debug mode * @brief TIM9 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM10_STOP) #if defined(DBGMCU_CR_DBG_TIM10_STOP)
/** /**
* @brief TIM10 Peripherals Debug mode * @brief TIM10 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM11_STOP) #if defined(DBGMCU_CR_DBG_TIM11_STOP)
/** /**
* @brief TIM11 Peripherals Debug mode * @brief TIM11 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
#endif #endif
#if defined(DBGMCU_CR_DBG_TIM15_STOP)
#if defined (DBGMCU_CR_DBG_TIM15_STOP)
/** /**
* @brief TIM15 Peripherals Debug mode * @brief TIM15 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM16_STOP) #if defined(DBGMCU_CR_DBG_TIM16_STOP)
/** /**
* @brief TIM16 Peripherals Debug mode * @brief TIM16 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM17_STOP) #if defined(DBGMCU_CR_DBG_TIM17_STOP)
/** /**
* @brief TIM17 Peripherals Debug mode * @brief TIM17 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
#endif #endif
/** /**
* @} * @}
*/ */
/** @defgroup HAL_Private_Macros HAL Private Macros /** @defgroup HAL_Private_Macros HAL Private Macros
* @{ * @{
*/ */
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/** /**
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions /** @addtogroup HAL_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup HAL_Exported_Functions_Group1 /** @addtogroup HAL_Exported_Functions_Group1
* @{ * @{
*/ */
/* Initialization and de-initialization functions ******************************/ /* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void); HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void); void HAL_MspInit(void);
void HAL_MspDeInit(void); void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/** /**
* @} * @}
*/ */
/** @addtogroup HAL_Exported_Functions_Group2 /** @addtogroup HAL_Exported_Functions_Group2
* @{ * @{
*/ */
/* Peripheral Control functions ************************************************/ /* Peripheral Control functions ************************************************/
void HAL_IncTick(void); void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay); void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void); uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void); uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void); HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void); void HAL_SuspendTick(void);
void HAL_ResumeTick(void); void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void); uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void); uint32_t HAL_GetDEVID(void);
void HAL_DBGMCU_EnableDBGSleepMode(void); void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void); void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void); void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void); void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void); void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void); void HAL_DBGMCU_DisableDBGStandbyMode(void);
void HAL_GetUID(uint32_t *UID); void HAL_GetUID(uint32_t *UID);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/** @defgroup HAL_Private_Variables HAL Private Variables /** @defgroup HAL_Private_Variables HAL Private Variables
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @defgroup HAL_Private_Constants HAL Private Constants /** @defgroup HAL_Private_Constants HAL Private Constants
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }

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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h vendored
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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h vendored
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@@ -1,303 +1,306 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_cortex.h * @file stm32f1xx_hal_cortex.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of CORTEX HAL module. * @brief Header file of CORTEX HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CORTEX_H #ifndef __STM32F1xx_HAL_CORTEX_H
#define __STM32F1xx_HAL_CORTEX_H #define __STM32F1xx_HAL_CORTEX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup CORTEX /** @addtogroup CORTEX
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types Cortex Exported Types /** @defgroup CORTEX_Exported_Types Cortex Exported Types
* @{ * @{
*/ */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure * @brief MPU Region initialization structure
* @{ * @{
*/ */
typedef struct typedef struct {
{ uint8_t Enable; /*!< Specifies the status of the region.
uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ uint8_t Number; /*!< Specifies the number of the region to protect.
uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */
This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ uint8_t Size; /*!< Specifies the size of the region to protect.
uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */
This parameter can be a value of @ref CORTEX_MPU_Region_Size */ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level.
uint8_t TypeExtField; /*!< Specifies the TEX field level. This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ uint8_t AccessPermission; /*!< Specifies the region access permission type.
uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ uint8_t DisableExec; /*!< Specifies the instruction access status.
uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ } MPU_Region_InitTypeDef;
}MPU_Region_InitTypeDef;
/** /**
* @} * @}
*/ */
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{ * @{
*/ */
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{ * @{
*/ */
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority #define NVIC_PRIORITYGROUP_0 \
4 bits for subpriority */ 0x00000007U /*!< 0 bits for pre-emption priority \
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority 4 bits for subpriority */
3 bits for subpriority */ #define NVIC_PRIORITYGROUP_1 \
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority 0x00000006U /*!< 1 bits for pre-emption priority \
2 bits for subpriority */ 3 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority #define NVIC_PRIORITYGROUP_2 \
1 bits for subpriority */ 0x00000005U /*!< 2 bits for pre-emption priority \
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority 2 bits for subpriority */
0 bits for subpriority */ #define NVIC_PRIORITYGROUP_3 \
0x00000004U /*!< 3 bits for pre-emption priority \
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 \
0x00000003U /*!< 4 bits for pre-emption priority \
0 bits for subpriority */
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
* @{ * @{
*/ */
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U #define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/** /**
* @} * @}
*/ */
#if (__MPU_PRESENT == 1) #if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{ * @{
*/ */
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{ * @{
*/ */
#define MPU_REGION_ENABLE ((uint8_t)0x01) #define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00) #define MPU_REGION_DISABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{ * @{
*/ */
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{ * @{
*/ */
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{ * @{
*/ */
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{ * @{
*/ */
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{ * @{
*/ */
#define MPU_TEX_LEVEL0 ((uint8_t)0x00) #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01) #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02) #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{ * @{
*/ */
#define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05) #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06) #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07) #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08) #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{ * @{
*/ */
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01) #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{ * @{
*/ */
#define MPU_REGION_NUMBER0 ((uint8_t)0x00) #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01) #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02) #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03) #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07) #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/** /**
* @} * @}
*/ */
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/* Exported Macros -----------------------------------------------------------*/ /* Exported Macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions /** @addtogroup CORTEX_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup CORTEX_Exported_Functions_Group1 /** @addtogroup CORTEX_Exported_Functions_Group1
* @{ * @{
*/ */
/* Initialization and de-initialization functions *****************************/ /* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void); void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/** /**
* @} * @}
*/ */
/** @addtogroup CORTEX_Exported_Functions_Group2 /** @addtogroup CORTEX_Exported_Functions_Group2
* @{ * @{
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void); uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void); void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Enable(uint32_t MPU_Control);
@@ -305,122 +308,81 @@ void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{ * @{
*/ */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ #define IS_NVIC_PRIORITY_GROUP(GROUP) \
((GROUP) == NVIC_PRIORITYGROUP_1) || \ (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2))
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) \
((TYPE) == MPU_REGION_PRIV_RW) || \ (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \ || ((TYPE) == MPU_REGION_PRIV_RO_URO))
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ #define IS_MPU_REGION_NUMBER(NUMBER) \
((NUMBER) == MPU_REGION_NUMBER1) || \ (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) \
((NUMBER) == MPU_REGION_NUMBER2) || \ || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ #define IS_MPU_REGION_SIZE(SIZE) \
((SIZE) == MPU_REGION_SIZE_64B) || \ (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B) \
((SIZE) == MPU_REGION_SIZE_128B) || \ || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) \
((SIZE) == MPU_REGION_SIZE_256B) || \ || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) \
((SIZE) == MPU_REGION_SIZE_512B) || \ || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) \
((SIZE) == MPU_REGION_SIZE_1KB) || \ || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) \
((SIZE) == MPU_REGION_SIZE_2KB) || \ || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32F1xx_HAL_CORTEX_H */ #endif /* __STM32F1xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

199
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h vendored
View File

@@ -1,38 +1,38 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_def.h * @file stm32f1xx_hal_def.h
* @author MCD Application Team * @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and * @brief This file contains HAL common defines, enumeration, macros and
* structures definitions. * structures definitions.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_DEF #ifndef __STM32F1xx_HAL_DEF
@@ -52,92 +52,78 @@ extern "C" {
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** /**
* @brief HAL Status structures definition * @brief HAL Status structures definition
*/ */
typedef enum typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef;
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/** /**
* @brief HAL Lock structures definition * @brief HAL Lock structures definition
*/ */
typedef enum typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef;
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \ do { \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \ (__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0U) } while (0U)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
/** @brief Reset the Handle's State field. /** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle. * @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose: * @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter * - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field. * to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function * Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed * HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed). * (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling * - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function * In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware. * HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None * @retval None
*/ */
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
#if (USE_RTOS == 1U) #if (USE_RTOS == 1U)
/* Reserved for future use */ /* Reserved for future use */
#error "USE_RTOS should be 0 in the current HAL release" #error "USE_RTOS should be 0 in the current HAL release"
#else #else
#define __HAL_LOCK(__HANDLE__) \ #define __HAL_LOCK(__HANDLE__) \
do{ \ do { \
if((__HANDLE__)->Lock == HAL_LOCKED) \ if ((__HANDLE__)->Lock == HAL_LOCKED) { \
{ \ return HAL_BUSY; \
return HAL_BUSY; \ } else { \
} \ (__HANDLE__)->Lock = HAL_LOCKED; \
else \ } \
{ \ } while (0U)
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0U)
#define __HAL_UNLOCK(__HANDLE__) \ #define __HAL_UNLOCK(__HANDLE__) \
do{ \ do { \
(__HANDLE__)->Lock = HAL_UNLOCKED; \ (__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0U) } while (0U)
#endif /* USE_RTOS */ #endif /* USE_RTOS */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __weak #ifndef __weak
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#endif /* __weak */ #endif /* __weak */
#ifndef __packed #ifndef __packed
#define __packed __attribute__((__packed__)) #define __packed __attribute__((__packed__))
#endif /* __packed */ #endif /* __packed */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END #ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4))) #define __ALIGN_END __attribute__((aligned(4)))
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
@@ -147,19 +133,18 @@ typedef enum
#define __ALIGN_END #define __ALIGN_END
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */ #if defined(__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4) #define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */ #elif defined(__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
#endif /* __CC_ARM */ #endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */ #endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/** /**
* @brief __RAM_FUNC definition * @brief __RAM_FUNC definition
*/ */
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
/* ARM Compiler /* ARM Compiler
------------ ------------
RAM functions are defined using the toolchain options. RAM functions are defined using the toolchain options.
@@ -171,14 +156,14 @@ typedef enum
*/ */
#define __RAM_FUNC #define __RAM_FUNC
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
/* ICCARM Compiler /* ICCARM Compiler
--------------- ---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc". RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/ */
#define __RAM_FUNC __ramfunc #define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
/* GNU Compiler /* GNU Compiler
------------ ------------
RAM functions are defined using a specific toolchain attribute RAM functions are defined using a specific toolchain attribute
@@ -189,15 +174,15 @@ typedef enum
#endif #endif
/** /**
* @brief __NOINLINE definition * @brief __NOINLINE definition
*/ */
#if defined ( __CC_ARM ) || defined ( __GNUC__ ) #if defined(__CC_ARM) || defined(__GNUC__)
/* ARM & GNUCompiler /* ARM & GNUCompiler
---------------- ----------------
*/ */
#define __NOINLINE __attribute__ ( (noinline) ) #define __NOINLINE __attribute__((noinline))
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
/* ICCARM Compiler /* ICCARM Compiler
--------------- ---------------
*/ */

628
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h vendored
View File

@@ -1,468 +1,448 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_dma.h * @file stm32f1xx_hal_dma.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of DMA HAL module. * @brief Header file of DMA HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_DMA_H #ifndef __STM32F1xx_HAL_DMA_H
#define __STM32F1xx_HAL_DMA_H #define __STM32F1xx_HAL_DMA_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup DMA /** @addtogroup DMA
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types /** @defgroup DMA_Exported_Types DMA Exported Types
* @{ * @{
*/ */
/** /**
* @brief DMA Configuration Structure definition * @brief DMA Configuration Structure definition
*/ */
typedef struct typedef struct {
{ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory.
from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_Data_transfer_direction */
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */ This parameter can be a value of @ref DMA_Memory_incremented_mode */
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */ This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width. uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */ This parameter can be a value of @ref DMA_Memory_data_size */
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory @note The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */ data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */ This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef; } DMA_InitTypeDef;
/** /**
* @brief HAL DMA State structures definition * @brief HAL DMA State structures definition
*/ */
typedef enum typedef enum {
{ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ } HAL_DMA_StateTypeDef;
}HAL_DMA_StateTypeDef;
/** /**
* @brief HAL DMA Error Code structure definition * @brief HAL DMA Error Code structure definition
*/ */
typedef enum typedef enum {
{ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ } HAL_DMA_LevelCompleteTypeDef;
}HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callback ID structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
}HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
} DMA_HandleTypeDef;
/** /**
* @} * @brief HAL DMA Callback ID structure definition
*/ */
typedef enum {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
} HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef {
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void (*XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
void (*XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
void (*XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
void (*XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
} DMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants /** @defgroup DMA_Exported_Constants DMA Exported Constants
* @{ * @{
*/ */
/** @defgroup DMA_Error_Code DMA Error Code /** @defgroup DMA_Error_Code DMA Error Code
* @{ * @{
*/ */
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{ * @{
*/ */
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{ * @{
*/ */
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{ * @{
*/ */
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{ * @{
*/ */
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Memory_data_size DMA Memory data size /** @defgroup DMA_Memory_data_size DMA Memory data size
* @{ * @{
*/ */
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_mode DMA mode /** @defgroup DMA_mode DMA mode
* @{ * @{
*/ */
#define DMA_NORMAL 0x00000000U /*!< Normal mode */ #define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Priority_level DMA Priority level /** @defgroup DMA_Priority_level DMA Priority level
* @{ * @{
*/ */
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{ * @{
*/ */
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
/** /**
* @} * @}
*/ */
/** @defgroup DMA_flag_definitions DMA flag definitions /** @defgroup DMA_flag_definitions DMA flag definitions
* @{ * @{
*/ */
#define DMA_FLAG_GL1 0x00000001U #define DMA_FLAG_GL1 0x00000001U
#define DMA_FLAG_TC1 0x00000002U #define DMA_FLAG_TC1 0x00000002U
#define DMA_FLAG_HT1 0x00000004U #define DMA_FLAG_HT1 0x00000004U
#define DMA_FLAG_TE1 0x00000008U #define DMA_FLAG_TE1 0x00000008U
#define DMA_FLAG_GL2 0x00000010U #define DMA_FLAG_GL2 0x00000010U
#define DMA_FLAG_TC2 0x00000020U #define DMA_FLAG_TC2 0x00000020U
#define DMA_FLAG_HT2 0x00000040U #define DMA_FLAG_HT2 0x00000040U
#define DMA_FLAG_TE2 0x00000080U #define DMA_FLAG_TE2 0x00000080U
#define DMA_FLAG_GL3 0x00000100U #define DMA_FLAG_GL3 0x00000100U
#define DMA_FLAG_TC3 0x00000200U #define DMA_FLAG_TC3 0x00000200U
#define DMA_FLAG_HT3 0x00000400U #define DMA_FLAG_HT3 0x00000400U
#define DMA_FLAG_TE3 0x00000800U #define DMA_FLAG_TE3 0x00000800U
#define DMA_FLAG_GL4 0x00001000U #define DMA_FLAG_GL4 0x00001000U
#define DMA_FLAG_TC4 0x00002000U #define DMA_FLAG_TC4 0x00002000U
#define DMA_FLAG_HT4 0x00004000U #define DMA_FLAG_HT4 0x00004000U
#define DMA_FLAG_TE4 0x00008000U #define DMA_FLAG_TE4 0x00008000U
#define DMA_FLAG_GL5 0x00010000U #define DMA_FLAG_GL5 0x00010000U
#define DMA_FLAG_TC5 0x00020000U #define DMA_FLAG_TC5 0x00020000U
#define DMA_FLAG_HT5 0x00040000U #define DMA_FLAG_HT5 0x00040000U
#define DMA_FLAG_TE5 0x00080000U #define DMA_FLAG_TE5 0x00080000U
#define DMA_FLAG_GL6 0x00100000U #define DMA_FLAG_GL6 0x00100000U
#define DMA_FLAG_TC6 0x00200000U #define DMA_FLAG_TC6 0x00200000U
#define DMA_FLAG_HT6 0x00400000U #define DMA_FLAG_HT6 0x00400000U
#define DMA_FLAG_TE6 0x00800000U #define DMA_FLAG_TE6 0x00800000U
#define DMA_FLAG_GL7 0x01000000U #define DMA_FLAG_GL7 0x01000000U
#define DMA_FLAG_TC7 0x02000000U #define DMA_FLAG_TC7 0x02000000U
#define DMA_FLAG_HT7 0x04000000U #define DMA_FLAG_HT7 0x04000000U
#define DMA_FLAG_TE7 0x08000000U #define DMA_FLAG_TE7 0x08000000U
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros /** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{ * @{
*/ */
/** @brief Reset DMA handle state. /** @brief Reset DMA handle state.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval None * @retval None
*/ */
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/** /**
* @brief Enable the specified DMA Channel. * @brief Enable the specified DMA Channel.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval None * @retval None
*/ */
#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
/** /**
* @brief Disable the specified DMA Channel. * @brief Disable the specified DMA Channel.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval None * @retval None
*/ */
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
/* Interrupt & Flag management */ /* Interrupt & Flag management */
/** /**
* @brief Enables the specified DMA Channel interrupts. * @brief Enables the specified DMA Channel interrupts.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None * @retval None
*/ */
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
/** /**
* @brief Disable the specified DMA Channel interrupts. * @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None * @retval None
*/ */
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
/** /**
* @brief Check whether the specified DMA Channel interrupt is enabled or not. * @brief Check whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check. * @param __INTERRUPT__: specifies the DMA interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET). * @retval The state of DMA_IT (SET or RESET).
*/ */
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** /**
* @brief Return the number of remaining data units in the current DMA Channel transfer. * @brief Return the number of remaining data units in the current DMA Channel transfer.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The number of remaining data units in the current DMA Channel transfer. * @retval The number of remaining data units in the current DMA Channel transfer.
*/ */
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/** /**
* @} * @}
*/ */
/* Include DMA HAL Extension module */ /* Include DMA HAL Extension module */
#include "stm32f1xx_hal_dma_ex.h" #include "stm32f1xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions /** @addtogroup DMA_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup DMA_Exported_Functions_Group1 /** @addtogroup DMA_Exported_Functions_Group1
* @{ * @{
*/ */
/* Initialization and de-initialization functions *****************************/ /* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
/** @addtogroup DMA_Exported_Functions_Group2 /** @addtogroup DMA_Exported_Functions_Group2
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/** /**
* @} * @}
*/ */
/** @addtogroup DMA_Exported_Functions_Group3 /** @addtogroup DMA_Exported_Functions_Group3
* @{ * @{
*/ */
/* Peripheral State and Error functions ***************************************/ /* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros /** @defgroup DMA_Private_Macros DMA Private Macros
* @{ * @{
*/ */
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))
((STATE) == DMA_MINC_DISABLE))
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD))
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD))
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR))
((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/** /**
* @} * @}
*/ */
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }

493
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h vendored
View File

@@ -1,287 +1,330 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_dma_ex.h * @file stm32f1xx_hal_dma_ex.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of DMA HAL extension module. * @brief Header file of DMA HAL extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_DMA_EX_H #ifndef __STM32F1xx_HAL_DMA_EX_H
#define __STM32F1xx_HAL_DMA_EX_H #define __STM32F1xx_HAL_DMA_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup DMAEx DMAEx /** @defgroup DMAEx DMAEx
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
* @{ * @{
*/ */
/* Interrupt & Flag management */ /* Interrupt & Flag management */
#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
* @{ * @{
*/ */
/** /**
* @brief Returns the current DMA Channel transfer complete flag. * @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ? DMA_FLAG_TC1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ? DMA_FLAG_TC2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ? DMA_FLAG_TC3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ ? DMA_FLAG_TC4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ ? DMA_FLAG_TC5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_TC5) ? DMA_FLAG_TC6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_TC7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 : DMA_FLAG_TC5)
/** /**
* @brief Returns the current DMA Channel half transfer complete flag. * @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ? DMA_FLAG_HT1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ? DMA_FLAG_HT2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ? DMA_FLAG_HT3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ ? DMA_FLAG_HT4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ ? DMA_FLAG_HT5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_HT5) ? DMA_FLAG_HT6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_HT7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 : DMA_FLAG_HT5)
/** /**
* @brief Returns the current DMA Channel transfer error flag. * @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ? DMA_FLAG_TE1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ? DMA_FLAG_TE2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ? DMA_FLAG_TE3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ ? DMA_FLAG_TE4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ ? DMA_FLAG_TE5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_TE5) ? DMA_FLAG_TE6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_TE7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 : DMA_FLAG_TE5)
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ ? DMA_FLAG_GL1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ ? DMA_FLAG_GL2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ ? DMA_FLAG_GL3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ ? DMA_FLAG_GL4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ ? DMA_FLAG_GL5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_GL5) ? DMA_FLAG_GL6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
/** ? DMA_FLAG_GL7 \
* @brief Get the DMA Channel pending flags. : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
* @param __HANDLE__: DMA handle ? DMA_FLAG_GL1 \
* @param __FLAG__: Get the specified flag. : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
* This parameter can be any combination of the following values: ? DMA_FLAG_GL2 \
* @arg DMA_FLAG_TCx: Transfer complete flag : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
* @arg DMA_FLAG_HTx: Half transfer complete flag ? DMA_FLAG_GL3 \
* @arg DMA_FLAG_TEx: Transfer error flag : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 : DMA_FLAG_GL5)
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
(DMA1->ISR & (__FLAG__)))
/** /**
* @brief Clears the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval None * @retval The state of FLAG (SET or RESET).
*/ */
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
(DMA1->IFCR = (__FLAG__)))
/** /**
* @} * @brief Clears the DMA Channel pending flags.
*/ * @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
/**
* @}
*/
#else #else
/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
* @{ * @{
*/ */
/** /**
* @brief Returns the current DMA Channel transfer complete flag. * @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ? DMA_FLAG_TC1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ? DMA_FLAG_TC2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ? DMA_FLAG_TC3 \
DMA_FLAG_TC7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 : DMA_FLAG_TC7)
/** /**
* @brief Return the current DMA Channel half transfer complete flag. * @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ? DMA_FLAG_HT1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ? DMA_FLAG_HT2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ? DMA_FLAG_HT3 \
DMA_FLAG_HT7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 : DMA_FLAG_HT7)
/** /**
* @brief Return the current DMA Channel transfer error flag. * @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ? DMA_FLAG_TE1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ? DMA_FLAG_TE2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ? DMA_FLAG_TE3 \
DMA_FLAG_TE7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 : DMA_FLAG_TE7)
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ ? DMA_FLAG_GL1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ ? DMA_FLAG_GL2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ ? DMA_FLAG_GL3 \
DMA_FLAG_GL7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 : DMA_FLAG_GL7)
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag. * @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag * @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be 1_7 to select the DMA Channel flag. * Where x can be 1_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET). * @retval The state of FLAG (SET or RESET).
*/ */
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
/** /**
* @brief Clear the DMA Channel pending flags. * @brief Clear the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag * @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be 1_7 to select the DMA Channel flag. * Where x can be 1_7 to select the DMA Channel flag.
* @retval None * @retval None
*/ */
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
/** /**
* @} * @}
*/ */
#endif #endif
/**
* @}
*/
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/**
* @}
*/
#ifdef __cplusplus #ifdef __cplusplus
} }

352
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h vendored
View File

@@ -1,96 +1,91 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_flash.h * @file stm32f1xx_hal_flash.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of Flash HAL module. * @brief Header file of Flash HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_FLASH_H #ifndef __STM32F1xx_HAL_FLASH_H
#define __STM32F1xx_HAL_FLASH_H #define __STM32F1xx_HAL_FLASH_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup FLASH /** @addtogroup FLASH
* @{ * @{
*/ */
/** @addtogroup FLASH_Private_Constants /** @addtogroup FLASH_Private_Constants
* @{ * @{
*/ */
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
/** /**
* @} * @}
*/ */
/** @addtogroup FLASH_Private_Macros /** @addtogroup FLASH_Private_Macros
* @{ * @{
*/ */
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
#if defined(FLASH_ACR_LATENCY) #if defined(FLASH_ACR_LATENCY)
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1) || ((__LATENCY__) == FLASH_LATENCY_2))
((__LATENCY__) == FLASH_LATENCY_1) || \
((__LATENCY__) == FLASH_LATENCY_2))
#else #else
#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
#endif /* FLASH_ACR_LATENCY */ #endif /* FLASH_ACR_LATENCY */
/** /**
* @} * @}
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types /** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{ * @{
*/ */
/** /**
* @brief FLASH Procedure structure definition * @brief FLASH Procedure structure definition
*/ */
typedef enum typedef enum {
{ FLASH_PROC_NONE = 0U,
FLASH_PROC_NONE = 0U,
FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_PAGEERASE = 1U,
FLASH_PROC_MASSERASE = 2U, FLASH_PROC_MASSERASE = 2U,
FLASH_PROC_PROGRAMHALFWORD = 3U, FLASH_PROC_PROGRAMHALFWORD = 3U,
@@ -98,92 +93,91 @@ typedef enum
FLASH_PROC_PROGRAMDOUBLEWORD = 5U FLASH_PROC_PROGRAMDOUBLEWORD = 5U
} FLASH_ProcedureTypeDef; } FLASH_ProcedureTypeDef;
/** /**
* @brief FLASH handle Structure definition * @brief FLASH handle Structure definition
*/ */
typedef struct typedef struct {
{
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
__IO uint64_t Data; /*!< Internal variable to save data to be programmed */ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
HAL_LockTypeDef Lock; /*!< FLASH locking object */ __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
__IO uint32_t ErrorCode; /*!< FLASH error code HAL_LockTypeDef Lock; /*!< FLASH locking object */
This parameter can be a value of @ref FLASH_Error_Codes */
__IO uint32_t ErrorCode; /*!< FLASH error code
This parameter can be a value of @ref FLASH_Error_Codes */
} FLASH_ProcessTypeDef; } FLASH_ProcessTypeDef;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{ * @{
*/ */
/** @defgroup FLASH_Error_Codes FLASH Error Codes /** @defgroup FLASH_Error_Codes FLASH Error Codes
* @{ * @{
*/ */
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ #define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
/** /**
* @} * @}
*/ */
/** @defgroup FLASH_Type_Program FLASH Type Program /** @defgroup FLASH_Type_Program FLASH Type Program
* @{ * @{
*/ */
#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!<Program a half-word (16-bit) at a specified address.*/ #define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!<Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_WORD 0x02U /*!<Program a word (32-bit) at a specified address.*/ #define FLASH_TYPEPROGRAM_WORD 0x02U /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/ #define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/
/** /**
* @} * @}
*/ */
#if defined(FLASH_ACR_LATENCY) #if defined(FLASH_ACR_LATENCY)
/** @defgroup FLASH_Latency FLASH Latency /** @defgroup FLASH_Latency FLASH Latency
* @{ * @{
*/ */
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ #define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */ #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
/** /**
* @} * @}
*/ */
#else #else
/** @defgroup FLASH_Latency FLASH Latency /** @defgroup FLASH_Latency FLASH Latency
* @{ * @{
*/ */
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ #define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
/** /**
* @} * @}
*/ */
#endif /* FLASH_ACR_LATENCY */ #endif /* FLASH_ACR_LATENCY */
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @brief macros to control FLASH features * @brief macros to control FLASH features
* @{ * @{
*/ */
/** @defgroup FLASH_Half_Cycle FLASH Half Cycle /** @defgroup FLASH_Half_Cycle FLASH Half Cycle
* @brief macros to handle FLASH half cycle * @brief macros to handle FLASH half cycle
* @{ * @{
@@ -195,7 +189,7 @@ typedef struct
8 MHz that can be obtained with the use of HSI or HSE but not of PLL. 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
* @retval None * @retval None
*/ */
#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA) #define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
/** /**
* @brief Disable the FLASH half cycle access. * @brief Disable the FLASH half cycle access.
@@ -206,133 +200,132 @@ typedef struct
#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
/** /**
* @} * @}
*/ */
#if defined(FLASH_ACR_LATENCY) #if defined(FLASH_ACR_LATENCY)
/** @defgroup FLASH_EM_Latency FLASH Latency /** @defgroup FLASH_EM_Latency FLASH Latency
* @brief macros to handle FLASH Latency * @brief macros to handle FLASH Latency
* @{ * @{
*/ */
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__ FLASH Latency
* The value of this parameter depend on device used within the same series
* @retval None
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
/** /**
* @brief Get the FLASH Latency. * @brief Set the FLASH Latency.
* @retval FLASH Latency * @param __LATENCY__ FLASH Latency
* The value of this parameter depend on device used within the same series * The value of this parameter depend on device used within the same series
*/ * @retval None
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) */
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__))
/** /**
* @} * @brief Get the FLASH Latency.
*/ * @retval FLASH Latency
* The value of this parameter depend on device used within the same series
*/
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
/**
* @}
*/
#endif /* FLASH_ACR_LATENCY */ #endif /* FLASH_ACR_LATENCY */
/** @defgroup FLASH_Prefetch FLASH Prefetch /** @defgroup FLASH_Prefetch FLASH Prefetch
* @brief macros to handle FLASH Prefetch buffer * @brief macros to handle FLASH Prefetch buffer
* @{ * @{
*/ */
/** /**
* @brief Enable the FLASH prefetch buffer. * @brief Enable the FLASH prefetch buffer.
* @retval None * @retval None
*/ */
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
/** /**
* @brief Disable the FLASH prefetch buffer. * @brief Disable the FLASH prefetch buffer.
* @retval None * @retval None
*/ */
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Include FLASH HAL Extended module */ /* Include FLASH HAL Extended module */
#include "stm32f1xx_hal_flash_ex.h" #include "stm32f1xx_hal_flash_ex.h"
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions /** @addtogroup FLASH_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup FLASH_Exported_Functions_Group1 /** @addtogroup FLASH_Exported_Functions_Group1
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
/* FLASH IRQ handler function */ /* FLASH IRQ handler function */
void HAL_FLASH_IRQHandler(void); void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */ /* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/** /**
* @} * @}
*/ */
/** @addtogroup FLASH_Exported_Functions_Group2 /** @addtogroup FLASH_Exported_Functions_Group2
* @{ * @{
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
void HAL_FLASH_OB_Launch(void); void HAL_FLASH_OB_Launch(void);
/** /**
* @} * @}
*/ */
/** @addtogroup FLASH_Exported_Functions_Group3 /** @addtogroup FLASH_Exported_Functions_Group3
* @{ * @{
*/ */
/* Peripheral State and Error functions ***************************************/ /* Peripheral State and Error functions ***************************************/
uint32_t HAL_FLASH_GetError(void); uint32_t HAL_FLASH_GetError(void);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private function -------------------------------------------------*/ /* Private function -------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions /** @addtogroup FLASH_Private_Functions
* @{ * @{
*/ */
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#if defined(FLASH_BANK2_END) #if defined(FLASH_BANK2_END)
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
#endif /* FLASH_BANK2_END */ #endif /* FLASH_BANK2_END */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -341,4 +334,3 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
#endif /* __STM32F1xx_HAL_FLASH_H */ #endif /* __STM32F1xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h vendored
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399
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h vendored
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@@ -1,37 +1,37 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_gpio.h * @file stm32f1xx_hal_gpio.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of GPIO HAL module. * @brief Header file of GPIO HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_GPIO_H #ifndef __STM32F1xx_HAL_GPIO_H
@@ -45,275 +45,260 @@ extern "C" {
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup GPIO /** @addtogroup GPIO
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types /** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{ * @{
*/ */
/** /**
* @brief GPIO Init structure definition * @brief GPIO Init structure definition
*/ */
typedef struct typedef struct {
{ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
uint32_t Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins_define */
This parameter can be any value of @ref GPIO_pins_define */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins. uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode_define */ This parameter can be a value of @ref GPIO_mode_define */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull_define */ This parameter can be a value of @ref GPIO_pull_define */
uint32_t Speed; /*!< Specifies the speed for the selected pins. uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed_define */ This parameter can be a value of @ref GPIO_speed_define */
} GPIO_InitTypeDef; } GPIO_InitTypeDef;
/** /**
* @brief GPIO Bit SET and Bit RESET enumeration * @brief GPIO Bit SET and Bit RESET enumeration
*/ */
typedef enum typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState;
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
} GPIO_PinState;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{ * @{
*/ */
/** @defgroup GPIO_pins_define GPIO pins define /** @defgroup GPIO_pins_define GPIO pins define
* @{ * @{
*/ */
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ #define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
/** /**
* @} * @}
*/ */
/** @defgroup GPIO_mode_define GPIO mode define /** @defgroup GPIO_mode_define GPIO mode define
* @brief GPIO Configuration Mode * @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ * Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode * - X : GPIO mode or EXTI Mode
* - y : External IT or Event trigger detection * - y : External IT or Event trigger detection
* - z : IO configuration on External IT or Event * - z : IO configuration on External IT or Event
* - Y : Output type (Push Pull or Open Drain) * - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, Alternate or Analog) * - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{ * @{
*/ */
#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */ #define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */ #define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */ #define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */
#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */ #define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
/** /**
* @} * @}
*/ */
/** @defgroup GPIO_speed_define GPIO speed define /** @defgroup GPIO_speed_define GPIO speed define
* @brief GPIO Output Maximum frequency * @brief GPIO Output Maximum frequency
* @{ * @{
*/ */
#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */
/** /**
* @} * @}
*/ */
/** @defgroup GPIO_pull_define GPIO pull define /** @defgroup GPIO_pull_define GPIO pull define
* @brief GPIO Pull-Up or Pull-Down Activation * @brief GPIO Pull-Up or Pull-Down Activation
* @{ * @{
*/ */
#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ #define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ #define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ #define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{ * @{
*/ */
/** /**
* @brief Checks whether the specified EXTI line flag is set or not. * @brief Checks whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__: specifies the EXTI line flag to check. * @param __EXTI_LINE__: specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15) * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET). * @retval The new state of __EXTI_LINE__ (SET or RESET).
*/ */
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/** /**
* @brief Clears the EXTI's line pending flags. * @brief Clears the EXTI's line pending flags.
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear. * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None * @retval None
*/ */
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/** /**
* @brief Checks whether the specified EXTI line is asserted or not. * @brief Checks whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check. * @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15) * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET). * @retval The new state of __EXTI_LINE__ (SET or RESET).
*/ */
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/** /**
* @brief Clears the EXTI's line pending bits. * @brief Clears the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear. * @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None * @retval None
*/ */
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/** /**
* @brief Generates a Software interrupt on selected EXTI line. * @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the EXTI line to check. * @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15) * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None * @retval None
*/ */
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
/** /**
* @} * @}
*/ */
/* Include GPIO HAL Extension module */ /* Include GPIO HAL Extension module */
#include "stm32f1xx_hal_gpio_ex.h" #include "stm32f1xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions /** @addtogroup GPIO_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup GPIO_Exported_Functions_Group1 /** @addtogroup GPIO_Exported_Functions_Group1
* @{ * @{
*/ */
/* Initialization and de-initialization functions *****************************/ /* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/** /**
* @} * @}
*/ */
/** @addtogroup GPIO_Exported_Functions_Group2 /** @addtogroup GPIO_Exported_Functions_Group2
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants /** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros /** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{ * @{
*/ */
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_PIN(PIN) ((((PIN)&GPIO_PIN_MASK) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ #define IS_GPIO_MODE(MODE) \
((MODE) == GPIO_MODE_OUTPUT_PP) ||\ (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) \
((MODE) == GPIO_MODE_OUTPUT_OD) ||\ || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) \
((MODE) == GPIO_MODE_AF_PP) ||\ || ((MODE) == GPIO_MODE_ANALOG))
((MODE) == GPIO_MODE_AF_OD) ||\ #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
((MODE) == GPIO_MODE_IT_RISING) ||\ #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN))
((MODE) == GPIO_MODE_IT_FALLING) ||\
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING) ||\
((MODE) == GPIO_MODE_EVT_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
((PULL) == GPIO_PULLDOWN))
/** /**
* @} * @}
*/ */
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Functions GPIO Private Functions /** @defgroup GPIO_Private_Functions GPIO Private Functions
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }

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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h vendored
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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h vendored
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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h vendored
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@@ -1,37 +1,37 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_iwdg.h * @file stm32f1xx_hal_iwdg.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of IWDG HAL module. * @brief Header file of IWDG HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_IWDG_H #ifndef __STM32F1xx_HAL_IWDG_H
@@ -45,189 +45,181 @@ extern "C" {
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup IWDG /** @addtogroup IWDG
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Types IWDG Exported Types /** @defgroup IWDG_Exported_Types IWDG Exported Types
* @{ * @{
*/ */
/** /**
* @brief IWDG Init structure definition * @brief IWDG Init structure definition
*/ */
typedef struct typedef struct {
{ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
uint32_t Prescaler; /*!< Select the prescaler of the IWDG. This parameter can be a value of @ref IWDG_Prescaler */
This parameter can be a value of @ref IWDG_Prescaler */
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
} IWDG_InitTypeDef; } IWDG_InitTypeDef;
/** /**
* @brief IWDG Handle Structure definition * @brief IWDG Handle Structure definition
*/ */
typedef struct typedef struct {
{ IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
} IWDG_HandleTypeDef; } IWDG_HandleTypeDef;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
* @{ * @{
*/ */
/** @defgroup IWDG_Prescaler IWDG Prescaler /** @defgroup IWDG_Prescaler IWDG Prescaler
* @{ * @{
*/ */
#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */ #define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ #define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ #define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ #define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{ * @{
*/ */
/** /**
* @brief Enable the IWDG peripheral. * @brief Enable the IWDG peripheral.
* @param __HANDLE__ IWDG handle * @param __HANDLE__ IWDG handle
* @retval None * @retval None
*/ */
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/** /**
* @brief Reload IWDG counter with value defined in the reload register * @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR & IWDG_RLR registers disabled). * (write access to IWDG_PR & IWDG_RLR registers disabled).
* @param __HANDLE__ IWDG handle * @param __HANDLE__ IWDG handle
* @retval None * @retval None
*/ */
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/** /**
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions /** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{ * @{
*/ */
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
* @{ * @{
*/ */
/* Initialization/Start functions ********************************************/ /* Initialization/Start functions ********************************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/** /**
* @} * @}
*/ */
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @{ * @{
*/ */
/* I/O operation functions ****************************************************/ /* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Constants IWDG Private Constants /** @defgroup IWDG_Private_Constants IWDG Private Constants
* @{ * @{
*/ */
/** /**
* @brief IWDG Key Register BitMask * @brief IWDG Key Register BitMask
*/ */
#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ #define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ #define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ #define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ #define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
/** /**
* @} * @}
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Macros IWDG Private Macros /** @defgroup IWDG_Private_Macros IWDG Private Macros
* @{ * @{
*/ */
/** /**
* @brief Enable write access to IWDG_PR and IWDG_RLR registers. * @brief Enable write access to IWDG_PR and IWDG_RLR registers.
* @param __HANDLE__ IWDG handle * @param __HANDLE__ IWDG handle
* @retval None * @retval None
*/ */
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/** /**
* @brief Disable write access to IWDG_PR and IWDG_RLR registers. * @brief Disable write access to IWDG_PR and IWDG_RLR registers.
* @param __HANDLE__ IWDG handle * @param __HANDLE__ IWDG handle
* @retval None * @retval None
*/ */
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
/** /**
* @brief Check IWDG prescaler value. * @brief Check IWDG prescaler value.
* @param __PRESCALER__ IWDG prescaler value * @param __PRESCALER__ IWDG prescaler value
* @retval None * @retval None
*/ */
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ #define IS_IWDG_PRESCALER(__PRESCALER__) \
((__PRESCALER__) == IWDG_PRESCALER_8) || \ (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) \
((__PRESCALER__) == IWDG_PRESCALER_16) || \ || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128) || ((__PRESCALER__) == IWDG_PRESCALER_256))
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
/** /**
* @brief Check IWDG reload value. * @brief Check IWDG reload value.
* @param __RELOAD__ IWDG reload value * @param __RELOAD__ IWDG reload value
* @retval None * @retval None
*/ */
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }

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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h vendored
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@@ -1,345 +1,332 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_pwr.h * @file stm32f1xx_hal_pwr.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of PWR HAL module. * @brief Header file of PWR HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_PWR_H #ifndef __STM32F1xx_HAL_PWR_H
#define __STM32F1xx_HAL_PWR_H #define __STM32F1xx_HAL_PWR_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup PWR /** @addtogroup PWR
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types /** @defgroup PWR_Exported_Types PWR Exported Types
* @{ * @{
*/ */
/** /**
* @brief PWR PVD configuration structure definition * @brief PWR PVD configuration structure definition
*/ */
typedef struct typedef struct {
{ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This parameter can be a value of @ref PWR_PVD_detection_level */
This parameter can be a value of @ref PWR_PVD_detection_level */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode */
}PWR_PVDTypeDef;
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode */
} PWR_PVDTypeDef;
/** /**
* @} * @}
*/ */
/* Internal constants --------------------------------------------------------*/ /* Internal constants --------------------------------------------------------*/
/** @addtogroup PWR_Private_Constants /** @addtogroup PWR_Private_Constants
* @{ * @{
*/ */
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants /** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{ * @{
*/ */
/** @defgroup PWR_PVD_detection_level PWR PVD detection level /** @defgroup PWR_PVD_detection_level PWR PVD detection level
* @{ * @{
*/ */
#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
/** /**
* @} * @}
*/ */
/** @defgroup PWR_PVD_Mode PWR PVD Mode /** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{ * @{
*/ */
#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
/** /**
* @} * @}
*/ */
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{ * @{
*/ */
#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
/** /**
* @} * @}
*/ */
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{ * @{
*/ */
#define PWR_MAINREGULATOR_ON 0x00000000U #define PWR_MAINREGULATOR_ON 0x00000000U
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
/** /**
* @} * @}
*/ */
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{ * @{
*/ */
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
/** /**
* @} * @}
*/ */
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{ * @{
*/ */
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
/** /**
* @} * @}
*/ */
/** @defgroup PWR_Flag PWR Flag /** @defgroup PWR_Flag PWR Flag
* @{ * @{
*/ */
#define PWR_FLAG_WU PWR_CSR_WUF #define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO #define PWR_FLAG_PVDO PWR_CSR_PVDO
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Macros PWR Exported Macros /** @defgroup PWR_Exported_Macros PWR Exported Macros
* @{ * @{
*/ */
/** @brief Check PWR flag is set or not. /** @brief Check PWR flag is set or not.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
* was received from the WKUP pin or from the RTC alarm * was received from the WKUP pin or from the RTC alarm
* An additional wakeup event is detected if the WKUP pin is enabled * An additional wakeup event is detected if the WKUP pin is enabled
* (by setting the EWUP bit) when the WKUP pin level is already high. * (by setting the EWUP bit) when the WKUP pin level is already high.
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
* resumed from StandBy mode. * resumed from StandBy mode.
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
* For this reason, this bit is equal to 0 after Standby or reset * For this reason, this bit is equal to 0 after Standby or reset
* until the PVDE bit is set. * until the PVDE bit is set.
* @retval The new state of __FLAG__ (TRUE or FALSE). * @retval The new state of __FLAG__ (TRUE or FALSE).
*/ */
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the PWR's pending flags. /** @brief Clear the PWR's pending flags.
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag * @arg PWR_FLAG_SB: StandBy flag
*/ */
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
/** /**
* @brief Enable interrupt on PVD Exti Line 16. * @brief Enable interrupt on PVD Exti Line 16.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Disable interrupt on PVD Exti Line 16. * @brief Disable interrupt on PVD Exti Line 16.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Enable event on PVD Exti Line 16. * @brief Enable event on PVD Exti Line 16.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Disable event on PVD Exti Line 16. * @brief Disable event on PVD Exti Line 16.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
/** /**
* @brief PVD EXTI line configuration: set falling edge trigger. * @brief PVD EXTI line configuration: set falling edge trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Disable the PVD Extended Interrupt Falling Trigger. * @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief PVD EXTI line configuration: set rising edge trigger. * @brief PVD EXTI line configuration: set rising edge trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Disable the PVD Extended Interrupt Rising Trigger. * @brief Disable the PVD Extended Interrupt Rising Trigger.
* This parameter can be: * This parameter can be:
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief PVD EXTI line configuration: set rising & falling edge trigger. * @brief PVD EXTI line configuration: set rising & falling edge trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
/** /**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* This parameter can be: * This parameter can be:
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/** /**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not. * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
* @retval EXTI PVD Line Status. * @retval EXTI PVD Line Status.
*/ */
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
/** /**
* @brief Clear the PVD EXTI flag. * @brief Clear the PVD EXTI flag.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
/** /**
* @brief Generate a Software interrupt on selected EXTI line. * @brief Generate a Software interrupt on selected EXTI line.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
/** /**
* @} * @}
*/ */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/** @defgroup PWR_Private_Macros PWR Private Macros /** @defgroup PWR_Private_Macros PWR Private Macros
* @{ * @{
*/ */
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ #define IS_PWR_PVD_LEVEL(LEVEL) \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) \
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) \
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_PVD_MODE_NORMAL))
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
/** /**
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions /** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{ * @{
*/ */
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{ * @{
*/ */
/* Initialization and de-initialization functions *******************************/ /* Initialization and de-initialization functions *******************************/
void HAL_PWR_DeInit(void); void HAL_PWR_DeInit(void);
@@ -347,12 +334,12 @@ void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void); void HAL_PWR_DisableBkUpAccess(void);
/** /**
* @} * @}
*/ */
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{ * @{
*/ */
/* Peripheral Control functions ************************************************/ /* Peripheral Control functions ************************************************/
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
@@ -374,31 +361,28 @@ void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void); void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void); void HAL_PWR_DisableSEVOnPend(void);
void HAL_PWR_PVD_IRQHandler(void); void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void); void HAL_PWR_PVDCallback(void);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32F1xx_HAL_PWR_H */ #endif /* __STM32F1xx_HAL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h vendored
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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h vendored
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@@ -1,200 +1,192 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_tim_ex.h * @file stm32f1xx_hal_tim_ex.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of TIM HAL Extension module. * @brief Header file of TIM HAL Extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_TIM_EX_H #ifndef __STM32F1xx_HAL_TIM_EX_H
#define __STM32F1xx_HAL_TIM_EX_H #define __STM32F1xx_HAL_TIM_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup TIMEx /** @addtogroup TIMEx
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIMEx Exported Types /** @defgroup TIMEx_Exported_Types TIMEx Exported Types
* @{ * @{
*/ */
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
/** typedef struct {
* @brief TIM Hall sensor Configuration Structure definition
*/
typedef struct uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
{ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef; } TIM_HallSensor_InitTypeDef;
#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#if defined (STM32F100xB) || defined (STM32F100xE) || \ /**
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \ * @brief TIM Break and Dead time configuration Structure definition
defined (STM32F105xC) || defined (STM32F107xC) */
typedef struct {
/** uint32_t OffStateRunMode; /*!< TIM off state in run mode
* @brief TIM Break and Dead time configuration Structure definition This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
*/ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
typedef struct This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
{ uint32_t LockLevel; /*!< TIM Lock level
uint32_t OffStateRunMode; /*!< TIM off state in run mode This parameter can be a value of @ref TIM_Lock_level */
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ uint32_t DeadTime; /*!< TIM dead Time
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint32_t BreakState; /*!< TIM Break State
uint32_t LockLevel; /*!< TIM Lock level This parameter can be a value of @ref TIM_Break_Input_enable_disable */
This parameter can be a value of @ref TIM_Lock_level */ uint32_t BreakPolarity; /*!< TIM Break input polarity
uint32_t DeadTime; /*!< TIM dead Time This parameter can be a value of @ref TIM_Break_Polarity */
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
uint32_t BreakState; /*!< TIM Break State This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
uint32_t BreakPolarity; /*!< TIM Break input polarity
This parameter can be a value of @ref TIM_Break_Polarity */
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BreakDeadTimeConfigTypeDef; } TIM_BreakDeadTimeConfigTypeDef;
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */ /* defined(STM32F105xC) || defined(STM32F107xC) */
/** /**
* @brief TIM Master configuration Structure definition * @brief TIM Master configuration Structure definition
*/ */
typedef struct { typedef struct {
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection */ This parameter can be a value of @ref TIM_Master_Mode_Selection */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection uint32_t MasterSlaveMode; /*!< Master/slave mode selection
This parameter can be a value of @ref TIM_Master_Slave_Mode */ This parameter can be a value of @ref TIM_Master_Slave_Mode */
}TIM_MasterConfigTypeDef; } TIM_MasterConfigTypeDef;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
* @{ * @{
*/ */
/** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter /** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter
* @{ * @{
*/ */
#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */ #define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */ /* defined(STM32F105xC) || defined(STM32F107xC) */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** /**
* @brief Sets the TIM Output compare preload. * @brief Sets the TIM Output compare preload.
* @param __HANDLE__: TIM handle. * @param __HANDLE__: TIM handle.
* @param __CHANNEL__: TIM Channels to be configured. * @param __CHANNEL__: TIM Channels to be configured.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval None * @retval None
*/ */
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ (((__CHANNEL__) == TIM_CHANNEL_1) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
/** /**
* @brief Resets the TIM Output compare preload. * @brief Resets the TIM Output compare preload.
* @param __HANDLE__: TIM handle. * @param __HANDLE__: TIM handle.
* @param __CHANNEL__: TIM Channels to be configured. * @param __CHANNEL__: TIM Channels to be configured.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval None * @retval None
*/ */
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) \
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) : ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions /** @addtogroup TIMEx_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group1 /** @addtogroup TIMEx_Exported_Functions_Group1
* @{ * @{
*/ */
/* Timer Hall Sensor functions **********************************************/ /* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */ /* Non-Blocking mode: Interrupt */
@@ -204,12 +196,10 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/** /**
* @} * @}
*/ */
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @addtogroup TIMEx_Exported_Functions_Group2 /** @addtogroup TIMEx_Exported_Functions_Group2
* @{ * @{
@@ -227,8 +217,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/** /**
* @} * @}
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group3 /** @addtogroup TIMEx_Exported_Functions_Group3
* @{ * @{
@@ -245,8 +235,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/** /**
* @} * @}
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group4 /** @addtogroup TIMEx_Exported_Functions_Group4
* @{ * @{
@@ -260,8 +250,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/** /**
* @} * @}
*/ */
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */ /* defined(STM32F105xC) || defined(STM32F107xC) */
@@ -270,74 +260,69 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* @{ * @{
*/ */
/* Extended Control functions ************************************************/ /* Extended Control functions ************************************************/
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
defined (STM32F105xC) || defined (STM32F107xC) HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */ /* defined(STM32F105xC) || defined(STM32F107xC) */
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
/** /**
* @} * @}
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group6 /** @addtogroup TIMEx_Exported_Functions_Group6
* @{ * @{
*/ */
/* Extension Callback *********************************************************/ /* Extension Callback *********************************************************/
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
/** /**
* @} * @}
*/ */
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @addtogroup TIMEx_Exported_Functions_Group7 /** @addtogroup TIMEx_Exported_Functions_Group7
* @{ * @{
*/ */
/* Extension Peripheral State functions **************************************/ /* Extension Peripheral State functions **************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/** /**
* @} * @}
*/ */
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */ /* defined(STM32F105xC) || defined(STM32F107xC) */
/** /**
* @} * @}
*/ */
/* End of exported functions -------------------------------------------------*/ /* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/ /* Private functions----------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{ * @{
*/ */
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
/* End of private functions --------------------------------------------------*/ /* End of private functions --------------------------------------------------*/
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32F1xx_HAL_TIM_EX_H */ #endif /* __STM32F1xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

570
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c vendored
View File

@@ -52,13 +52,13 @@
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup HAL HAL /** @defgroup HAL HAL
* @brief HAL module driver. * @brief HAL module driver.
* @{ * @{
*/ */
#ifdef HAL_MODULE_ENABLED #ifdef HAL_MODULE_ENABLED
@@ -66,44 +66,41 @@
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/** @defgroup HAL_Private_Constants HAL Private Constants /** @defgroup HAL_Private_Constants HAL Private Constants
* @{ * @{
*/ */
/** /**
* @brief STM32F1xx HAL Driver version number V1.1.3 * @brief STM32F1xx HAL Driver version number V1.1.3
*/ */
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ #define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32F1xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32F1xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\ #define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24) | (__STM32F1xx_HAL_VERSION_SUB1 << 16) | (__STM32F1xx_HAL_VERSION_SUB2 << 8) | (__STM32F1xx_HAL_VERSION_RC))
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
|(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
|(__STM32F1xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK 0x00000FFFU #define IDCODE_DEVID_MASK 0x00000FFFU
/** /**
* @} * @}
*/ */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/** @defgroup HAL_Private_Variables HAL Private Variables /** @defgroup HAL_Private_Variables HAL Private Variables
* @{ * @{
*/ */
__IO uint32_t uwTick; __IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/** /**
* @} * @}
*/ */
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/
/** @defgroup HAL_Exported_Functions HAL Exported Functions /** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{ * @{
*/ */
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions * @brief Initialization and de-initialization functions
@@ -139,30 +136,27 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
*/ */
/** /**
* @brief This function is used to initialize the HAL Library; it must be the first * @brief This function is used to initialize the HAL Library; it must be the first
* instruction to be executed in the main program (before to call any other * instruction to be executed in the main program (before to call any other
* HAL function), it performs the following: * HAL function), it performs the following:
* Configure the Flash prefetch. * Configure the Flash prefetch.
* Configures the SysTick to generate an interrupt each 1 millisecond, * Configures the SysTick to generate an interrupt each 1 millisecond,
* which is clocked by the HSI (at this stage, the clock is not yet * which is clocked by the HSI (at this stage, the clock is not yet
* configured and thus the system is running from the internal HSI at 16 MHz). * configured and thus the system is running from the internal HSI at 16 MHz).
* Set NVIC Group Priority to 4. * Set NVIC Group Priority to 4.
* Calls the HAL_MspInit() callback function defined in user file * Calls the HAL_MspInit() callback function defined in user file
* "stm32f1xx_hal_msp.c" to do the global low level hardware initialization * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization
* *
* @note SysTick is used as time base for the HAL_Delay() function, the application * @note SysTick is used as time base for the HAL_Delay() function, the application
* need to ensure that the SysTick time base is always set to 1 millisecond * need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation. * to have correct HAL operation.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_Init(void) HAL_StatusTypeDef HAL_Init(void) {
{
/* Configure Flash prefetch */ /* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0) #if (PREFETCH_ENABLE != 0)
#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \ #if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
defined(STM32F102x6) || defined(STM32F102xB) || \ || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */ /* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE(); __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
@@ -183,13 +177,12 @@ HAL_StatusTypeDef HAL_Init(void)
} }
/** /**
* @brief This function de-Initializes common part of the HAL and stops the systick. * @brief This function de-Initializes common part of the HAL and stops the systick.
* of time base. * of time base.
* @note This function is optional. * @note This function is optional.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DeInit(void) HAL_StatusTypeDef HAL_DeInit(void) {
{
/* Reset of all peripherals */ /* Reset of all peripherals */
__HAL_RCC_APB1_FORCE_RESET(); __HAL_RCC_APB1_FORCE_RESET();
__HAL_RCC_APB1_RELEASE_RESET(); __HAL_RCC_APB1_RELEASE_RESET();
@@ -210,59 +203,52 @@ HAL_StatusTypeDef HAL_DeInit(void)
} }
/** /**
* @brief Initialize the MSP. * @brief Initialize the MSP.
* @retval None * @retval None
*/ */
__weak void HAL_MspInit(void) __weak void HAL_MspInit(void) {
{
/* NOTE : This function should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file the HAL_MspInit could be implemented in the user file
*/ */
} }
/** /**
* @brief DeInitializes the MSP. * @brief DeInitializes the MSP.
* @retval None * @retval None
*/ */
__weak void HAL_MspDeInit(void) __weak void HAL_MspDeInit(void) {
{
/* NOTE : This function should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file the HAL_MspDeInit could be implemented in the user file
*/ */
} }
/** /**
* @brief This function configures the source of the time base. * @brief This function configures the source of the time base.
* The time source is configured to have 1ms time base with a dedicated * The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority. * Tick interrupt priority.
* @note This function is called automatically at the beginning of program after * @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base. * @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals. * It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process, * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The SysTick interrupt must have higher priority (numerically lower) * The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other * The function is declared as __weak to be overwritten in case of other
* implementation in user file. * implementation in user file.
* @param TickPriority Tick interrupt priority. * @param TickPriority Tick interrupt priority.
* @retval HAL status * @retval HAL status
*/ */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
{
/* Configure the SysTick to have interrupt in 1ms time basis*/ /* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) {
{
return HAL_ERROR; return HAL_ERROR;
} }
/* Configure the SysTick IRQ priority */ /* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS)) if (TickPriority < (1UL << __NVIC_PRIO_BITS)) {
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority; uwTickPrio = TickPriority;
} } else {
else
{
return HAL_ERROR; return HAL_ERROR;
} }
@@ -271,8 +257,8 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
} }
/** /**
* @} * @}
*/ */
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions * @brief HAL Control functions
@@ -298,50 +284,39 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
*/ */
/** /**
* @brief This function is called to increment a global variable "uwTick" * @brief This function is called to increment a global variable "uwTick"
* used as application time base. * used as application time base.
* @note In the default implementation, this variable is incremented each 1ms * @note In the default implementation, this variable is incremented each 1ms
* in SysTick ISR. * in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file. * implementations in user file.
* @retval None * @retval None
*/ */
__weak void HAL_IncTick(void) __weak void HAL_IncTick(void) { uwTick += uwTickFreq; }
{
uwTick += uwTickFreq;
}
/** /**
* @brief Provides a tick value in millisecond. * @brief Provides a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file. * implementations in user file.
* @retval tick value * @retval tick value
*/ */
__weak uint32_t HAL_GetTick(void) __weak uint32_t HAL_GetTick(void) { return uwTick; }
{
return uwTick;
}
/** /**
* @brief This function returns a tick priority. * @brief This function returns a tick priority.
* @retval tick priority * @retval tick priority
*/ */
uint32_t HAL_GetTickPrio(void) uint32_t HAL_GetTickPrio(void) { return uwTickPrio; }
{
return uwTickPrio;
}
/** /**
* @brief Set new tick Freq. * @brief Set new tick Freq.
* @retval Status * @retval Status
*/ */
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) {
{ HAL_StatusTypeDef status = HAL_OK;
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_TICKFREQ(Freq)); assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq) if (uwTickFreq != Freq) {
{
uwTickFreq = Freq; uwTickFreq = Freq;
/* Apply the new tick Freq */ /* Apply the new tick Freq */
@@ -352,244 +327,207 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
} }
/** /**
* @brief Return tick frequency. * @brief Return tick frequency.
* @retval tick period in Hz * @retval tick period in Hz
*/ */
HAL_TickFreqTypeDef HAL_GetTickFreq(void) HAL_TickFreqTypeDef HAL_GetTickFreq(void) { return uwTickFreq; }
{
return uwTickFreq;
}
/** /**
* @brief This function provides minimum delay (in milliseconds) based * @brief This function provides minimum delay (in milliseconds) based
* on variable incremented. * on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base. * @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick * It is used to generate interrupts at regular time intervals where uwTick
* is incremented. * is incremented.
* @note This function is declared as __weak to be overwritten in case of other * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file. * implementations in user file.
* @param Delay specifies the delay time length, in milliseconds. * @param Delay specifies the delay time length, in milliseconds.
* @retval None * @retval None
*/ */
__weak void HAL_Delay(uint32_t Delay) __weak void HAL_Delay(uint32_t Delay) {
{
uint32_t tickstart = HAL_GetTick(); uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay; uint32_t wait = Delay;
/* Add a freq to guarantee minimum wait */ /* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY) if (wait < HAL_MAX_DELAY) {
{
wait += (uint32_t)(uwTickFreq); wait += (uint32_t)(uwTickFreq);
} }
while ((HAL_GetTick() - tickstart) < wait) while ((HAL_GetTick() - tickstart) < wait) {}
{
}
} }
/** /**
* @brief Suspend Tick increment. * @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is * @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick() * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the SysTick interrupt will be disabled and so Tick increment * is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended. * is suspended.
* @note This function is declared as __weak to be overwritten in case of other * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file. * implementations in user file.
* @retval None * @retval None
*/ */
__weak void HAL_SuspendTick(void) __weak void HAL_SuspendTick(void) {
{
/* Disable SysTick Interrupt */ /* Disable SysTick Interrupt */
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
} }
/** /**
* @brief Resume Tick increment. * @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is * @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick() * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the SysTick interrupt will be enabled and so Tick increment * is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed. * is resumed.
* @note This function is declared as __weak to be overwritten in case of other * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file. * implementations in user file.
* @retval None * @retval None
*/ */
__weak void HAL_ResumeTick(void) __weak void HAL_ResumeTick(void) {
{
/* Enable SysTick Interrupt */ /* Enable SysTick Interrupt */
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
} }
/** /**
* @brief Returns the HAL revision * @brief Returns the HAL revision
* @retval version 0xXYZR (8bits for each decimal, R for RC) * @retval version 0xXYZR (8bits for each decimal, R for RC)
*/ */
uint32_t HAL_GetHalVersion(void) uint32_t HAL_GetHalVersion(void) { return __STM32F1xx_HAL_VERSION; }
{
return __STM32F1xx_HAL_VERSION;
}
/** /**
* @brief Returns the device revision identifier. * @brief Returns the device revision identifier.
* Note: On devices STM32F10xx8 and STM32F10xxB, * Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G * STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6 * STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode). * debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* @retval Device revision identifier * @retval Device revision identifier
*/ */
uint32_t HAL_GetREVID(void) uint32_t HAL_GetREVID(void) { return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); }
{
return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos);
}
/** /**
* @brief Returns the device identifier. * @brief Returns the device identifier.
* Note: On devices STM32F10xx8 and STM32F10xxB, * Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G * STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6 * STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode). * debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* @retval Device identifier * @retval Device identifier
*/ */
uint32_t HAL_GetDEVID(void) uint32_t HAL_GetDEVID(void) { return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); }
{
return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
}
/** /**
* @brief Enable the Debug Module during SLEEP mode * @brief Enable the Debug Module during SLEEP mode
* @retval None * @retval None
*/ */
void HAL_DBGMCU_EnableDBGSleepMode(void) void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); }
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/** /**
* @brief Disable the Debug Module during SLEEP mode * @brief Disable the Debug Module during SLEEP mode
* Note: On devices STM32F10xx8 and STM32F10xxB, * Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G * STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6 * STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode). * debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* @retval None * @retval None
*/ */
void HAL_DBGMCU_DisableDBGSleepMode(void) void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); }
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/** /**
* @brief Enable the Debug Module during STOP mode * @brief Enable the Debug Module during STOP mode
* Note: On devices STM32F10xx8 and STM32F10xxB, * Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G * STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6 * STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode). * debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* Note: On all STM32F1 devices: * Note: On all STM32F1 devices:
* If the system tick timer interrupt is enabled during the Stop mode * If the system tick timer interrupt is enabled during the Stop mode
* debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
* the system from Stop mode. * the system from Stop mode.
* Workaround: To debug the Stop mode, disable the system tick timer * Workaround: To debug the Stop mode, disable the system tick timer
* interrupt. * interrupt.
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* Note: On all STM32F1 devices: * Note: On all STM32F1 devices:
* If the system tick timer interrupt is enabled during the Stop mode * If the system tick timer interrupt is enabled during the Stop mode
* debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
* the system from Stop mode. * the system from Stop mode.
* Workaround: To debug the Stop mode, disable the system tick timer * Workaround: To debug the Stop mode, disable the system tick timer
* interrupt. * interrupt.
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* @retval None * @retval None
*/ */
void HAL_DBGMCU_EnableDBGStopMode(void) void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); }
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/** /**
* @brief Disable the Debug Module during STOP mode * @brief Disable the Debug Module during STOP mode
* Note: On devices STM32F10xx8 and STM32F10xxB, * Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G * STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6 * STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode). * debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* @retval None * @retval None
*/ */
void HAL_DBGMCU_DisableDBGStopMode(void) void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); }
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/** /**
* @brief Enable the Debug Module during STANDBY mode * @brief Enable the Debug Module during STANDBY mode
* Note: On devices STM32F10xx8 and STM32F10xxB, * Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G * STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6 * STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode). * debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* @retval None * @retval None
*/ */
void HAL_DBGMCU_EnableDBGStandbyMode(void) void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); }
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/** /**
* @brief Disable the Debug Module during STANDBY mode * @brief Disable the Debug Module during STANDBY mode
* Note: On devices STM32F10xx8 and STM32F10xxB, * Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G * STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6 * STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode). * debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* @retval None * @retval None
*/ */
void HAL_DBGMCU_DisableDBGStandbyMode(void) void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); }
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/** /**
* @brief Return the unique device identifier (UID based on 96 bits) * @brief Return the unique device identifier (UID based on 96 bits)
* @param UID pointer to 3 words array. * @param UID pointer to 3 words array.
* @retval Device identifier * @retval Device identifier
*/ */
void HAL_GetUID(uint32_t *UID) void HAL_GetUID(uint32_t *UID) {
{
UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE))); UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
} }
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#endif /* HAL_MODULE_ENABLED */ #endif /* HAL_MODULE_ENABLED */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c vendored
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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c vendored
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source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c vendored
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@@ -3,43 +3,43 @@
* @file stm32f1xx_hal_cortex.c * @file stm32f1xx_hal_cortex.c
* @author MCD Application Team * @author MCD Application Team
* @brief CORTEX HAL module driver. * @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the CORTEX: * functionalities of the CORTEX:
* + Initialization and de-initialization functions * + Initialization and de-initialization functions
* + Peripheral Control functions * + Peripheral Control functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### How to use this driver ##### ##### How to use this driver #####
============================================================================== ==============================================================================
[..] [..]
*** How to configure Interrupts using CORTEX HAL driver *** *** How to configure Interrupts using CORTEX HAL driver ***
=========================================================== ===========================================================
[..] [..]
This section provides functions allowing to configure the NVIC interrupts (IRQ). This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M3 exceptions are managed by CMSIS functions. The Cortex-M3 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
function according to the following table. function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programming manual for details in how to configure priority. (#) please refer to programming manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority. The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority): -@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest preemption priority (+@) Lowest preemption priority
(+@) Lowest sub priority (+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number) (+@) Lowest hardware priority (IRQ number)
[..] [..]
*** How to configure Systick using CORTEX HAL driver *** *** How to configure Systick using CORTEX HAL driver ***
======================================================== ========================================================
[..] [..]
Setup SysTick Timer for time base. Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
is a CMSIS function that: is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter. (++) Configures the SysTick Reload register with value passed as function parameter.
@@ -48,22 +48,22 @@
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt. (++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter. (++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
inside the stm32f1xx_hal_cortex.h file. inside the stm32f1xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the (+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula: (+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF (++) Reload Value should not exceed 0xFFFFFF
@endverbatim @endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
@@ -99,13 +99,13 @@
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup CORTEX CORTEX /** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver * @brief CORTEX HAL module driver
* @{ * @{
*/ */
#ifdef HAL_CORTEX_MODULE_ENABLED #ifdef HAL_CORTEX_MODULE_ENABLED
@@ -117,91 +117,86 @@
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{ * @{
*/ */
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions * @brief Initialization and Configuration functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### Initialization and de-initialization functions ##### ##### Initialization and de-initialization functions #####
============================================================================== ==============================================================================
[..] [..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts This section provides the CORTEX HAL driver functions allowing to configure Interrupts
Systick functionalities Systick functionalities
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Sets the priority grouping field (preemption priority and subpriority) * @brief Sets the priority grouping field (preemption priority and subpriority)
* using the required unlock sequence. * using the required unlock sequence.
* @param PriorityGroup: The priority grouping bits length. * @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority * 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority * 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority * 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority * 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority * 0 bits for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority. * The pending IRQ priority will be managed only by the subpriority.
* @retval None * @retval None
*/ */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup); NVIC_SetPriorityGrouping(PriorityGroup);
} }
/** /**
* @brief Sets the priority of an interrupt. * @brief Sets the priority of an interrupt.
* @param IRQn: External interrupt number. * @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h)) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))
* @param PreemptPriority: The preemption priority for the IRQn channel. * @param PreemptPriority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 15 * This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority * A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel. * @param SubPriority: the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15 * This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority. * A lower priority value indicates a higher priority.
* @retval None * @retval None
*/ */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) {
{
uint32_t prioritygroup = 0x00U; uint32_t prioritygroup = 0x00U;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping(); prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
} }
/** /**
* @brief Enables a device specific interrupt in the NVIC interrupt controller. * @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before. * function should be called before.
* @param IRQn External interrupt number. * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None * @retval None
*/ */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
@@ -210,14 +205,13 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
} }
/** /**
* @brief Disables a device specific interrupt in the NVIC interrupt controller. * @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number. * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None * @retval None
*/ */
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
@@ -226,95 +220,88 @@ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
} }
/** /**
* @brief Initiates a system reset request to reset the MCU. * @brief Initiates a system reset request to reset the MCU.
* @retval None * @retval None
*/ */
void HAL_NVIC_SystemReset(void) void HAL_NVIC_SystemReset(void) {
{
/* System Reset */ /* System Reset */
NVIC_SystemReset(); NVIC_SystemReset();
} }
/** /**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts. * Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded. * @retval status: - 0 Function succeeded.
* - 1 Function failed. * - 1 Function failed.
*/ */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); }
{
return SysTick_Config(TicksNumb);
}
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions * @brief Cortex control functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### Peripheral Control functions ##### ##### Peripheral Control functions #####
============================================================================== ==============================================================================
[..] [..]
This subsection provides a set of functions allowing to control the CORTEX This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities. (NVIC, SYSTICK, MPU) functionalities.
@endverbatim @endverbatim
* @{ * @{
*/ */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
/** /**
* @brief Disables the MPU * @brief Disables the MPU
* @retval None * @retval None
*/ */
void HAL_MPU_Disable(void) void HAL_MPU_Disable(void) {
{
/* Make sure outstanding transfers are done */ /* Make sure outstanding transfers are done */
__DMB(); __DMB();
/* Disable fault exceptions */ /* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU and clear the control register*/ /* Disable the MPU and clear the control register*/
MPU->CTRL = 0U; MPU->CTRL = 0U;
} }
/** /**
* @brief Enable the MPU. * @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault, * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory * NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI * @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF * @arg MPU_HFNMI_PRIVDEF
* @retval None * @retval None
*/ */
void HAL_MPU_Enable(uint32_t MPU_Control) void HAL_MPU_Enable(uint32_t MPU_Control) {
{
/* Enable the MPU */ /* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */ /* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU setting take effects */ /* Ensure MPU setting take effects */
__DSB(); __DSB();
__ISB(); __ISB();
} }
/** /**
* @brief Initializes and configures the Region and the memory to be protected. * @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information. * the initialization and configuration information.
* @retval None * @retval None
*/ */
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
@@ -322,8 +309,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
/* Set the Region number */ /* Set the Region number */
MPU->RNR = MPU_Init->Number; MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != RESET) if ((MPU_Init->Enable) != RESET) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
@@ -333,20 +319,12 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress; MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos)
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | | ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos)
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | | ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | } else {
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00U; MPU->RBAR = 0x00U;
MPU->RASR = 0x00U; MPU->RASR = 0x00U;
} }
@@ -354,71 +332,67 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @brief Gets the priority grouping field from the NVIC Interrupt Controller. * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/ */
uint32_t HAL_NVIC_GetPriorityGrouping(void) uint32_t HAL_NVIC_GetPriorityGrouping(void) {
{
/* Get the PRIGROUP[10:8] field value */ /* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping(); return NVIC_GetPriorityGrouping();
} }
/** /**
* @brief Gets the priority of an interrupt. * @brief Gets the priority of an interrupt.
* @param IRQn: External interrupt number. * @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @param PriorityGroup: the priority grouping bits length. * @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority * 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority * 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority * 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority * 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority * 0 bits for subpriority
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority: Pointer on the Subpriority value (starting from 0). * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
* @retval None * @retval None
*/ */
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */ /* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
} }
/** /**
* @brief Sets Pending bit of an external interrupt. * @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number * @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None * @retval None
*/ */
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */ /* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn); NVIC_SetPendingIRQ(IRQn);
} }
/** /**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC * @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt). * and returns the pending bit for the specified interrupt).
* @param IRQn External interrupt number. * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval status: - 0 Interrupt status is not pending. * @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending. * - 1 Interrupt status is pending.
*/ */
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
@@ -427,14 +401,13 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
} }
/** /**
* @brief Clears the pending bit of an external interrupt. * @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number. * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None * @retval None
*/ */
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
@@ -443,15 +416,14 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
} }
/** /**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number * @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval status: - 0 Interrupt status is not pending. * @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending. * - 1 Interrupt status is pending.
*/ */
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
@@ -460,62 +432,54 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
} }
/** /**
* @brief Configures the SysTick clock source. * @brief Configures the SysTick clock source.
* @param CLKSource: specifies the SysTick clock source. * @param CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None * @retval None
*/ */
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
if (CLKSource == SYSTICK_CLKSOURCE_HCLK) if (CLKSource == SYSTICK_CLKSOURCE_HCLK) {
{
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
} } else {
else
{
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
} }
} }
/** /**
* @brief This function handles SYSTICK interrupt request. * @brief This function handles SYSTICK interrupt request.
* @retval None * @retval None
*/ */
void HAL_SYSTICK_IRQHandler(void) void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); }
{
HAL_SYSTICK_Callback();
}
/** /**
* @brief SYSTICK callback. * @brief SYSTICK callback.
* @retval None * @retval None
*/ */
__weak void HAL_SYSTICK_Callback(void) __weak void HAL_SYSTICK_Callback(void) {
{
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file the HAL_SYSTICK_Callback could be implemented in the user file
*/ */
} }
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#endif /* HAL_CORTEX_MODULE_ENABLED */ #endif /* HAL_CORTEX_MODULE_ENABLED */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

579
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c vendored
View File

@@ -14,7 +14,7 @@
============================================================================== ==============================================================================
[..] [..]
(#) Enable and configure the peripheral to be connected to the DMA Channel (#) Enable and configure the peripheral to be connected to the DMA Channel
(except for internal SRAM / FLASH memories: no initialization is (except for internal SRAM / FLASH memories: no initialization is
necessary). Please refer to the Reference manual for connection between peripherals necessary). Please refer to the Reference manual for connection between peripherals
and DMA requests. and DMA requests.
@@ -23,11 +23,11 @@
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
using HAL_DMA_Init() function. using HAL_DMA_Init() function.
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection. detection.
(#) Use HAL_DMA_Abort() function to abort the current transfer (#) Use HAL_DMA_Abort() function to abort the current transfer
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed. -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
*** Polling mode IO operation *** *** Polling mode IO operation ***
================================= =================================
@@ -51,7 +51,7 @@
XferErrorCallback (i.e. a member of DMA handle structure). XferErrorCallback (i.e. a member of DMA handle structure).
*** DMA HAL driver macros list *** *** DMA HAL driver macros list ***
============================================= =============================================
[..] [..]
Below the list of most used macros in DMA HAL driver. Below the list of most used macros in DMA HAL driver.
@@ -61,10 +61,10 @@
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
[..] [..]
(@) You can refer to the DMA HAL driver header file for more useful macros (@) You can refer to the DMA HAL driver header file for more useful macros
@endverbatim @endverbatim
****************************************************************************** ******************************************************************************
@@ -101,13 +101,13 @@
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup DMA DMA /** @defgroup DMA DMA
* @brief DMA HAL module driver * @brief DMA HAL module driver
* @{ * @{
*/ */
#ifdef HAL_DMA_MODULE_ENABLED #ifdef HAL_DMA_MODULE_ENABLED
@@ -117,21 +117,21 @@
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
/** @defgroup DMA_Private_Functions DMA Private Functions /** @defgroup DMA_Private_Functions DMA Private Functions
* @{ * @{
*/ */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/** /**
* @} * @}
*/ */
/* Exported functions ---------------------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/
/** @defgroup DMA_Exported_Functions DMA Exported Functions /** @defgroup DMA_Exported_Functions DMA Exported Functions
* @{ * @{
*/ */
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions * @brief Initialization and de-initialization functions
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
@@ -139,30 +139,28 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
=============================================================================== ===============================================================================
[..] [..]
This section provides functions allowing to initialize the DMA Channel source This section provides functions allowing to initialize the DMA Channel source
and destination addresses, incrementation and data sizes, transfer direction, and destination addresses, incrementation and data sizes, transfer direction,
circular/normal mode selection, memory-to-memory mode selection and Channel priority value. circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
[..] [..]
The HAL_DMA_Init() function follows the DMA configuration procedures as described in The HAL_DMA_Init() function follows the DMA configuration procedures as described in
reference manual. reference manual.
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Initialize the DMA according to the specified * @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and initialize the associated handle. * parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) {
{
uint32_t tmp = 0U; uint32_t tmp = 0U;
/* Check the DMA handle allocation */ /* Check the DMA handle allocation */
if(hdma == NULL) if (hdma == NULL) {
{
return HAL_ERROR; return HAL_ERROR;
} }
@@ -176,23 +174,20 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC) #if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F100xE) || defined(STM32F105xC) || defined(STM32F107xC)
/* calculation of the channel index */ /* calculation of the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
{
/* DMA1 */ /* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
hdma->DmaBaseAddress = DMA1; hdma->DmaBaseAddress = DMA1;
} } else {
else
{
/* DMA2 */ /* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2; hdma->DmaBaseAddress = DMA2;
} }
#else #else
/* DMA1 */ /* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
hdma->DmaBaseAddress = DMA1; hdma->DmaBaseAddress = DMA1;
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */ #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
@@ -203,15 +198,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
tmp = hdma->Instance->CCR; tmp = hdma->Instance->CCR;
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ tmp &= ((uint32_t) ~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR));
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */ /* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction | tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority;
hdma->Init.PeriphInc | hdma->Init.MemInc |
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
hdma->Init.Mode | hdma->Init.Priority;
/* Write to DMA Channel CR register */ /* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp; hdma->Instance->CCR = tmp;
@@ -228,16 +218,14 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
} }
/** /**
* @brief DeInitialize the DMA peripheral. * @brief DeInitialize the DMA peripheral.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) {
{
/* Check the DMA handle allocation */ /* Check the DMA handle allocation */
if(hdma == NULL) if (hdma == NULL) {
{
return HAL_ERROR; return HAL_ERROR;
} }
@@ -248,34 +236,31 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE(hdma); __HAL_DMA_DISABLE(hdma);
/* Reset DMA Channel control register */ /* Reset DMA Channel control register */
hdma->Instance->CCR = 0U; hdma->Instance->CCR = 0U;
/* Reset DMA Channel Number of Data to Transfer register */ /* Reset DMA Channel Number of Data to Transfer register */
hdma->Instance->CNDTR = 0U; hdma->Instance->CNDTR = 0U;
/* Reset DMA Channel peripheral address register */ /* Reset DMA Channel peripheral address register */
hdma->Instance->CPAR = 0U; hdma->Instance->CPAR = 0U;
/* Reset DMA Channel memory address register */ /* Reset DMA Channel memory address register */
hdma->Instance->CMAR = 0U; hdma->Instance->CMAR = 0U;
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC) #if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F100xE) || defined(STM32F105xC) || defined(STM32F107xC)
/* calculation of the channel index */ /* calculation of the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
{
/* DMA1 */ /* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
hdma->DmaBaseAddress = DMA1; hdma->DmaBaseAddress = DMA1;
} } else {
else
{
/* DMA2 */ /* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2; hdma->DmaBaseAddress = DMA2;
} }
#else #else
/* DMA1 */ /* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
hdma->DmaBaseAddress = DMA1; hdma->DmaBaseAddress = DMA1;
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */ #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
@@ -283,10 +268,10 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
/* Clean all callbacks */ /* Clean all callbacks */
hdma->XferCpltCallback = NULL; hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL; hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL; hdma->XferAbortCallback = NULL;
/* Reset the error code */ /* Reset the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE; hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -301,8 +286,8 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
} }
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
* @brief Input and Output operation functions * @brief Input and Output operation functions
@@ -324,16 +309,15 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
*/ */
/** /**
* @brief Start the DMA Transfer. * @brief Start the DMA Transfer.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address * @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address * @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination * @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
{
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */ /* Check the parameters */
@@ -342,41 +326,37 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
/* Process locked */ /* Process locked */
__HAL_LOCK(hdma); __HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State) if (HAL_DMA_STATE_READY == hdma->State) {
{
/* Change DMA peripheral state */ /* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY; hdma->State = HAL_DMA_STATE_BUSY;
hdma->ErrorCode = HAL_DMA_ERROR_NONE; hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */ /* Disable the peripheral */
__HAL_DMA_DISABLE(hdma); __HAL_DMA_DISABLE(hdma);
/* Configure the source, destination address and the data length & clear flags*/ /* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma); __HAL_DMA_ENABLE(hdma);
} else {
/* Process Unlocked */
__HAL_UNLOCK(hdma);
status = HAL_BUSY;
} }
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
status = HAL_BUSY;
}
return status; return status;
} }
/** /**
* @brief Start the DMA Transfer with interrupt enabled. * @brief Start the DMA Transfer with interrupt enabled.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address * @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address * @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination * @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
{
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */ /* Check the parameters */
@@ -384,61 +364,54 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/* Process locked */ /* Process locked */
__HAL_LOCK(hdma); __HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State) if (HAL_DMA_STATE_READY == hdma->State) {
{
/* Change DMA peripheral state */ /* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY; hdma->State = HAL_DMA_STATE_BUSY;
hdma->ErrorCode = HAL_DMA_ERROR_NONE; hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */ /* Disable the peripheral */
__HAL_DMA_DISABLE(hdma); __HAL_DMA_DISABLE(hdma);
/* Configure the source, destination address and the data length & clear flags*/ /* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the transfer complete interrupt */ /* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */ /* Enable the transfer Error interrupt */
if(NULL != hdma->XferHalfCpltCallback) if (NULL != hdma->XferHalfCpltCallback) {
{
/* Enable the Half transfer complete interrupt as well */ /* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
} } else {
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
} }
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma); __HAL_DMA_ENABLE(hdma);
} } else {
else
{
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
/* Remain BUSY */ /* Remain BUSY */
status = HAL_BUSY; status = HAL_BUSY;
} }
return status; return status;
} }
/** /**
* @brief Abort the DMA Transfer. * @brief Abort the DMA Transfer.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) {
{
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Disable DMA IT */ /* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Disable the channel */ /* Disable the channel */
__HAL_DMA_DISABLE(hdma); __HAL_DMA_DISABLE(hdma);
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
@@ -446,30 +419,26 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
hdma->State = HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
return status; return status;
} }
/** /**
* @brief Aborts the DMA Transfer in Interrupt mode. * @brief Aborts the DMA Transfer in Interrupt mode.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) {
{
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma->State) if (HAL_DMA_STATE_BUSY != hdma->State) {
{
/* no transfer ongoing */ /* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
status = HAL_ERROR; status = HAL_ERROR;
} } else {
else
{
/* Disable DMA IT */ /* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
@@ -486,29 +455,26 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
/* Call User Abort callback */ /* Call User Abort callback */
if(hdma->XferAbortCallback != NULL) if (hdma->XferAbortCallback != NULL) {
{
hdma->XferAbortCallback(hdma); hdma->XferAbortCallback(hdma);
} }
} }
return status; return status;
} }
/** /**
* @brief Polling for transfer complete. * @brief Polling for transfer complete.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param CompleteLevel: Specifies the DMA level complete. * @param CompleteLevel: Specifies the DMA level complete.
* @param Timeout: Timeout duration. * @param Timeout: Timeout duration.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) {
{
uint32_t temp; uint32_t temp;
uint32_t tickstart = 0U; uint32_t tickstart = 0U;
if(HAL_DMA_STATE_BUSY != hdma->State) if (HAL_DMA_STATE_BUSY != hdma->State) {
{
/* no transfer ongoing */ /* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
@@ -516,20 +482,16 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
} }
/* Polling mode not supported in circular mode */ /* Polling mode not supported in circular mode */
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) {
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR; return HAL_ERROR;
} }
/* Get the level transfer complete flag */ /* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER) if (CompleteLevel == HAL_DMA_FULL_TRANSFER) {
{
/* Transfer Complete flag */ /* Transfer Complete flag */
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
} } else {
else
{
/* Half Transfer Complete flag */ /* Half Transfer Complete flag */
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
} }
@@ -537,10 +499,8 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
/* Get tick */ /* Get tick */
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) while (__HAL_DMA_GET_FLAG(hdma, temp) == RESET) {
{ if ((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) {
if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
{
/* When a DMA transfer error occurs */ /* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */ /* A hardware clear of its EN bits is performed */
/* Clear all flags */ /* Clear all flags */
@@ -550,7 +510,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
/* Change the DMA state */ /* Change the DMA state */
hdma->State= HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
@@ -558,10 +518,8 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
return HAL_ERROR; return HAL_ERROR;
} }
/* Check for the Timeout */ /* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY) if (Timeout != HAL_MAX_DELAY) {
{ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update error code */ /* Update error code */
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
@@ -576,21 +534,18 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
} }
} }
if(CompleteLevel == HAL_DMA_FULL_TRANSFER) if (CompleteLevel == HAL_DMA_FULL_TRANSFER) {
{
/* Clear the transfer complete flag */ /* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
/* The selected Channelx EN bit is cleared (DMA is disabled and /* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */ all transfers are complete) */
hdma->State = HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
} } else {
else
{
/* Clear the half transfer complete flag */ /* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
} }
/* Process unlocked */ /* Process unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
@@ -598,22 +553,19 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
} }
/** /**
* @brief Handles DMA interrupt request. * @brief Handles DMA interrupt request.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval None * @retval None
*/ */
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) {
{ uint32_t flag_it = hdma->DmaBaseAddress->ISR;
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
uint32_t source_it = hdma->Instance->CCR; uint32_t source_it = hdma->Instance->CCR;
/* Half Transfer Complete Interrupt management ******************************/ /* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) {
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
{
/* Disable the half transfer interrupt */ /* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
} }
@@ -623,40 +575,35 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* DMA peripheral state is not updated in Half Transfer */ /* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */ /* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL) if (hdma->XferHalfCpltCallback != NULL) {
{
/* Half transfer callback */ /* Half transfer callback */
hdma->XferHalfCpltCallback(hdma); hdma->XferHalfCpltCallback(hdma);
} }
} }
/* Transfer Complete Interrupt management ***********************************/ /* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) {
{ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the transfer complete and error interrupt */ /* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
/* Change the DMA state */ /* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
} }
/* Clear the transfer complete flag */ /* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL) if (hdma->XferCpltCallback != NULL) {
{
/* Transfer complete callback */ /* Transfer complete callback */
hdma->XferCpltCallback(hdma); hdma->XferCpltCallback(hdma);
} }
} }
/* Transfer Error Interrupt management **************************************/ /* Transfer Error Interrupt management **************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) else if ((RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) {
{
/* When a DMA transfer error occurs */ /* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */ /* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */ /* Disable ALL DMA IT */
@@ -674,8 +621,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
if (hdma->XferErrorCallback != NULL) if (hdma->XferErrorCallback != NULL) {
{
/* Transfer error callback */ /* Transfer error callback */
hdma->XferErrorCallback(hdma); hdma->XferErrorCallback(hdma);
} }
@@ -684,119 +630,109 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
} }
/** /**
* @brief Register callbacks * @brief Register callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param CallbackID: User Callback identifer * @param CallbackID: User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback: pointer to private callbacsk function which has pointer to * @param pCallback: pointer to private callbacsk function which has pointer to
* a DMA_HandleTypeDef structure as parameter. * a DMA_HandleTypeDef structure as parameter.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma)) {
{
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Process locked */ /* Process locked */
__HAL_LOCK(hdma); __HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State) if (HAL_DMA_STATE_READY == hdma->State) {
{ switch (CallbackID) {
switch (CallbackID) case HAL_DMA_XFER_CPLT_CB_ID:
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = pCallback; hdma->XferCpltCallback = pCallback;
break; break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = pCallback;
break;
case HAL_DMA_XFER_ERROR_CB_ID: case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = pCallback;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = pCallback; hdma->XferErrorCallback = pCallback;
break; break;
case HAL_DMA_XFER_ABORT_CB_ID: case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = pCallback; hdma->XferAbortCallback = pCallback;
break; break;
default: default:
status = HAL_ERROR; status = HAL_ERROR;
break; break;
} }
} } else {
else
{
status = HAL_ERROR; status = HAL_ERROR;
} }
/* Release Lock */ /* Release Lock */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
return status; return status;
} }
/** /**
* @brief UnRegister callbacks * @brief UnRegister callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param CallbackID: User Callback identifer * @param CallbackID: User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) {
{
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Process locked */ /* Process locked */
__HAL_LOCK(hdma); __HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State) if (HAL_DMA_STATE_READY == hdma->State) {
{ switch (CallbackID) {
switch (CallbackID) case HAL_DMA_XFER_CPLT_CB_ID:
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = NULL; hdma->XferCpltCallback = NULL;
break; break;
case HAL_DMA_XFER_HALFCPLT_CB_ID: case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL;
break; break;
case HAL_DMA_XFER_ERROR_CB_ID: case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = NULL; hdma->XferErrorCallback = NULL;
break; break;
case HAL_DMA_XFER_ABORT_CB_ID: case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = NULL; hdma->XferAbortCallback = NULL;
break; break;
case HAL_DMA_XFER_ALL_CB_ID: case HAL_DMA_XFER_ALL_CB_ID:
hdma->XferCpltCallback = NULL; hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL; hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL; hdma->XferAbortCallback = NULL;
break; break;
default: default:
status = HAL_ERROR; status = HAL_ERROR;
break; break;
} }
} } else {
else
{
status = HAL_ERROR; status = HAL_ERROR;
} }
/* Release Lock */ /* Release Lock */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
return status; return status;
} }
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions * @brief Peripheral State and Errors functions
@@ -804,7 +740,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
@verbatim @verbatim
=============================================================================== ===============================================================================
##### Peripheral State and Errors functions ##### ##### Peripheral State and Errors functions #####
=============================================================================== ===============================================================================
[..] [..]
This subsection provides functions allowing to This subsection provides functions allowing to
(+) Check the DMA state (+) Check the DMA state
@@ -815,51 +751,46 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
*/ */
/** /**
* @brief Return the DMA hande state. * @brief Return the DMA hande state.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL state * @retval HAL state
*/ */
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) {
{
/* Return DMA handle state */ /* Return DMA handle state */
return hdma->State; return hdma->State;
} }
/** /**
* @brief Return the DMA error code. * @brief Return the DMA error code.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval DMA Error Code * @retval DMA Error Code
*/ */
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; }
{
return hdma->ErrorCode;
}
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup DMA_Private_Functions /** @addtogroup DMA_Private_Functions
* @{ * @{
*/ */
/** /**
* @brief Sets the DMA Transfer parameter. * @brief Sets the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address * @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address * @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination * @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status * @retval HAL status
*/ */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
{
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
@@ -867,8 +798,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
hdma->Instance->CNDTR = DataLength; hdma->Instance->CNDTR = DataLength;
/* Memory to Peripheral */ /* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) {
{
/* Configure DMA Channel destination address */ /* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress; hdma->Instance->CPAR = DstAddress;
@@ -876,8 +806,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
hdma->Instance->CMAR = SrcAddress; hdma->Instance->CMAR = SrcAddress;
} }
/* Peripheral to Memory */ /* Peripheral to Memory */
else else {
{
/* Configure DMA Channel source address */ /* Configure DMA Channel source address */
hdma->Instance->CPAR = SrcAddress; hdma->Instance->CPAR = SrcAddress;
@@ -887,16 +816,16 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
} }
/** /**
* @} * @}
*/ */
#endif /* HAL_DMA_MODULE_ENABLED */ #endif /* HAL_DMA_MODULE_ENABLED */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

705
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c vendored
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780
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c vendored
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415
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c vendored
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@@ -121,52 +121,52 @@
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup GPIO GPIO /** @defgroup GPIO GPIO
* @brief GPIO HAL module driver * @brief GPIO HAL module driver
* @{ * @{
*/ */
#ifdef HAL_GPIO_MODULE_ENABLED #ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Constants GPIO Private Constants /** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{ * @{
*/ */
#define GPIO_MODE 0x00000003U #define GPIO_MODE 0x00000003U
#define EXTI_MODE 0x10000000U #define EXTI_MODE 0x10000000U
#define GPIO_MODE_IT 0x00010000U #define GPIO_MODE_IT 0x00010000U
#define GPIO_MODE_EVT 0x00020000U #define GPIO_MODE_EVT 0x00020000U
#define RISING_EDGE 0x00100000U #define RISING_EDGE 0x00100000U
#define FALLING_EDGE 0x00200000U #define FALLING_EDGE 0x00200000U
#define GPIO_OUTPUT_TYPE 0x00000010U #define GPIO_OUTPUT_TYPE 0x00000010U
#define GPIO_NUMBER 16U #define GPIO_NUMBER 16U
/* Definitions for bit manipulation of CRL and CRH register */ /* Definitions for bit manipulation of CRL and CRH register */
#define GPIO_CR_MODE_INPUT 0x00000000U /*!< 00: Input mode (reset state) */ #define GPIO_CR_MODE_INPUT 0x00000000U /*!< 00: Input mode (reset state) */
#define GPIO_CR_CNF_ANALOG 0x00000000U /*!< 00: Analog mode */ #define GPIO_CR_CNF_ANALOG 0x00000000U /*!< 00: Analog mode */
#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004U /*!< 01: Floating input (reset state) */ #define GPIO_CR_CNF_INPUT_FLOATING 0x00000004U /*!< 01: Floating input (reset state) */
#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008U /*!< 10: Input with pull-up / pull-down */ #define GPIO_CR_CNF_INPUT_PU_PD 0x00000008U /*!< 10: Input with pull-up / pull-down */
#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U /*!< 00: General purpose output push-pull */ #define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U /*!< 00: General purpose output push-pull */
#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U /*!< 01: General purpose output Open-drain */ #define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U /*!< 01: General purpose output Open-drain */
#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U /*!< 10: Alternate function output Push-pull */ #define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U /*!< 10: Alternate function output Push-pull */
#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU /*!< 11: Alternate function output Open-drain */ #define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU /*!< 11: Alternate function output Open-drain */
/** /**
* @} * @}
*/ */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{ * @{
*/ */
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions * @brief Initialization and Configuration functions
@@ -183,23 +183,21 @@
* @{ * @{
*/ */
/** /**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral. * the configuration information for the specified GPIO peripheral.
* @retval None * @retval None
*/ */
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) {
{
uint32_t position; uint32_t position;
uint32_t ioposition = 0x00U; uint32_t ioposition = 0x00U;
uint32_t iocurrent = 0x00U; uint32_t iocurrent = 0x00U;
uint32_t temp = 0x00U; uint32_t temp = 0x00U;
uint32_t config = 0x00U; uint32_t config = 0x00U;
__IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
uint32_t registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ uint32_t registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@@ -207,93 +205,86 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */ /* Configure the port pins */
for (position = 0U; position < GPIO_NUMBER; position++) for (position = 0U; position < GPIO_NUMBER; position++) {
{
/* Get the IO position */ /* Get the IO position */
ioposition = (0x01U << position); ioposition = (0x01U << position);
/* Get the current IO position */ /* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
if (iocurrent == ioposition) if (iocurrent == ioposition) {
{
/* Check the Alternate function parameters */ /* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode) switch (GPIO_Init->Mode) {
{ /* If we are configuring the pin in OUTPUT push-pull mode */
/* If we are configuring the pin in OUTPUT push-pull mode */ case GPIO_MODE_OUTPUT_PP:
case GPIO_MODE_OUTPUT_PP: /* Check the GPIO speed parameter */
/* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; break;
break;
/* If we are configuring the pin in OUTPUT open-drain mode */ /* If we are configuring the pin in OUTPUT open-drain mode */
case GPIO_MODE_OUTPUT_OD: case GPIO_MODE_OUTPUT_OD:
/* Check the GPIO speed parameter */ /* Check the GPIO speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
break; break;
/* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
case GPIO_MODE_AF_PP: case GPIO_MODE_AF_PP:
/* Check the GPIO speed parameter */ /* Check the GPIO speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
break; break;
/* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
case GPIO_MODE_AF_OD: case GPIO_MODE_AF_OD:
/* Check the GPIO speed parameter */ /* Check the GPIO speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
break; break;
/* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
case GPIO_MODE_INPUT: case GPIO_MODE_INPUT:
case GPIO_MODE_IT_RISING: case GPIO_MODE_IT_RISING:
case GPIO_MODE_IT_FALLING: case GPIO_MODE_IT_FALLING:
case GPIO_MODE_IT_RISING_FALLING: case GPIO_MODE_IT_RISING_FALLING:
case GPIO_MODE_EVT_RISING: case GPIO_MODE_EVT_RISING:
case GPIO_MODE_EVT_FALLING: case GPIO_MODE_EVT_FALLING:
case GPIO_MODE_EVT_RISING_FALLING: case GPIO_MODE_EVT_RISING_FALLING:
/* Check the GPIO pull parameter */ /* Check the GPIO pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
if (GPIO_Init->Pull == GPIO_NOPULL) if (GPIO_Init->Pull == GPIO_NOPULL) {
{ config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; } else if (GPIO_Init->Pull == GPIO_PULLUP) {
} config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
else if (GPIO_Init->Pull == GPIO_PULLUP)
{
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
/* Set the corresponding ODR bit */ /* Set the corresponding ODR bit */
GPIOx->BSRR = ioposition; GPIOx->BSRR = ioposition;
} } else /* GPIO_PULLDOWN */
else /* GPIO_PULLDOWN */ {
{ config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
/* Reset the corresponding ODR bit */ /* Reset the corresponding ODR bit */
GPIOx->BRR = ioposition; GPIOx->BRR = ioposition;
} }
break; break;
/* If we are configuring the pin in INPUT analog mode */ /* If we are configuring the pin in INPUT analog mode */
case GPIO_MODE_ANALOG: case GPIO_MODE_ANALOG:
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break; break;
/* Parameters are checked with assert_param */ /* Parameters are checked with assert_param */
default: default:
break; break;
} }
/* Check if the current bit belongs to first half or last half of the pin count number /* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/ in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U); registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
/* Apply the new configuration of the pin to the register */ /* Apply the new configuration of the pin to the register */
@@ -301,8 +292,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/*--------------------- EXTI Mode Configuration ------------------------*/ /*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */ /* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) {
{
/* Enable AFIO Clock */ /* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE(); __HAL_RCC_AFIO_CLK_ENABLE();
temp = AFIO->EXTICR[position >> 2U]; temp = AFIO->EXTICR[position >> 2U];
@@ -310,44 +300,31 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
AFIO->EXTICR[position >> 2U] = temp; AFIO->EXTICR[position >> 2U] = temp;
/* Configure the interrupt mask */ /* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) {
{
SET_BIT(EXTI->IMR, iocurrent); SET_BIT(EXTI->IMR, iocurrent);
} } else {
else
{
CLEAR_BIT(EXTI->IMR, iocurrent); CLEAR_BIT(EXTI->IMR, iocurrent);
} }
/* Configure the event mask */ /* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) {
{
SET_BIT(EXTI->EMR, iocurrent); SET_BIT(EXTI->EMR, iocurrent);
} } else {
else
{
CLEAR_BIT(EXTI->EMR, iocurrent); CLEAR_BIT(EXTI->EMR, iocurrent);
} }
/* Enable or disable the rising trigger */ /* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) {
{
SET_BIT(EXTI->RTSR, iocurrent); SET_BIT(EXTI->RTSR, iocurrent);
} } else {
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent); CLEAR_BIT(EXTI->RTSR, iocurrent);
} }
/* Enable or disable the falling trigger */ /* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) {
{
SET_BIT(EXTI->FTSR, iocurrent); SET_BIT(EXTI->FTSR, iocurrent);
} } else {
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent); CLEAR_BIT(EXTI->FTSR, iocurrent);
} }
} }
@@ -356,36 +333,33 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
} }
/** /**
* @brief De-initializes the GPIOx peripheral registers to their default reset values. * @brief De-initializes the GPIOx peripheral registers to their default reset values.
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: specifies the port bit to be written. * @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15). * This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None * @retval None
*/ */
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) {
{ uint32_t position = 0x00U;
uint32_t position = 0x00U;
uint32_t iocurrent = 0x00U; uint32_t iocurrent = 0x00U;
uint32_t tmp = 0x00U; uint32_t tmp = 0x00U;
__IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
uint32_t registeroffset = 0U; uint32_t registeroffset = 0U;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */ /* Configure the port pins */
while ((GPIO_Pin >> position) != 0U) while ((GPIO_Pin >> position) != 0U) {
{
/* Get current io position */ /* Get current io position */
iocurrent = (GPIO_Pin) & (1U << position); iocurrent = (GPIO_Pin) & (1U << position);
if (iocurrent) if (iocurrent) {
{
/*------------------------- GPIO Mode Configuration --------------------*/ /*------------------------- GPIO Mode Configuration --------------------*/
/* Check if the current bit belongs to first half or last half of the pin count number /* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register */ in order to address CRH or CRL register */
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U); registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
/* CRL/CRH default value is floating input(0x04) shifted to correct position */ /* CRL/CRH default value is floating input(0x04) shifted to correct position */
@@ -399,8 +373,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp = AFIO->EXTICR[position >> 2U]; tmp = AFIO->EXTICR[position >> 2U];
tmp &= 0x0FU << (4U * (position & 0x03U)); tmp &= 0x0FU << (4U * (position & 0x03U));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) {
{
tmp = 0x0FU << (4U * (position & 0x03U)); tmp = 0x0FU << (4U * (position & 0x03U));
CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp); CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp);
@@ -419,8 +392,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
} }
/** /**
* @} * @}
*/ */
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief GPIO Read and Write * @brief GPIO Read and Write
@@ -437,70 +410,61 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
*/ */
/** /**
* @brief Reads the specified input port pin. * @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: specifies the port bit to read. * @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15). * This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value. * @retval The input port pin value.
*/ */
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
{
GPIO_PinState bitstatus; GPIO_PinState bitstatus;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) {
{
bitstatus = GPIO_PIN_SET; bitstatus = GPIO_PIN_SET;
} } else {
else
{
bitstatus = GPIO_PIN_RESET; bitstatus = GPIO_PIN_RESET;
} }
return bitstatus; return bitstatus;
} }
/** /**
* @brief Sets or clears the selected data port bit. * @brief Sets or clears the selected data port bit.
* *
* @note This function uses GPIOx_BSRR register to allow atomic read/modify * @note This function uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between * accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access. * the read and the modify access.
* *
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: specifies the port bit to be written. * @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15). * This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit. * @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values: * This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin * @arg GPIO_PIN_SET: to set the port pin
* @retval None * @retval None
*/ */
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState)); assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET) if (PinState != GPIO_PIN_RESET) {
{
GPIOx->BSRR = GPIO_Pin; GPIOx->BSRR = GPIO_Pin;
} } else {
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
} }
} }
/** /**
* @brief Toggles the specified GPIO pin * @brief Toggles the specified GPIO pin
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: Specifies the pins to be toggled. * @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None * @retval None
*/ */
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN(GPIO_Pin));
@@ -508,17 +472,16 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
} }
/** /**
* @brief Locks GPIO Pins configuration registers. * @brief Locks GPIO Pins configuration registers.
* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence * @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
* has been applied on a port bit, it is no longer possible to modify the value of the port bit until * has been applied on a port bit, it is no longer possible to modify the value of the port bit until
* the next reset. * the next reset.
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
* @param GPIO_Pin: specifies the port bit to be locked. * @param GPIO_Pin: specifies the port bit to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None * @retval None
*/ */
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
{
__IO uint32_t tmp = GPIO_LCKR_LCKK; __IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */ /* Check the parameters */
@@ -536,38 +499,32 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
/* Read LCKK bit*/ /* Read LCKK bit*/
tmp = GPIOx->LCKR; tmp = GPIOx->LCKR;
if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) {
{
return HAL_OK; return HAL_OK;
} } else {
else
{
return HAL_ERROR; return HAL_ERROR;
} }
} }
/** /**
* @brief This function handles EXTI interrupt request. * @brief This function handles EXTI interrupt request.
* @param GPIO_Pin: Specifies the pins connected EXTI line * @param GPIO_Pin: Specifies the pins connected EXTI line
* @retval None * @retval None
*/ */
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) {
{
/* EXTI line interrupt detected */ /* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) {
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin);
} }
} }
/** /**
* @brief EXTI line detection callbacks. * @brief EXTI line detection callbacks.
* @param GPIO_Pin: Specifies the pins connected EXTI line * @param GPIO_Pin: Specifies the pins connected EXTI line
* @retval None * @retval None
*/ */
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
{
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin); UNUSED(GPIO_Pin);
/* NOTE: This function Should not be modified, when the callback is needed, /* NOTE: This function Should not be modified, when the callback is needed,
@@ -576,20 +533,20 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
} }
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#endif /* HAL_GPIO_MODULE_ENABLED */ #endif /* HAL_GPIO_MODULE_ENABLED */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

69
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c vendored
View File

@@ -56,19 +56,19 @@
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup GPIOEx GPIOEx /** @defgroup GPIOEx GPIOEx
* @brief GPIO HAL module driver * @brief GPIO HAL module driver
* @{ * @{
*/ */
#ifdef HAL_GPIO_MODULE_ENABLED #ifdef HAL_GPIO_MODULE_ENABLED
/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
* @{ * @{
*/ */
/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions * @brief Extended features functions
@@ -87,15 +87,14 @@
*/ */
/** /**
* @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
* @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
* This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
* @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
* This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
* @retval None * @retval None
*/ */
void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) {
{
/* Verify the parameters */ /* Verify the parameters */
assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
@@ -105,39 +104,33 @@ void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource
} }
/** /**
* @brief Enables the Event Output. * @brief Enables the Event Output.
* @retval None * @retval None
*/ */
void HAL_GPIOEx_EnableEventout(void) void HAL_GPIOEx_EnableEventout(void) { SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); }
{
SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
}
/** /**
* @brief Disables the Event Output. * @brief Disables the Event Output.
* @retval None * @retval None
*/ */
void HAL_GPIOEx_DisableEventout(void) void HAL_GPIOEx_DisableEventout(void) { CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); }
{
CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
}
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#endif /* HAL_GPIO_MODULE_ENABLED */ #endif /* HAL_GPIO_MODULE_ENABLED */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

3728
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c vendored
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File diff suppressed because it is too large Load Diff

85
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c vendored
View File

@@ -103,27 +103,27 @@
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
#ifdef HAL_IWDG_MODULE_ENABLED #ifdef HAL_IWDG_MODULE_ENABLED
/** @defgroup IWDG IWDG /** @defgroup IWDG IWDG
* @brief IWDG HAL module driver. * @brief IWDG HAL module driver.
* @{ * @{
*/ */
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Defines IWDG Private Defines /** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{ * @{
*/ */
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to HSI variation, we need to wait at higher prescaler (256), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */ least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48U #define HAL_IWDG_DEFAULT_TIMEOUT 48U
/** /**
* @} * @}
*/ */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
@@ -131,8 +131,8 @@
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup IWDG_Exported_Functions /** @addtogroup IWDG_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup IWDG_Exported_Functions_Group1 /** @addtogroup IWDG_Exported_Functions_Group1
* @brief Initialization and Start functions. * @brief Initialization and Start functions.
@@ -152,20 +152,18 @@
*/ */
/** /**
* @brief Initialize the IWDG according to the specified parameters in the * @brief Initialize the IWDG according to the specified parameters in the
* IWDG_InitTypeDef and start watchdog. Before exiting function, * IWDG_InitTypeDef and start watchdog. Before exiting function,
* watchdog is refreshed in order to have correct time base. * watchdog is refreshed in order to have correct time base.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module. * the configuration information for the specified IWDG module.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) {
{
uint32_t tickstart; uint32_t tickstart;
/* Check the IWDG handle allocation */ /* Check the IWDG handle allocation */
if (hiwdg == NULL) if (hiwdg == NULL) {
{
return HAL_ERROR; return HAL_ERROR;
} }
@@ -181,17 +179,15 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
IWDG_ENABLE_WRITE_ACCESS(hiwdg); IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the Prescaler & Reload values to work with */ /* Write to IWDG registers the Prescaler & Reload values to work with */
hiwdg->Instance->PR = hiwdg->Init.Prescaler; hiwdg->Instance->PR = hiwdg->Init.Prescaler;
hiwdg->Instance->RLR = hiwdg->Init.Reload; hiwdg->Instance->RLR = hiwdg->Init.Reload;
/* Check pending flag, if previous update not done, return timeout */ /* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
/* Wait for register to be updated */ /* Wait for register to be updated */
while (hiwdg->Instance->SR != RESET) while (hiwdg->Instance->SR != RESET) {
{ if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) {
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
} }
@@ -204,8 +200,8 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
} }
/** /**
* @} * @}
*/ */
/** @addtogroup IWDG_Exported_Functions_Group2 /** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions * @brief IO operation functions
@@ -222,13 +218,12 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
*/ */
/** /**
* @brief Refresh the IWDG. * @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module. * the configuration information for the specified IWDG module.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) {
{
/* Reload IWDG counter with value defined in the reload register */ /* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg); __HAL_IWDG_RELOAD_COUNTER(hiwdg);
@@ -237,20 +232,20 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
} }
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#endif /* HAL_IWDG_MODULE_ENABLED */ #endif /* HAL_IWDG_MODULE_ENABLED */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

571
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c vendored
View File

@@ -1,55 +1,55 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_pwr.c * @file stm32f1xx_hal_pwr.c
* @author MCD Application Team * @author MCD Application Team
* @brief PWR HAL module driver. * @brief PWR HAL module driver.
* *
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral: * functionalities of the Power Controller (PWR) peripheral:
* + Initialization/de-initialization functions * + Initialization/de-initialization functions
* + Peripheral Control functions * + Peripheral Control functions
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met: * are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice, * 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. * this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, * 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation * this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution. * and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors * 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software * may be used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup PWR PWR /** @defgroup PWR PWR
* @brief PWR HAL module driver * @brief PWR HAL module driver
* @{ * @{
*/ */
#ifdef HAL_PWR_MODULE_ENABLED #ifdef HAL_PWR_MODULE_ENABLED
@@ -57,68 +57,67 @@
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/** @defgroup PWR_Private_Constants PWR Private Constants /** @defgroup PWR_Private_Constants PWR Private Constants
* @{ * @{
*/ */
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT 0x00010000U
#define PVD_MODE_EVT 0x00020000U
#define PVD_RISING_EDGE 0x00000001U
#define PVD_FALLING_EDGE 0x00000002U
/**
* @}
*/
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT 0x00010000U
#define PVD_MODE_EVT 0x00020000U
#define PVD_RISING_EDGE 0x00000001U
#define PVD_FALLING_EDGE 0x00000002U
/**
* @}
*/
/** @defgroup PWR_register_alias_address PWR Register alias address /** @defgroup PWR_register_alias_address PWR Register alias address
* @{ * @{
*/ */
/* ------------- PWR registers bit address in the alias region ---------------*/ /* ------------- PWR registers bit address in the alias region ---------------*/
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
#define PWR_CR_OFFSET 0x00U #define PWR_CR_OFFSET 0x00U
#define PWR_CSR_OFFSET 0x04U #define PWR_CSR_OFFSET 0x04U
#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
/** /**
* @} * @}
*/ */
/** @defgroup PWR_CR_register_alias PWR CR Register alias address /** @defgroup PWR_CR_register_alias PWR CR Register alias address
* @{ * @{
*/ */
/* --- CR Register ---*/ /* --- CR Register ---*/
/* Alias word address of LPSDSR bit */ /* Alias word address of LPSDSR bit */
#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos #define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))
/* Alias word address of DBP bit */ /* Alias word address of DBP bit */
#define DBP_BIT_NUMBER PWR_CR_DBP_Pos #define DBP_BIT_NUMBER PWR_CR_DBP_Pos
#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))
/* Alias word address of PVDE bit */ /* Alias word address of PVDE bit */
#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))
/** /**
* @} * @}
*/ */
/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
* @{ * @{
*/ */
/* --- CSR Register ---*/ /* --- CSR Register ---*/
/* Alias word address of EWUP1 bit */ /* Alias word address of EWUP1 bit */
#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
@@ -130,22 +129,20 @@ static void PWR_OverloadWfe(void);
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
__NOINLINE __NOINLINE
static void PWR_OverloadWfe(void) static void PWR_OverloadWfe(void) {
{ __asm volatile("wfe");
__asm volatile( "wfe" ); __asm volatile("nop");
__asm volatile( "nop" );
} }
/** /**
* @} * @}
*/ */
/** @defgroup PWR_Exported_Functions PWR Exported Functions /** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{ * @{
*/ */
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions * @brief Initialization and de-initialization functions
* *
@verbatim @verbatim
@@ -166,53 +163,50 @@ static void PWR_OverloadWfe(void)
*/ */
/** /**
* @brief Deinitializes the PWR peripheral registers to their default reset values. * @brief Deinitializes the PWR peripheral registers to their default reset values.
* @retval None * @retval None
*/ */
void HAL_PWR_DeInit(void) void HAL_PWR_DeInit(void) {
{
__HAL_RCC_PWR_FORCE_RESET(); __HAL_RCC_PWR_FORCE_RESET();
__HAL_RCC_PWR_RELEASE_RESET(); __HAL_RCC_PWR_RELEASE_RESET();
} }
/** /**
* @brief Enables access to the backup domain (RTC registers, RTC * @brief Enables access to the backup domain (RTC registers, RTC
* backup data registers ). * backup data registers ).
* @note If the HSE divided by 128 is used as the RTC clock, the * @note If the HSE divided by 128 is used as the RTC clock, the
* Backup Domain Access should be kept enabled. * Backup Domain Access should be kept enabled.
* @retval None * @retval None
*/ */
void HAL_PWR_EnableBkUpAccess(void) void HAL_PWR_EnableBkUpAccess(void) {
{
/* Enable access to RTC and backup registers */ /* Enable access to RTC and backup registers */
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; *(__IO uint32_t *)CR_DBP_BB = (uint32_t)ENABLE;
} }
/** /**
* @brief Disables access to the backup domain (RTC registers, RTC * @brief Disables access to the backup domain (RTC registers, RTC
* backup data registers). * backup data registers).
* @note If the HSE divided by 128 is used as the RTC clock, the * @note If the HSE divided by 128 is used as the RTC clock, the
* Backup Domain Access should be kept enabled. * Backup Domain Access should be kept enabled.
* @retval None * @retval None
*/ */
void HAL_PWR_DisableBkUpAccess(void) void HAL_PWR_DisableBkUpAccess(void) {
{
/* Disable access to RTC and backup registers */ /* Disable access to RTC and backup registers */
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; *(__IO uint32_t *)CR_DBP_BB = (uint32_t)DISABLE;
} }
/** /**
* @} * @}
*/ */
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @brief Low Power modes configuration functions * @brief Low Power modes configuration functions
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
##### Peripheral Control functions ##### ##### Peripheral Control functions #####
=============================================================================== ===============================================================================
*** PVD configuration *** *** PVD configuration ***
========================= =========================
[..] [..]
@@ -239,12 +233,12 @@ void HAL_PWR_DisableBkUpAccess(void)
===================================== =====================================
[..] [..]
The device features 3 low-power modes: The device features 3 low-power modes:
(+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
NVIC, SysTick, etc. are kept running NVIC, SysTick, etc. are kept running
(+) Stop mode: All clocks are stopped (+) Stop mode: All clocks are stopped
(+) Standby mode: 1.8V domain powered off (+) Standby mode: 1.8V domain powered off
*** Sleep mode *** *** Sleep mode ***
================== ==================
[..] [..]
@@ -253,7 +247,7 @@ void HAL_PWR_DisableBkUpAccess(void)
functions with functions with
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
(+) Exit: (+) Exit:
(++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) can wake up the device from Sleep mode. controller (NVIC) can wake up the device from Sleep mode.
@@ -266,7 +260,7 @@ void HAL_PWR_DisableBkUpAccess(void)
[..] [..]
The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
clock gating. The voltage regulator can be configured either in normal or low-power mode. clock gating. The voltage regulator can be configured either in normal or low-power mode.
In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
oscillators are disabled. SRAM and register contents are preserved. oscillators are disabled. SRAM and register contents are preserved.
In Stop mode, all I/O pins keep the same state as in Run mode. In Stop mode, all I/O pins keep the same state as in Run mode.
@@ -285,27 +279,27 @@ void HAL_PWR_DisableBkUpAccess(void)
==================== ====================
[..] [..]
The Standby mode allows to achieve the lowest power consumption. It is based on the The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
switched off. SRAM and register contents are lost except for registers in the Backup domain switched off. SRAM and register contents are lost except for registers in the Backup domain
and Standby circuitry and Standby circuitry
(+) Entry: (+) Entry:
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
(+) Exit: (+) Exit:
(++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
NRSTpin, IWDG Reset NRSTpin, IWDG Reset
*** Auto-wakeup (AWU) from low-power mode *** *** Auto-wakeup (AWU) from low-power mode ***
============================================= =============================================
[..] [..]
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
without depending on an external interrupt (Auto-wakeup mode). without depending on an external interrupt (Auto-wakeup mode).
(+) RTC auto-wakeup (AWU) from the Stop and Standby modes (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
*** PWR Workarounds linked to Silicon Limitation *** *** PWR Workarounds linked to Silicon Limitation ***
@@ -314,124 +308,114 @@ void HAL_PWR_DisableBkUpAccess(void)
Below the list of all silicon limitations known on STM32F1xx prouct. Below the list of all silicon limitations known on STM32F1xx prouct.
(#)Workarounds Implemented inside PWR HAL Driver (#)Workarounds Implemented inside PWR HAL Driver
(##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
* @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
* information for the PVD. * information for the PVD.
* @note Refer to the electrical characteristics of your device datasheet for * @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each * more details about the voltage threshold corresponding to each
* detection level. * detection level.
* @retval None * @retval None
*/ */
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
/* Set PLS[7:5] bits according to PVDLevel value */ /* Set PLS[7:5] bits according to PVDLevel value */
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
/* Clear any previous config. Keep it clear if no event or IT mode is selected */ /* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT(); __HAL_PWR_PVD_EXTI_DISABLE_IT();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
/* Configure interrupt mode */ /* Configure interrupt mode */
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) {
{
__HAL_PWR_PVD_EXTI_ENABLE_IT(); __HAL_PWR_PVD_EXTI_ENABLE_IT();
} }
/* Configure event mode */ /* Configure event mode */
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) {
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT(); __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
} }
/* Configure the edge */ /* Configure the edge */
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) {
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
} }
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) {
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
} }
} }
/** /**
* @brief Enables the Power Voltage Detector(PVD). * @brief Enables the Power Voltage Detector(PVD).
* @retval None * @retval None
*/ */
void HAL_PWR_EnablePVD(void) void HAL_PWR_EnablePVD(void) {
{
/* Enable the power voltage detector */ /* Enable the power voltage detector */
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)ENABLE;
} }
/** /**
* @brief Disables the Power Voltage Detector(PVD). * @brief Disables the Power Voltage Detector(PVD).
* @retval None * @retval None
*/ */
void HAL_PWR_DisablePVD(void) void HAL_PWR_DisablePVD(void) {
{
/* Disable the power voltage detector */ /* Disable the power voltage detector */
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)DISABLE;
} }
/** /**
* @brief Enables the WakeUp PINx functionality. * @brief Enables the WakeUp PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1 * @arg PWR_WAKEUP_PIN1
* @retval None * @retval None
*/ */
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) {
{
/* Check the parameter */ /* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
/* Enable the EWUPx pin */ /* Enable the EWUPx pin */
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; *(__IO uint32_t *)CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
} }
/** /**
* @brief Disables the WakeUp PINx functionality. * @brief Disables the WakeUp PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1 * @arg PWR_WAKEUP_PIN1
* @retval None * @retval None
*/ */
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) {
{
/* Check the parameter */ /* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
/* Disable the EWUPx pin */ /* Disable the EWUPx pin */
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; *(__IO uint32_t *)CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
} }
/** /**
* @brief Enters Sleep mode. * @brief Enters Sleep mode.
* @note In Sleep mode, all I/O pins keep the same state as in Run mode. * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
* @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software
* @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
* When WFI entry is used, tick interrupt have to be disabled if not desired as * When WFI entry is used, tick interrupt have to be disabled if not desired as
* the interrupt wake up source. * the interrupt wake up source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
* @retval None * @retval None
*/ */
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) {
{
/* Check the parameters */ /* Check the parameters */
/* No check on Regulator because parameter not used in SLEEP mode */ /* No check on Regulator because parameter not used in SLEEP mode */
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
@@ -443,13 +427,10 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select SLEEP mode entry -------------------------------------------------*/ /* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI) if (SLEEPEntry == PWR_SLEEPENTRY_WFI) {
{
/* Request Wait For Interrupt */ /* Request Wait For Interrupt */
__WFI(); __WFI();
} } else {
else
{
/* Request Wait For Event */ /* Request Wait For Event */
__SEV(); __SEV();
__WFE(); __WFE();
@@ -458,32 +439,31 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
} }
/** /**
* @brief Enters Stop mode. * @brief Enters Stop mode.
* @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note When exiting Stop mode by using an interrupt or a wakeup event, * @note When exiting Stop mode by using an interrupt or a wakeup event,
* HSI RC oscillator is selected as system clock. * HSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode, an additional * @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode. * startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption * By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced. * is higher although the startup time is reduced.
* @param Regulator: Specifies the regulator state in Stop mode. * @param Regulator: Specifies the regulator state in Stop mode.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
* @retval None * @retval None
*/ */
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) {
{
/* Check the parameters */ /* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
CLEAR_BIT(PWR->CR, PWR_CR_PDDS); CLEAR_BIT(PWR->CR, PWR_CR_PDDS);
/* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
@@ -492,13 +472,10 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Stop mode entry --------------------------------------------------*/ /* Select Stop mode entry --------------------------------------------------*/
if(STOPEntry == PWR_STOPENTRY_WFI) if (STOPEntry == PWR_STOPENTRY_WFI) {
{
/* Request Wait For Interrupt */ /* Request Wait For Interrupt */
__WFI(); __WFI();
} } else {
else
{
/* Request Wait For Event */ /* Request Wait For Event */
__SEV(); __SEV();
PWR_OverloadWfe(); /* WFE redefine locally */ PWR_OverloadWfe(); /* WFE redefine locally */
@@ -509,15 +486,14 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
} }
/** /**
* @brief Enters Standby mode. * @brief Enters Standby mode.
* @note In Standby mode, all I/O pins are high impedance except for: * @note In Standby mode, all I/O pins are high impedance except for:
* - Reset pad (still available) * - Reset pad (still available)
* - TAMPER pin if configured for tamper or calibration out. * - TAMPER pin if configured for tamper or calibration out.
* - WKUP pin (PA0) if enabled. * - WKUP pin (PA0) if enabled.
* @retval None * @retval None
*/ */
void HAL_PWR_EnterSTANDBYMode(void) void HAL_PWR_EnterSTANDBYMode(void) {
{
/* Select Standby mode */ /* Select Standby mode */
SET_BIT(PWR->CR, PWR_CR_PDDS); SET_BIT(PWR->CR, PWR_CR_PDDS);
@@ -525,79 +501,67 @@ void HAL_PWR_EnterSTANDBYMode(void)
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* This option is used to ensure that store operations are completed */ /* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM) #if defined(__CC_ARM)
__force_stores(); __force_stores();
#endif #endif
/* Request Wait For Interrupt */ /* Request Wait For Interrupt */
__WFI(); __WFI();
} }
/** /**
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over. * re-enters SLEEP mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run only on * Setting this bit is useful when the processor is expected to run only on
* interruptions handling. * interruptions handling.
* @retval None * @retval None
*/ */
void HAL_PWR_EnableSleepOnExit(void) void HAL_PWR_EnableSleepOnExit(void) {
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */ /* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
} }
/** /**
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over. * re-enters SLEEP mode when an interruption handling is over.
* @retval None * @retval None
*/ */
void HAL_PWR_DisableSleepOnExit(void) void HAL_PWR_DisableSleepOnExit(void) {
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
} }
/** /**
* @brief Enables CORTEX M3 SEVONPEND bit. * @brief Enables CORTEX M3 SEVONPEND bit.
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended. * WFE to wake up when an interrupt moves from inactive to pended.
* @retval None * @retval None
*/ */
void HAL_PWR_EnableSEVOnPend(void) void HAL_PWR_EnableSEVOnPend(void) {
{
/* Set SEVONPEND bit of Cortex System Control Register */ /* Set SEVONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
} }
/** /**
* @brief Disables CORTEX M3 SEVONPEND bit. * @brief Disables CORTEX M3 SEVONPEND bit.
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended. * WFE to wake up when an interrupt moves from inactive to pended.
* @retval None * @retval None
*/ */
void HAL_PWR_DisableSEVOnPend(void) void HAL_PWR_DisableSEVOnPend(void) {
{
/* Clear SEVONPEND bit of Cortex System Control Register */ /* Clear SEVONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
} }
/** /**
* @brief This function handles the PWR PVD interrupt request. * @brief This function handles the PWR PVD interrupt request.
* @note This API should be called under the PVD_IRQHandler(). * @note This API should be called under the PVD_IRQHandler().
* @retval None * @retval None
*/ */
void HAL_PWR_PVD_IRQHandler(void) void HAL_PWR_PVD_IRQHandler(void) {
{
/* Check PWR exti flag */ /* Check PWR exti flag */
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) if (__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) {
{
/* PWR PVD interrupt user callback */ /* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback(); HAL_PWR_PVDCallback();
@@ -607,31 +571,30 @@ void HAL_PWR_PVD_IRQHandler(void)
} }
/** /**
* @brief PWR PVD interrupt callback * @brief PWR PVD interrupt callback
* @retval None * @retval None
*/ */
__weak void HAL_PWR_PVDCallback(void) __weak void HAL_PWR_PVDCallback(void) {
{
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PWR_PVDCallback could be implemented in the user file the HAL_PWR_PVDCallback could be implemented in the user file
*/ */
} }
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#endif /* HAL_PWR_MODULE_ENABLED */ #endif /* HAL_PWR_MODULE_ENABLED */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

933
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c vendored
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784
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c vendored
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4992
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c vendored
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1271
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c vendored
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59
source/Core/BSP/Miniware/flash.c
View File

@@ -5,42 +5,37 @@
* Author: Ralim * Author: Ralim
*/ */
#include "BSP_Flash.h"
#include "BSP.h" #include "BSP.h"
#include "string.h" #include "BSP_Flash.h"
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
#include "string.h"
static uint16_t settings_page[512] __attribute__ ((section (".settings_page"))); static uint16_t settings_page[512] __attribute__((section(".settings_page")));
uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length) { uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
FLASH_EraseInitTypeDef pEraseInit; FLASH_EraseInitTypeDef pEraseInit;
pEraseInit.TypeErase = FLASH_TYPEERASE_PAGES; pEraseInit.TypeErase = FLASH_TYPEERASE_PAGES;
pEraseInit.Banks = FLASH_BANK_1; pEraseInit.Banks = FLASH_BANK_1;
pEraseInit.NbPages = 1; pEraseInit.NbPages = 1;
pEraseInit.PageAddress = (uint32_t) settings_page; pEraseInit.PageAddress = (uint32_t)settings_page;
uint32_t failingAddress = 0; uint32_t failingAddress = 0;
resetWatchdog(); resetWatchdog();
__HAL_FLASH_CLEAR_FLAG( __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_BSY);
FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_BSY); HAL_FLASH_Unlock();
HAL_FLASH_Unlock(); HAL_Delay(1);
HAL_Delay(1); resetWatchdog();
resetWatchdog(); HAL_FLASHEx_Erase(&pEraseInit, &failingAddress);
HAL_FLASHEx_Erase(&pEraseInit, &failingAddress); //^ Erase the page of flash (1024 bytes on this stm32)
//^ Erase the page of flash (1024 bytes on this stm32) // erased the chunk
// erased the chunk // now we program it
// now we program it uint16_t *data = (uint16_t *)buffer;
uint16_t *data = (uint16_t*) buffer; HAL_FLASH_Unlock();
HAL_FLASH_Unlock(); for (uint8_t i = 0; i < (length / 2); i++) {
for (uint8_t i = 0; i < (length / 2); i++) { resetWatchdog();
resetWatchdog(); HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, (uint32_t)&settings_page[i], data[i]);
HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, }
(uint32_t) &settings_page[i], data[i]); HAL_FLASH_Lock();
} return 1;
HAL_FLASH_Lock();
return 1;
} }
void flash_read_buffer(uint8_t *buffer, const uint16_t length) { void flash_read_buffer(uint8_t *buffer, const uint16_t length) { memcpy(buffer, settings_page, length); }
memcpy(buffer, settings_page, length);
}

307
source/Core/BSP/Miniware/fusb302b.cpp
View File

@@ -17,10 +17,10 @@
#include "Model_Config.h" #include "Model_Config.h"
#ifdef POW_PD #ifdef POW_PD
#include "BSP.h" #include "BSP.h"
#include "fusb302b.h"
#include "I2CBB.hpp" #include "I2CBB.hpp"
#include <pd.h> #include "fusb302b.h"
#include "int_n.h" #include "int_n.h"
#include <pd.h>
/* /*
* Read a single byte from the FUSB302B * Read a single byte from the FUSB302B
* *
@@ -30,11 +30,11 @@
* Returns the value read from addr. * Returns the value read from addr.
*/ */
static uint8_t fusb_read_byte(uint8_t addr) { static uint8_t fusb_read_byte(uint8_t addr) {
uint8_t data[1]; uint8_t data[1];
if (!I2CBB::Mem_Read(FUSB302B_ADDR, addr, (uint8_t*) data, 1)) { if (!I2CBB::Mem_Read(FUSB302B_ADDR, addr, (uint8_t *)data, 1)) {
return 0; return 0;
} }
return data[0]; return data[0];
} }
/* /*
@@ -45,9 +45,7 @@ static uint8_t fusb_read_byte(uint8_t addr) {
* size: The number of bytes to read * size: The number of bytes to read
* buf: The buffer into which data will be read * buf: The buffer into which data will be read
*/ */
static bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) { static bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) { return I2CBB::Mem_Read(FUSB302B_ADDR, addr, buf, size); }
return I2CBB::Mem_Read(FUSB302B_ADDR, addr, buf, size);
}
/* /*
* Write a single byte to the FUSB302B * Write a single byte to the FUSB302B
@@ -56,9 +54,7 @@ static bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) {
* addr: The memory address to which we will write * addr: The memory address to which we will write
* byte: The value to write * byte: The value to write
*/ */
static bool fusb_write_byte(uint8_t addr, uint8_t byte) { static bool fusb_write_byte(uint8_t addr, uint8_t byte) { return I2CBB::Mem_Write(FUSB302B_ADDR, addr, (uint8_t *)&byte, 1); }
return I2CBB::Mem_Write(FUSB302B_ADDR, addr, (uint8_t*) &byte, 1);
}
/* /*
* Write multiple bytes to the FUSB302B * Write multiple bytes to the FUSB302B
@@ -68,198 +64,183 @@ static bool fusb_write_byte(uint8_t addr, uint8_t byte) {
* size: The number of bytes to write * size: The number of bytes to write
* buf: The buffer to write * buf: The buffer to write
*/ */
static bool fusb_write_buf(uint8_t addr, uint8_t size, const uint8_t *buf) { static bool fusb_write_buf(uint8_t addr, uint8_t size, const uint8_t *buf) { return I2CBB::Mem_Write(FUSB302B_ADDR, addr, buf, size); }
return I2CBB::Mem_Write(FUSB302B_ADDR, addr, buf, size);
}
void fusb_send_message(const union pd_msg *msg) { void fusb_send_message(const union pd_msg *msg) {
if (!I2CBB::lock2()) { if (!I2CBB::lock2()) {
return; return;
} }
/* Token sequences for the FUSB302B */ /* Token sequences for the FUSB302B */
static uint8_t sop_seq[5] = { static uint8_t sop_seq[5] = {FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP2, FUSB_FIFO_TX_PACKSYM};
FUSB_FIFO_TX_SOP1, static const uint8_t eop_seq[4] = {FUSB_FIFO_TX_JAM_CRC, FUSB_FIFO_TX_EOP, FUSB_FIFO_TX_TXOFF, FUSB_FIFO_TX_TXON};
FUSB_FIFO_TX_SOP1,
FUSB_FIFO_TX_SOP1,
FUSB_FIFO_TX_SOP2,
FUSB_FIFO_TX_PACKSYM };
static const uint8_t eop_seq[4] = {
FUSB_FIFO_TX_JAM_CRC,
FUSB_FIFO_TX_EOP,
FUSB_FIFO_TX_TXOFF,
FUSB_FIFO_TX_TXON };
/* Take the I2C2 mutex now so there can't be a race condition on sop_seq */ /* Take the I2C2 mutex now so there can't be a race condition on sop_seq */
/* Get the length of the message: a two-octet header plus NUMOBJ four-octet /* Get the length of the message: a two-octet header plus NUMOBJ four-octet
* data objects */ * data objects */
uint8_t msg_len = 2 + 4 * PD_NUMOBJ_GET(msg); uint8_t msg_len = 2 + 4 * PD_NUMOBJ_GET(msg);
/* Set the number of bytes to be transmitted in the packet */ /* Set the number of bytes to be transmitted in the packet */
sop_seq[4] = FUSB_FIFO_TX_PACKSYM | msg_len; sop_seq[4] = FUSB_FIFO_TX_PACKSYM | msg_len;
/* Write all three parts of the message to the TX FIFO */ /* Write all three parts of the message to the TX FIFO */
fusb_write_buf( FUSB_FIFOS, 5, sop_seq); fusb_write_buf(FUSB_FIFOS, 5, sop_seq);
fusb_write_buf( FUSB_FIFOS, msg_len, msg->bytes); fusb_write_buf(FUSB_FIFOS, msg_len, msg->bytes);
fusb_write_buf( FUSB_FIFOS, 4, eop_seq); fusb_write_buf(FUSB_FIFOS, 4, eop_seq);
I2CBB::unlock2();
I2CBB::unlock2();
} }
uint8_t fusb_read_message(union pd_msg *msg) { uint8_t fusb_read_message(union pd_msg *msg) {
if (!I2CBB::lock2()) { if (!I2CBB::lock2()) {
asm("bkpt"); asm("bkpt");
} }
static uint8_t garbage[4]; static uint8_t garbage[4];
uint8_t numobj; uint8_t numobj;
// Read the header. If its not a SOP we dont actually want it at all // Read the header. If its not a SOP we dont actually want it at all
// But on some revisions of the fusb if you dont both pick them up and read them out of the fifo, it gets stuck // But on some revisions of the fusb if you dont both pick them up and read them out of the fifo, it gets stuck
fusb_read_byte( FUSB_FIFOS); fusb_read_byte(FUSB_FIFOS);
/* Read the message header into msg */ /* Read the message header into msg */
fusb_read_buf( FUSB_FIFOS, 2, msg->bytes); fusb_read_buf(FUSB_FIFOS, 2, msg->bytes);
/* Get the number of data objects */ /* Get the number of data objects */
numobj = PD_NUMOBJ_GET(msg); numobj = PD_NUMOBJ_GET(msg);
/* If there is at least one data object, read the data objects */ /* If there is at least one data object, read the data objects */
if (numobj > 0) { if (numobj > 0) {
fusb_read_buf( FUSB_FIFOS, numobj * 4, msg->bytes + 2); fusb_read_buf(FUSB_FIFOS, numobj * 4, msg->bytes + 2);
} }
/* Throw the CRC32 in the garbage, since the PHY already checked it. */ /* Throw the CRC32 in the garbage, since the PHY already checked it. */
fusb_read_buf( FUSB_FIFOS, 4, garbage); fusb_read_buf(FUSB_FIFOS, 4, garbage);
I2CBB::unlock2(); I2CBB::unlock2();
return 0; return 0;
} }
void fusb_send_hardrst() { void fusb_send_hardrst() {
if (!I2CBB::lock2()) { if (!I2CBB::lock2()) {
return; return;
} }
/* Send a hard reset */ /* Send a hard reset */
fusb_write_byte( FUSB_CONTROL3, 0x07 | FUSB_CONTROL3_SEND_HARD_RESET); fusb_write_byte(FUSB_CONTROL3, 0x07 | FUSB_CONTROL3_SEND_HARD_RESET);
I2CBB::unlock2(); I2CBB::unlock2();
} }
bool fusb_setup() { bool fusb_setup() {
if (!I2CBB::lock2()) { if (!I2CBB::lock2()) {
return false; return false;
} }
/* Fully reset the FUSB302B */ /* Fully reset the FUSB302B */
// fusb_write_byte( FUSB_RESET, FUSB_RESET_SW_RES); // fusb_write_byte( FUSB_RESET, FUSB_RESET_SW_RES);
// osDelay(2); // osDelay(2);
if (!fusb_read_id()) { if (!fusb_read_id()) {
return false; return false;
} }
/* Turn on all power */ /* Turn on all power */
fusb_write_byte( FUSB_POWER, 0x0F); fusb_write_byte(FUSB_POWER, 0x0F);
/* Set interrupt masks */ /* Set interrupt masks */
//Setting to 0 so interrupts are allowed // Setting to 0 so interrupts are allowed
fusb_write_byte( FUSB_MASK1, 0x00); fusb_write_byte(FUSB_MASK1, 0x00);
fusb_write_byte( FUSB_MASKA, 0x00); fusb_write_byte(FUSB_MASKA, 0x00);
fusb_write_byte( FUSB_MASKB, 0x00); fusb_write_byte(FUSB_MASKB, 0x00);
fusb_write_byte( FUSB_CONTROL0, 0b11 << 2); fusb_write_byte(FUSB_CONTROL0, 0b11 << 2);
/* Enable automatic retransmission */ /* Enable automatic retransmission */
fusb_write_byte( FUSB_CONTROL3, 0x07); fusb_write_byte(FUSB_CONTROL3, 0x07);
//set defaults // set defaults
fusb_write_byte( FUSB_CONTROL2, 0x00); fusb_write_byte(FUSB_CONTROL2, 0x00);
/* Flush the RX buffer */ /* Flush the RX buffer */
fusb_write_byte( FUSB_CONTROL1, fusb_write_byte(FUSB_CONTROL1, FUSB_CONTROL1_RX_FLUSH);
FUSB_CONTROL1_RX_FLUSH);
/* Measure CC1 */ /* Measure CC1 */
fusb_write_byte( FUSB_SWITCHES0, 0x07); fusb_write_byte(FUSB_SWITCHES0, 0x07);
osDelay(10); osDelay(10);
uint8_t cc1 = fusb_read_byte( FUSB_STATUS0) & FUSB_STATUS0_BC_LVL; uint8_t cc1 = fusb_read_byte(FUSB_STATUS0) & FUSB_STATUS0_BC_LVL;
/* Measure CC2 */ /* Measure CC2 */
fusb_write_byte( FUSB_SWITCHES0, 0x0B); fusb_write_byte(FUSB_SWITCHES0, 0x0B);
osDelay(10); osDelay(10);
uint8_t cc2 = fusb_read_byte( FUSB_STATUS0) & FUSB_STATUS0_BC_LVL; uint8_t cc2 = fusb_read_byte(FUSB_STATUS0) & FUSB_STATUS0_BC_LVL;
/* Select the correct CC line for BMC signaling; also enable AUTO_CRC */ /* Select the correct CC line for BMC signaling; also enable AUTO_CRC */
if (cc1 > cc2) { if (cc1 > cc2) {
fusb_write_byte( FUSB_SWITCHES1, 0x25); fusb_write_byte(FUSB_SWITCHES1, 0x25);
fusb_write_byte( FUSB_SWITCHES0, 0x07); fusb_write_byte(FUSB_SWITCHES0, 0x07);
} else { } else {
fusb_write_byte( FUSB_SWITCHES1, 0x26); fusb_write_byte(FUSB_SWITCHES1, 0x26);
fusb_write_byte( FUSB_SWITCHES0, 0x0B); fusb_write_byte(FUSB_SWITCHES0, 0x0B);
} }
I2CBB::unlock2(); I2CBB::unlock2();
fusb_reset(); fusb_reset();
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Pull = GPIO_PULLUP;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 10, 0); HAL_NVIC_SetPriority(EXTI9_5_IRQn, 10, 0);
HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
return true; return true;
} }
void fusb_get_status(union fusb_status *status) { void fusb_get_status(union fusb_status *status) {
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
if (!I2CBB::lock2()) { if (!I2CBB::lock2()) {
return; return;
} }
} }
/* Read the interrupt and status flags into status */
fusb_read_buf( FUSB_STATUS0A, 7, status->bytes);
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
I2CBB::unlock2();
}
/* Read the interrupt and status flags into status */
fusb_read_buf(FUSB_STATUS0A, 7, status->bytes);
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
I2CBB::unlock2();
}
} }
enum fusb_typec_current fusb_get_typec_current() { enum fusb_typec_current fusb_get_typec_current() {
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
if (!I2CBB::lock2()) { if (!I2CBB::lock2()) {
return fusb_tcc_none; return fusb_tcc_none;
} }
} }
/* Read the BC_LVL into a variable */ /* Read the BC_LVL into a variable */
enum fusb_typec_current bc_lvl = (enum fusb_typec_current) (fusb_read_byte( enum fusb_typec_current bc_lvl = (enum fusb_typec_current)(fusb_read_byte(FUSB_STATUS0) & FUSB_STATUS0_BC_LVL);
FUSB_STATUS0) & FUSB_STATUS0_BC_LVL); if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { I2CBB::unlock2();
I2CBB::unlock2(); }
} return bc_lvl;
return bc_lvl;
} }
void fusb_reset() { void fusb_reset() {
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
if (!I2CBB::lock2()) { if (!I2CBB::lock2()) {
return; return;
} }
} }
/* Flush the TX buffer */ /* Flush the TX buffer */
fusb_write_byte( FUSB_CONTROL0, 0x44); fusb_write_byte(FUSB_CONTROL0, 0x44);
/* Flush the RX buffer */ /* Flush the RX buffer */
fusb_write_byte( FUSB_CONTROL1, FUSB_CONTROL1_RX_FLUSH); fusb_write_byte(FUSB_CONTROL1, FUSB_CONTROL1_RX_FLUSH);
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
I2CBB::unlock2(); I2CBB::unlock2();
} }
} }
bool fusb_read_id() { bool fusb_read_id() {
//Return true if read of the revision ID is sane // Return true if read of the revision ID is sane
uint8_t version = 0; uint8_t version = 0;
fusb_read_buf(FUSB_DEVICE_ID, 1, &version); fusb_read_buf(FUSB_DEVICE_ID, 1, &version);
if (version == 0 || version == 0xFF) if (version == 0 || version == 0xFF)
return false; return false;
return true; return true;
} }
uint8_t fusb302_detect() { uint8_t fusb302_detect() {
//Probe the I2C bus for its address // Probe the I2C bus for its address
return I2CBB::probe(FUSB302B_ADDR); return I2CBB::probe(FUSB302B_ADDR);
} }
#endif #endif

17
source/Core/BSP/Miniware/logo.cpp
View File

@@ -8,19 +8,18 @@
#include "BSP.h" #include "BSP.h"
#include "OLED.hpp" #include "OLED.hpp"
static uint8_t logo_page[1024] __attribute__ ((section (".logo_page"))); static uint8_t logo_page[1024] __attribute__((section(".logo_page")));
// Logo header signature. // Logo header signature.
#define LOGO_HEADER_VALUE 0xF00DAA55 #define LOGO_HEADER_VALUE 0xF00DAA55
uint8_t showBootLogoIfavailable() { uint8_t showBootLogoIfavailable() {
// Do not show logo data if signature is not found. // Do not show logo data if signature is not found.
if (LOGO_HEADER_VALUE != *(reinterpret_cast<const uint32_t*>(logo_page))) { if (LOGO_HEADER_VALUE != *(reinterpret_cast<const uint32_t *>(logo_page))) {
return 0; return 0;
} }
OLED::drawAreaSwapped(0, 0, 96, 16, (uint8_t*) (logo_page + 4)); OLED::drawAreaSwapped(0, 0, 96, 16, (uint8_t *)(logo_page + 4));
OLED::refresh(); OLED::refresh();
return 1; return 1;
} }

850
source/Core/BSP/Miniware/port.c
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File diff suppressed because it is too large Load Diff

177
source/Core/BSP/Miniware/portmacro.h
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@@ -43,24 +43,24 @@ extern "C" {
*/ */
/* Type definitions. */ /* Type definitions. */
#define portCHAR char #define portCHAR char
#define portFLOAT float #define portFLOAT float
#define portDOUBLE double #define portDOUBLE double
#define portLONG long #define portLONG long
#define portSHORT short #define portSHORT short
#define portSTACK_TYPE uint32_t #define portSTACK_TYPE uint32_t
#define portBASE_TYPE long #define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t; typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t; typedef long BaseType_t;
typedef unsigned long UBaseType_t; typedef unsigned long UBaseType_t;
#if( configUSE_16_BIT_TICKS == 1 ) #if (configUSE_16_BIT_TICKS == 1)
typedef uint16_t TickType_t; typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff #define portMAX_DELAY (TickType_t)0xffff
#else #else
typedef uint32_t TickType_t; typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL #define portMAX_DELAY (TickType_t)0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */ not need to be guarded with a critical section. */
@@ -69,52 +69,54 @@ typedef uint32_t TickType_t;
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Architecture specifics. */ /* Architecture specifics. */
#define portSTACK_GROWTH ( -1 ) #define portSTACK_GROWTH (-1)
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
#define portBYTE_ALIGNMENT 8 #define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Scheduler utilities. */ /* Scheduler utilities. */
#define portYIELD() \ #define portYIELD() \
{ \ { \
/* Set a PendSV to request a context switch. */ \ /* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
within the specified behaviour for the architecture. */ \ within the specified behaviour for the architecture. */ \
__asm volatile( "dsb" ::: "memory" ); \ __asm volatile("dsb" ::: "memory"); \
__asm volatile( "isb" ); \ __asm volatile("isb"); \
} }
#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_INT_CTRL_REG (*((volatile uint32_t *)0xe000ed04))
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) #define portNVIC_PENDSVSET_BIT (1UL << 28UL)
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD() #define portEND_SWITCHING_ISR(xSwitchRequired) \
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) if (xSwitchRequired != pdFALSE) \
portYIELD()
#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Critical section management. */ /* Critical section management. */
extern void vPortEnterCritical(void); extern void vPortEnterCritical(void);
extern void vPortExitCritical(void); extern void vPortExitCritical(void);
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x) #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)
#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
#define portENABLE_INTERRUPTS() vPortSetBASEPRI(0) #define portENABLE_INTERRUPTS() vPortSetBASEPRI(0)
#define portENTER_CRITICAL() vPortEnterCritical() #define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical() #define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are /* Task function macros as described on the FreeRTOS.org WEB site. These are
not necessary for to use this port. They are defined so the common demo files not necessary for to use this port. They are defined so the common demo files
(which build with all the ports) will build. */ (which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */ /* Tickless idle/low power functionality. */
#ifndef portSUPPRESS_TICKS_AND_SLEEP #ifndef portSUPPRESS_TICKS_AND_SLEEP
extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime); extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime)
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@@ -126,112 +128,103 @@ extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Generic helper function. */ /* Generic helper function. */
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( __attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros(uint32_t ulBitmap) {
uint32_t ulBitmap) { uint8_t ucReturn;
uint8_t ucReturn;
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); __asm volatile("clz %0, %1" : "=r"(ucReturn) : "r"(ulBitmap) : "memory");
return ucReturn; return ucReturn;
} }
/* Check the configuration. */ /* Check the configuration. */
#if( configMAX_PRIORITIES > 32 ) #if (configMAX_PRIORITIES > 32)
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
#endif #endif
/* Store/clear the ready priorities in a bit map. */ /* Store/clear the ready priorities in a bit map. */
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) #define portRECORD_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) |= (1UL << (uxPriority))
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) #define portRESET_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) &= ~(1UL << (uxPriority))
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) #define portGET_HIGHEST_PRIORITY(uxTopPriority, uxReadyPriorities) uxTopPriority = (31UL - (uint32_t)ucPortCountLeadingZeros((uxReadyPriorities)))
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#ifdef configASSERT #ifdef configASSERT
void vPortValidateInterruptPriority( void ); void vPortValidateInterruptPriority(void);
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif #endif
/* portNOP() is not required by this port. */ /* portNOP() is not required by this port. */
#define portNOP() #define portNOP()
#define portINLINE __inline #define portINLINE __inline
#ifndef portFORCE_INLINE #ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__(( always_inline)) #define portFORCE_INLINE inline __attribute__((always_inline))
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) { portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) {
uint32_t ulCurrentInterrupt; uint32_t ulCurrentInterrupt;
BaseType_t xReturn; BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */ /* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory");
if (ulCurrentInterrupt == 0) { if (ulCurrentInterrupt == 0) {
xReturn = pdFALSE; xReturn = pdFALSE;
} else { } else {
xReturn = pdTRUE; xReturn = pdTRUE;
} }
return xReturn; return xReturn;
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortRaiseBASEPRI(void) { portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
uint32_t ulNewBASEPRI; uint32_t ulNewBASEPRI;
__asm volatile __asm volatile(" mov %0, %1 \n"
( " msr basepri, %0 \n"
" mov %0, %1 \n" " isb \n"
" msr basepri, %0 \n" " dsb \n"
" isb \n" : "=r"(ulNewBASEPRI)
" dsb \n" : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" : "memory");
);
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) { portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) {
uint32_t ulOriginalBASEPRI, ulNewBASEPRI; uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile __asm volatile(" mrs %0, basepri \n"
( " mov %1, %2 \n"
" mrs %0, basepri \n" " msr basepri, %1 \n"
" mov %1, %2 \n" " isb \n"
" msr basepri, %1 \n" " dsb \n"
" isb \n" : "=r"(ulOriginalBASEPRI), "=r"(ulNewBASEPRI)
" dsb \n" : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" : "memory");
);
/* This return will not be reached but is necessary to prevent compiler /* This return will not be reached but is necessary to prevent compiler
warnings. */ warnings. */
return ulOriginalBASEPRI; return ulOriginalBASEPRI;
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { __asm volatile(" msr basepri, %0 " ::"r"(ulNewMaskValue) : "memory"); }
__asm volatile
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
);
}
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) #define portMEMORY_BARRIER() __asm volatile("" ::: "memory")
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* PORTMACRO_H */ #endif /* PORTMACRO_H */

12
source/Core/BSP/Miniware/postRTOS.cpp
View File

@@ -1,21 +1,21 @@
#include "BSP.h" #include "BSP.h"
#include "FreeRTOS.h" #include "FreeRTOS.h"
#include "I2C_Wrapper.hpp"
#include "QC3.h" #include "QC3.h"
#include "Settings.h" #include "Settings.h"
#include "cmsis_os.h" #include "cmsis_os.h"
#include "fusbpd.h"
#include "main.hpp" #include "main.hpp"
#include "power.hpp" #include "power.hpp"
#include "stdlib.h" #include "stdlib.h"
#include "task.h" #include "task.h"
#include "I2C_Wrapper.hpp"
#include "fusbpd.h"
// Initialisation to be performed with scheduler active // Initialisation to be performed with scheduler active
void postRToSInit() { void postRToSInit() {
#ifdef POW_PD #ifdef POW_PD
if (usb_pd_detect() == true) { if (usb_pd_detect() == true) {
//Spawn all of the USB-C processors // Spawn all of the USB-C processors
fusb302_start_processing(); fusb302_start_processing();
} }
#endif #endif
} }

24
source/Core/BSP/Miniware/preRTOS.cpp
View File

@@ -5,22 +5,22 @@
* Author: Ralim * Author: Ralim
*/ */
#include <I2C_Wrapper.hpp>
#include "BSP.h" #include "BSP.h"
#include "Setup.h"
#include "Pins.h"
#include "I2CBB.hpp" #include "I2CBB.hpp"
#include "fusbpd.h"
#include "Model_Config.h" #include "Model_Config.h"
#include "Pins.h"
#include "Setup.h"
#include "fusbpd.h"
#include <I2C_Wrapper.hpp>
void preRToSInit() { void preRToSInit() {
/* Reset of all peripherals, Initializes the Flash interface and the Systick. /* Reset of all peripherals, Initializes the Flash interface and the Systick.
*/ */
HAL_Init(); HAL_Init();
Setup_HAL(); // Setup all the HAL objects Setup_HAL(); // Setup all the HAL objects
BSPInit(); BSPInit();
#ifdef I2C_SOFT #ifdef I2C_SOFT
I2CBB::init(); I2CBB::init();
#endif #endif
/* Init the IPC objects */ /* Init the IPC objects */
FRToSI2C::FRToSInit(); FRToSI2C::FRToSInit();
} }

213
source/Core/BSP/Miniware/stm32f1xx_hal_msp.c
View File

@@ -1,141 +1,132 @@
#include "Pins.h" #include "Pins.h"
#include "stm32f1xx_hal.h"
#include "Setup.h" #include "Setup.h"
#include "stm32f1xx_hal.h"
/** /**
* Initializes the Global MSP. * Initializes the Global MSP.
*/ */
void HAL_MspInit(void) { void HAL_MspInit(void) {
__HAL_RCC_AFIO_CLK_ENABLE() __HAL_RCC_AFIO_CLK_ENABLE();
;
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* System interrupt init*/
/* MemoryManagement_IRQn interrupt configuration */
HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
/* BusFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
/* UsageFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
/* SVCall_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
/* DebugMonitor_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
/* System interrupt init*/
/* MemoryManagement_IRQn interrupt configuration */
HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
/* BusFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
/* UsageFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
/* SVCall_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
/* DebugMonitor_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
} }
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
if (hadc->Instance == ADC1) { if (hadc->Instance == ADC1) {
__HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC1_CLK_ENABLE();
;
/* ADC1 DMA Init */ /* ADC1 DMA Init */
/* ADC1 Init */ /* ADC1 Init */
hdma_adc1.Instance = DMA1_Channel1; hdma_adc1.Instance = DMA1_Channel1;
hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma_adc1.Init.Mode = DMA_CIRCULAR; hdma_adc1.Init.Mode = DMA_CIRCULAR;
hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM;
HAL_DMA_Init(&hdma_adc1); HAL_DMA_Init(&hdma_adc1);
__HAL_LINKDMA(hadc, DMA_Handle, hdma_adc1); __HAL_LINKDMA(hadc, DMA_Handle, hdma_adc1);
/* ADC1 interrupt Init */ /* ADC1 interrupt Init */
HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0); HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(ADC1_2_IRQn); HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
} else { } else {
__HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC2_CLK_ENABLE();
;
/**ADC2 GPIO Configuration /**ADC2 GPIO Configuration
PB0 ------> ADC2_IN8 PB0 ------> ADC2_IN8
PB1 ------> ADC2_IN9 PB1 ------> ADC2_IN9
*/ */
GPIO_InitStruct.Pin = TIP_TEMP_Pin; GPIO_InitStruct.Pin = TIP_TEMP_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
HAL_GPIO_Init(TIP_TEMP_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(TIP_TEMP_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Pin = TMP36_INPUT_Pin; GPIO_InitStruct.Pin = TMP36_INPUT_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
HAL_GPIO_Init(TMP36_INPUT_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(TMP36_INPUT_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Pin = VIN_Pin; GPIO_InitStruct.Pin = VIN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
HAL_GPIO_Init(VIN_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(VIN_GPIO_Port, &GPIO_InitStruct);
/* ADC2 interrupt Init */
HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
}
/* ADC2 interrupt Init */
HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
}
} }
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) { void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) {
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
/**I2C1 GPIO Configuration /**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL PB6 ------> I2C1_SCL
PB7 ------> I2C1_SDA PB7 ------> I2C1_SDA
*/ */
GPIO_InitStruct.Pin = SCL_Pin | SDA_Pin; GPIO_InitStruct.Pin = SCL_Pin | SDA_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* Peripheral clock enable */ /* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE() __HAL_RCC_I2C1_CLK_ENABLE();
; /* I2C1 DMA Init */
/* I2C1 DMA Init */ /* I2C1_RX Init */
/* I2C1_RX Init */ hdma_i2c1_rx.Instance = DMA1_Channel7;
hdma_i2c1_rx.Instance = DMA1_Channel7; hdma_i2c1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_i2c1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_i2c1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_i2c1_rx.Init.PeriphInc = DMA_PINC_DISABLE; hdma_i2c1_rx.Init.MemInc = DMA_MINC_ENABLE;
hdma_i2c1_rx.Init.MemInc = DMA_MINC_ENABLE; hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_i2c1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; hdma_i2c1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_i2c1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; hdma_i2c1_rx.Init.Mode = DMA_NORMAL;
hdma_i2c1_rx.Init.Mode = DMA_NORMAL; hdma_i2c1_rx.Init.Priority = DMA_PRIORITY_LOW;
hdma_i2c1_rx.Init.Priority = DMA_PRIORITY_LOW; HAL_DMA_Init(&hdma_i2c1_rx);
HAL_DMA_Init(&hdma_i2c1_rx);
__HAL_LINKDMA(hi2c, hdmarx, hdma_i2c1_rx); __HAL_LINKDMA(hi2c, hdmarx, hdma_i2c1_rx);
/* I2C1_TX Init */ /* I2C1_TX Init */
hdma_i2c1_tx.Instance = DMA1_Channel6; hdma_i2c1_tx.Instance = DMA1_Channel6;
hdma_i2c1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; hdma_i2c1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_i2c1_tx.Init.PeriphInc = DMA_PINC_DISABLE; hdma_i2c1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_i2c1_tx.Init.MemInc = DMA_MINC_ENABLE; hdma_i2c1_tx.Init.MemInc = DMA_MINC_ENABLE;
hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; hdma_i2c1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_i2c1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; hdma_i2c1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_i2c1_tx.Init.Mode = DMA_NORMAL; hdma_i2c1_tx.Init.Mode = DMA_NORMAL;
hdma_i2c1_tx.Init.Priority = DMA_PRIORITY_MEDIUM; hdma_i2c1_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
HAL_DMA_Init(&hdma_i2c1_tx); HAL_DMA_Init(&hdma_i2c1_tx);
__HAL_LINKDMA(hi2c, hdmatx, hdma_i2c1_tx); __HAL_LINKDMA(hi2c, hdmatx, hdma_i2c1_tx);
/* I2C1 interrupt Init */
HAL_NVIC_SetPriority(I2C1_EV_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
HAL_NVIC_SetPriority(I2C1_ER_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(I2C1_ER_IRQn);
/* I2C1 interrupt Init */
HAL_NVIC_SetPriority(I2C1_EV_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
HAL_NVIC_SetPriority(I2C1_ER_IRQn, 15, 0);
HAL_NVIC_EnableIRQ(I2C1_ER_IRQn);
} }
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base) { void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base) {
if (htim_base->Instance == TIM3) { if (htim_base->Instance == TIM3) {
/* Peripheral clock enable */ /* Peripheral clock enable */
__HAL_RCC_TIM3_CLK_ENABLE() __HAL_RCC_TIM3_CLK_ENABLE();
; } else if (htim_base->Instance == TIM2) {
} else if (htim_base->Instance == TIM2) { /* Peripheral clock enable */
/* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE();
__HAL_RCC_TIM2_CLK_ENABLE() }
;
}
} }

78
source/Core/BSP/Miniware/stm32f1xx_hal_timebase_TIM.c
View File

@@ -62,7 +62,7 @@
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
TIM_HandleTypeDef htim1; TIM_HandleTypeDef htim1;
uint32_t uwIncrementState = 0; uint32_t uwIncrementState = 0;
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
@@ -76,49 +76,49 @@ uint32_t uwIncrementState = 0;
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
RCC_ClkInitTypeDef clkconfig; RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0; uint32_t uwTimclock = 0;
uint32_t uwPrescalerValue = 0; uint32_t uwPrescalerValue = 0;
uint32_t pFLatency; uint32_t pFLatency;
/*Configure the TIM1 IRQ priority */ /*Configure the TIM1 IRQ priority */
HAL_NVIC_SetPriority(TIM1_UP_IRQn, TickPriority, 0); HAL_NVIC_SetPriority(TIM1_UP_IRQn, TickPriority, 0);
/* Enable the TIM1 global Interrupt */ /* Enable the TIM1 global Interrupt */
HAL_NVIC_EnableIRQ(TIM1_UP_IRQn); HAL_NVIC_EnableIRQ(TIM1_UP_IRQn);
/* Enable TIM1 clock */ /* Enable TIM1 clock */
__HAL_RCC_TIM1_CLK_ENABLE(); __HAL_RCC_TIM1_CLK_ENABLE();
/* Get clock configuration */ /* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
/* Compute TIM1 clock */ /* Compute TIM1 clock */
uwTimclock = HAL_RCC_GetPCLK2Freq(); uwTimclock = HAL_RCC_GetPCLK2Freq();
/* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */ /* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); uwPrescalerValue = (uint32_t)((uwTimclock / 1000000) - 1);
/* Initialize TIM1 */ /* Initialize TIM1 */
htim1.Instance = TIM1; htim1.Instance = TIM1;
/* Initialize TIMx peripheral as follow: /* Initialize TIMx peripheral as follow:
+ Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base. + Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0 + ClockDivision = 0
+ Counter direction = Up + Counter direction = Up
*/ */
htim1.Init.Period = (1000000 / 1000) - 1; htim1.Init.Period = (1000000 / 1000) - 1;
htim1.Init.Prescaler = uwPrescalerValue; htim1.Init.Prescaler = uwPrescalerValue;
htim1.Init.ClockDivision = 0; htim1.Init.ClockDivision = 0;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP; htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
if (HAL_TIM_Base_Init(&htim1) == HAL_OK) { if (HAL_TIM_Base_Init(&htim1) == HAL_OK) {
/* Start the TIM time Base generation in interrupt mode */ /* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim1); return HAL_TIM_Base_Start_IT(&htim1);
} }
/* Return function status */ /* Return function status */
return HAL_ERROR; return HAL_ERROR;
} }
/** /**
@@ -128,8 +128,8 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
* @retval None * @retval None
*/ */
void HAL_SuspendTick(void) { void HAL_SuspendTick(void) {
/* Disable TIM1 update Interrupt */ /* Disable TIM1 update Interrupt */
__HAL_TIM_DISABLE_IT(&htim1, TIM_IT_UPDATE); __HAL_TIM_DISABLE_IT(&htim1, TIM_IT_UPDATE);
} }
/** /**
@@ -139,8 +139,8 @@ void HAL_SuspendTick(void) {
* @retval None * @retval None
*/ */
void HAL_ResumeTick(void) { void HAL_ResumeTick(void) {
/* Enable TIM1 Update interrupt */ /* Enable TIM1 Update interrupt */
__HAL_TIM_ENABLE_IT(&htim1, TIM_IT_UPDATE); __HAL_TIM_ENABLE_IT(&htim1, TIM_IT_UPDATE);
} }
/** /**

80
source/Core/BSP/Miniware/stm32f1xx_it.c
View File

@@ -1,42 +1,34 @@
// This is the stock standard STM interrupt file full of handlers // This is the stock standard STM interrupt file full of handlers
#include "stm32f1xx_hal.h"
#include "stm32f1xx.h"
#include "stm32f1xx_it.h" #include "stm32f1xx_it.h"
#include "cmsis_os.h"
#include "Setup.h" #include "Setup.h"
#include "cmsis_os.h"
#include "stm32f1xx.h"
#include "stm32f1xx_hal.h"
extern TIM_HandleTypeDef htim1; //used for the systick extern TIM_HandleTypeDef htim1; // used for the systick
/******************************************************************************/ /******************************************************************************/
/* Cortex-M3 Processor Interruption and Exception Handlers */ /* Cortex-M3 Processor Interruption and Exception Handlers */
/******************************************************************************/ /******************************************************************************/
void NMI_Handler(void) { void NMI_Handler(void) {}
}
//We have the assembly for a breakpoint trigger here to halt the system when a debugger is connected // We have the assembly for a breakpoint trigger here to halt the system when a debugger is connected
// Hardfault handler, often a screwup in the code // Hardfault handler, often a screwup in the code
void HardFault_Handler(void) { void HardFault_Handler(void) {}
}
// Memory management unit had an error // Memory management unit had an error
void MemManage_Handler(void) { void MemManage_Handler(void) {}
}
// Prefetcher or busfault occured // Prefetcher or busfault occured
void BusFault_Handler(void) { void BusFault_Handler(void) {}
}
void UsageFault_Handler(void) { void UsageFault_Handler(void) {}
}
void DebugMon_Handler(void) { void DebugMon_Handler(void) {}
}
// Systick is used by FreeRTOS tick // Systick is used by FreeRTOS tick
void SysTick_Handler(void) { void SysTick_Handler(void) { osSystickHandler(); }
osSystickHandler();
}
/******************************************************************************/ /******************************************************************************/
/* STM32F1xx Peripheral Interrupt Handlers */ /* STM32F1xx Peripheral Interrupt Handlers */
@@ -46,42 +38,22 @@ void SysTick_Handler(void) {
/******************************************************************************/ /******************************************************************************/
// DMA used to move the ADC readings into system ram // DMA used to move the ADC readings into system ram
void DMA1_Channel1_IRQHandler(void) { void DMA1_Channel1_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_adc1); }
HAL_DMA_IRQHandler(&hdma_adc1); // ADC interrupt used for DMA
} void ADC1_2_IRQHandler(void) { HAL_ADC_IRQHandler(&hadc1); }
//ADC interrupt used for DMA
void ADC1_2_IRQHandler(void) {
HAL_ADC_IRQHandler(&hadc1);
}
//Timer 1 has overflowed, used for HAL ticks // Timer 1 has overflowed, used for HAL ticks
void TIM1_UP_IRQHandler(void) { void TIM1_UP_IRQHandler(void) { HAL_TIM_IRQHandler(&htim1); }
HAL_TIM_IRQHandler(&htim1); // Timer 3 is used for the PWM output to the tip
} void TIM3_IRQHandler(void) { HAL_TIM_IRQHandler(&htim3); }
//Timer 3 is used for the PWM output to the tip
void TIM3_IRQHandler(void) {
HAL_TIM_IRQHandler(&htim3);
}
//Timer 2 is used for co-ordination of PWM & ADC // Timer 2 is used for co-ordination of PWM & ADC
void TIM2_IRQHandler(void) { void TIM2_IRQHandler(void) { HAL_TIM_IRQHandler(&htim2); }
HAL_TIM_IRQHandler(&htim2);
}
void I2C1_EV_IRQHandler(void) { void I2C1_EV_IRQHandler(void) { HAL_I2C_EV_IRQHandler(&hi2c1); }
HAL_I2C_EV_IRQHandler(&hi2c1); void I2C1_ER_IRQHandler(void) { HAL_I2C_ER_IRQHandler(&hi2c1); }
}
void I2C1_ER_IRQHandler(void) {
HAL_I2C_ER_IRQHandler(&hi2c1);
}
void DMA1_Channel6_IRQHandler(void) { void DMA1_Channel6_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_i2c1_tx); }
HAL_DMA_IRQHandler(&hdma_i2c1_tx);
}
void DMA1_Channel7_IRQHandler(void) { void DMA1_Channel7_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_i2c1_rx); }
HAL_DMA_IRQHandler(&hdma_i2c1_rx); void EXTI9_5_IRQHandler(void) { HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); }
}
void EXTI9_5_IRQHandler(void) {
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
}

303
source/Core/BSP/Miniware/system_stm32f1xx.c
View File

@@ -2,10 +2,11 @@
// And as such, is BSD licneced from STM // And as such, is BSD licneced from STM
#include "stm32f1xx.h" #include "stm32f1xx.h"
#if !defined (HSI_VALUE) #if !defined(HSI_VALUE)
#define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. #define HSI_VALUE \
This value can be provided and adapted by the user application. */ 8000000U /*!< Default value of the Internal oscillator in Hz. \
#endif /* HSI_VALUE */ This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/*!< Uncomment the following line if you need to use external SRAM */ /*!< Uncomment the following line if you need to use external SRAM */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
@@ -13,23 +14,23 @@
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
#ifndef VECT_TAB_OFFSET #ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00004000U /*!< Vector Table base offset field. #define VECT_TAB_OFFSET \
This value must be a multiple of 0x200. */ 0x00004000U /*!< Vector Table base offset field. \
//We offset this by 0x4000 to because of the bootloader This value must be a multiple of 0x200. */
// We offset this by 0x4000 to because of the bootloader
#endif #endif
/******************************************************************************* /*******************************************************************************
* Clock Definitions * Clock Definitions
*******************************************************************************/ *******************************************************************************/
#if defined(STM32F100xB) ||defined(STM32F100xE) #if defined(STM32F100xB) || defined(STM32F100xE)
uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */ uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */
#else /*!< HSI Selected as System Clock source */ #else /*!< HSI Selected as System Clock source */
uint32_t SystemCoreClock = 64000000U; /*!< System Clock Frequency (Core Clock) */ uint32_t SystemCoreClock = 64000000U; /*!< System Clock Frequency (Core Clock) */
#endif #endif
const uint8_t AHBPrescTable[16U] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
8, 9 }; const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
const uint8_t APBPrescTable[8U] = { 0, 0, 0, 0, 1, 2, 3, 4 };
/** /**
* @brief Setup the microcontroller system * @brief Setup the microcontroller system
@@ -40,57 +41,57 @@ const uint8_t APBPrescTable[8U] = { 0, 0, 0, 0, 1, 2, 3, 4 };
* @retval None * @retval None
*/ */
void SystemInit(void) { void SystemInit(void) {
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */ /* Set HSION bit */
RCC->CR |= 0x00000001U; RCC->CR |= 0x00000001U;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC) #if !defined(STM32F105xC) && !defined(STM32F107xC)
RCC->CFGR &= 0xF8FF0000U; RCC->CFGR &= 0xF8FF0000U;
#else #else
RCC->CFGR &= 0xF0FF0000U; RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */ #endif /* STM32F105xC */
/* Reset HSEON, CSSON and PLLON bits */ /* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= 0xFEF6FFFFU; RCC->CR &= 0xFEF6FFFFU;
/* Reset HSEBYP bit */ /* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU; RCC->CR &= 0xFFFBFFFFU;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= 0xFF80FFFFU; RCC->CFGR &= 0xFF80FFFFU;
#if defined(STM32F105xC) || defined(STM32F107xC) #if defined(STM32F105xC) || defined(STM32F107xC)
/* Reset PLL2ON and PLL3ON bits */ /* Reset PLL2ON and PLL3ON bits */
RCC->CR &= 0xEBFFFFFFU; RCC->CR &= 0xEBFFFFFFU;
/* Disable all interrupts and clear pending bits */ /* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000U; RCC->CIR = 0x00FF0000U;
/* Reset CFGR2 register */ /* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000U; RCC->CFGR2 = 0x00000000U;
#elif defined(STM32F100xB) || defined(STM32F100xE) #elif defined(STM32F100xB) || defined(STM32F100xE)
/* Disable all interrupts and clear pending bits */ /* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000U; RCC->CIR = 0x009F0000U;
/* Reset CFGR2 register */ /* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000U; RCC->CFGR2 = 0x00000000U;
#else #else
/* Disable all interrupts and clear pending bits */ /* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000U; RCC->CIR = 0x009F0000U;
#endif /* STM32F105xC */ #endif /* STM32F105xC */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM #ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl(); SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
#endif #endif
#ifdef VECT_TAB_SRAM #ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else #else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif #endif
} }
/** /**
@@ -129,7 +130,7 @@ void SystemInit(void) {
* @retval None * @retval None
*/ */
void SystemCoreClockUpdate(void) { void SystemCoreClockUpdate(void) {
uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
#if defined(STM32F105xC) || defined(STM32F107xC) #if defined(STM32F105xC) || defined(STM32F107xC)
uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
@@ -139,116 +140,106 @@ void SystemCoreClockUpdate(void) {
uint32_t prediv1factor = 0U; uint32_t prediv1factor = 0U;
#endif /* STM32F100xB or STM32F100xE */ #endif /* STM32F100xB or STM32F100xE */
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp) { switch (tmp) {
case 0x00U: /* HSI used as system clock */ case 0x00U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
case 0x04U: /* HSE used as system clock */ case 0x04U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE; SystemCoreClock = HSE_VALUE;
break; break;
case 0x08U: /* PLL used as system clock */ case 0x08U: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/ /* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
#if !defined(STM32F105xC) && !defined(STM32F107xC) #if !defined(STM32F105xC) && !defined(STM32F107xC)
pllmull = (pllmull >> 18U) + 2U; pllmull = (pllmull >> 18U) + 2U;
if (pllsource == 0x00U) { if (pllsource == 0x00U) {
/* HSI oscillator clock divided by 2 selected as PLL clock entry */ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
} else { } else {
#if defined(STM32F100xB) || defined(STM32F100xE) #if defined(STM32F100xB) || defined(STM32F100xE)
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
/* HSE oscillator clock selected as PREDIV1 clock entry */ /* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else
/* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t) RESET) {/* HSE oscillator clock divided by 2 */
SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
} else {
SystemCoreClock = HSE_VALUE * pllmull;
}
#endif
}
#else #else
pllmull = pllmull >> 18U; /* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) { /* HSE oscillator clock divided by 2 */
if (pllmull != 0x0DU) SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
{ } else {
pllmull += 2U; SystemCoreClock = HSE_VALUE * pllmull;
} }
else #endif
{ /* PLL multiplication factor = PLL input clock * 6.5 */ }
pllmull = 13U / 2U; #else
} pllmull = pllmull >> 18U;
if (pllsource == 0x00U)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
}
else
{/* PREDIV1 selected as PLL clock entry */
/* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
if (prediv1source == 0U)
{
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
}
else
{/* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
}
}
#endif /* STM32F105xC */
break;
default: if (pllmull != 0x0DU) {
SystemCoreClock = HSI_VALUE; pllmull += 2U;
break; } else { /* PLL multiplication factor = PLL input clock * 6.5 */
} pllmull = 13U / 2U;
}
/* Compute HCLK clock frequency ----------------*/ if (pllsource == 0x00U) {
/* Get HCLK prescaler */ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
/* HCLK clock frequency */ } else { /* PREDIV1 selected as PLL clock entry */
SystemCoreClock >>= tmp;
/* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
if (prediv1source == 0U) {
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
} else { /* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
}
}
#endif /* STM32F105xC */
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
} }
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/** /**
* @brief Setup the external memory controller. Called in startup_stm32f1xx.s * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
* before jump to __main * before jump to __main
* @param None * @param None
* @retval None * @retval None
*/ */
#ifdef DATA_IN_ExtSRAM #ifdef DATA_IN_ExtSRAM
/** /**
* @brief Setup the external memory controller. * @brief Setup the external memory controller.
* Called in startup_stm32f1xx_xx.s/.c before jump to main. * Called in startup_stm32f1xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted on STM3210E-EVAL * This function configures the external SRAM mounted on STM3210E-EVAL
* board (STM32 High density devices). This SRAM will be used as program * board (STM32 High density devices). This SRAM will be used as program
* data memory (including heap and stack). * data memory (including heap and stack).
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemInit_ExtMemCtl(void) void SystemInit_ExtMemCtl(void) {
{
__IO uint32_t tmpreg; __IO uint32_t tmpreg;
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */ required, then adjust the Register Addresses */
/* Enable FSMC clock */ /* Enable FSMC clock */
@@ -256,36 +247,36 @@ void SystemInit_ExtMemCtl(void)
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0U; RCC->APB2ENR = 0x000001E0U;
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
(void)(tmpreg); (void)(tmpreg);
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/ /*---------------- SRAM Address lines configuration -------------------------*/
/*---------------- NOE and NWE configuration --------------------------------*/ /*---------------- NOE and NWE configuration --------------------------------*/
/*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/
GPIOD->CRL = 0x44BB44BBU; GPIOD->CRL = 0x44BB44BBU;
GPIOD->CRH = 0xBBBBBBBBU; GPIOD->CRH = 0xBBBBBBBBU;
GPIOE->CRL = 0xB44444BBU; GPIOE->CRL = 0xB44444BBU;
GPIOE->CRH = 0xBBBBBBBBU; GPIOE->CRH = 0xBBBBBBBBU;
GPIOF->CRL = 0x44BBBBBBU; GPIOF->CRL = 0x44BBBBBBU;
GPIOF->CRH = 0xBBBB4444U; GPIOF->CRH = 0xBBBB4444U;
GPIOG->CRL = 0x44BBBBBBU; GPIOG->CRL = 0x44BBBBBBU;
GPIOG->CRH = 0x444B4B44U; GPIOG->CRH = 0x444B4B44U;
/*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
FSMC_Bank1->BTCR[4U] = 0x00001091U; FSMC_Bank1->BTCR[4U] = 0x00001091U;
FSMC_Bank1->BTCR[5U] = 0x00110212U; FSMC_Bank1->BTCR[5U] = 0x00110212U;
} }

163
source/Core/BSP/Pine64/BSP.cpp
View File

@@ -9,123 +9,112 @@
#include "main.hpp" #include "main.hpp"
#include <IRQ.h> #include <IRQ.h>
const uint16_t powerPWM = 255; const uint16_t powerPWM = 255;
const uint8_t holdoffTicks = 25; // delay of 7 ms const uint8_t holdoffTicks = 25; // delay of 7 ms
const uint8_t tempMeasureTicks = 25; const uint8_t tempMeasureTicks = 25;
uint16_t totalPWM; // htim2.Init.Period, the full PWM cycle uint16_t totalPWM; // htim2.Init.Period, the full PWM cycle
// 2 second filter (ADC is PID_TIM_HZ Hz) // 2 second filter (ADC is PID_TIM_HZ Hz)
history<uint16_t, PID_TIM_HZ> rawTempFilter = { { 0 }, 0, 0 }; history<uint16_t, PID_TIM_HZ> rawTempFilter = {{0}, 0, 0};
void resetWatchdog() { void resetWatchdog() { fwdgt_counter_reload(); }
fwdgt_counter_reload();
}
uint16_t getTipInstantTemperature() { uint16_t getTipInstantTemperature() {
volatile uint16_t sum = 0; // 12 bit readings * 8*2 -> 16 bits volatile uint16_t sum = 0; // 12 bit readings * 8*2 -> 16 bits
for (int i = 0; i < 4; i++) { for (int i = 0; i < 4; i++) {
sum += adc_inserted_data_read(ADC0, i); sum += adc_inserted_data_read(ADC0, i);
sum += adc_inserted_data_read(ADC1, i); sum += adc_inserted_data_read(ADC1, i);
} }
return sum; // 8x over sample return sum; // 8x over sample
} }
uint16_t getTipRawTemp(uint8_t refresh) { uint16_t getTipRawTemp(uint8_t refresh) {
if (refresh) { if (refresh) {
uint16_t lastSample = getTipInstantTemperature(); uint16_t lastSample = getTipInstantTemperature();
rawTempFilter.update(lastSample); rawTempFilter.update(lastSample);
return lastSample; return lastSample;
} else { } else {
return rawTempFilter.average(); return rawTempFilter.average();
} }
} }
uint16_t getHandleTemperature() { uint16_t getHandleTemperature() {
#ifdef TEMP_TMP36 #ifdef TEMP_TMP36
// We return the current handle temperature in X10 C // We return the current handle temperature in X10 C
// TMP36 in handle, 0.5V offset and then 10mV per deg C (0.75V @ 25C for // TMP36 in handle, 0.5V offset and then 10mV per deg C (0.75V @ 25C for
// example) STM32 = 4096 count @ 3.3V input -> But We oversample by 32/(2^2) = // example) STM32 = 4096 count @ 3.3V input -> But We oversample by 32/(2^2) =
// 8 times oversampling Therefore 32768 is the 3.3V input, so 0.1007080078125 // 8 times oversampling Therefore 32768 is the 3.3V input, so 0.1007080078125
// mV per count So we need to subtract an offset of 0.5V to center on 0C // mV per count So we need to subtract an offset of 0.5V to center on 0C
// (4964.8 counts) // (4964.8 counts)
// //
int32_t result = getADC(0); int32_t result = getADC(0);
result -= 4965; // remove 0.5V offset result -= 4965; // remove 0.5V offset
// 10mV per C // 10mV per C
// 99.29 counts per Deg C above 0C // 99.29 counts per Deg C above 0C
result *= 100; result *= 100;
result /= 993; result /= 993;
return result; return result;
#else #else
#error #error
#endif #endif
} }
uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) { uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) {
static uint8_t preFillneeded = 10; static uint8_t preFillneeded = 10;
static uint32_t samples[BATTFILTERDEPTH]; static uint32_t samples[BATTFILTERDEPTH];
static uint8_t index = 0; static uint8_t index = 0;
if (preFillneeded) { if (preFillneeded) {
for (uint8_t i = 0; i < BATTFILTERDEPTH; i++) for (uint8_t i = 0; i < BATTFILTERDEPTH; i++)
samples[i] = getADC(1); samples[i] = getADC(1);
preFillneeded--; preFillneeded--;
} }
if (sample) { if (sample) {
samples[index] = getADC(1); samples[index] = getADC(1);
index = (index + 1) % BATTFILTERDEPTH; index = (index + 1) % BATTFILTERDEPTH;
} }
uint32_t sum = 0; uint32_t sum = 0;
for (uint8_t i = 0; i < BATTFILTERDEPTH; i++) for (uint8_t i = 0; i < BATTFILTERDEPTH; i++)
sum += samples[i]; sum += samples[i];
sum /= BATTFILTERDEPTH; sum /= BATTFILTERDEPTH;
if (divisor == 0) { if (divisor == 0) {
divisor = 1; divisor = 1;
} }
return sum * 4 / divisor; return sum * 4 / divisor;
} }
void unstick_I2C() { void unstick_I2C() {
/* configure SDA/SCL for GPIO */ /* configure SDA/SCL for GPIO */
GPIO_BC(GPIOB) |= SDA_Pin | SCL_Pin; GPIO_BC(GPIOB) |= SDA_Pin | SCL_Pin;
gpio_init(SDA_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, gpio_init(SDA_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin);
SDA_Pin | SCL_Pin); asm("nop");
asm("nop"); asm("nop");
asm("nop"); asm("nop");
asm("nop"); asm("nop");
asm("nop"); asm("nop");
asm("nop"); GPIO_BOP(GPIOB) |= SCL_Pin;
GPIO_BOP(GPIOB) |= SCL_Pin; asm("nop");
asm("nop"); asm("nop");
asm("nop"); asm("nop");
asm("nop"); asm("nop");
asm("nop"); asm("nop");
asm("nop"); GPIO_BOP(GPIOB) |= SDA_Pin;
GPIO_BOP(GPIOB) |= SDA_Pin; /* connect PB6 to I2C0_SCL */
/* connect PB6 to I2C0_SCL */ /* connect PB7 to I2C0_SDA */
/* connect PB7 to I2C0_SDA */ gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin);
gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ,
SDA_Pin | SCL_Pin);
} }
uint8_t getButtonA() { uint8_t getButtonA() { return (gpio_input_bit_get(KEY_A_GPIO_Port, KEY_A_Pin) == SET) ? 1 : 0; }
return (gpio_input_bit_get(KEY_A_GPIO_Port, KEY_A_Pin) == SET) ? 1 : 0; uint8_t getButtonB() { return (gpio_input_bit_get(KEY_B_GPIO_Port, KEY_B_Pin) == SET) ? 1 : 0; }
}
uint8_t getButtonB() {
return (gpio_input_bit_get(KEY_B_GPIO_Port, KEY_B_Pin) == SET) ? 1 : 0;
}
void reboot() { void reboot() {
//Spin for watchdog // Spin for watchdog
for (;;) { for (;;) {}
}
} }
void delay_ms(uint16_t count) { void delay_ms(uint16_t count) { delay_1ms(count); }
delay_1ms(count);
}
uint32_t __get_IPSR(void) { uint32_t __get_IPSR(void) {
return 0; // To shut-up CMSIS return 0; // To shut-up CMSIS
} }

16
source/Core/BSP/Pine64/BSP_PD.c
View File

@@ -12,14 +12,14 @@
* An array of all of the desired voltages & minimum currents in preferred order * An array of all of the desired voltages & minimum currents in preferred order
*/ */
const uint16_t USB_PD_Desired_Levels[] = { const uint16_t USB_PD_Desired_Levels[] = {
//mV desired input, mA minimum required current // mV desired input, mA minimum required current
//Tip is ~ 7.5 ohms // Tip is ~ 7.5 ohms
20000, 2666, // 20V, 2.6A 20000, 2666, // 20V, 2.6A
15000, 2000, // 15V 2A 15000, 2000, // 15V 2A
12000, 1600, //12V @ 1.6A 12000, 1600, // 12V @ 1.6A
9000, 1200, //9V @ 1.2A 9000, 1200, // 9V @ 1.2A
5000, 100, //5V @ whatever 5000, 100, // 5V @ whatever
}; };
const uint8_t USB_PD_Desired_Levels_Len = 5; const uint8_t USB_PD_Desired_Levels_Len = 5;
#endif #endif

123
source/Core/BSP/Pine64/FreeRTOSConfig.h
View File

@@ -1,96 +1,95 @@
#ifndef FREERTOS_CONFIG_H #ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H
#include <stdint.h>
#include "nuclei_sdk_soc.h" #include "nuclei_sdk_soc.h"
//RISC-V configuration #include <stdint.h>
// RISC-V configuration
#define USER_MODE_TASKS 0 #define USER_MODE_TASKS 0
#define configUSE_PREEMPTION 1 #define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configUSE_TICKLESS_IDLE 0 #define configUSE_TICKLESS_IDLE 0
#define configCPU_CLOCK_HZ ((uint32_t)SystemCoreClock) #define configCPU_CLOCK_HZ ((uint32_t)SystemCoreClock)
#define configRTC_CLOCK_HZ ((uint32_t)32768) #define configRTC_CLOCK_HZ ((uint32_t)32768)
#define configTICK_RATE_HZ ((TickType_t)1000) #define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES (4) #define configMAX_PRIORITIES (4)
#define configMINIMAL_STACK_SIZE ((unsigned short)128) #define configMINIMAL_STACK_SIZE ((unsigned short)128)
#define configMAX_TASK_NAME_LEN 24 #define configMAX_TASK_NAME_LEN 24
#define configUSE_16_BIT_TICKS 0 #define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0 #define configIDLE_SHOULD_YIELD 0
#define configUSE_TASK_NOTIFICATIONS 1 #define configUSE_TASK_NOTIFICATIONS 1
#define configUSE_MUTEXES 1 #define configUSE_MUTEXES 1
#define configUSE_RECURSIVE_MUTEXES 0 #define configUSE_RECURSIVE_MUTEXES 0
#define configUSE_COUNTING_SEMAPHORES 0 #define configUSE_COUNTING_SEMAPHORES 0
#define configQUEUE_REGISTRY_SIZE 10 #define configQUEUE_REGISTRY_SIZE 10
#define configUSE_QUEUE_SETS 0 #define configUSE_QUEUE_SETS 0
#define configUSE_TIME_SLICING 1 #define configUSE_TIME_SLICING 1
#define configUSE_NEWLIB_REENTRANT 0 #define configUSE_NEWLIB_REENTRANT 0
#define configENABLE_BACKWARD_COMPATIBILITY 0 #define configENABLE_BACKWARD_COMPATIBILITY 0
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
#define INCLUDE_uxTaskGetStackHighWaterMark 1 #define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_xTaskGetSchedulerState 1 #define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_vTaskDelay 1 #define INCLUDE_vTaskDelay 1
/* Memory allocation related definitions. */ /* Memory allocation related definitions. */
#define configSUPPORT_STATIC_ALLOCATION 1 #define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 0 #define configSUPPORT_DYNAMIC_ALLOCATION 0
#define configTOTAL_HEAP_SIZE 1024 #define configTOTAL_HEAP_SIZE 1024
#define configAPPLICATION_ALLOCATED_HEAP 0 #define configAPPLICATION_ALLOCATED_HEAP 0
/* Hook function related definitions. */ /* Hook function related definitions. */
#define configUSE_IDLE_HOOK 1 #define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0 #define configUSE_TICK_HOOK 0
#define configCHECK_FOR_STACK_OVERFLOW 2 #define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_MALLOC_FAILED_HOOK 0 #define configUSE_MALLOC_FAILED_HOOK 0
#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 #define configUSE_DAEMON_TASK_STARTUP_HOOK 0
/* Run time and task stats gathering related definitions. */ /* Run time and task stats gathering related definitions. */
#define configGENERATE_RUN_TIME_STATS 0 #define configGENERATE_RUN_TIME_STATS 0
#define configUSE_TRACE_FACILITY 1 #define configUSE_TRACE_FACILITY 1
#define configUSE_STATS_FORMATTING_FUNCTIONS 1 #define configUSE_STATS_FORMATTING_FUNCTIONS 1
/* Co-routine related definitions. */ /* Co-routine related definitions. */
#define configUSE_CO_ROUTINES 0 #define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES 1 #define configMAX_CO_ROUTINE_PRIORITIES 1
/* Software timer related definitions. */ /* Software timer related definitions. */
#define configUSE_TIMERS 0 #define configUSE_TIMERS 0
#define configTIMER_TASK_PRIORITY 3 #define configTIMER_TASK_PRIORITY 3
#define configTIMER_QUEUE_LENGTH 5 #define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE #define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
/* Interrupt nesting behaviour configuration. */ /* Interrupt nesting behaviour configuration. */
#define configPRIO_BITS (4UL) #define configPRIO_BITS (4UL)
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x1 #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x1
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 0xe #define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 0xe
#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) #define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) #define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* Define to trap errors during development. */ /* Define to trap errors during development. */
#define configASSERT(x) \ #define configASSERT(x) \
if ((x) == 0) \ if ((x) == 0) { \
{ \ taskDISABLE_INTERRUPTS(); \
taskDISABLE_INTERRUPTS(); \ for (;;) \
for (;;) \ ; \
; \ }
}
#define INCLUDE_vTaskPrioritySet 1 #define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1 #define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1 #define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskSuspend 1 #define INCLUDE_vTaskSuspend 1
#define INCLUDE_xResumeFromISR 1 #define INCLUDE_xResumeFromISR 1
#define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1 #define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 1 #define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1 #define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_xTaskGetIdleTaskHandle 1 #define INCLUDE_xTaskGetIdleTaskHandle 1
#define INCLUDE_eTaskGetState 0 #define INCLUDE_eTaskGetState 0
#define INCLUDE_xEventGroupSetBitFromISR 1 #define INCLUDE_xEventGroupSetBitFromISR 1
#define INCLUDE_xTimerPendFunctionCall 0 #define INCLUDE_xTimerPendFunctionCall 0
#define INCLUDE_xTaskAbortDelay 0 #define INCLUDE_xTaskAbortDelay 0
#define INCLUDE_xTaskGetHandle 1 #define INCLUDE_xTaskGetHandle 1
#define INCLUDE_xTaskResumeFromISR 1 #define INCLUDE_xTaskResumeFromISR 1
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#endif /* FREERTOS_CONFIG_H */ #endif /* FREERTOS_CONFIG_H */

945
source/Core/BSP/Pine64/I2C_Wrapper.cpp
View File

@@ -12,517 +12,506 @@ SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr;
StaticSemaphore_t FRToSI2C::xSemaphoreBuffer; StaticSemaphore_t FRToSI2C::xSemaphoreBuffer;
#define I2C_TIME_OUT (uint16_t)(12000) #define I2C_TIME_OUT (uint16_t)(12000)
void FRToSI2C::CpltCallback() { void FRToSI2C::CpltCallback() {
// TODO // TODO
} }
bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }
return Mem_Write(address, reg, &data, 1);
}
uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) { uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) {
uint8_t temp = 0; uint8_t temp = 0;
Mem_Read(add, reg, &temp, 1); Mem_Read(add, reg, &temp, 1);
return temp; return temp;
} }
bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_buffer, uint16_t number_of_byte) { bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_buffer, uint16_t number_of_byte) {
if (!lock()) if (!lock())
return false; return false;
i2c_interrupt_disable(I2C0, I2C_INT_ERR); i2c_interrupt_disable(I2C0, I2C_INT_ERR);
i2c_interrupt_disable(I2C0, I2C_INT_BUF); i2c_interrupt_disable(I2C0, I2C_INT_BUF);
i2c_interrupt_disable(I2C0, I2C_INT_EV); i2c_interrupt_disable(I2C0, I2C_INT_EV);
dma_parameter_struct dma_init_struct; dma_parameter_struct dma_init_struct;
uint8_t state = I2C_START; uint8_t state = I2C_START;
uint8_t in_rx_cycle = 0; uint8_t in_rx_cycle = 0;
uint16_t timeout = 0; uint16_t timeout = 0;
uint8_t tries = 0; uint8_t tries = 0;
uint8_t i2c_timeout_flag = 0; uint8_t i2c_timeout_flag = 0;
while (!(i2c_timeout_flag)) { while (!(i2c_timeout_flag)) {
switch (state) { switch (state) {
case I2C_START: case I2C_START:
tries++; tries++;
if (tries > 64) { if (tries > 64) {
i2c_stop_on_bus(I2C0); i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */ /* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) { while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
unlock(); unlock();
return false; return false;
} }
if (0 == in_rx_cycle) { if (0 == in_rx_cycle) {
/* disable I2C0 */ /* disable I2C0 */
i2c_disable(I2C0); i2c_disable(I2C0);
/* enable I2C0 */ /* enable I2C0 */
i2c_enable(I2C0); i2c_enable(I2C0);
/* enable acknowledge */ /* enable acknowledge */
i2c_ack_config(I2C0, I2C_ACK_ENABLE); i2c_ack_config(I2C0, I2C_ACK_ENABLE);
/* i2c master sends start signal only when the bus is idle */ /* i2c master sends start signal only when the bus is idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT )) { while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
/* send the start signal */ /* send the start signal */
i2c_start_on_bus(I2C0); i2c_start_on_bus(I2C0);
timeout = 0; timeout = 0;
state = I2C_SEND_ADDRESS; state = I2C_SEND_ADDRESS;
} else { } else {
I2C_Unstick(); I2C_Unstick();
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
} }
} else { } else {
i2c_start_on_bus(I2C0); i2c_start_on_bus(I2C0);
timeout = 0; timeout = 0;
state = I2C_SEND_ADDRESS; state = I2C_SEND_ADDRESS;
} }
break; break;
case I2C_SEND_ADDRESS: case I2C_SEND_ADDRESS:
/* i2c master sends START signal successfully */ /* i2c master sends START signal successfully */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT )) { while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
if (RESET == in_rx_cycle) { if (RESET == in_rx_cycle) {
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER); i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
state = I2C_CLEAR_ADDRESS_FLAG; state = I2C_CLEAR_ADDRESS_FLAG;
} else { } else {
i2c_master_addressing(I2C0, DevAddress, I2C_RECEIVER); i2c_master_addressing(I2C0, DevAddress, I2C_RECEIVER);
state = I2C_CLEAR_ADDRESS_FLAG; state = I2C_CLEAR_ADDRESS_FLAG;
} }
timeout = 0; timeout = 0;
} else { } else {
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
in_rx_cycle = 0; in_rx_cycle = 0;
} }
break; break;
case I2C_CLEAR_ADDRESS_FLAG: case I2C_CLEAR_ADDRESS_FLAG:
/* address flag set means i2c slave sends ACK */ /* address flag set means i2c slave sends ACK */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT )) { while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) { if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_AERR); i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_stop_on_bus(I2C0); i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */ /* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) { while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
// Address NACK'd // Address NACK'd
unlock(); unlock();
return false; return false;
} }
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
timeout = 0; timeout = 0;
state = I2C_TRANSMIT_DATA; state = I2C_TRANSMIT_DATA;
} else { } else {
i2c_stop_on_bus(I2C0); i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */ /* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) { while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
// Address NACK'd // Address NACK'd
unlock(); unlock();
return false; return false;
} }
break; break;
case I2C_TRANSMIT_DATA: case I2C_TRANSMIT_DATA:
if (0 == in_rx_cycle) { if (0 == in_rx_cycle) {
/* wait until the transmit data buffer is empty */ /* wait until the transmit data buffer is empty */
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT )) { while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
// Write out the 8 byte address // Write out the 8 byte address
i2c_data_transmit(I2C0, read_address); i2c_data_transmit(I2C0, read_address);
timeout = 0; timeout = 0;
} else { } else {
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
in_rx_cycle = 0; in_rx_cycle = 0;
} }
/* wait until BTC bit is set */ /* wait until BTC bit is set */
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT )) { while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
in_rx_cycle = 1; in_rx_cycle = 1;
} else { } else {
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
in_rx_cycle = 0; in_rx_cycle = 0;
} }
} else { } else {
/* one byte master reception procedure (polling) */ /* one byte master reception procedure (polling) */
if (number_of_byte < 2) { if (number_of_byte < 2) {
/* disable acknowledge */ /* disable acknowledge */
i2c_ack_config(I2C0, I2C_ACK_DISABLE); i2c_ack_config(I2C0, I2C_ACK_DISABLE);
/* clear ADDSEND register by reading I2C_STAT0 then I2C_STAT1 register /* clear ADDSEND register by reading I2C_STAT0 then I2C_STAT1 register
* (I2C_STAT0 has already been read) */ * (I2C_STAT0 has already been read) */
i2c_flag_get(I2C0, I2C_FLAG_ADDSEND); i2c_flag_get(I2C0, I2C_FLAG_ADDSEND);
/* send a stop condition to I2C bus*/ /* send a stop condition to I2C bus*/
i2c_stop_on_bus(I2C0); i2c_stop_on_bus(I2C0);
/* wait for the byte to be received */ /* wait for the byte to be received */
while (!i2c_flag_get(I2C0, I2C_FLAG_RBNE)) while (!i2c_flag_get(I2C0, I2C_FLAG_RBNE))
; ;
/* read the byte received from the EEPROM */ /* read the byte received from the EEPROM */
*p_buffer = i2c_data_receive(I2C0); *p_buffer = i2c_data_receive(I2C0);
/* decrement the read bytes counter */ /* decrement the read bytes counter */
number_of_byte--; number_of_byte--;
timeout = 0; timeout = 0;
} else { /* more than one byte master reception procedure (DMA) */ } else { /* more than one byte master reception procedure (DMA) */
dma_deinit(DMA0, DMA_CH6); dma_deinit(DMA0, DMA_CH6);
dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_addr = (uint32_t) p_buffer; dma_init_struct.memory_addr = (uint32_t)p_buffer;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
dma_init_struct.number = number_of_byte; dma_init_struct.number = number_of_byte;
dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0); dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0);
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
dma_init(DMA0, DMA_CH6, &dma_init_struct); dma_init(DMA0, DMA_CH6, &dma_init_struct);
i2c_dma_last_transfer_config(I2C0, I2C_DMALST_ON); i2c_dma_last_transfer_config(I2C0, I2C_DMALST_ON);
/* enable I2C0 DMA */ /* enable I2C0 DMA */
i2c_dma_enable(I2C0, I2C_DMA_ON); i2c_dma_enable(I2C0, I2C_DMA_ON);
/* enable DMA0 channel5 */ /* enable DMA0 channel5 */
dma_channel_enable(DMA0, DMA_CH6); dma_channel_enable(DMA0, DMA_CH6);
/* wait until BTC bit is set */ /* wait until BTC bit is set */
while (!dma_flag_get(DMA0, DMA_CH6, DMA_FLAG_FTF)) { while (!dma_flag_get(DMA0, DMA_CH6, DMA_FLAG_FTF)) {}
/* send a stop condition to I2C bus*/
} i2c_stop_on_bus(I2C0);
/* send a stop condition to I2C bus*/ }
i2c_stop_on_bus(I2C0); timeout = 0;
} state = I2C_STOP;
timeout = 0; }
state = I2C_STOP; break;
} case I2C_STOP:
break; /* i2c master sends STOP signal successfully */
case I2C_STOP: while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
/* i2c master sends STOP signal successfully */ timeout++;
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) { }
timeout++; if (timeout < I2C_TIME_OUT) {
} timeout = 0;
if (timeout < I2C_TIME_OUT) { state = I2C_END;
timeout = 0; i2c_timeout_flag = I2C_OK;
state = I2C_END; } else {
i2c_timeout_flag = I2C_OK; timeout = 0;
} else { state = I2C_START;
timeout = 0; in_rx_cycle = 0;
state = I2C_START; }
in_rx_cycle = 0; break;
} default:
break; state = I2C_START;
default: in_rx_cycle = 0;
state = I2C_START; i2c_timeout_flag = I2C_OK;
in_rx_cycle = 0; timeout = 0;
i2c_timeout_flag = I2C_OK; break;
timeout = 0; }
break; }
} unlock();
} return true;
unlock();
return true;
} }
bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_buffer, uint16_t number_of_byte) { bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_buffer, uint16_t number_of_byte) {
if (!lock()) if (!lock())
return false; return false;
i2c_interrupt_disable(I2C0, I2C_INT_ERR); i2c_interrupt_disable(I2C0, I2C_INT_ERR);
i2c_interrupt_disable(I2C0, I2C_INT_EV); i2c_interrupt_disable(I2C0, I2C_INT_EV);
i2c_interrupt_disable(I2C0, I2C_INT_BUF); i2c_interrupt_disable(I2C0, I2C_INT_BUF);
dma_parameter_struct dma_init_struct; dma_parameter_struct dma_init_struct;
uint8_t state = I2C_START; uint8_t state = I2C_START;
uint16_t timeout = 0; uint16_t timeout = 0;
bool done = false; bool done = false;
bool timedout = false; bool timedout = false;
while (!(done || timedout)) { while (!(done || timedout)) {
switch (state) { switch (state) {
case I2C_START: case I2C_START:
/* i2c master sends start signal only when the bus is idle */ /* i2c master sends start signal only when the bus is idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT )) { while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
i2c_start_on_bus(I2C0); i2c_start_on_bus(I2C0);
timeout = 0; timeout = 0;
state = I2C_SEND_ADDRESS; state = I2C_SEND_ADDRESS;
} else { } else {
I2C_Unstick(); I2C_Unstick();
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
} }
break; break;
case I2C_SEND_ADDRESS: case I2C_SEND_ADDRESS:
/* i2c master sends START signal successfully */ /* i2c master sends START signal successfully */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT )) { while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER); i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
timeout = 0; timeout = 0;
state = I2C_CLEAR_ADDRESS_FLAG; state = I2C_CLEAR_ADDRESS_FLAG;
} else { } else {
timedout = true; timedout = true;
done = true; done = true;
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
} }
break; break;
case I2C_CLEAR_ADDRESS_FLAG: case I2C_CLEAR_ADDRESS_FLAG:
/* address flag set means i2c slave sends ACK */ /* address flag set means i2c slave sends ACK */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT )) { while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) { if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_AERR); i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_stop_on_bus(I2C0); i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */ /* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) { while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
// Address NACK'd // Address NACK'd
unlock(); unlock();
return false; return false;
} }
} }
timeout = 0; timeout = 0;
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
state = I2C_TRANSMIT_DATA; state = I2C_TRANSMIT_DATA;
} else { } else {
// Dont retry as this means a NAK // Dont retry as this means a NAK
i2c_stop_on_bus(I2C0); i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */ /* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) { while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
unlock(); unlock();
return false; return false;
} }
break; break;
case I2C_TRANSMIT_DATA: case I2C_TRANSMIT_DATA:
/* wait until the transmit data buffer is empty */ /* wait until the transmit data buffer is empty */
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT )) { while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
/* send the EEPROM's internal address to write to : only one byte /* send the EEPROM's internal address to write to : only one byte
* address */ * address */
i2c_data_transmit(I2C0, MemAddress); i2c_data_transmit(I2C0, MemAddress);
timeout = 0; timeout = 0;
} else { } else {
timedout = true; timedout = true;
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
} }
/* wait until BTC bit is set */ /* wait until BTC bit is set */
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) while (!i2c_flag_get(I2C0, I2C_FLAG_BTC))
; ;
dma_deinit(DMA0, DMA_CH5); dma_deinit(DMA0, DMA_CH5);
dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_addr = (uint32_t) p_buffer; dma_init_struct.memory_addr = (uint32_t)p_buffer;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
dma_init_struct.number = number_of_byte; dma_init_struct.number = number_of_byte;
dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0); dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0);
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
dma_init(DMA0, DMA_CH5, &dma_init_struct); dma_init(DMA0, DMA_CH5, &dma_init_struct);
/* enable I2C0 DMA */ /* enable I2C0 DMA */
i2c_dma_enable(I2C0, I2C_DMA_ON); i2c_dma_enable(I2C0, I2C_DMA_ON);
/* enable DMA0 channel5 */ /* enable DMA0 channel5 */
dma_channel_enable(DMA0, DMA_CH5); dma_channel_enable(DMA0, DMA_CH5);
/* wait until BTC bit is set */ /* wait until BTC bit is set */
while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) { while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {}
/* wait until BTC bit is set */
} while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) {}
/* wait until BTC bit is set */ state = I2C_STOP;
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) { break;
} case I2C_STOP:
state = I2C_STOP; /* send a stop condition to I2C bus */
break; i2c_stop_on_bus(I2C0);
case I2C_STOP: /* i2c master sends STOP signal successfully */
/* send a stop condition to I2C bus */ while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
i2c_stop_on_bus(I2C0); timeout++;
/* i2c master sends STOP signal successfully */ }
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) { if (timeout < I2C_TIME_OUT) {
timeout++; timeout = 0;
} state = I2C_END;
if (timeout < I2C_TIME_OUT) { done = true;
timeout = 0; } else {
state = I2C_END; timedout = true;
done = true; done = true;
} else { timeout = 0;
timedout = true; state = I2C_START;
done = true; }
timeout = 0; break;
state = I2C_START; default:
} state = I2C_START;
break; timeout = 0;
default: break;
state = I2C_START; }
timeout = 0; }
break; unlock();
} return timedout == false;
}
unlock();
return timedout == false;
} }
bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) { bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) { return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1); }
return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1);
}
bool FRToSI2C::probe(uint16_t DevAddress) { bool FRToSI2C::probe(uint16_t DevAddress) {
uint8_t temp[1]; uint8_t temp[1];
return Mem_Read(DevAddress, 0x00, temp, sizeof(temp)); return Mem_Read(DevAddress, 0x00, temp, sizeof(temp));
} }
void FRToSI2C::I2C_Unstick() { void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
unstick_I2C();
}
bool FRToSI2C::lock() { bool FRToSI2C::lock() {
if (I2CSemaphore == nullptr) { if (I2CSemaphore == nullptr) {
return false; return false;
} }
if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) { if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) {
return true; return true;
} }
return xSemaphoreTake(I2CSemaphore, TICKS_SECOND) == pdTRUE; return xSemaphoreTake(I2CSemaphore, TICKS_SECOND) == pdTRUE;
} }
void FRToSI2C::unlock() { void FRToSI2C::unlock() {
if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) { if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) {
return; return;
} }
xSemaphoreGive(I2CSemaphore); xSemaphoreGive(I2CSemaphore);
} }
bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) { bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) {
for (int index = 0; index < registersLength; index++) { for (int index = 0; index < registersLength; index++) {
if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) { if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) {
return false; return false;
} }
if (registers[index].pause_ms) { if (registers[index].pause_ms) {
delay_ms(registers[index].pause_ms); delay_ms(registers[index].pause_ms);
} }
} }
return true; return true;
} }
bool FRToSI2C::wakePart(uint16_t DevAddress) { bool FRToSI2C::wakePart(uint16_t DevAddress) {
// wakepart is a special case where only the device address is sent // wakepart is a special case where only the device address is sent
if (!lock()) if (!lock())
return false; return false;
i2c_interrupt_disable(I2C0, I2C_INT_ERR); i2c_interrupt_disable(I2C0, I2C_INT_ERR);
i2c_interrupt_disable(I2C0, I2C_INT_EV); i2c_interrupt_disable(I2C0, I2C_INT_EV);
i2c_interrupt_disable(I2C0, I2C_INT_BUF); i2c_interrupt_disable(I2C0, I2C_INT_BUF);
uint8_t state = I2C_START; uint8_t state = I2C_START;
uint16_t timeout = 0; uint16_t timeout = 0;
bool done = false; bool done = false;
bool timedout = false; bool timedout = false;
while (!(done || timedout)) { while (!(done || timedout)) {
switch (state) { switch (state) {
case I2C_START: case I2C_START:
/* i2c master sends start signal only when the bus is idle */ /* i2c master sends start signal only when the bus is idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT )) { while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
i2c_start_on_bus(I2C0); i2c_start_on_bus(I2C0);
timeout = 0; timeout = 0;
state = I2C_SEND_ADDRESS; state = I2C_SEND_ADDRESS;
} else { } else {
I2C_Unstick(); I2C_Unstick();
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
} }
break; break;
case I2C_SEND_ADDRESS: case I2C_SEND_ADDRESS:
/* i2c master sends START signal successfully */ /* i2c master sends START signal successfully */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT )) { while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER); i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
timeout = 0; timeout = 0;
state = I2C_CLEAR_ADDRESS_FLAG; state = I2C_CLEAR_ADDRESS_FLAG;
} else { } else {
timedout = true; timedout = true;
done = true; done = true;
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
} }
break; break;
case I2C_CLEAR_ADDRESS_FLAG: case I2C_CLEAR_ADDRESS_FLAG:
/* address flag set means i2c slave sends ACK */ /* address flag set means i2c slave sends ACK */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT )) { while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) { if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_AERR); i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_stop_on_bus(I2C0); i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */ /* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) { while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
// Address NACK'd // Address NACK'd
unlock(); unlock();
return false; return false;
} }
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
timeout = 0; timeout = 0;
state = I2C_STOP; state = I2C_STOP;
} else { } else {
// Dont retry as this means a NAK // Dont retry as this means a NAK
i2c_stop_on_bus(I2C0); i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */ /* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) { while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
unlock(); unlock();
return false; return false;
} }
break; break;
case I2C_STOP: case I2C_STOP:
/* send a stop condition to I2C bus */ /* send a stop condition to I2C bus */
i2c_stop_on_bus(I2C0); i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */ /* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) { while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout < I2C_TIME_OUT) {
timeout = 0; timeout = 0;
state = I2C_END; state = I2C_END;
done = true; done = true;
} else { } else {
timedout = true; timedout = true;
done = true; done = true;
timeout = 0; timeout = 0;
state = I2C_START; state = I2C_START;
} }
break; break;
default: default:
state = I2C_START; state = I2C_START;
timeout = 0; timeout = 0;
break; break;
} }
} }
unlock(); unlock();
return timedout == false; return timedout == false;
} }

160
source/Core/BSP/Pine64/IRQ.cpp
View File

@@ -8,119 +8,117 @@
#include "IRQ.h" #include "IRQ.h"
#include "Pins.h" #include "Pins.h"
#include "int_n.h" #include "int_n.h"
volatile uint8_t i2c_read_process = 0; volatile uint8_t i2c_read_process = 0;
volatile uint8_t i2c_write_process = 0; volatile uint8_t i2c_write_process = 0;
volatile uint8_t i2c_slave_address = 0; volatile uint8_t i2c_slave_address = 0;
volatile uint8_t i2c_error_code = 0; volatile uint8_t i2c_error_code = 0;
volatile uint8_t *i2c_write; volatile uint8_t *i2c_write;
volatile uint8_t *i2c_read; volatile uint8_t *i2c_read;
volatile uint16_t i2c_nbytes; volatile uint16_t i2c_nbytes;
volatile uint16_t i2c_write_dress; volatile uint16_t i2c_write_dress;
volatile uint16_t i2c_read_dress; volatile uint16_t i2c_read_dress;
volatile uint8_t i2c_process_flag = 0; volatile uint8_t i2c_process_flag = 0;
void ADC0_1_IRQHandler(void) { void ADC0_1_IRQHandler(void) {
adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC); adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC);
// unblock the PID controller thread // unblock the PID controller thread
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
BaseType_t xHigherPriorityTaskWoken = pdFALSE; BaseType_t xHigherPriorityTaskWoken = pdFALSE;
if (pidTaskNotification) { if (pidTaskNotification) {
vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken); vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken); portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
} }
} }
} }
volatile uint16_t PWMSafetyTimer = 0; volatile uint16_t PWMSafetyTimer = 0;
volatile uint8_t pendingPWM = 0; volatile uint8_t pendingPWM = 0;
void TIMER1_IRQHandler(void) { void TIMER1_IRQHandler(void) {
if (timer_interrupt_flag_get(TIMER1, TIMER_INT_UP) == SET) { if (timer_interrupt_flag_get(TIMER1, TIMER_INT_UP) == SET) {
timer_interrupt_flag_clear(TIMER1, TIMER_INT_UP); timer_interrupt_flag_clear(TIMER1, TIMER_INT_UP);
// rollover turn on output if required // rollover turn on output if required
if (PWMSafetyTimer && pendingPWM) { if (PWMSafetyTimer && pendingPWM) {
timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 50); timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 50);
} }
if (PWMSafetyTimer) { if (PWMSafetyTimer) {
PWMSafetyTimer--; PWMSafetyTimer--;
} }
} }
if (timer_interrupt_flag_get(TIMER1, TIMER_INT_CH1) == SET) { if (timer_interrupt_flag_get(TIMER1, TIMER_INT_CH1) == SET) {
timer_interrupt_flag_clear(TIMER1, TIMER_INT_CH1); timer_interrupt_flag_clear(TIMER1, TIMER_INT_CH1);
// This is triggered on pwm setpoint trigger; we want to copy the pending // This is triggered on pwm setpoint trigger; we want to copy the pending
// PWM value into the output control reg // PWM value into the output control reg
timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0); timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0);
if (pendingPWM) { if (pendingPWM) {
timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, pendingPWM); timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, pendingPWM);
} }
} }
} }
void setTipPWM(uint8_t pulse) { void setTipPWM(uint8_t pulse) {
PWMSafetyTimer = 10; // This is decremented in the handler for PWM so that the tip pwm is PWMSafetyTimer = 10; // This is decremented in the handler for PWM so that the tip pwm is
// disabled if the PID task is not scheduled often enough. // disabled if the PID task is not scheduled often enough.
pendingPWM = pulse; pendingPWM = pulse;
} }
static bool fastPWM; static bool fastPWM;
static void switchToFastPWM(void) { static void switchToFastPWM(void) {
fastPWM = true; fastPWM = true;
totalPWM = powerPWM + tempMeasureTicks * 2; totalPWM = powerPWM + tempMeasureTicks * 2;
TIMER_CAR(TIMER1) = (uint32_t) totalPWM; TIMER_CAR(TIMER1) = (uint32_t)totalPWM;
// ~3.5 Hz rate // ~3.5 Hz rate
TIMER_CH0CV(TIMER1) = powerPWM + holdoffTicks * 2; TIMER_CH0CV(TIMER1) = powerPWM + holdoffTicks * 2;
// 1 kHz tick rate // 1 kHz tick rate
TIMER_PSC(TIMER1) = 12000; TIMER_PSC(TIMER1) = 12000;
/* generate an update event */ /* generate an update event */
TIMER_SWEVG(TIMER1) |= (uint32_t) TIMER_SWEVG_UPG; TIMER_SWEVG(TIMER1) |= (uint32_t)TIMER_SWEVG_UPG;
} }
static void switchToSlowPWM(void) { static void switchToSlowPWM(void) {
fastPWM = false; fastPWM = false;
totalPWM = powerPWM + tempMeasureTicks; totalPWM = powerPWM + tempMeasureTicks;
TIMER_CAR(TIMER1) = (uint32_t) totalPWM; TIMER_CAR(TIMER1) = (uint32_t)totalPWM;
// ~1.84 Hz rate // ~1.84 Hz rate
TIMER_CH0CV(TIMER1) = powerPWM + holdoffTicks; TIMER_CH0CV(TIMER1) = powerPWM + holdoffTicks;
// 500 Hz tick rate // 500 Hz tick rate
TIMER_PSC(TIMER1) = 24000; TIMER_PSC(TIMER1) = 24000;
/* generate an update event */ /* generate an update event */
TIMER_SWEVG(TIMER1) |= (uint32_t) TIMER_SWEVG_UPG; TIMER_SWEVG(TIMER1) |= (uint32_t)TIMER_SWEVG_UPG;
} }
bool tryBetterPWM(uint8_t pwm) { bool tryBetterPWM(uint8_t pwm) {
if (fastPWM && pwm == powerPWM) { if (fastPWM && pwm == powerPWM) {
// maximum power for fast PWM reached, need to go slower to get more // maximum power for fast PWM reached, need to go slower to get more
switchToSlowPWM(); switchToSlowPWM();
return true; return true;
} else if (!fastPWM && pwm < 230) { } else if (!fastPWM && pwm < 230) {
// 254 in fast PWM mode gives the same power as 239 in slow // 254 in fast PWM mode gives the same power as 239 in slow
// allow for some reasonable hysteresis by switching only when it goes // allow for some reasonable hysteresis by switching only when it goes
// below 230 (equivalent to 245 in fast mode) // below 230 (equivalent to 245 in fast mode)
switchToFastPWM(); switchToFastPWM();
return true; return true;
} }
return false; return false;
} }
void EXTI5_9_IRQHandler(void) { void EXTI5_9_IRQHandler(void) {
#ifdef POW_PD #ifdef POW_PD
if (RESET != exti_interrupt_flag_get(EXTI_5)) { if (RESET != exti_interrupt_flag_get(EXTI_5)) {
exti_interrupt_flag_clear(EXTI_5); exti_interrupt_flag_clear(EXTI_5);
if (RESET == gpio_input_bit_get(FUSB302_IRQ_GPIO_Port, FUSB302_IRQ_Pin)) { if (RESET == gpio_input_bit_get(FUSB302_IRQ_GPIO_Port, FUSB302_IRQ_Pin)) {
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
InterruptHandler::irqCallback(); InterruptHandler::irqCallback();
} }
} }
} }
#endif #endif
} }
// These are unused for now // These are unused for now
void I2C0_EV_IRQHandler(void) { void I2C0_EV_IRQHandler(void) {}
}
void I2C0_ER_IRQHandler(void) { void I2C0_ER_IRQHandler(void) {}
}

42
source/Core/BSP/Pine64/IRQ.h
View File

@@ -25,31 +25,31 @@ void I2C0_EV_IRQHandler(void);
/* handle I2C0 error interrupt request */ /* handle I2C0 error interrupt request */
void I2C0_ER_IRQHandler(void); void I2C0_ER_IRQHandler(void);
typedef enum { typedef enum {
I2C_SEND_ADDRESS_FIRST = 0, //Sending slave address I2C_SEND_ADDRESS_FIRST = 0, // Sending slave address
I2C_CLEAR_ADDRESS_FLAG_FIRST, // Clear address send I2C_CLEAR_ADDRESS_FLAG_FIRST, // Clear address send
I2C_TRANSMIT_WRITE_READ_ADD, //Transmit the memory address to read/write from I2C_TRANSMIT_WRITE_READ_ADD, // Transmit the memory address to read/write from
I2C_SEND_ADDRESS_SECOND, //Send address again for read I2C_SEND_ADDRESS_SECOND, // Send address again for read
I2C_CLEAR_ADDRESS_FLAG_SECOND, //Clear address again I2C_CLEAR_ADDRESS_FLAG_SECOND, // Clear address again
I2C_TRANSMIT_DATA, //Transmit recieve data I2C_TRANSMIT_DATA, // Transmit recieve data
I2C_STOP, //Send stop I2C_STOP, // Send stop
I2C_ABORTED, // I2C_ABORTED, //
I2C_DONE,// I2C transfer is complete I2C_DONE, // I2C transfer is complete
I2C_START , I2C_START,
I2C_END, I2C_END,
I2C_OK, I2C_OK,
I2C_SEND_ADDRESS, I2C_SEND_ADDRESS,
I2C_CLEAR_ADDRESS_FLAG, I2C_CLEAR_ADDRESS_FLAG,
} i2c_process_enum; } i2c_process_enum;
extern volatile uint8_t i2c_slave_address; extern volatile uint8_t i2c_slave_address;
extern volatile uint8_t i2c_read_process; extern volatile uint8_t i2c_read_process;
extern volatile uint8_t i2c_write_process; extern volatile uint8_t i2c_write_process;
extern volatile uint8_t i2c_error_code; extern volatile uint8_t i2c_error_code;
extern volatile uint8_t* i2c_write; extern volatile uint8_t *i2c_write;
extern volatile uint8_t* i2c_read; extern volatile uint8_t *i2c_read;
extern volatile uint16_t i2c_nbytes; extern volatile uint16_t i2c_nbytes;
extern volatile uint16_t i2c_write_dress; extern volatile uint16_t i2c_write_dress;
extern volatile uint16_t i2c_read_dress; extern volatile uint16_t i2c_read_dress;
extern volatile uint8_t i2c_process_flag; extern volatile uint8_t i2c_process_flag;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

53
source/Core/BSP/Pine64/Pins.h
View File

@@ -9,46 +9,45 @@
#define BSP_MINIWARE_PINS_H_ #define BSP_MINIWARE_PINS_H_
#include "gd32vf103_gpio.h" #include "gd32vf103_gpio.h"
#define KEY_B_Pin BIT(1) #define KEY_B_Pin BIT(1)
#define KEY_B_GPIO_Port GPIOB #define KEY_B_GPIO_Port GPIOB
#define TMP36_INPUT_Pin BIT(4) #define TMP36_INPUT_Pin BIT(4)
#define TMP36_INPUT_GPIO_Port GPIOA #define TMP36_INPUT_GPIO_Port GPIOA
#define TMP36_ADC0_CHANNEL ADC_CHANNEL_4 #define TMP36_ADC0_CHANNEL ADC_CHANNEL_4
#define TMP36_ADC1_CHANNEL ADC_CHANNEL_4 #define TMP36_ADC1_CHANNEL ADC_CHANNEL_4
#define TIP_TEMP_Pin BIT(1) #define TIP_TEMP_Pin BIT(1)
#define TIP_TEMP_GPIO_Port GPIOA #define TIP_TEMP_GPIO_Port GPIOA
#define TIP_TEMP_ADC0_CHANNEL ADC_CHANNEL_1 #define TIP_TEMP_ADC0_CHANNEL ADC_CHANNEL_1
#define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_1 #define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_1
#define VIN_Pin BIT(0) #define VIN_Pin BIT(0)
#define VIN_GPIO_Port GPIOA #define VIN_GPIO_Port GPIOA
#define VIN_ADC0_CHANNEL ADC_CHANNEL_0 #define VIN_ADC0_CHANNEL ADC_CHANNEL_0
#define VIN_ADC1_CHANNEL ADC_CHANNEL_0 #define VIN_ADC1_CHANNEL ADC_CHANNEL_0
#define OLED_RESET_Pin BIT(9) #define OLED_RESET_Pin BIT(9)
#define OLED_RESET_GPIO_Port GPIOA #define OLED_RESET_GPIO_Port GPIOA
#define KEY_A_Pin BIT(0) #define KEY_A_Pin BIT(0)
#define KEY_A_GPIO_Port GPIOB #define KEY_A_GPIO_Port GPIOB
#define PWM_Out_Pin BIT(6) #define PWM_Out_Pin BIT(6)
#define PWM_Out_GPIO_Port GPIOA #define PWM_Out_GPIO_Port GPIOA
#define SCL_Pin BIT(6) #define SCL_Pin BIT(6)
#define SCL_GPIO_Port GPIOB #define SCL_GPIO_Port GPIOB
#define SDA_Pin BIT(7) #define SDA_Pin BIT(7)
#define SDA_GPIO_Port GPIOB #define SDA_GPIO_Port GPIOB
#define USB_DM_Pin BIT(11)
#define USB_DM_Pin BIT(11)
#define USB_DM_LOW_GPIO_Port GPIOA #define USB_DM_LOW_GPIO_Port GPIOA
#define QC_DP_LOW_Pin BIT(7) #define QC_DP_LOW_Pin BIT(7)
#define QC_DP_LOW_GPIO_Port GPIOA #define QC_DP_LOW_GPIO_Port GPIOA
// LOW = low resistance, HIGH = high resistance // LOW = low resistance, HIGH = high resistance
#define QC_DM_LOW_Pin BIT(8) #define QC_DM_LOW_Pin BIT(8)
#define QC_DM_LOW_GPIO_Port GPIOA #define QC_DM_LOW_GPIO_Port GPIOA
#define QC_DM_HIGH_Pin BIT(10) #define QC_DM_HIGH_Pin BIT(10)
#define QC_DM_HIGH_GPIO_Port GPIOA #define QC_DM_HIGH_GPIO_Port GPIOA
#define FUSB302_IRQ_Pin BIT(5) #define FUSB302_IRQ_Pin BIT(5)
#define FUSB302_IRQ_GPIO_Port GPIOB #define FUSB302_IRQ_GPIO_Port GPIOB
#endif /* BSP_MINIWARE_PINS_H_ */ #endif /* BSP_MINIWARE_PINS_H_ */

54
source/Core/BSP/Pine64/Power.cpp
View File

@@ -1,49 +1,49 @@
#include "BSP.h" #include "BSP.h"
#include "BSP_Power.h" #include "BSP_Power.h"
#include "Model_Config.h"
#include "Pins.h"
#include "QC3.h" #include "QC3.h"
#include "Settings.h" #include "Settings.h"
#include "Pins.h"
#include "fusbpd.h" #include "fusbpd.h"
#include "Model_Config.h"
#include "policy_engine.h"
#include "int_n.h" #include "int_n.h"
#include "policy_engine.h"
bool FUSB302_present = false; bool FUSB302_present = false;
void power_check() { void power_check() {
#ifdef POW_PD #ifdef POW_PD
if (FUSB302_present) { if (FUSB302_present) {
//Cant start QC until either PD works or fails // Cant start QC until either PD works or fails
if (PolicyEngine::setupCompleteOrTimedOut() == false) { if (PolicyEngine::setupCompleteOrTimedOut() == false) {
return; return;
} }
if (PolicyEngine::pdHasNegotiated()) { if (PolicyEngine::pdHasNegotiated()) {
return; return;
} }
} }
#endif #endif
#ifdef POW_QC #ifdef POW_QC
QC_resync(); QC_resync();
#endif #endif
} }
uint8_t usb_pd_detect() { uint8_t usb_pd_detect() {
#ifdef POW_PD #ifdef POW_PD
FUSB302_present = fusb302_detect(); FUSB302_present = fusb302_detect();
return FUSB302_present; return FUSB302_present;
#endif #endif
return false; return false;
} }
bool getIsPoweredByDCIN() { bool getIsPoweredByDCIN() {
//We return false until we are sure we are not using PD // We return false until we are sure we are not using PD
if (PolicyEngine::setupCompleteOrTimedOut() == false) { if (PolicyEngine::setupCompleteOrTimedOut() == false) {
return false; return false;
} }
if (PolicyEngine::pdHasNegotiated()) { if (PolicyEngine::pdHasNegotiated()) {
return false; // We are using PD return false; // We are using PD
} }
if (hasQCNegotiated()) { if (hasQCNegotiated()) {
return false; // We are using QC return false; // We are using QC
} }
return true; return true;
} }

62
source/Core/BSP/Pine64/QC_GPIO.cpp
View File

@@ -4,63 +4,55 @@
* Created on: 29 May 2020 * Created on: 29 May 2020
* Author: Ralim * Author: Ralim
*/ */
#include "gd32vf103_libopt.h"
#include "BSP.h" #include "BSP.h"
#include "Pins.h" #include "Pins.h"
#include "QC3.h" #include "QC3.h"
#include "Settings.h" #include "Settings.h"
#include "gd32vf103_libopt.h"
#ifdef POW_QC #ifdef POW_QC
void QC_DPlusZero_Six() { void QC_DPlusZero_Six() {
// pull down D+ // pull down D+
gpio_bit_reset(QC_DP_LOW_GPIO_Port, QC_DP_LOW_Pin); gpio_bit_reset(QC_DP_LOW_GPIO_Port, QC_DP_LOW_Pin);
} }
void QC_DNegZero_Six() { void QC_DNegZero_Six() {
gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin); gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin);
gpio_bit_reset(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin); gpio_bit_reset(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin);
} }
void QC_DPlusThree_Three() { void QC_DPlusThree_Three() {
// pull up D+ // pull up D+
gpio_bit_set(QC_DP_LOW_GPIO_Port, QC_DP_LOW_Pin); gpio_bit_set(QC_DP_LOW_GPIO_Port, QC_DP_LOW_Pin);
} }
void QC_DNegThree_Three() { void QC_DNegThree_Three() {
gpio_bit_set(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin); gpio_bit_set(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin);
gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin); gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin);
}
void QC_DM_PullDown() {
gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, USB_DM_Pin);
}
void QC_DM_No_PullDown() {
gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_2MHZ, USB_DM_Pin);
} }
void QC_DM_PullDown() { gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, USB_DM_Pin); }
void QC_DM_No_PullDown() { gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_2MHZ, USB_DM_Pin); }
void QC_Init_GPIO() { void QC_Init_GPIO() {
// Setup any GPIO into the right states for QC // Setup any GPIO into the right states for QC
//D+ pulldown as output // D+ pulldown as output
gpio_init(QC_DP_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DP_LOW_Pin); gpio_init(QC_DP_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DP_LOW_Pin);
//Make two D- pins floating // Make two D- pins floating
QC_DM_PullDown(); QC_DM_PullDown();
} }
void QC_Post_Probe_En() { void QC_Post_Probe_En() {
//Make two D- pins outputs // Make two D- pins outputs
gpio_init(QC_DM_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_LOW_Pin); gpio_init(QC_DM_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_LOW_Pin);
gpio_init(QC_DM_HIGH_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_HIGH_Pin); gpio_init(QC_DM_HIGH_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_HIGH_Pin);
} }
uint8_t QC_DM_PulledDown() { uint8_t QC_DM_PulledDown() { return gpio_input_bit_get(USB_DM_LOW_GPIO_Port, USB_DM_Pin) == RESET ? 1 : 0; }
return gpio_input_bit_get(USB_DM_LOW_GPIO_Port, USB_DM_Pin) == RESET ? 1 : 0;
}
#endif #endif
void QC_resync() { void QC_resync() {
#ifdef POW_QC #ifdef POW_QC
uint8_t targetvoltage = 90; uint8_t targetvoltage = 90;
if (systemSettings.QCIdealVoltage == 1) { if (systemSettings.QCIdealVoltage == 1) {
targetvoltage = 120; targetvoltage = 120;
} else if (systemSettings.QCIdealVoltage == 2) { } else if (systemSettings.QCIdealVoltage == 2) {
targetvoltage = 200; targetvoltage = 200;
} }
seekQC(targetvoltage, systemSettings.voltageDiv); // Run the QC seek again if we have drifted too much seekQC(targetvoltage, systemSettings.voltageDiv); // Run the QC seek again if we have drifted too much
#endif #endif
} }

470
source/Core/BSP/Pine64/Setup.cpp
View File

@@ -10,9 +10,8 @@
#include "gd32vf103.h" #include "gd32vf103.h"
#include <string.h> #include <string.h>
#define ADC_NORM_CHANNELS 2 #define ADC_NORM_CHANNELS 2
#define ADC_NORM_SAMPLES 32 #define ADC_NORM_SAMPLES 32
uint16_t ADCReadings[ADC_NORM_SAMPLES * uint16_t ADCReadings[ADC_NORM_SAMPLES * ADC_NORM_CHANNELS]; // room for 32 lots of the pair of readings
ADC_NORM_CHANNELS]; // room for 32 lots of the pair of readings
// Functions // Functions
void setup_gpio(); void setup_gpio();
@@ -23,282 +22,263 @@ void setup_timers();
void setup_iwdg(); void setup_iwdg();
void hardware_init() { void hardware_init() {
// GPIO // GPIO
setup_gpio(); setup_gpio();
// DMA // DMA
setup_dma(); setup_dma();
// I2C // I2C
setup_i2c(); setup_i2c();
// ADC's // ADC's
setup_adc(); setup_adc();
// Timers // Timers
setup_timers(); setup_timers();
// Watchdog // Watchdog
setup_iwdg(); setup_iwdg();
/* enable TIMER1 - PWM control timing*/ /* enable TIMER1 - PWM control timing*/
timer_enable(TIMER1); timer_enable(TIMER1);
timer_enable(TIMER2); timer_enable(TIMER2);
} }
// channel 0 -> temperature sensor, 1-> VIN // channel 0 -> temperature sensor, 1-> VIN
uint16_t getADC(uint8_t channel) { uint16_t getADC(uint8_t channel) {
uint32_t sum = 0; uint32_t sum = 0;
for (uint8_t i = 0; i < ADC_NORM_SAMPLES; i++) for (uint8_t i = 0; i < ADC_NORM_SAMPLES; i++)
sum += ADCReadings[channel + (i * ADC_NORM_CHANNELS)]; sum += ADCReadings[channel + (i * ADC_NORM_CHANNELS)];
return sum >> 2; return sum >> 2;
} }
void setup_gpio() { void setup_gpio() {
/* enable GPIOB clock */ /* enable GPIOB clock */
rcu_periph_clock_enable(RCU_GPIOA); rcu_periph_clock_enable(RCU_GPIOA);
/* enable GPIOB clock */ /* enable GPIOB clock */
rcu_periph_clock_enable(RCU_GPIOB); rcu_periph_clock_enable(RCU_GPIOB);
// Alternate function clock enable // Alternate function clock enable
rcu_periph_clock_enable(RCU_AF); rcu_periph_clock_enable(RCU_AF);
// Buttons as input // Buttons as input
gpio_init(KEY_A_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_A_Pin); gpio_init(KEY_A_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_A_Pin);
gpio_init(KEY_B_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_B_Pin); gpio_init(KEY_B_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_B_Pin);
// OLED reset as output // OLED reset as output
gpio_init(OLED_RESET_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, gpio_init(OLED_RESET_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, OLED_RESET_Pin);
OLED_RESET_Pin); gpio_bit_set(SDA_GPIO_Port, SDA_Pin);
gpio_bit_set(SDA_GPIO_Port, SDA_Pin); gpio_bit_set(SDA_GPIO_Port, SCL_Pin);
gpio_bit_set(SDA_GPIO_Port, SCL_Pin); // I2C as AF Open Drain
// I2C as AF Open Drain gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_2MHZ, SDA_Pin | SCL_Pin);
gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_2MHZ, // PWM output as AF Push Pull
SDA_Pin | SCL_Pin); gpio_init(PWM_Out_GPIO_Port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, PWM_Out_Pin);
// PWM output as AF Push Pull // Analog Inputs ... as analog inputs
gpio_init(PWM_Out_GPIO_Port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, gpio_init(TMP36_INPUT_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, TMP36_INPUT_Pin);
PWM_Out_Pin); gpio_init(TIP_TEMP_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, TIP_TEMP_Pin);
// Analog Inputs ... as analog inputs gpio_init(VIN_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, VIN_Pin);
gpio_init(TMP36_INPUT_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ,
TMP36_INPUT_Pin);
gpio_init(TIP_TEMP_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ,
TIP_TEMP_Pin);
gpio_init(VIN_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, VIN_Pin);
// Remap PB4 away from JTAG NJRST // Remap PB4 away from JTAG NJRST
gpio_pin_remap_config(GPIO_SWJ_NONJTRST_REMAP, ENABLE); gpio_pin_remap_config(GPIO_SWJ_NONJTRST_REMAP, ENABLE);
// TODO - rest of pins as floating // TODO - rest of pins as floating
} }
void setup_dma() { void setup_dma() {
// Setup DMA for ADC0 // Setup DMA for ADC0
{ {
/* enable DMA0 clock */ /* enable DMA0 clock */
rcu_periph_clock_enable(RCU_DMA0); rcu_periph_clock_enable(RCU_DMA0);
rcu_periph_clock_enable(RCU_DMA1); rcu_periph_clock_enable(RCU_DMA1);
/* ADC_DMA_channel configuration */ /* ADC_DMA_channel configuration */
dma_parameter_struct dma_data_parameter; dma_parameter_struct dma_data_parameter;
/* ADC DMA_channel configuration */ /* ADC DMA_channel configuration */
dma_deinit(DMA0, DMA_CH0); dma_deinit(DMA0, DMA_CH0);
/* initialize DMA data mode */ /* initialize DMA data mode */
dma_data_parameter.periph_addr = (uint32_t) (&ADC_RDATA(ADC0)); dma_data_parameter.periph_addr = (uint32_t)(&ADC_RDATA(ADC0));
dma_data_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE; dma_data_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_data_parameter.memory_addr = (uint32_t) (ADCReadings); dma_data_parameter.memory_addr = (uint32_t)(ADCReadings);
dma_data_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE; dma_data_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_data_parameter.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; dma_data_parameter.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
dma_data_parameter.memory_width = DMA_MEMORY_WIDTH_16BIT; dma_data_parameter.memory_width = DMA_MEMORY_WIDTH_16BIT;
dma_data_parameter.direction = DMA_PERIPHERAL_TO_MEMORY; dma_data_parameter.direction = DMA_PERIPHERAL_TO_MEMORY;
dma_data_parameter.number = ADC_NORM_SAMPLES * ADC_NORM_CHANNELS; dma_data_parameter.number = ADC_NORM_SAMPLES * ADC_NORM_CHANNELS;
dma_data_parameter.priority = DMA_PRIORITY_HIGH; dma_data_parameter.priority = DMA_PRIORITY_HIGH;
dma_init(DMA0, DMA_CH0, &dma_data_parameter); dma_init(DMA0, DMA_CH0, &dma_data_parameter);
dma_circulation_enable(DMA0, DMA_CH0); dma_circulation_enable(DMA0, DMA_CH0);
/* enable DMA channel */ /* enable DMA channel */
dma_channel_enable(DMA0, DMA_CH0); dma_channel_enable(DMA0, DMA_CH0);
} }
} }
void setup_i2c() { void setup_i2c() {
/* enable I2C0 clock */ /* enable I2C0 clock */
rcu_periph_clock_enable(RCU_I2C0); rcu_periph_clock_enable(RCU_I2C0);
// Setup I20 at 400kHz // Setup I20 at 400kHz
i2c_clock_config(I2C0, 400 * 1000, I2C_DTCY_2); i2c_clock_config(I2C0, 400 * 1000, I2C_DTCY_2);
i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, 0x00); i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, 0x00);
i2c_enable(I2C0); i2c_enable(I2C0);
/* enable acknowledge */ /* enable acknowledge */
i2c_ack_config(I2C0, I2C_ACK_ENABLE); i2c_ack_config(I2C0, I2C_ACK_ENABLE);
eclic_irq_enable(I2C0_EV_IRQn, 1, 0); eclic_irq_enable(I2C0_EV_IRQn, 1, 0);
eclic_irq_enable(I2C0_ER_IRQn, 2, 0); eclic_irq_enable(I2C0_ER_IRQn, 2, 0);
} }
void setup_adc() { void setup_adc() {
// Setup ADC in normal + injected mode // Setup ADC in normal + injected mode
// Want it to sample handle temp and input voltage normally via dma // Want it to sample handle temp and input voltage normally via dma
// Then injected trigger to sample tip temp // Then injected trigger to sample tip temp
memset(ADCReadings, 0, sizeof(ADCReadings)); memset(ADCReadings, 0, sizeof(ADCReadings));
rcu_periph_clock_enable(RCU_ADC0); rcu_periph_clock_enable(RCU_ADC0);
rcu_periph_clock_enable(RCU_ADC1); rcu_periph_clock_enable(RCU_ADC1);
adc_deinit(ADC0); adc_deinit(ADC0);
adc_deinit(ADC1); adc_deinit(ADC1);
/* config ADC clock */ /* config ADC clock */
rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV16); rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV16);
// Run in normal parallel + inserted parallel // Run in normal parallel + inserted parallel
adc_mode_config(ADC0, ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL); adc_mode_config(ADC0, ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL);
adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE); adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE);
adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE); adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE);
adc_special_function_config(ADC1, ADC_CONTINUOUS_MODE, ENABLE); adc_special_function_config(ADC1, ADC_CONTINUOUS_MODE, ENABLE);
adc_special_function_config(ADC1, ADC_SCAN_MODE, ENABLE); adc_special_function_config(ADC1, ADC_SCAN_MODE, ENABLE);
// Align right // Align right
adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT);
adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT); adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT);
// Setup reading 2 channels on regular mode (Handle Temp + dc in) // Setup reading 2 channels on regular mode (Handle Temp + dc in)
adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, ADC_NORM_CHANNELS); adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, ADC_NORM_CHANNELS);
adc_channel_length_config(ADC1, ADC_REGULAR_CHANNEL, ADC_NORM_CHANNELS); adc_channel_length_config(ADC1, ADC_REGULAR_CHANNEL, ADC_NORM_CHANNELS);
// Setup the two channels // Setup the two channels
adc_regular_channel_config(ADC0, 0, TMP36_ADC0_CHANNEL, adc_regular_channel_config(ADC0, 0, TMP36_ADC0_CHANNEL,
ADC_SAMPLETIME_71POINT5); // temp sensor ADC_SAMPLETIME_71POINT5); // temp sensor
adc_regular_channel_config(ADC1, 0, TMP36_ADC1_CHANNEL, adc_regular_channel_config(ADC1, 0, TMP36_ADC1_CHANNEL,
ADC_SAMPLETIME_71POINT5); // temp sensor ADC_SAMPLETIME_71POINT5); // temp sensor
adc_regular_channel_config(ADC0, 1, VIN_ADC0_CHANNEL, adc_regular_channel_config(ADC0, 1, VIN_ADC0_CHANNEL,
ADC_SAMPLETIME_71POINT5); // DC Input voltage ADC_SAMPLETIME_71POINT5); // DC Input voltage
adc_regular_channel_config(ADC1, 1, VIN_ADC1_CHANNEL, adc_regular_channel_config(ADC1, 1, VIN_ADC1_CHANNEL,
ADC_SAMPLETIME_71POINT5); // DC Input voltage ADC_SAMPLETIME_71POINT5); // DC Input voltage
// Setup that we want all 4 inserted readings to be the tip temp // Setup that we want all 4 inserted readings to be the tip temp
adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 4); adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 4);
adc_channel_length_config(ADC1, ADC_INSERTED_CHANNEL, 4); adc_channel_length_config(ADC1, ADC_INSERTED_CHANNEL, 4);
for (int rank = 0; rank < 4; rank++) { for (int rank = 0; rank < 4; rank++) {
adc_inserted_channel_config(ADC0, rank, TIP_TEMP_ADC0_CHANNEL, adc_inserted_channel_config(ADC0, rank, TIP_TEMP_ADC0_CHANNEL, ADC_SAMPLETIME_1POINT5);
ADC_SAMPLETIME_1POINT5); adc_inserted_channel_config(ADC1, rank, TIP_TEMP_ADC1_CHANNEL, ADC_SAMPLETIME_1POINT5);
adc_inserted_channel_config(ADC1, rank, TIP_TEMP_ADC1_CHANNEL, }
ADC_SAMPLETIME_1POINT5); // Setup timer 1 channel 0 to trigger injected measurements
} adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_T1_CH0);
// Setup timer 1 channel 0 to trigger injected measurements adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_T1_CH0);
adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL,
ADC0_1_EXTTRIG_INSERTED_T1_CH0);
adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL,
ADC0_1_EXTTRIG_INSERTED_T1_CH0);
adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE);
ADC0_1_EXTTRIG_REGULAR_NONE); adc_external_trigger_source_config(ADC1, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE);
adc_external_trigger_source_config(ADC1, ADC_REGULAR_CHANNEL, // Enable triggers for the ADC
ADC0_1_EXTTRIG_REGULAR_NONE); adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE);
// Enable triggers for the ADC adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ENABLE);
adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE); adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE);
adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ENABLE); adc_external_trigger_config(ADC1, ADC_REGULAR_CHANNEL, ENABLE);
adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE);
adc_external_trigger_config(ADC1, ADC_REGULAR_CHANNEL, ENABLE);
adc_watchdog_disable(ADC0); adc_watchdog_disable(ADC0);
adc_watchdog_disable(ADC1); adc_watchdog_disable(ADC1);
adc_resolution_config(ADC0, ADC_RESOLUTION_12B); adc_resolution_config(ADC0, ADC_RESOLUTION_12B);
adc_resolution_config(ADC1, ADC_RESOLUTION_12B); adc_resolution_config(ADC1, ADC_RESOLUTION_12B);
/* clear the ADC flag */ /* clear the ADC flag */
adc_oversample_mode_disable(ADC0); adc_oversample_mode_disable(ADC0);
adc_oversample_mode_disable(ADC1); adc_oversample_mode_disable(ADC1);
adc_enable(ADC0); adc_enable(ADC0);
adc_calibration_enable(ADC0); adc_calibration_enable(ADC0);
adc_enable(ADC1); adc_enable(ADC1);
adc_calibration_enable(ADC1); adc_calibration_enable(ADC1);
adc_dma_mode_enable(ADC0); adc_dma_mode_enable(ADC0);
// Enable interrupt on end of injected readings // Enable interrupt on end of injected readings
adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOC); adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOC);
adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC); adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC);
adc_interrupt_enable(ADC0, ADC_INT_EOIC); adc_interrupt_enable(ADC0, ADC_INT_EOIC);
eclic_irq_enable(ADC0_1_IRQn, 2, 0); eclic_irq_enable(ADC0_1_IRQn, 2, 0);
adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL); adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL);
adc_software_trigger_enable(ADC1, ADC_REGULAR_CHANNEL); adc_software_trigger_enable(ADC1, ADC_REGULAR_CHANNEL);
adc_tempsensor_vrefint_disable(); adc_tempsensor_vrefint_disable();
} }
void setup_timers() { void setup_timers() {
// Setup timer 1 to run the actual PWM level // Setup timer 1 to run the actual PWM level
/* enable timer1 clock */ /* enable timer1 clock */
rcu_periph_clock_enable(RCU_TIMER1); rcu_periph_clock_enable(RCU_TIMER1);
rcu_periph_clock_enable(RCU_TIMER2); rcu_periph_clock_enable(RCU_TIMER2);
timer_oc_parameter_struct timer_ocintpara; timer_oc_parameter_struct timer_ocintpara;
timer_parameter_struct timer_initpara; timer_parameter_struct timer_initpara;
{ {
// deinit to reset the timer // deinit to reset the timer
timer_deinit(TIMER1); timer_deinit(TIMER1);
/* initialize TIMER init parameter struct */ /* initialize TIMER init parameter struct */
timer_struct_para_init(&timer_initpara); timer_struct_para_init(&timer_initpara);
/* TIMER1 configuration */ /* TIMER1 configuration */
timer_initpara.prescaler = 5000; timer_initpara.prescaler = 5000;
timer_initpara.alignedmode = TIMER_COUNTER_EDGE; timer_initpara.alignedmode = TIMER_COUNTER_EDGE;
timer_initpara.counterdirection = TIMER_COUNTER_UP; timer_initpara.counterdirection = TIMER_COUNTER_UP;
timer_initpara.period = powerPWM + tempMeasureTicks; timer_initpara.period = powerPWM + tempMeasureTicks;
timer_initpara.clockdivision = TIMER_CKDIV_DIV4; timer_initpara.clockdivision = TIMER_CKDIV_DIV4;
timer_initpara.repetitioncounter = 0; timer_initpara.repetitioncounter = 0;
timer_init(TIMER1, &timer_initpara); timer_init(TIMER1, &timer_initpara);
/* CH0 configured to implement the PWM irq's for the output control*/ /* CH0 configured to implement the PWM irq's for the output control*/
timer_channel_output_struct_para_init(&timer_ocintpara); timer_channel_output_struct_para_init(&timer_ocintpara);
timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
timer_ocintpara.outputstate = TIMER_CCX_ENABLE; timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocintpara); timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocintpara);
timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, powerPWM + holdoffTicks);
powerPWM + holdoffTicks); timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_PWM1);
timer_channel_output_mode_config(TIMER1, TIMER_CH_0, timer_channel_output_shadow_config(TIMER1, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE);
TIMER_OC_MODE_PWM1); /* CH1 used for irq */
timer_channel_output_shadow_config(TIMER1, TIMER_CH_0, timer_channel_output_struct_para_init(&timer_ocintpara);
TIMER_OC_SHADOW_DISABLE); timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
/* CH1 used for irq */ timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
timer_channel_output_struct_para_init(&timer_ocintpara); timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocintpara);
timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocintpara);
timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 0); timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 0);
timer_channel_output_mode_config(TIMER1, TIMER_CH_1, timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_PWM0);
TIMER_OC_MODE_PWM0); timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE);
timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, // IRQ
TIMER_OC_SHADOW_DISABLE); timer_interrupt_enable(TIMER1, TIMER_INT_UP);
// IRQ timer_interrupt_enable(TIMER1, TIMER_INT_CH1);
timer_interrupt_enable(TIMER1, TIMER_INT_UP); }
timer_interrupt_enable(TIMER1, TIMER_INT_CH1);
}
eclic_irq_enable(TIMER1_IRQn, 2, 5); eclic_irq_enable(TIMER1_IRQn, 2, 5);
// Setup timer 2 to control the output signal // Setup timer 2 to control the output signal
{ {
timer_deinit(TIMER2); timer_deinit(TIMER2);
/* initialize TIMER init parameter struct */ /* initialize TIMER init parameter struct */
timer_struct_para_init(&timer_initpara); timer_struct_para_init(&timer_initpara);
/* TIMER1 configuration */ /* TIMER1 configuration */
timer_initpara.prescaler = 200; timer_initpara.prescaler = 200;
timer_initpara.alignedmode = TIMER_COUNTER_EDGE; timer_initpara.alignedmode = TIMER_COUNTER_EDGE;
timer_initpara.counterdirection = TIMER_COUNTER_UP; timer_initpara.counterdirection = TIMER_COUNTER_UP;
timer_initpara.period = 100; timer_initpara.period = 100;
timer_initpara.clockdivision = TIMER_CKDIV_DIV4; timer_initpara.clockdivision = TIMER_CKDIV_DIV4;
timer_initpara.repetitioncounter = 0; timer_initpara.repetitioncounter = 0;
timer_init(TIMER2, &timer_initpara); timer_init(TIMER2, &timer_initpara);
/* CH0 configuration in PWM mode0 */ /* CH0 configuration in PWM mode0 */
timer_channel_output_struct_para_init(&timer_ocintpara); timer_channel_output_struct_para_init(&timer_ocintpara);
timer_ocintpara.outputstate = TIMER_CCX_ENABLE; timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE; timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE;
timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH;
timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW;
timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
timer_channel_output_config(TIMER2, TIMER_CH_0, &timer_ocintpara); timer_channel_output_config(TIMER2, TIMER_CH_0, &timer_ocintpara);
timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0); timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0);
timer_channel_output_mode_config(TIMER2, TIMER_CH_0, timer_channel_output_mode_config(TIMER2, TIMER_CH_0, TIMER_OC_MODE_PWM0);
TIMER_OC_MODE_PWM0); timer_channel_output_shadow_config(TIMER2, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE);
timer_channel_output_shadow_config(TIMER2, TIMER_CH_0, timer_auto_reload_shadow_enable(TIMER2);
TIMER_OC_SHADOW_DISABLE); timer_enable(TIMER2);
timer_auto_reload_shadow_enable(TIMER2); }
timer_enable(TIMER2);
}
} }
void setup_iwdg() { void setup_iwdg() {
fwdgt_config(0x0FFF, FWDGT_PSC_DIV256); fwdgt_config(0x0FFF, FWDGT_PSC_DIV256);
fwdgt_enable(); fwdgt_enable();
} }
void setupFUSBIRQ() { void setupFUSBIRQ() {
// Setup IRQ for USB-PD // Setup IRQ for USB-PD
gpio_init(FUSB302_IRQ_GPIO_Port, GPIO_MODE_IPU, GPIO_OSPEED_2MHZ, gpio_init(FUSB302_IRQ_GPIO_Port, GPIO_MODE_IPU, GPIO_OSPEED_2MHZ, FUSB302_IRQ_Pin);
FUSB302_IRQ_Pin); eclic_irq_enable(EXTI5_9_IRQn, 1, 1);
eclic_irq_enable(EXTI5_9_IRQn, 1, 1); /* connect key EXTI line to key GPIO pin */
/* connect key EXTI line to key GPIO pin */ gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOB, GPIO_PIN_SOURCE_5);
gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOB, GPIO_PIN_SOURCE_5);
/* configure key EXTI line */ /* configure key EXTI line */
exti_init(EXTI_5, EXTI_INTERRUPT, EXTI_TRIG_FALLING); exti_init(EXTI_5, EXTI_INTERRUPT, EXTI_TRIG_FALLING);
exti_interrupt_flag_clear(EXTI_5); exti_interrupt_flag_clear(EXTI_5);
} }

4
source/Core/BSP/Pine64/Setup.h
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@@ -14,8 +14,8 @@
extern "C" { extern "C" {
#endif #endif
uint16_t getADC(uint8_t channel); uint16_t getADC(uint8_t channel);
void hardware_init(); void hardware_init();
void setupFUSBIRQ(); void setupFUSBIRQ();
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

154
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_compatiable.h vendored
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@@ -22,7 +22,7 @@
* @brief ARM compatiable function definitions header file * @brief ARM compatiable function definitions header file
*/ */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ===== ARM Compatiable Functions ===== */ /* ===== ARM Compatiable Functions ===== */
@@ -37,27 +37,27 @@
* @{ * @{
*/ */
/** \brief Instruction Synchronization Barrier, compatiable with ARM */ /** \brief Instruction Synchronization Barrier, compatiable with ARM */
#define __ISB() __RWMB() #define __ISB() __RWMB()
/** \brief Data Synchronization Barrier, compatiable with ARM */ /** \brief Data Synchronization Barrier, compatiable with ARM */
#define __DSB() __RWMB() #define __DSB() __RWMB()
/** \brief Data Memory Barrier, compatiable with ARM */ /** \brief Data Memory Barrier, compatiable with ARM */
#define __DMB() __RWMB() #define __DMB() __RWMB()
/** \brief LDRT Unprivileged (8 bit), ARM Compatiable */ /** \brief LDRT Unprivileged (8 bit), ARM Compatiable */
#define __LDRBT(ptr) __LB((ptr)) #define __LDRBT(ptr) __LB((ptr))
/** \brief LDRT Unprivileged (16 bit), ARM Compatiable */ /** \brief LDRT Unprivileged (16 bit), ARM Compatiable */
#define __LDRHT(ptr) __LH((ptr)) #define __LDRHT(ptr) __LH((ptr))
/** \brief LDRT Unprivileged (32 bit), ARM Compatiable */ /** \brief LDRT Unprivileged (32 bit), ARM Compatiable */
#define __LDRT(ptr) __LW((ptr)) #define __LDRT(ptr) __LW((ptr))
/** \brief STRT Unprivileged (8 bit), ARM Compatiable */ /** \brief STRT Unprivileged (8 bit), ARM Compatiable */
#define __STRBT(ptr) __SB((ptr)) #define __STRBT(ptr) __SB((ptr))
/** \brief STRT Unprivileged (16 bit), ARM Compatiable */ /** \brief STRT Unprivileged (16 bit), ARM Compatiable */
#define __STRHT(ptr) __SH((ptr)) #define __STRHT(ptr) __SH((ptr))
/** \brief STRT Unprivileged (32 bit), ARM Compatiable */ /** \brief STRT Unprivileged (32 bit), ARM Compatiable */
#define __STRT(ptr) __SW((ptr)) #define __STRT(ptr) __SW((ptr))
/* ===== Saturation Operations ===== */ /* ===== Saturation Operations ===== */
/** /**
@@ -68,20 +68,19 @@
* \return Saturated value * \return Saturated value
*/ */
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __SSAT(val, sat) __RV_SCLIP32((val), (sat-1)) #define __SSAT(val, sat) __RV_SCLIP32((val), (sat - 1))
#else #else
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) {
{ if ((sat >= 1U) && (sat <= 32U)) {
if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max;
const int32_t min = -1 - max ; if (val > max) {
if (val > max) { return max;
return max; } else if (val < min) {
} else if (val < min) { return min;
return min;
}
} }
return val; }
return val;
} }
#endif #endif
@@ -93,19 +92,18 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
* \return Saturated value * \return Saturated value
*/ */
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __USAT(val, sat) __RV_UCLIP32((val), (sat-1)) #define __USAT(val, sat) __RV_UCLIP32((val), (sat - 1))
#else #else
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) {
{ if (sat <= 31U) {
if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U);
const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) {
if (val > (int32_t)max) { return max;
return max; } else if (val < 0) {
} else if (val < 0) { return 0U;
return 0U;
}
} }
return (uint32_t)val; }
return (uint32_t)val;
} }
#endif #endif
@@ -117,15 +115,11 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
* \param [in] value Value to reverse * \param [in] value Value to reverse
* \return Reversed value * \return Reversed value
*/ */
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) {
{ uint32_t result;
uint32_t result;
result = ((value & 0xff000000) >> 24) result = ((value & 0xff000000) >> 24) | ((value & 0x00ff0000) >> 8) | ((value & 0x0000ff00) << 8) | ((value & 0x000000ff) << 24);
| ((value & 0x00ff0000) >> 8 ) return result;
| ((value & 0x0000ff00) << 8 )
| ((value & 0x000000ff) << 24);
return result;
} }
/** /**
@@ -135,15 +129,11 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
* \param [in] value Value to reverse * \param [in] value Value to reverse
* \return Reversed value * \return Reversed value
*/ */
__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) {
{ uint32_t result;
uint32_t result; result = ((value & 0xff000000) >> 8) | ((value & 0x00ff00000) << 8) | ((value & 0x0000ff00) >> 8) | ((value & 0x000000ff) << 8);
result = ((value & 0xff000000) >> 8)
| ((value & 0x00ff00000) << 8 )
| ((value & 0x0000ff00) >> 8 )
| ((value & 0x000000ff) << 8) ;
return result; return result;
} }
/** /**
@@ -154,11 +144,10 @@ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
* \param [in] value Value to reverse * \param [in] value Value to reverse
* \return Reversed value * \return Reversed value
*/ */
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) {
{ int16_t result;
int16_t result; result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8);
result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8); return result;
return result;
} }
/** /**
@@ -169,13 +158,12 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
* \param [in] op2 Number of Bits to rotate(0-31) * \param [in] op2 Number of Bits to rotate(0-31)
* \return Rotated value * \return Rotated value
*/ */
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) {
{ op2 = op2 & 0x1F;
op2 = op2 & 0x1F; if (op2 == 0U) {
if (op2 == 0U) { return op1;
return op1; }
} return (op1 >> op2) | (op1 << (32U - op2));
return (op1 >> op2) | (op1 << (32U - op2));
} }
/** /**
@@ -185,21 +173,20 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
* \return Reversed value * \return Reversed value
*/ */
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __RBIT(value) __RV_BITREVI((value), 31) #define __RBIT(value) __RV_BITREVI((value), 31)
#else #else
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) {
{ uint32_t result;
uint32_t result; uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */ result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U) { for (value >>= 1U; value != 0U; value >>= 1U) {
result <<= 1U; result <<= 1U;
result |= value & 1U; result |= value & 1U;
s--; s--;
} }
result <<= s; /* shift when v's highest bits are zero */ result <<= s; /* shift when v's highest bits are zero */
return result; return result;
} }
#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */ #endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */
@@ -210,17 +197,16 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
* \return number of leading zeros in value * \return number of leading zeros in value
*/ */
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __CLZ(data) __RV_CLZ32(data) #define __CLZ(data) __RV_CLZ32(data)
#else #else
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) {
{ uint8_t ret = 0;
uint8_t ret = 0; uint32_t temp = ~data;
uint32_t temp = ~data; while (temp & 0x80000000) {
while (temp & 0x80000000) { temp <<= 1;
temp <<= 1; ret++;
ret++; }
} return ret;
return ret;
} }
#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */ #endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */

837
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_base.h vendored
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30
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_cache.h vendored
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@@ -31,7 +31,7 @@
* * 1: Present * * 1: Present
*/ */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)
@@ -59,11 +59,8 @@
* - This \ref CSR_MCACHE_CTL register control I Cache enable. * - This \ref CSR_MCACHE_CTL register control I Cache enable.
* \sa * \sa
* - \ref DisableICache * - \ref DisableICache
*/ */
__STATIC_FORCEINLINE void EnableICache (void) __STATIC_FORCEINLINE void EnableICache(void) { __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); }
{
__RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
}
/** /**
* \brief Disable ICache * \brief Disable ICache
@@ -74,12 +71,9 @@ __STATIC_FORCEINLINE void EnableICache (void)
* \sa * \sa
* - \ref EnableICache * - \ref EnableICache
*/ */
__STATIC_FORCEINLINE void DisableICache (void) __STATIC_FORCEINLINE void DisableICache(void) { __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); }
{
__RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
}
/** @} */ /* End of Doxygen Group NMSIS_Core_ICache */ /** @} */ /* End of Doxygen Group NMSIS_Core_ICache */
#endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */ #endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */
#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
/** /**
@@ -96,11 +90,8 @@ __STATIC_FORCEINLINE void DisableICache (void)
* - This \ref CSR_MCACHE_CTL register control D Cache enable. * - This \ref CSR_MCACHE_CTL register control D Cache enable.
* \sa * \sa
* - \ref DisableDCache * - \ref DisableDCache
*/ */
__STATIC_FORCEINLINE void EnableDCache (void) __STATIC_FORCEINLINE void EnableDCache(void) { __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); }
{
__RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
}
/** /**
* \brief Disable DCache * \brief Disable DCache
@@ -111,12 +102,9 @@ __STATIC_FORCEINLINE void EnableDCache (void)
* \sa * \sa
* - \ref EnableDCache * - \ref EnableDCache
*/ */
__STATIC_FORCEINLINE void DisableDCache (void) __STATIC_FORCEINLINE void DisableDCache(void) { __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); }
{
__RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
}
/** @} */ /* End of Doxygen Group NMSIS_Core_DCache */ /** @} */ /* End of Doxygen Group NMSIS_Core_DCache */
#endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */ #endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */
#ifdef __cplusplus #ifdef __cplusplus
} }

3240
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_dsp.h vendored
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560
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_eclic.h vendored
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@@ -33,7 +33,7 @@
* *
*/ */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
@@ -48,86 +48,85 @@
/** /**
* \brief Union type to access CLICFG configure register. * \brief Union type to access CLICFG configure register.
*/ */
typedef union typedef union {
{ struct {
struct { uint8_t _reserved0 : 1; /*!< bit: 0 Overflow condition code flag */
uint8_t _reserved0:1; /*!< bit: 0 Overflow condition code flag */ uint8_t nlbits : 4; /*!< bit: 29 Carry condition code flag */
uint8_t nlbits:4; /*!< bit: 29 Carry condition code flag */ uint8_t _reserved1 : 2; /*!< bit: 30 Zero condition code flag */
uint8_t _reserved1:2; /*!< bit: 30 Zero condition code flag */ uint8_t _reserved2 : 1; /*!< bit: 31 Negative condition code flag */
uint8_t _reserved2:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */
} b; /*!< Structure used for bit access */ uint8_t w; /*!< Type used for byte access */
uint8_t w; /*!< Type used for byte access */
} CLICCFG_Type; } CLICCFG_Type;
/** /**
* \brief Union type to access CLICINFO information register. * \brief Union type to access CLICINFO information register.
*/ */
typedef union { typedef union {
struct { struct {
uint32_t numint:13; /*!< bit: 0..12 number of maximum interrupt inputs supported */ uint32_t numint : 13; /*!< bit: 0..12 number of maximum interrupt inputs supported */
uint32_t version:8; /*!< bit: 13..20 20:17 for architecture version,16:13 for implementation version */ uint32_t version : 8; /*!< bit: 13..20 20:17 for architecture version,16:13 for implementation version */
uint32_t intctlbits:4; /*!< bit: 21..24 specifies how many hardware bits are actually implemented in the clicintctl registers */ uint32_t intctlbits : 4; /*!< bit: 21..24 specifies how many hardware bits are actually implemented in the clicintctl registers */
uint32_t _reserved0:8; /*!< bit: 25..31 Reserved */ uint32_t _reserved0 : 8; /*!< bit: 25..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} CLICINFO_Type; } CLICINFO_Type;
/** /**
* \brief Access to the structure of a vector interrupt controller. * \brief Access to the structure of a vector interrupt controller.
*/ */
typedef struct { typedef struct {
__IOM uint8_t INTIP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */ __IOM uint8_t INTIP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */
__IOM uint8_t INTIE; /*!< Offset: 0x001 (R/W) Interrupt set enable register */ __IOM uint8_t INTIE; /*!< Offset: 0x001 (R/W) Interrupt set enable register */
__IOM uint8_t INTATTR; /*!< Offset: 0x002 (R/W) Interrupt set attributes register */ __IOM uint8_t INTATTR; /*!< Offset: 0x002 (R/W) Interrupt set attributes register */
__IOM uint8_t INTCTRL; /*!< Offset: 0x003 (R/W) Interrupt configure register */ __IOM uint8_t INTCTRL; /*!< Offset: 0x003 (R/W) Interrupt configure register */
} CLIC_CTRL_Type; } CLIC_CTRL_Type;
typedef struct { typedef struct {
__IOM uint8_t CFG; /*!< Offset: 0x000 (R/W) CLIC configuration register */ __IOM uint8_t CFG; /*!< Offset: 0x000 (R/W) CLIC configuration register */
uint8_t RESERVED0[3]; uint8_t RESERVED0[3];
__IM uint32_t INFO; /*!< Offset: 0x004 (R/ ) CLIC information register */ __IM uint32_t INFO; /*!< Offset: 0x004 (R/ ) CLIC information register */
uint8_t RESERVED1[3]; uint8_t RESERVED1[3];
__IOM uint8_t MTH; /*!< Offset: 0x00B (R/W) CLIC machine mode threshold register */ __IOM uint8_t MTH; /*!< Offset: 0x00B (R/W) CLIC machine mode threshold register */
uint32_t RESERVED2[0x3FD]; uint32_t RESERVED2[0x3FD];
CLIC_CTRL_Type CTRL[4096]; /*!< Offset: 0x1000 (R/W) CLIC register structure for INTIP, INTIE, INTATTR, INTCTL */ CLIC_CTRL_Type CTRL[4096]; /*!< Offset: 0x1000 (R/W) CLIC register structure for INTIP, INTIE, INTATTR, INTCTL */
} CLIC_Type; } CLIC_Type;
#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */ #define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */
#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */ #define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */
#define CLIC_CLICINFO_CTLBIT_Pos 21U /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Position */ #define CLIC_CLICINFO_CTLBIT_Pos 21U /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Position */
#define CLIC_CLICINFO_CTLBIT_Msk (0xFUL << CLIC_CLICINFO_CTLBIT_Pos) /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Mask */ #define CLIC_CLICINFO_CTLBIT_Msk (0xFUL << CLIC_CLICINFO_CTLBIT_Pos) /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Mask */
#define CLIC_CLICINFO_VER_Pos 13U /*!< CLIC CLICINFO: VERSION Position */ #define CLIC_CLICINFO_VER_Pos 13U /*!< CLIC CLICINFO: VERSION Position */
#define CLIC_CLICINFO_VER_Msk (0xFFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICINFO: VERSION Mask */ #define CLIC_CLICINFO_VER_Msk (0xFFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICINFO: VERSION Mask */
#define CLIC_CLICINFO_NUM_Pos 0U /*!< CLIC CLICINFO: NUM Position */ #define CLIC_CLICINFO_NUM_Pos 0U /*!< CLIC CLICINFO: NUM Position */
#define CLIC_CLICINFO_NUM_Msk (0xFFFUL << CLIC_CLICINFO_NUM_Pos) /*!< CLIC CLICINFO: NUM Mask */ #define CLIC_CLICINFO_NUM_Msk (0xFFFUL << CLIC_CLICINFO_NUM_Pos) /*!< CLIC CLICINFO: NUM Mask */
#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */ #define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */
#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */ #define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */
#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */ #define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */
#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */ #define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */
#define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */ #define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */
#define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */ #define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */
#define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */ #define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */
#define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */ #define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */
#define ECLIC_MAX_NLBITS 8U /*!< Max nlbit of the CLICINTCTLBITS */ #define ECLIC_MAX_NLBITS 8U /*!< Max nlbit of the CLICINTCTLBITS */
#define ECLIC_MODE_MTVEC_Msk 3U /*!< ECLIC Mode mask for MTVT CSR Register */ #define ECLIC_MODE_MTVEC_Msk 3U /*!< ECLIC Mode mask for MTVT CSR Register */
#define ECLIC_NON_VECTOR_INTERRUPT 0x0 /*!< Non-Vector Interrupt Mode of ECLIC */ #define ECLIC_NON_VECTOR_INTERRUPT 0x0 /*!< Non-Vector Interrupt Mode of ECLIC */
#define ECLIC_VECTOR_INTERRUPT 0x1 /*!< Vector Interrupt Mode of ECLIC */ #define ECLIC_VECTOR_INTERRUPT 0x1 /*!< Vector Interrupt Mode of ECLIC */
/**\brief ECLIC Trigger Enum for different Trigger Type */ /**\brief ECLIC Trigger Enum for different Trigger Type */
typedef enum ECLIC_TRIGGER { typedef enum ECLIC_TRIGGER {
ECLIC_LEVEL_TRIGGER = 0x0, /*!< Level Triggerred, trig[0] = 0 */ ECLIC_LEVEL_TRIGGER = 0x0, /*!< Level Triggerred, trig[0] = 0 */
ECLIC_POSTIVE_EDGE_TRIGGER = 0x1, /*!< Postive/Rising Edge Triggered, trig[1] = 1, trig[0] = 0 */ ECLIC_POSTIVE_EDGE_TRIGGER = 0x1, /*!< Postive/Rising Edge Triggered, trig[1] = 1, trig[0] = 0 */
ECLIC_NEGTIVE_EDGE_TRIGGER = 0x3, /*!< Negtive/Falling Edge Triggered, trig[1] = 1, trig[0] = 0 */ ECLIC_NEGTIVE_EDGE_TRIGGER = 0x3, /*!< Negtive/Falling Edge Triggered, trig[1] = 1, trig[0] = 0 */
ECLIC_MAX_TRIGGER = 0x3 /*!< MAX Supported Trigger Mode */ ECLIC_MAX_TRIGGER = 0x3 /*!< MAX Supported Trigger Mode */
} ECLIC_TRIGGER_Type; } ECLIC_TRIGGER_Type;
#ifndef __ECLIC_BASEADDR #ifndef __ECLIC_BASEADDR
@@ -137,12 +136,12 @@ typedef enum ECLIC_TRIGGER {
#ifndef __ECLIC_INTCTLBITS #ifndef __ECLIC_INTCTLBITS
/* Define __ECLIC_INTCTLBITS to get via ECLIC->INFO if not defined */ /* Define __ECLIC_INTCTLBITS to get via ECLIC->INFO if not defined */
#define __ECLIC_INTCTLBITS (__ECLIC_GetInfoCtlbits()) #define __ECLIC_INTCTLBITS (__ECLIC_GetInfoCtlbits())
#endif #endif
/* ECLIC Memory mapping of Device */ /* ECLIC Memory mapping of Device */
#define ECLIC_BASE __ECLIC_BASEADDR /*!< ECLIC Base Address */ #define ECLIC_BASE __ECLIC_BASEADDR /*!< ECLIC Base Address */
#define ECLIC ((CLIC_Type *) ECLIC_BASE) /*!< CLIC configuration struct */ #define ECLIC ((CLIC_Type *)ECLIC_BASE) /*!< CLIC configuration struct */
/** @} */ /* end of group NMSIS_Core_ECLIC_Registers */ /** @} */ /* end of group NMSIS_Core_ECLIC_Registers */
@@ -170,80 +169,80 @@ typedef enum ECLIC_TRIGGER {
*/ */
#if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__) #if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)
typedef enum IRQn { typedef enum IRQn {
/* ========= Nuclei N/NX Core Specific Interrupt Numbers =========== */ /* ========= Nuclei N/NX Core Specific Interrupt Numbers =========== */
/* Core Internal Interrupt IRQn definitions */ /* Core Internal Interrupt IRQn definitions */
Reserved0_IRQn = 0, /*!< Internal reserved */ Reserved0_IRQn = 0, /*!< Internal reserved */
Reserved1_IRQn = 1, /*!< Internal reserved */ Reserved1_IRQn = 1, /*!< Internal reserved */
Reserved2_IRQn = 2, /*!< Internal reserved */ Reserved2_IRQn = 2, /*!< Internal reserved */
SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */ SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */
Reserved3_IRQn = 4, /*!< Internal reserved */ Reserved3_IRQn = 4, /*!< Internal reserved */
Reserved4_IRQn = 5, /*!< Internal reserved */ Reserved4_IRQn = 5, /*!< Internal reserved */
Reserved5_IRQn = 6, /*!< Internal reserved */ Reserved5_IRQn = 6, /*!< Internal reserved */
SysTimer_IRQn = 7, /*!< System Timer Interrupt */ SysTimer_IRQn = 7, /*!< System Timer Interrupt */
Reserved6_IRQn = 8, /*!< Internal reserved */ Reserved6_IRQn = 8, /*!< Internal reserved */
Reserved7_IRQn = 9, /*!< Internal reserved */ Reserved7_IRQn = 9, /*!< Internal reserved */
Reserved8_IRQn = 10, /*!< Internal reserved */ Reserved8_IRQn = 10, /*!< Internal reserved */
Reserved9_IRQn = 11, /*!< Internal reserved */ Reserved9_IRQn = 11, /*!< Internal reserved */
Reserved10_IRQn = 12, /*!< Internal reserved */ Reserved10_IRQn = 12, /*!< Internal reserved */
Reserved11_IRQn = 13, /*!< Internal reserved */ Reserved11_IRQn = 13, /*!< Internal reserved */
Reserved12_IRQn = 14, /*!< Internal reserved */ Reserved12_IRQn = 14, /*!< Internal reserved */
Reserved13_IRQn = 15, /*!< Internal reserved */ Reserved13_IRQn = 15, /*!< Internal reserved */
Reserved14_IRQn = 16, /*!< Internal reserved */ Reserved14_IRQn = 16, /*!< Internal reserved */
Reserved15_IRQn = 17, /*!< Internal reserved */ Reserved15_IRQn = 17, /*!< Internal reserved */
Reserved16_IRQn = 18, /*!< Internal reserved */ Reserved16_IRQn = 18, /*!< Internal reserved */
/* ========= Device Specific Interrupt Numbers =================== */ /* ========= Device Specific Interrupt Numbers =================== */
/* ToDo: add here your device specific external interrupt numbers. /* ToDo: add here your device specific external interrupt numbers.
* 19~max(NUM_INTERRUPT, 1023) is reserved number for user. * 19~max(NUM_INTERRUPT, 1023) is reserved number for user.
* Maxmum interrupt supported could get from clicinfo.NUM_INTERRUPT. * Maxmum interrupt supported could get from clicinfo.NUM_INTERRUPT.
* According the interrupt handlers defined in startup_Device.S * According the interrupt handlers defined in startup_Device.S
* eg.: Interrupt for Timer#1 eclic_tim1_handler -> TIM1_IRQn */ * eg.: Interrupt for Timer#1 eclic_tim1_handler -> TIM1_IRQn */
FirstDeviceSpecificInterrupt_IRQn = 19, /*!< First Device Specific Interrupt */ FirstDeviceSpecificInterrupt_IRQn = 19, /*!< First Device Specific Interrupt */
SOC_INT_MAX, /*!< Number of total interrupts */ SOC_INT_MAX, /*!< Number of total interrupts */
} IRQn_Type; } IRQn_Type;
#endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */ #endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */
#ifdef NMSIS_ECLIC_VIRTUAL #ifdef NMSIS_ECLIC_VIRTUAL
#ifndef NMSIS_ECLIC_VIRTUAL_HEADER_FILE #ifndef NMSIS_ECLIC_VIRTUAL_HEADER_FILE
#define NMSIS_ECLIC_VIRTUAL_HEADER_FILE "nmsis_eclic_virtual.h" #define NMSIS_ECLIC_VIRTUAL_HEADER_FILE "nmsis_eclic_virtual.h"
#endif #endif
#include NMSIS_ECLIC_VIRTUAL_HEADER_FILE #include NMSIS_ECLIC_VIRTUAL_HEADER_FILE
#else #else
#define ECLIC_SetCfgNlbits __ECLIC_SetCfgNlbits #define ECLIC_SetCfgNlbits __ECLIC_SetCfgNlbits
#define ECLIC_GetCfgNlbits __ECLIC_GetCfgNlbits #define ECLIC_GetCfgNlbits __ECLIC_GetCfgNlbits
#define ECLIC_GetInfoVer __ECLIC_GetInfoVer #define ECLIC_GetInfoVer __ECLIC_GetInfoVer
#define ECLIC_GetInfoCtlbits __ECLIC_GetInfoCtlbits #define ECLIC_GetInfoCtlbits __ECLIC_GetInfoCtlbits
#define ECLIC_GetInfoNum __ECLIC_GetInfoNum #define ECLIC_GetInfoNum __ECLIC_GetInfoNum
#define ECLIC_SetMth __ECLIC_SetMth #define ECLIC_SetMth __ECLIC_SetMth
#define ECLIC_GetMth __ECLIC_GetMth #define ECLIC_GetMth __ECLIC_GetMth
#define ECLIC_EnableIRQ __ECLIC_EnableIRQ #define ECLIC_EnableIRQ __ECLIC_EnableIRQ
#define ECLIC_GetEnableIRQ __ECLIC_GetEnableIRQ #define ECLIC_GetEnableIRQ __ECLIC_GetEnableIRQ
#define ECLIC_DisableIRQ __ECLIC_DisableIRQ #define ECLIC_DisableIRQ __ECLIC_DisableIRQ
#define ECLIC_SetPendingIRQ __ECLIC_SetPendingIRQ #define ECLIC_SetPendingIRQ __ECLIC_SetPendingIRQ
#define ECLIC_GetPendingIRQ __ECLIC_GetPendingIRQ #define ECLIC_GetPendingIRQ __ECLIC_GetPendingIRQ
#define ECLIC_ClearPendingIRQ __ECLIC_ClearPendingIRQ #define ECLIC_ClearPendingIRQ __ECLIC_ClearPendingIRQ
#define ECLIC_SetTrigIRQ __ECLIC_SetTrigIRQ #define ECLIC_SetTrigIRQ __ECLIC_SetTrigIRQ
#define ECLIC_GetTrigIRQ __ECLIC_GetTrigIRQ #define ECLIC_GetTrigIRQ __ECLIC_GetTrigIRQ
#define ECLIC_SetShvIRQ __ECLIC_SetShvIRQ #define ECLIC_SetShvIRQ __ECLIC_SetShvIRQ
#define ECLIC_GetShvIRQ __ECLIC_GetShvIRQ #define ECLIC_GetShvIRQ __ECLIC_GetShvIRQ
#define ECLIC_SetCtrlIRQ __ECLIC_SetCtrlIRQ #define ECLIC_SetCtrlIRQ __ECLIC_SetCtrlIRQ
#define ECLIC_GetCtrlIRQ __ECLIC_GetCtrlIRQ #define ECLIC_GetCtrlIRQ __ECLIC_GetCtrlIRQ
#define ECLIC_SetLevelIRQ __ECLIC_SetLevelIRQ #define ECLIC_SetLevelIRQ __ECLIC_SetLevelIRQ
#define ECLIC_GetLevelIRQ __ECLIC_GetLevelIRQ #define ECLIC_GetLevelIRQ __ECLIC_GetLevelIRQ
#define ECLIC_SetPriorityIRQ __ECLIC_SetPriorityIRQ #define ECLIC_SetPriorityIRQ __ECLIC_SetPriorityIRQ
#define ECLIC_GetPriorityIRQ __ECLIC_GetPriorityIRQ #define ECLIC_GetPriorityIRQ __ECLIC_GetPriorityIRQ
#endif /* NMSIS_ECLIC_VIRTUAL */ #endif /* NMSIS_ECLIC_VIRTUAL */
#ifdef NMSIS_VECTAB_VIRTUAL #ifdef NMSIS_VECTAB_VIRTUAL
#ifndef NMSIS_VECTAB_VIRTUAL_HEADER_FILE #ifndef NMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define NMSIS_VECTAB_VIRTUAL_HEADER_FILE "nmsis_vectab_virtual.h" #define NMSIS_VECTAB_VIRTUAL_HEADER_FILE "nmsis_vectab_virtual.h"
#endif #endif
#include NMSIS_VECTAB_VIRTUAL_HEADER_FILE #include NMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else #else
#define ECLIC_SetVector __ECLIC_SetVector #define ECLIC_SetVector __ECLIC_SetVector
#define ECLIC_GetVector __ECLIC_GetVector #define ECLIC_GetVector __ECLIC_GetVector
#endif /* (NMSIS_VECTAB_VIRTUAL) */ #endif /* (NMSIS_VECTAB_VIRTUAL) */
/** /**
* \brief Set nlbits value * \brief Set nlbits value
@@ -255,10 +254,9 @@ typedef enum IRQn {
* \sa * \sa
* - \ref ECLIC_GetCfgNlbits * - \ref ECLIC_GetCfgNlbits
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits) __STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits) {
{ ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk;
ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk; ECLIC->CFG |= (uint8_t)((nlbits << CLIC_CLICCFG_NLBIT_Pos) & CLIC_CLICCFG_NLBIT_Msk);
ECLIC->CFG |= (uint8_t)((nlbits <<CLIC_CLICCFG_NLBIT_Pos) & CLIC_CLICCFG_NLBIT_Msk);
} }
/** /**
@@ -271,10 +269,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits)
* \sa * \sa
* - \ref ECLIC_SetCfgNlbits * - \ref ECLIC_SetCfgNlbits
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void) { return ((uint32_t)((ECLIC->CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos)); }
{
return ((uint32_t)((ECLIC->CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos));
}
/** /**
* \brief Get the ECLIC version number * \brief Get the ECLIC version number
@@ -286,11 +281,8 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void)
* - Bit 20:17 for architecture version, bit 16:13 for implementation version. * - Bit 20:17 for architecture version, bit 16:13 for implementation version.
* \sa * \sa
* - \ref ECLIC_GetInfoNum * - \ref ECLIC_GetInfoNum
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos)); }
{
return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos));
}
/** /**
* \brief Get CLICINTCTLBITS * \brief Get CLICINTCTLBITS
@@ -304,10 +296,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void)
* \sa * \sa
* - \ref ECLIC_GetInfoNum * - \ref ECLIC_GetInfoNum
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos)); }
{
return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos));
}
/** /**
* \brief Get number of maximum interrupt inputs supported * \brief Get number of maximum interrupt inputs supported
@@ -320,10 +309,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void)
* \sa * \sa
* - \ref ECLIC_GetInfoCtlbits * - \ref ECLIC_GetInfoCtlbits
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos)); }
{
return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos));
}
/** /**
* \brief Set Machine Mode Interrupt Level Threshold * \brief Set Machine Mode Interrupt Level Threshold
@@ -333,10 +319,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void)
* \sa * \sa
* - \ref ECLIC_GetMth * - \ref ECLIC_GetMth
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth) __STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth) { ECLIC->MTH = mth; }
{
ECLIC->MTH = mth;
}
/** /**
* \brief Get Machine Mode Interrupt Level Threshold * \brief Get Machine Mode Interrupt Level Threshold
@@ -346,11 +329,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth)
* \sa * \sa
* - \ref ECLIC_SetMth * - \ref ECLIC_SetMth
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void) __STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void) { return (ECLIC->MTH); }
{
return (ECLIC->MTH);
}
/** /**
* \brief Enable a specific interrupt * \brief Enable a specific interrupt
@@ -362,10 +341,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void)
* \sa * \sa
* - \ref ECLIC_DisableIRQ * - \ref ECLIC_DisableIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk; }
{
ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk;
}
/** /**
* \brief Get a specific interrupt enable status * \brief Get a specific interrupt enable status
@@ -381,10 +357,7 @@ __STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn)
* - \ref ECLIC_EnableIRQ * - \ref ECLIC_EnableIRQ
* - \ref ECLIC_DisableIRQ * - \ref ECLIC_DisableIRQ
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn) { return ((uint32_t)(ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk); }
{
return((uint32_t) (ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk);
}
/** /**
* \brief Disable a specific interrupt * \brief Disable a specific interrupt
@@ -396,10 +369,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_EnableIRQ * - \ref ECLIC_EnableIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk; }
{
ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk;
}
/** /**
* \brief Get the pending specific interrupt * \brief Get the pending specific interrupt
@@ -415,10 +385,7 @@ __STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn)
* - \ref ECLIC_SetPendingIRQ * - \ref ECLIC_SetPendingIRQ
* - \ref ECLIC_ClearPendingIRQ * - \ref ECLIC_ClearPendingIRQ
*/ */
__STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk); }
{
return((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk);
}
/** /**
* \brief Set a specific interrupt to pending * \brief Set a specific interrupt to pending
@@ -431,10 +398,7 @@ __STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn)
* - \ref ECLIC_GetPendingIRQ * - \ref ECLIC_GetPendingIRQ
* - \ref ECLIC_ClearPendingIRQ * - \ref ECLIC_ClearPendingIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk; }
{
ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk;
}
/** /**
* \brief Clear a specific interrupt from pending * \brief Clear a specific interrupt from pending
@@ -448,10 +412,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn)
* - \ref ECLIC_SetPendingIRQ * - \ref ECLIC_SetPendingIRQ
* - \ref ECLIC_GetPendingIRQ * - \ref ECLIC_GetPendingIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIP &= ~CLIC_INTIP_IP_Msk; }
{
ECLIC->CTRL[IRQn].INTIP &= ~ CLIC_INTIP_IP_Msk;
}
/** /**
* \brief Set trigger mode and polarity for a specific interrupt * \brief Set trigger mode and polarity for a specific interrupt
@@ -469,10 +430,9 @@ __STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetTrigIRQ * - \ref ECLIC_GetTrigIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig) __STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig) {
{ ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk;
ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk; ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig << CLIC_INTATTR_TRIG_Pos);
ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig<<CLIC_INTATTR_TRIG_Pos);
} }
/** /**
@@ -490,10 +450,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig)
* \sa * \sa
* - \ref ECLIC_SetTrigIRQ * - \ref ECLIC_SetTrigIRQ
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn) { return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk) >> CLIC_INTATTR_TRIG_Pos)); }
{
return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk)>>CLIC_INTATTR_TRIG_Pos));
}
/** /**
* \brief Set interrupt working mode for a specific interrupt * \brief Set interrupt working mode for a specific interrupt
@@ -508,10 +465,9 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetShvIRQ * - \ref ECLIC_GetShvIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv) __STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv) {
{ ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk;
ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk; ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv << CLIC_INTATTR_SHV_Pos);
ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv<<CLIC_INTATTR_SHV_Pos);
} }
/** /**
@@ -527,10 +483,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv)
* \sa * \sa
* - \ref ECLIC_SetShvIRQ * - \ref ECLIC_SetShvIRQ
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn) { return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk) >> CLIC_INTATTR_SHV_Pos)); }
{
return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk)>>CLIC_INTATTR_SHV_Pos));
}
/** /**
* \brief Modify ECLIC Interrupt Input Control Register for a specific interrupt * \brief Modify ECLIC Interrupt Input Control Register for a specific interrupt
@@ -543,10 +496,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetCtrlIRQ * - \ref ECLIC_GetCtrlIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl) __STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl) { ECLIC->CTRL[IRQn].INTCTRL = intctrl; }
{
ECLIC->CTRL[IRQn].INTCTRL = intctrl;
}
/** /**
* \brief Get ECLIC Interrupt Input Control Register value for a specific interrupt * \brief Get ECLIC Interrupt Input Control Register value for a specific interrupt
@@ -559,10 +509,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl)
* \sa * \sa
* - \ref ECLIC_SetCtrlIRQ * - \ref ECLIC_SetCtrlIRQ
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn) { return (ECLIC->CTRL[IRQn].INTCTRL); }
{
return (ECLIC->CTRL[IRQn].INTCTRL);
}
/** /**
* \brief Set ECLIC Interrupt level of a specific interrupt * \brief Set ECLIC Interrupt level of a specific interrupt
@@ -579,27 +526,26 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetLevelIRQ * - \ref ECLIC_GetLevelIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs) __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs) {
{ uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
if (nlbits == 0) { if (nlbits == 0) {
return; return;
} }
if (nlbits > intctlbits) { if (nlbits > intctlbits) {
nlbits = intctlbits; nlbits = intctlbits;
} }
uint8_t maxlvl = ((1 << nlbits) - 1); uint8_t maxlvl = ((1 << nlbits) - 1);
if (lvl_abs > maxlvl) { if (lvl_abs > maxlvl) {
lvl_abs = maxlvl; lvl_abs = maxlvl;
} }
uint8_t lvl = lvl_abs << (ECLIC_MAX_NLBITS - nlbits); uint8_t lvl = lvl_abs << (ECLIC_MAX_NLBITS - nlbits);
uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn); uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
cur_ctrl = cur_ctrl << nlbits; cur_ctrl = cur_ctrl << nlbits;
cur_ctrl = cur_ctrl >> nlbits; cur_ctrl = cur_ctrl >> nlbits;
__ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | lvl)); __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | lvl));
} }
/** /**
@@ -613,21 +559,20 @@ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)
* \sa * \sa
* - \ref ECLIC_SetLevelIRQ * - \ref ECLIC_SetLevelIRQ
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn) {
{ uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
if (nlbits == 0) { if (nlbits == 0) {
return 0; return 0;
} }
if (nlbits > intctlbits) { if (nlbits > intctlbits) {
nlbits = intctlbits; nlbits = intctlbits;
} }
uint8_t intctrl = __ECLIC_GetCtrlIRQ(IRQn); uint8_t intctrl = __ECLIC_GetCtrlIRQ(IRQn);
uint8_t lvl_abs = intctrl >> (ECLIC_MAX_NLBITS - nlbits); uint8_t lvl_abs = intctrl >> (ECLIC_MAX_NLBITS - nlbits);
return lvl_abs; return lvl_abs;
} }
/** /**
@@ -644,23 +589,22 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetPriorityIRQ * - \ref ECLIC_GetPriorityIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri) __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri) {
{ uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; if (nlbits < intctlbits) {
if (nlbits < intctlbits) { uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1);
uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1); if (pri > maxpri) {
if (pri > maxpri) { pri = maxpri;
pri = maxpri;
}
pri = pri << (ECLIC_MAX_NLBITS - intctlbits);
uint8_t mask = ((uint8_t)(-1)) >> intctlbits;
pri = pri | mask;
uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
cur_ctrl = cur_ctrl >> (ECLIC_MAX_NLBITS - nlbits);
cur_ctrl = cur_ctrl << (ECLIC_MAX_NLBITS - nlbits);
__ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | pri));
} }
pri = pri << (ECLIC_MAX_NLBITS - intctlbits);
uint8_t mask = ((uint8_t)(-1)) >> intctlbits;
pri = pri | mask;
uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
cur_ctrl = cur_ctrl >> (ECLIC_MAX_NLBITS - nlbits);
cur_ctrl = cur_ctrl << (ECLIC_MAX_NLBITS - nlbits);
__ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | pri));
}
} }
/** /**
@@ -674,19 +618,18 @@ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)
* \sa * \sa
* - \ref ECLIC_SetPriorityIRQ * - \ref ECLIC_SetPriorityIRQ
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn) {
{ uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; if (nlbits < intctlbits) {
if (nlbits < intctlbits) { uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn); uint8_t pri = cur_ctrl << nlbits;
uint8_t pri = cur_ctrl << nlbits; pri = pri >> nlbits;
pri = pri >> nlbits; pri = pri >> (ECLIC_MAX_NLBITS - intctlbits);
pri = pri >> (ECLIC_MAX_NLBITS - intctlbits); return pri;
return pri; } else {
} else { return 0;
return 0; }
}
} }
/** /**
@@ -705,20 +648,19 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetVector * - \ref ECLIC_GetVector
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) __STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) {
{
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
volatile uint32_t vec_base; volatile uint32_t vec_base;
vec_base = ((uint32_t)__RV_CSR_READ(CSR_MTVT)); vec_base = ((uint32_t)__RV_CSR_READ(CSR_MTVT));
(* (unsigned long *) (vec_base + ((int32_t)IRQn) * 4)) = vector; (*(unsigned long *)(vec_base + ((int32_t)IRQn) * 4)) = vector;
#elif __RISCV_XLEN == 64 #elif __RISCV_XLEN == 64
volatile uint64_t vec_base; volatile uint64_t vec_base;
vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT)); vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT));
(* (unsigned long *) (vec_base + ((int32_t)IRQn) * 8)) = vector; (*(unsigned long *)(vec_base + ((int32_t)IRQn) * 8)) = vector;
#else // TODO Need cover for XLEN=128 case in future #else // TODO Need cover for XLEN=128 case in future
volatile uint64_t vec_base; volatile uint64_t vec_base;
vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT)); vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT));
(* (unsigned long *) (vec_base + ((int32_t)IRQn) * 8)) = vector; (*(unsigned long *)(vec_base + ((int32_t)IRQn) * 8)) = vector;
#endif #endif
} }
@@ -734,14 +676,13 @@ __STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector)
* \sa * \sa
* - \ref ECLIC_SetVector * - \ref ECLIC_SetVector
*/ */
__STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) __STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) {
{
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*4)); return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 4));
#elif __RISCV_XLEN == 64 #elif __RISCV_XLEN == 64
return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*8)); return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 8));
#else // TODO Need cover for XLEN=128 case in future #else // TODO Need cover for XLEN=128 case in future
return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*8)); return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 8));
#endif #endif
} }
@@ -755,11 +696,10 @@ __STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn)
* \sa * \sa
* - \ref __get_exc_entry * - \ref __get_exc_entry
*/ */
__STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) __STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) {
{ addr &= (rv_csr_t)(~0x3F);
addr &= (rv_csr_t)(~0x3F); addr |= ECLIC_MODE_MTVEC_Msk;
addr |= ECLIC_MODE_MTVEC_Msk; __RV_CSR_WRITE(CSR_MTVEC, addr);
__RV_CSR_WRITE(CSR_MTVEC, addr);
} }
/** /**
@@ -772,10 +712,9 @@ __STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr)
* \sa * \sa
* - \ref __set_exc_entry * - \ref __set_exc_entry
*/ */
__STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void) __STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void) {
{ unsigned long addr = __RV_CSR_READ(CSR_MTVEC);
unsigned long addr = __RV_CSR_READ(CSR_MTVEC); return (addr & ~ECLIC_MODE_MTVEC_Msk);
return (addr & ~ECLIC_MODE_MTVEC_Msk);
} }
/** /**
@@ -789,15 +728,14 @@ __STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void)
* \sa * \sa
* - \ref __get_nonvec_entry * - \ref __get_nonvec_entry
*/ */
__STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr) __STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr) {
{ if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
if (__RV_CSR_READ(CSR_MTVT2) & 0x1){ __RV_CSR_WRITE(CSR_MTVT2, addr | 0x01);
__RV_CSR_WRITE(CSR_MTVT2, addr | 0x01); } else {
} else { addr &= (rv_csr_t)(~0x3F);
addr &= (rv_csr_t)(~0x3F); addr |= ECLIC_MODE_MTVEC_Msk;
addr |= ECLIC_MODE_MTVEC_Msk; __RV_CSR_WRITE(CSR_MTVEC, addr);
__RV_CSR_WRITE(CSR_MTVEC, addr); }
}
} }
/** /**
@@ -811,14 +749,13 @@ __STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr)
* \sa * \sa
* - \ref __set_nonvec_entry * - \ref __set_nonvec_entry
*/ */
__STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void) __STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void) {
{ if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
if (__RV_CSR_READ(CSR_MTVT2) & 0x1) { return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1));
return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1)); } else {
} else { rv_csr_t addr = __RV_CSR_READ(CSR_MTVEC);
rv_csr_t addr = __RV_CSR_READ(CSR_MTVEC); return (addr & ~ECLIC_MODE_MTVEC_Msk);
return (addr & ~ECLIC_MODE_MTVEC_Msk); }
}
} }
/** /**
@@ -831,10 +768,7 @@ __STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void)
* - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector. * - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector.
* - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored. * - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored.
*/ */
__STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void) __STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void) { return __RV_CSR_READ(CSR_MNVEC); }
{
return __RV_CSR_READ(CSR_MNVEC);
}
/** /**
* \brief Save necessary CSRs into variables for vector interrupt nesting * \brief Save necessary CSRs into variables for vector interrupt nesting
@@ -866,11 +800,11 @@ __STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void)
* } * }
* \endcode * \endcode
*/ */
#define SAVE_IRQ_CSR_CONTEXT() \ #define SAVE_IRQ_CSR_CONTEXT() \
rv_csr_t __mcause = __RV_CSR_READ(CSR_MCAUSE); \ rv_csr_t __mcause = __RV_CSR_READ(CSR_MCAUSE); \
rv_csr_t __mepc = __RV_CSR_READ(CSR_MEPC); \ rv_csr_t __mepc = __RV_CSR_READ(CSR_MEPC); \
rv_csr_t __msubm = __RV_CSR_READ(CSR_MSUBM); \ rv_csr_t __msubm = __RV_CSR_READ(CSR_MSUBM); \
__enable_irq(); __enable_irq();
/** /**
* \brief Restore necessary CSRs from variables for vector interrupt nesting * \brief Restore necessary CSRs from variables for vector interrupt nesting
@@ -881,11 +815,11 @@ __STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void)
* - Interrupt will be disabled after this macro is called * - Interrupt will be disabled after this macro is called
* - It need to be used together with \ref SAVE_IRQ_CSR_CONTEXT * - It need to be used together with \ref SAVE_IRQ_CSR_CONTEXT
*/ */
#define RESTORE_IRQ_CSR_CONTEXT() \ #define RESTORE_IRQ_CSR_CONTEXT() \
__disable_irq(); \ __disable_irq(); \
__RV_CSR_WRITE(CSR_MSUBM, __msubm); \ __RV_CSR_WRITE(CSR_MSUBM, __msubm); \
__RV_CSR_WRITE(CSR_MEPC, __mepc); \ __RV_CSR_WRITE(CSR_MEPC, __mepc); \
__RV_CSR_WRITE(CSR_MCAUSE, __mcause); __RV_CSR_WRITE(CSR_MCAUSE, __mcause);
/** @} */ /* End of Doxygen Group NMSIS_Core_IntExc */ /** @} */ /* End of Doxygen Group NMSIS_Core_IntExc */

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