Merge pull request #801 from Ralim/formatting

Formatting; creates clang format spec and re-formats everything to be the same.

source/.clang-format

@@ -0,0 +1,138 @@
+# Roughly based on LLVM, tweaked a tad for readability on wide screens
+---
+Language:        Cpp
+# BasedOnStyle:  LLVM
+AccessModifierOffset: -2
+AlignAfterOpenBracket: Align
+AlignConsecutiveMacros: true
+AlignConsecutiveAssignments: true
+AlignConsecutiveDeclarations: true
+AlignEscapedNewlines: Left
+AlignOperands:   true
+AlignTrailingComments: true
+AllowAllArgumentsOnNextLine: true
+AllowAllConstructorInitializersOnNextLine: true
+AllowAllParametersOfDeclarationOnNextLine: true
+AllowShortBlocksOnASingleLine: Empty
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: All
+AllowShortLambdasOnASingleLine: All
+AllowShortIfStatementsOnASingleLine: Never
+AllowShortLoopsOnASingleLine: false
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakAfterReturnType: None
+AlwaysBreakBeforeMultilineStrings: false
+AlwaysBreakTemplateDeclarations: MultiLine
+BinPackArguments: true
+BinPackParameters: true
+BraceWrapping:
+  AfterCaseLabel:  false
+  AfterClass:      false
+  AfterControlStatement: false
+  AfterEnum:       false
+  AfterFunction:   false
+  AfterNamespace:  false
+  AfterObjCDeclaration: false
+  AfterStruct:     false
+  AfterUnion:      false
+  AfterExternBlock: false
+  BeforeCatch:     false
+  BeforeElse:      false
+  IndentBraces:    false
+  SplitEmptyFunction: true
+  SplitEmptyRecord: true
+  SplitEmptyNamespace: true
+BreakBeforeBinaryOperators: true
+BreakBeforeBraces: Attach
+BreakBeforeInheritanceComma: false
+BreakInheritanceList: BeforeColon
+BreakBeforeTernaryOperators: true
+BreakConstructorInitializersBeforeComma: false
+BreakConstructorInitializers: BeforeColon
+BreakAfterJavaFieldAnnotations: false
+BreakStringLiterals: true
+ColumnLimit:     200
+CommentPragmas:  '^ IWYU pragma:'
+CompactNamespaces: false
+ConstructorInitializerAllOnOneLineOrOnePerLine: false
+ConstructorInitializerIndentWidth: 4
+ContinuationIndentWidth: 4
+Cpp11BracedListStyle: true
+DeriveLineEnding: true
+DerivePointerAlignment: false
+DisableFormat:   false
+ExperimentalAutoDetectBinPacking: false
+FixNamespaceComments: true
+ForEachMacros:
+  - foreach
+  - Q_FOREACH
+  - BOOST_FOREACH
+IncludeBlocks:   Preserve
+IncludeCategories:
+  - Regex:           '^"(llvm|llvm-c|clang|clang-c)/'
+    Priority:        2
+    SortPriority:    0
+  - Regex:           '^(<|"(gtest|gmock|isl|json)/)'
+    Priority:        3
+    SortPriority:    0
+  - Regex:           '.*'
+    Priority:        1
+    SortPriority:    0
+IncludeIsMainRegex: '(Test)?$'
+IncludeIsMainSourceRegex: ''
+IndentCaseLabels: false
+IndentGotoLabels: true
+IndentPPDirectives: None
+IndentWidth:     2
+IndentWrappedFunctionNames: false
+JavaScriptQuotes: Leave
+JavaScriptWrapImports: true
+KeepEmptyLinesAtTheStartOfBlocks: true
+MacroBlockBegin: ''
+MacroBlockEnd:   ''
+MaxEmptyLinesToKeep: 1
+NamespaceIndentation: None
+ObjCBinPackProtocolList: Auto
+ObjCBlockIndentWidth: 2
+ObjCSpaceAfterProperty: false
+ObjCSpaceBeforeProtocolList: true
+PenaltyBreakAssignment: 2
+PenaltyBreakBeforeFirstCallParameter: 19
+PenaltyBreakComment: 300
+PenaltyBreakFirstLessLess: 120
+PenaltyBreakString: 1000
+PenaltyBreakTemplateDeclaration: 10
+PenaltyExcessCharacter: 1000000
+PenaltyReturnTypeOnItsOwnLine: 60
+PointerAlignment: Right
+ReflowComments:  true
+SortIncludes:    true
+SortUsingDeclarations: true
+SpaceAfterCStyleCast: false
+SpaceAfterLogicalNot: false
+SpaceAfterTemplateKeyword: true
+SpaceBeforeAssignmentOperators: true
+SpaceBeforeCpp11BracedList: false
+SpaceBeforeCtorInitializerColon: true
+SpaceBeforeInheritanceColon: true
+SpaceBeforeParens: ControlStatements
+SpaceBeforeRangeBasedForLoopColon: true
+SpaceInEmptyBlock: false
+SpaceInEmptyParentheses: false
+SpacesBeforeTrailingComments: 1
+SpacesInAngles:  false
+SpacesInConditionalStatement: false
+SpacesInContainerLiterals: true
+SpacesInCStyleCastParentheses: false
+SpacesInParentheses: false
+SpacesInSquareBrackets: false
+SpaceBeforeSquareBrackets: false
+Standard:        Latest
+StatementMacros:
+  - Q_UNUSED
+  - QT_REQUIRE_VERSION
+TabWidth:        8
+UseCRLF:         false
+UseTab:          Never
+...
+

source/Core/BSP/BSP.h

@@ -1,10 +1,10 @@
-#include <stdint.h>
-#include <stdbool.h>
 #include "BSP_Flash.h"
 #include "BSP_Power.h"
 #include "BSP_QC.h"
 #include "Defines.h"
 #include "Model_Config.h"
+#include <stdbool.h>
+#include <stdint.h>
 /*
  * BSP.h -- Board Support
  *

source/Core/BSP/BSP_Power.h

@@ -12,7 +12,6 @@
 extern "C" {
 #endif
 
-
 // Called periodically in the movement handling thread
 // Can be used to check any details for the power system
 void power_check();

source/Core/BSP/Defines.h

@@ -8,10 +8,7 @@
 #ifndef BSP_DEFINES_H_
 #define BSP_DEFINES_H_
 
-
+enum Orientation { ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3 };
-enum Orientation {
-	ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3
-};
 
 // It is assumed that all hardware implements an 8Hz update period at this time
 #define PID_TIM_HZ   (8)

source/Core/BSP/Miniware/BSP.cpp

@@ -1,14 +1,13 @@
 // BSP mapping functions
 
-#include <IRQ.h>
 #include "BSP.h"
+#include "I2C_Wrapper.hpp"
+#include "Model_Config.h"
+#include "Pins.h"
 #include "Setup.h"
 #include "history.hpp"
-#include "Pins.h"
 #include "main.hpp"
-#include "history.hpp"
+#include <IRQ.h>
-#include "Model_Config.h"
-#include "I2C_Wrapper.hpp"
 volatile uint16_t PWMSafetyTimer = 0;
 volatile uint8_t  pendingPWM     = 0;
 
@@ -22,9 +21,7 @@ static bool fastPWM;
 
 // 2 second filter (ADC is PID_TIM_HZ Hz)
 history<uint16_t, PID_TIM_HZ> rawTempFilter = {{0}, 0, 0};
-void resetWatchdog() {
+void                          resetWatchdog() { HAL_IWDG_Refresh(&hiwdg); }
-	HAL_IWDG_Refresh(&hiwdg);
-}
 #ifdef TEMP_NTC
 // Lookup table for the NTC
 // Stored as ADCReading,Temp in degC
@@ -333,21 +330,11 @@ void unstick_I2C() {
   HAL_I2C_Init(&hi2c1);
 }
 
-uint8_t getButtonA() {
+uint8_t getButtonA() { return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ? 1 : 0; }
-	return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ? 1 : 0;
+uint8_t getButtonB() { return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ? 1 : 0; }
-}
-uint8_t getButtonB() {
-	return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ? 1 : 0;
-}
 
-void BSPInit(void) {
+void BSPInit(void) { switchToFastPWM(); }
-	switchToFastPWM();
-}
 
-void reboot() {
+void reboot() { NVIC_SystemReset(); }
-	NVIC_SystemReset();
-}
 
-void delay_ms(uint16_t count) {
+void delay_ms(uint16_t count) { HAL_Delay(count); }
-	HAL_Delay(count);
-}

source/Core/BSP/Miniware/FreeRTOSConfig.h

@@ -154,7 +154,12 @@ extern uint32_t SystemCoreClock;
 /* Normal assert() semantics without relying on the provision of an assert.h
  header file. */
 /* USER CODE BEGIN 1 */
-#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} 
+#define configASSERT(x)       \
+  if ((x) == 0) {             \
+    taskDISABLE_INTERRUPTS(); \
+    for (;;)                  \
+      ;                       \
+  }
 /* USER CODE END 1 */
 
 /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS

source/Core/BSP/Miniware/I2C_Wrapper.cpp

@@ -17,13 +17,11 @@ void FRToSI2C::CpltCallback() {
   }
 }
 
-bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t MemAddress,
+bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size) {
-		uint8_t *pData, uint16_t Size) {
 
   if (!lock())
     return false;
-	if (HAL_I2C_Mem_Read(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT,
+  if (HAL_I2C_Mem_Read(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT, pData, Size, 500) != HAL_OK) {
-			pData, Size, 500) != HAL_OK) {
 
     I2C_Unstick();
     unlock();
@@ -33,22 +31,18 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t MemAddress,
   unlock();
   return true;
 }
-bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) {
+bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }
-	return Mem_Write(address, reg, &data, 1);
-}
 
 uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) {
   uint8_t tx_data[1];
   Mem_Read(add, reg, tx_data, 1);
   return tx_data[0];
 }
-bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
+bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size) {
-		uint8_t *pData, uint16_t Size) {
 
   if (!lock())
     return false;
-	if (HAL_I2C_Mem_Write(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT,
+  if (HAL_I2C_Mem_Write(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT, pData, Size, 500) != HAL_OK) {
-			pData, Size, 500) != HAL_OK) {
 
     I2C_Unstick();
     unlock();
@@ -62,8 +56,7 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
 bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
   if (!lock())
     return false;
-	if (HAL_I2C_Master_Transmit_DMA(&hi2c1, DevAddress, pData, Size)
+  if (HAL_I2C_Master_Transmit_DMA(&hi2c1, DevAddress, pData, Size) != HAL_OK) {
-			!= HAL_OK) {
     I2C_Unstick();
     unlock();
     return false;
@@ -75,29 +68,20 @@ bool FRToSI2C::probe(uint16_t DevAddress) {
   if (!lock())
     return false;
   uint8_t buffer[1];
-	bool worked = HAL_I2C_Mem_Read(&hi2c1, DevAddress, 0x0F,
+  bool    worked = HAL_I2C_Mem_Read(&hi2c1, DevAddress, 0x0F, I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000) == HAL_OK;
-			I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000) == HAL_OK;
   unlock();
   return worked;
 }
 
-void FRToSI2C::I2C_Unstick() {
+void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
-	unstick_I2C();
-}
 
-void FRToSI2C::unlock() {
+void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); }
-	xSemaphoreGive(I2CSemaphore);
-}
 
-bool FRToSI2C::lock() {
+bool FRToSI2C::lock() { return xSemaphoreTake(I2CSemaphore, (TickType_t)50) == pdTRUE; }
-	return xSemaphoreTake(I2CSemaphore, (TickType_t)50) == pdTRUE;
-}
 
-bool FRToSI2C::writeRegistersBulk(const uint8_t address,
+bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) {
-		const I2C_REG *registers, const uint8_t registersLength) {
   for (int index = 0; index < registersLength; index++) {
-		if (!I2C_RegisterWrite(address, registers[index].reg,
+    if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) {
-				registers[index].val)) {
       return false;
     }
     if (registers[index].pause_ms)

source/Core/BSP/Miniware/IRQ.cpp

@@ -16,32 +16,17 @@ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) {
   BaseType_t xHigherPriorityTaskWoken = pdFALSE;
   if (hadc == &hadc1) {
     if (pidTaskNotification) {
-			vTaskNotifyGiveFromISR(pidTaskNotification,
+      vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken);
-					&xHigherPriorityTaskWoken);
       portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
     }
   }
 }
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
-	FRToSI2C::CpltCallback();
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
-}
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
-	FRToSI2C::CpltCallback();
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
-}
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) { FRToSI2C::CpltCallback(); }
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
-	FRToSI2C::CpltCallback();
-}
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c __unused) {
-
-	FRToSI2C::CpltCallback();
-}
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
-
-	FRToSI2C::CpltCallback();
-}
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c __unused) {
-	FRToSI2C::CpltCallback();
-}
 
 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
   (void)GPIO_Pin;

source/Core/BSP/Miniware/IRQ.h

@@ -9,10 +9,10 @@
 #define BSP_MINIWARE_IRQ_H_
 
 #include "BSP.h"
-#include "stm32f1xx_hal.h"
 #include "I2C_Wrapper.hpp"
 #include "Setup.h"
 #include "main.hpp"
+#include "stm32f1xx_hal.h"
 
 #ifdef __cplusplus
 extern "C" {

source/Core/BSP/Miniware/Power.cpp

@@ -1,12 +1,12 @@
 #include "BSP.h"
 #include "BSP_Power.h"
+#include "Model_Config.h"
+#include "Pins.h"
 #include "QC3.h"
 #include "Settings.h"
-#include "Pins.h"
 #include "fusbpd.h"
-#include "Model_Config.h"
-#include "policy_engine.h"
 #include "int_n.h"
+#include "policy_engine.h"
 bool FUSB302_present = false;
 
 void power_check() {
@@ -46,4 +46,3 @@ bool getIsPoweredByDCIN() {
   return true;
 #endif
 }
-

source/Core/BSP/Miniware/QC_GPIO.cpp

@@ -5,11 +5,11 @@
  *      Author: Ralim
  */
 #include "BSP.h"
+#include "Model_Config.h"
 #include "Pins.h"
 #include "QC3.h"
 #include "Settings.h"
 #include "stm32f1xx_hal.h"
-#include "Model_Config.h"
 #ifdef POW_QC
 void QC_DPlusZero_Six() {
   HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_RESET); // pull down D+
@@ -66,9 +66,7 @@ void QC_Post_Probe_En() {
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 }
 
-uint8_t QC_DM_PulledDown() {
+uint8_t QC_DM_PulledDown() { return HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11) == GPIO_PIN_RESET ? 1 : 0; }
-	return HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11) == GPIO_PIN_RESET ? 1 : 0;
-}
 #endif
 void QC_resync() {
 #ifdef POW_QC

source/Core/BSP/Miniware/Setup.c

@@ -75,8 +75,7 @@ void SystemClock_Config(void) {
 
   /**Initializes the CPU, AHB and APB busses clocks
    */
-	RCC_OscInitStruct.OscillatorType =
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI;
-	RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI;
   RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
   RCC_OscInitStruct.HSICalibrationValue = 16;
   RCC_OscInitStruct.LSIState            = RCC_LSI_ON;
@@ -87,20 +86,17 @@ void SystemClock_Config(void) {
 
   /**Initializes the CPU, AHB and APB busses clocks
    */
-	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
+  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-	RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV16; // TIM
                                                      // 2,3,4,5,6,7,12,13,14
-	RCC_ClkInitStruct.APB2CLKDivider =
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;  // 64 mhz to some peripherals and adc
-	RCC_HCLK_DIV1;  // 64 mhz to some peripherals and adc
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
 
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
-	PeriphClkInit.AdcClockSelection =
+  PeriphClkInit.AdcClockSelection    = RCC_ADCPCLK2_DIV6; // 6 or 8 are the only non overclocked options
-	RCC_ADCPCLK2_DIV6;  // 6 or 8 are the only non overclocked options
   HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
 
   /**Configure the Systick interrupt time
@@ -300,8 +296,7 @@ static void MX_TIM3_Init(void) {
   HAL_GPIO_Init(PWM_Out_GPIO_Port, &GPIO_InitStruct);
 #ifdef MODEL_TS100
   // Remap TIM3_CH1 to be on PB4
-	__HAL_AFIO_REMAP_TIM3_PARTIAL()
+  __HAL_AFIO_REMAP_TIM3_PARTIAL();
-	;
 #else
   // No re-map required
 #endif
@@ -370,8 +365,7 @@ static void MX_TIM2_Init(void) {
  */
 static void MX_DMA_Init(void) {
   /* DMA controller clock enable */
-	__HAL_RCC_DMA1_CLK_ENABLE()
+  __HAL_RCC_DMA1_CLK_ENABLE();
-	;
 
   /* DMA interrupt init */
   /* DMA1_Channel1_IRQn interrupt configuration */
@@ -399,12 +393,9 @@ static void MX_GPIO_Init(void) {
   GPIO_InitTypeDef GPIO_InitStruct;
 
   /* GPIO Ports Clock Enable */
-	__HAL_RCC_GPIOD_CLK_ENABLE()
+  __HAL_RCC_GPIOD_CLK_ENABLE();
-	;
+  __HAL_RCC_GPIOA_CLK_ENABLE();
-	__HAL_RCC_GPIOA_CLK_ENABLE()
+  __HAL_RCC_GPIOB_CLK_ENABLE();
-	;
-	__HAL_RCC_GPIOB_CLK_ENABLE()
-	;
 
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET);
@@ -414,26 +405,21 @@ static void MX_GPIO_Init(void) {
   GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
   HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
   /*Configure peripheral I/O remapping */
-	__HAL_AFIO_REMAP_PD01_ENABLE()
+  __HAL_AFIO_REMAP_PD01_ENABLE();
-	;
   //^ remap XTAL so that pins can be analog (all input buffers off).
   // reduces power consumption
 
   /*
    * Configure All pins as analog by default
    */
-	GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 |
+  GPIO_InitStruct.Pin  = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_15;
-	GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 |
-	GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_15;
   GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
   GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
 #ifdef MODEL_TS100
                         GPIO_PIN_3 |
 #endif
-			GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 |
+                        GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
-			GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 |
-			GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
 #ifdef MODEL_TS100
@@ -479,7 +465,5 @@ static void MX_GPIO_Init(void) {
   HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_SET);
 }
 #ifdef USE_FULL_ASSERT
-void assert_failed(uint8_t* file, uint32_t line){
+void assert_failed(uint8_t *file, uint32_t line) { asm("bkpt"); }
-	asm("bkpt");
-}
 #endif

source/Core/BSP/Miniware/Software_I2C.h

@@ -7,8 +7,8 @@
 
 #ifndef BSP_MINIWARE_SOFTWARE_I2C_H_
 #define BSP_MINIWARE_SOFTWARE_I2C_H_
-#include "Model_Config.h"
 #include "BSP.h"
+#include "Model_Config.h"
 #include "stm32f1xx_hal.h"
 #ifdef I2C_SOFT
 
@@ -18,7 +18,12 @@
 #define SOFT_SDA_LOW()  HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET)
 #define SOFT_SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port, SDA2_Pin) == GPIO_PIN_SET ? 1 : 0)
 #define SOFT_SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port, SCL2_Pin) == GPIO_PIN_SET ? 1 : 0)
-#define SOFT_I2C_DELAY() {for(int xx=0;xx<40;xx++){asm("nop");}}
+#define SOFT_I2C_DELAY()              \
+  {                                   \
+    for (int xx = 0; xx < 40; xx++) { \
+      asm("nop");                     \
+    }                                 \
+  }
 
 #endif
 

source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h

@@ -43,7 +43,6 @@
  ******************************************************************************
  */
 
-
 /** @addtogroup CMSIS
  * @{
  */
@@ -84,8 +83,7 @@
  */
 
 /*!< Interrupt Number Definition */
-typedef enum
+typedef enum {
-{
   /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
   NonMaskableInt_IRQn   = -14, /*!< 2 Non Maskable Interrupt                             */
   HardFault_IRQn        = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt                     */
@@ -159,8 +157,7 @@ typedef enum
  * @brief Analog to Digital Converter
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t SR;
   __IO uint32_t CR1;
   __IO uint32_t CR2;
@@ -183,8 +180,7 @@ typedef struct
   __IO uint32_t DR;
 } ADC_TypeDef;
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t SR;  /*!< ADC status register,    used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address         */
   __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04  */
   __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08  */
@@ -196,8 +192,7 @@ typedef struct
  * @brief Backup Registers
  */
 
-typedef struct
+typedef struct {
-{
   uint32_t      RESERVED0;
   __IO uint32_t DR1;
   __IO uint32_t DR2;
@@ -218,8 +213,7 @@ typedef struct
  * @brief Controller Area Network TxMailBox
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t TIR;
   __IO uint32_t TDTR;
   __IO uint32_t TDLR;
@@ -230,8 +224,7 @@ typedef struct
  * @brief Controller Area Network FIFOMailBox
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t RIR;
   __IO uint32_t RDTR;
   __IO uint32_t RDLR;
@@ -242,8 +235,7 @@ typedef struct
  * @brief Controller Area Network FilterRegister
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t FR1;
   __IO uint32_t FR2;
 } CAN_FilterRegister_TypeDef;
@@ -252,8 +244,7 @@ typedef struct
  * @brief Controller Area Network
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t              MCR;
   __IO uint32_t              MSR;
   __IO uint32_t              TSR;
@@ -282,8 +273,7 @@ typedef struct
  * @brief CRC calculation unit
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t DR;        /*!< CRC Data register,                           Address offset: 0x00 */
   __IO uint8_t  IDR;       /*!< CRC Independent data register,               Address offset: 0x04 */
   uint8_t       RESERVED0; /*!< Reserved,                                    Address offset: 0x05 */
@@ -291,13 +281,11 @@ typedef struct
   __IO uint32_t CR;        /*!< CRC Control register,                        Address offset: 0x08 */
 } CRC_TypeDef;
 
-
 /**
  * @brief Debug MCU
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t IDCODE;
   __IO uint32_t CR;
 } DBGMCU_TypeDef;
@@ -306,28 +294,23 @@ typedef struct
  * @brief DMA Controller
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t CCR;
   __IO uint32_t CNDTR;
   __IO uint32_t CPAR;
   __IO uint32_t CMAR;
 } DMA_Channel_TypeDef;
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t ISR;
   __IO uint32_t IFCR;
 } DMA_TypeDef;
 
-
-
 /**
  * @brief External Interrupt/Event Controller
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t IMR;
   __IO uint32_t EMR;
   __IO uint32_t RTSR;
@@ -340,8 +323,7 @@ typedef struct
  * @brief FLASH Registers
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t ACR;
   __IO uint32_t KEYR;
   __IO uint32_t OPTKEYR;
@@ -357,8 +339,7 @@ typedef struct
  * @brief Option Bytes Registers
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint16_t RDP;
   __IO uint16_t USER;
   __IO uint16_t Data0;
@@ -373,8 +354,7 @@ typedef struct
  * @brief General Purpose I/O
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t CRL;
   __IO uint32_t CRH;
   __IO uint32_t IDR;
@@ -388,8 +368,7 @@ typedef struct
  * @brief Alternate Function I/O
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t EVCR;
   __IO uint32_t MAPR;
   __IO uint32_t EXTICR[4];
@@ -400,8 +379,7 @@ typedef struct
  * @brief Inter Integrated Circuit Interface
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t CR1;
   __IO uint32_t CR2;
   __IO uint32_t OAR1;
@@ -417,8 +395,7 @@ typedef struct
  * @brief Independent WATCHDOG
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t KR;  /*!< Key register,                                Address offset: 0x00 */
   __IO uint32_t PR;  /*!< Prescaler register,                          Address offset: 0x04 */
   __IO uint32_t RLR; /*!< Reload register,                             Address offset: 0x08 */
@@ -429,8 +406,7 @@ typedef struct
  * @brief Power Control
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t CR;
   __IO uint32_t CSR;
 } PWR_TypeDef;
@@ -439,8 +415,7 @@ typedef struct
  * @brief Reset and Clock Control
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t CR;
   __IO uint32_t CFGR;
   __IO uint32_t CIR;
@@ -452,15 +427,13 @@ typedef struct
   __IO uint32_t BDCR;
   __IO uint32_t CSR;
 
-
 } RCC_TypeDef;
 
 /**
  * @brief Real-Time Clock
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t CRH;
   __IO uint32_t CRL;
   __IO uint32_t PRLH;
@@ -477,8 +450,7 @@ typedef struct
  * @brief SD host Interface
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t POWER;
   __IO uint32_t CLKCR;
   __IO uint32_t ARG;
@@ -505,8 +477,7 @@ typedef struct
  * @brief Serial Peripheral Interface
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t CR1;
   __IO uint32_t CR2;
   __IO uint32_t SR;
@@ -520,8 +491,7 @@ typedef struct
 /**
  * @brief TIM Timers
  */
-typedef struct
+typedef struct {
-{
   __IO uint32_t CR1;   /*!< TIM control register 1,                      Address offset: 0x00 */
   __IO uint32_t CR2;   /*!< TIM control register 2,                      Address offset: 0x04 */
   __IO uint32_t SMCR;  /*!< TIM slave Mode Control register,             Address offset: 0x08 */
@@ -545,13 +515,11 @@ typedef struct
   __IO uint32_t OR;    /*!< TIM option register,                         Address offset: 0x50 */
 } TIM_TypeDef;
 
-
 /**
  * @brief Universal Synchronous Asynchronous Receiver Transmitter
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t SR;   /*!< USART Status register,                   Address offset: 0x00 */
   __IO uint32_t DR;   /*!< USART Data register,                     Address offset: 0x04 */
   __IO uint32_t BRR;  /*!< USART Baud rate register,                Address offset: 0x08 */
@@ -565,8 +533,7 @@ typedef struct
  * @brief Universal Serial Bus Full Speed Device
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint16_t EP0R;          /*!< USB Endpoint 0 register,                   Address offset: 0x00 */
   __IO uint16_t RESERVED0;     /*!< Reserved */
   __IO uint16_t EP1R;          /*!< USB Endpoint 1 register,                   Address offset: 0x04 */
@@ -595,13 +562,11 @@ typedef struct
   __IO uint16_t RESERVEDC;     /*!< Reserved */
 } USB_TypeDef;
 
-
 /**
  * @brief Window WATCHDOG
  */
 
-typedef struct
+typedef struct {
-{
   __IO uint32_t CR;  /*!< WWDG Control register,       Address offset: 0x00 */
   __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
   __IO uint32_t SR;  /*!< WWDG Status register,        Address offset: 0x08 */
@@ -615,7 +580,6 @@ typedef struct
  * @{
  */
 
-
 #define FLASH_BASE      0x08000000U /*!< FLASH base address in the alias region */
 #define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
 #define SRAM_BASE       0x20000000U /*!< SRAM base address in the alias region */
@@ -624,7 +588,6 @@ typedef struct
 #define SRAM_BB_BASE   0x22000000U /*!< SRAM base address in the bit-band region */
 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
 
-
 /*!< Peripheral memory map */
 #define APB1PERIPH_BASE PERIPH_BASE
 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
@@ -675,15 +638,12 @@ typedef struct
 #define UID_BASE       0x1FFFF7E8U                    /*!< Unique device ID register base address */
 #define OB_BASE        0x1FFFF800U                    /*!< Flash Option Bytes base address */
 
-
-
 #define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
 
 /* USB device FS */
 #define USB_BASE    (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
 
-
 /**
  * @}
  */
@@ -735,7 +695,6 @@ typedef struct
 #define OB            ((OB_TypeDef *)OB_BASE)
 #define DBGMCU        ((DBGMCU_TypeDef *)DBGMCU_BASE)
 
-
 /**
  * @}
  */
@@ -827,7 +786,6 @@ typedef struct
 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
 #define PWR_CR_DBP     PWR_CR_DBP_Msk           /*!< Disable Backup Domain write protection */
 
-
 /*******************  Bit definition for PWR_CSR register  ********************/
 #define PWR_CSR_WUF_Pos  (0U)
 #define PWR_CSR_WUF_Msk  (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
@@ -977,7 +935,6 @@ typedef struct
 #define RCC_CR_PLLRDY_Msk  (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
 #define RCC_CR_PLLRDY      RCC_CR_PLLRDY_Msk           /*!< PLL clock ready flag */
 
-
 /*******************  Bit definition for RCC_CFGR register  *******************/
 /*!< SW configuration */
 #define RCC_CFGR_SW_Pos (0U)
@@ -1205,7 +1162,6 @@ typedef struct
 #define RCC_CIR_CSSC_Msk     (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
 #define RCC_CIR_CSSC         RCC_CIR_CSSC_Msk           /*!< Clock Security System Interrupt Clear */
 
-
 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
 #define RCC_APB2RSTR_AFIORST_Pos (0U)
 #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
@@ -1240,14 +1196,10 @@ typedef struct
 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
 #define RCC_APB2RSTR_USART1RST     RCC_APB2RSTR_USART1RST_Msk           /*!< USART1 reset */
 
-
 #define RCC_APB2RSTR_IOPERST_Pos (6U)
 #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
 #define RCC_APB2RSTR_IOPERST     RCC_APB2RSTR_IOPERST_Msk           /*!< I/O port E reset */
 
-
-
-
 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
 #define RCC_APB1RSTR_TIM2RST_Pos   (0U)
 #define RCC_APB1RSTR_TIM2RST_Msk   (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
@@ -1293,11 +1245,6 @@ typedef struct
 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
 #define RCC_APB1RSTR_USBRST     RCC_APB1RSTR_USBRST_Msk           /*!< USB Device reset */
 
-
-
-
-
-
 /******************  Bit definition for RCC_AHBENR register  ******************/
 #define RCC_AHBENR_DMA1EN_Pos  (0U)
 #define RCC_AHBENR_DMA1EN_Msk  (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
@@ -1312,9 +1259,6 @@ typedef struct
 #define RCC_AHBENR_CRCEN_Msk   (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
 #define RCC_AHBENR_CRCEN       RCC_AHBENR_CRCEN_Msk           /*!< CRC clock enable */
 
-
-
-
 /******************  Bit definition for RCC_APB2ENR register  *****************/
 #define RCC_APB2ENR_AFIOEN_Pos (0U)
 #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
@@ -1349,14 +1293,10 @@ typedef struct
 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
 #define RCC_APB2ENR_USART1EN     RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
 
-
 #define RCC_APB2ENR_IOPEEN_Pos (6U)
 #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
 #define RCC_APB2ENR_IOPEEN     RCC_APB2ENR_IOPEEN_Msk           /*!< I/O port E clock enable */
 
-
-
-
 /*****************  Bit definition for RCC_APB1ENR register  ******************/
 #define RCC_APB1ENR_TIM2EN_Pos   (0U)
 #define RCC_APB1ENR_TIM2EN_Msk   (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
@@ -1402,11 +1342,6 @@ typedef struct
 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
 #define RCC_APB1ENR_USBEN     RCC_APB1ENR_USBEN_Msk           /*!< USB Device clock enable */
 
-
-
-
-
-
 /*******************  Bit definition for RCC_BDCR register  *******************/
 #define RCC_BDCR_LSEON_Pos  (0U)
 #define RCC_BDCR_LSEON_Msk  (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
@@ -1466,8 +1401,6 @@ typedef struct
 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
 #define RCC_CSR_LPWRRSTF     RCC_CSR_LPWRRSTF_Msk           /*!< Low-Power reset flag */
 
-
- 
 /******************************************************************************/
 /*                                                                            */
 /*                General Purpose and Alternate Function I/O                  */
@@ -2190,7 +2123,6 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk     (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
 #define AFIO_MAPR_SWJ_CFG_DISABLE         AFIO_MAPR_SWJ_CFG_DISABLE_Msk           /*!< JTAG-DP Disabled and SW-DP Disabled */
 
-
 /*****************  Bit definition for AFIO_EXTICR1 register  *****************/
 #define AFIO_EXTICR1_EXTI0_Pos (0U)
 #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
@@ -2585,8 +2517,6 @@ typedef struct
 
 /******************  Bit definition for AFIO_MAPR2 register  ******************/
 
-
-
 /******************************************************************************/
 /*                                                                            */
 /*                    External Interrupt/Event Controller                     */
@@ -3843,7 +3773,6 @@ typedef struct
 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
 #define ADC_DR_ADC2DATA     ADC_DR_ADC2DATA_Msk              /*!< ADC group regular conversion data for ADC slave, in multimode */
 
-
 /*****************************************************************************/
 /*                                                                           */
 /*                               Timers (TIM)                                */
@@ -4560,7 +4489,6 @@ typedef struct
 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
 #define WWDG_SR_EWIF     WWDG_SR_EWIF_Msk           /*!< Early Wakeup Interrupt Flag */
 
-
 /******************************************************************************/
 /*                                                                            */
 /*                          SD host Interface                                 */
@@ -9601,7 +9529,6 @@ typedef struct
 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
 #define SPI_I2SCFGR_I2SMOD     SPI_I2SCFGR_I2SMOD_Msk           /*!< I2S mode selection */
 
-
 /******************************************************************************/
 /*                                                                            */
 /*                      Inter-integrated Circuit Interface                    */
@@ -10271,8 +10198,6 @@ typedef struct
 #define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
 #define FLASH_WRP3_nWRP3     FLASH_WRP3_nWRP3_Msk            /*!< Flash memory write protection complemented option bytes */
 
-
-
 /**
  * @}
  */
@@ -10286,8 +10211,7 @@ typedef struct
  */
 
 /****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || ((INSTANCE) == ADC2))
-                                       ((INSTANCE) == ADC2))
 
 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
 
@@ -10304,20 +10228,12 @@ typedef struct
 /****************************** DAC Instances *********************************/
 
 /****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+#define IS_DMA_ALL_INSTANCE(INSTANCE)                                                                                                                                                                 \
-                                       ((INSTANCE) == DMA1_Channel2) || \
+  (((INSTANCE) == DMA1_Channel1) || ((INSTANCE) == DMA1_Channel2) || ((INSTANCE) == DMA1_Channel3) || ((INSTANCE) == DMA1_Channel4) || ((INSTANCE) == DMA1_Channel5) || ((INSTANCE) == DMA1_Channel6) \
-                                       ((INSTANCE) == DMA1_Channel3) || \
+   || ((INSTANCE) == DMA1_Channel7))
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7))
 
 /******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE))
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE))
 
 /**************************** GPIO Alternate Function Instances ***************/
 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
@@ -10326,8 +10242,7 @@ typedef struct
 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
 
 /******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2))
-                                       ((INSTANCE) == I2C2))
 
 /******************************* SMBUS Instances ******************************/
 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
@@ -10336,228 +10251,100 @@ typedef struct
 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
 
 /******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2))
-                                       ((INSTANCE) == SPI2))
 
 /****************************** START TIM Instances ***************************/
 /****************************** TIM Instances *********************************/
-#define IS_TIM_INSTANCE(INSTANCE)\
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
 
-#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
 
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-  ((INSTANCE) == TIM1)
 
 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL)                                                                                                                 \
-   ((((INSTANCE) == TIM1) &&                  \
+  ((((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4)))    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+   || (((INSTANCE) == TIM2) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+   || (((INSTANCE) == TIM3) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+   || (((INSTANCE) == TIM4) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))))
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4))))
 
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3)))
-    (((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))
 
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-  ((INSTANCE) == TIM1)
 
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-  (((INSTANCE) == TIM1)    || \
-   ((INSTANCE) == TIM2)    || \
-   ((INSTANCE) == TIM3)    || \
-   ((INSTANCE) == TIM4))
 
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-  ((INSTANCE) == TIM1)
 
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-                                        ((INSTANCE) == TIM2)    || \
-                                        ((INSTANCE) == TIM3)    || \
-                                        ((INSTANCE) == TIM4))
 
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
-                                                         ((INSTANCE) == TIM2)    || \
-                                                         ((INSTANCE) == TIM3)    || \
-                                                         ((INSTANCE) == TIM4))
 
 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
 
 /****************************** END TIM Instances *****************************/
 
-
 /******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
 
 /******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
 
 /******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
-                                               ((INSTANCE) == USART2) || \
-                                               ((INSTANCE) == USART3))
 
 /******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
-                                        ((INSTANCE) == USART2) || \
-                                        ((INSTANCE) == USART3))
 
 /****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
 
 /********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
 
 /*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
 
 /***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
-                                                   ((INSTANCE) == USART2) || \
-                                                   ((INSTANCE) == USART3))
 
 /***************** UART Instances : DMA mode available **********************/
-#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
-                                        ((INSTANCE) == USART2) || \
-                                        ((INSTANCE) == USART3))
 
 /****************************** RTC Instances *********************************/
 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -10568,8 +10355,6 @@ typedef struct
 /****************************** USB Instances ********************************/
 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
 
-
-
 #define RCC_HSE_MIN 4000000U
 #define RCC_HSE_MAX 16000000U
 
@@ -10604,7 +10389,6 @@ typedef struct
 #define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn
 #define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn
 
-
 /* Aliases for __IRQHandler */
 #define ADC1_IRQHandler               ADC1_2_IRQHandler
 #define TIM9_IRQHandler               TIM1_BRK_IRQHandler
@@ -10623,7 +10407,6 @@ typedef struct
 #define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler
 #define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler
 
-
 /**
  * @}
  */
@@ -10632,13 +10415,10 @@ typedef struct
  * @}
  */
 
-
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
 
 #endif /* __STM32F103xB_H */
 
-  
-  
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h

@@ -75,9 +75,8 @@
    application
   */
 
-#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
+#if !defined(STM32F100xB) && !defined(STM32F100xE) && !defined(STM32F101x6) && !defined(STM32F101xB) && !defined(STM32F101xE) && !defined(STM32F101xG) && !defined(STM32F102x6) \
-    !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
+    && !defined(STM32F102xB) && !defined(STM32F103x6) && !defined(STM32F103xB) && !defined(STM32F103xE) && !defined(STM32F103xG) && !defined(STM32F105xC) && !defined(STM32F107xC)
-    !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
 /* #define STM32F100xB  */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
 /* #define STM32F100xE */  /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
 /* #define STM32F101x6  */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
@@ -114,10 +113,7 @@
 #define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
 #define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8]  sub2 version */
 #define __STM32F1_CMSIS_VERSION_RC   (0x00) /*!< [7:0]  release candidate */
-#define __STM32F1_CMSIS_VERSION        ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
+#define __STM32F1_CMSIS_VERSION      ((__STM32F1_CMSIS_VERSION_MAIN << 24) | (__STM32F1_CMSIS_VERSION_SUB1 << 16) | (__STM32F1_CMSIS_VERSION_SUB2 << 8) | (__STM32F1_CMSIS_VERSION_RC))
-                                       |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
-                                       |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
-                                       |(__STM32F1_CMSIS_VERSION_RC))
 
 /**
  * @}
@@ -166,30 +162,17 @@
 /** @addtogroup Exported_types
  * @{
  */
-typedef enum 
+typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
 
-typedef enum 
+typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState;
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
 
-typedef enum 
+typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrorStatus;
-{
-  ERROR = 0, 
-  SUCCESS = !ERROR
-} ErrorStatus;
 
 /**
  * @}
  */
 
-
 /** @addtogroup Exported_macros
  * @{
  */
@@ -209,7 +192,6 @@ typedef enum
 
 #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
 
-
 /**
  * @}
  */
@@ -218,7 +200,6 @@ typedef enum
 #include "stm32f1xx_hal.h"
 #endif /* USE_HAL_DRIVER */
 
-
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
@@ -232,7 +213,4 @@ typedef enum
  * @}
  */
 
-
-
-
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h

@@ -61,7 +61,6 @@
  * @}
  */
 
-
 /** @addtogroup STM32F10x_System_Exported_types
  * @{
  */

source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_common_tables.h

@@ -85,7 +85,6 @@ extern const float32_t twiddleCoef_rfft_1024[1024];
 extern const float32_t twiddleCoef_rfft_2048[2048];
 extern const float32_t twiddleCoef_rfft_4096[4096];
 
-
 /* floating-point bit reversal tables */
 #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20)
 #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48)

source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_const_structs.h

@@ -43,8 +43,8 @@
 #ifndef _ARM_CONST_STRUCTS_H
 #define _ARM_CONST_STRUCTS_H
 
-#include "arm_math.h"
 #include "arm_common_tables.h"
+#include "arm_math.h"
 
 extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
 extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;

source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_armcc.h

@@ -31,11 +31,9 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #ifndef __CMSIS_ARMCC_H
 #define __CMSIS_ARMCC_H
 
-
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
 #endif
@@ -54,133 +52,111 @@
   \details Returns the content of the Control Register.
   \return               Control Register value
  */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
+__STATIC_INLINE uint32_t __get_CONTROL(void) {
-{
   register uint32_t __regControl __ASM("control");
   return (__regControl);
 }
 
-
 /**
   \brief   Set Control Register
   \details Writes the given value to the Control Register.
   \param [in]    control  Control Register value to set
  */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
+__STATIC_INLINE void __set_CONTROL(uint32_t control) {
-{
   register uint32_t __regControl __ASM("control");
   __regControl = control;
 }
 
-
 /**
   \brief   Get IPSR Register
   \details Returns the content of the IPSR Register.
   \return               IPSR Register value
  */
-__STATIC_INLINE uint32_t __get_IPSR(void)
+__STATIC_INLINE uint32_t __get_IPSR(void) {
-{
   register uint32_t __regIPSR __ASM("ipsr");
   return (__regIPSR);
 }
 
-
 /**
   \brief   Get APSR Register
   \details Returns the content of the APSR Register.
   \return               APSR Register value
  */
-__STATIC_INLINE uint32_t __get_APSR(void)
+__STATIC_INLINE uint32_t __get_APSR(void) {
-{
   register uint32_t __regAPSR __ASM("apsr");
   return (__regAPSR);
 }
 
-
 /**
   \brief   Get xPSR Register
   \details Returns the content of the xPSR Register.
   \return               xPSR Register value
  */
-__STATIC_INLINE uint32_t __get_xPSR(void)
+__STATIC_INLINE uint32_t __get_xPSR(void) {
-{
   register uint32_t __regXPSR __ASM("xpsr");
   return (__regXPSR);
 }
 
-
 /**
   \brief   Get Process Stack Pointer
   \details Returns the current value of the Process Stack Pointer (PSP).
   \return               PSP Register value
  */
-__STATIC_INLINE uint32_t __get_PSP(void)
+__STATIC_INLINE uint32_t __get_PSP(void) {
-{
   register uint32_t __regProcessStackPointer __ASM("psp");
   return (__regProcessStackPointer);
 }
 
-
 /**
   \brief   Set Process Stack Pointer
   \details Assigns the given value to the Process Stack Pointer (PSP).
   \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) {
-{
   register uint32_t __regProcessStackPointer __ASM("psp");
   __regProcessStackPointer = topOfProcStack;
 }
 
-
 /**
   \brief   Get Main Stack Pointer
   \details Returns the current value of the Main Stack Pointer (MSP).
   \return               MSP Register value
  */
-__STATIC_INLINE uint32_t __get_MSP(void)
+__STATIC_INLINE uint32_t __get_MSP(void) {
-{
   register uint32_t __regMainStackPointer __ASM("msp");
   return (__regMainStackPointer);
 }
 
-
 /**
   \brief   Set Main Stack Pointer
   \details Assigns the given value to the Main Stack Pointer (MSP).
   \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) {
-{
   register uint32_t __regMainStackPointer __ASM("msp");
   __regMainStackPointer = topOfMainStack;
 }
 
-
 /**
   \brief   Get Priority Mask
   \details Returns the current state of the priority mask bit from the Priority Mask Register.
   \return               Priority Mask value
  */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
+__STATIC_INLINE uint32_t __get_PRIMASK(void) {
-{
   register uint32_t __regPriMask __ASM("primask");
   return (__regPriMask);
 }
 
-
 /**
   \brief   Set Priority Mask
   \details Assigns the given value to the Priority Mask Register.
   \param [in]    priMask  Priority Mask
  */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) {
-{
   register uint32_t __regPriMask __ASM("primask");
   __regPriMask = (priMask);
 }
 
-
 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
 
 /**
@@ -190,7 +166,6 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  */
 #define __enable_fault_irq __enable_fiq
 
-
 /**
   \brief   Disable FIQ
   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
@@ -198,70 +173,59 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  */
 #define __disable_fault_irq __disable_fiq
 
-
 /**
   \brief   Get Base Priority
   \details Returns the current value of the Base Priority register.
   \return               Base Priority register value
  */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+__STATIC_INLINE uint32_t __get_BASEPRI(void) {
-{
   register uint32_t __regBasePri __ASM("basepri");
   return (__regBasePri);
 }
 
-
 /**
   \brief   Set Base Priority
   \details Assigns the given value to the Base Priority register.
   \param [in]    basePri  Base Priority value to set
  */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) {
-{
   register uint32_t __regBasePri __ASM("basepri");
   __regBasePri = (basePri & 0xFFU);
 }
 
-
 /**
   \brief   Set Base Priority with condition
   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
            or the new value increases the BASEPRI priority level.
   \param [in]    basePri  Base Priority value to set
  */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) {
-{
   register uint32_t __regBasePriMax __ASM("basepri_max");
   __regBasePriMax = (basePri & 0xFFU);
 }
 
-
 /**
   \brief   Get Fault Mask
   \details Returns the current value of the Fault Mask register.
   \return               Fault Mask register value
  */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+__STATIC_INLINE uint32_t __get_FAULTMASK(void) {
-{
   register uint32_t __regFaultMask __ASM("faultmask");
   return (__regFaultMask);
 }
 
-
 /**
   \brief   Set Fault Mask
   \details Assigns the given value to the Fault Mask register.
   \param [in]    faultMask  Fault Mask value to set
  */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) {
-{
   register uint32_t __regFaultMask __ASM("faultmask");
   __regFaultMask = (faultMask & (uint32_t)1);
 }
 
 #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
 
-
 #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
 
 /**
@@ -269,8 +233,7 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
   \details Returns the current value of the Floating Point Status/Control register.
   \return               Floating Point Status/Control register value
  */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
+__STATIC_INLINE uint32_t __get_FPSCR(void) {
-{
 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
   register uint32_t __regfpscr __ASM("fpscr");
   return (__regfpscr);
@@ -279,14 +242,12 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
 #endif
 }
 
-
 /**
   \brief   Set FPSCR
   \details Assigns the given value to the Floating Point Status/Control register.
   \param [in]    fpscr  Floating Point Status/Control value to set
  */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) {
-{
 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
   register uint32_t __regfpscr __ASM("fpscr");
   __regfpscr = (fpscr);
@@ -295,11 +256,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 
 #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
 
-
-
 /*@} end of CMSIS_Core_RegAccFunctions */
 
-
 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions
@@ -312,14 +270,12 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  */
 #define __NOP __nop
 
-
 /**
   \brief   Wait For Interrupt
   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
  */
 #define __WFI __wfi
 
-
 /**
   \brief   Wait For Event
   \details Wait For Event is a hint instruction that permits the processor to enter
@@ -327,21 +283,20 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  */
 #define __WFE __wfe
 
-
 /**
   \brief   Send Event
   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  */
 #define __SEV __sev
 
-
 /**
   \brief   Instruction Synchronization Barrier
   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
            so that all instructions following the ISB are fetched from cache or memory,
            after the instruction has been completed.
  */
-#define __ISB() do {\
+#define __ISB()           \
+  do {                    \
     __schedule_barrier(); \
     __isb(0xF);           \
     __schedule_barrier(); \
@@ -352,7 +307,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
   \details Acts as a special kind of Data Memory Barrier.
            It completes when all explicit memory accesses before this instruction complete.
  */
-#define __DSB() do {\
+#define __DSB()           \
+  do {                    \
     __schedule_barrier(); \
     __dsb(0xF);           \
     __schedule_barrier(); \
@@ -363,7 +319,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
   \details Ensures the apparent order of the explicit memory operations before
            and after the instruction, without ensuring their completion.
  */
-#define __DMB() do {\
+#define __DMB()           \
+  do {                    \
     __schedule_barrier(); \
     __dmb(0xF);           \
     __schedule_barrier(); \
@@ -377,7 +334,6 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  */
 #define __REV __rev
 
-
 /**
   \brief   Reverse byte order (16 bit)
   \details Reverses the byte order in two unsigned short values.
@@ -385,11 +341,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
   \return               Reversed value
  */
 #ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr }
-{
-  rev16 r0, r0
-  bx lr
-}
 #endif
 
 /**
@@ -399,14 +351,9 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
   \return               Reversed value
  */
 #ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr }
-{
-  revsh r0, r0
-  bx lr
-}
 #endif
 
-
 /**
   \brief   Rotate Right in unsigned value (32 bit)
   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@@ -416,7 +363,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
  */
 #define __ROR __ror
 
-
 /**
   \brief   Breakpoint
   \details Causes the processor to enter Debug state.
@@ -426,7 +372,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
  */
 #define __BKPT(value) __breakpoint(value)
 
-
 /**
   \brief   Reverse bit order of value
   \details Reverses the bit order of the given value.
@@ -436,14 +381,12 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
 #define __RBIT __rbit
 #else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
-{
   uint32_t result;
   int32_t  s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
 
   result = value; /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value; value >>= 1U)
+  for (value >>= 1U; value; value >>= 1U) {
-  {
     result <<= 1U;
     result |= value & 1U;
     s--;
@@ -453,7 +396,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 }
 #endif
 
-
 /**
   \brief   Count leading zeros
   \details Counts the number of leading zeros of a data value.
@@ -462,7 +404,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
  */
 #define __CLZ __clz
 
-
 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
 
 /**
@@ -477,7 +418,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop")
 #endif
 
-
 /**
   \brief   LDR Exclusive (16 bit)
   \details Executes a exclusive LDR instruction for 16 bit values.
@@ -490,7 +430,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop")
 #endif
 
-
 /**
   \brief   LDR Exclusive (32 bit)
   \details Executes a exclusive LDR instruction for 32 bit values.
@@ -503,7 +442,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop")
 #endif
 
-
 /**
   \brief   STR Exclusive (8 bit)
   \details Executes a exclusive STR instruction for 8 bit values.
@@ -518,7 +456,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
 #endif
 
-
 /**
   \brief   STR Exclusive (16 bit)
   \details Executes a exclusive STR instruction for 16 bit values.
@@ -533,7 +470,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
 #endif
 
-
 /**
   \brief   STR Exclusive (32 bit)
   \details Executes a exclusive STR instruction for 32 bit values.
@@ -548,14 +484,12 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
 #endif
 
-
 /**
   \brief   Remove the exclusive lock
   \details Removes the exclusive lock which is created by LDREX.
  */
 #define __CLREX __clrex
 
-
 /**
   \brief   Signed Saturate
   \details Saturates a signed value.
@@ -565,7 +499,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
  */
 #define __SSAT __ssat
 
-
 /**
   \brief   Unsigned Saturate
   \details Saturates an unsigned value.
@@ -575,7 +508,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
  */
 #define __USAT __usat
 
-
 /**
   \brief   Rotate Right with Extend (32 bit)
   \details Moves each bit of a bitstring right by one bit.
@@ -584,14 +516,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return               Rotated value
  */
 #ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr }
-{
-  rrx r0, r0
-  bx lr
-}
 #endif
 
-
 /**
   \brief   LDRT Unprivileged (8 bit)
   \details Executes a Unprivileged LDRT instruction for 8 bit value.
@@ -600,7 +527,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
  */
 #define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
 
-
 /**
   \brief   LDRT Unprivileged (16 bit)
   \details Executes a Unprivileged LDRT instruction for 16 bit values.
@@ -609,7 +535,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
  */
 #define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
 
-
 /**
   \brief   LDRT Unprivileged (32 bit)
   \details Executes a Unprivileged LDRT instruction for 32 bit values.
@@ -618,7 +543,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
  */
 #define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
 
-
 /**
   \brief   STRT Unprivileged (8 bit)
   \details Executes a Unprivileged STRT instruction for 8 bit values.
@@ -627,7 +551,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
  */
 #define __STRBT(value, ptr) __strt(value, ptr)
 
-
 /**
   \brief   STRT Unprivileged (16 bit)
   \details Executes a Unprivileged STRT instruction for 16 bit values.
@@ -636,7 +559,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
  */
 #define __STRHT(value, ptr) __strt(value, ptr)
 
-
 /**
   \brief   STRT Unprivileged (32 bit)
   \details Executes a Unprivileged STRT instruction for 32 bit values.
@@ -649,7 +571,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
 
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
-
 /* ###################  Compiler specific Intrinsics  ########################### */
 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
   Access to dedicated SIMD instructions
@@ -718,17 +639,13 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
 #define __QADD    __qadd
 #define __QSUB    __qsub
 
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
 
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
 
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+#define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U)) >> 32U))
-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
 
 #endif /* (__CORTEX_M >= 0x04) */
 /*@} end of group CMSIS_SIMD_intrinsics */
 
-
 #endif /* __CMSIS_ARMCC_H */

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0.h

@@ -31,7 +31,6 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #if defined(__ICCARM__)
 #pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
      Function-like macros are used to allow more efficient code.
  */
 
-
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
@@ -73,12 +71,10 @@
 /*  CMSIS CM0 definitions */
 #define __CM0_CMSIS_VERSION_MAIN (0x04U)                                                       /*!< [31:16] CMSIS HAL main version */
 #define __CM0_CMSIS_VERSION_SUB  (0x1EU)                                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+#define __CM0_CMSIS_VERSION      ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-                                    __CM0_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
 
 #define __CORTEX_M (0x00U) /*!< Cortex-M Core */
 
-
 #if defined(__CC_ARM)
 #define __ASM           __asm    /*!< asm keyword for ARM Compiler */
 #define __INLINE        __inline /*!< inline keyword for ARM Compiler */
@@ -160,8 +156,8 @@
 
 #endif
 
-#include "core_cmInstr.h"                /* Core Instruction Access */
 #include "core_cmFunc.h"  /* Core Function Access */
+#include "core_cmInstr.h" /* Core Instruction Access */
 
 #ifdef __cplusplus
 }
@@ -219,8 +215,6 @@
 
 /*@} end of group Cortex_M0 */
 
-
-
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
@@ -244,10 +238,8 @@
 /**
   \brief  Union type to access the Application Program Status Register (APSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t _reserved0 : 28; /*!< bit:  0..27  Reserved */
     uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
     uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
@@ -270,14 +262,11 @@ typedef union
 #define APSR_V_Pos 28U                 /*!< APSR: V Position */
 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
 
-
 /**
   \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
   } b;                        /*!< Structure used for bit  access */
@@ -288,14 +277,11 @@ typedef union
 #define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
     uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
@@ -327,14 +313,11 @@ typedef union
 #define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Control Registers (CONTROL).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t _reserved0 : 1;  /*!< bit:      0  Reserved */
     uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
     uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
@@ -348,7 +331,6 @@ typedef union
 
 /*@} end of group CMSIS_CORE */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
@@ -359,8 +341,7 @@ typedef union
 /**
   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
   uint32_t       RESERVED0[31U];
   __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
@@ -375,7 +356,6 @@ typedef struct
 
 /*@} end of group CMSIS_NVIC */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCB     System Control Block (SCB)
@@ -386,8 +366,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control Block (SCB).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register */
   __IOM uint32_t ICSR;  /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
   uint32_t       RESERVED0;
@@ -482,7 +461,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
@@ -493,8 +471,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Timer (SysTick).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
   __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
@@ -534,7 +511,6 @@ typedef struct
 
 /*@} end of group CMSIS_SysTick */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
@@ -544,7 +520,6 @@ typedef struct
  */
 /*@} end of group CMSIS_CoreDebug */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_bitfield     Core register bit field macros
@@ -570,7 +545,6 @@ typedef struct
 
 /*@} end of group CMSIS_core_bitfield */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_base     Core Definitions
@@ -588,11 +562,8 @@ typedef struct
 #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
 #define NVIC    ((NVIC_Type *)NVIC_BASE)       /*!< NVIC configuration struct */
 
-
 /*@} */
 
-
-
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
@@ -604,8 +575,6 @@ typedef struct
   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
-
-
 /* ##########################   NVIC functions  #################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -620,28 +589,19 @@ typedef struct
 #define _SHP_IDX(IRQn)   ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
 #define _IP_IDX(IRQn)    ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
 
-
 /**
   \brief   Enable External Interrupt
   \details Enables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Disable External Interrupt
   \details Disables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Pending Interrupt
@@ -650,33 +610,21 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not pending.
   \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
-{
-  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
 
 /**
   \brief   Set Pending Interrupt
   \details Sets the pending bit of an external interrupt.
   \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Clear Pending Interrupt
   \details Clears the pending bit of an external interrupt.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Set Interrupt Priority
@@ -685,21 +633,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
-{
+  if ((int32_t)(IRQn) < 0) {
-  if ((int32_t)(IRQn) < 0)
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  {
+  } else {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+    NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
   }
 }
 
-
 /**
   \brief   Get Interrupt Priority
   \details Reads the priority of an interrupt.
@@ -709,30 +650,23 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
   \return             Interrupt Priority.
                       Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
-{
 
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) < 0) {
-  {
     return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
+  } else {
-  else
-  {
     return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
-
 /**
   \brief   System Reset
   \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void) {
-{
   __DSB(); /* Ensure all outstanding memory accesses included
               buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
-                 SCB_AIRCR_SYSRESETREQ_Msk);
   __DSB(); /* Ensure completion of memory access */
 
   for (;;) /* wait until reset */
@@ -743,8 +677,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
-
-
 /* ##################################    SysTick function  ############################################ */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -766,19 +698,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
            must contain a vendor-specific implementation of this function.
  */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
-{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
     return (1UL); /* Reload value impossible */
   }
 
   SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
   NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
   SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
   return (0UL);                                                                                    /* Function successful */
 }
 
@@ -786,9 +714,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 /*@} end of CMSIS_Core_SysTickFunctions */
 
-
-
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0plus.h

@@ -31,7 +31,6 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #if defined(__ICCARM__)
 #pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
      Function-like macros are used to allow more efficient code.
  */
 
-
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
@@ -73,12 +71,10 @@
 /*  CMSIS CM0+ definitions */
 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)                                                               /*!< [31:16] CMSIS HAL main version */
 #define __CM0PLUS_CMSIS_VERSION_SUB  (0x1EU)                                                               /*!< [15:0]  CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-                                       __CM0PLUS_CMSIS_VERSION_SUB           ) /*!< CMSIS HAL version number */
 
 #define __CORTEX_M (0x00U) /*!< Cortex-M Core */
 
-
 #if defined(__CC_ARM)
 #define __ASM           __asm    /*!< asm keyword for ARM Compiler */
 #define __INLINE        __inline /*!< inline keyword for ARM Compiler */
@@ -160,8 +156,8 @@
 
 #endif
 
-#include "core_cmInstr.h"                /* Core Instruction Access */
 #include "core_cmFunc.h"  /* Core Function Access */
+#include "core_cmInstr.h" /* Core Instruction Access */
 
 #ifdef __cplusplus
 }
@@ -229,8 +225,6 @@
 
 /*@} end of group Cortex-M0+ */
 
-
-
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
@@ -255,10 +249,8 @@
 /**
   \brief  Union type to access the Application Program Status Register (APSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t _reserved0 : 28; /*!< bit:  0..27  Reserved */
     uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
     uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
@@ -281,14 +273,11 @@ typedef union
 #define APSR_V_Pos 28U                 /*!< APSR: V Position */
 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
 
-
 /**
   \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
   } b;                        /*!< Structure used for bit  access */
@@ -299,14 +288,11 @@ typedef union
 #define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
     uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
@@ -338,14 +324,11 @@ typedef union
 #define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Control Registers (CONTROL).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
     uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
@@ -362,7 +345,6 @@ typedef union
 
 /*@} end of group CMSIS_CORE */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
@@ -373,8 +355,7 @@ typedef union
 /**
   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
   uint32_t       RESERVED0[31U];
   __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
@@ -389,7 +370,6 @@ typedef struct
 
 /*@} end of group CMSIS_NVIC */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCB     System Control Block (SCB)
@@ -400,8 +380,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control Block (SCB).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register */
   __IOM uint32_t ICSR;  /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
 #if (__VTOR_PRESENT == 1U)
@@ -506,7 +485,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
@@ -517,8 +495,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Timer (SysTick).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
   __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
@@ -569,8 +546,7 @@ typedef struct
 /**
   \brief  Structure type to access the Memory Protection Unit (MPU).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  TYPE; /*!< Offset: 0x000 (R/ )  MPU Type Register */
   __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W)  MPU Control Register */
   __IOM uint32_t RNR;  /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
@@ -646,7 +622,6 @@ typedef struct
 /*@} end of group CMSIS_MPU */
 #endif
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
@@ -656,7 +631,6 @@ typedef struct
  */
 /*@} end of group CMSIS_CoreDebug */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_bitfield     Core register bit field macros
@@ -682,7 +656,6 @@ typedef struct
 
 /*@} end of group CMSIS_core_bitfield */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_base     Core Definitions
@@ -707,8 +680,6 @@ typedef struct
 
 /*@} */
 
-
-
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
@@ -720,8 +691,6 @@ typedef struct
   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
-
-
 /* ##########################   NVIC functions  #################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -736,28 +705,19 @@ typedef struct
 #define _SHP_IDX(IRQn)   ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
 #define _IP_IDX(IRQn)    ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
 
-
 /**
   \brief   Enable External Interrupt
   \details Enables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Disable External Interrupt
   \details Disables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Pending Interrupt
@@ -766,33 +726,21 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not pending.
   \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
-{
-  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
 
 /**
   \brief   Set Pending Interrupt
   \details Sets the pending bit of an external interrupt.
   \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Clear Pending Interrupt
   \details Clears the pending bit of an external interrupt.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Set Interrupt Priority
@@ -801,21 +749,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
-{
+  if ((int32_t)(IRQn) < 0) {
-  if ((int32_t)(IRQn) < 0)
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  {
+  } else {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+    NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
   }
 }
 
-
 /**
   \brief   Get Interrupt Priority
   \details Reads the priority of an interrupt.
@@ -825,30 +766,23 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
   \return             Interrupt Priority.
                       Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
-{
 
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) < 0) {
-  {
     return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
+  } else {
-  else
-  {
     return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
-
 /**
   \brief   System Reset
   \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void) {
-{
   __DSB(); /* Ensure all outstanding memory accesses included
               buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
-                 SCB_AIRCR_SYSRESETREQ_Msk);
   __DSB(); /* Ensure completion of memory access */
 
   for (;;) /* wait until reset */
@@ -859,8 +793,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
-
-
 /* ##################################    SysTick function  ############################################ */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -882,19 +814,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
            must contain a vendor-specific implementation of this function.
  */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
-{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
     return (1UL); /* Reload value impossible */
   }
 
   SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
   NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
   SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
   return (0UL);                                                                                    /* Function successful */
 }
 
@@ -902,9 +830,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 /*@} end of CMSIS_Core_SysTickFunctions */
 
-
-
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm3.h

@@ -31,7 +31,6 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #if defined(__ICCARM__)
 #pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
      Function-like macros are used to allow more efficient code.
  */
 
-
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
@@ -73,12 +71,10 @@
 /*  CMSIS CM3 definitions */
 #define __CM3_CMSIS_VERSION_MAIN (0x04U)                                                       /*!< [31:16] CMSIS HAL main version */
 #define __CM3_CMSIS_VERSION_SUB  (0x1EU)                                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+#define __CM3_CMSIS_VERSION      ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-                                    __CM3_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
 
 #define __CORTEX_M (0x03U) /*!< Cortex-M Core */
 
-
 #if defined(__CC_ARM)
 #define __ASM           __asm    /*!< asm keyword for ARM Compiler */
 #define __INLINE        __inline /*!< inline keyword for ARM Compiler */
@@ -160,8 +156,8 @@
 
 #endif
 
-#include "core_cmInstr.h"                /* Core Instruction Access */
 #include "core_cmFunc.h"  /* Core Function Access */
+#include "core_cmInstr.h" /* Core Instruction Access */
 
 #ifdef __cplusplus
 }
@@ -224,8 +220,6 @@
 
 /*@} end of group Cortex_M3 */
 
-
-
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
@@ -251,10 +245,8 @@
 /**
   \brief  Union type to access the Application Program Status Register (APSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t _reserved0 : 27; /*!< bit:  0..26  Reserved */
     uint32_t Q : 1;           /*!< bit:     27  Saturation condition flag */
     uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
@@ -281,14 +273,11 @@ typedef union
 #define APSR_Q_Pos 27U                 /*!< APSR: Q Position */
 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
 
-
 /**
   \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
   } b;                        /*!< Structure used for bit  access */
@@ -299,14 +288,11 @@ typedef union
 #define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
     uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
@@ -345,14 +331,11 @@ typedef union
 #define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Control Registers (CONTROL).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
     uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
@@ -369,7 +352,6 @@ typedef union
 
 /*@} end of group CMSIS_CORE */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
@@ -380,8 +362,7 @@ typedef union
 /**
   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
   uint32_t       RESERVED0[24U];
   __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
@@ -403,7 +384,6 @@ typedef struct
 
 /*@} end of group CMSIS_NVIC */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCB     System Control Block (SCB)
@@ -414,8 +394,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control Block (SCB).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  CPUID;    /*!< Offset: 0x000 (R/ )  CPUID Base Register */
   __IOM uint32_t ICSR;     /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
   __IOM uint32_t VTOR;     /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
@@ -630,7 +609,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -641,8 +619,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
-typedef struct
+typedef struct {
-{
   uint32_t      RESERVED0[1U];
   __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
@@ -669,7 +646,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCnotSCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
@@ -680,8 +656,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Timer (SysTick).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
   __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
@@ -721,7 +696,6 @@ typedef struct
 
 /*@} end of group CMSIS_SysTick */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
@@ -732,10 +706,8 @@ typedef struct
 /**
   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
-typedef struct
+typedef struct {
-{
+  __OM union {
-  __OM  union
-  {
     __OM uint8_t  u8;  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
     __OM uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
     __OM uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
@@ -824,7 +796,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_ITM */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
@@ -835,8 +806,7 @@ typedef struct
 /**
   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register */
   __IOM uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register */
   __IOM uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register */
@@ -971,7 +941,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_DWT */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
@@ -982,8 +951,7 @@ typedef struct
 /**
   \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
   __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
   uint32_t       RESERVED0[2U];
@@ -1126,7 +1094,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_TPI */
 
-
 #if (__MPU_PRESENT == 1U)
 /**
   \ingroup  CMSIS_core_register
@@ -1138,8 +1105,7 @@ typedef struct
 /**
   \brief  Structure type to access the Memory Protection Unit (MPU).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  TYPE;    /*!< Offset: 0x000 (R/ )  MPU Type Register */
   __IOM uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register */
   __IOM uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
@@ -1221,7 +1187,6 @@ typedef struct
 /*@} end of group CMSIS_MPU */
 #endif
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
@@ -1232,8 +1197,7 @@ typedef struct
 /**
   \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
   __OM uint32_t  DCRSR; /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
   __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
@@ -1326,7 +1290,6 @@ typedef struct
 
 /*@} end of group CMSIS_CoreDebug */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_bitfield     Core register bit field macros
@@ -1352,7 +1315,6 @@ typedef struct
 
 /*@} end of group CMSIS_core_bitfield */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_base     Core Definitions
@@ -1386,8 +1348,6 @@ typedef struct
 
 /*@} */
 
-
-
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
@@ -1400,8 +1360,6 @@ typedef struct
   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
-
-
 /* ##########################   NVIC functions  #################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -1419,52 +1377,36 @@ typedef struct
            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
   \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
-{
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
 
   reg_value = SCB->AIRCR;                                                                             /* read old register configuration    */
   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));                         /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
+  reg_value  = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
   SCB->AIRCR = reg_value;
 }
 
-
 /**
   \brief   Get Priority Grouping
   \details Reads the priority grouping field from the NVIC Interrupt Controller.
   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
 
 /**
   \brief   Enable External Interrupt
   \details Enables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Disable External Interrupt
   \details Disables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Pending Interrupt
@@ -1473,33 +1415,23 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not pending.
   \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
-{
   return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
 
-
 /**
   \brief   Set Pending Interrupt
   \details Sets the pending bit of an external interrupt.
   \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Clear Pending Interrupt
   \details Clears the pending bit of an external interrupt.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Active Interrupt
@@ -1508,11 +1440,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not active.
   \return             1  Interrupt status is active.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
 
 /**
   \brief   Set Interrupt Priority
@@ -1521,19 +1449,14 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
-{
+  if ((int32_t)(IRQn) < 0) {
-  if ((int32_t)(IRQn) < 0)
-  {
     SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
+  } else {
-  else
-  {
     NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
   }
 }
 
-
 /**
   \brief   Get Interrupt Priority
   \details Reads the priority of an interrupt.
@@ -1543,20 +1466,15 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
   \return             Interrupt Priority.
                       Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
-{
 
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) < 0) {
-  {
     return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
+  } else {
-  else
-  {
     return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
-
 /**
   \brief   Encode Priority
   \details Encodes the priority for an interrupt with the given priority group,
@@ -1568,8 +1486,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
   \param [in]       SubPriority  Subpriority value (starting from 0).
   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
-{
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
@@ -1577,13 +1494,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-  return (
+  return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
 }
 
-
 /**
   \brief   Decode Priority
   \details Decodes an interrupt priority value with a given priority group to
@@ -1595,8 +1508,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
   \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
-{
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
@@ -1608,18 +1520,14 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
   *pSubPriority     = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
 }
 
-
 /**
   \brief   System Reset
   \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void) {
-{
   __DSB();                                                                                                                         /* Ensure all outstanding memory accesses included
                                                                                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
   __DSB();                                                                                                                         /* Ensure completion of memory access */
 
   for (;;) /* wait until reset */
@@ -1630,8 +1538,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
-
-
 /* ##################################    SysTick function  ############################################ */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -1653,19 +1559,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
            must contain a vendor-specific implementation of this function.
  */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
-{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
     return (1UL); /* Reload value impossible */
   }
 
   SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
   NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
   SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
   return (0UL);                                                                                    /* Function successful */
 }
 
@@ -1673,8 +1575,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 /*@} end of CMSIS_Core_SysTickFunctions */
 
-
-
 /* ##################################### Debug In/Output function ########################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -1686,7 +1586,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 extern volatile int32_t ITM_RxBuffer;  /*!< External variable to receive characters. */
 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
-
 /**
   \brief   ITM Send Character
   \details Transmits a character via the ITM channel 0, and
@@ -1695,13 +1594,11 @@ extern volatile int32_t ITM_RxBuffer;                    /*!< External variable
   \param [in]     ch  Character to transmit.
   \returns            Character to transmit.
  */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
-{
   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
       ((ITM->TER & 1UL) != 0UL))                  /* ITM Port #0 enabled */
   {
-    while (ITM->PORT[0U].u32 == 0UL)
+    while (ITM->PORT[0U].u32 == 0UL) {
-    {
       __NOP();
     }
     ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -1709,19 +1606,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
   return (ch);
 }
 
-
 /**
   \brief   ITM Receive Character
   \details Inputs a character via the external variable \ref ITM_RxBuffer.
   \return             Received character.
   \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
-{
   int32_t ch = -1; /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-  {
     ch           = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
   }
@@ -1729,31 +1623,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
   return (ch);
 }
 
-
 /**
   \brief   ITM Check Character
   \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
   \return          0  No character available.
   \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
+__STATIC_INLINE int32_t ITM_CheckChar(void) {
-{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-  {
     return (0); /* no character available */
-  }
+  } else {
-  else
-  {
     return (1); /*    character available */
   }
 }
 
 /*@} end of CMSIS_core_DebugFunctions */
 
-
-
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm4.h

@@ -31,7 +31,6 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #if defined(__ICCARM__)
 #pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
      Function-like macros are used to allow more efficient code.
  */
 
-
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
@@ -73,12 +71,10 @@
 /*  CMSIS CM4 definitions */
 #define __CM4_CMSIS_VERSION_MAIN (0x04U)                                                       /*!< [31:16] CMSIS HAL main version */
 #define __CM4_CMSIS_VERSION_SUB  (0x1EU)                                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+#define __CM4_CMSIS_VERSION      ((__CM4_CMSIS_VERSION_MAIN << 16U) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-                                    __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
 
 #define __CORTEX_M (0x04U) /*!< Cortex-M Core */
 
-
 #if defined(__CC_ARM)
 #define __ASM           __asm    /*!< asm keyword for ARM Compiler */
 #define __INLINE        __inline /*!< inline keyword for ARM Compiler */
@@ -207,8 +203,8 @@
 
 #endif
 
-#include "core_cmInstr.h"                /* Core Instruction Access */
 #include "core_cmFunc.h"  /* Core Function Access */
+#include "core_cmInstr.h" /* Core Instruction Access */
 #include "core_cmSimd.h"  /* Compiler specific SIMD Intrinsics */
 
 #ifdef __cplusplus
@@ -277,8 +273,6 @@
 
 /*@} end of group Cortex_M4 */
 
-
-
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
@@ -305,10 +299,8 @@
 /**
   \brief  Union type to access the Application Program Status Register (APSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t _reserved0 : 16; /*!< bit:  0..15  Reserved */
     uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags */
     uint32_t _reserved1 : 7;  /*!< bit: 20..26  Reserved */
@@ -340,14 +332,11 @@ typedef union
 #define APSR_GE_Pos 16U                    /*!< APSR: GE Position */
 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
 
-
 /**
   \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
   } b;                        /*!< Structure used for bit  access */
@@ -358,14 +347,11 @@ typedef union
 #define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;        /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 7; /*!< bit:  9..15  Reserved */
     uint32_t GE : 4;         /*!< bit: 16..19  Greater than or Equal flags */
@@ -409,14 +395,11 @@ typedef union
 #define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Control Registers (CONTROL).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
     uint32_t FPCA : 1;        /*!< bit:      2  FP extension active flag */
@@ -437,7 +420,6 @@ typedef union
 
 /*@} end of group CMSIS_CORE */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
@@ -448,8 +430,7 @@ typedef union
 /**
   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
   uint32_t       RESERVED0[24U];
   __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
@@ -471,7 +452,6 @@ typedef struct
 
 /*@} end of group CMSIS_NVIC */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCB     System Control Block (SCB)
@@ -482,8 +462,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control Block (SCB).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  CPUID;    /*!< Offset: 0x000 (R/ )  CPUID Base Register */
   __IOM uint32_t ICSR;     /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
   __IOM uint32_t VTOR;     /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
@@ -690,7 +669,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -701,8 +679,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
-typedef struct
+typedef struct {
-{
   uint32_t       RESERVED0[1U];
   __IM uint32_t  ICTR;  /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
   __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
@@ -730,7 +707,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCnotSCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
@@ -741,8 +717,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Timer (SysTick).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
   __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
@@ -782,7 +757,6 @@ typedef struct
 
 /*@} end of group CMSIS_SysTick */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
@@ -793,10 +767,8 @@ typedef struct
 /**
   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
-typedef struct
+typedef struct {
-{
+  __OM union {
-  __OM  union
-  {
     __OM uint8_t  u8;  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
     __OM uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
     __OM uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
@@ -885,7 +857,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_ITM */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
@@ -896,8 +867,7 @@ typedef struct
 /**
   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register */
   __IOM uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register */
   __IOM uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register */
@@ -1032,7 +1002,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_DWT */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
@@ -1043,8 +1012,7 @@ typedef struct
 /**
   \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
   __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
   uint32_t       RESERVED0[2U];
@@ -1187,7 +1155,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_TPI */
 
-
 #if (__MPU_PRESENT == 1U)
 /**
   \ingroup  CMSIS_core_register
@@ -1199,8 +1166,7 @@ typedef struct
 /**
   \brief  Structure type to access the Memory Protection Unit (MPU).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  TYPE;    /*!< Offset: 0x000 (R/ )  MPU Type Register */
   __IOM uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register */
   __IOM uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
@@ -1282,7 +1248,6 @@ typedef struct
 /*@} end of group CMSIS_MPU */
 #endif
 
-
 #if (__FPU_PRESENT == 1U)
 /**
   \ingroup  CMSIS_core_register
@@ -1294,8 +1259,7 @@ typedef struct
 /**
   \brief  Structure type to access the Floating Point Unit (FPU).
  */
-typedef struct
+typedef struct {
-{
   uint32_t       RESERVED0[1U];
   __IOM uint32_t FPCCR;  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
   __IOM uint32_t FPCAR;  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
@@ -1390,7 +1354,6 @@ typedef struct
 /*@} end of group CMSIS_FPU */
 #endif
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
@@ -1401,8 +1364,7 @@ typedef struct
 /**
   \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
   __OM uint32_t  DCRSR; /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
   __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
@@ -1495,7 +1457,6 @@ typedef struct
 
 /*@} end of group CMSIS_CoreDebug */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_bitfield     Core register bit field macros
@@ -1521,7 +1482,6 @@ typedef struct
 
 /*@} end of group CMSIS_core_bitfield */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_base     Core Definitions
@@ -1560,8 +1520,6 @@ typedef struct
 
 /*@} */
 
-
-
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
@@ -1574,8 +1532,6 @@ typedef struct
   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
-
-
 /* ##########################   NVIC functions  #################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -1593,52 +1549,36 @@ typedef struct
            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
   \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
-{
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
 
   reg_value = SCB->AIRCR;                                                                             /* read old register configuration    */
   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));                         /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
+  reg_value  = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
   SCB->AIRCR = reg_value;
 }
 
-
 /**
   \brief   Get Priority Grouping
   \details Reads the priority grouping field from the NVIC Interrupt Controller.
   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
 
 /**
   \brief   Enable External Interrupt
   \details Enables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Disable External Interrupt
   \details Disables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Pending Interrupt
@@ -1647,33 +1587,23 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not pending.
   \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
-{
   return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
 
-
 /**
   \brief   Set Pending Interrupt
   \details Sets the pending bit of an external interrupt.
   \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Clear Pending Interrupt
   \details Clears the pending bit of an external interrupt.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Active Interrupt
@@ -1682,11 +1612,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not active.
   \return             1  Interrupt status is active.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
 
 /**
   \brief   Set Interrupt Priority
@@ -1695,19 +1621,14 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
-{
+  if ((int32_t)(IRQn) < 0) {
-  if ((int32_t)(IRQn) < 0)
-  {
     SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
+  } else {
-  else
-  {
     NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
   }
 }
 
-
 /**
   \brief   Get Interrupt Priority
   \details Reads the priority of an interrupt.
@@ -1717,20 +1638,15 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
   \return             Interrupt Priority.
                       Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
-{
 
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) < 0) {
-  {
     return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
+  } else {
-  else
-  {
     return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
-
 /**
   \brief   Encode Priority
   \details Encodes the priority for an interrupt with the given priority group,
@@ -1742,8 +1658,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
   \param [in]       SubPriority  Subpriority value (starting from 0).
   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
-{
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
@@ -1751,13 +1666,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-  return (
+  return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
 }
 
-
 /**
   \brief   Decode Priority
   \details Decodes an interrupt priority value with a given priority group to
@@ -1769,8 +1680,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
   \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
-{
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
@@ -1782,18 +1692,14 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
   *pSubPriority     = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
 }
 
-
 /**
   \brief   System Reset
   \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void) {
-{
   __DSB();                                                                                                                         /* Ensure all outstanding memory accesses included
                                                                                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
   __DSB();                                                                                                                         /* Ensure completion of memory access */
 
   for (;;) /* wait until reset */
@@ -1804,8 +1710,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
-
-
 /* ##################################    SysTick function  ############################################ */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -1827,19 +1731,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
            must contain a vendor-specific implementation of this function.
  */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
-{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
     return (1UL); /* Reload value impossible */
   }
 
   SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
   NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
   SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
   return (0UL);                                                                                    /* Function successful */
 }
 
@@ -1847,8 +1747,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 /*@} end of CMSIS_Core_SysTickFunctions */
 
-
-
 /* ##################################### Debug In/Output function ########################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -1860,7 +1758,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 extern volatile int32_t ITM_RxBuffer;  /*!< External variable to receive characters. */
 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
-
 /**
   \brief   ITM Send Character
   \details Transmits a character via the ITM channel 0, and
@@ -1869,13 +1766,11 @@ extern volatile int32_t ITM_RxBuffer;                    /*!< External variable
   \param [in]     ch  Character to transmit.
   \returns            Character to transmit.
  */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
-{
   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
       ((ITM->TER & 1UL) != 0UL))                  /* ITM Port #0 enabled */
   {
-    while (ITM->PORT[0U].u32 == 0UL)
+    while (ITM->PORT[0U].u32 == 0UL) {
-    {
       __NOP();
     }
     ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -1883,19 +1778,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
   return (ch);
 }
 
-
 /**
   \brief   ITM Receive Character
   \details Inputs a character via the external variable \ref ITM_RxBuffer.
   \return             Received character.
   \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
-{
   int32_t ch = -1; /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-  {
     ch           = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
   }
@@ -1903,31 +1795,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
   return (ch);
 }
 
-
 /**
   \brief   ITM Check Character
   \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
   \return          0  No character available.
   \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
+__STATIC_INLINE int32_t ITM_CheckChar(void) {
-{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-  {
     return (0); /* no character available */
-  }
+  } else {
-  else
-  {
     return (1); /*    character available */
   }
 }
 
 /*@} end of CMSIS_core_DebugFunctions */
 
-
-
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm7.h

@@ -31,7 +31,6 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #if defined(__ICCARM__)
 #pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
      Function-like macros are used to allow more efficient code.
  */
 
-
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
@@ -73,12 +71,10 @@
 /*  CMSIS CM7 definitions */
 #define __CM7_CMSIS_VERSION_MAIN (0x04U)                                                       /*!< [31:16] CMSIS HAL main version */
 #define __CM7_CMSIS_VERSION_SUB  (0x1EU)                                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+#define __CM7_CMSIS_VERSION      ((__CM7_CMSIS_VERSION_MAIN << 16U) | __CM7_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-                                    __CM7_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
 
 #define __CORTEX_M (0x07U) /*!< Cortex-M Core */
 
-
 #if defined(__CC_ARM)
 #define __ASM           __asm    /*!< asm keyword for ARM Compiler */
 #define __INLINE        __inline /*!< inline keyword for ARM Compiler */
@@ -207,8 +203,8 @@
 
 #endif
 
-#include "core_cmInstr.h"                /* Core Instruction Access */
 #include "core_cmFunc.h"  /* Core Function Access */
+#include "core_cmInstr.h" /* Core Instruction Access */
 #include "core_cmSimd.h"  /* Compiler specific SIMD Intrinsics */
 
 #ifdef __cplusplus
@@ -292,8 +288,6 @@
 
 /*@} end of group Cortex_M7 */
 
-
-
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
@@ -320,10 +314,8 @@
 /**
   \brief  Union type to access the Application Program Status Register (APSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t _reserved0 : 16; /*!< bit:  0..15  Reserved */
     uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags */
     uint32_t _reserved1 : 7;  /*!< bit: 20..26  Reserved */
@@ -355,14 +347,11 @@ typedef union
 #define APSR_GE_Pos 16U                    /*!< APSR: GE Position */
 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
 
-
 /**
   \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
   } b;                        /*!< Structure used for bit  access */
@@ -373,14 +362,11 @@ typedef union
 #define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;        /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 7; /*!< bit:  9..15  Reserved */
     uint32_t GE : 4;         /*!< bit: 16..19  Greater than or Equal flags */
@@ -424,14 +410,11 @@ typedef union
 #define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Control Registers (CONTROL).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
     uint32_t FPCA : 1;        /*!< bit:      2  FP extension active flag */
@@ -452,7 +435,6 @@ typedef union
 
 /*@} end of group CMSIS_CORE */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
@@ -463,8 +445,7 @@ typedef union
 /**
   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
   uint32_t       RESERVED0[24U];
   __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
@@ -486,7 +467,6 @@ typedef struct
 
 /*@} end of group CMSIS_NVIC */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCB     System Control Block (SCB)
@@ -497,8 +477,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control Block (SCB).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  CPUID;       /*!< Offset: 0x000 (R/ )  CPUID Base Register */
   __IOM uint32_t ICSR;        /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
   __IOM uint32_t VTOR;        /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
@@ -892,7 +871,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -903,8 +881,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
-typedef struct
+typedef struct {
-{
   uint32_t       RESERVED0[1U];
   __IM uint32_t  ICTR;  /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
   __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
@@ -932,7 +909,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCnotSCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
@@ -943,8 +919,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Timer (SysTick).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
   __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
@@ -984,7 +959,6 @@ typedef struct
 
 /*@} end of group CMSIS_SysTick */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
@@ -995,10 +969,8 @@ typedef struct
 /**
   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
-typedef struct
+typedef struct {
-{
+  __OM union {
-  __OM  union
-  {
     __OM uint8_t  u8;  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
     __OM uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
     __OM uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
@@ -1087,7 +1059,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_ITM */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
@@ -1098,8 +1069,7 @@ typedef struct
 /**
   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register */
   __IOM uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register */
   __IOM uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register */
@@ -1237,7 +1207,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_DWT */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
@@ -1248,8 +1217,7 @@ typedef struct
 /**
   \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
   __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
   uint32_t       RESERVED0[2U];
@@ -1392,7 +1360,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_TPI */
 
-
 #if (__MPU_PRESENT == 1U)
 /**
   \ingroup  CMSIS_core_register
@@ -1404,8 +1371,7 @@ typedef struct
 /**
   \brief  Structure type to access the Memory Protection Unit (MPU).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  TYPE;    /*!< Offset: 0x000 (R/ )  MPU Type Register */
   __IOM uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register */
   __IOM uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
@@ -1487,7 +1453,6 @@ typedef struct
 /*@} end of group CMSIS_MPU */
 #endif
 
-
 #if (__FPU_PRESENT == 1U)
 /**
   \ingroup  CMSIS_core_register
@@ -1499,8 +1464,7 @@ typedef struct
 /**
   \brief  Structure type to access the Floating Point Unit (FPU).
  */
-typedef struct
+typedef struct {
-{
   uint32_t       RESERVED0[1U];
   __IOM uint32_t FPCCR;  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
   __IOM uint32_t FPCAR;  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
@@ -1598,7 +1562,6 @@ typedef struct
 /*@} end of group CMSIS_FPU */
 #endif
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
@@ -1609,8 +1572,7 @@ typedef struct
 /**
   \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
   __OM uint32_t  DCRSR; /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
   __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
@@ -1703,7 +1665,6 @@ typedef struct
 
 /*@} end of group CMSIS_CoreDebug */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_bitfield     Core register bit field macros
@@ -1729,7 +1690,6 @@ typedef struct
 
 /*@} end of group CMSIS_core_bitfield */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_base     Core Definitions
@@ -1768,8 +1728,6 @@ typedef struct
 
 /*@} */
 
-
-
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
@@ -1782,8 +1740,6 @@ typedef struct
   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
-
-
 /* ##########################   NVIC functions  #################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -1801,52 +1757,36 @@ typedef struct
            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
   \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
-{
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
 
   reg_value = SCB->AIRCR;                                                                             /* read old register configuration    */
   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));                         /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
+  reg_value  = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
   SCB->AIRCR = reg_value;
 }
 
-
 /**
   \brief   Get Priority Grouping
   \details Reads the priority grouping field from the NVIC Interrupt Controller.
   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
 
 /**
   \brief   Enable External Interrupt
   \details Enables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Disable External Interrupt
   \details Disables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Pending Interrupt
@@ -1855,33 +1795,23 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not pending.
   \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
-{
   return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
 
-
 /**
   \brief   Set Pending Interrupt
   \details Sets the pending bit of an external interrupt.
   \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Clear Pending Interrupt
   \details Clears the pending bit of an external interrupt.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Active Interrupt
@@ -1890,11 +1820,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not active.
   \return             1  Interrupt status is active.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
 
 /**
   \brief   Set Interrupt Priority
@@ -1903,19 +1829,14 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
-{
+  if ((int32_t)(IRQn) < 0) {
-  if ((int32_t)(IRQn) < 0)
-  {
     SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
+  } else {
-  else
-  {
     NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
   }
 }
 
-
 /**
   \brief   Get Interrupt Priority
   \details Reads the priority of an interrupt.
@@ -1925,20 +1846,15 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
   \return             Interrupt Priority.
                       Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
-{
 
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) < 0) {
-  {
     return (((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
+  } else {
-  else
-  {
     return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
-
 /**
   \brief   Encode Priority
   \details Encodes the priority for an interrupt with the given priority group,
@@ -1950,8 +1866,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
   \param [in]       SubPriority  Subpriority value (starting from 0).
   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
-{
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
@@ -1959,13 +1874,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-  return (
+  return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
 }
 
-
 /**
   \brief   Decode Priority
   \details Decodes an interrupt priority value with a given priority group to
@@ -1977,8 +1888,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
   \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
-{
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
@@ -1990,18 +1900,14 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
   *pSubPriority     = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
 }
 
-
 /**
   \brief   System Reset
   \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void) {
-{
   __DSB();                                                                                                                         /* Ensure all outstanding memory accesses included
                                                                                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
   __DSB();                                                                                                                         /* Ensure completion of memory access */
 
   for (;;) /* wait until reset */
@@ -2012,7 +1918,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
-
 /* ##########################  FPU functions  #################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -2029,30 +1934,21 @@ __STATIC_INLINE void NVIC_SystemReset(void)
    - \b  1: Single precision FPU
    - \b  2: Double + Single precision FPU
  */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+__STATIC_INLINE uint32_t SCB_GetFPUType(void) {
-{
   uint32_t mvfr0;
 
   mvfr0 = SCB->MVFR0;
-  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL)
+  if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
-  {
     return 2UL; /* Double + Single precision FPU */
-  }
+  } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
-  else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
-  {
     return 1UL; /* Single precision FPU */
-  }
+  } else {
-  else
-  {
     return 0UL; /* No FPU */
   }
 }
 
-
 /*@} end of CMSIS_Core_FpuFunctions */
 
-
-
 /* ##########################  Cache functions  #################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -2065,13 +1961,11 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
 #define CCSIDR_WAYS(x) (((x)&SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
 #define CCSIDR_SETS(x) (((x)&SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos)
 
-
 /**
   \brief   Enable I-Cache
   \details Turns on I-Cache
   */
-__STATIC_INLINE void SCB_EnableICache (void)
+__STATIC_INLINE void SCB_EnableICache(void) {
-{
 #if (__ICACHE_PRESENT == 1U)
   __DSB();
   __ISB();
@@ -2082,13 +1976,11 @@ __STATIC_INLINE void SCB_EnableICache (void)
 #endif
 }
 
-
 /**
   \brief   Disable I-Cache
   \details Turns off I-Cache
   */
-__STATIC_INLINE void SCB_DisableICache (void)
+__STATIC_INLINE void SCB_DisableICache(void) {
-{
 #if (__ICACHE_PRESENT == 1U)
   __DSB();
   __ISB();
@@ -2099,13 +1991,11 @@ __STATIC_INLINE void SCB_DisableICache (void)
 #endif
 }
 
-
 /**
   \brief   Invalidate I-Cache
   \details Invalidates I-Cache
   */
-__STATIC_INLINE void SCB_InvalidateICache (void)
+__STATIC_INLINE void SCB_InvalidateICache(void) {
-{
 #if (__ICACHE_PRESENT == 1U)
   __DSB();
   __ISB();
@@ -2115,13 +2005,11 @@ __STATIC_INLINE void SCB_InvalidateICache (void)
 #endif
 }
 
-
 /**
   \brief   Enable D-Cache
   \details Turns on D-Cache
   */
-__STATIC_INLINE void SCB_EnableDCache (void)
+__STATIC_INLINE void SCB_EnableDCache(void) {
-{
 #if (__DCACHE_PRESENT == 1U)
   uint32_t ccsidr;
   uint32_t sets;
@@ -2137,8 +2025,7 @@ __STATIC_INLINE void SCB_EnableDCache (void)
   do {
     ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
     do {
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+      SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk));
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
 #if defined(__CC_ARM)
       __schedule_barrier();
 #endif
@@ -2153,13 +2040,11 @@ __STATIC_INLINE void SCB_EnableDCache (void)
 #endif
 }
 
-
 /**
   \brief   Disable D-Cache
   \details Turns off D-Cache
   */
-__STATIC_INLINE void SCB_DisableDCache (void)
+__STATIC_INLINE void SCB_DisableDCache(void) {
-{
 #if (__DCACHE_PRESENT == 1U)
   uint32_t ccsidr;
   uint32_t sets;
@@ -2177,8 +2062,7 @@ __STATIC_INLINE void SCB_DisableDCache (void)
   do {
     ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
     do {
-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+      SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk));
-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
 #if defined(__CC_ARM)
       __schedule_barrier();
 #endif
@@ -2190,13 +2074,11 @@ __STATIC_INLINE void SCB_DisableDCache (void)
 #endif
 }
 
-
 /**
   \brief   Invalidate D-Cache
   \details Invalidates D-Cache
   */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
+__STATIC_INLINE void SCB_InvalidateDCache(void) {
-{
 #if (__DCACHE_PRESENT == 1U)
   uint32_t ccsidr;
   uint32_t sets;
@@ -2212,8 +2094,7 @@ __STATIC_INLINE void SCB_InvalidateDCache (void)
   do {
     ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
     do {
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+      SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk));
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
 #if defined(__CC_ARM)
       __schedule_barrier();
 #endif
@@ -2225,13 +2106,11 @@ __STATIC_INLINE void SCB_InvalidateDCache (void)
 #endif
 }
 
-
 /**
   \brief   Clean D-Cache
   \details Cleans D-Cache
   */
-__STATIC_INLINE void SCB_CleanDCache (void)
+__STATIC_INLINE void SCB_CleanDCache(void) {
-{
 #if (__DCACHE_PRESENT == 1U)
   uint32_t ccsidr;
   uint32_t sets;
@@ -2247,8 +2126,7 @@ __STATIC_INLINE void SCB_CleanDCache (void)
   do {
     ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
     do {
-        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+      SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk));
-                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
 #if defined(__CC_ARM)
       __schedule_barrier();
 #endif
@@ -2260,13 +2138,11 @@ __STATIC_INLINE void SCB_CleanDCache (void)
 #endif
 }
 
-
 /**
   \brief   Clean & Invalidate D-Cache
   \details Cleans and Invalidates D-Cache
   */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+__STATIC_INLINE void SCB_CleanInvalidateDCache(void) {
-{
 #if (__DCACHE_PRESENT == 1U)
   uint32_t ccsidr;
   uint32_t sets;
@@ -2282,8 +2158,7 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
   do {
     ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
     do {
-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+      SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk));
-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
 #if defined(__CC_ARM)
       __schedule_barrier();
 #endif
@@ -2295,15 +2170,13 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
 #endif
 }
 
-
 /**
   \brief   D-Cache Invalidate by address
   \details Invalidates D-Cache for the given address
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 */
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize) {
-{
 #if (__DCACHE_PRESENT == 1U)
   int32_t  op_size  = dsize;
   uint32_t op_addr  = (uint32_t)addr;
@@ -2322,15 +2195,13 @@ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize
 #endif
 }
 
-
 /**
   \brief   D-Cache Clean by address
   \details Cleans D-Cache for the given address
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 */
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+__STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize) {
-{
 #if (__DCACHE_PRESENT == 1)
   int32_t  op_size  = dsize;
   uint32_t op_addr  = (uint32_t)addr;
@@ -2349,15 +2220,13 @@ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
 #endif
 }
 
-
 /**
   \brief   D-Cache Clean and Invalidate by address
   \details Cleans and invalidates D_Cache for the given address
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 */
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize) {
-{
 #if (__DCACHE_PRESENT == 1U)
   int32_t  op_size  = dsize;
   uint32_t op_addr  = (uint32_t)addr;
@@ -2376,11 +2245,8 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t
 #endif
 }
 
-
 /*@} end of CMSIS_Core_CacheFunctions */
 
-
-
 /* ##################################    SysTick function  ############################################ */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -2402,19 +2268,15 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t
            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
            must contain a vendor-specific implementation of this function.
  */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
-{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
     return (1UL); /* Reload value impossible */
   }
 
   SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
   NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
   SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
   return (0UL);                                                                                    /* Function successful */
 }
 
@@ -2422,8 +2284,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 /*@} end of CMSIS_Core_SysTickFunctions */
 
-
-
 /* ##################################### Debug In/Output function ########################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -2435,7 +2295,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 extern volatile int32_t ITM_RxBuffer;  /*!< External variable to receive characters. */
 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
-
 /**
   \brief   ITM Send Character
   \details Transmits a character via the ITM channel 0, and
@@ -2444,13 +2303,11 @@ extern volatile int32_t ITM_RxBuffer;                    /*!< External variable
   \param [in]     ch  Character to transmit.
   \returns            Character to transmit.
  */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
-{
   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
       ((ITM->TER & 1UL) != 0UL))                  /* ITM Port #0 enabled */
   {
-    while (ITM->PORT[0U].u32 == 0UL)
+    while (ITM->PORT[0U].u32 == 0UL) {
-    {
       __NOP();
     }
     ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -2458,19 +2315,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
   return (ch);
 }
 
-
 /**
   \brief   ITM Receive Character
   \details Inputs a character via the external variable \ref ITM_RxBuffer.
   \return             Received character.
   \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
-{
   int32_t ch = -1; /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-  {
     ch           = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
   }
@@ -2478,31 +2332,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
   return (ch);
 }
 
-
 /**
   \brief   ITM Check Character
   \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
   \return          0  No character available.
   \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
+__STATIC_INLINE int32_t ITM_CheckChar(void) {
-{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-  {
     return (0); /* no character available */
-  }
+  } else {
-  else
-  {
     return (1); /*    character available */
   }
 }
 
 /*@} end of CMSIS_core_DebugFunctions */
 
-
-
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmFunc.h

@@ -31,7 +31,6 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #if defined(__ICCARM__)
 #pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -41,7 +40,6 @@
 #ifndef __CORE_CMFUNC_H
 #define __CORE_CMFUNC_H
 
-
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmInstr.h

@@ -31,7 +31,6 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #if defined(__ICCARM__)
 #pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -41,7 +40,6 @@
 #ifndef __CORE_CMINSTR_H
 #define __CORE_CMINSTR_H
 
-
 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmSimd.h

@@ -31,7 +31,6 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #if defined(__ICCARM__)
 #pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -45,7 +44,6 @@
 extern "C" {
 #endif
 
-
 /* ###################  Compiler specific Intrinsics  ########################### */
 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
   Access to dedicated SIMD instructions
@@ -88,7 +86,6 @@
 
 /*@} end of group CMSIS_SIMD_intrinsics */
 
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_sc000.h

@@ -31,7 +31,6 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #if defined(__ICCARM__)
 #pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
      Function-like macros are used to allow more efficient code.
  */
 
-
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
@@ -73,12 +71,10 @@
 /*  CMSIS SC000 definitions */
 #define __SC000_CMSIS_VERSION_MAIN (0x04U)                                                           /*!< [31:16] CMSIS HAL main version */
 #define __SC000_CMSIS_VERSION_SUB  (0x1EU)                                                           /*!< [15:0]  CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+#define __SC000_CMSIS_VERSION      ((__SC000_CMSIS_VERSION_MAIN << 16U) | __SC000_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-                                      __SC000_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */
 
 #define __CORTEX_SC (000U) /*!< Cortex secure core */
 
-
 #if defined(__CC_ARM)
 #define __ASM           __asm    /*!< asm keyword for ARM Compiler */
 #define __INLINE        __inline /*!< inline keyword for ARM Compiler */
@@ -160,8 +156,8 @@
 
 #endif
 
-#include "core_cmInstr.h"                /* Core Instruction Access */
 #include "core_cmFunc.h"  /* Core Function Access */
+#include "core_cmInstr.h" /* Core Instruction Access */
 
 #ifdef __cplusplus
 }
@@ -224,8 +220,6 @@
 
 /*@} end of group SC000 */
 
-
-
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
@@ -250,10 +244,8 @@
 /**
   \brief  Union type to access the Application Program Status Register (APSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t _reserved0 : 28; /*!< bit:  0..27  Reserved */
     uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
     uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
@@ -276,14 +268,11 @@ typedef union
 #define APSR_V_Pos 28U                 /*!< APSR: V Position */
 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
 
-
 /**
   \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
   } b;                        /*!< Structure used for bit  access */
@@ -294,14 +283,11 @@ typedef union
 #define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
     uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
@@ -333,14 +319,11 @@ typedef union
 #define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Control Registers (CONTROL).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t _reserved0 : 1;  /*!< bit:      0  Reserved */
     uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
     uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
@@ -354,7 +337,6 @@ typedef union
 
 /*@} end of group CMSIS_CORE */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
@@ -365,8 +347,7 @@ typedef union
 /**
   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
   uint32_t       RESERVED0[31U];
   __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
@@ -381,7 +362,6 @@ typedef struct
 
 /*@} end of group CMSIS_NVIC */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCB     System Control Block (SCB)
@@ -392,8 +372,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control Block (SCB).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register */
   __IOM uint32_t ICSR;  /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
   __IOM uint32_t VTOR;  /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
@@ -494,7 +473,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -505,8 +483,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
-typedef struct
+typedef struct {
-{
   uint32_t       RESERVED0[2U];
   __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 } SCnSCB_Type;
@@ -517,7 +494,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCnotSCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
@@ -528,8 +504,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Timer (SysTick).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
   __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
@@ -580,8 +555,7 @@ typedef struct
 /**
   \brief  Structure type to access the Memory Protection Unit (MPU).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  TYPE; /*!< Offset: 0x000 (R/ )  MPU Type Register */
   __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W)  MPU Control Register */
   __IOM uint32_t RNR;  /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
@@ -657,7 +631,6 @@ typedef struct
 /*@} end of group CMSIS_MPU */
 #endif
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
@@ -667,7 +640,6 @@ typedef struct
  */
 /*@} end of group CMSIS_CoreDebug */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_bitfield     Core register bit field macros
@@ -693,7 +665,6 @@ typedef struct
 
 /*@} end of group CMSIS_core_bitfield */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_base     Core Definitions
@@ -719,8 +690,6 @@ typedef struct
 
 /*@} */
 
-
-
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
@@ -732,8 +701,6 @@ typedef struct
   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
-
-
 /* ##########################   NVIC functions  #################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -748,28 +715,19 @@ typedef struct
 #define _SHP_IDX(IRQn)   ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
 #define _IP_IDX(IRQn)    ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
 
-
 /**
   \brief   Enable External Interrupt
   \details Enables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Disable External Interrupt
   \details Disables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Pending Interrupt
@@ -778,33 +736,21 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not pending.
   \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
-{
-  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
 
 /**
   \brief   Set Pending Interrupt
   \details Sets the pending bit of an external interrupt.
   \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Clear Pending Interrupt
   \details Clears the pending bit of an external interrupt.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Set Interrupt Priority
@@ -813,21 +759,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
-{
+  if ((int32_t)(IRQn) < 0) {
-  if ((int32_t)(IRQn) < 0)
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  {
+  } else {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+    NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
   }
 }
 
-
 /**
   \brief   Get Interrupt Priority
   \details Reads the priority of an interrupt.
@@ -837,30 +776,23 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
   \return             Interrupt Priority.
                       Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
-{
 
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) < 0) {
-  {
     return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
+  } else {
-  else
-  {
     return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
-
 /**
   \brief   System Reset
   \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void) {
-{
   __DSB(); /* Ensure all outstanding memory accesses included
               buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
-                 SCB_AIRCR_SYSRESETREQ_Msk);
   __DSB(); /* Ensure completion of memory access */
 
   for (;;) /* wait until reset */
@@ -871,8 +803,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
-
-
 /* ##################################    SysTick function  ############################################ */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -894,19 +824,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
            must contain a vendor-specific implementation of this function.
  */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
-{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
     return (1UL); /* Reload value impossible */
   }
 
   SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
   NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
   SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
   return (0UL);                                                                                    /* Function successful */
 }
 
@@ -914,9 +840,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 /*@} end of CMSIS_Core_SysTickFunctions */
 
-
-
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_sc300.h

@@ -31,7 +31,6 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #if defined(__ICCARM__)
 #pragma system_include /* treat file as system include file for MISRA check */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
      Function-like macros are used to allow more efficient code.
  */
 
-
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
@@ -73,12 +71,10 @@
 /*  CMSIS SC300 definitions */
 #define __SC300_CMSIS_VERSION_MAIN (0x04U)                                                           /*!< [31:16] CMSIS HAL main version */
 #define __SC300_CMSIS_VERSION_SUB  (0x1EU)                                                           /*!< [15:0]  CMSIS HAL sub version */
-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+#define __SC300_CMSIS_VERSION      ((__SC300_CMSIS_VERSION_MAIN << 16U) | __SC300_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-                                      __SC300_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */
 
 #define __CORTEX_SC (300U) /*!< Cortex secure core */
 
-
 #if defined(__CC_ARM)
 #define __ASM           __asm    /*!< asm keyword for ARM Compiler */
 #define __INLINE        __inline /*!< inline keyword for ARM Compiler */
@@ -160,8 +156,8 @@
 
 #endif
 
-#include "core_cmInstr.h"                /* Core Instruction Access */
 #include "core_cmFunc.h"  /* Core Function Access */
+#include "core_cmInstr.h" /* Core Instruction Access */
 
 #ifdef __cplusplus
 }
@@ -224,8 +220,6 @@
 
 /*@} end of group SC300 */
 
-
-
 /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
@@ -251,10 +245,8 @@
 /**
   \brief  Union type to access the Application Program Status Register (APSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t _reserved0 : 27; /*!< bit:  0..26  Reserved */
     uint32_t Q : 1;           /*!< bit:     27  Saturation condition flag */
     uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
@@ -281,14 +273,11 @@ typedef union
 #define APSR_Q_Pos 27U                 /*!< APSR: Q Position */
 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
 
-
 /**
   \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
   } b;                        /*!< Structure used for bit  access */
@@ -299,14 +288,11 @@ typedef union
 #define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
     uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
     uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
@@ -345,14 +331,11 @@ typedef union
 #define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
 
-
 /**
   \brief  Union type to access the Control Registers (CONTROL).
  */
-typedef union
+typedef union {
-{
+  struct {
-  struct
-  {
     uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
     uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
     uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
@@ -369,7 +352,6 @@ typedef union
 
 /*@} end of group CMSIS_CORE */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
@@ -380,8 +362,7 @@ typedef union
 /**
   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
   uint32_t       RESERVED0[24U];
   __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
@@ -403,7 +384,6 @@ typedef struct
 
 /*@} end of group CMSIS_NVIC */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCB     System Control Block (SCB)
@@ -414,8 +394,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control Block (SCB).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  CPUID;    /*!< Offset: 0x000 (R/ )  CPUID Base Register */
   __IOM uint32_t ICSR;     /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
   __IOM uint32_t VTOR;     /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
@@ -627,7 +606,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -638,8 +616,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
-typedef struct
+typedef struct {
-{
   uint32_t      RESERVED0[1U];
   __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
   uint32_t      RESERVED1[1U];
@@ -651,7 +628,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCnotSCB */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
@@ -662,8 +638,7 @@ typedef struct
 /**
   \brief  Structure type to access the System Timer (SysTick).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
   __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
   __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
@@ -703,7 +678,6 @@ typedef struct
 
 /*@} end of group CMSIS_SysTick */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
@@ -714,10 +688,8 @@ typedef struct
 /**
   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
-typedef struct
+typedef struct {
-{
+  __OM union {
-  __OM  union
-  {
     __OM uint8_t  u8;  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
     __OM uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
     __OM uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
@@ -806,7 +778,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_ITM */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
@@ -817,8 +788,7 @@ typedef struct
 /**
   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register */
   __IOM uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register */
   __IOM uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register */
@@ -953,7 +923,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_DWT */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
@@ -964,8 +933,7 @@ typedef struct
 /**
   \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
   __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
   uint32_t       RESERVED0[2U];
@@ -1108,7 +1076,6 @@ typedef struct
 
 /*@}*/ /* end of group CMSIS_TPI */
 
-
 #if (__MPU_PRESENT == 1U)
 /**
   \ingroup  CMSIS_core_register
@@ -1120,8 +1087,7 @@ typedef struct
 /**
   \brief  Structure type to access the Memory Protection Unit (MPU).
  */
-typedef struct
+typedef struct {
-{
   __IM uint32_t  TYPE;    /*!< Offset: 0x000 (R/ )  MPU Type Register */
   __IOM uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register */
   __IOM uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
@@ -1203,7 +1169,6 @@ typedef struct
 /*@} end of group CMSIS_MPU */
 #endif
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
@@ -1214,8 +1179,7 @@ typedef struct
 /**
   \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
-typedef struct
+typedef struct {
-{
   __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
   __OM uint32_t  DCRSR; /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
   __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
@@ -1308,7 +1272,6 @@ typedef struct
 
 /*@} end of group CMSIS_CoreDebug */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_bitfield     Core register bit field macros
@@ -1334,7 +1297,6 @@ typedef struct
 
 /*@} end of group CMSIS_core_bitfield */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_base     Core Definitions
@@ -1368,8 +1330,6 @@ typedef struct
 
 /*@} */
 
-
-
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
@@ -1382,8 +1342,6 @@ typedef struct
   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
-
-
 /* ##########################   NVIC functions  #################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -1401,52 +1359,36 @@ typedef struct
            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
   \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
-{
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
 
   reg_value = SCB->AIRCR;                                                                             /* read old register configuration    */
   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));                         /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
+  reg_value  = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
   SCB->AIRCR = reg_value;
 }
 
-
 /**
   \brief   Get Priority Grouping
   \details Reads the priority grouping field from the NVIC Interrupt Controller.
   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
 
 /**
   \brief   Enable External Interrupt
   \details Enables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Disable External Interrupt
   \details Disables a device-specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Pending Interrupt
@@ -1455,33 +1397,23 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not pending.
   \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
-{
   return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
 }
 
-
 /**
   \brief   Set Pending Interrupt
   \details Sets the pending bit of an external interrupt.
   \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Clear Pending Interrupt
   \details Clears the pending bit of an external interrupt.
   \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
-{
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
 
 /**
   \brief   Get Active Interrupt
@@ -1490,11 +1422,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
   \return             0  Interrupt status is not active.
   \return             1  Interrupt status is active.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
-{
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
 
 /**
   \brief   Set Interrupt Priority
@@ -1503,19 +1431,14 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
-{
+  if ((int32_t)(IRQn) < 0) {
-  if ((int32_t)(IRQn) < 0)
-  {
     SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
+  } else {
-  else
-  {
     NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
   }
 }
 
-
 /**
   \brief   Get Interrupt Priority
   \details Reads the priority of an interrupt.
@@ -1525,20 +1448,15 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
   \return             Interrupt Priority.
                       Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
-{
 
-  if ((int32_t)(IRQn) < 0)
+  if ((int32_t)(IRQn) < 0) {
-  {
     return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
+  } else {
-  else
-  {
     return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
-
 /**
   \brief   Encode Priority
   \details Encodes the priority for an interrupt with the given priority group,
@@ -1550,8 +1468,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
   \param [in]       SubPriority  Subpriority value (starting from 0).
   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
-{
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
@@ -1559,13 +1476,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-  return (
+  return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
 }
 
-
 /**
   \brief   Decode Priority
   \details Decodes an interrupt priority value with a given priority group to
@@ -1577,8 +1490,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
   \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
-{
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
@@ -1590,18 +1502,14 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
   *pSubPriority     = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
 }
 
-
 /**
   \brief   System Reset
   \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void) {
-{
   __DSB();                                                                                                                         /* Ensure all outstanding memory accesses included
                                                                                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
   __DSB();                                                                                                                         /* Ensure completion of memory access */
 
   for (;;) /* wait until reset */
@@ -1612,8 +1520,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
-
-
 /* ##################################    SysTick function  ############################################ */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -1635,19 +1541,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
            must contain a vendor-specific implementation of this function.
  */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
-{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
     return (1UL); /* Reload value impossible */
   }
 
   SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
   NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
   SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
   return (0UL);                                                                                    /* Function successful */
 }
 
@@ -1655,8 +1557,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 /*@} end of CMSIS_Core_SysTickFunctions */
 
-
-
 /* ##################################### Debug In/Output function ########################################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface
@@ -1668,7 +1568,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 extern volatile int32_t ITM_RxBuffer;  /*!< External variable to receive characters. */
 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
-
 /**
   \brief   ITM Send Character
   \details Transmits a character via the ITM channel 0, and
@@ -1677,13 +1576,11 @@ extern volatile int32_t ITM_RxBuffer;                    /*!< External variable
   \param [in]     ch  Character to transmit.
   \returns            Character to transmit.
  */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
-{
   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
       ((ITM->TER & 1UL) != 0UL))                  /* ITM Port #0 enabled */
   {
-    while (ITM->PORT[0U].u32 == 0UL)
+    while (ITM->PORT[0U].u32 == 0UL) {
-    {
       __NOP();
     }
     ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -1691,19 +1588,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
   return (ch);
 }
 
-
 /**
   \brief   ITM Receive Character
   \details Inputs a character via the external variable \ref ITM_RxBuffer.
   \return             Received character.
   \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
-{
   int32_t ch = -1; /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-  {
     ch           = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
   }
@@ -1711,31 +1605,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
   return (ch);
 }
 
-
 /**
   \brief   ITM Check Character
   \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
   \return          0  No character available.
   \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
+__STATIC_INLINE int32_t ITM_CheckChar(void) {
-{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-  {
     return (0); /* no character available */
-  }
+  } else {
-  else
-  {
     return (1); /*    character available */
   }
 }
 
 /*@} end of CMSIS_core_DebugFunctions */
 
-
-
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

@@ -275,8 +275,6 @@
 #define __HAL_REMAPDMA_CHANNEL_ENABLE  __HAL_DMA_REMAP_CHANNEL_ENABLE
 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
 
-  
-  
 /**
  * @}
  */
@@ -378,7 +376,6 @@
  * @}
  */
 
-
 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
  * @{
  */
@@ -470,12 +467,10 @@
 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
 #endif /* STM32H7  */
 
-  
 /**
  * @}
  */
 
-  
 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
  * @{
  */
@@ -720,7 +715,6 @@
  * @}
  */
 
-  
 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
  * @{
  */
@@ -741,7 +735,6 @@
  * @}
  */
 
-  
 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
  * @{
  */
@@ -882,7 +875,6 @@
  * @}
  */
 
-  
 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
  * @{
  */
@@ -996,8 +988,7 @@
  * @}
  */
 
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-    defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
  * @{
  */
@@ -1213,7 +1204,6 @@
  * @}
  */
 
-  
 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
  * @{
  */
@@ -1262,7 +1252,6 @@
  * @}
  */
 
-   
 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
  * @{
  */
@@ -1395,7 +1384,6 @@
 #define __HAL_FREEZE_CAN2_DBGMCU    __HAL_DBGMCU_FREEZE_CAN2
 #define __HAL_UNFREEZE_CAN2_DBGMCU  __HAL_DBGMCU_UNFREEZE_CAN2
 
-
 #define __HAL_FREEZE_TIM15_DBGMCU          __HAL_DBGMCU_FREEZE_TIM15
 #define __HAL_UNFREEZE_TIM15_DBGMCU        __HAL_DBGMCU_UNFREEZE_TIM15
 #define __HAL_FREEZE_TIM16_DBGMCU          __HAL_DBGMCU_FREEZE_TIM16
@@ -1434,158 +1422,176 @@
 #define COMP_LOCK  __HAL_COMP_LOCK
 
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)                                   \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+                                            : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)                                   \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+                                            : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)                                   \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+                                            : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__)                                   \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+                                            : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+  (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+  (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
 #endif
 #if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)                                         \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                                    \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+       ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()                                            \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                  : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)                                         \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                                     \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+       ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()                                            \
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                  : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)                                         \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                                     \
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+       ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()                                            \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                  : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__)                                         \
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                                      \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+       ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()                                            \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+                                                  : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)                                       \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                           \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+       ? __HAL_COMP_COMP1_EXTI_ENABLE_IT()                                            \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                  : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)                                       \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                            \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+       ? __HAL_COMP_COMP1_EXTI_DISABLE_IT()                                            \
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                  : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+  (((__FLAG__) == COMP_EXTI_LINE_COMP1)    \
+       ? __HAL_COMP_COMP1_EXTI_GET_FLAG()  \
+       : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
+  (((__FLAG__) == COMP_EXTI_LINE_COMP1)      \
+       ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()  \
+       : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
 #endif
 #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)                                                                                                                                           \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                                                                                                                                      \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+       ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()                                                                                                                                              \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2)                                                                                                                                                \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+             ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()                                                                                                                                        \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+             : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3)                                                                                                                                          \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+                   ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE()                                                                                                                                  \
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE()                                                                                       \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                              : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE()                                            \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                                                                         : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                                                                                                                    : __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)                                                                                                                                           \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                                                                                                                                       \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+       ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()                                                                                                                                              \
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2)                                                                                                                                                 \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+             ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()                                                                                                                                        \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+             : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3)                                                                                                                                           \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                   ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE()                                                                                                                                  \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE()                                                                                       \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                              : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE()                                            \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+                                                                                                         : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                                                                                                                    : __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)                                                                                                                                           \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                                                                                                                                       \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+       ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()                                                                                                                                              \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2)                                                                                                                                                 \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+             ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()                                                                                                                                        \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+             : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3)                                                                                                                                           \
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                   ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE()                                                                                                                                  \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE()                                                                                       \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                              : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE()                                            \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                                                                         : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                                                                                                                    : __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__)                                                                                                                                           \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                                                                                                                                        \
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+       ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()                                                                                                                                              \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2)                                                                                                                                                  \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+             ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()                                                                                                                                        \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+             : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3)                                                                                                                                            \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                   ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE()                                                                                                                                  \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE()                                                                                       \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+                                                              : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE()                                            \
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                                                                         : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                                                                                                                    : __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)                                                         \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                                             \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+       ? __HAL_COMP_COMP1_EXTI_ENABLE_IT()                                                              \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2)                                                       \
-                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+             ? __HAL_COMP_COMP2_EXTI_ENABLE_IT()                                                        \
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+             : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3)                                                 \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                   ? __HAL_COMP_COMP3_EXTI_ENABLE_IT()                                                  \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4)                                           \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                         ? __HAL_COMP_COMP4_EXTI_ENABLE_IT()                                            \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                         : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                                    : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)                                                         \
+  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)                                                              \
+       ? __HAL_COMP_COMP1_EXTI_DISABLE_IT()                                                              \
+       : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2)                                                        \
+             ? __HAL_COMP_COMP2_EXTI_DISABLE_IT()                                                        \
+             : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3)                                                  \
+                   ? __HAL_COMP_COMP3_EXTI_DISABLE_IT()                                                  \
+                   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4)                                            \
+                         ? __HAL_COMP_COMP4_EXTI_DISABLE_IT()                                            \
+                         : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \
+                                                                    : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)                                                         \
+  (((__FLAG__) == COMP_EXTI_LINE_COMP1)                                                            \
+       ? __HAL_COMP_COMP1_EXTI_GET_FLAG()                                                          \
+       : ((__FLAG__) == COMP_EXTI_LINE_COMP2)                                                      \
+             ? __HAL_COMP_COMP2_EXTI_GET_FLAG()                                                    \
+             : ((__FLAG__) == COMP_EXTI_LINE_COMP3)                                                \
+                   ? __HAL_COMP_COMP3_EXTI_GET_FLAG()                                              \
+                   : ((__FLAG__) == COMP_EXTI_LINE_COMP4)                                          \
+                         ? __HAL_COMP_COMP4_EXTI_GET_FLAG()                                        \
+                         : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \
+                                                                : ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)                                                         \
+  (((__FLAG__) == COMP_EXTI_LINE_COMP1)                                                              \
+       ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()                                                          \
+       : ((__FLAG__) == COMP_EXTI_LINE_COMP2)                                                        \
+             ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()                                                    \
+             : ((__FLAG__) == COMP_EXTI_LINE_COMP3)                                                  \
+                   ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG()                                              \
+                   : ((__FLAG__) == COMP_EXTI_LINE_COMP4)                                            \
+                         ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG()                                        \
+                         : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \
+                                                                : ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
 #endif
 #if defined(STM32F373xC) || defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG())
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
 #endif
 #else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG())
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
 #endif
 
 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
@@ -1616,9 +1622,7 @@
  * @{
  */
 
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
-                          ((WAVE) == DAC_WAVE_NOISE)|| \
-                          ((WAVE) == DAC_WAVE_TRIANGLE))
 
 /**
  * @}
@@ -1691,12 +1695,10 @@
 
 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
 
-
 /**
  * @}
  */
 
-
 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
  * @{
  */
@@ -1706,7 +1708,6 @@
  * @}
  */
 
-
 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
  * @{
  */
@@ -1719,7 +1720,6 @@
  * @}
  */
 
-  
 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
  * @{
  */
@@ -1741,7 +1741,6 @@
  * @}
  */
 
-
 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
  * @{
  */
@@ -1761,7 +1760,11 @@
 #define __HAL_PWR_INTERNALWAKEUP_ENABLE       HAL_PWREx_EnableInternalWakeUpLine
 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE  HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() \
+  do {                                          \
+    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();   \
+    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();  \
+  } while (0)
 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE            __HAL_PWR_PVD_EXTI_DISABLE_EVENT
 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE             __HAL_PWR_PVD_EXTI_ENABLE_EVENT
 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -1770,8 +1773,20 @@
 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_DISABLE() \
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+  do {                          \
+    HAL_PWREx_DisablePVM1();    \
+    HAL_PWREx_DisablePVM2();    \
+    HAL_PWREx_DisablePVM3();    \
+    HAL_PWREx_DisablePVM4();    \
+  } while (0)
+#define __HAL_PWR_PVM_ENABLE() \
+  do {                         \
+    HAL_PWREx_EnablePVM1();    \
+    HAL_PWREx_EnablePVM2();    \
+    HAL_PWREx_EnablePVM3();    \
+    HAL_PWREx_EnablePVM4();    \
+  } while (0)
 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE        HAL_PWREx_DisableSRAM2ContentRetention
 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE         HAL_PWREx_EnableSRAM2ContentRetention
 #define __HAL_PWR_VDDIO2_DISABLE                       HAL_PWREx_DisableVddIO2
@@ -1798,7 +1813,6 @@
  * @}
  */
 
-  
 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
  * @{
  */
@@ -2881,21 +2895,22 @@
 
 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
 #else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)                                      \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+                                                  : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)                                      \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+                                                  : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)                                      \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+                                                  : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)                                      \
-                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() \
-                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+                                                  : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) \
-                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT)   \
-                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+       ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()       \
+       : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
 #endif /* STM32F1 */
 
 #define IS_ALARM                              IS_RTC_ALARM
@@ -3055,7 +3070,6 @@
  * @}
  */
 
-
 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
  * @{
  */
@@ -3200,7 +3214,6 @@
  * @}
  */
 
-
 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
  * @{
  */
@@ -3216,4 +3229,3 @@
 #endif /* ___STM32_HAL_LEGACY */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h

@@ -62,13 +62,7 @@ extern "C" {
 /** @defgroup HAL_TICK_FREQ Tick Frequency
  * @{
  */
-typedef enum
+typedef enum { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef;
-{
-  HAL_TICK_FREQ_10HZ         = 100U,
-  HAL_TICK_FREQ_100HZ        = 10U,
-  HAL_TICK_FREQ_1KHZ         = 1U,
-  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
-} HAL_TickFreqTypeDef;
 /**
  * @}
  */
@@ -248,7 +242,6 @@ extern HAL_TickFreqTypeDef uwTickFreq;
 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
 #endif
 
-
 #if defined(DBGMCU_CR_DBG_TIM15_STOP)
 /**
  * @brief  TIM15 Peripherals Debug mode
@@ -280,9 +273,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
 /** @defgroup HAL_Private_Macros HAL Private Macros
  * @{
  */
-#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))
-                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
-                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
 /**
  * @}
  */

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h

@@ -64,11 +64,10 @@
  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
  *         ADC can be either disabled or enabled without conversion on going on regular group.
  */
-typedef struct
+typedef struct {
-{
   uint32_t DataAlign;          /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
-                                       or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
+                                    or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset
-                                       This parameter can be a value of @ref ADC_Data_align */
+                                  application): MSB on register bit 14 and LSB on register bit 3).          This parameter can be a value of @ref ADC_Data_align */
   uint32_t ScanConvMode;       /*!< Configures the sequencer of regular and injected groups.
                                     This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
                                     If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
@@ -86,7 +85,8 @@ typedef struct
   uint32_t NbrOfConversion;    /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
                                     To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
                                     This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
-  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+  uint32_t
+      DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
                                   Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
                                   Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
                                   This parameter can be set to ENABLE or DISABLE. */
@@ -104,18 +104,18 @@ typedef struct
  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
  *         ADC can be either disabled or enabled without conversion on going on regular group.
  */
-typedef struct 
+typedef struct {
-{
+  uint32_t
-  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
+      Channel;           /*!< Specifies the channel to configure into ADC regular group.
                               This parameter can be a value of @ref ADC_channels
                               Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
                               Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
-                                        Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
+                              Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection
-                                              It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
+                            trigger.      It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.      Refer to errata sheet of these devices for more details. */
-                                              Refer to errata sheet of these devices for more details. */
   uint32_t Rank;         /*!< Specifies the rank in the regular group sequencer
                               This parameter can be a value of @ref ADC_regular_rank
-                                        Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+                              Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or
+                            parameter number of conversions can be adjusted) */
   uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
                               Unit: ADC clock cycles
                               Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
@@ -132,8 +132,7 @@ typedef struct
  * @note   The setting of these parameters with function is conditioned to ADC state.
  *         ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
  */
-typedef struct
+typedef struct {
-{
   uint32_t WatchdogMode;   /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
                                 This parameter can be a value of @ref ADC_analog_watchdog_mode. */
   uint32_t Channel;        /*!< Selects which ADC channel to monitor by analog watchdog.
@@ -163,14 +162,16 @@ typedef struct
 #define HAL_ADC_STATE_ERROR_DMA      0x00000040U /*!< DMA error occurrence */
 
 /* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY          0x00000100U    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+#define HAL_ADC_STATE_REG_BUSY                                                                                                     \
+  0x00000100U                               /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, \
                                                 external trigger, low power auto power-on, multimode ADC master control) */
 #define HAL_ADC_STATE_REG_EOC   0x00000200U /*!< Conversion data available on group regular */
 #define HAL_ADC_STATE_REG_OVR   0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
 #define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised  */
 
 /* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY          0x00001000U    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+#define HAL_ADC_STATE_INJ_BUSY                                                                                                          \
+  0x00001000U                               /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, \
                                                 external trigger, low power auto power-on, multimode ADC master control) */
 #define HAL_ADC_STATE_INJ_EOC   0x00002000U /*!< Conversion data available on group injected */
 #define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
@@ -183,12 +184,10 @@ typedef struct
 /* States of ADC multi-mode */
 #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */
 
-
 /**
  * @brief  ADC handle Structure definition
  */
-typedef struct
+typedef struct {
-{
   ADC_TypeDef *Instance; /*!< Register base address */
 
   ADC_InitTypeDef Init; /*!< ADC required parameters */
@@ -205,8 +204,6 @@ typedef struct
  * @}
  */
 
-
-
 /* Exported constants --------------------------------------------------------*/
 
 /** @defgroup ADC_Exported_Constants ADC Exported Constants
@@ -217,7 +214,8 @@ typedef struct
  * @{
  */
 #define HAL_ADC_ERROR_NONE 0x00U /*!< No error                                              */
-#define HAL_ADC_ERROR_INTERNAL            0x01U   /*!< ADC IP internal error: if problem of clocking, 
+#define HAL_ADC_ERROR_INTERNAL                                                      \
+  0x01U                         /*!< ADC IP internal error: if problem of clocking, \
                                      enable/disable, erroneous state                       */
 #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error                                         */
 #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error                                    */
@@ -226,7 +224,6 @@ typedef struct
  * @}
  */
 
-
 /** @defgroup ADC_Data_align ADC data alignment
  * @{
  */
@@ -381,7 +378,6 @@ typedef struct
  * @}
  */
 
-
 /**
  * @}
  */
@@ -414,28 +410,19 @@ typedef struct
  * @{
  */
 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
-     (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 |     \
+  (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
-      ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 |     \
-      ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
-     (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
+  (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2)
-      ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
 
 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
-     (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 |     \
+  (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
-      ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 |     \
-      ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
-     (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
+  (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1)
-      ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
 
 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
-     (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 |     \
+  (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
-      ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 |     \
-      ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
-     (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
+  (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0)
-      ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
 
 #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS    0x00000000U
 #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
@@ -465,7 +452,6 @@ typedef struct
  * @}
  */
 
-
 /* Exported macro ------------------------------------------------------------*/
 
 /** @defgroup ADC_Exported_Macros ADC Exported Macros
@@ -483,16 +469,14 @@ typedef struct
  * @param __HANDLE__: ADC handle
  * @retval None
  */
-#define __HAL_ADC_ENABLE(__HANDLE__)                                           \
+#define __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
-  (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
 
 /**
  * @brief Disable the ADC peripheral
  * @param __HANDLE__: ADC handle
  * @retval None
  */
-#define __HAL_ADC_DISABLE(__HANDLE__)                                          \
+#define __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
-  (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
 
 /** @brief Enable the ADC end of conversion interrupt.
  * @param __HANDLE__: ADC handle
@@ -503,8 +487,7 @@ typedef struct
  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
  * @retval None
  */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-  (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
 
 /** @brief Disable the ADC end of conversion interrupt.
  * @param __HANDLE__: ADC handle
@@ -515,8 +498,7 @@ typedef struct
  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
  * @retval None
  */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-  (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
 
 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
  * @param __HANDLE__: ADC handle
@@ -527,8 +509,7 @@ typedef struct
  *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
  * @retval None
  */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
-  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /** @brief Get the selected ADC's flag status.
  * @param __HANDLE__: ADC handle
@@ -541,8 +522,7 @@ typedef struct
  *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
  * @retval None
  */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-  ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief Clear the ADC's pending flags
  * @param __HANDLE__: ADC handle
@@ -555,15 +535,13 @@ typedef struct
  *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
  * @retval None
  */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
-  (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
 
 /** @brief  Reset ADC handle state
  * @param  __HANDLE__: ADC handle
  * @retval None
  */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
 
 /**
  * @}
@@ -582,9 +560,7 @@ typedef struct
  * @param __HANDLE__: ADC handle
  * @retval SET (ADC enabled) or RESET (ADC disabled)
  */
-#define ADC_IS_ENABLE(__HANDLE__)                                              \
+#define ADC_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON)) ? SET : RESET)
-  ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON )           \
-   ) ? SET : RESET)
 
 /**
  * @brief Test if conversion trigger of regular group is software start
@@ -592,8 +568,7 @@ typedef struct
  * @param __HANDLE__: ADC handle
  * @retval SET (software start) or RESET (external trigger)
  */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
-  (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
 
 /**
  * @brief Test if conversion trigger of injected group is software start
@@ -601,8 +576,7 @@ typedef struct
  * @param __HANDLE__: ADC handle
  * @retval SET (software start) or RESET (external trigger)
  */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
-  (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
 
 /**
  * @brief Simultaneously clears and sets specific bits of the handle State
@@ -618,16 +592,14 @@ typedef struct
  * @param __HANDLE__: ADC handle
  * @retval None
  */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
 
 /**
  * @brief Set ADC number of conversions into regular channel sequence length.
  * @param _NbrOfConversion_: Regular channel sequence length
  * @retval None
  */
-#define ADC_SQR1_L_SHIFT(_NbrOfConversion_)                                    \
+#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
-  (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
 
 /**
  * @brief Set the ADC's sample time for channel numbers between 10 and 18.
@@ -635,8 +607,7 @@ typedef struct
  * @param _CHANNELNB_: Channel number.
  * @retval None
  */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_)                                   \
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_)-10)))
-  ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
 
 /**
  * @brief Set the ADC's sample time for channel numbers between 0 and 9.
@@ -644,8 +615,7 @@ typedef struct
  * @param _CHANNELNB_: Channel number.
  * @retval None
  */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_)                                   \
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
-  ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
 
 /**
  * @brief Set the selected regular channel rank for rank between 1 and 6.
@@ -653,8 +623,7 @@ typedef struct
  * @param _RANKNB_: Rank number.
  * @retval None
  */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_)                                     \
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_)-1)))
-  ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
 
 /**
  * @brief Set the selected regular channel rank for rank between 7 and 12.
@@ -662,8 +631,7 @@ typedef struct
  * @param _RANKNB_: Rank number.
  * @retval None
  */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_)                                     \
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_)-7)))
-  ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
 
 /**
  * @brief Set the selected regular channel rank for rank between 13 and 16.
@@ -671,16 +639,14 @@ typedef struct
  * @param _RANKNB_: Rank number.
  * @retval None
  */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_)                                     \
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_)-13)))
-  ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
 
 /**
  * @brief Set the injected sequence length.
  * @param _JSQR_JL_: Sequence length.
  * @retval None
  */
-#define ADC_JSQR_JL_SHIFT(_JSQR_JL_)                                           \
+#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_)-1) << ADC_JSQR_JL_Pos)
-  (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
 
 /**
  * @brief Set the selected injected channel rank
@@ -692,24 +658,21 @@ typedef struct
  * @param _JSQR_JL_: Sequence length.
  * @retval None
  */
-#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_)                       \
+#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
-  ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
 
 /**
  * @brief Enable ADC continuous conversion mode.
  * @param _CONTINUOUS_MODE_: Continuous mode.
  * @retval None
  */
-#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_)                                  \
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
-  ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
 
 /**
  * @brief Configures the number of discontinuous conversions for the regular group channels.
  * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
  * @retval None
  */
-#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_)                    \
+#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_)-1) << ADC_CR1_DISCNUM_Pos)
-  (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
 
 /**
  * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
@@ -718,10 +681,7 @@ typedef struct
  */
 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter   */
 /*       is equivalent to ADC_SCAN_ENABLE.                                    */
-#define ADC_CR1_SCAN_SET(_SCAN_MODE_)                                          \
+#define ADC_CR1_SCAN_SET(_SCAN_MODE_) ((((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)) ? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE))
-  (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)           \
-   )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE)                                   \
-  )
 
 /**
  * @brief Get the maximum ADC conversion cycles on all channels.
@@ -736,89 +696,47 @@ typedef struct
  * @retval ADC conversion cycles on all channels
  */
 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                                                                                                            \
-    (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&                     \
+  (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET))             \
-       (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ?                     \
+       ?                                                                                                                                                                                \
                                                                                                                                                                                         \
-          (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
+       (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET))        \
-             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ?               \
+            ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5                                                                                                                             \
-               ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5)   \
+            : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5)                                                                                                                           \
-          :                                                                                                      \
+       : ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET))     \
-          ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
+           || ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) \
-             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) ||               \
+              ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5                                                                                                                          \
-            ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET)  &&               \
+              : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5))
-             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ?               \
-               ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
-     )
 
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT))
-                                  ((ALIGN) == ADC_DATAALIGN_LEFT)    )
 
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || ((SCAN_MODE) == ADC_SCAN_ENABLE))
-                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)    )
 
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)  || \
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING))
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  )
 
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
+#define IS_ADC_CHANNEL(CHANNEL)                                                                                                                                                                      \
-                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
+  (((CHANNEL) == ADC_CHANNEL_0) || ((CHANNEL) == ADC_CHANNEL_1) || ((CHANNEL) == ADC_CHANNEL_2) || ((CHANNEL) == ADC_CHANNEL_3) || ((CHANNEL) == ADC_CHANNEL_4) || ((CHANNEL) == ADC_CHANNEL_5)      \
-                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
+   || ((CHANNEL) == ADC_CHANNEL_6) || ((CHANNEL) == ADC_CHANNEL_7) || ((CHANNEL) == ADC_CHANNEL_8) || ((CHANNEL) == ADC_CHANNEL_9) || ((CHANNEL) == ADC_CHANNEL_10) || ((CHANNEL) == ADC_CHANNEL_11) \
-                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
+   || ((CHANNEL) == ADC_CHANNEL_12) || ((CHANNEL) == ADC_CHANNEL_13) || ((CHANNEL) == ADC_CHANNEL_14) || ((CHANNEL) == ADC_CHANNEL_15) || ((CHANNEL) == ADC_CHANNEL_16)                              \
-                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
+   || ((CHANNEL) == ADC_CHANNEL_17))
-                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_16)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_17)            )
 
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
+#define IS_ADC_SAMPLE_TIME(TIME)                                                                                                                                 \
-                                  ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
+  (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || ((TIME) == ADC_SAMPLETIME_28CYCLES_5) \
-                                  ((TIME) == ADC_SAMPLETIME_13CYCLES_5)  || \
+   || ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
-                                  ((TIME) == ADC_SAMPLETIME_28CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_41CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_55CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_71CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_239CYCLES_5)   )
 
-#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
+#define IS_ADC_REGULAR_RANK(CHANNEL)                                                                                                                                                             \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
+  (((CHANNEL) == ADC_REGULAR_RANK_1) || ((CHANNEL) == ADC_REGULAR_RANK_2) || ((CHANNEL) == ADC_REGULAR_RANK_3) || ((CHANNEL) == ADC_REGULAR_RANK_4) || ((CHANNEL) == ADC_REGULAR_RANK_5)         \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
+   || ((CHANNEL) == ADC_REGULAR_RANK_6) || ((CHANNEL) == ADC_REGULAR_RANK_7) || ((CHANNEL) == ADC_REGULAR_RANK_8) || ((CHANNEL) == ADC_REGULAR_RANK_9) || ((CHANNEL) == ADC_REGULAR_RANK_10)     \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
+   || ((CHANNEL) == ADC_REGULAR_RANK_11) || ((CHANNEL) == ADC_REGULAR_RANK_12) || ((CHANNEL) == ADC_REGULAR_RANK_13) || ((CHANNEL) == ADC_REGULAR_RANK_14) || ((CHANNEL) == ADC_REGULAR_RANK_15) \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
+   || ((CHANNEL) == ADC_REGULAR_RANK_16))
-                                      ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_10) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_11) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_12) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_13) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_14) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_15) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_16)   )
 
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)                                                                                                                                                        \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
+  (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
+   || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC))
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
 
-#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP)         || \
+#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || ((CONVERSION) == ADC_INJECTED_GROUP) || ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP))
-                                             ((CONVERSION) == ADC_INJECTED_GROUP)        || \
-                                             ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)  )
 
 #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
 
-
 /** @defgroup ADC_range_verification ADC range verification
  * For a unique ADC resolution: 12 bits
  * @{
@@ -860,7 +778,6 @@ typedef struct
  * @{
  */
 
-
 /* Initialization and de-initialization functions  **********************************/
 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
@@ -876,7 +793,6 @@ void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
  * @{
  */
 
-
 /* Blocking mode: Polling */
 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
@@ -904,7 +820,6 @@ void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
  * @}
  */
 
-
 /* Peripheral Control functions ***********************************************/
 /** @addtogroup ADC_Exported_Functions_Group3
  * @{
@@ -915,7 +830,6 @@ HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_Ana
  * @}
  */
 
-
 /* Peripheral State functions *************************************************/
 /** @addtogroup ADC_Exported_Functions_Group4
  * @{
@@ -926,12 +840,10 @@ uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
  * @}
  */
 
-
 /**
  * @}
  */
 
-
 /* Internal HAL driver functions **********************************************/
 /** @addtogroup ADC_Private_Functions
  * @{
@@ -946,7 +858,6 @@ void              ADC_DMAError(DMA_HandleTypeDef *hdma);
  * @}
  */
 
-
 /**
  * @}
  */
@@ -959,7 +870,6 @@ void              ADC_DMAError(DMA_HandleTypeDef *hdma);
 }
 #endif
 
-
 #endif /* __STM32F1xx_HAL_ADC_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h

@@ -68,18 +68,18 @@
  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
  *          - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
  */
-typedef struct 
+typedef struct {
-{
   uint32_t InjectedChannel;         /*!< Selection of ADC channel to configure
                                          This parameter can be a value of @ref ADC_channels
                                          Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
                                          Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
-                                               Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
+                                         Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with
-                                                     It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
+                                       injection         trigger.              It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.              Refer to
-                                                     Refer to errata sheet of these devices for more details. */
+                                       errata         sheet of these devices for more details. */
   uint32_t InjectedRank;            /*!< Rank in the injected group sequencer
                                          This parameter must be a value of @ref ADCEx_injected_rank
-                                               Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+                                         Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel
+                                       setting (or parameter number of conversions can be adjusted) */
   uint32_t InjectedSamplingTime;    /*!< Sampling time value to be set for the selected channel.
                                          Unit: ADC clock cycles
                                          Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
@@ -98,13 +98,12 @@ typedef struct
                                          This parameter must be a number between Min_Data = 1 and Max_Data = 4.
                                          Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+  uint32_t
-                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+      InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive
-                                               Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+                                        parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous
-                                               This parameter can be set to ENABLE or DISABLE.
+                                        mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE
-                                               Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+                                        or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                        Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
   uint32_t AutoInjectedConv;         /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
                                           This parameter can be set to ENABLE or DISABLE.
                                           Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
@@ -118,8 +117,8 @@ typedef struct
                                           If set to external trigger source, triggering is on event rising edge.
                                           This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
                                           Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
-                                                     If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
+                                                If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                        the fly)    Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                    configure a channel on injected group can impact the configuration of other channels previously set. */
 } ADC_InjectionConfTypeDef;
 
@@ -129,18 +128,18 @@ typedef struct
  * @note   The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
  *         State of ADCs of the common group must be: disabled.
  */
-typedef struct
+typedef struct {
-{
   uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
                       This parameter can be a value of @ref ADCEx_Common_mode
-                                   Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change.
+                      Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any
-                                   Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2.
+                    configuration change. Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1
-                                   Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode.
+                    and ADC2. Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC
-                                   Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters).
+                    clock cycles for slow interleaved mode. Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration
-                                         The equivalences are:
+                    structure can have additional parameters). The equivalences are:
-                                           - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
+                              - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several
-                                           - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
+                    ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
-
+                              - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32
+                    devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
 
 } ADC_MultiModeTypeDef;
 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
@@ -149,7 +148,6 @@ typedef struct
  * @}
  */
 
-
 /* Exported constants --------------------------------------------------------*/
 
 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
@@ -272,12 +270,20 @@ typedef struct
 #define ADC_MODE_INDEPENDENT               0x00000000U                     /*!< ADC dual mode disabled (ADC independent mode) */
 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG   ((uint32_t)(ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
-#define ADC_DUALMODE_INJECSIMULT_INTERLFAST   ((uint32_t)(                                        ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INJECSIMULT_INTERLFAST                                                                                                                                                          \
-#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW   ((uint32_t)(                    ADC_CR1_DUALMOD_2                                        )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+  ((uint32_t)(ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling \
+                                                         phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW                                                                                                                                                           \
+  ((uint32_t)(ADC_CR1_DUALMOD_2)) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock \
+                                     cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
 #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
 #define ADC_DUALMODE_REGSIMULT   ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
-#define ADC_DUALMODE_INTERLFAST               ((uint32_t)(                    ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INTERLFAST                                                                                                                                                                      \
-#define ADC_DUALMODE_INTERLSLOW               ((uint32_t)(ADC_CR1_DUALMOD_3                                                            )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+  ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles \
+                                                                             (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
+#define ADC_DUALMODE_INTERLSLOW                                                                                                                                                        \
+  ((uint32_t)(ADC_CR1_DUALMOD_3)) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter \
+                                     "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
 #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
 /**
  * @}
@@ -288,7 +294,6 @@ typedef struct
  * @}
  */
 
-
 /* Private constants ---------------------------------------------------------*/
 
 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
@@ -372,7 +377,6 @@ typedef struct
  * @}
  */
 
-
 /* Exported macro ------------------------------------------------------------*/
 
 /* Private macro -------------------------------------------------------------*/
@@ -383,7 +387,6 @@ typedef struct
 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
 /* code of final user.                                                        */
 
-    
 /**
  * @brief For devices with 3 ADCs: Defines the external trigger source
  *        for regular group according to ADC into common group ADC1&ADC2 or
@@ -396,20 +399,9 @@ typedef struct
  */
 #if defined(STM32F103xE) || defined(STM32F103xG)
 #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
- (( (((__HANDLE__)->Instance) == ADC3)                                         \
+  (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO) ? (ADC3_EXTERNALTRIG_T8_TRGO) : (__EXT_TRIG_CONV__)) : (__EXT_TRIG_CONV__))
-  )?                                                                           \
-   ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO                     \
-     )?                                                                        \
-      (ADC3_EXTERNALTRIG_T8_TRGO)                                              \
-      :                                                                        \
-      (__EXT_TRIG_CONV__)                                                      \
-   )                                                                           \
-   :                                                                           \
-   (__EXT_TRIG_CONV__)                                                         \
- )
 #else
-#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__)                         \
+#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) (__EXT_TRIG_CONV__)
-  (__EXT_TRIG_CONV__)
 #endif /* STM32F103xE || STM32F103xG */
 
 /**
@@ -424,39 +416,20 @@ typedef struct
  */
 #if defined(STM32F103xE) || defined(STM32F103xG)
 #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
- (( (((__HANDLE__)->Instance) == ADC3)                                         \
+  (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) ? (ADC3_EXTERNALTRIGINJEC_T8_CC4) : (__EXT_TRIG_INJECTCONV__)) : (__EXT_TRIG_INJECTCONV__))
-  )?                                                                           \
-   ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4           \
-     )?                                                                        \
-      (ADC3_EXTERNALTRIGINJEC_T8_CC4)                                          \
-      :                                                                        \
-      (__EXT_TRIG_INJECTCONV__)                                                \
-   )                                                                           \
-   :                                                                           \
-   (__EXT_TRIG_INJECTCONV__)                                                   \
- )
 #else
-#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__)                  \
+#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) (__EXT_TRIG_INJECTCONV__)
-   (__EXT_TRIG_INJECTCONV__)
 #endif /* STM32F103xE || STM32F103xG */
 
-
 /**
  * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
  * @param __HANDLE__: ADC handle
  * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
  */
 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
-#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__)                                    \
+#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_DUALMOD) : (RESET))
- (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)   \
-  )?                                                                           \
-   (ADC1->CR1 & ADC_CR1_DUALMOD)                                               \
-   :                                                                           \
-   (RESET)                                                                     \
- )
 #else
-#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__)                                    \
+#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (RESET)
-  (RESET)
 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
 
 /**
@@ -465,16 +438,9 @@ typedef struct
  * @retval None
  */
 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
-#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (((((__HANDLE__)->Instance) == ADC2)) ? ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) : (!RESET))
-  (( (((__HANDLE__)->Instance) == ADC2)                                        \
-   )?                                                                          \
-    ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET)                                   \
-    :                                                                          \
-    (!RESET)                                                                   \
-  )
 #else
-#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (!RESET)
-  (!RESET)
 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
 
 /**
@@ -483,16 +449,9 @@ typedef struct
  * @retval None
  */
 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
-#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)                                \
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_JAUTO) : (RESET))
-  (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)  \
-   )?                                                                          \
-    (ADC1->CR1 & ADC_CR1_JAUTO)                                                \
-    :                                                                          \
-    (RESET)                                                                    \
-  )
 #else
-#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)                                \
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (RESET)
-  (RESET)
 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
 
 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
@@ -502,8 +461,7 @@ typedef struct
  * @param __HANDLE_OTHER_ADC__: other ADC handle
  * @retval None
  */
-#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__)                 \
+#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
-  ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
 
 /**
  * @brief Set handle of the ADC slave associated to the ADC master
@@ -513,18 +471,13 @@ typedef struct
  * @param __HANDLE_SLAVE__: ADC slave handle
  * @retval None
  */
-#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)                   \
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ((__HANDLE_SLAVE__)->Instance = ADC2)
-  ((__HANDLE_SLAVE__)->Instance = ADC2)
 
 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
 
-#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
+#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || ((CHANNEL) == ADC_INJECTED_RANK_2) || ((CHANNEL) == ADC_INJECTED_RANK_3) || ((CHANNEL) == ADC_INJECTED_RANK_4))
-                                       ((CHANNEL) == ADC_INJECTED_RANK_2) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_3) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_4))
 
-#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)  || \
+#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
-                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
 
 /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
  * @{
@@ -534,121 +487,69 @@ typedef struct
  * @}
  */
 
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
+    || defined(STM32F105xC) || defined(STM32F107xC)
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
-                                 ((REGTRIG) == ADC_SOFTWARE_START))
 #endif
 #if defined(STM32F101xE)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO)   || \
-                                 ((REGTRIG) == ADC_SOFTWARE_START))
 #endif
 #if defined(STM32F101xG)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
-                                 ((REGTRIG) == ADC_SOFTWARE_START))
 #endif
 #if defined(STM32F103xE) || defined(STM32F103xG)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
+#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                              \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
+  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)     \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)   \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)    || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO)   || \
-                                 ((REGTRIG) == ADC_SOFTWARE_START))
 #endif
 
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
+    || defined(STM32F105xC) || defined(STM32F107xC)
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
-                                      ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
 #endif
 #if defined(STM32F101xE)
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
-                                      ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
 #endif
 #if defined(STM32F101xG)
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
-                                      ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
 #endif
 #if defined(STM32F103xE) || defined(STM32F103xG)
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
+#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
+  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)   \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)   || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)   \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
-                                      ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
 #endif
 
 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT)                || \
+#define IS_ADC_MODE(MODE)                                                                                                                                                                \
-                           ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)  || \
+  (((MODE) == ADC_MODE_INDEPENDENT) || ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) \
-                           ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)    || \
+   || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || ((MODE) == ADC_DUALMODE_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT) || ((MODE) == ADC_DUALMODE_INTERLFAST)               \
-                           ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
+   || ((MODE) == ADC_DUALMODE_INTERLSLOW) || ((MODE) == ADC_DUALMODE_ALTERTRIG))
-                           ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
-                           ((MODE) == ADC_DUALMODE_INJECSIMULT)            || \
-                           ((MODE) == ADC_DUALMODE_REGSIMULT)              || \
-                           ((MODE) == ADC_DUALMODE_INTERLFAST)             || \
-                           ((MODE) == ADC_DUALMODE_INTERLSLOW)             || \
-                           ((MODE) == ADC_DUALMODE_ALTERTRIG) )
 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
 
 /**
  * @}
  */
 
-    
-
-    
-    
-   
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup ADCEx_Exported_Functions
  * @{
@@ -689,7 +590,6 @@ void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* ha
  * @}
  */
 
-
 /* Peripheral Control functions ***********************************************/
 /** @addtogroup ADCEx_Exported_Functions_Group2
  * @{
@@ -702,12 +602,10 @@ HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc
  * @}
  */
 
-
 /**
  * @}
  */
 
-
 /**
  * @}
  */
@@ -722,5 +620,4 @@ HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc
 
 #endif /* __STM32F1xx_HAL_ADC_EX_H */
 
-
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h

@@ -61,8 +61,7 @@
  * @brief  MPU Region initialization structure
  * @{
  */
-typedef struct
+typedef struct {
-{
   uint8_t Enable;           /*!< Specifies the status of the region.
                                  This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
   uint8_t Number;           /*!< Specifies the number of the region to protect.
@@ -103,15 +102,20 @@ typedef struct
 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
  * @{
  */
-#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
+#define NVIC_PRIORITYGROUP_0                       \
+  0x00000007U /*!< 0 bits for pre-emption priority \
                    4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
+#define NVIC_PRIORITYGROUP_1                       \
+  0x00000006U /*!< 1 bits for pre-emption priority \
                    3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
+#define NVIC_PRIORITYGROUP_2                       \
+  0x00000005U /*!< 2 bits for pre-emption priority \
                    2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
+#define NVIC_PRIORITYGROUP_3                       \
+  0x00000004U /*!< 3 bits for pre-emption priority \
                    1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
+#define NVIC_PRIORITYGROUP_4                       \
+  0x00000003U /*!< 4 bits for pre-emption priority \
                    0 bits for subpriority */
 /**
  * @}
@@ -263,7 +267,6 @@ typedef struct
  * @}
  */
 
-
 /* Exported Macros -----------------------------------------------------------*/
 
 /* Exported functions --------------------------------------------------------*/
@@ -319,11 +322,8 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
  * @{
  */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+#define IS_NVIC_PRIORITY_GROUP(GROUP) \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+  (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))
-                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
 
 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
 
@@ -331,73 +331,36 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
 
 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
 
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
 
 #if (__MPU_PRESENT == 1U)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
-                                     ((STATE) == MPU_REGION_DISABLE))
 
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
 
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
 
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
 
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
 
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2))
-                                ((TYPE) == MPU_TEX_LEVEL1)  || \
-                                ((TYPE) == MPU_TEX_LEVEL2))
 
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)                                                                                                                                    \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+  (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+   || ((TYPE) == MPU_REGION_PRIV_RO_URO))
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
 
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
+#define IS_MPU_REGION_NUMBER(NUMBER)                                                                                                                                                \
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
+  (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) \
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
+   || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER7))
 
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+#define IS_MPU_REGION_SIZE(SIZE)                                                                                                                                                          \
-                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+  (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B)         \
-                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+   || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB)        \
-                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+   || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+   || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB)        \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+   || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+   || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
 
 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
 #endif /* __MPU_PRESENT */
@@ -422,5 +385,4 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
 
 #endif /* __STM32F1xx_HAL_CORTEX_H */
 
-
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h

@@ -54,22 +54,12 @@ extern "C" {
 /**
  * @brief  HAL Status structures definition
  */
-typedef enum
+typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef;
-{
-  HAL_OK       = 0x00U,
-  HAL_ERROR    = 0x01U,
-  HAL_BUSY     = 0x02U,
-  HAL_TIMEOUT  = 0x03U
-} HAL_StatusTypeDef;
 
 /**
  * @brief  HAL Lock structures definition
  */
-typedef enum
+typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef;
-{
-  HAL_UNLOCKED = 0x00U,
-  HAL_LOCKED   = 0x01U
-} HAL_LockTypeDef;
 
 /* Exported macro ------------------------------------------------------------*/
 #define HAL_MAX_DELAY 0xFFFFFFFFU
@@ -108,12 +98,9 @@ typedef enum
 #else
 #define __HAL_LOCK(__HANDLE__)              \
   do {                                      \
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+    if ((__HANDLE__)->Lock == HAL_LOCKED) { \
-                                    {                                      \
       return HAL_BUSY;                      \
-                                    }                                      \
+    } else {                                \
-                                    else                                   \
-                                    {                                      \
       (__HANDLE__)->Lock = HAL_LOCKED;      \
     }                                       \
   } while (0U)
@@ -133,7 +120,6 @@ typedef enum
 #endif /* __packed */
 #endif /* __GNUC__ */
 
-
 /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
 #if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
 #ifndef __ALIGN_END
@@ -155,7 +141,6 @@ typedef enum
 #endif /* __ALIGN_BEGIN */
 #endif /* __GNUC__ */
 
-
 /**
  * @brief  __RAM_FUNC definition
  */

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h

@@ -61,8 +61,7 @@
 /**
  * @brief  DMA Configuration Structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
                            from memory to memory or from peripheral to memory.
                            This parameter can be a value of @ref DMA_Data_transfer_direction */
@@ -91,8 +90,7 @@ typedef struct
 /**
  * @brief  HAL DMA State structures definition
  */
-typedef enum
+typedef enum {
-{
   HAL_DMA_STATE_RESET   = 0x00U, /*!< DMA not yet initialized or disabled    */
   HAL_DMA_STATE_READY   = 0x01U, /*!< DMA initialized and ready for use      */
   HAL_DMA_STATE_BUSY    = 0x02U, /*!< DMA process is ongoing                 */
@@ -102,8 +100,7 @@ typedef enum
 /**
  * @brief  HAL DMA Error Code structure definition
  */
-typedef enum
+typedef enum {
-{
   HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer     */
   HAL_DMA_HALF_TRANSFER = 0x01U  /*!< Half Transfer     */
 } HAL_DMA_LevelCompleteTypeDef;
@@ -111,8 +108,7 @@ typedef enum
 /**
  * @brief  HAL DMA Callback ID structure definition
  */
-typedef enum
+typedef enum {
-{
   HAL_DMA_XFER_CPLT_CB_ID     = 0x00U, /*!< Full transfer     */
   HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer     */
   HAL_DMA_XFER_ERROR_CB_ID    = 0x02U, /*!< Error             */
@@ -124,8 +120,7 @@ typedef enum
 /**
  * @brief  DMA handle Structure definition
  */
-typedef struct __DMA_HandleTypeDef
+typedef struct __DMA_HandleTypeDef {
-{
   DMA_Channel_TypeDef *Instance; /*!< Register base address                  */
 
   DMA_InitTypeDef Init; /*!< DMA communication parameters           */
@@ -242,7 +237,6 @@ typedef struct __DMA_HandleTypeDef
  * @}
  */
 
-
 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
  * @{
  */
@@ -292,7 +286,6 @@ typedef struct __DMA_HandleTypeDef
  * @}
  */
 
-
 /* Exported macros -----------------------------------------------------------*/
 /** @defgroup DMA_Exported_Macros DMA Exported Macros
  * @{
@@ -318,7 +311,6 @@ typedef struct __DMA_HandleTypeDef
  */
 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
 
-
 /* Interrupt & Flag management */
 
 /**
@@ -422,33 +414,21 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
  * @{
  */
 
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 
 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
 
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))
-                                            ((STATE) == DMA_PINC_DISABLE))
 
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))
-                                        ((STATE) == DMA_MINC_DISABLE))
 
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD))
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))
 
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD))
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
 
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR))
-                           ((MODE) == DMA_CIRCULAR))
 
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 
 /**
  * @}

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h

@@ -59,8 +59,7 @@
  * @{
  */
 /* Interrupt & Flag management */
-#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
 /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
  * @{
  */
@@ -71,18 +70,27 @@
  * @retval The specified transfer complete flag index.
  */
 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)                                                                            \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+       ? DMA_FLAG_TC1                                                                                                      \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+             ? DMA_FLAG_TC2                                                                                                \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+                   ? DMA_FLAG_TC3                                                                                          \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+                         ? DMA_FLAG_TC4                                                                                    \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+                               ? DMA_FLAG_TC5                                                                              \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
-   DMA_FLAG_TC5)
+                                     ? DMA_FLAG_TC6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_TC7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_TC1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_TC2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_TC3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 : DMA_FLAG_TC5)
 
 /**
  * @brief  Returns the current DMA Channel half transfer complete flag.
@@ -90,18 +98,27 @@
  * @retval The specified half transfer complete flag index.
  */
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)                                                                            \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+       ? DMA_FLAG_HT1                                                                                                      \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+             ? DMA_FLAG_HT2                                                                                                \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+                   ? DMA_FLAG_HT3                                                                                          \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+                         ? DMA_FLAG_HT4                                                                                    \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+                               ? DMA_FLAG_HT5                                                                              \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
-   DMA_FLAG_HT5)
+                                     ? DMA_FLAG_HT6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_HT7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_HT1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_HT2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_HT3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 : DMA_FLAG_HT5)
 
 /**
  * @brief  Returns the current DMA Channel transfer error flag.
@@ -109,18 +126,27 @@
  * @retval The specified transfer error flag index.
  */
 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)                                                                            \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+       ? DMA_FLAG_TE1                                                                                                      \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+             ? DMA_FLAG_TE2                                                                                                \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+                   ? DMA_FLAG_TE3                                                                                          \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+                         ? DMA_FLAG_TE4                                                                                    \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+                               ? DMA_FLAG_TE5                                                                              \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
-   DMA_FLAG_TE5)
+                                     ? DMA_FLAG_TE6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_TE7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_TE1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_TE2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_TE3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 : DMA_FLAG_TE5)
 
 /**
  * @brief  Return the current DMA Channel Global interrupt flag.
@@ -128,18 +154,27 @@
  * @retval The specified transfer error flag index.
  */
 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)                                                                            \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                                       \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
+       ? DMA_FLAG_GL1                                                                                                      \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                                 \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
+             ? DMA_FLAG_GL2                                                                                                \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                                           \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
+                   ? DMA_FLAG_GL3                                                                                          \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                                     \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
+                         ? DMA_FLAG_GL4                                                                                    \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))                               \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
+                               ? DMA_FLAG_GL5                                                                              \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
+                               : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))                         \
-   DMA_FLAG_GL5)
+                                     ? DMA_FLAG_GL6                                                                        \
+                                     : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))                   \
+                                           ? DMA_FLAG_GL7                                                                  \
+                                           : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))             \
+                                                 ? DMA_FLAG_GL1                                                            \
+                                                 : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))       \
+                                                       ? DMA_FLAG_GL2                                                      \
+                                                       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
+                                                             ? DMA_FLAG_GL3                                                \
+                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 : DMA_FLAG_GL5)
 
 /**
  * @brief  Get the DMA Channel pending flags.
@@ -152,9 +187,7 @@
  *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
  * @retval The state of FLAG (SET or RESET).
  */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
-  (DMA1->ISR & (__FLAG__)))
 
 /**
  * @brief  Clears the DMA Channel pending flags.
@@ -167,9 +200,7 @@
  *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
  * @retval None
  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
-  (DMA1->IFCR = (__FLAG__)))
 
 /**
  * @}
@@ -186,13 +217,16 @@
  * @retval The specified transfer complete flag index.
  */
 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)                                                             \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+       ? DMA_FLAG_TC1                                                                                       \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+             ? DMA_FLAG_TC2                                                                                 \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+                   ? DMA_FLAG_TC3                                                                           \
-   DMA_FLAG_TC7)
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_TC4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 : DMA_FLAG_TC7)
 
 /**
  * @brief  Return the current DMA Channel half transfer complete flag.
@@ -200,13 +234,16 @@
  * @retval The specified half transfer complete flag index.
  */
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)                                                             \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+       ? DMA_FLAG_HT1                                                                                       \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+             ? DMA_FLAG_HT2                                                                                 \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+                   ? DMA_FLAG_HT3                                                                           \
-   DMA_FLAG_HT7)
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_HT4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 : DMA_FLAG_HT7)
 
 /**
  * @brief  Return the current DMA Channel transfer error flag.
@@ -214,13 +251,16 @@
  * @retval The specified transfer error flag index.
  */
 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)                                                             \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+       ? DMA_FLAG_TE1                                                                                       \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+             ? DMA_FLAG_TE2                                                                                 \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+                   ? DMA_FLAG_TE3                                                                           \
-   DMA_FLAG_TE7)
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_TE4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 : DMA_FLAG_TE7)
 
 /**
  * @brief  Return the current DMA Channel Global interrupt flag.
@@ -228,13 +268,16 @@
  * @retval The specified transfer error flag index.
  */
 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)                                                             \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
+  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))                                        \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
+       ? DMA_FLAG_GL1                                                                                       \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
+       : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))                                  \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
+             ? DMA_FLAG_GL2                                                                                 \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
+             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))                            \
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
+                   ? DMA_FLAG_GL3                                                                           \
-   DMA_FLAG_GL7)
+                   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))                      \
+                         ? DMA_FLAG_GL4                                                                     \
+                         : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
+                                                                                             : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 : DMA_FLAG_GL7)
 
 /**
  * @brief  Get the DMA Channel pending flags.

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h

@@ -64,14 +64,10 @@
  * @{
  */
 
-#define IS_FLASH_TYPEPROGRAM(VALUE)  (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
-                                      ((VALUE) == FLASH_TYPEPROGRAM_WORD)     || \
-                                      ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))  
 
 #if defined(FLASH_ACR_LATENCY)
-#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
+#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1) || ((__LATENCY__) == FLASH_LATENCY_2))
-                                       ((__LATENCY__) == FLASH_LATENCY_1) || \
-                                       ((__LATENCY__) == FLASH_LATENCY_2))
 
 #else
 #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
@@ -88,8 +84,7 @@
 /**
  * @brief  FLASH Procedure structure definition
  */
-typedef enum 
+typedef enum {
-{
   FLASH_PROC_NONE              = 0U,
   FLASH_PROC_PAGEERASE         = 1U,
   FLASH_PROC_MASSERASE         = 2U,
@@ -101,8 +96,7 @@ typedef enum
 /**
  * @brief  FLASH handle Structure definition
  */
-typedef struct
+typedef struct {
-{
   __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
 
   __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
@@ -223,7 +217,6 @@ typedef struct
  */
 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__))
 
-
 /**
  * @brief  Get the FLASH Latency.
  * @retval FLASH Latency
@@ -341,4 +334,3 @@ HAL_StatusTypeDef       FLASH_WaitForLastOperationBank2(uint32_t Timeout);
 #endif /* __STM32F1xx_HAL_FLASH_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h

@@ -90,84 +90,88 @@
 
 /* Low Density */
 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
-                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU))
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))
 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
 
 /* Medium Density */
 #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                                  \
-                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U)                      \
-                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
+       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU)        \
-                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))
+       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U)               \
+              ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU) \
+              : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))))
 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
 
 /* High Density */
 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                           \
-                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U)              \
-                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))
+       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0807FFFFU) \
+       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0805FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU)))
 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
 
 /* XL Density */
 #if defined(FLASH_BANK2_END)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
-                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU))
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080FFFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080BFFFFU))
 #endif /* FLASH_BANK2_END */
 
 /* Connectivity Line */
 #if (defined(STM32F105xC) || defined(STM32F107xC))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \
+#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                           \
-                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) ==  0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
+  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U)              \
-                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU)))
+       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU) \
+       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU)))
 #endif /* STM32F105xC || STM32F107xC */
 
 #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
 
 #if defined(FLASH_BANK2_END)
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || ((BANK) == FLASH_BANK_BOTH))
-                             ((BANK) == FLASH_BANK_2)  || \
-                             ((BANK) == FLASH_BANK_BOTH))
 #else
 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
 #endif /* FLASH_BANK2_END */
 
 /* Low Density */
 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
-                                            ((ADDRESS) <= FLASH_BANK1_END) :  ((ADDRESS) <= 0x08003FFFU)))
 
 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
 
 /* Medium Density */
 #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                      \
-                                           ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
+  (((ADDRESS) >= FLASH_BASE)                                                                   \
-                                           ((ADDRESS) <= 0x0800FFFF) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
+   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U)                                    \
-                                           ((ADDRESS) <= 0x08007FFF) :  ((ADDRESS) <= 0x08003FFFU)))))
+           ? ((ADDRESS) <= FLASH_BANK1_END)                                                    \
+           : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS) <= 0x0800FFFF) \
+                                                                   : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
 
 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
 
 /* High Density */
 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                     \
-                                           ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
+  (((ADDRESS) >= FLASH_BASE)                                                                  \
-                                           ((ADDRESS) <= 0x0805FFFFU) :  ((ADDRESS) <= 0x0803FFFFU))))
+   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS) <= FLASH_BANK1_END) \
+                                                             : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
 
 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
 
 /* XL Density */
 #if defined(FLASH_BANK2_END)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
-                                           ((ADDRESS) <= FLASH_BANK2_END) :  ((ADDRESS) <= 0x080BFFFFU)))
 
 #endif /* FLASH_BANK2_END */
 
 /* Connectivity Line */
 #if (defined(STM32F105xC) || defined(STM32F107xC))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                     \
-                                           ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
+  (((ADDRESS) >= FLASH_BASE)                                                                  \
-                                           ((ADDRESS) <= 0x0801FFFFU) :  ((ADDRESS) <= 0x0800FFFFU))))
+   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS) <= FLASH_BANK1_END) \
+                                                             : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
 
 #endif /* STM32F105xC || STM32F107xC */
 
@@ -183,8 +187,7 @@
 /**
  * @brief  FLASH Erase structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
                            This parameter can be a value of @ref FLASHEx_Type_Erase */
 
@@ -203,8 +206,7 @@ typedef struct
 /**
  * @brief  FLASH Options bytes program structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t OptionType; /*!< OptionType: Option byte to be configured.
                             This parameter can be a value of @ref FLASHEx_OB_Type */
 
@@ -329,9 +331,7 @@ typedef struct
  * @{
  */
 /* STM32 Low and Medium density devices */
-#if  defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
-  || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
-  || defined(STM32F103xB)
 #define OB_WRP_PAGES0TO3   0x00000001U /*!< Write protection of page 0 to 3 */
 #define OB_WRP_PAGES4TO7   0x00000002U /*!< Write protection of page 4 to 7 */
 #define OB_WRP_PAGES8TO11  0x00000004U /*!< Write protection of page 8 to 11 */
@@ -371,11 +371,8 @@ typedef struct
 #define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */
 #endif                                   /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
 
-
 /* STM32 High-density, XL-density and Connectivity line devices */
-#if  defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-  || defined(STM32F101xG) || defined(STM32F103xG) \
-  || defined(STM32F105xC) || defined(STM32F107xC)
 #define OB_WRP_PAGES0TO1    0x00000001U /*!< Write protection of page 0 TO 1 */
 #define OB_WRP_PAGES2TO3    0x00000002U /*!< Write protection of page 2 TO 3 */
 #define OB_WRP_PAGES4TO5    0x00000004U /*!< Write protection of page 4 TO 5 */
@@ -582,7 +579,6 @@ typedef struct
  * @}
  */
 
-
 /**
  * @}
  */
@@ -608,7 +604,8 @@ typedef struct
  *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
  * @retval none
  */
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  do { \
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)           \
+  do {                                                 \
     /* Enable Bank1 IT */                              \
     SET_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
     /* Enable Bank2 IT */                              \
@@ -625,7 +622,8 @@ typedef struct
  *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
  * @retval none
  */
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  do { \
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)            \
+  do {                                                   \
     /* Disable Bank1 IT */                               \
     CLEAR_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
     /* Disable Bank2 IT */                               \
@@ -647,11 +645,8 @@ typedef struct
  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
  * @retval The new state of __FLAG__ (SET or RESET).
  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
+#define __HAL_FLASH_GET_FLAG(__FLAG__) \
-                                            (FLASH->OBR & FLASH_OBR_OPTERR) : \
+  (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : ((((__FLAG__)&SR_FLAG_MASK) != RESET) ? (FLASH->SR & ((__FLAG__)&SR_FLAG_MASK)) : (FLASH->SR2 & ((__FLAG__) >> 16U))))
-                                        ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
-                                            (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
-                                            (FLASH->SR2 & ((__FLAG__) >> 16U))))
 
 /**
  * @brief  Clear the specified FLASH flag.
@@ -668,21 +663,18 @@ typedef struct
  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
  * @retval none
  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)  do { \
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        \
+  do {                                          \
     /* Clear FLASH_FLAG_OPTVERR flag */         \
-                          if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
+    if ((__FLAG__) == FLASH_FLAG_OPTVERR) {     \
-                          { \
       CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR);  \
-                          } \
+    } else {                                    \
-                          else { \
       /* Clear Flag in Bank1 */                 \
-                          if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
+      if (((__FLAG__)&SR_FLAG_MASK) != RESET) { \
-                          { \
         FLASH->SR = ((__FLAG__)&SR_FLAG_MASK);  \
       }                                         \
       /* Clear Flag in Bank2 */                 \
-                          if (((__FLAG__) >> 16U) != RESET) \
+      if (((__FLAG__) >> 16U) != RESET) {       \
-                          { \
         FLASH->SR2 = ((__FLAG__) >> 16U);       \
       }                                         \
     }                                           \
@@ -719,9 +711,7 @@ typedef struct
  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
  * @retval The new state of __FLAG__ (SET or RESET).
  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)  (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
+#define __HAL_FLASH_GET_FLAG(__FLAG__)        (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : (FLASH->SR & (__FLAG__)))
-                                            (FLASH->OBR & FLASH_OBR_OPTERR) : \
-                                            (FLASH->SR & (__FLAG__)))
 /**
  * @brief  Clear the specified FLASH flag.
  * @param  __FLAG__ specifies the FLASH flags to clear.
@@ -732,13 +722,12 @@ typedef struct
  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
  * @retval none
  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   do { \
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)       \
+  do {                                         \
     /* Clear FLASH_FLAG_OPTVERR flag */        \
-                          if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
+    if ((__FLAG__) == FLASH_FLAG_OPTVERR) {    \
-                          { \
       CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
-                          } \
+    } else {                                   \
-                          else { \
       /* Clear Flag in Bank1 */                \
       FLASH->SR = (__FLAG__);                  \
     }                                          \

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h

@@ -60,8 +60,7 @@ extern "C" {
 /**
  * @brief GPIO Init structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
                      This parameter can be any value of @ref GPIO_pins_define */
 
@@ -78,11 +77,7 @@ typedef struct
 /**
  * @brief  GPIO Bit SET and Bit RESET enumeration
  */
-typedef enum
+typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState;
-{
-  GPIO_PIN_RESET = 0U,
-  GPIO_PIN_SET
-} GPIO_PinState;
 /**
  * @}
  */
@@ -278,22 +273,12 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
  */
 #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
 #define IS_GPIO_PIN(PIN)           ((((PIN)&GPIO_PIN_MASK) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
+#define IS_GPIO_MODE(MODE)                                                                                                                                                                             \
-                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
+  (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING)  \
-                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
+   || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) \
-                            ((MODE) == GPIO_MODE_AF_PP)              ||\
+   || ((MODE) == GPIO_MODE_ANALOG))
-                            ((MODE) == GPIO_MODE_AF_OD)              ||\
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
-                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
+#define IS_GPIO_PULL(PULL)   (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN))
-                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
-                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
-                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
-                            ((MODE) == GPIO_MODE_ANALOG))
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
-                              ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
-                            ((PULL) == GPIO_PULLDOWN))
 /**
  * @}
  */

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h

@@ -84,22 +84,11 @@ extern "C" {
 #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
 #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
 
-#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
+#define IS_AFIO_EVENTOUT_PIN(__PIN__)                                                                                                                                                                 \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
+  (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4)         \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
+   || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9)      \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
+   || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
+   || ((__PIN__) == AFIO_EVENTOUT_PIN_15))
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
-                                       ((__PIN__) == AFIO_EVENTOUT_PIN_15))
 /**
  * @}
  */
@@ -114,11 +103,8 @@ extern "C" {
 #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
 #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
 
-#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
+#define IS_AFIO_EVENTOUT_PORT(__PORT__) \
-                                         ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
+  (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))
-                                         ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
-                                         ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
-                                         ((__PORT__) == AFIO_EVENTOUT_PORT_E))
 /**
  * @}
  */
@@ -825,43 +811,42 @@ extern "C" {
  * @{
  */
 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : 3U)
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :3U)
 #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : 4U)
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :\
-                                   ((__GPIOx__) == (GPIOD))? 3U :4U)
 #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+#define GPIO_GET_INDEX(__GPIOx__) \
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
+  (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : ((__GPIOx__) == (GPIOE)) ? 4U : ((__GPIOx__) == (GPIOF)) ? 5U : 6U)
-                                   ((__GPIOx__) == (GPIOC))? 2U :\
-                                   ((__GPIOx__) == (GPIOD))? 3U :\
-                                   ((__GPIOx__) == (GPIOE))? 4U :\
-                                   ((__GPIOx__) == (GPIOF))? 5U :6U)
 #endif
 
-#define AFIO_REMAP_ENABLE(REMAP_PIN)       do{ uint32_t tmpreg = AFIO->MAPR; \
+#define AFIO_REMAP_ENABLE(REMAP_PIN) \
+  do {                               \
+    uint32_t tmpreg = AFIO->MAPR;    \
     tmpreg |= AFIO_MAPR_SWJ_CFG;     \
     tmpreg |= REMAP_PIN;             \
     AFIO->MAPR = tmpreg;             \
   } while (0U)
 
-#define AFIO_REMAP_DISABLE(REMAP_PIN)      do{ uint32_t tmpreg = AFIO->MAPR;  \
+#define AFIO_REMAP_DISABLE(REMAP_PIN) \
+  do {                                \
+    uint32_t tmpreg = AFIO->MAPR;     \
     tmpreg |= AFIO_MAPR_SWJ_CFG;      \
     tmpreg &= ~REMAP_PIN;             \
     AFIO->MAPR = tmpreg;              \
   } while (0U)
 
-#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \
+#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) \
+  do {                                                \
+    uint32_t tmpreg = AFIO->MAPR;                     \
     tmpreg &= ~REMAP_PIN_MASK;                        \
     tmpreg |= AFIO_MAPR_SWJ_CFG;                      \
     tmpreg |= REMAP_PIN;                              \
     AFIO->MAPR = tmpreg;                              \
   } while (0U)
 
-#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG)  do{ uint32_t tmpreg = AFIO->MAPR;     \
+#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) \
+  do {                                    \
+    uint32_t tmpreg = AFIO->MAPR;         \
     tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk;     \
     tmpreg |= DBGAFR_SWJCFG;              \
     AFIO->MAPR = tmpreg;                  \

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h

@@ -60,8 +60,7 @@
 /**
  * @brief  I2C Configuration Structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t ClockSpeed; /*!< Specifies the clock frequency.
                             This parameter must be set to a value lower than 400kHz */
 
@@ -114,8 +113,7 @@ typedef struct
  *             0  : Ready (no Tx operation ongoing)
  *             1  : Busy (Tx operation ongoing)
  */
-typedef enum
+typedef enum {
-{
   HAL_I2C_STATE_RESET          = 0x00U, /*!< Peripheral is not yet Initialized         */
   HAL_I2C_STATE_READY          = 0x20U, /*!< Peripheral Initialized and ready for use  */
   HAL_I2C_STATE_BUSY           = 0x24U, /*!< An internal process is ongoing            */
@@ -149,8 +147,7 @@ typedef enum
  *          b3-b2-b1-b0  (not used)
  *             xxxx : Should be set to 0000
  */
-typedef enum
+typedef enum {
-{
   HAL_I2C_MODE_NONE   = 0x00U, /*!< No I2C communication on going             */
   HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode       */
   HAL_I2C_MODE_SLAVE  = 0x20U, /*!< I2C communication is in Slave Mode        */
@@ -161,8 +158,7 @@ typedef enum
 /**
  * @brief  I2C handle Structure definition
  */
-typedef struct
+typedef struct {
-{
   I2C_TypeDef *Instance; /*!< I2C registers base address               */
 
   I2C_InitTypeDef Init; /*!< I2C communication parameters             */
@@ -406,8 +402,9 @@ typedef struct
  *            @arg I2C_FLAG_MSL: Master/Slave flag
  * @retval The new state of __FLAG__ (TRUE or FALSE).
  */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)                                                                                            \
-                                                 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
+  ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? ((((__HANDLE__)->Instance->SR1) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)) \
+                                             : ((((__HANDLE__)->Instance->SR2) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)))
 
 /** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
  * @param  __HANDLE__: specifies the I2C Handle.
@@ -578,10 +575,11 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 #define I2C_FREQRANGE(__PCLK__)                             ((__PCLK__) / 1000000U)
 #define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)             (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__)*300U) / 1000U) + 1U))
 #define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)             ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U) ? 4U : I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) \
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+  (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2) ? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)                       \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+  (((__SPEED__) <= 100000U) ? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) \
+                            : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U) ? 1U : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
 
 #define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
 #define I2C_7BIT_ADD_READ(__ADDRESS__)  ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
@@ -596,25 +594,16 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 /** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
  * @{
  */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+#define IS_I2C_DUTY_CYCLE(CYCLE)                 (((CYCLE) == I2C_DUTYCYCLE_2) || ((CYCLE) == I2C_DUTYCYCLE_16_9))
-                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))
+#define IS_I2C_ADDRESSING_MODE(ADDRESS)          (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
-#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)             (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+#define IS_I2C_GENERAL_CALL(CALL)                (((CALL) == I2C_GENERALCALL_DISABLE) || ((CALL) == I2C_GENERALCALL_ENABLE))
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+#define IS_I2C_NO_STRETCH(STRETCH)               (((STRETCH) == I2C_NOSTRETCH_DISABLE) || ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+#define IS_I2C_MEMADD_SIZE(SIZE)                 (((SIZE) == I2C_MEMADD_SIZE_8BIT) || ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
-                                   ((CALL) == I2C_GENERALCALL_ENABLE))
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
-                                    ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
-                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))
 #define IS_I2C_CLOCK_SPEED(SPEED)                (((SPEED) > 0) && ((SPEED) <= 400000U))
 #define IS_I2C_OWN_ADDRESS1(ADDRESS1)            (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
 #define IS_I2C_OWN_ADDRESS2(ADDRESS2)            (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == I2C_FIRST_FRAME)              || \
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || ((REQUEST) == I2C_NEXT_FRAME) || ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME))
-                                                       ((REQUEST) == I2C_NEXT_FRAME)               || \
-                                                       ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
-                                                       ((REQUEST) == I2C_LAST_FRAME))
 /**
  * @}
  */
@@ -644,7 +633,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 }
 #endif
 
-
 #endif /* __STM32F1xx_HAL_I2C_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h

@@ -60,8 +60,7 @@ extern "C" {
 /**
  * @brief  IWDG Init structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
                            This parameter can be a value of @ref IWDG_Prescaler */
 
@@ -73,8 +72,7 @@ typedef struct
 /**
  * @brief  IWDG Handle Structure definition
  */
-typedef struct
+typedef struct {
-{
   IWDG_TypeDef *Instance; /*!< Register base address    */
 
   IWDG_InitTypeDef Init; /*!< IWDG required parameters */
@@ -108,7 +106,6 @@ typedef struct
  * @}
  */
 
-
 /* Exported macros -----------------------------------------------------------*/
 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
  * @{
@@ -201,13 +198,9 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
  * @param  __PRESCALER__  IWDG prescaler value
  * @retval None
  */
-#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
+#define IS_IWDG_PRESCALER(__PRESCALER__)                                                                                                                              \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
+  (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+   || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128) || ((__PRESCALER__) == IWDG_PRESCALER_256))
-                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
 
 /**
  * @brief  Check IWDG reload value.
@@ -228,7 +221,6 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
  * @}
  */
 
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h

@@ -61,8 +61,7 @@
 /**
  * @brief  PWR PVD configuration structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
                           This parameter can be a value of @ref PWR_PVD_detection_level */
 
@@ -70,12 +69,10 @@ typedef struct
                       This parameter can be a value of @ref PWR_PVD_Mode */
 } PWR_PVDTypeDef;
 
-
 /**
  * @}
  */
 
-
 /* Internal constants --------------------------------------------------------*/
 
 /** @addtogroup PWR_Private_Constants
@@ -88,7 +85,6 @@ typedef struct
  * @}
  */
 
- 
 /* Exported constants --------------------------------------------------------*/
 
 /** @defgroup PWR_Exported_Constants PWR Exported Constants
@@ -126,7 +122,6 @@ typedef struct
  * @}
  */
 
-
 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
  * @{
  */
@@ -174,7 +169,6 @@ typedef struct
 #define PWR_FLAG_SB   PWR_CSR_SBF
 #define PWR_FLAG_PVDO PWR_CSR_PVDO
 
-
 /**
  * @}
  */
@@ -237,21 +231,18 @@ typedef struct
  */
 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
 
-
 /**
  * @brief  PVD EXTI line configuration: set falling edge trigger.
  * @retval None.
  */
 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
 
-
 /**
  * @brief Disable the PVD Extended Interrupt Falling Trigger.
  * @retval None.
  */
 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
 
-
 /**
  * @brief  PVD EXTI line configuration: set rising edge trigger.
  * @retval None.
@@ -269,16 +260,18 @@ typedef struct
  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
  * @retval None.
  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();              \
+  __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
 
 /**
  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
  * This parameter can be:
  * @retval None.
  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
-
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();              \
-
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
 
 /**
  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
@@ -305,21 +298,17 @@ typedef struct
 /** @defgroup PWR_Private_Macros PWR Private Macros
  * @{
  */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+#define IS_PWR_PVD_LEVEL(LEVEL)                                                                                                                                                           \
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+  (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) \
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+   || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
 
-
+#define IS_PWR_PVD_MODE(MODE)                                                                                                                                       \
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+  (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) \
-                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+   || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))
-                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_NORMAL)) 
 
 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
 
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
 
 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
 
@@ -329,8 +318,6 @@ typedef struct
  * @}
  */
 
-
-
 /* Exported functions --------------------------------------------------------*/
 
 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
@@ -374,8 +361,6 @@ void HAL_PWR_DisableSleepOnExit(void);
 void HAL_PWR_EnableSEVOnPend(void);
 void HAL_PWR_DisableSEVOnPend(void);
 
-
-
 void HAL_PWR_PVD_IRQHandler(void);
 void HAL_PWR_PVDCallback(void);
 /**
@@ -398,7 +383,6 @@ void HAL_PWR_PVDCallback(void);
 }
 #endif
 
-
 #endif /* __STM32F1xx_HAL_PWR_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h

@@ -61,8 +61,7 @@
 /**
  * @brief  RCC PLL configuration structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t PLLState; /*!< PLLState: The new state of the PLL.
                          This parameter can be a value of @ref RCC_PLL_Config */
 
@@ -76,8 +75,7 @@ typedef struct
 /**
  * @brief  RCC System, AHB and APB busses clock configuration structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t ClockType; /*!< The clock to be configured.
                            This parameter can be a value of @ref RCC_System_Clock_Type */
 
@@ -255,7 +253,6 @@ typedef struct
  * @}
  */
 
-
 /** @defgroup RCC_MCO_Index MCO Index
  * @{
  */
@@ -335,7 +332,8 @@ typedef struct
  *         using it.
  * @{
  */
-#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
+#define __HAL_RCC_DMA1_CLK_ENABLE()                    \
+  do {                                                 \
     __IO uint32_t tmpreg;                              \
     SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);           \
     /* Delay after an RCC peripheral clock enabling */ \
@@ -343,7 +341,8 @@ typedef struct
     UNUSED(tmpreg);                                    \
   } while (0U)
 
-#define __HAL_RCC_SRAM_CLK_ENABLE()   do { \
+#define __HAL_RCC_SRAM_CLK_ENABLE()                    \
+  do {                                                 \
     __IO uint32_t tmpreg;                              \
     SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);           \
     /* Delay after an RCC peripheral clock enabling */ \
@@ -351,7 +350,8 @@ typedef struct
     UNUSED(tmpreg);                                    \
   } while (0U)
 
-#define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
+#define __HAL_RCC_FLITF_CLK_ENABLE()                    \
+  do {                                                  \
     __IO uint32_t tmpreg;                               \
     SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);           \
     /* Delay after an RCC peripheral clock enabling */  \
@@ -359,7 +359,8 @@ typedef struct
     UNUSED(tmpreg);                                     \
   } while (0U)
 
-#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
+#define __HAL_RCC_CRC_CLK_ENABLE()                     \
+  do {                                                 \
     __IO uint32_t tmpreg;                              \
     SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);            \
     /* Delay after an RCC peripheral clock enabling */ \
@@ -404,7 +405,8 @@ typedef struct
  *         using it.
  * @{
  */
-#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
+#define __HAL_RCC_TIM2_CLK_ENABLE()                      \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -412,7 +414,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
+#define __HAL_RCC_TIM3_CLK_ENABLE()                      \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -420,7 +423,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
+#define __HAL_RCC_WWDG_CLK_ENABLE()                      \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -428,7 +432,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
+#define __HAL_RCC_USART2_CLK_ENABLE()                      \
+  do {                                                     \
     __IO uint32_t tmpreg;                                  \
     SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);           \
     /* Delay after an RCC peripheral clock enabling */     \
@@ -436,7 +441,8 @@ typedef struct
     UNUSED(tmpreg);                                        \
   } while (0U)
 
-#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
+#define __HAL_RCC_I2C1_CLK_ENABLE()                      \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -444,7 +450,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_BKP_CLK_ENABLE()   do { \
+#define __HAL_RCC_BKP_CLK_ENABLE()                      \
+  do {                                                  \
     __IO uint32_t tmpreg;                               \
     SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);           \
     /* Delay after an RCC peripheral clock enabling */  \
@@ -452,7 +459,8 @@ typedef struct
     UNUSED(tmpreg);                                     \
   } while (0U)
 
-#define __HAL_RCC_PWR_CLK_ENABLE()   do { \
+#define __HAL_RCC_PWR_CLK_ENABLE()                      \
+  do {                                                  \
     __IO uint32_t tmpreg;                               \
     SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);           \
     /* Delay after an RCC peripheral clock enabling */  \
@@ -507,7 +515,8 @@ typedef struct
  *         using it.
  * @{
  */
-#define __HAL_RCC_AFIO_CLK_ENABLE()   do { \
+#define __HAL_RCC_AFIO_CLK_ENABLE()                      \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -515,7 +524,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
+#define __HAL_RCC_GPIOA_CLK_ENABLE()                     \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -523,7 +533,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
+#define __HAL_RCC_GPIOB_CLK_ENABLE()                     \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -531,7 +542,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
+#define __HAL_RCC_GPIOC_CLK_ENABLE()                     \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -539,7 +551,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+#define __HAL_RCC_GPIOD_CLK_ENABLE()                     \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -547,7 +560,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
+#define __HAL_RCC_ADC1_CLK_ENABLE()                      \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -555,7 +569,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
+#define __HAL_RCC_TIM1_CLK_ENABLE()                      \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -563,7 +578,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
+#define __HAL_RCC_SPI1_CLK_ENABLE()                      \
+  do {                                                   \
     __IO uint32_t tmpreg;                                \
     SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);           \
     /* Delay after an RCC peripheral clock enabling */   \
@@ -571,7 +587,8 @@ typedef struct
     UNUSED(tmpreg);                                      \
   } while (0U)
 
-#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
+#define __HAL_RCC_USART1_CLK_ENABLE()                      \
+  do {                                                     \
     __IO uint32_t tmpreg;                                  \
     SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);           \
     /* Delay after an RCC peripheral clock enabling */     \
@@ -709,8 +726,7 @@ typedef struct
  *         (default is RCC_HSICALIBRATION_DEFAULT).
  *         This parameter must be a number between 0 and 0x1F.
  */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
-          (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
 
 /**
  * @}
@@ -766,22 +782,15 @@ typedef struct
  */
 #define __HAL_RCC_HSE_CONFIG(__STATE__)         \
   do {                                          \
-                      if ((__STATE__) == RCC_HSE_ON)                        \
+    if ((__STATE__) == RCC_HSE_ON) {            \
-                      {                                                     \
       SET_BIT(RCC->CR, RCC_CR_HSEON);           \
-                      }                                                     \
+    } else if ((__STATE__) == RCC_HSE_OFF) {    \
-                      else if ((__STATE__) == RCC_HSE_OFF)                  \
-                      {                                                     \
       CLEAR_BIT(RCC->CR, RCC_CR_HSEON);         \
       CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);        \
-                      }                                                     \
+    } else if ((__STATE__) == RCC_HSE_BYPASS) { \
-                      else if ((__STATE__) == RCC_HSE_BYPASS)               \
-                      {                                                     \
       SET_BIT(RCC->CR, RCC_CR_HSEBYP);          \
       SET_BIT(RCC->CR, RCC_CR_HSEON);           \
-                      }                                                     \
+    } else {                                    \
-                      else                                                  \
-                      {                                                     \
       CLEAR_BIT(RCC->CR, RCC_CR_HSEON);         \
       CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);        \
     }                                           \
@@ -814,22 +823,15 @@ typedef struct
  */
 #define __HAL_RCC_LSE_CONFIG(__STATE__)         \
   do {                                          \
-                      if ((__STATE__) == RCC_LSE_ON)                        \
+    if ((__STATE__) == RCC_LSE_ON) {            \
-                      {                                                     \
       SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);       \
-                      }                                                     \
+    } else if ((__STATE__) == RCC_LSE_OFF) {    \
-                      else if ((__STATE__) == RCC_LSE_OFF)                  \
-                      {                                                     \
       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);     \
       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);    \
-                      }                                                     \
+    } else if ((__STATE__) == RCC_LSE_BYPASS) { \
-                      else if ((__STATE__) == RCC_LSE_BYPASS)               \
-                      {                                                     \
       SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);      \
       SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);       \
-                      }                                                     \
+    } else {                                    \
-                      else                                                  \
-                      {                                                     \
       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);     \
       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);    \
     }                                           \
@@ -886,8 +888,7 @@ typedef struct
   *             @arg @ref RCC_PLL_MUL9   PLLVCO = PLL clock entry x 9
   *
   */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL), ((__RCC_PLLSOURCE__) | (__PLLMUL__)))
-          MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
 
 /** @brief  Get oscillator clock selected as PLL input clock
  * @retval The clock source used for PLL entry. The returned value can be one
@@ -913,8 +914,7 @@ typedef struct
  *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
  *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
  */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
 
 /** @brief  Macro to get the clock source used as system clock.
  * @retval The clock source used as system clock. The returned value can be one
@@ -965,9 +965,7 @@ typedef struct
  */
 #endif
 
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
-                 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
-
 
 /**
  * @}
@@ -1143,9 +1141,7 @@ typedef struct
   *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)?   RCC->CR   : \
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) & (1U << ((__FLAG__)&RCC_FLAG_MASK)))
-                                      ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
-                                                                              RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
 
 /**
  * @}
@@ -1329,47 +1325,30 @@ void              HAL_RCC_CSSCallback(void);
  * @}
  */
 
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)                                                                                                                                                      \
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
+  (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+   || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+#define IS_RCC_HSE(__HSE__)                 (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS))
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+#define IS_RCC_LSE(__LSE__)                 (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
-                             ((__HSE__) == RCC_HSE_BYPASS))
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
-                             ((__LSE__) == RCC_LSE_BYPASS))
 #define IS_RCC_HSI(__HSI__)                 (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
 #define IS_RCC_LSI(__LSI__)                 (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
+#define IS_RCC_PLL(__PLL__)                 (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
-                             ((__PLL__) == RCC_PLL_ON))
 
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
+#define IS_RCC_CLOCKTYPE(CLK)                                                                                                                                           \
-                               (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
+  ((((CLK)&RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK)&RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK)&RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \
-                               (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
+   || (((CLK)&RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
-                               (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__)        (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+#define IS_RCC_HCLK(__HCLK__)                                                                                                                                                   \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+  (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) \
-#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+   || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))
-                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+#define IS_RCC_PCLK(__PCLK__)  (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))
-                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV512))
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
-                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
-                               ((__PCLK__) == RCC_HCLK_DIV16))
 #define IS_RCC_MCO(__MCO__)    ((__MCO__) == RCC_MCO)
 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) \
-                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+  (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
-                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
-                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
 
 /**
  * @}
@@ -1390,4 +1369,3 @@ void              HAL_RCC_CSSCallback(void);
 #endif /* __STM32F1xx_HAL_RCC_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h

@@ -59,8 +59,7 @@
 /**
  * @brief  TIM Time base Configuration Structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
                            This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
 
@@ -90,8 +89,7 @@ typedef struct
 /**
  * @brief  TIM Output Compare Configuration Structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t OCMode; /*!< Specifies the TIM mode.
                         This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
 
@@ -109,7 +107,6 @@ typedef struct
                              This parameter can be a value of @ref TIM_Output_Fast_State
                              @note This parameter is valid only in PWM1 and PWM2 mode. */
 
-
   uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
                              This parameter can be a value of @ref TIM_Output_Compare_Idle_State
                              @note This parameter is valid only for TIM1 and TIM8. */
@@ -122,8 +119,7 @@ typedef struct
 /**
  * @brief  TIM One Pulse Mode Configuration Structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t OCMode; /*!< Specifies the TIM mode.
                         This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
 
@@ -155,12 +151,10 @@ typedef struct
                          This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
 } TIM_OnePulse_InitTypeDef;
 
-
 /**
  * @brief  TIM Input Capture Configuration Structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
                             This parameter can be a value of @ref TIM_Input_Capture_Polarity */
 
@@ -177,8 +171,7 @@ typedef struct
 /**
  * @brief  TIM Encoder Configuration Structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
                              This parameter can be a value of @ref TIM_Encoder_Mode */
 
@@ -207,12 +200,10 @@ typedef struct
                            This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
 } TIM_Encoder_InitTypeDef;
 
-
 /**
  * @brief  TIM Clock Configuration Handle Structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t ClockSource;    /*!< TIM clock sources
                                 This parameter can be a value of @ref TIM_Clock_Source */
   uint32_t ClockPolarity;  /*!< TIM clock polarity
@@ -226,8 +217,7 @@ typedef struct
 /**
  * @brief  TIM Clear Input Configuration Handle Structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t ClearInputState;     /*!< TIM clear Input state
                                      This parameter can be ENABLE or DISABLE */
   uint32_t ClearInputSource;    /*!< TIM clear Input sources
@@ -260,8 +250,7 @@ typedef struct {
 /**
  * @brief  HAL State structures definition
  */
-typedef enum
+typedef enum {
-{
   HAL_TIM_STATE_RESET   = 0x00U, /*!< Peripheral not yet initialized or disabled  */
   HAL_TIM_STATE_READY   = 0x01U, /*!< Peripheral Initialized and ready for use    */
   HAL_TIM_STATE_BUSY    = 0x02U, /*!< An internal process is ongoing              */
@@ -272,8 +261,7 @@ typedef enum
 /**
  * @brief  HAL Active channel structures definition
  */
-typedef enum
+typedef enum {
-{
   HAL_TIM_ACTIVE_CHANNEL_1       = 0x01U, /*!< The active channel is 1     */
   HAL_TIM_ACTIVE_CHANNEL_2       = 0x02U, /*!< The active channel is 2     */
   HAL_TIM_ACTIVE_CHANNEL_3       = 0x04U, /*!< The active channel is 3     */
@@ -284,8 +272,7 @@ typedef enum
 /**
  * @brief  TIM Time Base Handle Structure definition
  */
-typedef struct
+typedef struct {
-{
   TIM_TypeDef *         Instance;  /*!< Register base address             */
   TIM_Base_InitTypeDef  Init;      /*!< TIM Time Base required parameters */
   HAL_TIM_ActiveChannel Channel;   /*!< Active channel                    */
@@ -468,9 +455,11 @@ typedef struct
 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
  * @{
  */
-#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
+#define TIM_ICSELECTION_DIRECTTI                                   \
+  (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
                                     connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
+#define TIM_ICSELECTION_INDIRECTTI                                                         \
+  (TIM_CCMR1_CC1S_1)                         /*!< TIM Input 1, 2, 3 or 4 is selected to be \
                                                             connected to IC2, IC1, IC4 or IC3, respectively */
 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
 /**
@@ -887,225 +876,123 @@ typedef struct
  * @{
  */
 
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP)              || \
+#define IS_TIM_COUNTER_MODE(MODE)                                                                                                                                 \
-                                   ((MODE) == TIM_COUNTERMODE_DOWN)            || \
+  (((MODE) == TIM_COUNTERMODE_UP) || ((MODE) == TIM_COUNTERMODE_DOWN) || ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+   || ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
 
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || ((DIV) == TIM_CLOCKDIVISION_DIV2) || ((DIV) == TIM_CLOCKDIVISION_DIV4))
-                                       ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
-                                       ((DIV) == TIM_CLOCKDIVISION_DIV4))
 
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
 
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2))
-                               ((MODE) == TIM_OCMODE_PWM2))
 
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)       || \
+#define IS_TIM_OC_MODE(MODE)                                                                                                                                                  \
-                          ((MODE) == TIM_OCMODE_ACTIVE)           || \
+  (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_FORCED_ACTIVE) \
-                          ((MODE) == TIM_OCMODE_INACTIVE)         || \
+   || ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
-                          ((MODE) == TIM_OCMODE_TOGGLE)           || \
-                          ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
-                          ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
 
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || ((STATE) == TIM_OCFAST_ENABLE))
-                                  ((STATE) == TIM_OCFAST_ENABLE))
 
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || ((POLARITY) == TIM_OCPOLARITY_LOW))
-                                      ((POLARITY) == TIM_OCPOLARITY_LOW))
 
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || ((POLARITY) == TIM_OCNPOLARITY_LOW))
-                                       ((POLARITY) == TIM_OCNPOLARITY_LOW))
 
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || ((STATE) == TIM_OCIDLESTATE_RESET))
-                                    ((STATE) == TIM_OCIDLESTATE_RESET))
 
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || ((STATE) == TIM_OCNIDLESTATE_RESET))
-                                     ((STATE) == TIM_OCNIDLESTATE_RESET))
 
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4) || ((CHANNEL) == TIM_CHANNEL_ALL))
-                                  ((CHANNEL) == TIM_CHANNEL_2) || \
-                                  ((CHANNEL) == TIM_CHANNEL_3) || \
-                                  ((CHANNEL) == TIM_CHANNEL_4) || \
-                                  ((CHANNEL) == TIM_CHANNEL_ALL))
 
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))
-                                      ((CHANNEL) == TIM_CHANNEL_2))
 
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3))
-                                                ((CHANNEL) == TIM_CHANNEL_2) || \
-                                                ((CHANNEL) == TIM_CHANNEL_3))
 
-#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-                                          ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
-                                          ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
 
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI)   || \
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || ((SELECTION) == TIM_ICSELECTION_TRC))
-                                        ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
-                                        ((SELECTION) == TIM_ICSELECTION_TRC))
 
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || ((PRESCALER) == TIM_ICPSC_DIV2) || ((PRESCALER) == TIM_ICPSC_DIV4) || ((PRESCALER) == TIM_ICPSC_DIV8))
-                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV8))
 
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPETITIVE))
-                               ((MODE) == TIM_OPMODE_REPETITIVE))
 
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || ((MODE) == TIM_ENCODERMODE_TI2) || ((MODE) == TIM_ENCODERMODE_TI12))
-                                   ((MODE) == TIM_ENCODERMODE_TI2) || \
-                                   ((MODE) == TIM_ENCODERMODE_TI12))   
 
 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE)&0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
 
 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE)&0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
 
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+#define IS_TIM_CLOCKSOURCE(CLOCK)                                                                                                                                                                \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+  (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || ((CLOCK) == TIM_CLOCKSOURCE_ITR2) \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
+   || ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || ((CLOCK) == TIM_CLOCKSOURCE_TI1) || ((CLOCK) == TIM_CLOCKSOURCE_TI2) || ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
 
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
+#define IS_TIM_CLOCKPOLARITY(POLARITY)                                                                                                                                                  \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+  (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
+   || ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
 
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+  (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) 
 
 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
 
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)      || \
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
-                                          ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
 
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-                                              ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
 
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)   (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) \
-                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+  (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
-                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
 
 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
 
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || ((STATE) == TIM_OSSR_DISABLE))
-                                  ((STATE) == TIM_OSSR_DISABLE))
 
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || ((STATE) == TIM_OSSI_DISABLE))
-                                  ((STATE) == TIM_OSSI_DISABLE))
 
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || ((LEVEL) == TIM_LOCKLEVEL_1) || ((LEVEL) == TIM_LOCKLEVEL_2) || ((LEVEL) == TIM_LOCKLEVEL_3))
-                                  ((LEVEL) == TIM_LOCKLEVEL_1)   || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_2)   || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_3))
 
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || ((STATE) == TIM_BREAK_DISABLE))
-                                   ((STATE) == TIM_BREAK_DISABLE))
 
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
-                                         ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
 
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
-                                              ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
 
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET)  || \
+#define IS_TIM_TRGO_SOURCE(SOURCE)                                                                                                                                                                \
-                                    ((SOURCE) == TIM_TRGO_ENABLE) || \
+  (((SOURCE) == TIM_TRGO_RESET) || ((SOURCE) == TIM_TRGO_ENABLE) || ((SOURCE) == TIM_TRGO_UPDATE) || ((SOURCE) == TIM_TRGO_OC1) || ((SOURCE) == TIM_TRGO_OC1REF) || ((SOURCE) == TIM_TRGO_OC2REF) \
-                                    ((SOURCE) == TIM_TRGO_UPDATE) || \
+   || ((SOURCE) == TIM_TRGO_OC3REF) || ((SOURCE) == TIM_TRGO_OC4REF))
-                                    ((SOURCE) == TIM_TRGO_OC1)    || \
-                                    ((SOURCE) == TIM_TRGO_OC1REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC2REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC3REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC4REF))
 
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+#define IS_TIM_SLAVE_MODE(MODE) \
-                                 ((MODE) == TIM_SLAVEMODE_GATED)   || \
+  (((MODE) == TIM_SLAVEMODE_DISABLE) || ((MODE) == TIM_SLAVEMODE_GATED) || ((MODE) == TIM_SLAVEMODE_RESET) || ((MODE) == TIM_SLAVEMODE_TRIGGER) || ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
-                                 ((MODE) == TIM_SLAVEMODE_RESET)   || \
-                                 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
-                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
 
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
-                                 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
 
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0)    || \
+#define IS_TIM_TRIGGER_SELECTION(SELECTION)                                                                                                                                                          \
-                                             ((SELECTION) == TIM_TS_ITR1)    || \
+  (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3) || ((SELECTION) == TIM_TS_TI1F_ED) || ((SELECTION) == TIM_TS_TI1FP1) \
-                                             ((SELECTION) == TIM_TS_ITR2)    || \
+   || ((SELECTION) == TIM_TS_TI2FP2) || ((SELECTION) == TIM_TS_ETRF))
-                                             ((SELECTION) == TIM_TS_ITR3)    || \
-                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
-                                             ((SELECTION) == TIM_TS_TI1FP1)  || \
-                                             ((SELECTION) == TIM_TS_TI2FP2)  || \
-                                             ((SELECTION) == TIM_TS_ETRF))
 
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) \
-                                                           ((SELECTION) == TIM_TS_ITR1) || \
+  (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3) || ((SELECTION) == TIM_TS_NONE))
-                                                           ((SELECTION) == TIM_TS_ITR2) || \
-                                                           ((SELECTION) == TIM_TS_ITR3) || \
-                                                           ((SELECTION) == TIM_TS_NONE))
 
-#define IS_TIM_TRIGGERPOLARITY(POLARITY)     (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+#define IS_TIM_TRIGGERPOLARITY(POLARITY)                                                                                                                                                        \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+  (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED) || ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || ((POLARITY) == TIM_TRIGGERPOLARITY_RISING) || ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING) \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
+   || ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE))
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
 
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER)  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
 
 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
 
-#define IS_TIM_TI1SELECTION(TI1SELECTION)   (((TI1SELECTION) == TIM_TI1SELECTION_CH1)            || \
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-                                             ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
 
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1)   || \
+#define IS_TIM_DMA_BASE(BASE)                                                                                                                                                                     \
-                               ((BASE) == TIM_DMABASE_CR2)   || \
+  (((BASE) == TIM_DMABASE_CR1) || ((BASE) == TIM_DMABASE_CR2) || ((BASE) == TIM_DMABASE_SMCR) || ((BASE) == TIM_DMABASE_DIER) || ((BASE) == TIM_DMABASE_SR) || ((BASE) == TIM_DMABASE_EGR)        \
-                               ((BASE) == TIM_DMABASE_SMCR)  || \
+   || ((BASE) == TIM_DMABASE_CCMR1) || ((BASE) == TIM_DMABASE_CCMR2) || ((BASE) == TIM_DMABASE_CCER) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) || ((BASE) == TIM_DMABASE_ARR) \
-                               ((BASE) == TIM_DMABASE_DIER)  || \
+   || ((BASE) == TIM_DMABASE_RCR) || ((BASE) == TIM_DMABASE_CCR1) || ((BASE) == TIM_DMABASE_CCR2) || ((BASE) == TIM_DMABASE_CCR3) || ((BASE) == TIM_DMABASE_CCR4) || ((BASE) == TIM_DMABASE_BDTR) \
-                               ((BASE) == TIM_DMABASE_SR)    || \
+   || ((BASE) == TIM_DMABASE_DCR))
-                               ((BASE) == TIM_DMABASE_EGR)   || \
-                               ((BASE) == TIM_DMABASE_CCMR1) || \
-                               ((BASE) == TIM_DMABASE_CCMR2) || \
-                               ((BASE) == TIM_DMABASE_CCER)  || \
-                               ((BASE) == TIM_DMABASE_CNT)   || \
-                               ((BASE) == TIM_DMABASE_PSC)   || \
-                               ((BASE) == TIM_DMABASE_ARR)   || \
-                               ((BASE) == TIM_DMABASE_RCR)   || \
-                               ((BASE) == TIM_DMABASE_CCR1)  || \
-                               ((BASE) == TIM_DMABASE_CCR2)  || \
-                               ((BASE) == TIM_DMABASE_CCR3)  || \
-                               ((BASE) == TIM_DMABASE_CCR4)  || \
-                               ((BASE) == TIM_DMABASE_BDTR)  || \
-                               ((BASE) == TIM_DMABASE_DCR))
 
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
+#define IS_TIM_DMA_LENGTH(LENGTH)                                                                                                                                                                  \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
+  (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS)         \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
+   || ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS)     \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
+   || ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS)  \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
+   || ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
+   || ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
 
 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
 
@@ -1116,10 +1003,10 @@ typedef struct
  * @retval None
  */
 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)                               \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+  (((__CHANNEL__) == TIM_CHANNEL_1)                                                                \
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+       ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__))                                            \
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+       : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+                                          : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
 
 /** @brief Reset TIM IC prescaler
  * @param  __HANDLE__: TIM handle
@@ -1127,11 +1014,10 @@ typedef struct
  * @retval None
  */
 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)                                      \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+  (((__CHANNEL__) == TIM_CHANNEL_1)                                                              \
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+       ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC)                                    \
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+       : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+                                          : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
 
 /** @brief Set TIM IC polarity
  * @param  __HANDLE__: TIM handle
@@ -1140,10 +1026,10 @@ typedef struct
  * @retval None
  */
 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)                                                                                               \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__))                                                                               \
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+                                    : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U))                                    \
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+                                                                       : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) \
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
+                                                                                                          : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
 
 /** @brief Reset TIM IC polarity
  * @param  __HANDLE__: TIM handle
@@ -1151,10 +1037,10 @@ typedef struct
  * @retval None
  */
 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)                                                                                                                                 \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t) ~(TIM_CCER_CC1P | TIM_CCER_CC1NP))                                                                       \
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+                                    : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t) ~(TIM_CCER_CC2P | TIM_CCER_CC2NP))                                    \
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+                                                                       : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t) ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) \
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
+                                                                                                          : ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
 
 /**
  * @}
@@ -1207,10 +1093,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat
  */
 #define __HAL_TIM_DISABLE(__HANDLE__)                                   \
   do {                                                                  \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) {    \
-                            { \
+      if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
-                            { \
         (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN);                  \
       }                                                                 \
     }                                                                   \
@@ -1225,10 +1109,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat
  */
 #define __HAL_TIM_MOE_DISABLE(__HANDLE__)                               \
   do {                                                                  \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) {    \
-                          { \
+      if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
-                            { \
         (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE);                \
       }                                                                 \
     }                                                                   \
@@ -1396,8 +1278,7 @@ mode.
  * @param  __COMPARE__: specifies the Capture Compare register new value.
  * @retval None
  */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
 
 /**
  * @brief  Gets the TIM Capture Compare Register value on runtime
@@ -1410,8 +1291,7 @@ mode.
  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
  */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
-  (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
 
 /**
  * @brief  Sets the TIM Counter Register value on runtime.
@@ -1426,8 +1306,7 @@ mode.
  * @param  __HANDLE__: TIM handle.
  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
  */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
-   ((__HANDLE__)->Instance->CNT)
 
 /**
  * @brief  Sets the TIM Autoreload Register value on runtime without calling
@@ -1447,8 +1326,7 @@ mode.
  * @param  __HANDLE__: TIM handle.
  * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
  */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
-   ((__HANDLE__)->Instance->ARR)
 
 /**
  * @brief  Sets the TIM Clock Division value on runtime without calling
@@ -1476,8 +1354,7 @@ mode.
  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
  */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-   ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
 
 /**
  * @brief  Sets the TIM Input Capture prescaler on runtime without calling
@@ -1519,10 +1396,10 @@ mode.
  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
  */
 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)                                             \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+  (((__CHANNEL__) == TIM_CHANNEL_1)                                                                    \
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+       ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC)                                            \
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+       : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \
-   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+                                          : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
 
 /**
  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register
@@ -1532,8 +1409,7 @@ mode.
  *        enabled)
  * @retval None
  */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= (TIM_CR1_URS))
-    ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
 
 /**
  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register
@@ -1546,8 +1422,7 @@ mode.
  *          (+) Update generation through the slave mode controller
  * @retval None
  */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_URS))
-      ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
 
 /**
  * @brief  Sets the TIM Capture x input polarity on runtime.
@@ -1730,11 +1605,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
 uint32_t          HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h

@@ -57,13 +57,11 @@
  * @{
  */
 
-
 /**
  * @brief  TIM Hall sensor Configuration Structure definition
  */
 
-typedef struct
+typedef struct {
-{
 
   uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -77,16 +75,12 @@ typedef struct
                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
 } TIM_HallSensor_InitTypeDef;
 
-
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
 
 /**
  * @brief  TIM Break and Dead time configuration Structure definition
  */
-typedef struct
+typedef struct {
-{
   uint32_t OffStateRunMode;  /*!< TIM off state in run mode
                                 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
   uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
@@ -122,9 +116,7 @@ typedef struct {
  */
 
 /* Exported constants --------------------------------------------------------*/
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
  * @{
  */
@@ -157,10 +149,10 @@ typedef struct {
  * @retval None
  */
 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)                                   \
-        (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+  (((__CHANNEL__) == TIM_CHANNEL_1)                                                            \
-         ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+       ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE)                                    \
-         ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+       : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
-         ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+                                          : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
 
 /**
  * @brief  Resets the TIM Output compare preload.
@@ -174,10 +166,10 @@ typedef struct {
  * @retval None
  */
 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)                                                                                                             \
-        (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE)                                                                       \
-         ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
+                                    : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE)                                    \
-         ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
+                                                                       : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) \
-         ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
+                                                                                                          : ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup TIMEx_Exported_Functions
@@ -207,9 +199,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
  * @}
  */
 
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
 
 /** @addtogroup TIMEx_Exported_Functions_Group2
  * @{
@@ -270,9 +260,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
  * @{
  */
 /* Extended Control functions  ************************************************/
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
@@ -295,9 +283,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
  * @}
  */
 
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
 /** @addtogroup TIMEx_Exported_Functions_Group7
  * @{
  */
@@ -337,7 +323,6 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
 }
 #endif
 
-
 #endif /* __STM32F1xx_HAL_TIM_EX_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c

@@ -75,10 +75,7 @@
 #define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
 #define __STM32F1xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8]  sub2 version */
 #define __STM32F1xx_HAL_VERSION_RC   (0x00U) /*!< [7:0]  release candidate */
-#define __STM32F1xx_HAL_VERSION         ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
+#define __STM32F1xx_HAL_VERSION      ((__STM32F1xx_HAL_VERSION_MAIN << 24) | (__STM32F1xx_HAL_VERSION_SUB1 << 16) | (__STM32F1xx_HAL_VERSION_SUB2 << 8) | (__STM32F1xx_HAL_VERSION_RC))
-                                        |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
-                                        |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
-                                        |(__STM32F1xx_HAL_VERSION_RC))
 
 #define IDCODE_DEVID_MASK 0x00000FFFU
 
@@ -155,14 +152,11 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
  *         to have correct HAL operation.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_Init(void)
+HAL_StatusTypeDef HAL_Init(void) {
-{
   /* Configure Flash prefetch */
 #if (PREFETCH_ENABLE != 0)
-#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
+#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
-    defined(STM32F102x6) || defined(STM32F102xB) || \
+    || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
-    defined(STM32F105xC) || defined(STM32F107xC)
 
   /* Prefetch buffer is not available on value line devices */
   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
@@ -188,8 +182,7 @@ HAL_StatusTypeDef HAL_Init(void)
  * @note This function is optional.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_DeInit(void)
+HAL_StatusTypeDef HAL_DeInit(void) {
-{
   /* Reset of all peripherals */
   __HAL_RCC_APB1_FORCE_RESET();
   __HAL_RCC_APB1_RELEASE_RESET();
@@ -213,8 +206,7 @@ HAL_StatusTypeDef HAL_DeInit(void)
  * @brief  Initialize the MSP.
  * @retval None
  */
-__weak void HAL_MspInit(void)
+__weak void HAL_MspInit(void) {
-{
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_MspInit could be implemented in the user file
    */
@@ -224,8 +216,7 @@ __weak void HAL_MspInit(void)
  * @brief  DeInitializes the MSP.
  * @retval None
  */
-__weak void HAL_MspDeInit(void)
+__weak void HAL_MspDeInit(void) {
-{
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_MspDeInit could be implemented in the user file
    */
@@ -247,22 +238,17 @@ __weak void HAL_MspDeInit(void)
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
-{
   /* Configure the SysTick to have interrupt in 1ms time basis*/
-  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) {
-  {
     return HAL_ERROR;
   }
 
   /* Configure the SysTick IRQ priority */
-  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS)) {
-  {
     HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
     uwTickPrio = TickPriority;
-  }
+  } else {
-  else
-  {
     return HAL_ERROR;
   }
 
@@ -306,10 +292,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
  *      implementations in user file.
  * @retval None
  */
-__weak void HAL_IncTick(void)
+__weak void HAL_IncTick(void) { uwTick += uwTickFreq; }
-{
-  uwTick += uwTickFreq;
-}
 
 /**
  * @brief Provides a tick value in millisecond.
@@ -317,31 +300,23 @@ __weak void HAL_IncTick(void)
  *       implementations in user file.
  * @retval tick value
  */
-__weak uint32_t HAL_GetTick(void)
+__weak uint32_t HAL_GetTick(void) { return uwTick; }
-{
-  return uwTick;
-}
 
 /**
  * @brief This function returns a tick priority.
  * @retval tick priority
  */
-uint32_t HAL_GetTickPrio(void)
+uint32_t HAL_GetTickPrio(void) { return uwTickPrio; }
-{
-  return uwTickPrio;
-}
 
 /**
  * @brief Set new tick Freq.
  * @retval Status
  */
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) {
-{
   HAL_StatusTypeDef status = HAL_OK;
   assert_param(IS_TICKFREQ(Freq));
 
-  if (uwTickFreq != Freq)
+  if (uwTickFreq != Freq) {
-  {
     uwTickFreq = Freq;
 
     /* Apply the new tick Freq  */
@@ -355,10 +330,7 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
  * @brief Return tick frequency.
  * @retval tick period in Hz
  */
-HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+HAL_TickFreqTypeDef HAL_GetTickFreq(void) { return uwTickFreq; }
-{
-  return uwTickFreq;
-}
 
 /**
  * @brief This function provides minimum delay (in milliseconds) based
@@ -371,20 +343,16 @@ HAL_TickFreqTypeDef HAL_GetTickFreq(void)
  * @param Delay specifies the delay time length, in milliseconds.
  * @retval None
  */
-__weak void HAL_Delay(uint32_t Delay)
+__weak void HAL_Delay(uint32_t Delay) {
-{
   uint32_t tickstart = HAL_GetTick();
   uint32_t wait      = Delay;
 
   /* Add a freq to guarantee minimum wait */
-  if (wait < HAL_MAX_DELAY)
+  if (wait < HAL_MAX_DELAY) {
-  {
     wait += (uint32_t)(uwTickFreq);
   }
 
-  while ((HAL_GetTick() - tickstart) < wait)
+  while ((HAL_GetTick() - tickstart) < wait) {}
-  {
-  }
 }
 
 /**
@@ -397,8 +365,7 @@ __weak void HAL_Delay(uint32_t Delay)
  *       implementations in user file.
  * @retval None
  */
-__weak void HAL_SuspendTick(void)
+__weak void HAL_SuspendTick(void) {
-{
   /* Disable SysTick Interrupt */
   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
 }
@@ -413,8 +380,7 @@ __weak void HAL_SuspendTick(void)
  *       implementations in user file.
  * @retval None
  */
-__weak void HAL_ResumeTick(void)
+__weak void HAL_ResumeTick(void) {
-{
   /* Enable SysTick Interrupt */
   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
 }
@@ -423,10 +389,7 @@ __weak void HAL_ResumeTick(void)
  * @brief  Returns the HAL revision
  * @retval version 0xXYZR (8bits for each decimal, R for RC)
  */
-uint32_t HAL_GetHalVersion(void)
+uint32_t HAL_GetHalVersion(void) { return __STM32F1xx_HAL_VERSION; }
-{
-  return __STM32F1xx_HAL_VERSION;
-}
 
 /**
  * @brief Returns the device revision identifier.
@@ -439,10 +402,7 @@ uint32_t HAL_GetHalVersion(void)
  *       Refer to errata sheet of these devices for more details.
  * @retval Device revision identifier
  */
-uint32_t HAL_GetREVID(void)
+uint32_t HAL_GetREVID(void) { return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); }
-{
-  return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
 
 /**
  * @brief  Returns the device identifier.
@@ -455,19 +415,13 @@ uint32_t HAL_GetREVID(void)
  *       Refer to errata sheet of these devices for more details.
  * @retval Device identifier
  */
-uint32_t HAL_GetDEVID(void)
+uint32_t HAL_GetDEVID(void) { return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); }
-{
-  return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
 
 /**
  * @brief  Enable the Debug Module during SLEEP mode
  * @retval None
  */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
+void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); }
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
 
 /**
  * @brief  Disable the Debug Module during SLEEP mode
@@ -480,10 +434,7 @@ void HAL_DBGMCU_EnableDBGSleepMode(void)
  *       Refer to errata sheet of these devices for more details.
  * @retval None
  */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
+void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); }
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
 
 /**
  * @brief  Enable the Debug Module during STOP mode
@@ -510,10 +461,7 @@ void HAL_DBGMCU_DisableDBGSleepMode(void)
  *       Refer to errata sheet of these devices for more details.
  * @retval None
  */
-void HAL_DBGMCU_EnableDBGStopMode(void)
+void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); }
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
 
 /**
  * @brief  Disable the Debug Module during STOP mode
@@ -526,10 +474,7 @@ void HAL_DBGMCU_EnableDBGStopMode(void)
  *       Refer to errata sheet of these devices for more details.
  * @retval None
  */
-void HAL_DBGMCU_DisableDBGStopMode(void)
+void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); }
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
 
 /**
  * @brief  Enable the Debug Module during STANDBY mode
@@ -542,10 +487,7 @@ void HAL_DBGMCU_DisableDBGStopMode(void)
  *       Refer to errata sheet of these devices for more details.
  * @retval None
  */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
+void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); }
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
 
 /**
  * @brief  Disable the Debug Module during STANDBY mode
@@ -558,18 +500,14 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void)
  *       Refer to errata sheet of these devices for more details.
  * @retval None
  */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
+void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); }
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
 
 /**
  * @brief Return the unique device identifier (UID based on 96 bits)
  * @param UID pointer to 3 words array.
  * @retval Device identifier
  */
-void HAL_GetUID(uint32_t *UID)
+void HAL_GetUID(uint32_t *UID) {
-{
   UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
   UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
   UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c

@@ -139,8 +139,7 @@
  * @param  hadc: ADC handle
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) {
-{
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
   uint32_t          tickstart;
   __IO uint32_t     wait_loop_index = 0U;
@@ -159,22 +158,16 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 
   /* Check if ADC is effectively disabled */
-  if (tmp_hal_status == HAL_OK)
+  if (tmp_hal_status == HAL_OK) {
-  {
     /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL);
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_BUSY_INTERNAL);
 
     /* Hardware prerequisite: delay before starting the calibration.          */
     /*  - Computation of CPU clock cycles corresponding to ADC clock cycles.  */
     /*  - Wait for the expected ADC clock cycles delay */
-    wait_loop_index = ((SystemCoreClock
+    wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES);
-                        / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
-                       * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES        );
 
-    while(wait_loop_index != 0U)
+    while (wait_loop_index != 0U) {
-    {
       wait_loop_index--;
     }
 
@@ -187,14 +180,10 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
     tickstart = HAL_GetTick();
 
     /* Wait for calibration reset completion */
-    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
+    while (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) {
-    {
+      if ((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) {
-      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
-      {
         /* Update ADC state machine to error */
-        ADC_STATE_CLR_SET(hadc->State,
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
-                          HAL_ADC_STATE_BUSY_INTERNAL,
-                          HAL_ADC_STATE_ERROR_INTERNAL);
 
         /* Process unlocked */
         __HAL_UNLOCK(hadc);
@@ -203,21 +192,16 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
       }
     }
 
-    
     /* 4. Start ADC calibration */
     SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
 
     tickstart = HAL_GetTick();
 
     /* Wait for calibration completion */
-    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
+    while (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) {
-    {
+      if ((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) {
-      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
-      {
         /* Update ADC state machine to error */
-        ADC_STATE_CLR_SET(hadc->State,
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
-                          HAL_ADC_STATE_BUSY_INTERNAL,
-                          HAL_ADC_STATE_ERROR_INTERNAL);
 
         /* Process unlocked */
         __HAL_UNLOCK(hadc);
@@ -227,9 +211,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
     }
 
     /* Set ADC state */
-    ADC_STATE_CLR_SET(hadc->State,
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
-                      HAL_ADC_STATE_BUSY_INTERNAL,
-                      HAL_ADC_STATE_READY);
   }
 
   /* Process unlocked */
@@ -245,8 +227,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
  * @param  hadc: ADC handle
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) {
-{
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 
   /* Check the parameters */
@@ -259,23 +240,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
   tmp_hal_status = ADC_Enable(hadc);
 
   /* Start conversion if ADC is effectively enabled */
-  if (tmp_hal_status == HAL_OK)
+  if (tmp_hal_status == HAL_OK) {
-  {
     /* Set ADC state                                                          */
     /* - Clear state bitfield related to injected group conversion results    */
     /* - Set state bitfield related to injected operation                     */
-    ADC_STATE_CLR_SET(hadc->State,
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
-                      HAL_ADC_STATE_INJ_BUSY);
 
     /* Case of independent mode or multimode (for devices with several ADCs): */
     /* Set multimode state.                                                   */
-    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
-    {
       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-    }
+    } else {
-    else
-    {
       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
     }
 
@@ -283,8 +258,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
     /* Note: On this device, there is no ADC error code fields related to     */
     /*       conversions on group injected only. In case of conversion on     */
     /*       going on group regular, no error code is reset.                  */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) {
-    {
       /* Reset ADC all error code fields */
       ADC_CLEAR_ERRORCODE(hadc);
     }
@@ -307,23 +281,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
     /* Case of multimode enabled (for devices with several ADCs): if ADC is   */
     /* slave, ADC is enabled only (conversion is not started). If ADC is      */
     /* master, ADC is enabled and conversion is started.                      */
-    if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
+    if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) {
-    {
+      if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
-      if (ADC_IS_SOFTWARE_START_INJECTED(hadc)     &&
-          ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
-      {
         /* Start ADC conversion on injected group with SW start */
         SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
-      }
+      } else {
-      else
-      {
         /* Start ADC conversion on injected group with external trigger */
         SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
       }
     }
-  }
+  } else {
-  else
-  {
     /* Process unlocked */
     __HAL_UNLOCK(hadc);
   }
@@ -344,8 +311,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
  * @param  hadc: ADC handle
  * @retval None
  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) {
-{
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 
   /* Check the parameters */
@@ -360,24 +326,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
   /*   continue (injected and regular groups stop conversion and ADC disable  */
   /*   are common)                                                            */
   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
-  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
+  if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) {
-     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
-  {
     /* Stop potential conversion on going, on regular and injected groups */
     /* Disable ADC peripheral */
     tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 
     /* Check if ADC is effectively disabled */
-    if (tmp_hal_status == HAL_OK)
+    if (tmp_hal_status == HAL_OK) {
-    {
       /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
+      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
-                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                        HAL_ADC_STATE_READY);
     }
-  }
+  } else {
-  else
-  {
     /* Update ADC state machine to error */
     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 
@@ -397,8 +356,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
  * @param  Timeout: Timeout value in millisecond.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) {
-{
   uint32_t tickstart;
 
   /* Variables for polling in case of scan mode enabled and polling for each  */
@@ -428,16 +386,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
   /*    settings, conversion time range can be from 28 to 32256 CPU cycles).  */
   /*    As flag JEOC is not set after each conversion, no timeout status can  */
   /*    be set.                                                               */
-  if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
+  if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) {
-  {
     /* Wait until End of Conversion flag is raised */
-    while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
+    while (HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) {
-    {
       /* Check if timeout is disabled (set to infinite wait) */
-      if(Timeout != HAL_MAX_DELAY)
+      if (Timeout != HAL_MAX_DELAY) {
-      {
+        if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
-        if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
-        {
           /* Update ADC state machine to timeout */
           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
 
@@ -448,24 +402,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
         }
       }
     }
-  }
+  } else {
-  else
-  {
     /* Replace polling by wait for maximum conversion time */
     /*  - Computation of CPU clock cycles corresponding to ADC clock cycles   */
     /*    and ADC maximum conversion cycles on all channels.                  */
     /*  - Wait for the expected ADC clock cycles delay                        */
-    Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
+    Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_CONVCYCLES_MAX_RANGE(hadc));
-                                          / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
-                                         * ADC_CONVCYCLES_MAX_RANGE(hadc)                 );
 
-    while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
+    while (Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) {
-    {
       /* Check if timeout is disabled (set to infinite wait) */
-      if(Timeout != HAL_MAX_DELAY)
+      if (Timeout != HAL_MAX_DELAY) {
-      {
+        if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
           /* Update ADC state machine to timeout */
           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
 
@@ -490,16 +437,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
   /* Determine whether any further conversion upcoming on group injected      */
   /* by external trigger or by automatic injected conversion                  */
   /* from group regular.                                                      */
-  if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     || 
+  if (ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)))) {
-     (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&     
-     (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
-      (hadc->Init.ContinuousConvMode == DISABLE)   )        )   )
-  {
     /* Set ADC state */
     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
 
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) {
-    {
       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
     }
   }
@@ -515,8 +457,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
  * @param  hadc: ADC handle
  * @retval HAL status.
  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) {
-{
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 
   /* Check the parameters */
@@ -529,23 +470,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
   tmp_hal_status = ADC_Enable(hadc);
 
   /* Start conversion if ADC is effectively enabled */
-  if (tmp_hal_status == HAL_OK)
+  if (tmp_hal_status == HAL_OK) {
-  {
     /* Set ADC state                                                          */
     /* - Clear state bitfield related to injected group conversion results    */
     /* - Set state bitfield related to injected operation                     */
-    ADC_STATE_CLR_SET(hadc->State,
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
-                      HAL_ADC_STATE_INJ_BUSY);
 
     /* Case of independent mode or multimode (for devices with several ADCs): */
     /* Set multimode state.                                                   */
-    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
-    {
       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
-    }
+    } else {
-    else
-    {
       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
     }
 
@@ -553,8 +488,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
     /* Note: On this device, there is no ADC error code fields related to     */
     /*       conversions on group injected only. In case of conversion on     */
     /*       going on group regular, no error code is reset.                  */
-    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) {
-    {
       /* Reset ADC all error code fields */
       ADC_CLEAR_ERRORCODE(hadc);
     }
@@ -577,23 +511,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
     /* trigger event.                                                         */
     /* If automatic injected conversion is enabled, conversion will start     */
     /* after next regular group conversion.                                   */
-    if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
+    if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) {
-    {
+      if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
-      if (ADC_IS_SOFTWARE_START_INJECTED(hadc)     &&
-          ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
-      {
         /* Start ADC conversion on injected group with SW start */
         SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
-      }
+      } else {
-      else
-      {
         /* Start ADC conversion on injected group with external trigger */
         SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
       }
     }
-  }
+  } else {
-  else
-  {
     /* Process unlocked */
     __HAL_UNLOCK(hadc);
   }
@@ -614,8 +541,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
  * @param  hadc: ADC handle
  * @retval None
  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) {
-{
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 
   /* Check the parameters */
@@ -630,27 +556,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
   /*   continue (injected and regular groups stop conversion and ADC disable  */
   /*   are common)                                                            */
   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
-  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
+  if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) {
-     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
-  {
     /* Stop potential conversion on going, on regular and injected groups */
     /* Disable ADC peripheral */
     tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 
     /* Check if ADC is effectively disabled */
-    if (tmp_hal_status == HAL_OK)
+    if (tmp_hal_status == HAL_OK) {
-    {
       /* Disable ADC end of conversion interrupt for injected channels */
       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
 
       /* Set ADC state */
-      ADC_STATE_CLR_SET(hadc->State,
+      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
-                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                        HAL_ADC_STATE_READY);
     }
-  }
+  } else {
-  else
-  {
     /* Update ADC state machine to error */
     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 
@@ -683,8 +602,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
  * @retval None
  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) {
-{
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
   ADC_HandleTypeDef tmphadcSlave;
 
@@ -702,8 +620,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
   /* conversion trigger ADC_SOFTWARE_START.                                   */
   /* Note: External trigger of ADC slave must be enabled, it is already done  */
   /*       into function "HAL_ADC_Init()".                                    */
-  if(!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave))  
+  if (!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) {
-  {
     /* Update ADC state machine to error */
     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 
@@ -716,25 +633,20 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
   /* Enable the ADC peripherals: master and slave (in case if not already     */
   /* enabled previously)                                                      */
   tmp_hal_status = ADC_Enable(hadc);
-  if (tmp_hal_status == HAL_OK)
+  if (tmp_hal_status == HAL_OK) {
-  {
     tmp_hal_status = ADC_Enable(&tmphadcSlave);
   }
 
   /* Start conversion if all ADCs of multimode are effectively enabled */
-  if (tmp_hal_status == HAL_OK)
+  if (tmp_hal_status == HAL_OK) {
-  {
     /* Set ADC state (ADC master)                                             */
     /* - Clear state bitfield related to regular group conversion results     */
     /* - Set state bitfield related to regular operation                      */
-    ADC_STATE_CLR_SET(hadc->State,
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_REG_BUSY);
-                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE,
-                      HAL_ADC_STATE_REG_BUSY);
 
     /* If conversions on group regular are also triggering group injected,    */
     /* update ADC state.                                                      */
-    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) {
-    {
       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
     }
 
@@ -746,7 +658,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
     /* Set ADC error code to none */
     ADC_CLEAR_ERRORCODE(hadc);
 
-    
     /* Set the DMA transfer complete callback */
     hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
 
@@ -756,7 +667,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
     /* Set the DMA error callback */
     hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
 
-    
     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
     /* start (in case of SW start):                                           */
 
@@ -775,19 +685,14 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
     /* trigger event.                                                         */
     /* Note: Alternate trigger for single conversion could be to force an     */
     /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
-    if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+    if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) {
-    {
       /* Start ADC conversion on regular group with SW start */
       SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
-    }
+    } else {
-    else
-    {
       /* Start ADC conversion on regular group with external trigger */
       SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
     }
-  }
+  } else {
-  else
-  {
     /* Process unlocked */
     __HAL_UNLOCK(hadc);
   }
@@ -809,8 +714,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
  * @retval None
  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) {
-{
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
   ADC_HandleTypeDef tmphadcSlave;
 
@@ -820,14 +724,12 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
   /* Process locked */
   __HAL_LOCK(hadc);
 
- 
   /* Stop potential conversion on going, on regular and injected groups */
   /* Disable ADC master peripheral */
   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 
   /* Check if ADC is effectively disabled */
-  if(tmp_hal_status == HAL_OK)
+  if (tmp_hal_status == HAL_OK) {
-  {
     /* Set a temporary handle of the ADC slave associated to the ADC master   */
     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
 
@@ -835,8 +737,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
     tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
 
     /* Check if ADC is effectively disabled */
-    if(tmp_hal_status != HAL_OK)
+    if (tmp_hal_status != HAL_OK) {
-    {
       /* Update ADC state machine to error */
       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 
@@ -857,9 +758,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
 
     /* Change ADC state (ADC master) */
-    ADC_STATE_CLR_SET(hadc->State,
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
-                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
-                      HAL_ADC_STATE_READY);
   }
 
   /* Process unlocked */
@@ -898,8 +797,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
  *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
  * @retval ADC group injected conversion data
  */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) {
-{
   uint32_t tmp_jdr = 0U;
 
   /* Check the parameters */
@@ -907,8 +805,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
 
   /* Get ADC converted value */
-  switch(InjectedRank)
+  switch (InjectedRank) {
-  {  
   case ADC_INJECTED_RANK_4:
     tmp_jdr = hadc->Instance->JDR4;
     break;
@@ -935,8 +832,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
  * @retval The converted data value.
  */
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) {
-{
   uint32_t tmpDR = 0U;
 
   /* Check the parameters */
@@ -952,8 +848,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
   /* only if ADC1 DMA mode is enabled.                                        */
   tmpDR = hadc->Instance->DR;
 
-  if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA))
+  if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA)) {
-  {
     tmpDR |= (ADC2->DR << 16U);
   }
 
@@ -967,8 +862,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
  * @param  hadc: ADC handle
  * @retval None
  */
-__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) {
-{
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
@@ -1009,8 +903,7 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
  *         injected group.
  * @retval None
  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) {
-{
   HAL_StatusTypeDef tmp_hal_status  = HAL_OK;
   __IO uint32_t     wait_loop_index = 0U;
 
@@ -1022,8 +915,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
   assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
   assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
 
-  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) {
-  {
     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
@@ -1071,31 +963,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
     /* Since injected channels rank conv. order depends on total number of   */
     /* injected conversions, selected rank must be below or equal to total   */
     /* number of injected conversions to be updated.                         */
-    if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
+    if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) {
-    {
       /* Clear the old SQx bits for the selected rank */
       /* Set the SQx bits for the selected rank */
       MODIFY_REG(hadc->Instance->JSQR,
 
-                 ADC_JSQR_JL                                               |
+                 ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion),
-                 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,                         
-                                  sConfigInjected->InjectedRank,         
-                                  sConfigInjected->InjectedNbrOfConversion)   ,
 
-                 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
+                 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion)
-                 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,      
+                     | ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion));
-                                  sConfigInjected->InjectedRank,         
+    } else {
-                                  sConfigInjected->InjectedNbrOfConversion)    );
-    }
-    else
-    {
       /* Clear the old SQx bits for the selected rank */
       MODIFY_REG(hadc->Instance->JSQR,
 
-                 ADC_JSQR_JL                                               |
+                 ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion),
-                 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,                         
-                                  sConfigInjected->InjectedRank,         
-                                  sConfigInjected->InjectedNbrOfConversion) ,
 
                  0x00000000U);
     }
@@ -1110,29 +991,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
   /*  - Injected discontinuous mode                                           */
   /* Note: In case of ADC already enabled, caution to not launch an unwanted  */
   /*       conversion while modifying register CR2 by writing 1 to bit ADON.  */
-  if (ADC_IS_ENABLE(hadc) == RESET)
+  if (ADC_IS_ENABLE(hadc) == RESET) {
-  {    
+    MODIFY_REG(hadc->Instance->CR2, ADC_CR2_JEXTSEL | ADC_CR2_ADON, ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv));
-    MODIFY_REG(hadc->Instance->CR2                                           ,
-               ADC_CR2_JEXTSEL |
-               ADC_CR2_ADON                                                  ,
-               ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) );
   }
 
-  
   /* Configuration of injected group                                          */
   /*  - Automatic injected conversion                                         */
   /*  - Injected discontinuous mode                                           */
 
   /* Automatic injected conversion can be enabled if injected group         */
   /* external triggers are disabled.                                        */
-    if (sConfigInjected->AutoInjectedConv == ENABLE)
+  if (sConfigInjected->AutoInjectedConv == ENABLE) {
-    {
+    if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) {
-      if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
-      {
       SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      }
+    } else {
-      else
-      {
       /* Update ADC state machine to error */
       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 
@@ -1142,14 +1014,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
 
   /* Injected discontinuous can be enabled only if auto-injected mode is    */
   /* disabled.                                                              */
-    if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
+  if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) {
-    {
+    if (sConfigInjected->AutoInjectedConv == DISABLE) {
-      if (sConfigInjected->AutoInjectedConv == DISABLE)
-      {
       SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
-      } 
+    } else {
-      else
-      {
       /* Update ADC state machine to error */
       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 
@@ -1157,88 +1025,61 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
     }
   }
 
-
   /* InjectedChannel sampling time configuration */
   /* For channels 10 to 17 */
-  if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
+  if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) {
+    MODIFY_REG(hadc->Instance->SMPR1, ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel), ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel));
+  } else /* For channels 0 to 9 */
   {
-    MODIFY_REG(hadc->Instance->SMPR1                                                             ,
+    MODIFY_REG(hadc->Instance->SMPR2, ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel), ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel));
-               ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel)                      ,
-               ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
-  }
-  else /* For channels 0 to 9 */
-  {
-    MODIFY_REG(hadc->Instance->SMPR2                                                             ,
-               ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel)                       ,
-               ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
   }
 
   /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor  */
   /* and VREFINT measurement path.                                            */
-  if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
+  if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)) {
-      (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
-  {
     SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
   }
 
-  
   /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
-  switch(sConfigInjected->InjectedRank)
+  switch (sConfigInjected->InjectedRank) {
-  {
   case 1:
     /* Set injected channel 1 offset */
-      MODIFY_REG(hadc->Instance->JOFR1,
+    MODIFY_REG(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1, sConfigInjected->InjectedOffset);
-                 ADC_JOFR1_JOFFSET1,
-                 sConfigInjected->InjectedOffset);
     break;
   case 2:
     /* Set injected channel 2 offset */
-      MODIFY_REG(hadc->Instance->JOFR2,
+    MODIFY_REG(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2, sConfigInjected->InjectedOffset);
-                 ADC_JOFR2_JOFFSET2,
-                 sConfigInjected->InjectedOffset);
     break;
   case 3:
     /* Set injected channel 3 offset */
-      MODIFY_REG(hadc->Instance->JOFR3,
+    MODIFY_REG(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3, sConfigInjected->InjectedOffset);
-                 ADC_JOFR3_JOFFSET3,
-                 sConfigInjected->InjectedOffset);
     break;
   case 4:
   default:
-      MODIFY_REG(hadc->Instance->JOFR4,
+    MODIFY_REG(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4, sConfigInjected->InjectedOffset);
-                 ADC_JOFR4_JOFFSET4,
-                 sConfigInjected->InjectedOffset);
     break;
   }
 
   /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
   /* and VREFINT measurement path.                                            */
-  if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
+  if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)) {
-      (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
-  {
     /* For STM32F1 devices with several ADC: Only ADC1 can access internal    */
     /* measurement channels (VrefInt/TempSensor). If these channels are       */
     /* intended to be set on other ADC instances, an error is reported.       */
-    if (hadc->Instance == ADC1)
+    if (hadc->Instance == ADC1) {
-    {
+      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) {
-      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
-      {
         SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 
-        if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
+        if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) {
-        {
           /* Delay for temperature sensor stabilization time */
           /* Compute number of CPU cycles to wait for */
           wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
-          while(wait_loop_index != 0U)
+          while (wait_loop_index != 0U) {
-          {
             wait_loop_index--;
           }
         }
       }
-    }
+    } else {
-    else
-    {
       /* Update ADC state machine to error */
       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 
@@ -1270,8 +1111,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
  * @param  multimode: Structure of ADC multimode configuration
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) {
-{
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
   ADC_HandleTypeDef tmphadcSlave;
 
@@ -1293,25 +1133,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
   /*  - Multimode mode selection                                              */
   /* To optimize code, all multimode settings can be set when both ADCs of    */
   /* the common group are in state: disabled.                                 */
-  if ((ADC_IS_ENABLE(hadc) == RESET)                     &&
+  if ((ADC_IS_ENABLE(hadc) == RESET) && (ADC_IS_ENABLE(&tmphadcSlave) == RESET) && (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance))) {
-      (ADC_IS_ENABLE(&tmphadcSlave) == RESET)            &&
+    MODIFY_REG(hadc->Instance->CR1, ADC_CR1_DUALMOD, multimode->Mode);
-      (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance))   )
-  {
-    MODIFY_REG(hadc->Instance->CR1,
-               ADC_CR1_DUALMOD    ,
-               multimode->Mode     );
   }
   /* If one of the ADC sharing the same common group is enabled, no update    */
   /* could be done on neither of the multimode structure parameters.          */
-  else
+  else {
-  {
     /* Update ADC state machine to error */
     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 
     tmp_hal_status = HAL_ERROR;
   }
 
-    
   /* Process unlocked */
   __HAL_UNLOCK(hadc);
 

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c

@@ -120,7 +120,6 @@
  * @{
  */
 
-
 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
   *  @brief    Initialization and Configuration functions
   *
@@ -136,7 +135,6 @@
   * @{
   */
 
-
 /**
  * @brief  Sets the priority grouping field (preemption priority and subpriority)
  *         using the required unlock sequence.
@@ -156,8 +154,7 @@
  *         The pending IRQ priority will be managed only by the subpriority.
  * @retval None
  */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
-{
   /* Check the parameters */
   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
 
@@ -178,8 +175,7 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  *         A lower priority value indicates a higher priority.
  * @retval None
  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) {
-{ 
   uint32_t prioritygroup = 0x00U;
 
   /* Check the parameters */
@@ -200,8 +196,7 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
  * @retval None
  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) {
-{
   /* Check the parameters */
   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 
@@ -216,8 +211,7 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
  * @retval None
  */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) {
-{
   /* Check the parameters */
   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 
@@ -229,8 +223,7 @@ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
  * @brief  Initiates a system reset request to reset the MCU.
  * @retval None
  */
-void HAL_NVIC_SystemReset(void)
+void HAL_NVIC_SystemReset(void) {
-{
   /* System Reset */
   NVIC_SystemReset();
 }
@@ -242,10 +235,7 @@ void HAL_NVIC_SystemReset(void)
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); }
-{
-   return SysTick_Config(TicksNumb);
-}
 /**
  * @}
  */
@@ -271,8 +261,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
  * @brief  Disables the MPU
  * @retval None
  */
-void HAL_MPU_Disable(void)
+void HAL_MPU_Disable(void) {
-{
   /* Make sure outstanding transfers are done */
   __DMB();
 
@@ -294,8 +283,7 @@ void HAL_MPU_Disable(void)
  *            @arg MPU_HFNMI_PRIVDEF
  * @retval None
  */
-void HAL_MPU_Enable(uint32_t MPU_Control)
+void HAL_MPU_Enable(uint32_t MPU_Control) {
-{
   /* Enable the MPU */
   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 
@@ -313,8 +301,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
  *                the initialization and configuration information.
  * @retval None
  */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) {
-{
   /* Check the parameters */
   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
@@ -322,8 +309,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
   /* Set the Region number */
   MPU->RNR = MPU_Init->Number;
 
-  if ((MPU_Init->Enable) != RESET)
+  if ((MPU_Init->Enable) != RESET) {
-  {
     /* Check the parameters */
     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
@@ -335,18 +321,10 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
 
     MPU->RBAR = MPU_Init->BaseAddress;
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos)
-                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+                | ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos)
-                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+                | ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
-                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+  } else {
-                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
-                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
-                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
-                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
-                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
-  }
-  else
-  {
     MPU->RBAR = 0x00U;
     MPU->RASR = 0x00U;
   }
@@ -357,8 +335,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
  */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
+uint32_t HAL_NVIC_GetPriorityGrouping(void) {
-{
   /* Get the PRIGROUP[10:8] field value */
   return NVIC_GetPriorityGrouping();
 }
@@ -384,8 +361,7 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
  * @retval None
  */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) {
-{
   /* Check the parameters */
   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
   /* Get priority for Cortex-M system or device specific interrupts */
@@ -399,8 +375,7 @@ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPre
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
  * @retval None
  */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) {
-{
   /* Check the parameters */
   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 
@@ -417,8 +392,7 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
  * @retval status: - 0  Interrupt status is not pending.
  *                 - 1  Interrupt status is pending.
  */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) {
-{
   /* Check the parameters */
   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 
@@ -433,8 +407,7 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
  * @retval None
  */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
-{
   /* Check the parameters */
   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 
@@ -450,8 +423,7 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  * @retval status: - 0  Interrupt status is not pending.
  *                 - 1  Interrupt status is pending.
  */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) {
-{
   /* Check the parameters */
   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 
@@ -467,16 +439,12 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
  * @retval None
  */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) {
-{
   /* Check the parameters */
   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
-  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK) {
-  {
     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
-  }
+  } else {
-  else
-  {
     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
   }
 }
@@ -485,17 +453,13 @@ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
  * @brief  This function handles SYSTICK interrupt request.
  * @retval None
  */
-void HAL_SYSTICK_IRQHandler(void)
+void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); }
-{
-  HAL_SYSTICK_Callback();
-}
 
 /**
  * @brief  SYSTICK callback.
  * @retval None
  */
-__weak void HAL_SYSTICK_Callback(void)
+__weak void HAL_SYSTICK_Callback(void) {
-{
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SYSTICK_Callback could be implemented in the user file
    */

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c

@@ -156,13 +156,11 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) {
-{
   uint32_t tmp = 0U;
 
   /* Check the DMA handle allocation */
-  if(hdma == NULL)
+  if (hdma == NULL) {
-  {
     return HAL_ERROR;
   }
 
@@ -178,14 +176,11 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
 
 #if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F100xE) || defined(STM32F105xC) || defined(STM32F107xC)
   /* calculation of the channel index */
-  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
-  {
     /* DMA1 */
     hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
     hdma->DmaBaseAddress = DMA1;
-  }
+  } else {
-  else 
-  {
     /* DMA2 */
     hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
     hdma->DmaBaseAddress = DMA2;
@@ -203,15 +198,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
   tmp = hdma->Instance->CCR;
 
   /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
-  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
+  tmp &= ((uint32_t) ~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR));
-                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
-                      DMA_CCR_DIR));
 
   /* Prepare the DMA Channel configuration */
-  tmp |=  hdma->Init.Direction        |
+  tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority;
-          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
-          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
-          hdma->Init.Mode                | hdma->Init.Priority;
 
   /* Write to DMA Channel CR register */
   hdma->Instance->CCR = tmp;
@@ -233,11 +223,9 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) {
-{
   /* Check the DMA handle allocation */
-  if(hdma == NULL)
+  if (hdma == NULL) {
-  {
     return HAL_ERROR;
   }
 
@@ -261,14 +249,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 
 #if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F100xE) || defined(STM32F105xC) || defined(STM32F107xC)
   /* calculation of the channel index */
-  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
-  {
     /* DMA1 */
     hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
     hdma->DmaBaseAddress = DMA1;
-  }
+  } else {
-  else
-  {
     /* DMA2 */
     hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
     hdma->DmaBaseAddress = DMA2;
@@ -332,8 +317,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
-{
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Check the parameters */
@@ -342,8 +326,7 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
   /* Process locked */
   __HAL_LOCK(hdma);
 
-  if(HAL_DMA_STATE_READY == hdma->State)
+  if (HAL_DMA_STATE_READY == hdma->State) {
-  {
     /* Change DMA peripheral state */
     hdma->State     = HAL_DMA_STATE_BUSY;
     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -356,9 +339,7 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
 
     /* Enable the Peripheral */
     __HAL_DMA_ENABLE(hdma);
-  }
+  } else {
-  else
-  {
     /* Process Unlocked */
     __HAL_UNLOCK(hdma);
     status = HAL_BUSY;
@@ -375,8 +356,7 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
-{
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Check the parameters */
@@ -385,8 +365,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
   /* Process locked */
   __HAL_LOCK(hdma);
 
-  if(HAL_DMA_STATE_READY == hdma->State)
+  if (HAL_DMA_STATE_READY == hdma->State) {
-  {
     /* Change DMA peripheral state */
     hdma->State     = HAL_DMA_STATE_BUSY;
     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -399,21 +378,16 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
 
     /* Enable the transfer complete interrupt */
     /* Enable the transfer Error interrupt */
-    if(NULL != hdma->XferHalfCpltCallback)
+    if (NULL != hdma->XferHalfCpltCallback) {
-    {
       /* Enable the Half transfer complete interrupt as well */
       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
-    }
+    } else {
-    else
-    {
       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
     }
     /* Enable the Peripheral */
     __HAL_DMA_ENABLE(hdma);
-  }
+  } else {
-  else
-  {      
     /* Process Unlocked */
     __HAL_UNLOCK(hdma);
 
@@ -429,8 +403,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) {
-{
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Disable DMA IT */
@@ -457,19 +430,15 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
  *                 the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) {
-{  
   HAL_StatusTypeDef status = HAL_OK;
 
-  if(HAL_DMA_STATE_BUSY != hdma->State)
+  if (HAL_DMA_STATE_BUSY != hdma->State) {
-  {
     /* no transfer ongoing */
     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 
     status = HAL_ERROR;
-  }
+  } else {
-  else
-  { 
     /* Disable DMA IT */
     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 
@@ -486,8 +455,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
     __HAL_UNLOCK(hdma);
 
     /* Call User Abort callback */
-    if(hdma->XferAbortCallback != NULL)
+    if (hdma->XferAbortCallback != NULL) {
-    {
       hdma->XferAbortCallback(hdma);
     }
   }
@@ -502,13 +470,11 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
  * @param  Timeout:       Timeout duration.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) {
-{
   uint32_t temp;
   uint32_t tickstart = 0U;
 
-  if(HAL_DMA_STATE_BUSY != hdma->State)
+  if (HAL_DMA_STATE_BUSY != hdma->State) {
-  {
     /* no transfer ongoing */
     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
     __HAL_UNLOCK(hdma);
@@ -516,20 +482,16 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
   }
 
   /* Polling mode not supported in circular mode */
-  if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
+  if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) {
-  {
     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
     return HAL_ERROR;
   }
 
   /* Get the level transfer complete flag */
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  if (CompleteLevel == HAL_DMA_FULL_TRANSFER) {
-  {
     /* Transfer Complete flag */
     temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
-  }
+  } else {
-  else
-  {
     /* Half Transfer Complete flag */
     temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
   }
@@ -537,10 +499,8 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
   /* Get tick */
   tickstart = HAL_GetTick();
 
-  while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+  while (__HAL_DMA_GET_FLAG(hdma, temp) == RESET) {
-  {
+    if ((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) {
-    if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
-    {
       /* When a DMA transfer error occurs */
       /* A hardware clear of its EN bits is performed */
       /* Clear all flags */
@@ -558,10 +518,8 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
       return HAL_ERROR;
     }
     /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY) {
-    {
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
-      if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
-      {
         /* Update error code */
         SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
 
@@ -576,17 +534,14 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
     }
   }
 
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  if (CompleteLevel == HAL_DMA_FULL_TRANSFER) {
-  {
     /* Clear the transfer complete flag */
     __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 
     /* The selected Channelx EN bit is cleared (DMA is disabled and
     all transfers are complete) */
     hdma->State = HAL_DMA_STATE_READY;
-  }
+  } else {
-  else
-  {
     /* Clear the half transfer complete flag */
     __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
   }
@@ -603,17 +558,14 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
  *               the configuration information for the specified DMA Channel.
  * @retval None
  */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) {
-{
   uint32_t flag_it   = hdma->DmaBaseAddress->ISR;
   uint32_t source_it = hdma->Instance->CCR;
 
   /* Half Transfer Complete Interrupt management ******************************/
-  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
+  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) {
-  {
     /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
-    {
       /* Disable the half transfer interrupt */
       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
     }
@@ -623,18 +575,15 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
     /* DMA peripheral state is not updated in Half Transfer */
     /* but in Transfer Complete case */
 
-    if(hdma->XferHalfCpltCallback != NULL)
+    if (hdma->XferHalfCpltCallback != NULL) {
-    {
       /* Half transfer callback */
       hdma->XferHalfCpltCallback(hdma);
     }
   }
 
   /* Transfer Complete Interrupt management ***********************************/
-  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
+  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) {
-  {
+    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
-    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-    {
       /* Disable the transfer complete and error interrupt */
       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
 
@@ -647,16 +596,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
     /* Process Unlocked */
     __HAL_UNLOCK(hdma);
 
-    if(hdma->XferCpltCallback != NULL)
+    if (hdma->XferCpltCallback != NULL) {
-    {
       /* Transfer complete callback */
       hdma->XferCpltCallback(hdma);
     }
   }
 
   /* Transfer Error Interrupt management **************************************/
-  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
+  else if ((RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) {
-  {
     /* When a DMA transfer error occurs */
     /* A hardware clear of its EN bits is performed */
     /* Disable ALL DMA IT */
@@ -674,8 +621,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
     /* Process Unlocked */
     __HAL_UNLOCK(hdma);
 
-    if (hdma->XferErrorCallback != NULL)
+    if (hdma->XferErrorCallback != NULL) {
-    {
       /* Transfer error callback */
       hdma->XferErrorCallback(hdma);
     }
@@ -693,17 +639,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
  *                   a DMA_HandleTypeDef structure as parameter.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma)) {
-{
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Process locked */
   __HAL_LOCK(hdma);
 
-  if(HAL_DMA_STATE_READY == hdma->State)
+  if (HAL_DMA_STATE_READY == hdma->State) {
-  {
+    switch (CallbackID) {
-    switch (CallbackID)
-    {
     case HAL_DMA_XFER_CPLT_CB_ID:
       hdma->XferCpltCallback = pCallback;
       break;
@@ -724,9 +667,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
       status = HAL_ERROR;
       break;
     }
-  }
+  } else {
-  else
-  {
     status = HAL_ERROR;
   }
 
@@ -744,17 +685,14 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
  *                    a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) {
-{
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Process locked */
   __HAL_LOCK(hdma);
 
-  if(HAL_DMA_STATE_READY == hdma->State)
+  if (HAL_DMA_STATE_READY == hdma->State) {
-  {
+    switch (CallbackID) {
-    switch (CallbackID)
-    {
     case HAL_DMA_XFER_CPLT_CB_ID:
       hdma->XferCpltCallback = NULL;
       break;
@@ -782,9 +720,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
       status = HAL_ERROR;
       break;
     }
-  }
+  } else {
-  else
-  {
     status = HAL_ERROR;
   }
 
@@ -820,8 +756,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
  *               the configuration information for the specified DMA Channel.
  * @retval HAL state
  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) {
-{
   /* Return DMA handle state */
   return hdma->State;
 }
@@ -832,10 +767,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
  *              the configuration information for the specified DMA Channel.
  * @retval DMA Error Code
  */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; }
-{
-  return hdma->ErrorCode;
-}
 
 /**
  * @}
@@ -858,8 +790,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
-{
   /* Clear all flags */
   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 
@@ -867,8 +798,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
   hdma->Instance->CNDTR = DataLength;
 
   /* Memory to Peripheral */
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) {
-  {
     /* Configure DMA Channel destination address */
     hdma->Instance->CPAR = DstAddress;
 
@@ -876,8 +806,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
     hdma->Instance->CMAR = SrcAddress;
   }
   /* Peripheral to Memory */
-  else
+  else {
-  {
     /* Configure DMA Channel source address */
     hdma->Instance->CPAR = SrcAddress;
 

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c

@@ -181,8 +181,7 @@ extern void    FLASH_PageErase(uint32_t PageAddress);
  *
  * @retval HAL_StatusTypeDef HAL Status
  */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) {
-{
   HAL_StatusTypeDef status       = HAL_ERROR;
   uint8_t           index        = 0;
   uint8_t           nbiterations = 0;
@@ -195,45 +194,34 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
 
 #if defined(FLASH_BANK2_END)
-  if(Address <= FLASH_BANK1_END)
+  if (Address <= FLASH_BANK1_END) {
-  {
 #endif /* FLASH_BANK2_END */
     /* Wait for last operation to be completed */
     status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
 #if defined(FLASH_BANK2_END)
-  }
+  } else {
-  else
-  {
     /* Wait for last operation to be completed */
     status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
   }
 #endif /* FLASH_BANK2_END */
 
-  if(status == HAL_OK)
+  if (status == HAL_OK) {
-  {
+    if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) {
-    if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
-    {
       /* Program halfword (16-bit) at a specified address. */
       nbiterations = 1U;
-    }
+    } else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) {
-    else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
-    {
       /* Program word (32-bit = 2*16-bit) at a specified address. */
       nbiterations = 2U;
-    }
+    } else {
-    else
-    {
       /* Program double word (64-bit = 4*16-bit) at a specified address. */
       nbiterations = 4U;
     }
 
-    for (index = 0U; index < nbiterations; index++)
+    for (index = 0U; index < nbiterations; index++) {
-    {
       FLASH_Program_HalfWord((Address + (2U * index)), (uint16_t)(Data >> (16U * index)));
 
 #if defined(FLASH_BANK2_END)
-      if(Address <= FLASH_BANK1_END)
+      if (Address <= FLASH_BANK1_END) {
-      {
 #endif /* FLASH_BANK2_END */
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@@ -241,9 +229,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
         /* If the program operation is completed, disable the PG Bit */
         CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
 #if defined(FLASH_BANK2_END)
-      }
+      } else {
-      else
-      {
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
 
@@ -252,8 +238,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
       }
 #endif /* FLASH_BANK2_END */
       /* In case of error, stop programation procedure */
-      if (status != HAL_OK)
+      if (status != HAL_OK) {
-      {
         break;
       }
     }
@@ -280,8 +265,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
  *
  * @retval HAL_StatusTypeDef HAL Status
  */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) {
-{
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Process Locked */
@@ -293,18 +277,15 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
 
 #if defined(FLASH_BANK2_END)
   /* If procedure already ongoing, reject the next one */
-  if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+  if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
-  {
     return HAL_ERROR;
   }
 
-  if(Address <= FLASH_BANK1_END)
+  if (Address <= FLASH_BANK1_END) {
-  {
     /* Enable End of FLASH Operation and Error source interrupts */
     __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1);
 
-  }else
+  } else {
-  {
     /* Enable End of FLASH Operation and Error source interrupts */
     __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
   }
@@ -316,20 +297,15 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
   pFlash.Address = Address;
   pFlash.Data    = Data;
 
-  if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+  if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) {
-  {
     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
     /* Program halfword (16-bit) at a specified address. */
     pFlash.DataRemaining = 1U;
-  }
+  } else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) {
-  else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
-  {
     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
     /* Program word (32-bit : 2*16-bit) at a specified address. */
     pFlash.DataRemaining = 2U;
-  }
+  } else {
-  else
-  {
     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
     /* Program double word (64-bit : 4*16-bit) at a specified address. */
     pFlash.DataRemaining = 4U;
@@ -345,14 +321,12 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
  * @brief This function handles FLASH interrupt request.
  * @retval None
  */
-void HAL_FLASH_IRQHandler(void)
+void HAL_FLASH_IRQHandler(void) {
-{
   uint32_t addresstmp = 0U;
 
   /* Check FLASH operation error flags */
 #if defined(FLASH_BANK2_END)
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))
-    (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))
 #else
   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
 #endif /* FLASH_BANK2_END */
@@ -374,28 +348,23 @@ void HAL_FLASH_IRQHandler(void)
 
   /* Check FLASH End of Operation flag  */
 #if defined(FLASH_BANK2_END)
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1))
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) {
-  {
     /* Clear FLASH End of Operation pending bit */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1);
 #else
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) {
-  {
     /* Clear FLASH End of Operation pending bit */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
 #endif /* FLASH_BANK2_END */
 
     /* Process can continue only if no error detected */
-    if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+    if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
-    {
+      if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) {
-      if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
-      {
         /* Nb of pages to erased can be decreased */
         pFlash.DataRemaining--;
 
         /* Check if there are still pages to erase */
-        if(pFlash.DataRemaining != 0U)
+        if (pFlash.DataRemaining != 0U) {
-        {
           addresstmp = pFlash.Address;
           /*Indicate user which sector has been erased */
           HAL_FLASH_EndOfOperationCallback(addresstmp);
@@ -408,9 +377,7 @@ void HAL_FLASH_IRQHandler(void)
           CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
 
           FLASH_PageErase(addresstmp);
-        }
+        } else {
-        else
-        {
           /* No more pages to Erase, user callback can be called. */
           /* Reset Sector and stop Erase pages procedure */
           pFlash.Address = addresstmp = 0xFFFFFFFFU;
@@ -418,16 +385,13 @@ void HAL_FLASH_IRQHandler(void)
           /* FLASH EOP interrupt user callback */
           HAL_FLASH_EndOfOperationCallback(addresstmp);
         }
-      }
+      } else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) {
-      else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
-      {
         /* Operation is completed, disable the MER Bit */
         CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
 
 #if defined(FLASH_BANK2_END)
         /* Stop Mass Erase procedure if no pending mass erase on other bank */
-        if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER))
+        if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) {
-        {
 #endif /* FLASH_BANK2_END */
           /* MassErase ended. Return the selected bank */
           /* FLASH EOP interrupt user callback */
@@ -439,14 +403,12 @@ void HAL_FLASH_IRQHandler(void)
 #if defined(FLASH_BANK2_END)
       }
 #endif /* FLASH_BANK2_END */
-      else
+      else {
-      {
         /* Nb of 16-bit data to program can be decreased */
         pFlash.DataRemaining--;
 
         /* Check if there are still 16-bit data to program */
-        if(pFlash.DataRemaining != 0U)
+        if (pFlash.DataRemaining != 0U) {
-        {
           /* Increment address to 16-bit */
           pFlash.Address += 2U;
           addresstmp = pFlash.Address;
@@ -459,21 +421,14 @@ void HAL_FLASH_IRQHandler(void)
 
           /*Program halfword (16-bit) at a specified address.*/
           FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
-        }
+        } else {
-        else
-        {
           /* Program ended. Return the selected address */
           /* FLASH EOP interrupt user callback */
-          if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+          if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) {
-          {
             HAL_FLASH_EndOfOperationCallback(pFlash.Address);
-          }
+          } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) {
-          else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
-          {
             HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
-          }
+          } else {
-          else 
-          {
             HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
           }
 
@@ -487,22 +442,18 @@ void HAL_FLASH_IRQHandler(void)
 
 #if defined(FLASH_BANK2_END)
   /* Check FLASH End of Operation flag  */
-  if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2))
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) {
-  {
     /* Clear FLASH End of Operation pending bit */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
 
     /* Process can continue only if no error detected */
-    if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+    if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
-    {
+      if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) {
-      if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
-      {
         /* Nb of pages to erased can be decreased */
         pFlash.DataRemaining--;
 
         /* Check if there are still pages to erase*/
-        if(pFlash.DataRemaining != 0U)
+        if (pFlash.DataRemaining != 0U) {
-        {
           /* Indicate user which page address has been erased*/
           HAL_FLASH_EndOfOperationCallback(pFlash.Address);
 
@@ -514,9 +465,7 @@ void HAL_FLASH_IRQHandler(void)
           CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
 
           FLASH_PageErase(addresstmp);
-        }
+        } else {
-        else
-        {
           /*No more pages to Erase*/
 
           /*Reset Address and stop Erase pages procedure*/
@@ -526,29 +475,23 @@ void HAL_FLASH_IRQHandler(void)
           /* FLASH EOP interrupt user callback */
           HAL_FLASH_EndOfOperationCallback(pFlash.Address);
         }
-      }
+      } else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) {
-      else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
-      {
         /* Operation is completed, disable the MER Bit */
         CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
 
-        if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER))
+        if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) {
-        {
           /* MassErase ended. Return the selected bank*/
           /* FLASH EOP interrupt user callback */
           HAL_FLASH_EndOfOperationCallback(0U);
 
           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
         }
-      }
+      } else {
-      else
-      {
         /* Nb of 16-bit data to program can be decreased */
         pFlash.DataRemaining--;
 
         /* Check if there are still 16-bit data to program */
-        if(pFlash.DataRemaining != 0U)
+        if (pFlash.DataRemaining != 0U) {
-        {
           /* Increment address to 16-bit */
           pFlash.Address += 2U;
           addresstmp = pFlash.Address;
@@ -561,21 +504,14 @@ void HAL_FLASH_IRQHandler(void)
 
           /*Program halfword (16-bit) at a specified address.*/
           FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
-        }
+        } else {
-        else
-        {
           /*Program ended. Return the selected address*/
           /* FLASH EOP interrupt user callback */
-          if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+          if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) {
-          {
             HAL_FLASH_EndOfOperationCallback(pFlash.Address);
-          }
+          } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) {
-          else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
-          {
             HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
-          }
+          } else {
-          else 
-          {
             HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
           }
 
@@ -588,8 +524,7 @@ void HAL_FLASH_IRQHandler(void)
   }
 #endif
 
-  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) {
-  {
 #if defined(FLASH_BANK2_END)
     /* Operation is completed, disable the PG, PER and MER Bits for both bank */
     CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
@@ -619,8 +554,7 @@ void HAL_FLASH_IRQHandler(void)
  *                 - Program: Address which was selected for data program
  * @retval none
  */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) {
-{
   /* Prevent unused argument(s) compilation warning */
   UNUSED(ReturnValue);
 
@@ -637,8 +571,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
  *                 - Program: Address which was selected for data program
  * @retval none
  */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) {
-{
   /* Prevent unused argument(s) compilation warning */
   UNUSED(ReturnValue);
 
@@ -670,32 +603,27 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
  * @brief  Unlock the FLASH control register access
  * @retval HAL Status
  */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+HAL_StatusTypeDef HAL_FLASH_Unlock(void) {
-{
   HAL_StatusTypeDef status = HAL_OK;
 
-  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+  if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) {
-  {
     /* Authorize the FLASH Registers access */
     WRITE_REG(FLASH->KEYR, FLASH_KEY1);
     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
 
     /* Verify Flash is unlocked */
-    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+    if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) {
-    {
       status = HAL_ERROR;
     }
   }
 #if defined(FLASH_BANK2_END)
-  if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET)
+  if (READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) {
-  {
     /* Authorize the FLASH BANK2 Registers access */
     WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
     WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
 
     /* Verify Flash BANK2 is unlocked */
-    if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET)
+    if (READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) {
-    {
       status = HAL_ERROR;
     }
   }
@@ -708,8 +636,7 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void)
  * @brief  Locks the FLASH control register access
  * @retval HAL Status
  */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
+HAL_StatusTypeDef HAL_FLASH_Lock(void) {
-{
   /* Set the LOCK Bit to lock the FLASH Registers access */
   SET_BIT(FLASH->CR, FLASH_CR_LOCK);
 
@@ -725,16 +652,12 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void)
  * @brief  Unlock the FLASH Option Control Registers access.
  * @retval HAL Status
  */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) {
-{
+  if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) {
-  if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
-  {
     /* Authorizes the Option Byte register programming */
     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
-  }
+  } else {
-  else
-  {
     return HAL_ERROR;
   }
 
@@ -745,8 +668,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
  * @brief  Lock the FLASH Option Control Registers access.
  * @retval HAL Status
  */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) {
-{
   /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
   CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
 
@@ -758,8 +680,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
  * @note   This function will reset automatically the MCU.
  * @retval None
  */
-void HAL_FLASH_OB_Launch(void)
+void HAL_FLASH_OB_Launch(void) {
-{
   /* Initiates a system reset request to launch the option byte loading */
   HAL_NVIC_SystemReset();
 }
@@ -787,10 +708,7 @@ void HAL_FLASH_OB_Launch(void)
  * @retval FLASH_ErrorCode The returned value can be:
  *            @ref FLASH_Error_Codes
  */
-uint32_t HAL_FLASH_GetError(void)
+uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; }
-{
-   return pFlash.ErrorCode;
-}
 
 /**
  * @}
@@ -810,21 +728,17 @@ uint32_t HAL_FLASH_GetError(void)
  * @param  Data    specify the data to be programmed.
  * @retval None
  */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) {
-{
   /* Clean the error context */
   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
 #if defined(FLASH_BANK2_END)
-  if(Address <= FLASH_BANK1_END)
+  if (Address <= FLASH_BANK1_END) {
-  {
 #endif /* FLASH_BANK2_END */
     /* Proceed to program the new data */
     SET_BIT(FLASH->CR, FLASH_CR_PG);
 #if defined(FLASH_BANK2_END)
-  }
+  } else {
-  else
-  {
     /* Proceed to program the new data */
     SET_BIT(FLASH->CR2, FLASH_CR2_PG);
   }
@@ -839,36 +753,28 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
  * @param  Timeout  maximum flash operation timeout
  * @retval HAL Status
  */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) {
-{
   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
      Even if the FLASH operation fails, the BUSY flag will be reset and an error
      flag will be set */
 
   uint32_t tickstart = HAL_GetTick();
 
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
+  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) {
-  { 
+    if (Timeout != HAL_MAX_DELAY) {
-    if (Timeout != HAL_MAX_DELAY)
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
-    {
-      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
-      {
         return HAL_TIMEOUT;
       }
     }
   }
 
   /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) {
-  {
     /* Clear FLASH End of Operation pending bit */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
   }
 
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  || 
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) {
-     __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 
-     __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
-  {
     /*Save the error code*/
     FLASH_SetErrorCode();
     return HAL_ERROR;
@@ -884,34 +790,28 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
  * @param  Timeout maximum flash operation timeout
  * @retval HAL_StatusTypeDef HAL Status
  */
-HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)
+HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) {
-{ 
   /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
      Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error
      flag will be set */
 
   uint32_t tickstart = HAL_GetTick();
 
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) 
+  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) {
-  { 
+    if (Timeout != HAL_MAX_DELAY) {
-    if (Timeout != HAL_MAX_DELAY)
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
-    {
-      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
-      {
         return HAL_TIMEOUT;
       }
     }
   }
 
   /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2))
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) {
-  {
     /* Clear FLASH End of Operation pending bit */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
   }
 
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) {
-  {
     /*Save the error code*/
     FLASH_SetErrorCode();
     return HAL_ERROR;
@@ -919,7 +819,6 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)
 
   /* If there is an error flag set */
   return HAL_OK;
-  
 }
 #endif /* FLASH_BANK2_END */
 
@@ -927,8 +826,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)
  * @brief  Set the specific FLASH error flag.
  * @retval None
  */
-static void FLASH_SetErrorCode(void)
+static void FLASH_SetErrorCode(void) {
-{
   uint32_t flags = 0U;
 
 #if defined(FLASH_BANK2_END)
@@ -957,8 +855,7 @@ static void FLASH_SetErrorCode(void)
     flags |= FLASH_FLAG_PGERR;
 #endif /* FLASH_BANK2_END */
   }
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) {
-  {
     pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
   }

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c

@@ -156,7 +156,6 @@ static uint8_t           FLASH_OB_GetUser(void);
   * @{
   */
 
-
 /**
  * @brief  Perform a mass erase or erase the specified FLASH memory pages
  * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
@@ -172,8 +171,7 @@ static uint8_t           FLASH_OB_GetUser(void);
  *
  * @retval HAL_StatusTypeDef HAL Status
  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) {
-{
   HAL_StatusTypeDef status  = HAL_ERROR;
   uint32_t          address = 0U;
 
@@ -183,23 +181,17 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
   /* Check the parameters */
   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
 
-  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) {
-  {
 #if defined(FLASH_BANK2_END)
-    if (pEraseInit->Banks == FLASH_BANK_BOTH)
+    if (pEraseInit->Banks == FLASH_BANK_BOTH) {
-    {
       /* Mass Erase requested for Bank1 and Bank2 */
       /* Wait for last operation to be completed */
-      if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
+      if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) {
-          (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
-      {
         /*Mass erase to be done*/
         FLASH_MassErase(FLASH_BANK_BOTH);
 
         /* Wait for last operation to be completed */
-        if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
+        if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) {
-            (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
-        {
           status = HAL_OK;
         }
 
@@ -207,13 +199,10 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
         CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
         CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
       }
-    }
+    } else if (pEraseInit->Banks == FLASH_BANK_2) {
-    else if (pEraseInit->Banks == FLASH_BANK_2)
-    {
       /* Mass Erase requested for Bank2 */
       /* Wait for last operation to be completed */
-      if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+      if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) {
-      {
         /*Mass erase to be done*/
         FLASH_MassErase(FLASH_BANK_2);
 
@@ -223,14 +212,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
         /* If the erase operation is completed, disable the MER Bit */
         CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
       }
-    }
+    } else
-    else 
 #endif /* FLASH_BANK2_END */
     {
       /* Mass Erase requested for Bank1 */
       /* Wait for last operation to be completed */
-      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) {
-      {
         /*Mass erase to be done*/
         FLASH_MassErase(FLASH_BANK_1);
 
@@ -241,9 +228,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
         CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
       }
     }
-  }
+  } else {
-  else
-  {
     /* Page Erase is requested */
     /* Check the parameters */
     assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
@@ -251,19 +236,14 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
 
 #if defined(FLASH_BANK2_END)
     /* Page Erase requested on address located on bank2 */
-    if(pEraseInit->PageAddress > FLASH_BANK1_END)
+    if (pEraseInit->PageAddress > FLASH_BANK1_END) {
-    {   
       /* Wait for last operation to be completed */
-      if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+      if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) {
-      {
         /*Initialization of PageError variable*/
         *PageError = 0xFFFFFFFFU;
 
         /* Erase by page by page to be done*/
-        for(address = pEraseInit->PageAddress;
+        for (address = pEraseInit->PageAddress; address < (pEraseInit->PageAddress + (pEraseInit->NbPages) * FLASH_PAGE_SIZE); address += FLASH_PAGE_SIZE) {
-            address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
-            address += FLASH_PAGE_SIZE)
-        {
           FLASH_PageErase(address);
 
           /* Wait for last operation to be completed */
@@ -272,30 +252,24 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
           /* If the erase operation is completed, disable the PER Bit */
           CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
 
-          if (status != HAL_OK)
+          if (status != HAL_OK) {
-          {
             /* In case of error, stop erase procedure and return the faulty address */
             *PageError = address;
             break;
           }
         }
       }
-    }
+    } else
-    else
 #endif /* FLASH_BANK2_END */
     {
       /* Page Erase requested on address located on bank1 */
       /* Wait for last operation to be completed */
-      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) {
-      {
         /*Initialization of PageError variable*/
         *PageError = 0xFFFFFFFFU;
 
         /* Erase page by page to be done*/
-        for(address = pEraseInit->PageAddress;
+        for (address = pEraseInit->PageAddress; address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) {
-            address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
-            address += FLASH_PAGE_SIZE)
-        {
           FLASH_PageErase(address);
 
           /* Wait for last operation to be completed */
@@ -304,8 +278,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
           /* If the erase operation is completed, disable the PER Bit */
           CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
 
-          if (status != HAL_OK)
+          if (status != HAL_OK) {
-          {
             /* In case of error, stop erase procedure and return the faulty address */
             *PageError = address;
             break;
@@ -332,16 +305,14 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
  *
  * @retval HAL_StatusTypeDef HAL Status
  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) {
-{
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Process Locked */
   __HAL_LOCK(&pFlash);
 
   /* If procedure already ongoing, reject the next one */
-  if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+  if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
-  {
     return HAL_ERROR;
   }
 
@@ -356,14 +327,11 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
 
 #endif
-  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) {
-  {
     /*Mass erase to be done*/
     pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
     FLASH_MassErase(pEraseInit->Banks);
-  }
+  } else {
-  else
-  {
     /* Erase by page to be done*/
 
     /* Check the parameters */
@@ -410,8 +378,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
  * @retval HAL status
  */
 
-HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) {
-{
   uint8_t           rdptmp = OB_RDP_LEVEL_0;
   HAL_StatusTypeDef status = HAL_ERROR;
 
@@ -421,8 +388,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 
-  if(status == HAL_OK)
+  if (status == HAL_OK) {
-  {
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
@@ -436,8 +402,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
     /* If the erase operation is completed, disable the OPTER Bit */
     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
 
-    if(status == HAL_OK)
+    if (status == HAL_OK) {
-    {
       /* Restore the last read protection Option Byte value */
       status = FLASH_OB_RDP_LevelConfig(rdptmp);
     }
@@ -459,8 +424,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
  *
  * @retval HAL_StatusTypeDef HAL Status
  */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) {
-{
   HAL_StatusTypeDef status = HAL_ERROR;
 
   /* Process Locked */
@@ -470,21 +434,16 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
 
   /* Write protection configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+  if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) {
-  {
     assert_param(IS_WRPSTATE(pOBInit->WRPState));
-    if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+    if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) {
-    {
       /* Enable of Write protection on the selected page */
       status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
-    }
+    } else {
-    else
-    {
       /* Disable of Write protection on the selected page */
       status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
     }
-    if (status != HAL_OK)
+    if (status != HAL_OK) {
-    {
       /* Process Unlocked */
       __HAL_UNLOCK(&pFlash);
       return status;
@@ -492,11 +451,9 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
   }
 
   /* Read protection configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+  if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) {
-  {
     status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
-    if (status != HAL_OK)
+    if (status != HAL_OK) {
-    {
       /* Process Unlocked */
       __HAL_UNLOCK(&pFlash);
       return status;
@@ -504,11 +461,9 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
   }
 
   /* USER configuration */
-  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+  if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) {
-  {
     status = FLASH_OB_UserConfig(pOBInit->USERConfig);
-    if (status != HAL_OK)
+    if (status != HAL_OK) {
-    {
       /* Process Unlocked */
       __HAL_UNLOCK(&pFlash);
       return status;
@@ -516,11 +471,9 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
   }
 
   /* DATA configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
+  if ((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) {
-  {
     status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
-    if (status != HAL_OK)
+    if (status != HAL_OK) {
-    {
       /* Process Unlocked */
       __HAL_UNLOCK(&pFlash);
       return status;
@@ -540,8 +493,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
  *
  * @retval None
  */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) {
-{
   pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
 
   /*Get WRP*/
@@ -562,17 +514,13 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
  *            @arg @ref OB_DATA_ADDRESS_DATA1
  * @retval Value programmed in USER data
  */
-uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
+uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) {
-{
   uint32_t value = 0;
 
-  if (DATAAdress == OB_DATA_ADDRESS_DATA0)
+  if (DATAAdress == OB_DATA_ADDRESS_DATA0) {
-  {
     /* Get value programmed in OB USER Data0 */
     value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
-  }
+  } else {
-  else
-  {
     /* Get value programmed in OB USER Data1 */
     value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
   }
@@ -608,8 +556,7 @@ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
   *
   * @retval None
   */
-static void FLASH_MassErase(uint32_t Banks)
+static void FLASH_MassErase(uint32_t Banks) {
-{
   /* Check the parameters */
   assert_param(IS_FLASH_BANK(Banks));
 
@@ -617,22 +564,17 @@ static void FLASH_MassErase(uint32_t Banks)
   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
 #if defined(FLASH_BANK2_END)
-  if(Banks == FLASH_BANK_BOTH)
+  if (Banks == FLASH_BANK_BOTH) {
-  {
     /* bank1 & bank2 will be erased*/
     SET_BIT(FLASH->CR, FLASH_CR_MER);
     SET_BIT(FLASH->CR2, FLASH_CR2_MER);
     SET_BIT(FLASH->CR, FLASH_CR_STRT);
     SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
-  }
+  } else if (Banks == FLASH_BANK_2) {
-  else if(Banks == FLASH_BANK_2)
-  {
     /*Only bank2 will be erased*/
     SET_BIT(FLASH->CR2, FLASH_CR2_MER);
     SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
-  }
+  } else {
-  else
-  {
 #endif /* FLASH_BANK2_END */
 #if !defined(FLASH_BANK2_END)
     /* Prevent unused argument(s) compilation warning */
@@ -657,8 +599,7 @@ static void FLASH_MassErase(uint32_t Banks)
  *         The value of this parameter depend on device used within the same series
  * @retval HAL status
  */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) {
-{
   HAL_StatusTypeDef status    = HAL_OK;
   uint16_t          WRP0_Data = 0xFFFF;
 #if defined(FLASH_WRP1_WRP1)
@@ -709,21 +650,18 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 
-  if(status == HAL_OK)
+  if (status == HAL_OK) {
-  { 
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
     /* To be able to write again option byte, need to perform a option byte erase */
     status = HAL_FLASHEx_OBErase();
-    if (status == HAL_OK)  
+    if (status == HAL_OK) {
-    {
       /* Enable write protection */
       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
 
 #if defined(FLASH_WRP0_WRP0)
-      if(WRP0_Data != 0xFFU)
+      if (WRP0_Data != 0xFFU) {
-      {
         OB->WRP0 &= WRP0_Data;
 
         /* Wait for last operation to be completed */
@@ -732,8 +670,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
 #endif /* FLASH_WRP0_WRP0 */
 
 #if defined(FLASH_WRP1_WRP1)
-      if((status == HAL_OK) && (WRP1_Data != 0xFFU))
+      if ((status == HAL_OK) && (WRP1_Data != 0xFFU)) {
-      {
         OB->WRP1 &= WRP1_Data;
 
         /* Wait for last operation to be completed */
@@ -742,8 +679,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
 #endif /* FLASH_WRP1_WRP1 */
 
 #if defined(FLASH_WRP2_WRP2)
-      if((status == HAL_OK) && (WRP2_Data != 0xFFU))
+      if ((status == HAL_OK) && (WRP2_Data != 0xFFU)) {
-      {
         OB->WRP2 &= WRP2_Data;
 
         /* Wait for last operation to be completed */
@@ -752,8 +688,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
 #endif /* FLASH_WRP2_WRP2 */
 
 #if defined(FLASH_WRP3_WRP3)
-      if((status == HAL_OK) && (WRP3_Data != 0xFFU))
+      if ((status == HAL_OK) && (WRP3_Data != 0xFFU)) {
-      {
         OB->WRP3 &= WRP3_Data;
 
         /* Wait for last operation to be completed */
@@ -780,8 +715,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
  *         The value of this parameter depend on device used within the same series
  * @retval HAL status
  */
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) {
-{
   HAL_StatusTypeDef status    = HAL_OK;
   uint16_t          WRP0_Data = 0xFFFF;
 #if defined(FLASH_WRP1_WRP1)
@@ -829,24 +763,20 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
 #endif /* OB_WRP_PAGES96TO127MASK */
 
-    
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 
-  if(status == HAL_OK)
+  if (status == HAL_OK) {
-  { 
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
     /* To be able to write again option byte, need to perform a option byte erase */
     status = HAL_FLASHEx_OBErase();
-    if (status == HAL_OK)  
+    if (status == HAL_OK) {
-    {
       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
 
 #if defined(FLASH_WRP0_WRP0)
-      if(WRP0_Data != 0xFFU)
+      if (WRP0_Data != 0xFFU) {
-      {
         OB->WRP0 |= WRP0_Data;
 
         /* Wait for last operation to be completed */
@@ -855,8 +785,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
 #endif /* FLASH_WRP0_WRP0 */
 
 #if defined(FLASH_WRP1_WRP1)
-      if((status == HAL_OK) && (WRP1_Data != 0xFFU))
+      if ((status == HAL_OK) && (WRP1_Data != 0xFFU)) {
-      {
         OB->WRP1 |= WRP1_Data;
 
         /* Wait for last operation to be completed */
@@ -865,8 +794,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
 #endif /* FLASH_WRP1_WRP1 */
 
 #if defined(FLASH_WRP2_WRP2)
-      if((status == HAL_OK) && (WRP2_Data != 0xFFU))
+      if ((status == HAL_OK) && (WRP2_Data != 0xFFU)) {
-      {
         OB->WRP2 |= WRP2_Data;
 
         /* Wait for last operation to be completed */
@@ -875,8 +803,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
 #endif /* FLASH_WRP2_WRP2 */
 
 #if defined(FLASH_WRP3_WRP3)
-      if((status == HAL_OK) && (WRP3_Data != 0xFFU))
+      if ((status == HAL_OK) && (WRP3_Data != 0xFFU)) {
-      {
         OB->WRP3 |= WRP3_Data;
 
         /* Wait for last operation to be completed */
@@ -899,8 +826,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
  *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
  * @retval HAL status
  */
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) {
-{
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Check the parameters */
@@ -909,8 +835,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 
-  if(status == HAL_OK)
+  if (status == HAL_OK) {
-  { 
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
@@ -924,8 +849,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
     /* If the erase operation is completed, disable the OPTER Bit */
     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
 
-    if(status == HAL_OK)
+    if (status == HAL_OK) {
-    {
       /* Enable the Option Bytes Programming operation */
       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
 
@@ -950,8 +874,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
  *         And BFBF2(Bit5) for STM32F101xG and STM32F103xG .
  * @retval HAL status
  */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) {
-{
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Check the parameters */
@@ -965,8 +888,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 
-  if(status == HAL_OK)
+  if (status == HAL_OK) {
-  {     
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
@@ -1001,8 +923,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
  * @param  Data specifies the data to be programmed.
  * @retval HAL status
  */
-static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) {
-{
   HAL_StatusTypeDef status = HAL_ERROR;
 
   /* Check the parameters */
@@ -1011,8 +932,7 @@ static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 
-  if(status == HAL_OK)
+  if (status == HAL_OK) {
-  {
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
@@ -1034,8 +954,7 @@ static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
  * @brief  Return the FLASH Write Protection Option Bytes value.
  * @retval The FLASH Write Protection Option Bytes value
  */
-static uint32_t FLASH_OB_GetWRP(void)
+static uint32_t FLASH_OB_GetWRP(void) {
-{
   /* Return the FLASH write protection Register value */
   return (uint32_t)(READ_REG(FLASH->WRPR));
 }
@@ -1047,20 +966,16 @@ static uint32_t FLASH_OB_GetWRP(void)
  *            @arg @ref OB_RDP_LEVEL_0 No protection
  *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
  */
-static uint32_t FLASH_OB_GetRDP(void)
+static uint32_t FLASH_OB_GetRDP(void) {
-{
   uint32_t readstatus = OB_RDP_LEVEL_0;
   uint32_t tmp_reg    = 0U;
 
   /* Read RDP level bits */
   tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
 
-  if (tmp_reg == FLASH_OBR_RDPRT)
+  if (tmp_reg == FLASH_OBR_RDPRT) {
-  {
     readstatus = OB_RDP_LEVEL_1;
-  }
+  } else {
-  else 
-  {
     readstatus = OB_RDP_LEVEL_0;
   }
 
@@ -1073,8 +988,7 @@ static uint32_t FLASH_OB_GetRDP(void)
  *         FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
  *         And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG .
  */
-static uint8_t FLASH_OB_GetUser(void)
+static uint8_t FLASH_OB_GetUser(void) {
-{
   /* Return the User Option Byte */
   return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
 }
@@ -1102,21 +1016,17 @@ static uint8_t FLASH_OB_GetUser(void)
  *
  * @retval None
  */
-void FLASH_PageErase(uint32_t PageAddress)
+void FLASH_PageErase(uint32_t PageAddress) {
-{
   /* Clean the error context */
   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
 #if defined(FLASH_BANK2_END)
-  if(PageAddress > FLASH_BANK1_END)
+  if (PageAddress > FLASH_BANK1_END) {
-  { 
     /* Proceed to erase the page */
     SET_BIT(FLASH->CR2, FLASH_CR2_PER);
     WRITE_REG(FLASH->AR2, PageAddress);
     SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
-  }
+  } else {
-  else
-  {
 #endif /* FLASH_BANK2_END */
     /* Proceed to erase the page */
     SET_BIT(FLASH->CR, FLASH_CR_PER);

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c

@@ -183,7 +183,6 @@
   * @{
   */
 
-
 /**
  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
  * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
@@ -191,8 +190,7 @@
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) {
-{
   uint32_t position;
   uint32_t ioposition = 0x00U;
   uint32_t iocurrent  = 0x00U;
@@ -207,22 +205,19 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
 
   /* Configure the port pins */
-  for (position = 0U; position < GPIO_NUMBER; position++)
+  for (position = 0U; position < GPIO_NUMBER; position++) {
-  {
     /* Get the IO position */
     ioposition = (0x01U << position);
 
     /* Get the current IO position */
     iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 
-    if (iocurrent == ioposition)
+    if (iocurrent == ioposition) {
-    {
       /* Check the Alternate function parameters */
       assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
 
       /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
-      switch (GPIO_Init->Mode)
+      switch (GPIO_Init->Mode) {
-      {
       /* If we are configuring the pin in OUTPUT push-pull mode */
       case GPIO_MODE_OUTPUT_PP:
         /* Check the GPIO speed parameter */
@@ -261,18 +256,14 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
       case GPIO_MODE_EVT_RISING_FALLING:
         /* Check the GPIO pull parameter */
         assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-          if (GPIO_Init->Pull == GPIO_NOPULL)
+        if (GPIO_Init->Pull == GPIO_NOPULL) {
-          {
           config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
-          }
+        } else if (GPIO_Init->Pull == GPIO_PULLUP) {
-          else if (GPIO_Init->Pull == GPIO_PULLUP)
-          {
           config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 
           /* Set the corresponding ODR bit */
           GPIOx->BSRR = ioposition;
-          }
+        } else /* GPIO_PULLDOWN */
-          else /* GPIO_PULLDOWN */
         {
           config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 
@@ -301,8 +292,7 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
 
       /*--------------------- EXTI Mode Configuration ------------------------*/
       /* Configure the External Interrupt or event for the current IO */
-      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) {
-      {
         /* Enable AFIO Clock */
         __HAL_RCC_AFIO_CLK_ENABLE();
         temp = AFIO->EXTICR[position >> 2U];
@@ -310,44 +300,31 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
         AFIO->EXTICR[position >> 2U] = temp;
 
-
         /* Configure the interrupt mask */
-        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) {
-        {
           SET_BIT(EXTI->IMR, iocurrent);
-        }
+        } else {
-        else
-        {
           CLEAR_BIT(EXTI->IMR, iocurrent);
         }
 
         /* Configure the event mask */
-        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) {
-        {
           SET_BIT(EXTI->EMR, iocurrent);
-        }
+        } else {
-        else
-        {
           CLEAR_BIT(EXTI->EMR, iocurrent);
         }
 
         /* Enable or disable the rising trigger */
-        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) {
-        {
           SET_BIT(EXTI->RTSR, iocurrent);
-        }
+        } else {
-        else
-        {
           CLEAR_BIT(EXTI->RTSR, iocurrent);
         }
 
         /* Enable or disable the falling trigger */
-        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) {
-        {
           SET_BIT(EXTI->FTSR, iocurrent);
-        }
+        } else {
-        else
-        {
           CLEAR_BIT(EXTI->FTSR, iocurrent);
         }
       }
@@ -362,8 +339,7 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
  *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
  * @retval None
  */
-void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) {
-{
   uint32_t position  = 0x00U;
   uint32_t iocurrent = 0x00U;
   uint32_t tmp       = 0x00U;
@@ -375,13 +351,11 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
   assert_param(IS_GPIO_PIN(GPIO_Pin));
 
   /* Configure the port pins */
-  while ((GPIO_Pin >> position) != 0U)
+  while ((GPIO_Pin >> position) != 0U) {
-  {
     /* Get current io position */
     iocurrent = (GPIO_Pin) & (1U << position);
 
-    if (iocurrent)
+    if (iocurrent) {
-    {
       /*------------------------- GPIO Mode Configuration --------------------*/
       /* Check if the current bit belongs to first half or last half of the pin count number
        in order to address CRH or CRL register */
@@ -399,8 +373,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
 
       tmp = AFIO->EXTICR[position >> 2U];
       tmp &= 0x0FU << (4U * (position & 0x03U));
-      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) {
-      {
         tmp = 0x0FU << (4U * (position & 0x03U));
         CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp);
 
@@ -443,19 +416,15 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
  *         This parameter can be GPIO_PIN_x where x can be (0..15).
  * @retval The input port pin value.
  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
-{
   GPIO_PinState bitstatus;
 
   /* Check the parameters */
   assert_param(IS_GPIO_PIN(GPIO_Pin));
 
-  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) {
-  {
     bitstatus = GPIO_PIN_SET;
-  }
+  } else {
-  else
-  {
     bitstatus = GPIO_PIN_RESET;
   }
   return bitstatus;
@@ -477,18 +446,14 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) {
-{
   /* Check the parameters */
   assert_param(IS_GPIO_PIN(GPIO_Pin));
   assert_param(IS_GPIO_PIN_ACTION(PinState));
 
-  if (PinState != GPIO_PIN_RESET)
+  if (PinState != GPIO_PIN_RESET) {
-  {
     GPIOx->BSRR = GPIO_Pin;
-  }
+  } else {
-  else
-  {
     GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
   }
 }
@@ -499,8 +464,7 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
  * @param  GPIO_Pin: Specifies the pins to be toggled.
  * @retval None
  */
-void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
-{
   /* Check the parameters */
   assert_param(IS_GPIO_PIN(GPIO_Pin));
 
@@ -517,8 +481,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
  * @retval None
  */
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
-{
   __IO uint32_t tmp = GPIO_LCKR_LCKK;
 
   /* Check the parameters */
@@ -536,12 +499,9 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
   /* Read LCKK bit*/
   tmp = GPIOx->LCKR;
 
-  if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
+  if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) {
-  {
     return HAL_OK;
-  }
+  } else {
-  else
-  {
     return HAL_ERROR;
   }
 }
@@ -551,11 +511,9 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
  * @param  GPIO_Pin: Specifies the pins connected EXTI line
  * @retval None
  */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) {
-{
   /* EXTI line interrupt detected */
-  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) {
-  {
     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
     HAL_GPIO_EXTI_Callback(GPIO_Pin);
   }
@@ -566,8 +524,7 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
  * @param  GPIO_Pin: Specifies the pins connected EXTI line
  * @retval None
  */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
-{
   /* Prevent unused argument(s) compilation warning */
   UNUSED(GPIO_Pin);
   /* NOTE: This function Should not be modified, when the callback is needed,

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c

@@ -94,8 +94,7 @@
  *   This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
  * @retval None
  */
-void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
+void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) {
-{
   /* Verify the parameters */
   assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
   assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
@@ -108,19 +107,13 @@ void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource
  * @brief  Enables the Event Output.
  * @retval None
  */
-void HAL_GPIOEx_EnableEventout(void)
+void HAL_GPIOEx_EnableEventout(void) { SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); }
-{
-  SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
-}
 
 /**
  * @brief  Disables the Event Output.
  * @retval None
  */
-void HAL_GPIOEx_DisableEventout(void)
+void HAL_GPIOEx_DisableEventout(void) { CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); }
-{
-  CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
-}
 
 /**
  * @}

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c

@@ -159,13 +159,11 @@
  *                the configuration information for the specified IWDG module.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) {
-{
   uint32_t tickstart;
 
   /* Check the IWDG handle allocation */
-  if (hiwdg == NULL)
+  if (hiwdg == NULL) {
-  {
     return HAL_ERROR;
   }
 
@@ -188,10 +186,8 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
   tickstart = HAL_GetTick();
 
   /* Wait for register to be updated */
-  while (hiwdg->Instance->SR != RESET)
+  while (hiwdg->Instance->SR != RESET) {
-  {
+    if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) {
-    if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
-    {
       return HAL_TIMEOUT;
     }
   }
@@ -227,8 +223,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
  *                the configuration information for the specified IWDG module.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) {
-{
   /* Reload IWDG counter with value defined in the reload register */
   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
 

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c

@@ -71,7 +71,6 @@
  * @}
  */
 
-
 /** @defgroup PWR_register_alias_address PWR Register alias address
  * @{
  */
@@ -130,8 +129,7 @@ static void PWR_OverloadWfe(void);
 
 /* Private functions ---------------------------------------------------------*/
 __NOINLINE
-static void PWR_OverloadWfe(void)
+static void PWR_OverloadWfe(void) {
-{
   __asm volatile("wfe");
   __asm volatile("nop");
 }
@@ -140,7 +138,6 @@ static void PWR_OverloadWfe(void)
  * @}
  */
 
-
 /** @defgroup PWR_Exported_Functions PWR Exported Functions
  * @{
  */
@@ -169,8 +166,7 @@ static void PWR_OverloadWfe(void)
  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
  * @retval None
  */
-void HAL_PWR_DeInit(void)
+void HAL_PWR_DeInit(void) {
-{
   __HAL_RCC_PWR_FORCE_RESET();
   __HAL_RCC_PWR_RELEASE_RESET();
 }
@@ -182,8 +178,7 @@ void HAL_PWR_DeInit(void)
  *         Backup Domain Access should be kept enabled.
  * @retval None
  */
-void HAL_PWR_EnableBkUpAccess(void)
+void HAL_PWR_EnableBkUpAccess(void) {
-{
   /* Enable access to RTC and backup registers */
   *(__IO uint32_t *)CR_DBP_BB = (uint32_t)ENABLE;
 }
@@ -195,8 +190,7 @@ void HAL_PWR_EnableBkUpAccess(void)
  *         Backup Domain Access should be kept enabled.
  * @retval None
  */
-void HAL_PWR_DisableBkUpAccess(void)
+void HAL_PWR_DisableBkUpAccess(void) {
-{
   /* Disable access to RTC and backup registers */
   *(__IO uint32_t *)CR_DBP_BB = (uint32_t)DISABLE;
 }
@@ -329,8 +323,7 @@ void HAL_PWR_DisableBkUpAccess(void)
  *         detection level.
  * @retval None
  */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) {
-{
   /* Check the parameters */
   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
@@ -345,25 +338,21 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
 
   /* Configure interrupt mode */
-  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) {
-  {
     __HAL_PWR_PVD_EXTI_ENABLE_IT();
   }
 
   /* Configure event mode */
-  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) {
-  {
     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
   }
 
   /* Configure the edge */
-  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) {
-  {
     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
   }
 
-  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) {
-  {
     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
   }
 }
@@ -372,8 +361,7 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
  * @brief  Enables the Power Voltage Detector(PVD).
  * @retval None
  */
-void HAL_PWR_EnablePVD(void)
+void HAL_PWR_EnablePVD(void) {
-{
   /* Enable the power voltage detector */
   *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)ENABLE;
 }
@@ -382,8 +370,7 @@ void HAL_PWR_EnablePVD(void)
  * @brief  Disables the Power Voltage Detector(PVD).
  * @retval None
  */
-void HAL_PWR_DisablePVD(void)
+void HAL_PWR_DisablePVD(void) {
-{
   /* Disable the power voltage detector */
   *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)DISABLE;
 }
@@ -395,8 +382,7 @@ void HAL_PWR_DisablePVD(void)
  *           @arg PWR_WAKEUP_PIN1
  * @retval None
  */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) {
-{
   /* Check the parameter */
   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
   /* Enable the EWUPx pin */
@@ -410,8 +396,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
  *           @arg PWR_WAKEUP_PIN1
  * @retval None
  */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) {
-{
   /* Check the parameter */
   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
   /* Disable the EWUPx pin */
@@ -430,8 +415,7 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  * @retval None
  */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) {
-{
   /* Check the parameters */
   /* No check on Regulator because parameter not used in SLEEP mode */
   /* Prevent unused argument(s) compilation warning */
@@ -443,13 +427,10 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 
   /* Select SLEEP mode entry -------------------------------------------------*/
-  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  if (SLEEPEntry == PWR_SLEEPENTRY_WFI) {
-  {
     /* Request Wait For Interrupt */
     __WFI();
-  }
+  } else {
-  else
-  {
     /* Request Wait For Event */
     __SEV();
     __WFE();
@@ -476,8 +457,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
  * @retval None
  */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) {
-{
   /* Check the parameters */
   assert_param(IS_PWR_REGULATOR(Regulator));
   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
@@ -492,13 +472,10 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 
   /* Select Stop mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_STOPENTRY_WFI)
+  if (STOPEntry == PWR_STOPENTRY_WFI) {
-  {
     /* Request Wait For Interrupt */
     __WFI();
-  }
+  } else {
-  else
-  {
     /* Request Wait For Event */
     __SEV();
     PWR_OverloadWfe(); /* WFE redefine locally */
@@ -516,8 +493,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
  *          - WKUP pin (PA0) if enabled.
  * @retval None
  */
-void HAL_PWR_EnterSTANDBYMode(void)
+void HAL_PWR_EnterSTANDBYMode(void) {
-{
   /* Select Standby mode */
   SET_BIT(PWR->CR, PWR_CR_PDDS);
 
@@ -532,7 +508,6 @@ void HAL_PWR_EnterSTANDBYMode(void)
   __WFI();
 }
 
-
 /**
  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
@@ -541,63 +516,52 @@ void HAL_PWR_EnterSTANDBYMode(void)
  *       interruptions handling.
  * @retval None
  */
-void HAL_PWR_EnableSleepOnExit(void)
+void HAL_PWR_EnableSleepOnExit(void) {
-{
   /* Set SLEEPONEXIT bit of Cortex System Control Register */
   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 }
 
-
 /**
  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  *       re-enters SLEEP mode when an interruption handling is over.
  * @retval None
  */
-void HAL_PWR_DisableSleepOnExit(void)
+void HAL_PWR_DisableSleepOnExit(void) {
-{
   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 }
 
-
 /**
  * @brief Enables CORTEX M3 SEVONPEND bit.
  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
  *       WFE to wake up when an interrupt moves from inactive to pended.
  * @retval None
  */
-void HAL_PWR_EnableSEVOnPend(void)
+void HAL_PWR_EnableSEVOnPend(void) {
-{
   /* Set SEVONPEND bit of Cortex System Control Register */
   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 }
 
-
 /**
  * @brief Disables CORTEX M3 SEVONPEND bit.
  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
  *       WFE to wake up when an interrupt moves from inactive to pended.
  * @retval None
  */
-void HAL_PWR_DisableSEVOnPend(void)
+void HAL_PWR_DisableSEVOnPend(void) {
-{
   /* Clear SEVONPEND bit of Cortex System Control Register */
   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 }
 
-
-
 /**
  * @brief  This function handles the PWR PVD interrupt request.
  * @note   This API should be called under the PVD_IRQHandler().
  * @retval None
  */
-void HAL_PWR_PVD_IRQHandler(void)
+void HAL_PWR_PVD_IRQHandler(void) {
-{
   /* Check PWR exti flag */
-  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+  if (__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) {
-  {
     /* PWR PVD interrupt user callback */
     HAL_PWR_PVDCallback();
 
@@ -610,8 +574,7 @@ void HAL_PWR_PVD_IRQHandler(void)
  * @brief  PWR PVD interrupt callback
  * @retval None
  */
-__weak void HAL_PWR_PVDCallback(void)
+__weak void HAL_PWR_PVDCallback(void) {
-{
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PWR_PVDCallback could be implemented in the user file
    */

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c

@@ -215,8 +215,7 @@ static void RCC_Delay(uint32_t mdelay);
  *            - LSI, LSE and RTC clocks
  * @retval HAL_StatusTypeDef
  */
-HAL_StatusTypeDef HAL_RCC_DeInit(void)
+HAL_StatusTypeDef HAL_RCC_DeInit(void) {
-{
   uint32_t tickstart;
 
   /* Get Start Tick */
@@ -226,10 +225,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   SET_BIT(RCC->CR, RCC_CR_HSION);
 
   /* Wait till HSI is ready */
-  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) {
-  {
+    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
-    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
-    {
       return HAL_TIMEOUT;
     }
   }
@@ -244,10 +241,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   CLEAR_REG(RCC->CFGR);
 
   /* Wait till clock switch is ready */
-  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
+  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) {
-  {
+    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
-    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-    {
       return HAL_TIMEOUT;
     }
   }
@@ -256,8 +251,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   SystemCoreClock = HSI_VALUE;
 
   /* Adapt Systick interrupt period */
-  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) {
-  {
     return HAL_ERROR;
   }
 
@@ -268,10 +262,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
 
   /* Wait till PLL is disabled */
-  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) {
-  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
-    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
-    {
       return HAL_TIMEOUT;
     }
   }
@@ -286,10 +278,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON);
 
   /* Wait till HSE is disabled */
-  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
+  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) {
-  {
+    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) {
-    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
-    {
       return HAL_TIMEOUT;
     }
   }
@@ -305,10 +295,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
 
   /* Wait till PLL2 is disabled */
-  while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET)
+  while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) {
-  {
+    if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
-    if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
-    {
       return HAL_TIMEOUT;
     }
   }
@@ -322,10 +310,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
 
   /* Wait till PLL3 is disabled */
-  while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET)
+  while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) {
-  {
+    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
-    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
-    {
       return HAL_TIMEOUT;
     }
   }
@@ -360,8 +346,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) {
-{
   uint32_t tickstart = 0U;
 
   /* Check the parameters */
@@ -370,33 +355,26 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 
   /*------------------------------- HSE Configuration ------------------------*/
   /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) {
-  {
     /* Check the parameters */
     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
 
     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
     if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
-       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
+        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) {
-    {
       /* When HSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) {
-      {
         return HAL_ERROR;
       }
       /* Otherwise, just the calibration is allowed */
-      else
+      else {
-      {
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
       }
-    }
+    } else {
-    else
-    {
       /* Check the HSI State */
-      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) {
-      {
         /* Enable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_ENABLE();
 
@@ -404,19 +382,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         tickstart = HAL_GetTick();
 
         /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) {
-        {
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
             return HAL_TIMEOUT;
           }
         }
 
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
+      } else {
-      else
-      {
         /* Disable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_DISABLE();
 
@@ -424,10 +398,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         tickstart = HAL_GetTick();
 
         /* Wait till HSI is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
-        {
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
             return HAL_TIMEOUT;
           }
         }
@@ -438,34 +410,25 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 
   /*------------------------------ LSE Configuration -------------------------*/
 
-
 #if defined(RCC_CR_PLL2ON)
   /*-------------------------------- PLL2 Configuration -----------------------*/
   /* Check the parameters */
   assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
-  if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
+  if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) {
-  {
     /* This bit can not be cleared if the PLL2 clock is used indirectly as system
       clock (i.e. it is used as PLL clock entry that is used as system clock). */
-    if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
+    if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-        (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
+        && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) {
-        ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
-    {
       return HAL_ERROR;
-    }
+    } else {
-    else
+      if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) {
-    {
-      if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
-      {
         /* Check the parameters */
         assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
         assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
 
         /* Prediv2 can be written only when the PLLI2S is disabled. */
         /* Return an error only if new value is different from the programmed value */
-        if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) {
-          (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
-        {
           return HAL_ERROR;
         }
 
@@ -476,10 +439,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         tickstart = HAL_GetTick();
 
         /* Wait till PLL2 is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) {
-        {
+          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
-          if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
-          {
             return HAL_TIMEOUT;
           }
         }
@@ -497,16 +458,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         tickstart = HAL_GetTick();
 
         /* Wait till PLL2 is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) {
-        {
+          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
-          if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
-          {
             return HAL_TIMEOUT;
           }
         }
-      }
+      } else {
-      else
-      {
         /* Set PREDIV1 source to HSE */
         CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
 
@@ -517,10 +474,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         tickstart = HAL_GetTick();
 
         /* Wait till PLL2 is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) {
-        {
+          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
-          if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
-          {
             return HAL_TIMEOUT;
           }
         }
@@ -532,13 +487,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   /*-------------------------------- PLL Configuration -----------------------*/
   /* Check the parameters */
   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) {
-  {
     /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) {
-    { 
+      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) {
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
-      {
         /* Check the parameters */
         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
@@ -550,18 +502,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         tickstart = HAL_GetTick();
 
         /* Wait till PLL is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) {
-        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
             return HAL_TIMEOUT;
           }
         }
 
         /* Configure the HSE prediv factor --------------------------------*/
         /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
-        if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
+        if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) {
-        {
           /* Check the parameter */
           assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
 #if defined(RCC_CFGR2_PREDIV1SRC)
@@ -576,8 +525,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         }
 
         /* Configure the main PLL clock source and multiplication factors. */
-        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLMUL);
-                             RCC_OscInitStruct->PLL.PLLMUL);
         /* Enable the main PLL. */
         __HAL_RCC_PLL_ENABLE();
 
@@ -585,16 +533,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         tickstart = HAL_GetTick();
 
         /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) {
-        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
             return HAL_TIMEOUT;
           }
         }
-      }
+      } else {
-      else
-      {
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
 
@@ -602,17 +546,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         tickstart = HAL_GetTick();
 
         /* Wait till PLL is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) {
-        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
             return HAL_TIMEOUT;
           }
         }
       }
-    }
+    } else {
-    else
-    {
       return HAL_ERROR;
     }
   }
@@ -643,8 +583,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
  *         currently used as system clock source.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) {
-{
   uint32_t tickstart = 0U;
 
   /* Check the parameters */
@@ -658,32 +597,27 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
 
 #if defined(FLASH_ACR_LATENCY)
   /* Increasing the number of wait states because of higher CPU frequency */
-  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+  if (FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) {
-  {    
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+    if ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) {
-    {
       return HAL_ERROR;
     }
   }
 
 #endif /* FLASH_ACR_LATENCY */
   /*-------------------------- HCLK Configuration --------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) {
-  {
     /* Set the highest APBx dividers in order to ensure that we do not go through
     a non-spec phase whatever we decrease or increase HCLK. */
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) {
-    {
       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
     }
 
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) {
-    {
       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
     }
 
@@ -693,34 +627,27 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   }
 
   /*------------------------- SYSCLK Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) {
-  {    
     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
 
     /* HSE is selected as System Clock Source */
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) {
-    {
       /* Check the HSE ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) {
-      {
         return HAL_ERROR;
       }
     }
     /* PLL is selected as System Clock Source */
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) {
-    {
       /* Check the PLL ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) {
-      {
         return HAL_ERROR;
       }
     }
     /* HSI is selected as System Clock Source */
-    else
+    else {
-    {
       /* Check the HSI ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) {
-      {
         return HAL_ERROR;
       }
     }
@@ -729,32 +656,21 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
     /* Get Start Tick */
     tickstart = HAL_GetTick();
 
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) {
-    {
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+        if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
           return HAL_TIMEOUT;
         }
       }
-    }
+    } else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) {
-    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) {
-    {
+        if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
           return HAL_TIMEOUT;
         }
       }
-    }
+    } else {
-    else
+      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) {
-    {
+        if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
-      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
-      {
-        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-        {
           return HAL_TIMEOUT;
         }
       }
@@ -762,30 +678,26 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   }
 #if defined(FLASH_ACR_LATENCY)
   /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
+  if (FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) {
-  {    
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+    if ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) {
-    {
       return HAL_ERROR;
     }
   }
 #endif /* FLASH_ACR_LATENCY */
 
   /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) {
-  {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
   }
 
   /*-------------------------- PCLK2 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) {
-  {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
   }
@@ -849,8 +761,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   *            @arg @ref RCC_MCODIV_1 no division applied to MCO clock
   * @retval None
   */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) {
-{
   GPIO_InitTypeDef gpio = {0U};
 
   /* Check the parameters */
@@ -886,19 +797,13 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
  *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
  * @retval None
  */
-void HAL_RCC_EnableCSS(void)
+void HAL_RCC_EnableCSS(void) { *(__IO uint32_t *)RCC_CR_CSSON_BB = (uint32_t)ENABLE; }
-{
-  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
-}
 
 /**
  * @brief  Disables the Clock Security System.
  * @retval None
  */
-void HAL_RCC_DisableCSS(void)
+void HAL_RCC_DisableCSS(void) { *(__IO uint32_t *)RCC_CR_CSSON_BB = (uint32_t)DISABLE; }
-{
-  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
-}
 
 /**
  * @brief  Returns the SYSCLK frequency
@@ -929,8 +834,7 @@ void HAL_RCC_DisableCSS(void)
  *
  * @retval SYSCLK frequency
  */
-uint32_t HAL_RCC_GetSysClockFreq(void)
+uint32_t HAL_RCC_GetSysClockFreq(void) {
-{
 #if defined(RCC_CFGR2_PREDIV1SRC)
   const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
   const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
@@ -952,8 +856,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
   tmpreg = RCC->CFGR;
 
   /* Get SYSCLK source -------------------------------------------------------*/
-  switch (tmpreg & RCC_CFGR_SWS)
+  switch (tmpreg & RCC_CFGR_SWS) {
-  {
   case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
   {
     sysclockfreq = HSE_VALUE;
@@ -962,8 +865,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
   case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
   {
     pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
-      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+    if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) {
-      {
 #if defined(RCC_CFGR2_PREDIV1)
       prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
 #else
@@ -971,33 +873,27 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
 #endif /*RCC_CFGR2_PREDIV1*/
 #if defined(RCC_CFGR2_PREDIV1SRC)
 
-        if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
+      if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) {
-        {
         /* PLL2 selected as Prediv1 source */
         /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
         prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
         pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
         pllclk  = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv));
-        }
+      } else {
-        else
-        {
         /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
         pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
       }
 
       /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
       /* In this case need to divide pllclk by 2 */
-        if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
+      if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) {
-        {
         pllclk = pllclk / 2;
       }
 #else
       /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
       pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
 #endif /*RCC_CFGR2_PREDIV1SRC*/
-      }
+    } else {
-      else
-      {
       /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
       pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
     }
@@ -1023,10 +919,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
  *         and updated within this function
  * @retval HCLK frequency
  */
-uint32_t HAL_RCC_GetHCLKFreq(void)
+uint32_t HAL_RCC_GetHCLKFreq(void) { return SystemCoreClock; }
-{
-  return SystemCoreClock;
-}
 
 /**
  * @brief  Returns the PCLK1 frequency
@@ -1034,8 +927,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
+uint32_t HAL_RCC_GetPCLK1Freq(void) {
-{
   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 }
@@ -1046,8 +938,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency
  */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
+uint32_t HAL_RCC_GetPCLK2Freq(void) {
-{
   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 }
@@ -1059,14 +950,12 @@ uint32_t HAL_RCC_GetPCLK2Freq(void)
  * will be configured.
  * @retval None
  */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) {
-{
   /* Check the parameters */
   assert_param(RCC_OscInitStruct != NULL);
 
   /* Set all possible values for the Oscillator type parameter ---------------*/
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-                  | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
 
 #if defined(RCC_CFGR2_PREDIV1SRC)
   /* Get the Prediv1 source --------------------------------------------------*/
@@ -1074,76 +963,53 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 #endif /* RCC_CFGR2_PREDIV1SRC */
 
   /* Get the HSE configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) {
-  {
     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
-  }
+  } else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) {
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
-  {
     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
-  }
+  } else {
-  else
-  {
     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
   }
   RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
 
   /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) {
-  {
     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
-  }
+  } else {
-  else
-  {
     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
   }
 
   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
 
   /* Get the LSE configuration -----------------------------------------------*/
-  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) {
-  {
     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
-  }
+  } else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) {
-  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
-  {
     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
-  }
+  } else {
-  else
-  {
     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
   }
 
   /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) {
-  {
     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
-  }
+  } else {
-  else
-  {
     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
   }
 
-
   /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) {
-  {
     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
-  }
+  } else {
-  else
-  {
     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
   }
   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
   RCC_OscInitStruct->PLL.PLLMUL    = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
 #if defined(RCC_CR_PLL2ON)
   /* Get the PLL2 configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
+  if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON) {
-  {
     RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
-  }
+  } else {
-  else
-  {
     RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
   }
   RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
@@ -1159,8 +1025,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
  * @param  pFLatency Pointer on the Flash Latency.
  * @retval None
  */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) {
-{
   /* Check the parameters */
   assert_param(RCC_ClkInitStruct != NULL);
   assert_param(pFLatency != NULL);
@@ -1194,11 +1059,9 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pF
  * @note This API should be called under the NMI_Handler().
  * @retval None
  */
-void HAL_RCC_NMI_IRQHandler(void)
+void HAL_RCC_NMI_IRQHandler(void) {
-{
   /* Check RCC CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  if (__HAL_RCC_GET_IT(RCC_IT_CSS)) {
-  {
     /* RCC Clock Security System interrupt user callback */
     HAL_RCC_CSSCallback();
 
@@ -1212,22 +1075,18 @@ void HAL_RCC_NMI_IRQHandler(void)
  * @param  mdelay: specifies the delay time length, in milliseconds.
  * @retval None
  */
-static void RCC_Delay(uint32_t mdelay)
+static void RCC_Delay(uint32_t mdelay) {
-{
   __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
-  do 
+  do {
-  {
     __NOP();
-  } 
+  } while (Delay--);
-  while (Delay --);
 }
 
 /**
  * @brief  RCC Clock Security System interrupt callback
  * @retval none
  */
-__weak void HAL_RCC_CSSCallback(void)
+__weak void HAL_RCC_CSSCallback(void) {
-{
   /* NOTE : This function Should not be modified, when the callback is needed,
     the HAL_RCC_CSSCallback could be implemented in the user file
     */

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c

@@ -113,8 +113,7 @@
  *
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) {
-{
   uint32_t tickstart = 0U, temp_reg = 0U;
 #if defined(STM32F105xC) || defined(STM32F107xC)
   uint32_t pllactive = 0U;
@@ -124,8 +123,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
 
   /*------------------------------- RTC/LCD Configuration ------------------------*/
-  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) {
-  {
     /* check for RTC Parameters used to output RTCCLK */
     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
 
@@ -134,24 +132,20 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
     /* As soon as function is called to change RTC clock source, activation of the
        power domain is done. */
     /* Requires to enable write access to Backup Domain of necessary */
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+    if (__HAL_RCC_PWR_IS_CLK_DISABLED()) {
-    {
       __HAL_RCC_PWR_CLK_ENABLE();
       pwrclkchanged = SET;
     }
 
-    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) {
-    {
       /* Enable write access to Backup domain */
       SET_BIT(PWR->CR, PWR_CR_DBP);
 
       /* Wait for Backup domain Write protection disable */
       tickstart = HAL_GetTick();
 
-      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) {
-      {
+        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) {
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-        {
           return HAL_TIMEOUT;
         }
       }
@@ -159,8 +153,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
     /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
     temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) {
-    {
       /* Store the content of BDCR register before the reset of Backup Domain */
       temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
       /* RTC Clock selection can be changed only if the Backup Domain is reset */
@@ -170,16 +163,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       RCC->BDCR = temp_reg;
 
       /* Wait for LSERDY if LSE was enabled */
-      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
+      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) {
-      {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
 
         /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) {
-        {
+          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) {
-          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
-          {
             return HAL_TIMEOUT;
           }
         }
@@ -188,15 +178,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
     __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 
     /* Require to disable power clock if necessary */
-    if(pwrclkchanged == SET)
+    if (pwrclkchanged == SET) {
-    {
       __HAL_RCC_PWR_CLK_DISABLE();
     }
   }
 
   /*------------------------------ ADC clock Configuration ------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) {
-  {
     /* Check the parameters */
     assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
 
@@ -206,8 +194,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(STM32F105xC) || defined(STM32F107xC)
   /*------------------------------ I2S2 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) {
-  {
     /* Check the parameters */
     assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
 
@@ -216,8 +203,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*------------------------------ I2S3 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) {
-  {
     /* Check the parameters */
     assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
 
@@ -227,27 +213,22 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
   /*------------------------------ PLL I2S Configuration ----------------------*/
   /* Check that PLLI2S need to be enabled */
-  if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
+  if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) {
-  {
     /* Update flag to indicate that PLL I2S should be active */
     pllactive = 1;
   }
 
   /* Check if PLL I2S need to be enabled */
-  if (pllactive == 1)
+  if (pllactive == 1) {
-  {
     /* Enable PLL I2S only if not active */
-    if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
+    if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) {
-    {
       /* Check the parameters */
       assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
       assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
 
       /* Prediv2 can be written only when the PLL2 is disabled. */
       /* Return an error only if new value is different from the programmed value */
-      if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
+      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) {
-        (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
-      {
         return HAL_ERROR;
       }
 
@@ -264,31 +245,23 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       tickstart = HAL_GetTick();
 
       /* Wait till PLLI2S is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) {
-      {
+        if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
-        if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-        {
           return HAL_TIMEOUT;
         }
       }
-    }
+    } else {
-    else
-    {
       /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
-      if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
+      if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) {
-      {
         return HAL_ERROR;
       }
     }
   }
 #endif /* STM32F105xC || STM32F107xC */
 
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
   /*------------------------------ USB clock Configuration ------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) {
-  {
     /* Check the parameters */
     assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
 
@@ -307,8 +280,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
  *         returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
  * @retval None
  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) {
-{
   uint32_t srcclk = 0U;
 
   /* Set all possible values for the extended clock type parameter------------*/
@@ -345,9 +317,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 
 #endif /* STM32F103xE || STM32F103xG */
 
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
   /* Get the USB clock configuration -----------------------------------------*/
   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
   PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
@@ -400,8 +370,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
   @endif
   * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
   */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) {
-{
 #if defined(STM32F105xC) || defined(STM32F107xC)
   const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
   const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
@@ -409,8 +378,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
   uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
   uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
 #endif /* STM32F105xC || STM32F107xC */
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-    defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
   const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
   const uint8_t aPredivFactorTable[2]  = {1, 2};
 
@@ -421,60 +389,46 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
   /* Check the parameters */
   assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
 
-  switch (PeriphClk)
+  switch (PeriphClk) {
-  {
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
+  case RCC_PERIPHCLK_USB: {
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-  case RCC_PERIPHCLK_USB:  
-    {
     /* Get RCC configuration ------------------------------------------------------*/
     temp_reg = RCC->CFGR;
 
     /* Check if PLL is enabled */
-      if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
+    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) {
-      {
       pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
-        if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+      if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) {
-        {
+#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE)
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
         prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
 #else
         prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
 
 #if defined(STM32F105xC) || defined(STM32F107xC)
-          if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
+        if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) {
-          {
           /* PLL2 selected as Prediv1 source */
           /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
           prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
           pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
           pllclk  = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
-          }
+        } else {
-          else
-          {
           /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
           pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
         }
 
         /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
         /* In this case need to divide pllclk by 2 */
-          if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
+        if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) {
-          {
           pllclk = pllclk / 2;
         }
 #else
-          if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
+        if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) {
-          {
           /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
           pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
         }
 #endif /* STM32F105xC || STM32F107xC */
-        }
+      } else {
-        else
-        {
         /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
         pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
       }
@@ -482,25 +436,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
       /* Calcul of the USB frequency*/
 #if defined(STM32F105xC) || defined(STM32F107xC)
       /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
-        if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
+      if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) {
-        {
         /* Prescaler of 2 selected for USB */
         frequency = pllclk;
-        }
+      } else {
-        else
-        {
         /* Prescaler of 3 selected for USB */
         frequency = (2 * pllclk) / 3;
       }
 #else
       /* USBCLK = PLLCLK / USB prescaler */
-        if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
+      if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) {
-        {
         /* No prescaler selected for USB */
         frequency = pllclk;
-        }
+      } else {
-        else
-        {
         /* Prescaler of 1.5 selected for USB */
         frequency = (pllclk * 2) / 3;
       }
@@ -510,22 +458,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
   }
 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-  case RCC_PERIPHCLK_I2S2:  
+  case RCC_PERIPHCLK_I2S2: {
-    {
 #if defined(STM32F103xE) || defined(STM32F103xG)
     /* SYSCLK used as source clock for I2S2 */
     frequency = HAL_RCC_GetSysClockFreq();
 #else
-      if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
+    if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) {
-      {
       /* SYSCLK used as source clock for I2S2 */
       frequency = HAL_RCC_GetSysClockFreq();
-      }
+    } else {
-      else
-      {
       /* Check if PLLI2S is enabled */
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
+      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) {
-        {
         /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
         prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
         pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
@@ -535,22 +478,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
 #endif /* STM32F103xE || STM32F103xG */
     break;
   }
-  case RCC_PERIPHCLK_I2S3:
+  case RCC_PERIPHCLK_I2S3: {
-    {
 #if defined(STM32F103xE) || defined(STM32F103xG)
     /* SYSCLK used as source clock for I2S3 */
     frequency = HAL_RCC_GetSysClockFreq();
 #else
-      if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
+    if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) {
-      {
       /* SYSCLK used as source clock for I2S3 */
       frequency = HAL_RCC_GetSysClockFreq();
-      }
+    } else {
-      else
-      {
       /* Check if PLLI2S is enabled */
-        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
+      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) {
-        {
         /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
         prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
         pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
@@ -561,39 +499,31 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
     break;
   }
 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-  case RCC_PERIPHCLK_RTC:  
+  case RCC_PERIPHCLK_RTC: {
-    {
     /* Get RCC BDCR configuration ------------------------------------------------------*/
     temp_reg = RCC->BDCR;
 
     /* Check if LSE is ready if RTC clock selection is LSE */
-      if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
+    if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) {
-      {
       frequency = LSE_VALUE;
     }
     /* Check if LSI is ready if RTC clock selection is LSI */
-      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+    else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) {
-      {
       frequency = LSI_VALUE;
-      }
+    } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) {
-      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
-      {
       frequency = HSE_VALUE / 128U;
     }
     /* Clock not enabled for RTC*/
-      else
+    else {
-      {
       frequency = 0U;
     }
     break;
   }
-  case RCC_PERIPHCLK_ADC:  
+  case RCC_PERIPHCLK_ADC: {
-    {
     frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
     break;
   }
-  default: 
+  default: {
-    {
     break;
   }
   }
@@ -626,22 +556,18 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
  * @note   The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) {
-{
   uint32_t tickstart = 0U;
 
   /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
-  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
+  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) {
-  {
     /* Check the parameters */
     assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
     assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
 
     /* Prediv2 can be written only when the PLL2 is disabled. */
     /* Return an error only if new value is different from the programmed value */
-    if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
+    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) {
-      (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
-    {
       return HAL_ERROR;
     }
 
@@ -652,10 +578,8 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
     tickstart = HAL_GetTick();
 
     /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) {
-    {
+      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
         return HAL_TIMEOUT;
       }
     }
@@ -663,7 +587,6 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
     /* Configure the HSE prediv2 factor --------------------------------*/
     __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
 
-
     /* Configure the main PLLI2S multiplication factors. */
     __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
 
@@ -674,16 +597,12 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
     tickstart = HAL_GetTick();
 
     /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) {
-    {
+      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
         return HAL_TIMEOUT;
       }
     }
-  }
+  } else {
-  else
-  {
     /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
     return HAL_ERROR;
   }
@@ -696,13 +615,11 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
  * @note   PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) {
-{
   uint32_t tickstart = 0U;
 
   /* Disable PLL I2S as not requested by I2S2 or I2S3*/
-  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
+  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) {
-  {
     /* Disable the main PLLI2S. */
     __HAL_RCC_PLLI2S_DISABLE();
 
@@ -710,16 +627,12 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
     tickstart = HAL_GetTick();
 
     /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) {
-    {
+      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
         return HAL_TIMEOUT;
       }
     }
-  }
+  } else {
-  else
-  {
     /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
     return HAL_ERROR;
   }
@@ -752,29 +665,22 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
  * @note   The PLL2 configuration not modified if used indirectly as system clock.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef  *PLL2Init)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) {
-{
   uint32_t tickstart = 0U;
 
   /* This bit can not be cleared if the PLL2 clock is used indirectly as system
     clock (i.e. it is used as PLL clock entry that is used as system clock). */
-  if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
+  if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-        (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
+      && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) {
-        ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
-  {
     return HAL_ERROR;
-  }
+  } else {
-  else
-  {
     /* Check the parameters */
     assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
     assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
 
     /* Prediv2 can be written only when the PLLI2S is disabled. */
     /* Return an error only if new value is different from the programmed value */
-    if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
+    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) {
-      (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
-    {
       return HAL_ERROR;
     }
 
@@ -785,10 +691,8 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef  *PLL2Init)
     tickstart = HAL_GetTick();
 
     /* Wait till PLL2 is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) {
-    {
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
-      if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
-      {
         return HAL_TIMEOUT;
       }
     }
@@ -806,10 +710,8 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef  *PLL2Init)
     tickstart = HAL_GetTick();
 
     /* Wait till PLL2 is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) {
-    {
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
-      if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
-      {
         return HAL_TIMEOUT;
       }
     }
@@ -823,20 +725,15 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef  *PLL2Init)
  * @note   PLL2 is not disabled if used indirectly as system clock.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
+HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) {
-{
   uint32_t tickstart = 0U;
 
   /* This bit can not be cleared if the PLL2 clock is used indirectly as system
     clock (i.e. it is used as PLL clock entry that is used as system clock). */
-  if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
+  if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-        (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
+      && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) {
-        ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
-  {
     return HAL_ERROR;
-  }
+  } else {
-  else
-  {
     /* Disable the main PLL2. */
     __HAL_RCC_PLL2_DISABLE();
 
@@ -844,10 +741,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
     tickstart = HAL_GetTick();
 
     /* Wait till PLL2 is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) {
-    {
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
-      if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
-      {
         return HAL_TIMEOUT;
       }
     }
@@ -876,4 +771,3 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c

@@ -114,9 +114,7 @@
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
  * @{
  */
@@ -134,7 +132,6 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha
  * @{
  */
 
-
 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
  *  @brief    Timer Hall Sensor functions
  *
@@ -162,13 +159,11 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha
  * @param  sConfig : TIM Hall Sensor configuration structure
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) {
-{
   TIM_OC_InitTypeDef OC_Config;
 
   /* Check the TIM handle allocation */
-  if(htim == NULL)
+  if (htim == NULL) {
-  {
     return HAL_ERROR;
   }
 
@@ -180,8 +175,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
 
-  if(htim->State == HAL_TIM_STATE_RESET)
+  if (htim->State == HAL_TIM_STATE_RESET) {
-  {
     /* Allocate lock resource and initialize it */
     htim->Lock = HAL_UNLOCKED;
 
@@ -241,8 +235,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
  * @param  htim : TIM Hall Sensor handle
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
 
@@ -268,8 +261,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
  * @param  htim : TIM handle
  * @retval None
  */
-__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) {
-{
   /* Prevent unused argument(s) compilation warning */
   UNUSED(htim);
   /* NOTE : This function Should not be modified, when the callback is needed,
@@ -282,8 +274,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
  * @param  htim : TIM handle
  * @retval None
  */
-__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) {
-{
   /* Prevent unused argument(s) compilation warning */
   UNUSED(htim);
   /* NOTE : This function Should not be modified, when the callback is needed,
@@ -296,8 +287,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
  * @param  htim : TIM Hall Sensor handle
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
 
@@ -317,8 +307,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
  * @param  htim : TIM Hall Sensor handle
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
 
@@ -338,8 +327,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
  * @param  htim : TIM Hall Sensor handle
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
 
@@ -362,8 +350,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
  * @param  htim : TIM handle
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
 
@@ -388,23 +375,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
  * @param  Length : The length of data to be transferred from TIM peripheral to memory.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
 
-   if((htim->State == HAL_TIM_STATE_BUSY))
+  if ((htim->State == HAL_TIM_STATE_BUSY)) {
-  {
     return HAL_BUSY;
-  }
+  } else if ((htim->State == HAL_TIM_STATE_READY)) {
-  else if((htim->State == HAL_TIM_STATE_READY))
+    if (((uint32_t)pData == 0U) && (Length > 0U)) {
-  {
-    if(((uint32_t)pData == 0U) && (Length > 0U))
-    {
       return HAL_ERROR;
-    }
+    } else {
-    else
-    {
       htim->State = HAL_TIM_STATE_BUSY;
     }
   }
@@ -435,8 +415,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
  * @param  htim : TIM handle
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
 
@@ -444,7 +423,6 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
     (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
 
-
   /* Disable the capture compare Interrupts 1 event */
   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
 
@@ -459,9 +437,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
  * @}
  */
 
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
 
 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
  *  @brief    Timer Complementary Output Compare functions
@@ -494,8 +470,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
@@ -523,8 +498,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
@@ -552,33 +526,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
-  switch (Channel)
+  switch (Channel) {
-  {
+  case TIM_CHANNEL_1: {
-    case TIM_CHANNEL_1:
-    {
     /* Enable the TIM Output Compare interrupt */
     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_2:
+  case TIM_CHANNEL_2: {
-    {
     /* Enable the TIM Output Compare interrupt */
     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_3:
+  case TIM_CHANNEL_3: {
-    {
     /* Enable the TIM Output Compare interrupt */
     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
+  } break;
-    break;
 
   default:
     break;
@@ -611,35 +577,27 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
-{
   uint32_t tmpccer = 0U;
 
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
-  switch (Channel)
+  switch (Channel) {
-  {
+  case TIM_CHANNEL_1: {
-    case TIM_CHANNEL_1:
-    {
     /* Disable the TIM Output Compare interrupt */
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_2:
+  case TIM_CHANNEL_2: {
-    {
     /* Disable the TIM Output Compare interrupt */
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_3:
+  case TIM_CHANNEL_3: {
-    {
     /* Disable the TIM Output Compare interrupt */
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
+  } break;
-    break;
 
   default:
     break;
@@ -650,8 +608,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
 
   /* Disable the TIM Break interrupt (only if no more channel is active) */
   tmpccer = htim->Instance->CCER;
-  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) {
-  {
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
   }
 
@@ -678,30 +635,21 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
  * @param  Length : The length of data to be transferred from memory to TIM peripheral
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
-  if((htim->State == HAL_TIM_STATE_BUSY))
+  if ((htim->State == HAL_TIM_STATE_BUSY)) {
-  {
     return HAL_BUSY;
-  }
+  } else if ((htim->State == HAL_TIM_STATE_READY)) {
-  else if((htim->State == HAL_TIM_STATE_READY))
+    if (((uint32_t)pData == 0U) && (Length > 0U)) {
-  {
-    if(((uint32_t)pData == 0U) && (Length > 0U))
-    {
       return HAL_ERROR;
-    }
+    } else {
-    else
-    {
       htim->State = HAL_TIM_STATE_BUSY;
     }
   }
-  switch (Channel)
+  switch (Channel) {
-  {
+  case TIM_CHANNEL_1: {
-    case TIM_CHANNEL_1:
-    {
     /* Set the DMA Period elapsed callback */
     htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
 
@@ -713,11 +661,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
 
     /* Enable the TIM Output Compare DMA request */
     __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_2:
+  case TIM_CHANNEL_2: {
-    {
     /* Set the DMA Period elapsed callback */
     htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
 
@@ -729,11 +675,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
 
     /* Enable the TIM Output Compare DMA request */
     __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_3:
+  case TIM_CHANNEL_3: {
-    {
     /* Set the DMA Period elapsed callback */
     htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
 
@@ -745,8 +689,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
 
     /* Enable the TIM Output Compare DMA request */
     __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
+  } break;
-    break;
 
   default:
     break;
@@ -776,33 +719,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
-  switch (Channel)
+  switch (Channel) {
-  {
+  case TIM_CHANNEL_1: {
-    case TIM_CHANNEL_1:
-    {
     /* Disable the TIM Output Compare DMA request */
     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_2:
+  case TIM_CHANNEL_2: {
-    {
     /* Disable the TIM Output Compare DMA request */
     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_3:
+  case TIM_CHANNEL_3: {
-    {
     /* Disable the TIM Output Compare DMA request */
     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
+  } break;
-    break;
 
   default:
     break;
@@ -868,8 +803,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
@@ -896,8 +830,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
@@ -925,33 +858,25 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
-  switch (Channel)
+  switch (Channel) {
-  {
+  case TIM_CHANNEL_1: {
-    case TIM_CHANNEL_1:
-    {
     /* Enable the TIM Capture/Compare 1 interrupt */
     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_2:
+  case TIM_CHANNEL_2: {
-    {
     /* Enable the TIM Capture/Compare 2 interrupt */
     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_3:
+  case TIM_CHANNEL_3: {
-    {
     /* Enable the TIM Capture/Compare 3 interrupt */
     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
+  } break;
-    break;
 
   default:
     break;
@@ -984,35 +909,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
-{
   uint32_t tmpccer = 0U;
 
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
-  switch (Channel)
+  switch (Channel) {
-  {
+  case TIM_CHANNEL_1: {
-    case TIM_CHANNEL_1:
-    {
     /* Disable the TIM Capture/Compare 1 interrupt */
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_2:
+  case TIM_CHANNEL_2: {
-    {
     /* Disable the TIM Capture/Compare 2 interrupt */
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_3:
+  case TIM_CHANNEL_3: {
-    {
     /* Disable the TIM Capture/Compare 3 interrupt */
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
+  } break;
-    break;
 
   default:
     break;
@@ -1023,8 +940,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
 
   /* Disable the TIM Break interrupt (only if no more channel is active) */
   tmpccer = htim->Instance->CCER;
-  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) {
-  {
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
   }
 
@@ -1051,30 +967,21 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
  * @param  Length : The length of data to be transferred from memory to TIM peripheral
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
-  if((htim->State == HAL_TIM_STATE_BUSY))
+  if ((htim->State == HAL_TIM_STATE_BUSY)) {
-  {
     return HAL_BUSY;
-  }
+  } else if ((htim->State == HAL_TIM_STATE_READY)) {
-  else if((htim->State == HAL_TIM_STATE_READY))
+    if (((uint32_t)pData == 0U) && (Length > 0U)) {
-  {
-    if(((uint32_t)pData == 0U) && (Length > 0U))
-    {
       return HAL_ERROR;
-    }
+    } else {
-    else
-    {
       htim->State = HAL_TIM_STATE_BUSY;
     }
   }
-  switch (Channel)
+  switch (Channel) {
-  {
+  case TIM_CHANNEL_1: {
-    case TIM_CHANNEL_1:
-    {
     /* Set the DMA Period elapsed callback */
     htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
 
@@ -1086,11 +993,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
 
     /* Enable the TIM Capture/Compare 1 DMA request */
     __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_2:
+  case TIM_CHANNEL_2: {
-    {
     /* Set the DMA Period elapsed callback */
     htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
 
@@ -1102,11 +1007,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
 
     /* Enable the TIM Capture/Compare 2 DMA request */
     __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_3:
+  case TIM_CHANNEL_3: {
-    {
     /* Set the DMA Period elapsed callback */
     htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
 
@@ -1118,8 +1021,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
 
     /* Enable the TIM Capture/Compare 3 DMA request */
     __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
+  } break;
-    break;
 
   default:
     break;
@@ -1149,33 +1051,25 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
-  switch (Channel)
+  switch (Channel) {
-  {
+  case TIM_CHANNEL_1: {
-    case TIM_CHANNEL_1:
-    {
     /* Disable the TIM Capture/Compare 1 DMA request */
     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_2:
+  case TIM_CHANNEL_2: {
-    {
     /* Disable the TIM Capture/Compare 2 DMA request */
     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
+  } break;
-    break;
 
-    case TIM_CHANNEL_3:
+  case TIM_CHANNEL_3: {
-    {
     /* Disable the TIM Capture/Compare 3 DMA request */
     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
+  } break;
-    break;
 
   default:
     break;
@@ -1229,8 +1123,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
 
@@ -1254,8 +1147,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
-{
 
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
@@ -1283,8 +1175,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
 
@@ -1314,8 +1205,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
 
@@ -1363,9 +1253,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
   * @{
   */
 
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
 
 /**
  * @brief  Configure the TIM commutation event sequence.
@@ -1389,17 +1277,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
 
   __HAL_LOCK(htim);
 
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) {
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {
     /* Select the Input trigger */
     htim->Instance->SMCR &= ~TIM_SMCR_TS;
     htim->Instance->SMCR |= InputTrigger;
@@ -1438,17 +1323,14 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint
  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
 
   __HAL_LOCK(htim);
 
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) {
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {
     /* Select the Input trigger */
     htim->Instance->SMCR &= ~TIM_SMCR_TS;
     htim->Instance->SMCR |= InputTrigger;
@@ -1491,17 +1373,14 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u
  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
 
   __HAL_LOCK(htim);
 
-  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) {
-      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {
     /* Select the Input trigger */
     htim->Instance->SMCR &= ~TIM_SMCR_TS;
     htim->Instance->SMCR |= InputTrigger;
@@ -1535,9 +1414,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim,
  *         contains the BDTR Register configuration  information for the TIM peripheral.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) {
-                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
-{
   uint32_t tmpbdtr = 0U;
 
   /* Check the parameters */
@@ -1586,8 +1463,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
  *         mode.
  * @retval HAL status
  */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) {
-{
   /* Check the parameters */
   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
@@ -1639,8 +1515,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
  * @param  htim : TIM handle
  * @retval None
  */
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) {
-{
   /* Prevent unused argument(s) compilation warning */
   UNUSED(htim);
   /* NOTE : This function Should not be modified, when the callback is needed,
@@ -1653,8 +1528,7 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
  * @param  htim : TIM handle
  * @retval None
  */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) {
-{
   /* Prevent unused argument(s) compilation warning */
   UNUSED(htim);
   /* NOTE : This function Should not be modified, when the callback is needed,
@@ -1667,8 +1541,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
  * @param  hdma : pointer to DMA handle.
  * @retval None
  */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) {
-{
   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   htim->State = HAL_TIM_STATE_READY;
@@ -1680,9 +1553,7 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
  * @}
  */
 
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
 
 /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
  *  @brief   Extension Peripheral State functions
@@ -1704,10 +1575,7 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
  * @param  htim : TIM Hall Sensor handle
  * @retval HAL state
  */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) { return htim->State; }
-{
-  return htim->State;
-}
 
 /**
  * @}
@@ -1720,9 +1588,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
  * @}
  */
 
-#if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
+#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-    defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
-    defined (STM32F105xC) || defined (STM32F107xC)
 
 /** @addtogroup TIMEx_Private_Functions
  * @{
@@ -1740,8 +1606,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
  * @retval None
  */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) {
-{
   uint32_t tmp = 0U;
 
   tmp = TIM_CCER_CC1NE << Channel;

source/Core/BSP/Miniware/flash.c

@@ -5,10 +5,10 @@
  *      Author: Ralim
  */
 
-#include "BSP_Flash.h"
 #include "BSP.h"
-#include "string.h"
+#include "BSP_Flash.h"
 #include "stm32f1xx_hal.h"
+#include "string.h"
 
 static uint16_t settings_page[512] __attribute__((section(".settings_page")));
 
@@ -20,8 +20,7 @@ uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
   pEraseInit.PageAddress  = (uint32_t)settings_page;
   uint32_t failingAddress = 0;
   resetWatchdog();
-	__HAL_FLASH_CLEAR_FLAG(
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_BSY);
-			FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_BSY);
   HAL_FLASH_Unlock();
   HAL_Delay(1);
   resetWatchdog();
@@ -33,14 +32,10 @@ uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
   HAL_FLASH_Unlock();
   for (uint8_t i = 0; i < (length / 2); i++) {
     resetWatchdog();
-		HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,
+    HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, (uint32_t)&settings_page[i], data[i]);
-				(uint32_t) &settings_page[i], data[i]);
   }
   HAL_FLASH_Lock();
   return 1;
 }
 
-void flash_read_buffer(uint8_t *buffer, const uint16_t length) {
+void flash_read_buffer(uint8_t *buffer, const uint16_t length) { memcpy(buffer, settings_page, length); }
-
-	memcpy(buffer, settings_page, length);
-}

source/Core/BSP/Miniware/fusb302b.cpp

@@ -17,10 +17,10 @@
 #include "Model_Config.h"
 #ifdef POW_PD
 #include "BSP.h"
-#include "fusb302b.h"
 #include "I2CBB.hpp"
-#include <pd.h>
+#include "fusb302b.h"
 #include "int_n.h"
+#include <pd.h>
 /*
  * Read a single byte from the FUSB302B
  *
@@ -45,9 +45,7 @@ static uint8_t fusb_read_byte(uint8_t addr) {
  * size: The number of bytes to read
  * buf: The buffer into which data will be read
  */
-static bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) {
+static bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) { return I2CBB::Mem_Read(FUSB302B_ADDR, addr, buf, size); }
-	return I2CBB::Mem_Read(FUSB302B_ADDR, addr, buf, size);
-}
 
 /*
  * Write a single byte to the FUSB302B
@@ -56,9 +54,7 @@ static bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) {
  * addr: The memory address to which we will write
  * byte: The value to write
  */
-static bool fusb_write_byte(uint8_t addr, uint8_t byte) {
+static bool fusb_write_byte(uint8_t addr, uint8_t byte) { return I2CBB::Mem_Write(FUSB302B_ADDR, addr, (uint8_t *)&byte, 1); }
-	return I2CBB::Mem_Write(FUSB302B_ADDR, addr, (uint8_t*) &byte, 1);
-}
 
 /*
  * Write multiple bytes to the FUSB302B
@@ -68,26 +64,15 @@ static bool fusb_write_byte(uint8_t addr, uint8_t byte) {
  * size: The number of bytes to write
  * buf: The buffer to write
  */
-static bool fusb_write_buf(uint8_t addr, uint8_t size, const uint8_t *buf) {
+static bool fusb_write_buf(uint8_t addr, uint8_t size, const uint8_t *buf) { return I2CBB::Mem_Write(FUSB302B_ADDR, addr, buf, size); }
-	return I2CBB::Mem_Write(FUSB302B_ADDR, addr, buf, size);
-}
 
 void fusb_send_message(const union pd_msg *msg) {
   if (!I2CBB::lock2()) {
     return;
   }
   /* Token sequences for the FUSB302B */
-	static uint8_t sop_seq[5] = {
+  static uint8_t       sop_seq[5] = {FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP2, FUSB_FIFO_TX_PACKSYM};
-	FUSB_FIFO_TX_SOP1,
+  static const uint8_t eop_seq[4] = {FUSB_FIFO_TX_JAM_CRC, FUSB_FIFO_TX_EOP, FUSB_FIFO_TX_TXOFF, FUSB_FIFO_TX_TXON};
-	FUSB_FIFO_TX_SOP1,
-	FUSB_FIFO_TX_SOP1,
-	FUSB_FIFO_TX_SOP2,
-	FUSB_FIFO_TX_PACKSYM };
-	static const uint8_t eop_seq[4] = {
-	FUSB_FIFO_TX_JAM_CRC,
-	FUSB_FIFO_TX_EOP,
-	FUSB_FIFO_TX_TXOFF,
-	FUSB_FIFO_TX_TXON };
 
   /* Take the I2C2 mutex now so there can't be a race condition on sop_seq */
   /* Get the length of the message: a two-octet header plus NUMOBJ four-octet
@@ -103,7 +88,6 @@ void fusb_send_message(const union pd_msg *msg) {
   fusb_write_buf(FUSB_FIFOS, 4, eop_seq);
 
   I2CBB::unlock2();
-
 }
 
 uint8_t fusb_read_message(union pd_msg *msg) {
@@ -169,8 +153,7 @@ bool fusb_setup() {
   // set defaults
   fusb_write_byte(FUSB_CONTROL2, 0x00);
   /* Flush the RX buffer */
-	fusb_write_byte( FUSB_CONTROL1,
+  fusb_write_byte(FUSB_CONTROL1, FUSB_CONTROL1_RX_FLUSH);
-	FUSB_CONTROL1_RX_FLUSH);
 
   /* Measure CC1 */
   fusb_write_byte(FUSB_SWITCHES0, 0x07);
@@ -215,7 +198,6 @@ void fusb_get_status(union fusb_status *status) {
   if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
     I2CBB::unlock2();
   }
-
 }
 
 enum fusb_typec_current fusb_get_typec_current() {
@@ -225,8 +207,7 @@ enum fusb_typec_current fusb_get_typec_current() {
     }
   }
   /* Read the BC_LVL into a variable */
-	enum fusb_typec_current bc_lvl = (enum fusb_typec_current) (fusb_read_byte(
+  enum fusb_typec_current bc_lvl = (enum fusb_typec_current)(fusb_read_byte(FUSB_STATUS0) & FUSB_STATUS0_BC_LVL);
-	FUSB_STATUS0) & FUSB_STATUS0_BC_LVL);
   if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
     I2CBB::unlock2();
   }

source/Core/BSP/Miniware/logo.cpp

@@ -23,4 +23,3 @@ uint8_t showBootLogoIfavailable() {
   OLED::refresh();
   return 1;
 }
-

source/Core/BSP/Miniware/port.c

@@ -163,8 +163,7 @@ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 #if (configASSERT_DEFINED == 1)
 static uint8_t                       ucMaxSysCallPriority         = 0;
 static uint32_t                      ulMaxPRIGROUPValue           = 0;
-static const volatile uint8_t *const pcInterruptPriorityRegisters =
+static const volatile uint8_t *const pcInterruptPriorityRegisters = (const volatile uint8_t *const)portNVIC_IP_REGISTERS_OFFSET_16;
-		(const volatile uint8_t* const ) portNVIC_IP_REGISTERS_OFFSET_16;
 #endif /* configASSERT_DEFINED */
 
 /*-----------------------------------------------------------*/
@@ -172,8 +171,7 @@ static const volatile uint8_t *const pcInterruptPriorityRegisters =
 /*
  * See header file for description.
  */
-StackType_t* pxPortInitialiseStack(StackType_t *pxTopOfStack,
+StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) {
-		TaskFunction_t pxCode, void *pvParameters) {
   /* Simulate the stack frame as it would be created by a context switch
    interrupt. */
   pxTopOfStack--;                   /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
@@ -214,8 +212,7 @@ static void prvTaskExitError(void) {
 /*-----------------------------------------------------------*/
 
 void vPortSVCHandler(void) {
-	__asm volatile (
+  __asm volatile("	ldr	r3, pxCurrentTCBConst2		\n"                 /* Restore the context. */
-			"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
                  "	ldr r1, [r3]					\n"         /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
                  "	ldr r0, [r1]					\n"         /* The first item in pxCurrentTCB is the task top of stack. */
                  "	ldmia r0!, {r4-r11}				\n"         /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
@@ -227,14 +224,12 @@ void vPortSVCHandler(void) {
                  "	bx r14							\n"
                  "									\n"
                  "	.align 4						\n"
-			"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+                 "pxCurrentTCBConst2: .word pxCurrentTCB				\n");
-	);
 }
 /*-----------------------------------------------------------*/
 
 static void prvPortStartFirstTask(void) {
-	__asm volatile(
+  __asm volatile(" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
-			" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
                  " ldr r0, [r0] 			\n"
                  " ldr r0, [r0] 			\n"
                  " msr msp, r0			\n"         /* Set the msp back to the start of the stack. */
@@ -243,8 +238,7 @@ static void prvPortStartFirstTask(void) {
                  " dsb					\n"
                  " isb					\n"
                  " svc 0					\n" /* System call to start first task. */
-			" nop					\n"
+                 " nop					\n");
-	);
 }
 /*-----------------------------------------------------------*/
 
@@ -259,9 +253,7 @@ BaseType_t xPortStartScheduler(void) {
 #if (configASSERT_DEFINED == 1)
   {
     volatile uint32_t       ulOriginalPriority;
-		volatile uint8_t *const pucFirstUserPriorityRegister =
+    volatile uint8_t *const pucFirstUserPriorityRegister = (volatile uint8_t *const)(portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER);
-				(volatile uint8_t* const ) ( portNVIC_IP_REGISTERS_OFFSET_16
-						+ portFIRST_USER_INTERRUPT_NUMBER);
     volatile uint8_t        ucMaxPriorityValue;
 
     /* Determine the maximum priority from which ISR safe FreeRTOS API
@@ -280,8 +272,7 @@ BaseType_t xPortStartScheduler(void) {
     ucMaxPriorityValue = *pucFirstUserPriorityRegister;
 
     /* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY
+    ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-				& ucMaxPriorityValue;
 
     /* Calculate the maximum acceptable priority group value for the number
      of bits read back. */
@@ -382,9 +373,7 @@ void vPortExitCritical(void) {
 void xPortPendSVHandler(void) {
   /* This is a naked function. */
 
-	__asm volatile
+  __asm volatile("	mrs r0, psp							\n"
-	(
-			"	mrs r0, psp							\n"
                  "	isb									\n"
                  "										\n"
                  "	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
@@ -409,9 +398,7 @@ void xPortPendSVHandler(void) {
                  "	bx r14								\n"
                  "										\n"
                  "	.align 4							\n"
-			"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+                 "pxCurrentTCBConst: .word pxCurrentTCB	\n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY));
-			::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
-	);
 }
 /*-----------------------------------------------------------*/
 
@@ -435,14 +422,12 @@ void xPortSysTickHandler(void) {
 
 #if (configUSE_TICKLESS_IDLE == 1)
 
-	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+__attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) {
-	{
   uint32_t   ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
   TickType_t xModifiableIdleTime;
 
   /* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+  if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks) {
-		{
     xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
   }
 
@@ -456,8 +441,7 @@ void xPortSysTickHandler(void) {
   tick periods.  -1 is used because this code will execute part way
   through one of the tick periods. */
   ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + (ulTimerCountsForOneTick * (xExpectedIdleTime - 1UL));
-		if( ulReloadValue > ulStoppedTimerCompensation )
+  if (ulReloadValue > ulStoppedTimerCompensation) {
-		{
     ulReloadValue -= ulStoppedTimerCompensation;
   }
 
@@ -469,8 +453,7 @@ void xPortSysTickHandler(void) {
 
   /* If a context switch is pending or a task is waiting for the scheduler
   to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+  if (eTaskConfirmSleepModeStatus() == eAbortSleep) {
-		{
     /* Restart from whatever is left in the count register to complete
     this tick period. */
     portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
@@ -485,9 +468,7 @@ void xPortSysTickHandler(void) {
     /* Re-enable interrupts - see comments above the cpsid instruction()
     above. */
     __asm volatile("cpsie i" ::: "memory");
-		}
+  } else {
-		else
-		{
     /* Set the new reload value. */
     portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
 
@@ -505,8 +486,7 @@ void xPortSysTickHandler(void) {
     time variable must remain unmodified, so a copy is taken. */
     xModifiableIdleTime = xExpectedIdleTime;
     configPRE_SLEEP_PROCESSING(xModifiableIdleTime);
-			if( xModifiableIdleTime > 0 )
+    if (xModifiableIdleTime > 0) {
-			{
       __asm volatile("dsb" ::: "memory");
       __asm volatile("wfi");
       __asm volatile("isb");
@@ -542,8 +522,7 @@ void xPortSysTickHandler(void) {
     correct for the entire expected idle time) or if the SysTick is yet
     to count to zero (in which case an interrupt other than the SysTick
     must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+    if ((portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT) != 0) {
-			{
       uint32_t ulCalculatedLoadValue;
 
       /* The tick interrupt is already pending, and the SysTick count
@@ -555,8 +534,7 @@ void xPortSysTickHandler(void) {
       /* Don't allow a tiny value, or values that have somehow
       underflowed because the post sleep hook did something
       that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+      if ((ulCalculatedLoadValue < ulStoppedTimerCompensation) || (ulCalculatedLoadValue > ulTimerCountsForOneTick)) {
-				{
         ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL);
       }
 
@@ -566,9 +544,7 @@ void xPortSysTickHandler(void) {
       function exits, the tick value maintained by the tick is stepped
       forward by one less than the time spent waiting. */
       ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
+    } else {
-			else
-			{
       /* Something other than the tick interrupt ended the sleep.
       Work out how long the sleep lasted rounded to complete tick
       periods (not the ulReload value which accounted for part
@@ -619,10 +595,8 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt(void) {
   portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
   /* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ)
+  portNVIC_SYSTICK_LOAD_REG = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ) - 1UL;
-			- 1UL;
+  portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT);
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT
-			| portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT);
 }
 /*-----------------------------------------------------------*/
 
@@ -679,9 +653,7 @@ void vPortValidateInterruptPriority(void) {
    scheduler.  Note however that some vendor specific peripheral libraries
    assume a non-zero priority group setting, in which cases using a value
    of zero will result in unpredictable behaviour. */
-	configASSERT(
+  configASSERT((portAIRCR_REG & portPRIORITY_GROUP_MASK) <= ulMaxPRIGROUPValue);
-			( portAIRCR_REG & portPRIORITY_GROUP_MASK) <= ulMaxPRIGROUPValue);
 }
 
 #endif /* configASSERT_DEFINED */
-

source/Core/BSP/Miniware/portmacro.h

@@ -88,7 +88,9 @@ typedef uint32_t TickType_t;
 
 #define portNVIC_INT_CTRL_REG  (*((volatile uint32_t *)0xe000ed04))
 #define portNVIC_PENDSVSET_BIT (1UL << 28UL)
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portEND_SWITCHING_ISR(xSwitchRequired) \
+  if (xSwitchRequired != pdFALSE)              \
+  portYIELD()
 #define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
 /*-----------------------------------------------------------*/
 
@@ -126,8 +128,7 @@ extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
 /* Generic helper function. */
-__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros(
+__attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros(uint32_t ulBitmap) {
-		uint32_t ulBitmap) {
   uint8_t ucReturn;
 
   __asm volatile("clz %0, %1" : "=r"(ucReturn) : "r"(ulBitmap) : "memory");
@@ -188,14 +189,13 @@ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) {
 portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
   uint32_t ulNewBASEPRI;
 
-	__asm volatile
+  __asm volatile("	mov %0, %1												\n"
-	(
-			"	mov %0, %1												\n"
                  "	msr basepri, %0											\n"
                  "	isb														\n"
                  "	dsb														\n"
-			:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+                 : "=r"(ulNewBASEPRI)
-	);
+                 : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+                 : "memory");
 }
 
 /*-----------------------------------------------------------*/
@@ -203,15 +203,14 @@ portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) {
   uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
 
-	__asm volatile
+  __asm volatile("	mrs %0, basepri											\n"
-	(
-			"	mrs %0, basepri											\n"
                  "	mov %1, %2												\n"
                  "	msr basepri, %1											\n"
                  "	isb														\n"
                  "	dsb														\n"
-			:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+                 : "=r"(ulOriginalBASEPRI), "=r"(ulNewBASEPRI)
-	);
+                 : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+                 : "memory");
 
   /* This return will not be reached but is necessary to prevent compiler
    warnings. */
@@ -219,12 +218,7 @@ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) {
 }
 /*-----------------------------------------------------------*/
 
-portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) {
+portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { __asm volatile("	msr basepri, %0	" ::"r"(ulNewMaskValue) : "memory"); }
-	__asm volatile
-	(
-			"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
-	);
-}
 /*-----------------------------------------------------------*/
 
 #define portMEMORY_BARRIER() __asm volatile("" ::: "memory")
@@ -234,4 +228,3 @@ portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) {
 #endif
 
 #endif /* PORTMACRO_H */
-

source/Core/BSP/Miniware/postRTOS.cpp

@@ -1,14 +1,14 @@
 #include "BSP.h"
 #include "FreeRTOS.h"
+#include "I2C_Wrapper.hpp"
 #include "QC3.h"
 #include "Settings.h"
 #include "cmsis_os.h"
+#include "fusbpd.h"
 #include "main.hpp"
 #include "power.hpp"
 #include "stdlib.h"
 #include "task.h"
-#include "I2C_Wrapper.hpp"
-#include "fusbpd.h"
 
 // Initialisation to be performed with scheduler active
 void postRToSInit() {

source/Core/BSP/Miniware/preRTOS.cpp

@@ -5,13 +5,13 @@
  *      Author: Ralim
  */
 
-#include <I2C_Wrapper.hpp>
 #include "BSP.h"
-#include "Setup.h"
-#include "Pins.h"
 #include "I2CBB.hpp"
-#include "fusbpd.h"
 #include "Model_Config.h"
+#include "Pins.h"
+#include "Setup.h"
+#include "fusbpd.h"
+#include <I2C_Wrapper.hpp>
 void preRToSInit() {
   /* Reset of all peripherals, Initializes the Flash interface and the Systick.
    */

source/Core/BSP/Miniware/stm32f1xx_hal_msp.c

@@ -1,12 +1,11 @@
 #include "Pins.h"
-#include "stm32f1xx_hal.h"
 #include "Setup.h"
+#include "stm32f1xx_hal.h"
 /**
  * Initializes the Global MSP.
  */
 void HAL_MspInit(void) {
-	__HAL_RCC_AFIO_CLK_ENABLE()
+  __HAL_RCC_AFIO_CLK_ENABLE();
-	;
 
   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 
@@ -25,15 +24,13 @@ void HAL_MspInit(void) {
   HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
   /* SysTick_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
-
 }
 
 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {
 
   GPIO_InitTypeDef GPIO_InitStruct;
   if (hadc->Instance == ADC1) {
-		__HAL_RCC_ADC1_CLK_ENABLE()
+    __HAL_RCC_ADC1_CLK_ENABLE();
-		;
 
     /* ADC1 DMA Init */
     /* ADC1 Init */
@@ -53,8 +50,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {
     HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0);
     HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
   } else {
-		__HAL_RCC_ADC2_CLK_ENABLE()
+    __HAL_RCC_ADC2_CLK_ENABLE();
-		;
 
     /**ADC2 GPIO Configuration
      PB0     ------> ADC2_IN8
@@ -74,7 +70,6 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {
     HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0);
     HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
   }
-
 }
 
 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) {
@@ -91,8 +86,7 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) {
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
   /* Peripheral clock enable */
-	__HAL_RCC_I2C1_CLK_ENABLE()
+  __HAL_RCC_I2C1_CLK_ENABLE();
-	;
   /* I2C1 DMA Init */
   /* I2C1_RX Init */
   hdma_i2c1_rx.Instance                 = DMA1_Channel7;
@@ -125,17 +119,14 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) {
   HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
   HAL_NVIC_SetPriority(I2C1_ER_IRQn, 15, 0);
   HAL_NVIC_EnableIRQ(I2C1_ER_IRQn);
-
 }
 
 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base) {
   if (htim_base->Instance == TIM3) {
     /* Peripheral clock enable */
-		__HAL_RCC_TIM3_CLK_ENABLE()
+    __HAL_RCC_TIM3_CLK_ENABLE();
-		;
   } else if (htim_base->Instance == TIM2) {
     /* Peripheral clock enable */
-		__HAL_RCC_TIM2_CLK_ENABLE()
+    __HAL_RCC_TIM2_CLK_ENABLE();
-		;
   }
 }

source/Core/BSP/Miniware/stm32f1xx_it.c

@@ -1,9 +1,9 @@
 // This is the stock standard STM interrupt file full of handlers
-#include "stm32f1xx_hal.h"
-#include "stm32f1xx.h"
 #include "stm32f1xx_it.h"
-#include "cmsis_os.h"
 #include "Setup.h"
+#include "cmsis_os.h"
+#include "stm32f1xx.h"
+#include "stm32f1xx_hal.h"
 
 extern TIM_HandleTypeDef htim1; // used for the systick
 
@@ -11,32 +11,24 @@ extern TIM_HandleTypeDef htim1; //used for the systick
 /*            Cortex-M3 Processor Interruption and Exception Handlers         */
 /******************************************************************************/
 
-void NMI_Handler(void) {
+void NMI_Handler(void) {}
-}
 
 // We have the assembly for a breakpoint trigger here to halt the system when a debugger is connected
 // Hardfault handler, often a screwup in the code
-void HardFault_Handler(void) {
+void HardFault_Handler(void) {}
-}
 
 // Memory management unit had an error
-void MemManage_Handler(void) {
+void MemManage_Handler(void) {}
-}
 
 // Prefetcher or busfault occured
-void BusFault_Handler(void) {
+void BusFault_Handler(void) {}
-}
 
-void UsageFault_Handler(void) {
+void UsageFault_Handler(void) {}
-}
 
-void DebugMon_Handler(void) {
+void DebugMon_Handler(void) {}
-}
 
 // Systick is used by FreeRTOS tick
-void SysTick_Handler(void) {
+void SysTick_Handler(void) { osSystickHandler(); }
-	osSystickHandler();
-}
 
 /******************************************************************************/
 /* STM32F1xx Peripheral Interrupt Handlers                                    */
@@ -46,42 +38,22 @@ void SysTick_Handler(void) {
 /******************************************************************************/
 
 // DMA used to move the ADC readings into system ram
-void DMA1_Channel1_IRQHandler(void) {
+void DMA1_Channel1_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_adc1); }
-	HAL_DMA_IRQHandler(&hdma_adc1);
-}
 // ADC interrupt used for DMA
-void ADC1_2_IRQHandler(void) {
+void ADC1_2_IRQHandler(void) { HAL_ADC_IRQHandler(&hadc1); }
-	HAL_ADC_IRQHandler(&hadc1);
-}
 
 // Timer 1 has overflowed, used for HAL ticks
-void TIM1_UP_IRQHandler(void) {
+void TIM1_UP_IRQHandler(void) { HAL_TIM_IRQHandler(&htim1); }
-	HAL_TIM_IRQHandler(&htim1);
-}
 // Timer 3 is used for the PWM output to the tip
-void TIM3_IRQHandler(void) {
+void TIM3_IRQHandler(void) { HAL_TIM_IRQHandler(&htim3); }
-	HAL_TIM_IRQHandler(&htim3);
-}
 
 // Timer 2 is used for co-ordination of PWM & ADC
-void TIM2_IRQHandler(void) {
+void TIM2_IRQHandler(void) { HAL_TIM_IRQHandler(&htim2); }
-	HAL_TIM_IRQHandler(&htim2);
-}
 
-void I2C1_EV_IRQHandler(void) {
+void I2C1_EV_IRQHandler(void) { HAL_I2C_EV_IRQHandler(&hi2c1); }
-	HAL_I2C_EV_IRQHandler(&hi2c1);
+void I2C1_ER_IRQHandler(void) { HAL_I2C_ER_IRQHandler(&hi2c1); }
-}
-void I2C1_ER_IRQHandler(void) {
-	HAL_I2C_ER_IRQHandler(&hi2c1);
-}
 
-void DMA1_Channel6_IRQHandler(void) {
+void DMA1_Channel6_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_i2c1_tx); }
-	HAL_DMA_IRQHandler(&hdma_i2c1_tx);
-}
 
-void DMA1_Channel7_IRQHandler(void) {
+void DMA1_Channel7_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_i2c1_rx); }
-	HAL_DMA_IRQHandler(&hdma_i2c1_rx);
+void EXTI9_5_IRQHandler(void) { HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); }
-}
-void EXTI9_5_IRQHandler(void) {
-	HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
-}

source/Core/BSP/Miniware/system_stm32f1xx.c

@@ -3,7 +3,8 @@
 #include "stm32f1xx.h"
 
 #if !defined(HSI_VALUE)
-  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
+#define HSI_VALUE                                               \
+  8000000U /*!< Default value of the Internal oscillator in Hz. \
                 This value can be provided and adapted by the user application. */
 #endif     /* HSI_VALUE */
 
@@ -13,7 +14,8 @@
 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
 
 #ifndef VECT_TAB_OFFSET
-#define VECT_TAB_OFFSET  0x00004000U /*!< Vector Table base offset field.
+#define VECT_TAB_OFFSET                            \
+  0x00004000U /*!< Vector Table base offset field. \
            This value must be a multiple of 0x200. */
 // We offset this by 0x4000 to because of the bootloader
 #endif
@@ -27,8 +29,7 @@
 uint32_t SystemCoreClock = 64000000U; /*!< System Clock Frequency (Core Clock) */
 #endif
 
-const uint8_t AHBPrescTable[16U] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7,
+const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-		8, 9 };
 const uint8_t APBPrescTable[8U]  = {0, 0, 0, 0, 1, 2, 3, 4};
 
 /**
@@ -178,34 +179,25 @@ void SystemCoreClockUpdate(void) {
 #else
     pllmull = pllmull >> 18U;
 
-      if (pllmull != 0x0DU)
+    if (pllmull != 0x0DU) {
-      {
       pllmull += 2U;
-      }
+    } else { /* PLL multiplication factor = PLL input clock * 6.5 */
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
       pllmull = 13U / 2U;
     }
 
-      if (pllsource == 0x00U)
+    if (pllsource == 0x00U) {
-      {
       /* HSI oscillator clock divided by 2 selected as PLL clock entry */
       SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
-      }
+    } else { /* PREDIV1 selected as PLL clock entry */
-      else
-      {/* PREDIV1 selected as PLL clock entry */
 
       /* Get PREDIV1 clock source and division factor */
       prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
 
-        if (prediv1source == 0U)
+      if (prediv1source == 0U) {
-        { 
         /* HSE oscillator clock selected as PREDIV1 clock entry */
         SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
-        }
+      } else { /* PLL2 clock selected as PREDIV1 clock entry */
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
 
         /* Get PREDIV2 division factor and PLL2 multiplication factor */
         prediv2factor   = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
@@ -245,8 +237,7 @@ void SystemCoreClockUpdate(void) {
  * @param  None
  * @retval None
  */
-void SystemInit_ExtMemCtl(void) 
+void SystemInit_ExtMemCtl(void) {
-{
   __IO uint32_t tmpreg;
   /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
     required, then adjust the Register Addresses */

source/Core/BSP/Pine64/BSP.cpp

@@ -17,9 +17,7 @@ uint16_t totalPWM; // htim2.Init.Period, the full PWM cycle
 
 // 2 second filter (ADC is PID_TIM_HZ Hz)
 history<uint16_t, PID_TIM_HZ> rawTempFilter = {{0}, 0, 0};
-void resetWatchdog() {
+void                          resetWatchdog() { fwdgt_counter_reload(); }
-	fwdgt_counter_reload();
-}
 
 uint16_t getTipInstantTemperature() {
   volatile uint16_t sum = 0; // 12 bit readings * 8*2 -> 16 bits
@@ -90,8 +88,7 @@ uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) {
 void unstick_I2C() {
   /* configure SDA/SCL for GPIO */
   GPIO_BC(GPIOB) |= SDA_Pin | SCL_Pin;
-	gpio_init(SDA_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ,
+  gpio_init(SDA_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin);
-	SDA_Pin | SCL_Pin);
   asm("nop");
   asm("nop");
   asm("nop");
@@ -106,26 +103,18 @@ void unstick_I2C() {
   GPIO_BOP(GPIOB) |= SDA_Pin;
   /* connect PB6 to I2C0_SCL */
   /* connect PB7 to I2C0_SDA */
-	gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ,
+  gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin);
-	SDA_Pin | SCL_Pin);
 }
 
-uint8_t getButtonA() {
+uint8_t getButtonA() { return (gpio_input_bit_get(KEY_A_GPIO_Port, KEY_A_Pin) == SET) ? 1 : 0; }
-	return (gpio_input_bit_get(KEY_A_GPIO_Port, KEY_A_Pin) == SET) ? 1 : 0;
+uint8_t getButtonB() { return (gpio_input_bit_get(KEY_B_GPIO_Port, KEY_B_Pin) == SET) ? 1 : 0; }
-}
-uint8_t getButtonB() {
-	return (gpio_input_bit_get(KEY_B_GPIO_Port, KEY_B_Pin) == SET) ? 1 : 0;
-}
 
 void reboot() {
   // Spin for watchdog
-	for (;;) {
+  for (;;) {}
-	}
 }
 
-void delay_ms(uint16_t count) {
+void     delay_ms(uint16_t count) { delay_1ms(count); }
-	delay_1ms(count);
-}
 uint32_t __get_IPSR(void) {
   return 0; // To shut-up CMSIS
 }

source/Core/BSP/Pine64/FreeRTOSConfig.h

@@ -1,7 +1,7 @@
 #ifndef FREERTOS_CONFIG_H
 #define FREERTOS_CONFIG_H
-#include <stdint.h>
 #include "nuclei_sdk_soc.h"
+#include <stdint.h>
 // RISC-V configuration
 #define USER_MODE_TASKS 0
 
@@ -67,8 +67,7 @@
 
 /* Define to trap errors during development. */
 #define configASSERT(x)       \
-    if ((x) == 0)                 \
+  if ((x) == 0) {             \
-    {                             \
     taskDISABLE_INTERRUPTS(); \
     for (;;)                  \
       ;                       \

source/Core/BSP/Pine64/I2C_Wrapper.cpp

@@ -15,9 +15,7 @@ void FRToSI2C::CpltCallback() {
   // TODO
 }
 
-bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) {
+bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }
-	return Mem_Write(address, reg, &data, 1);
-}
 
 uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) {
   uint8_t temp = 0;
@@ -195,9 +193,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
           /* enable DMA0 channel5 */
           dma_channel_enable(DMA0, DMA_CH6);
           /* wait until BTC bit is set */
-					while (!dma_flag_get(DMA0, DMA_CH6, DMA_FLAG_FTF)) {
+          while (!dma_flag_get(DMA0, DMA_CH6, DMA_FLAG_FTF)) {}
-
-					}
           /* send a stop condition to I2C bus*/
           i2c_stop_on_bus(I2C0);
         }
@@ -343,12 +339,9 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
       /* enable DMA0 channel5 */
       dma_channel_enable(DMA0, DMA_CH5);
       /* wait until BTC bit is set */
-			while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {
+      while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {}
-
-			}
       /* wait until BTC bit is set */
-			while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) {
+      while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) {}
-			}
       state = I2C_STOP;
       break;
     case I2C_STOP:
@@ -379,18 +372,14 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
   return timedout == false;
 }
 
-bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
+bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) { return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1); }
-	return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1);
-}
 
 bool FRToSI2C::probe(uint16_t DevAddress) {
   uint8_t temp[1];
   return Mem_Read(DevAddress, 0x00, temp, sizeof(temp));
 }
 
-void FRToSI2C::I2C_Unstick() {
+void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
-	unstick_I2C();
-}
 
 bool FRToSI2C::lock() {
   if (I2CSemaphore == nullptr) {

source/Core/BSP/Pine64/IRQ.cpp

@@ -119,8 +119,6 @@ void EXTI5_9_IRQHandler(void) {
 }
 
 // These are unused for now
-void I2C0_EV_IRQHandler(void) {
+void I2C0_EV_IRQHandler(void) {}
-}
 
-void I2C0_ER_IRQHandler(void) {
+void I2C0_ER_IRQHandler(void) {}
-}

source/Core/BSP/Pine64/Pins.h

@@ -35,7 +35,6 @@
 #define SDA_Pin              BIT(7)
 #define SDA_GPIO_Port        GPIOB
 
-
 #define USB_DM_Pin           BIT(11)
 #define USB_DM_LOW_GPIO_Port GPIOA
 

source/Core/BSP/Pine64/Power.cpp

@@ -1,12 +1,12 @@
 #include "BSP.h"
 #include "BSP_Power.h"
+#include "Model_Config.h"
+#include "Pins.h"
 #include "QC3.h"
 #include "Settings.h"
-#include "Pins.h"
 #include "fusbpd.h"
-#include "Model_Config.h"
-#include "policy_engine.h"
 #include "int_n.h"
+#include "policy_engine.h"
 bool FUSB302_present = false;
 
 void power_check() {

source/Core/BSP/Pine64/QC_GPIO.cpp

@@ -4,11 +4,11 @@
  *  Created on: 29 May 2020
  *      Author: Ralim
  */
-#include "gd32vf103_libopt.h"
 #include "BSP.h"
 #include "Pins.h"
 #include "QC3.h"
 #include "Settings.h"
+#include "gd32vf103_libopt.h"
 
 #ifdef POW_QC
 void QC_DPlusZero_Six() {
@@ -18,7 +18,6 @@ void QC_DPlusZero_Six() {
 void QC_DNegZero_Six() {
   gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin);
   gpio_bit_reset(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin);
-
 }
 void QC_DPlusThree_Three() {
   // pull up D+
@@ -28,12 +27,8 @@ void QC_DNegThree_Three() {
   gpio_bit_set(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin);
   gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin);
 }
-void QC_DM_PullDown() {
+void QC_DM_PullDown() { gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, USB_DM_Pin); }
-	gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, USB_DM_Pin);
+void QC_DM_No_PullDown() { gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_2MHZ, USB_DM_Pin); }
-}
-void QC_DM_No_PullDown() {
-	gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_2MHZ, USB_DM_Pin);
-}
 void QC_Init_GPIO() {
   // Setup any GPIO into the right states for QC
   // D+ pulldown as output
@@ -45,12 +40,9 @@ void QC_Post_Probe_En() {
   // Make two D- pins outputs
   gpio_init(QC_DM_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_LOW_Pin);
   gpio_init(QC_DM_HIGH_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_HIGH_Pin);
-
 }
 
-uint8_t QC_DM_PulledDown() {
+uint8_t QC_DM_PulledDown() { return gpio_input_bit_get(USB_DM_LOW_GPIO_Port, USB_DM_Pin) == RESET ? 1 : 0; }
-	return gpio_input_bit_get(USB_DM_LOW_GPIO_Port, USB_DM_Pin) == RESET ? 1 : 0;
-}
 #endif
 void QC_resync() {
 #ifdef POW_QC

source/Core/BSP/Pine64/Setup.cpp

@@ -11,8 +11,7 @@
 #include <string.h>
 #define ADC_NORM_CHANNELS 2
 #define ADC_NORM_SAMPLES  32
-uint16_t ADCReadings[ADC_NORM_SAMPLES *
+uint16_t ADCReadings[ADC_NORM_SAMPLES * ADC_NORM_CHANNELS]; // room for 32 lots of the pair of readings
-ADC_NORM_CHANNELS]; // room for 32 lots of the pair of readings
 
 // Functions
 void setup_gpio();
@@ -59,21 +58,16 @@ void setup_gpio() {
   gpio_init(KEY_A_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_A_Pin);
   gpio_init(KEY_B_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_B_Pin);
   // OLED reset as output
-	gpio_init(OLED_RESET_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ,
+  gpio_init(OLED_RESET_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, OLED_RESET_Pin);
-	OLED_RESET_Pin);
   gpio_bit_set(SDA_GPIO_Port, SDA_Pin);
   gpio_bit_set(SDA_GPIO_Port, SCL_Pin);
   // I2C as AF Open Drain
-	gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_2MHZ,
+  gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_2MHZ, SDA_Pin | SCL_Pin);
-	SDA_Pin | SCL_Pin);
   // PWM output as AF Push Pull
-	gpio_init(PWM_Out_GPIO_Port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ,
+  gpio_init(PWM_Out_GPIO_Port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, PWM_Out_Pin);
-			PWM_Out_Pin);
   // Analog Inputs ... as analog inputs
-	gpio_init(TMP36_INPUT_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ,
+  gpio_init(TMP36_INPUT_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, TMP36_INPUT_Pin);
-	TMP36_INPUT_Pin);
+  gpio_init(TIP_TEMP_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, TIP_TEMP_Pin);
-	gpio_init(TIP_TEMP_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ,
-			TIP_TEMP_Pin);
   gpio_init(VIN_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, VIN_Pin);
 
   // Remap PB4 away from JTAG NJRST
@@ -160,21 +154,15 @@ void setup_adc() {
   adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 4);
   adc_channel_length_config(ADC1, ADC_INSERTED_CHANNEL, 4);
   for (int rank = 0; rank < 4; rank++) {
-		adc_inserted_channel_config(ADC0, rank, TIP_TEMP_ADC0_CHANNEL,
+    adc_inserted_channel_config(ADC0, rank, TIP_TEMP_ADC0_CHANNEL, ADC_SAMPLETIME_1POINT5);
-		ADC_SAMPLETIME_1POINT5);
+    adc_inserted_channel_config(ADC1, rank, TIP_TEMP_ADC1_CHANNEL, ADC_SAMPLETIME_1POINT5);
-		adc_inserted_channel_config(ADC1, rank, TIP_TEMP_ADC1_CHANNEL,
-		ADC_SAMPLETIME_1POINT5);
   }
   // Setup timer 1 channel 0 to trigger injected measurements
-	adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL,
+  adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_T1_CH0);
-	ADC0_1_EXTTRIG_INSERTED_T1_CH0);
+  adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_T1_CH0);
-	adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL,
-	ADC0_1_EXTTRIG_INSERTED_T1_CH0);
 
-	adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL,
+  adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE);
-	ADC0_1_EXTTRIG_REGULAR_NONE);
+  adc_external_trigger_source_config(ADC1, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE);
-	adc_external_trigger_source_config(ADC1, ADC_REGULAR_CHANNEL,
-	ADC0_1_EXTTRIG_REGULAR_NONE);
   // Enable triggers for the ADC
   adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE);
   adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ENABLE);
@@ -229,12 +217,9 @@ void setup_timers() {
     timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
     timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocintpara);
 
-		timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0,
+    timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, powerPWM + holdoffTicks);
-				powerPWM + holdoffTicks);
+    timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_PWM1);
-		timer_channel_output_mode_config(TIMER1, TIMER_CH_0,
+    timer_channel_output_shadow_config(TIMER1, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE);
-				TIMER_OC_MODE_PWM1);
-		timer_channel_output_shadow_config(TIMER1, TIMER_CH_0,
-		TIMER_OC_SHADOW_DISABLE);
     /* CH1 used for irq */
     timer_channel_output_struct_para_init(&timer_ocintpara);
     timer_ocintpara.ocpolarity  = TIMER_OC_POLARITY_HIGH;
@@ -242,10 +227,8 @@ void setup_timers() {
     timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocintpara);
 
     timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 0);
-		timer_channel_output_mode_config(TIMER1, TIMER_CH_1,
+    timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_PWM0);
-				TIMER_OC_MODE_PWM0);
+    timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE);
-		timer_channel_output_shadow_config(TIMER1, TIMER_CH_1,
-		TIMER_OC_SHADOW_DISABLE);
     // IRQ
     timer_interrupt_enable(TIMER1, TIMER_INT_UP);
     timer_interrupt_enable(TIMER1, TIMER_INT_CH1);
@@ -276,10 +259,8 @@ void setup_timers() {
     timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
     timer_channel_output_config(TIMER2, TIMER_CH_0, &timer_ocintpara);
     timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0);
-		timer_channel_output_mode_config(TIMER2, TIMER_CH_0,
+    timer_channel_output_mode_config(TIMER2, TIMER_CH_0, TIMER_OC_MODE_PWM0);
-				TIMER_OC_MODE_PWM0);
+    timer_channel_output_shadow_config(TIMER2, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE);
-		timer_channel_output_shadow_config(TIMER2, TIMER_CH_0,
-		TIMER_OC_SHADOW_DISABLE);
     timer_auto_reload_shadow_enable(TIMER2);
     timer_enable(TIMER2);
   }
@@ -292,8 +273,7 @@ void setup_iwdg() {
 
 void setupFUSBIRQ() {
   // Setup IRQ for USB-PD
-	gpio_init(FUSB302_IRQ_GPIO_Port, GPIO_MODE_IPU, GPIO_OSPEED_2MHZ,
+  gpio_init(FUSB302_IRQ_GPIO_Port, GPIO_MODE_IPU, GPIO_OSPEED_2MHZ, FUSB302_IRQ_Pin);
-	FUSB302_IRQ_Pin);
   eclic_irq_enable(EXTI5_9_IRQn, 1, 1);
   /* connect key EXTI line to key GPIO pin */
   gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOB, GPIO_PIN_SOURCE_5);

source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_compatiable.h

@@ -70,8 +70,7 @@
 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
 #define __SSAT(val, sat) __RV_SCLIP32((val), (sat - 1))
 #else
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) {
-{
   if ((sat >= 1U) && (sat <= 32U)) {
     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
     const int32_t min = -1 - max;
@@ -95,8 +94,7 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
 #define __USAT(val, sat) __RV_UCLIP32((val), (sat - 1))
 #else
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) {
-{
   if (sat <= 31U) {
     const uint32_t max = ((1U << sat) - 1U);
     if (val > (int32_t)max) {
@@ -117,14 +115,10 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
  * \param [in]    value  Value to reverse
  * \return               Reversed value
  */
-__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) {
-{
   uint32_t result;
 
-    result =  ((value & 0xff000000) >> 24)
+  result = ((value & 0xff000000) >> 24) | ((value & 0x00ff0000) >> 8) | ((value & 0x0000ff00) << 8) | ((value & 0x000000ff) << 24);
-        | ((value & 0x00ff0000) >> 8 )
-        | ((value & 0x0000ff00) << 8 )
-        | ((value & 0x000000ff) << 24);
   return result;
 }
 
@@ -135,13 +129,9 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
  * \param [in]    value  Value to reverse
  * \return               Reversed value
  */
-__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) {
-{
   uint32_t result;
-    result =  ((value & 0xff000000) >> 8)
+  result = ((value & 0xff000000) >> 8) | ((value & 0x00ff00000) << 8) | ((value & 0x0000ff00) >> 8) | ((value & 0x000000ff) << 8);
-        | ((value & 0x00ff00000) << 8 )
-        | ((value & 0x0000ff00) >> 8 )
-        | ((value & 0x000000ff) << 8) ;
 
   return result;
 }
@@ -154,8 +144,7 @@ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
  * \param [in]    value  Value to reverse
  * \return               Reversed value
  */
-__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) {
-{
   int16_t result;
   result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8);
   return result;
@@ -169,8 +158,7 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
  * \param [in]    op2  Number of Bits to rotate(0-31)
  * \return               Rotated value
  */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) {
-{
   op2 = op2 & 0x1F;
   if (op2 == 0U) {
     return op1;
@@ -187,8 +175,7 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
 #define __RBIT(value) __RV_BITREVI((value), 31)
 #else
-__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) {
-{
   uint32_t result;
   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
 
@@ -212,8 +199,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
 #define __CLZ(data) __RV_CLZ32(data)
 #else
-__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) {
-{
   uint8_t  ret  = 0;
   uint32_t temp = ~data;
   while (temp & 0x80000000) {

source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_base.h

@@ -22,8 +22,8 @@
  * @file     core_feature_base.h
  * @brief    Base core feature API for Nuclei N/NX Core
  */
-#include <stdint.h>
 #include "riscv_encoding.h"
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -232,7 +232,6 @@ typedef union {
   rv_csr_t d; /*!< Type      used for csr data access */
 } CSR_MMISCCTRL_Type;
 
-
 /**
  * \brief  Union type to access MSAVESTATUS configure register.
  */
@@ -269,7 +268,6 @@ typedef union {
  *   @{
  */
 
-
 #ifndef __ASSEMBLY__
 
 /**
@@ -285,10 +283,7 @@ typedef union {
 #define __RV_CSR_SWAP(csr, val)                                                            \
   ({                                                                                       \
     register rv_csr_t __v = (unsigned long)(val);                                          \
-        __ASM volatile("csrrw %0, " STRINGIFY(csr) ", %1"       \
+    __ASM volatile("csrrw %0, " STRINGIFY(csr) ", %1" : "=r"(__v) : "rK"(__v) : "memory"); \
-                     : "=r"(__v)                                \
-                     : "rK"(__v)                                \
-                     : "memory");                               \
     __v;                                                                                   \
   })
 
@@ -303,10 +298,7 @@ typedef union {
 #define __RV_CSR_READ(csr)                                               \
   ({                                                                     \
     register rv_csr_t __v;                                               \
-        __ASM volatile("csrr %0, " STRINGIFY(csr)               \
+    __ASM volatile("csrr %0, " STRINGIFY(csr) : "=r"(__v) : : "memory"); \
-                     : "=r"(__v)                                \
-                     :                                          \
-                     : "memory");                               \
     __v;                                                                 \
   })
 
@@ -321,10 +313,7 @@ typedef union {
 #define __RV_CSR_WRITE(csr, val)                                            \
   ({                                                                        \
     register rv_csr_t __v = (rv_csr_t)(val);                                \
-        __ASM volatile("csrw " STRINGIFY(csr) ", %0"            \
+    __ASM volatile("csrw " STRINGIFY(csr) ", %0" : : "rK"(__v) : "memory"); \
-                     :                                          \
-                     : "rK"(__v)                                \
-                     : "memory");                               \
   })
 
 /**
@@ -340,10 +329,7 @@ typedef union {
 #define __RV_CSR_READ_SET(csr, val)                                                        \
   ({                                                                                       \
     register rv_csr_t __v = (rv_csr_t)(val);                                               \
-        __ASM volatile("csrrs %0, " STRINGIFY(csr) ", %1"       \
+    __ASM volatile("csrrs %0, " STRINGIFY(csr) ", %1" : "=r"(__v) : "rK"(__v) : "memory"); \
-                     : "=r"(__v)                                \
-                     : "rK"(__v)                                \
-                     : "memory");                               \
     __v;                                                                                   \
   })
 
@@ -358,10 +344,7 @@ typedef union {
 #define __RV_CSR_SET(csr, val)                                              \
   ({                                                                        \
     register rv_csr_t __v = (rv_csr_t)(val);                                \
-        __ASM volatile("csrs " STRINGIFY(csr) ", %0"            \
+    __ASM volatile("csrs " STRINGIFY(csr) ", %0" : : "rK"(__v) : "memory"); \
-                     :                                          \
-                     : "rK"(__v)                                \
-                     : "memory");                               \
   })
 
 /**
@@ -377,10 +360,7 @@ typedef union {
 #define __RV_CSR_READ_CLEAR(csr, val)                                                      \
   ({                                                                                       \
     register rv_csr_t __v = (rv_csr_t)(val);                                               \
-        __ASM volatile("csrrc %0, " STRINGIFY(csr) ", %1"       \
+    __ASM volatile("csrrc %0, " STRINGIFY(csr) ", %1" : "=r"(__v) : "rK"(__v) : "memory"); \
-                     : "=r"(__v)                                \
-                     : "rK"(__v)                                \
-                     : "memory");                               \
     __v;                                                                                   \
   })
 
@@ -395,10 +375,7 @@ typedef union {
 #define __RV_CSR_CLEAR(csr, val)                                            \
   ({                                                                        \
     register rv_csr_t __v = (rv_csr_t)(val);                                \
-        __ASM volatile("csrc " STRINGIFY(csr) ", %0"            \
+    __ASM volatile("csrc " STRINGIFY(csr) ", %0" : : "rK"(__v) : "memory"); \
-                     :                                          \
-                     : "rK"(__v)                                \
-                     : "memory");                               \
   })
 #endif /* __ASSEMBLY__ */
 
@@ -408,10 +385,7 @@ typedef union {
  * \remarks
  *          Can only be executed in Privileged modes.
  */
-__STATIC_FORCEINLINE void __enable_irq(void)
+__STATIC_FORCEINLINE void __enable_irq(void) { __RV_CSR_SET(CSR_MSTATUS, MSTATUS_MIE); }
-{
-    __RV_CSR_SET(CSR_MSTATUS, MSTATUS_MIE);
-}
 
 /**
  * \brief   Disable IRQ Interrupts
@@ -419,10 +393,7 @@ __STATIC_FORCEINLINE void __enable_irq(void)
  * \remarks
  *          Can only be executed in Privileged modes.
  */
-__STATIC_FORCEINLINE void __disable_irq(void)
+__STATIC_FORCEINLINE void __disable_irq(void) { __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_MIE); }
-{
-    __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
-}
 
 /**
  * \brief   Read whole 64 bits value of mcycle counter
@@ -430,8 +401,7 @@ __STATIC_FORCEINLINE void __disable_irq(void)
  * \return  The whole 64 bits value of MCYCLE
  * \remarks It will work for both RV32 and RV64 to get full 64bits value of MCYCLE
  */
-__STATIC_FORCEINLINE uint64_t __get_rv_cycle(void)
+__STATIC_FORCEINLINE uint64_t __get_rv_cycle(void) {
-{
 #if __RISCV_XLEN == 32
   volatile uint32_t high0, low, high;
   uint64_t          full;
@@ -457,8 +427,7 @@ __STATIC_FORCEINLINE uint64_t __get_rv_cycle(void)
  * \return  The whole 64 bits value of MINSTRET
  * \remarks It will work for both RV32 and RV64 to get full 64bits value of MINSTRET
  */
-__STATIC_FORCEINLINE uint64_t __get_rv_instret(void)
+__STATIC_FORCEINLINE uint64_t __get_rv_instret(void) {
-{
 #if __RISCV_XLEN == 32
   volatile uint32_t high0, low, high;
   uint64_t          full;
@@ -485,8 +454,7 @@ __STATIC_FORCEINLINE uint64_t __get_rv_instret(void)
  * \remarks It will work for both RV32 and RV64 to get full 64bits value of TIME
  * \attention only available when user mode available
  */
-__STATIC_FORCEINLINE uint64_t __get_rv_time(void)
+__STATIC_FORCEINLINE uint64_t __get_rv_time(void) {
-{
 #if __RISCV_XLEN == 32
   volatile uint32_t high0, low, high;
   uint64_t          full;
@@ -525,10 +493,7 @@ __STATIC_FORCEINLINE uint64_t __get_rv_time(void)
  * No Operation does nothing.
  * This instruction can be used for code alignment purposes.
  */
-__STATIC_FORCEINLINE void __NOP(void)
+__STATIC_FORCEINLINE void __NOP(void) { __ASM volatile("nop"); }
-{
-    __ASM volatile("nop");
-}
 
 /**
  * \brief   Wait For Interrupt
@@ -539,8 +504,7 @@ __STATIC_FORCEINLINE void __NOP(void)
  * 1. mstatus.MIE == 1(interrupt enabled), Core will enter ISR code
  * 2. mstatus.MIE == 0(interrupt disabled), Core will resume previous execution
  */
-__STATIC_FORCEINLINE void __WFI(void)
+__STATIC_FORCEINLINE void __WFI(void) {
-{
   __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
   __ASM volatile("wfi");
 }
@@ -552,8 +516,7 @@ __STATIC_FORCEINLINE void __WFI(void)
  * It will suspends execution until event, NMI or Debug happened.
  * When Core is waked up, Core will resume previous execution
  */
-__STATIC_FORCEINLINE void __WFE(void)
+__STATIC_FORCEINLINE void __WFE(void) {
-{
   __RV_CSR_SET(CSR_WFE, WFE_WFE);
   __ASM volatile("wfi");
   __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
@@ -566,10 +529,7 @@ __STATIC_FORCEINLINE void __WFE(void)
  * Debug tools can use this to investigate system state
  * when the instruction at a particular address is reached.
  */
-__STATIC_FORCEINLINE void __EBREAK(void)
+__STATIC_FORCEINLINE void __EBREAK(void) { __ASM volatile("ebreak"); }
-{
-    __ASM volatile("ebreak");
-}
 
 /**
  * \brief   Environment Call Instruction
@@ -577,10 +537,7 @@ __STATIC_FORCEINLINE void __EBREAK(void)
  * The ECALL instruction is used to make a service request to
  * the execution environment.
  */
-__STATIC_FORCEINLINE void __ECALL(void)
+__STATIC_FORCEINLINE void __ECALL(void) { __ASM volatile("ecall"); }
-{
-    __ASM volatile("ecall");
-}
 
 /**
  * \brief WFI Sleep Mode enumeration
@@ -597,10 +554,7 @@ typedef enum WFI_SleepMode {
  * WFI Sleep mode.
  * \param[in] mode      The sleep mode to be set
  */
-__STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode)
+__STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode) { __RV_CSR_WRITE(CSR_SLEEPVALUE, mode); }
-{
-    __RV_CSR_WRITE(CSR_SLEEPVALUE, mode);
-}
 
 /**
  * \brief   Send TX Event
@@ -608,70 +562,49 @@ __STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode)
  * Set the CSR TXEVT to control send a TX Event.
  * The Core will output signal tx_evt as output event signal.
  */
-__STATIC_FORCEINLINE void __TXEVT(void)
+__STATIC_FORCEINLINE void __TXEVT(void) { __RV_CSR_SET(CSR_TXEVT, 0x1); }
-{
-    __RV_CSR_SET(CSR_TXEVT, 0x1);
-}
 
 /**
  * \brief   Enable MCYCLE counter
  * \details
  * Clear the CY bit of MCOUNTINHIBIT to 0 to enable MCYCLE Counter
  */
-__STATIC_FORCEINLINE void __enable_mcycle_counter(void)
+__STATIC_FORCEINLINE void __enable_mcycle_counter(void) { __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY); }
-{
-    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
-}
 
 /**
  * \brief   Disable MCYCLE counter
  * \details
  * Set the CY bit of MCOUNTINHIBIT to 1 to disable MCYCLE Counter
  */
-__STATIC_FORCEINLINE void __disable_mcycle_counter(void)
+__STATIC_FORCEINLINE void __disable_mcycle_counter(void) { __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY); }
-{
-    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
-}
 
 /**
  * \brief   Enable MINSTRET counter
  * \details
  * Clear the IR bit of MCOUNTINHIBIT to 0 to enable MINSTRET Counter
  */
-__STATIC_FORCEINLINE void __enable_minstret_counter(void)
+__STATIC_FORCEINLINE void __enable_minstret_counter(void) { __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR); }
-{
-    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
-}
 
 /**
  * \brief   Disable MINSTRET counter
  * \details
  * Set the IR bit of MCOUNTINHIBIT to 1 to disable MINSTRET Counter
  */
-__STATIC_FORCEINLINE void __disable_minstret_counter(void)
+__STATIC_FORCEINLINE void __disable_minstret_counter(void) { __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR); }
-{
-    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
-}
 
 /**
  * \brief   Enable MCYCLE & MINSTRET counter
  * \details
  * Clear the IR and CY bit of MCOUNTINHIBIT to 1 to enable MINSTRET & MCYCLE Counter
  */
-__STATIC_FORCEINLINE void __enable_all_counter(void)
+__STATIC_FORCEINLINE void __enable_all_counter(void) { __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY); }
-{
-    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR|MCOUNTINHIBIT_CY);
-}
 
 /**
  * \brief   Disable MCYCLE & MINSTRET counter
  * \details
  * Set the IR and CY bit of MCOUNTINHIBIT to 1 to disable MINSTRET & MCYCLE Counter
  */
-__STATIC_FORCEINLINE void __disable_all_counter(void)
+__STATIC_FORCEINLINE void __disable_all_counter(void) { __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY); }
-{
-    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR|MCOUNTINHIBIT_CY);
-}
 
 /**
  * \brief Execute fence instruction, p -> pred, s -> succ
@@ -691,10 +624,7 @@ __STATIC_FORCEINLINE void __disable_all_counter(void)
  * The FENCE.I instruction is used to synchronize the instruction
  * and data streams.
  */
-__STATIC_FORCEINLINE void __FENCE_I(void)
+__STATIC_FORCEINLINE void __FENCE_I(void) { __ASM volatile("fence.i"); }
-{
-    __ASM volatile("fence.i");
-}
 
 /** \brief Read & Write Memory barrier */
 #define __RWMB() __FENCE(iorw, iorw)
@@ -717,7 +647,6 @@ __STATIC_FORCEINLINE void __FENCE_I(void)
 /** \brief CPU relax for busy loop */
 #define __CPU_RELAX() __ASM volatile("" : : : "memory")
 
-
 /* ===== Load/Store Operations ===== */
 /**
  * \brief  Load 8bit value from address (8 bit)
@@ -725,8 +654,7 @@ __STATIC_FORCEINLINE void __FENCE_I(void)
  * \param [in]    addr  Address pointer to data
  * \return              value of type uint8_t at (*addr)
  */
-__STATIC_FORCEINLINE uint8_t __LB(volatile void *addr)
+__STATIC_FORCEINLINE uint8_t __LB(volatile void *addr) {
-{
   uint8_t result;
 
   __ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr));
@@ -739,8 +667,7 @@ __STATIC_FORCEINLINE uint8_t __LB(volatile void *addr)
  * \param [in]    addr  Address pointer to data
  * \return              value of type uint16_t at (*addr)
  */
-__STATIC_FORCEINLINE uint16_t __LH(volatile void *addr)
+__STATIC_FORCEINLINE uint16_t __LH(volatile void *addr) {
-{
   uint16_t result;
 
   __ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr));
@@ -753,8 +680,7 @@ __STATIC_FORCEINLINE uint16_t __LH(volatile void *addr)
  * \param [in]    addr  Address pointer to data
  * \return              value of type uint32_t at (*addr)
  */
-__STATIC_FORCEINLINE uint32_t __LW(volatile void *addr)
+__STATIC_FORCEINLINE uint32_t __LW(volatile void *addr) {
-{
   uint32_t result;
 
   __ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr));
@@ -769,8 +695,7 @@ __STATIC_FORCEINLINE uint32_t __LW(volatile void *addr)
  * \return              value of type uint64_t at (*addr)
  * \remarks RV64 only macro
  */
-__STATIC_FORCEINLINE uint64_t __LD(volatile void *addr)
+__STATIC_FORCEINLINE uint64_t __LD(volatile void *addr) {
-{
   uint64_t result;
   __ASM volatile("ld %0, 0(%1)" : "=r"(result) : "r"(addr));
   return result;
@@ -783,10 +708,7 @@ __STATIC_FORCEINLINE uint64_t __LD(volatile void *addr)
  * \param [in]    addr  Address pointer to data
  * \param [in]    val   Value to set
  */
-__STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val)
+__STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val) { __ASM volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr)); }
-{
-    __ASM volatile ("sb %0, 0(%1)" : : "r" (val), "r" (addr));
-}
 
 /**
  * \brief  Write 16bit value to address (16 bit)
@@ -794,10 +716,7 @@ __STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val)
  * \param [in]    addr  Address pointer to data
  * \param [in]    val   Value to set
  */
-__STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val)
+__STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val) { __ASM volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr)); }
-{
-    __ASM volatile ("sh %0, 0(%1)" : : "r" (val), "r" (addr));
-}
 
 /**
  * \brief  Write 32bit value to address (32 bit)
@@ -805,10 +724,7 @@ __STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val)
  * \param [in]    addr  Address pointer to data
  * \param [in]    val   Value to set
  */
-__STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val)
+__STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val) { __ASM volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr)); }
-{
-    __ASM volatile ("sw %0, 0(%1)" : : "r" (val), "r" (addr));
-}
 
 #if __RISCV_XLEN != 32
 /**
@@ -817,10 +733,7 @@ __STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val)
  * \param [in]    addr  Address pointer to data
  * \param [in]    val   Value to set
  */
-__STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val)
+__STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val) { __ASM volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr)); }
-{
-    __ASM volatile ("sd %0, 0(%1)" : : "r" (val), "r" (addr));
-}
 #endif
 
 /**
@@ -834,19 +747,17 @@ __STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val)
  * \param [in]    newval    New value to be stored into the address
  * \return  return the initial value in memory
  */
-__STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval, uint32_t newval)
+__STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval, uint32_t newval) {
-{
   register uint32_t result;
   register uint32_t rc;
 
-    __ASM volatile (                                \
+  __ASM volatile("0:     lr.w %0, %2      \n"
-            "0:     lr.w %0, %2      \n"            \
+                 "       bne  %0, %z3, 1f \n"
-            "       bne  %0, %z3, 1f \n"            \
+                 "       sc.w %1, %z4, %2 \n"
-            "       sc.w %1, %z4, %2 \n"            \
+                 "       bnez %1, 0b      \n"
-            "       bnez %1, 0b      \n"            \
+                 "1:\n"
-            "1:\n"                                  \
+                 : "=&r"(result), "=&r"(rc), "+A"(*addr)
-            : "=&r"(result), "=&r"(rc), "+A"(*addr) \
+                 : "r"(oldval), "r"(newval)
-            : "r"(oldval), "r"(newval)              \
                  : "memory");
   return result;
 }
@@ -858,12 +769,10 @@ __STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval,
  * \param [in]    newval    New value to be stored into the address
  * \return  return the original value in memory
  */
-__STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
+__STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) {
-{
   register uint32_t result;
 
-    __ASM volatile ("amoswap.w %0, %2, %1" : \
+  __ASM volatile("amoswap.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
   return result;
 }
 
@@ -874,12 +783,10 @@ __STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newv
  * \param [in]    value  value to be ADDed
  * \return  return memory value + add value
  */
-__STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
+__STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) {
-{
   register int32_t result;
 
-    __ASM volatile ("amoadd.w %0, %2, %1" : \
+  __ASM volatile("amoadd.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -890,12 +797,10 @@ __STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
  * \param [in]    value  value to be ANDed
  * \return  return memory value & and value
  */
-__STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
+__STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) {
-{
   register int32_t result;
 
-    __ASM volatile ("amoand.w %0, %2, %1" : \
+  __ASM volatile("amoand.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -906,12 +811,10 @@ __STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
  * \param [in]    value  value to be ORed
  * \return  return memory value | and value
  */
-__STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
+__STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) {
-{
   register int32_t result;
 
-    __ASM volatile ("amoor.w %0, %2, %1" : \
+  __ASM volatile("amoor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -922,12 +825,10 @@ __STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
  * \param [in]    value  value to be XORed
  * \return  return memory value ^ and value
  */
-__STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
+__STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) {
-{
   register int32_t result;
 
-    __ASM volatile ("amoxor.w %0, %2, %1" : \
+  __ASM volatile("amoxor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -938,12 +839,10 @@ __STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
  * \param [in]    value  value to be compared
  * \return  return the bigger value
  */
-__STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
+__STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) {
-{
   register uint32_t result;
 
-    __ASM volatile ("amomaxu.w %0, %2, %1" : \
+  __ASM volatile("amomaxu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -954,12 +853,10 @@ __STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t valu
  * \param [in]    value  value to be compared
  * \return the bigger value
  */
-__STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
+__STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) {
-{
   register int32_t result;
 
-    __ASM volatile ("amomax.w %0, %2, %1" : \
+  __ASM volatile("amomax.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -970,12 +867,10 @@ __STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
  * \param [in]    value  value to be compared
  * \return the smaller value
  */
-__STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
+__STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) {
-{
   register uint32_t result;
 
-    __ASM volatile ("amominu.w %0, %2, %1" : \
+  __ASM volatile("amominu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -986,12 +881,10 @@ __STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t valu
  * \param [in]    value  value to be compared
  * \return  the smaller value
  */
-__STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
+__STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) {
-{
   register int32_t result;
 
-    __ASM volatile ("amomin.w %0, %2, %1" : \
+  __ASM volatile("amomin.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -1007,19 +900,17 @@ __STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
  * \param [in]    newval    New value to be stored into the address
  * \return  return the initial value in memory
  */
-__STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval, uint64_t newval)
+__STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval, uint64_t newval) {
-{
   register uint64_t result;
   register uint64_t rc;
 
-    __ASM volatile (                                \
+  __ASM volatile("0:     lr.d %0, %2      \n"
-            "0:     lr.d %0, %2      \n"            \
+                 "       bne  %0, %z3, 1f \n"
-            "       bne  %0, %z3, 1f \n"            \
+                 "       sc.d %1, %z4, %2 \n"
-            "       sc.d %1, %z4, %2 \n"            \
+                 "       bnez %1, 0b      \n"
-            "       bnez %1, 0b      \n"            \
+                 "1:\n"
-            "1:\n"                                  \
+                 : "=&r"(result), "=&r"(rc), "+A"(*addr)
-            : "=&r"(result), "=&r"(rc), "+A"(*addr) \
+                 : "r"(oldval), "r"(newval)
-            : "r"(oldval), "r"(newval)              \
                  : "memory");
   return result;
 }
@@ -1031,12 +922,10 @@ __STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval,
  * \param [in]    newval    New value to be stored into the address
  * \return  return the original value in memory
  */
-__STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newval)
+__STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newval) {
-{
   register uint64_t result;
 
-    __ASM volatile ("amoswap.d %0, %2, %1" : \
+  __ASM volatile("amoswap.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
   return result;
 }
 
@@ -1047,12 +936,10 @@ __STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newv
  * \param [in]    value  value to be ADDed
  * \return  return memory value + add value
  */
-__STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value)
+__STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value) {
-{
   register int64_t result;
 
-    __ASM volatile ("amoadd.d %0, %2, %1" : \
+  __ASM volatile("amoadd.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -1063,12 +950,10 @@ __STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value)
  * \param [in]    value  value to be ANDed
  * \return  return memory value & and value
  */
-__STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value)
+__STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value) {
-{
   register int64_t result;
 
-    __ASM volatile ("amoand.d %0, %2, %1" : \
+  __ASM volatile("amoand.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -1079,12 +964,10 @@ __STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value)
  * \param [in]    value  value to be ORed
  * \return  return memory value | and value
  */
-__STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value)
+__STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value) {
-{
   register int64_t result;
 
-    __ASM volatile ("amoor.d %0, %2, %1" : \
+  __ASM volatile("amoor.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -1095,12 +978,10 @@ __STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value)
  * \param [in]    value  value to be XORed
  * \return  return memory value ^ and value
  */
-__STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value)
+__STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value) {
-{
   register int64_t result;
 
-    __ASM volatile ("amoxor.d %0, %2, %1" : \
+  __ASM volatile("amoxor.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -1111,12 +992,10 @@ __STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value)
  * \param [in]    value  value to be compared
  * \return  return the bigger value
  */
-__STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t value)
+__STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t value) {
-{
   register uint64_t result;
 
-    __ASM volatile ("amomaxu.d %0, %2, %1" : \
+  __ASM volatile("amomaxu.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -1127,12 +1006,10 @@ __STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t valu
  * \param [in]    value  value to be compared
  * \return the bigger value
  */
-__STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value)
+__STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value) {
-{
   register int64_t result;
 
-    __ASM volatile ("amomax.d %0, %2, %1" : \
+  __ASM volatile("amomax.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -1143,12 +1020,10 @@ __STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value)
  * \param [in]    value  value to be compared
  * \return the smaller value
  */
-__STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t value)
+__STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t value) {
-{
   register uint64_t result;
 
-    __ASM volatile ("amominu.d %0, %2, %1" : \
+  __ASM volatile("amominu.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 
@@ -1159,12 +1034,10 @@ __STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t valu
  * \param [in]    value  value to be compared
  * \return  the smaller value
  */
-__STATIC_FORCEINLINE int64_t __AMOMIN_D(volatile int64_t *addr, int64_t value)
+__STATIC_FORCEINLINE int64_t __AMOMIN_D(volatile int64_t *addr, int64_t value) {
-{
   register int64_t result;
 
-    __ASM volatile ("amomin.d %0, %2, %1" : \
+  __ASM volatile("amomin.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
-            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
   return *addr;
 }
 #endif /* __RISCV_XLEN == 64  */

source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_cache.h

@@ -60,10 +60,7 @@
  * \sa
  * - \ref DisableICache
  */
-__STATIC_FORCEINLINE void EnableICache (void)
+__STATIC_FORCEINLINE void EnableICache(void) { __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); }
-{
-    __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
-}
 
 /**
  * \brief  Disable ICache
@@ -74,10 +71,7 @@ __STATIC_FORCEINLINE void EnableICache (void)
  * \sa
  * - \ref EnableICache
  */
-__STATIC_FORCEINLINE void DisableICache (void)
+__STATIC_FORCEINLINE void DisableICache(void) { __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); }
-{
-    __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
-}
 /** @} */ /* End of Doxygen Group NMSIS_Core_ICache */
 #endif    /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */
 
@@ -97,10 +91,7 @@ __STATIC_FORCEINLINE void DisableICache (void)
  * \sa
  * - \ref DisableDCache
  */
-__STATIC_FORCEINLINE void EnableDCache (void)
+__STATIC_FORCEINLINE void EnableDCache(void) { __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); }
-{
-    __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
-}
 
 /**
  * \brief  Disable DCache
@@ -111,10 +102,7 @@ __STATIC_FORCEINLINE void EnableDCache (void)
  * \sa
  * - \ref EnableDCache
  */
-__STATIC_FORCEINLINE void DisableDCache (void)
+__STATIC_FORCEINLINE void DisableDCache(void) { __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); }
-{
-    __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
-}
 /** @} */ /* End of Doxygen Group NMSIS_Core_DCache */
 #endif    /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */
 

source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_eclic.h

@@ -48,8 +48,7 @@
 /**
  * \brief  Union type to access CLICFG configure register.
  */
-typedef union
+typedef union {
-{
   struct {
     uint8_t _reserved0 : 1; /*!< bit:     0   Overflow condition code flag */
     uint8_t nlbits : 4;     /*!< bit:     29  Carry condition code flag */
@@ -255,8 +254,7 @@ typedef enum IRQn {
  * \sa
  * - \ref ECLIC_GetCfgNlbits
  */
-__STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits)
+__STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits) {
-{
   ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk;
   ECLIC->CFG |= (uint8_t)((nlbits << CLIC_CLICCFG_NLBIT_Pos) & CLIC_CLICCFG_NLBIT_Msk);
 }
@@ -271,10 +269,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits)
  * \sa
  * - \ref ECLIC_SetCfgNlbits
  */
-__STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void)
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void) { return ((uint32_t)((ECLIC->CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos)); }
-{
-    return ((uint32_t)((ECLIC->CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos));
-}
 
 /**
  * \brief  Get the ECLIC version number
@@ -287,10 +282,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void)
  * \sa
  * - \ref ECLIC_GetInfoNum
  */
-__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void)
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos)); }
-{
-    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos));
-}
 
 /**
  * \brief  Get CLICINTCTLBITS
@@ -304,10 +296,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void)
  * \sa
  * - \ref ECLIC_GetInfoNum
  */
-__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void)
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos)); }
-{
-    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos));
-}
 
 /**
  * \brief  Get number of maximum interrupt inputs supported
@@ -320,10 +309,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void)
  * \sa
  * - \ref ECLIC_GetInfoCtlbits
  */
-__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void)
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos)); }
-{
-    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos));
-}
 
 /**
  * \brief  Set Machine Mode Interrupt Level Threshold
@@ -333,10 +319,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void)
  * \sa
  * - \ref ECLIC_GetMth
  */
-__STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth)
+__STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth) { ECLIC->MTH = mth; }
-{
-    ECLIC->MTH = mth;
-}
 
 /**
  * \brief  Get Machine Mode Interrupt Level Threshold
@@ -346,11 +329,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth)
  * \sa
  * - \ref ECLIC_SetMth
  */
-__STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void)
+__STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void) { return (ECLIC->MTH); }
-{
-    return (ECLIC->MTH);
-}
-
 
 /**
  * \brief  Enable a specific interrupt
@@ -362,10 +341,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void)
  * \sa
  * - \ref ECLIC_DisableIRQ
  */
-__STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk; }
-{
-    ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk;
-}
 
 /**
  * \brief  Get a specific interrupt enable status
@@ -381,10 +357,7 @@ __STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn)
  * - \ref ECLIC_EnableIRQ
  * - \ref ECLIC_DisableIRQ
  */
-__STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn) { return ((uint32_t)(ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk); }
-{
-    return((uint32_t) (ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk);
-}
 
 /**
  * \brief  Disable a specific interrupt
@@ -396,10 +369,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn)
  * \sa
  * - \ref ECLIC_EnableIRQ
  */
-__STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk; }
-{
-    ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk;
-}
 
 /**
  * \brief  Get the pending specific interrupt
@@ -415,10 +385,7 @@ __STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn)
  * - \ref ECLIC_SetPendingIRQ
  * - \ref ECLIC_ClearPendingIRQ
  */
-__STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk); }
-{
-    return((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk);
-}
 
 /**
  * \brief  Set a specific interrupt to pending
@@ -431,10 +398,7 @@ __STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn)
  * - \ref ECLIC_GetPendingIRQ
  * - \ref ECLIC_ClearPendingIRQ
  */
-__STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk; }
-{
-    ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk;
-}
 
 /**
  * \brief  Clear a specific interrupt from pending
@@ -448,10 +412,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn)
  * - \ref ECLIC_SetPendingIRQ
  * - \ref ECLIC_GetPendingIRQ
  */
-__STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIP &= ~CLIC_INTIP_IP_Msk; }
-{
-    ECLIC->CTRL[IRQn].INTIP &= ~ CLIC_INTIP_IP_Msk;
-}
 
 /**
  * \brief  Set trigger mode and polarity for a specific interrupt
@@ -469,8 +430,7 @@ __STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn)
  * \sa
  * - \ref ECLIC_GetTrigIRQ
  */
-__STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig)
+__STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig) {
-{
   ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk;
   ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig << CLIC_INTATTR_TRIG_Pos);
 }
@@ -490,10 +450,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig)
  * \sa
  *     - \ref ECLIC_SetTrigIRQ
  */
-__STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn) { return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk) >> CLIC_INTATTR_TRIG_Pos)); }
-{
-    return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk)>>CLIC_INTATTR_TRIG_Pos));
-}
 
 /**
  * \brief  Set interrupt working mode for a specific interrupt
@@ -508,8 +465,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn)
  * \sa
  * - \ref ECLIC_GetShvIRQ
  */
-__STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv)
+__STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv) {
-{
   ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk;
   ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv << CLIC_INTATTR_SHV_Pos);
 }
@@ -527,10 +483,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv)
  * \sa
  * - \ref ECLIC_SetShvIRQ
  */
-__STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn) { return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk) >> CLIC_INTATTR_SHV_Pos)); }
-{
-    return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk)>>CLIC_INTATTR_SHV_Pos));
-}
 
 /**
  * \brief  Modify ECLIC Interrupt Input Control Register for a specific interrupt
@@ -543,10 +496,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn)
  * \sa
  * - \ref ECLIC_GetCtrlIRQ
  */
-__STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl)
+__STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl) { ECLIC->CTRL[IRQn].INTCTRL = intctrl; }
-{
-    ECLIC->CTRL[IRQn].INTCTRL = intctrl;
-}
 
 /**
  * \brief  Get ECLIC Interrupt Input Control Register value for a specific interrupt
@@ -559,10 +509,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl)
  * \sa
  * - \ref ECLIC_SetCtrlIRQ
  */
-__STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn) { return (ECLIC->CTRL[IRQn].INTCTRL); }
-{
-    return (ECLIC->CTRL[IRQn].INTCTRL);
-}
 
 /**
  * \brief  Set ECLIC Interrupt level of a specific interrupt
@@ -579,8 +526,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn)
  * \sa
  * - \ref ECLIC_GetLevelIRQ
  */
-__STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)
+__STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs) {
-{
   uint8_t nlbits     = __ECLIC_GetCfgNlbits();
   uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
 
@@ -613,8 +559,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)
  * \sa
  * - \ref ECLIC_SetLevelIRQ
  */
-__STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn) {
-{
   uint8_t nlbits     = __ECLIC_GetCfgNlbits();
   uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
 
@@ -644,8 +589,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn)
  * \sa
  * - \ref ECLIC_GetPriorityIRQ
  */
-__STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)
+__STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri) {
-{
   uint8_t nlbits     = __ECLIC_GetCfgNlbits();
   uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
   if (nlbits < intctlbits) {
@@ -674,8 +618,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)
  * \sa
  * - \ref ECLIC_SetPriorityIRQ
  */
-__STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn)
+__STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn) {
-{
   uint8_t nlbits     = __ECLIC_GetCfgNlbits();
   uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
   if (nlbits < intctlbits) {
@@ -705,8 +648,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn)
  * \sa
  * - \ref ECLIC_GetVector
  */
-__STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector)
+__STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) {
-{
 #if __RISCV_XLEN == 32
   volatile uint32_t vec_base;
   vec_base                                             = ((uint32_t)__RV_CSR_READ(CSR_MTVT));
@@ -734,8 +676,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector)
  * \sa
  *     - \ref ECLIC_SetVector
  */
-__STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn)
+__STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) {
-{
 #if __RISCV_XLEN == 32
   return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 4));
 #elif __RISCV_XLEN == 64
@@ -755,8 +696,7 @@ __STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn)
  * \sa
  * - \ref __get_exc_entry
  */
-__STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr)
+__STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) {
-{
   addr &= (rv_csr_t)(~0x3F);
   addr |= ECLIC_MODE_MTVEC_Msk;
   __RV_CSR_WRITE(CSR_MTVEC, addr);
@@ -772,8 +712,7 @@ __STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr)
  * \sa
  * - \ref __set_exc_entry
  */
-__STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void)
+__STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void) {
-{
   unsigned long addr = __RV_CSR_READ(CSR_MTVEC);
   return (addr & ~ECLIC_MODE_MTVEC_Msk);
 }
@@ -789,8 +728,7 @@ __STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void)
  * \sa
  * - \ref __get_nonvec_entry
  */
-__STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr)
+__STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr) {
-{
   if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
     __RV_CSR_WRITE(CSR_MTVT2, addr | 0x01);
   } else {
@@ -811,8 +749,7 @@ __STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr)
  * \sa
  * - \ref __set_nonvec_entry
  */
-__STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void)
+__STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void) {
-{
   if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
     return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1));
   } else {
@@ -831,10 +768,7 @@ __STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void)
  * - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector.
  * - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored.
  */
-__STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void)
+__STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void) { return __RV_CSR_READ(CSR_MNVEC); }
-{
-    return __RV_CSR_READ(CSR_MNVEC);
-}
 
 /**
  * \brief   Save necessary CSRs into variables for vector interrupt nesting

source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_fpu.h

@@ -85,7 +85,6 @@
  * */
 #define __disable_FPU() __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS)
 
-
 /**
  * \brief   Load a single-precision value from memory into float point register freg using flw instruction
  * \details The FLW instruction loads a single-precision floating point value from memory
@@ -103,9 +102,7 @@
 #define __RV_FLW(freg, addr, ofs)                                                             \
   ({                                                                                          \
     register rv_csr_t __addr = (rv_csr_t)(addr);                                              \
-        __ASM volatile("flw " STRINGIFY(freg) ", %0(%1)  "     \
+    __ASM volatile("flw " STRINGIFY(freg) ", %0(%1)  " : : "I"(ofs), "r"(__addr) : "memory"); \
-                     : : "I"(ofs), "r"(__addr)                 \
-                     : "memory");                              \
   })
 
 /**
@@ -124,9 +121,7 @@
 #define __RV_FSW(freg, addr, ofs)                                                             \
   ({                                                                                          \
     register rv_csr_t __addr = (rv_csr_t)(addr);                                              \
-        __ASM volatile("fsw " STRINGIFY(freg) ", %0(%1)  "     \
+    __ASM volatile("fsw " STRINGIFY(freg) ", %0(%1)  " : : "I"(ofs), "r"(__addr) : "memory"); \
-                     : : "I"(ofs), "r"(__addr)                 \
-                     : "memory");                              \
   })
 
 /**
@@ -147,9 +142,7 @@
 #define __RV_FLD(freg, addr, ofs)                                                             \
   ({                                                                                          \
     register rv_csr_t __addr = (rv_csr_t)(addr);                                              \
-        __ASM volatile("fld " STRINGIFY(freg) ", %0(%1)  "     \
+    __ASM volatile("fld " STRINGIFY(freg) ", %0(%1)  " : : "I"(ofs), "r"(__addr) : "memory"); \
-                     : : "I"(ofs), "r"(__addr)                 \
-                     : "memory");                              \
   })
 
 /**
@@ -170,9 +163,7 @@
 #define __RV_FSD(freg, addr, ofs)                                                             \
   ({                                                                                          \
     register rv_csr_t __addr = (rv_csr_t)(addr);                                              \
-        __ASM volatile("fsd " STRINGIFY(freg) ", %0(%1)  "     \
+    __ASM volatile("fsd " STRINGIFY(freg) ", %0(%1)  " : : "I"(ofs), "r"(__addr) : "memory"); \
-                     : : "I"(ofs), "r"(__addr)                 \
-                     : "memory");                              \
   })
 
 /**

source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_pmp.h

@@ -58,11 +58,11 @@
  * \param [in]    idx    PMP region index(0-15)
  * \return               PMPxCFG Register value
  */
-__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
+__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx) {
-{
   rv_csr_t pmpcfg = 0;
 
-    if (idx >= __PMP_ENTRY_NUM) return 0;
+  if (idx >= __PMP_ENTRY_NUM)
+    return 0;
 #if __RISCV_XLEN == 32
   if (idx < 4) {
     pmpcfg = __RV_CSR_READ(CSR_PMPCFG0);
@@ -100,10 +100,10 @@ __STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
  * \param [in]    idx      PMPx region index(0-15)
  * \param [in]    pmpxcfg  PMPxCFG register value to set
  */
-__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg)
+__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg) {
-{
   rv_csr_t pmpcfgx = 0;
-    if (idx >= __PMP_ENTRY_NUM) return;
+  if (idx >= __PMP_ENTRY_NUM)
+    return;
 
 #if __RISCV_XLEN == 32
   if (idx < 4) {
@@ -160,14 +160,18 @@ __STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg)
  * - For RV32, pmpcfg0–pmpcfg3, hold the configurations
  *   pmp0cfg–pmp15cfg for the 16 PMP entries
  */
-__STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx)
+__STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx) {
-{
   switch (idx) {
-        case 0: return __RV_CSR_READ(CSR_PMPCFG0);
+  case 0:
-        case 1: return __RV_CSR_READ(CSR_PMPCFG1);
+    return __RV_CSR_READ(CSR_PMPCFG0);
-        case 2: return __RV_CSR_READ(CSR_PMPCFG2);
+  case 1:
-        case 3: return __RV_CSR_READ(CSR_PMPCFG3);
+    return __RV_CSR_READ(CSR_PMPCFG1);
-        default: return 0;
+  case 2:
+    return __RV_CSR_READ(CSR_PMPCFG2);
+  case 3:
+    return __RV_CSR_READ(CSR_PMPCFG3);
+  default:
+    return 0;
   }
 }
 
@@ -183,14 +187,22 @@ __STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx)
  * - For RV32, pmpcfg0–pmpcfg3, hold the configurations
  *   pmp0cfg–pmp15cfg for the 16 PMP entries
  */
-__STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg)
+__STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg) {
-{
   switch (idx) {
-        case 0: __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg); break;
+  case 0:
-        case 1: __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg); break;
+    __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg);
-        case 2: __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg); break;
+    break;
-        case 3: __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg); break;
+  case 1:
-        default: return;
+    __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg);
+    break;
+  case 2:
+    __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg);
+    break;
+  case 3:
+    __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg);
+    break;
+  default:
+    return;
   }
 }
 
@@ -200,26 +212,42 @@ __STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg)
  * \param [in]    idx    PMP region index(0-15)
  * \return               PMPADDRx Register value
  */
-__STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx)
+__STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx) {
-{
   switch (idx) {
-        case 0: return __RV_CSR_READ(CSR_PMPADDR0);
+  case 0:
-        case 1: return __RV_CSR_READ(CSR_PMPADDR1);
+    return __RV_CSR_READ(CSR_PMPADDR0);
-        case 2: return __RV_CSR_READ(CSR_PMPADDR2);
+  case 1:
-        case 3: return __RV_CSR_READ(CSR_PMPADDR3);
+    return __RV_CSR_READ(CSR_PMPADDR1);
-        case 4: return __RV_CSR_READ(CSR_PMPADDR4);
+  case 2:
-        case 5: return __RV_CSR_READ(CSR_PMPADDR5);
+    return __RV_CSR_READ(CSR_PMPADDR2);
-        case 6: return __RV_CSR_READ(CSR_PMPADDR6);
+  case 3:
-        case 7: return __RV_CSR_READ(CSR_PMPADDR7);
+    return __RV_CSR_READ(CSR_PMPADDR3);
-        case 8: return __RV_CSR_READ(CSR_PMPADDR8);
+  case 4:
-        case 9: return __RV_CSR_READ(CSR_PMPADDR9);
+    return __RV_CSR_READ(CSR_PMPADDR4);
-        case 10: return __RV_CSR_READ(CSR_PMPADDR10);
+  case 5:
-        case 11: return __RV_CSR_READ(CSR_PMPADDR11);
+    return __RV_CSR_READ(CSR_PMPADDR5);
-        case 12: return __RV_CSR_READ(CSR_PMPADDR12);
+  case 6:
-        case 13: return __RV_CSR_READ(CSR_PMPADDR13);
+    return __RV_CSR_READ(CSR_PMPADDR6);
-        case 14: return __RV_CSR_READ(CSR_PMPADDR14);
+  case 7:
-        case 15: return __RV_CSR_READ(CSR_PMPADDR15);
+    return __RV_CSR_READ(CSR_PMPADDR7);
-        default: return 0;
+  case 8:
+    return __RV_CSR_READ(CSR_PMPADDR8);
+  case 9:
+    return __RV_CSR_READ(CSR_PMPADDR9);
+  case 10:
+    return __RV_CSR_READ(CSR_PMPADDR10);
+  case 11:
+    return __RV_CSR_READ(CSR_PMPADDR11);
+  case 12:
+    return __RV_CSR_READ(CSR_PMPADDR12);
+  case 13:
+    return __RV_CSR_READ(CSR_PMPADDR13);
+  case 14:
+    return __RV_CSR_READ(CSR_PMPADDR14);
+  case 15:
+    return __RV_CSR_READ(CSR_PMPADDR15);
+  default:
+    return 0;
   }
 }
 
@@ -229,26 +257,58 @@ __STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx)
  * \param [in]    idx      PMP region index(0-15)
  * \param [in]    pmpaddr  PMPADDRx Register value to set
  */
-__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, rv_csr_t pmpaddr)
+__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, rv_csr_t pmpaddr) {
-{
   switch (idx) {
-        case 0: __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr); break;
+  case 0:
-        case 1: __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr); break;
+    __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr);
-        case 2: __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr); break;
+    break;
-        case 3: __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr); break;
+  case 1:
-        case 4: __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr); break;
+    __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr);
-        case 5: __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr); break;
+    break;
-        case 6: __RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr); break;
+  case 2:
-        case 7: __RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr); break;
+    __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr);
-        case 8: __RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr); break;
+    break;
-        case 9: __RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr); break;
+  case 3:
-        case 10: __RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr); break;
+    __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr);
-        case 11: __RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr); break;
+    break;
-        case 12: __RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr); break;
+  case 4:
-        case 13: __RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr); break;
+    __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr);
-        case 14: __RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr); break;
+    break;
-        case 15: __RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr); break;
+  case 5:
-        default: return;
+    __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr);
+    break;
+  case 6:
+    __RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr);
+    break;
+  case 7:
+    __RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr);
+    break;
+  case 8:
+    __RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr);
+    break;
+  case 9:
+    __RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr);
+    break;
+  case 10:
+    __RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr);
+    break;
+  case 11:
+    __RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr);
+    break;
+  case 12:
+    __RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr);
+    break;
+  case 13:
+    __RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr);
+    break;
+  case 14:
+    __RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr);
+    break;
+  case 15:
+    __RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr);
+    break;
+  default:
+    return;
   }
 }
 /** @} */ /* End of Doxygen Group NMSIS_Core_PMP_Functions */

source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_timer.h

@@ -102,10 +102,7 @@ typedef struct {
  * - Load value is 64bits wide.
  * - \ref SysTimer_GetLoadValue
  */
-__STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value)
+__STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value) { SysTimer->MTIMER = value; }
-{
-    SysTimer->MTIMER = value;
-}
 
 /**
  * \brief  Get system timer load value
@@ -116,10 +113,7 @@ __STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value)
  * - Load value is 64bits wide.
  * - \ref SysTimer_SetLoadValue
  */
-__STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void)
+__STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void) { return SysTimer->MTIMER; }
-{
-    return SysTimer->MTIMER;
-}
 
 /**
  * \brief  Set system timer compare value
@@ -132,10 +126,7 @@ __STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void)
  * - Modify the load value or compare value less to clear the interrupt.
  * - \ref SysTimer_GetCompareValue
  */
-__STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value)
+__STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) { SysTimer->MTIMERCMP = value; }
-{
-    SysTimer->MTIMERCMP = value;
-}
 
 /**
  * \brief  Get system timer compare value
@@ -146,10 +137,7 @@ __STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value)
  * - Compare value is 64bits wide.
  * - \ref SysTimer_SetCompareValue
  */
-__STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void)
+__STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void) { return SysTimer->MTIMERCMP; }
-{
-    return SysTimer->MTIMERCMP;
-}
 
 /**
  * \brief  Enable system timer counter running
@@ -157,10 +145,7 @@ __STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void)
  * Enable system timer counter running by clear
  * TIMESTOP bit in MTIMECTL register.
  */
-__STATIC_FORCEINLINE void SysTimer_Start(void)
+__STATIC_FORCEINLINE void SysTimer_Start(void) { SysTimer->MTIMECTL &= ~(SysTimer_MTIMECTL_TIMESTOP_Msk); }
-{
-    SysTimer->MTIMECTL &= ~(SysTimer_MTIMECTL_TIMESTOP_Msk);
-}
 
 /**
  * \brief  Stop system timer counter running
@@ -168,10 +153,7 @@ __STATIC_FORCEINLINE void SysTimer_Start(void)
  * Stop system timer counter running by set
  * TIMESTOP bit in MTIMECTL register.
  */
-__STATIC_FORCEINLINE void SysTimer_Stop(void)
+__STATIC_FORCEINLINE void SysTimer_Stop(void) { SysTimer->MTIMECTL |= SysTimer_MTIMECTL_TIMESTOP_Msk; }
-{
-    SysTimer->MTIMECTL |= SysTimer_MTIMECTL_TIMESTOP_Msk;
-}
 
 /**
  * \brief  Set system timer control value
@@ -187,10 +169,7 @@ __STATIC_FORCEINLINE void SysTimer_Stop(void)
  *   Clear CLKSRC bit to 0 to use *mtime_toggle_a*, otherwise use *core_clk_aon*
  * - \ref SysTimer_GetControlValue
  */
-__STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl)
+__STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl) { SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk); }
-{
-    SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk);
-}
 
 /**
  * \brief  Get system timer control value
@@ -200,10 +179,7 @@ __STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl)
  * \remarks
  * - \ref SysTimer_SetControlValue
  */
-__STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void)
+__STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void) { return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk); }
-{
-    return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk);
-}
 
 /**
  * \brief  Trigger or set software interrupt via system timer
@@ -214,10 +190,7 @@ __STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void)
  * - \ref SysTimer_ClearSWIRQ
  * - \ref SysTimer_GetMsipValue
  */
-__STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void)
+__STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void) { SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk; }
-{
-    SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk;
-}
 
 /**
  * \brief  Clear system timer software interrupt pending request
@@ -228,10 +201,7 @@ __STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void)
  * - \ref SysTimer_SetSWIRQ
  * - \ref SysTimer_GetMsipValue
  */
-__STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void)
+__STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void) { SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk; }
-{
-    SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk;
-}
 
 /**
  * \brief  Get system timer MSIP register value
@@ -244,10 +214,7 @@ __STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void)
  * - \ref SysTimer_SetSWIRQ
  * - \ref SysTimer_ClearSWIRQ
  */
-__STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void)
+__STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void) { return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk); }
-{
-    return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk);
-}
 
 /**
  * \brief  Set system timer MSIP register value
@@ -255,10 +222,7 @@ __STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void)
  * This function set the system timer MSIP register value.
  * \param [in]  msip   value to set MSIP register
  */
-__STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip)
+__STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip) { SysTimer->MSIP = (msip & SysTimer_MSIP_Msk); }
-{
-    SysTimer->MSIP = (msip & SysTimer_MSIP_Msk);
-}
 
 /**
  * \brief  Do software reset request
@@ -270,10 +234,10 @@ __STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip)
  * - The software reset is sent to SoC, SoC need to generate reset signal and send back to Core
  * - This function will not return, it will do while(1) to wait the Core reset happened
  */
-__STATIC_FORCEINLINE void SysTimer_SoftwareReset(void)
+__STATIC_FORCEINLINE void SysTimer_SoftwareReset(void) {
-{
   SysTimer->MSFTRST = SysTimer_MSFRST_KEY;
-    while(1);
+  while (1)
+    ;
 }
 
 #if defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) && defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
@@ -301,8 +265,7 @@ __STATIC_FORCEINLINE void SysTimer_SoftwareReset(void)
  * \sa
  * - \ref SysTimer_SetCompareValue; SysTimer_SetLoadValue
  */
-__STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks) {
-{
   SysTimer_SetLoadValue(0);
   SysTimer_SetCompareValue(ticks);
   ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
@@ -334,8 +297,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks)
  * - \ref SysTimer_SetCompareValue
  * - \ref SysTimer_SetLoadValue
  */
-__STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks)
+__STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks) {
-{
   uint64_t cur_ticks    = SysTimer->MTIMER;
   uint64_t reload_ticks = ticks + cur_ticks;
 
@@ -361,4 +323,3 @@ __STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks)
 }
 #endif
 #endif /** __CORE_FEATURE_TIMER_H__  */
-

source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_compiler.h

@@ -32,6 +32,4 @@
 #error Unknown compiler.
 #endif
 
-
 #endif /* __NMSIS_COMPILER_H */
-

source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_gcc.h

@@ -22,8 +22,8 @@
  * @file     nmsis_gcc.h
  * @brief    NMSIS compiler GCC header file
  */
-#include <stdint.h>
 #include "riscv_encoding.h"
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -114,9 +114,7 @@
 #pragma GCC diagnostic ignored "-Wpacked"
 #pragma GCC diagnostic ignored "-Wattributes"
 /** \brief Packed struct for unaligned uint16_t write access */
-  __PACKED_STRUCT T_UINT16_WRITE {
+__PACKED_STRUCT        T_UINT16_WRITE { uint16_t v; };
-      uint16_t v;
-  };
 #pragma GCC diagnostic pop
 /** \brief Pointer for unaligned write of a uint16_t variable. */
 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
@@ -127,9 +125,7 @@
 #pragma GCC diagnostic ignored "-Wpacked"
 #pragma GCC diagnostic ignored "-Wattributes"
 /** \brief Packed struct for unaligned uint16_t read access */
-  __PACKED_STRUCT T_UINT16_READ {
+__PACKED_STRUCT        T_UINT16_READ { uint16_t v; };
-      uint16_t v;
-  };
 #pragma GCC diagnostic pop
 /** \brief Pointer for unaligned read of a uint16_t variable. */
 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
@@ -140,9 +136,7 @@
 #pragma GCC diagnostic ignored "-Wpacked"
 #pragma GCC diagnostic ignored "-Wattributes"
 /** \brief Packed struct for unaligned uint32_t write access */
-  __PACKED_STRUCT T_UINT32_WRITE {
+__PACKED_STRUCT        T_UINT32_WRITE { uint32_t v; };
-      uint32_t v;
-  };
 #pragma GCC diagnostic pop
 /** \brief Pointer for unaligned write of a uint32_t variable. */
 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
@@ -153,9 +147,7 @@
 #pragma GCC diagnostic ignored "-Wpacked"
 #pragma GCC diagnostic ignored "-Wattributes"
 /** \brief Packed struct for unaligned uint32_t read access */
-  __PACKED_STRUCT T_UINT32_READ {
+__PACKED_STRUCT        T_UINT32_READ { uint32_t v; };
-      uint32_t v;
-  };
 #pragma GCC diagnostic pop
 /** \brief Pointer for unaligned read of a uint32_t variable. */
 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
@@ -258,7 +250,6 @@
 
   /** @} */ /* end of group NMSIS_Core_PeriphAccess */
 
-
 #ifdef __cplusplus
 }
 #endif

source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/riscv_encoding.h

@@ -268,7 +268,6 @@
 /** Floating Point Register f0-f31, eg. f0 -> FREG(0) */
 #define FREG(idx) f##idx
 
-
 /* === PMP CFG Bits === */
 #define PMP_R       0x01
 #define PMP_W       0x02

source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/port.c

@@ -30,9 +30,9 @@
  *----------------------------------------------------------*/
 
 /* Scheduler includes. */
-#include <stdio.h>
 #include "FreeRTOS.h"
 #include "task.h"
+#include <stdio.h>
 
 //#define ENABLE_KERNEL_DEBUG
 
@@ -223,8 +223,7 @@ uint8_t uxMaxSysCallMTH = 255;
  * portTASK_RETURN_ADDRESS
  * pxCode
  */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) {
-{
   /* Simulate the stack frame as it would be created by a context switch
   interrupt. */
 
@@ -250,8 +249,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
 }
 /*-----------------------------------------------------------*/
 
-static void prvTaskExitError( void )
+static void prvTaskExitError(void) {
-{
   volatile uint32_t ulDummy = 0;
 
   /* A function that implements a task must not exit or attempt to return to
@@ -262,8 +260,7 @@ static void prvTaskExitError( void )
   defined, then stop here so application writers can catch the error. */
   configASSERT(uxCriticalNesting == ~0UL);
   portDISABLE_INTERRUPTS();
-    while( ulDummy == 0 )
+  while (ulDummy == 0) {
-    {
     /* This file calls prvTaskExitError() after the scheduler has been
     started to remove a compiler warning about the function being defined
     but never called.  ulDummy is used purely to quieten other warnings
@@ -277,8 +274,7 @@ static void prvTaskExitError( void )
 }
 /*-----------------------------------------------------------*/
 
-static uint8_t prvCheckMaxSysCallPrio( uint8_t max_syscall_prio )
+static uint8_t prvCheckMaxSysCallPrio(uint8_t max_syscall_prio) {
-{
   uint8_t nlbits     = __ECLIC_GetCfgNlbits();
   uint8_t intctlbits = __ECLIC_INTCTLBITS;
   uint8_t lvlbits, temp;
@@ -296,8 +292,7 @@ static uint8_t prvCheckMaxSysCallPrio( uint8_t max_syscall_prio )
   return max_syscall_prio;
 }
 
-static uint8_t prvCalcMaxSysCallMTH( uint8_t max_syscall_prio )
+static uint8_t prvCalcMaxSysCallMTH(uint8_t max_syscall_prio) {
-{
   uint8_t nlbits     = __ECLIC_GetCfgNlbits();
   uint8_t intctlbits = __ECLIC_INTCTLBITS;
   uint8_t lvlbits, lfabits;
@@ -325,8 +320,7 @@ static uint8_t prvCalcMaxSysCallMTH( uint8_t max_syscall_prio )
 /*
  * See header file for description.
  */
-BaseType_t xPortStartScheduler( void )
+BaseType_t xPortStartScheduler(void) {
-{
   /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. */
   configASSERT(configMAX_SYSCALL_INTERRUPT_PRIORITY);
 
@@ -367,16 +361,14 @@ BaseType_t xPortStartScheduler( void )
 }
 /*-----------------------------------------------------------*/
 
-void vPortEndScheduler( void )
+void vPortEndScheduler(void) {
-{
   /* Not implemented in ports where there is nothing to return to.
   Artificially force an assert. */
   configASSERT(uxCriticalNesting == 1000UL);
 }
 /*-----------------------------------------------------------*/
 
-void vPortEnterCritical( void )
+void vPortEnterCritical(void) {
-{
   portDISABLE_INTERRUPTS();
   uxCriticalNesting++;
 
@@ -385,26 +377,22 @@ void vPortEnterCritical( void )
   functions that end in "FromISR" can be used in an interrupt.  Only assert if
   the critical nesting count is 1 to protect against recursive calls if the
   assert function also uses a critical section. */
-    if( uxCriticalNesting == 1 )
+  if (uxCriticalNesting == 1) {
-    {
     configASSERT((__ECLIC_GetMth() & portMTH_MASK) == uxMaxSysCallMTH);
   }
 }
 /*-----------------------------------------------------------*/
 
-void vPortExitCritical( void )
+void vPortExitCritical(void) {
-{
   configASSERT(uxCriticalNesting);
   uxCriticalNesting--;
-    if( uxCriticalNesting == 0 )
+  if (uxCriticalNesting == 0) {
-    {
     portENABLE_INTERRUPTS();
   }
 }
 /*-----------------------------------------------------------*/
 
-void vPortAssert( int32_t x )
+void vPortAssert(int32_t x) {
-{
   TaskHandle_t th;
   if ((x) == 0) {
     taskDISABLE_INTERRUPTS();
@@ -422,9 +410,7 @@ void vPortAssert( int32_t x )
 }
 /*-----------------------------------------------------------*/
 
-
+void xPortTaskSwitch(void) {
-void xPortTaskSwitch( void )
-{
   portDISABLE_INTERRUPTS();
   /* Clear Software IRQ, A MUST */
   SysTimer_ClearSWIRQ();
@@ -433,8 +419,7 @@ void xPortTaskSwitch( void )
 }
 /*-----------------------------------------------------------*/
 
-void xPortSysTickHandler( void )
+void xPortSysTickHandler(void) {
-{
   /* The SysTick runs at the lowest interrupt priority, so when this interrupt
   executes all interrupts must be unmasked.  There is therefore no need to
   save and then restore the interrupt mask value as its value is already
@@ -443,8 +428,7 @@ void xPortSysTickHandler( void )
   {
     SysTick_Reload(SYSTICK_TICK_CONST);
     /* Increment the RTOS tick. */
-        if( xTaskIncrementTick() != pdFALSE )
+    if (xTaskIncrementTick() != pdFALSE) {
-        {
       /* A context switch is required.  Context switching is performed in
       the SWI interrupt.  Pend the SWI interrupt. */
       portYIELD();
@@ -456,16 +440,14 @@ void xPortSysTickHandler( void )
 
 #if (configUSE_TICKLESS_IDLE == 1)
 
-    __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+__attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) {
-    {
   uint32_t            ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
   volatile TickType_t xModifiableIdleTime, xTickCountBeforeSleep, XLastLoadValue;
 
   FREERTOS_PORT_DEBUG("Enter TickLess %d\n", (uint32_t)xExpectedIdleTime);
 
   /* Make sure the SysTick reload value does not overflow the counter. */
-        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+  if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks) {
-        {
     xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
   }
 
@@ -479,8 +461,7 @@ void xPortSysTickHandler( void )
   tick periods.  -1 is used because this code will execute part way
   through one of the tick periods. */
   ulReloadValue = (ulTimerCountsForOneTick * (xExpectedIdleTime - 1UL));
-        if( ulReloadValue > ulStoppedTimerCompensation )
+  if (ulReloadValue > ulStoppedTimerCompensation) {
-        {
     ulReloadValue -= ulStoppedTimerCompensation;
   }
 
@@ -490,8 +471,7 @@ void xPortSysTickHandler( void )
 
   /* If a context switch is pending or a task is waiting for the scheduler
   to be unsuspended then abandon the low power entry. */
-        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+  if (eTaskConfirmSleepModeStatus() == eAbortSleep) {
-        {
     /* Restart from whatever is left in the count register to complete
     this tick period. */
     /* Restart SysTick. */
@@ -504,9 +484,7 @@ void xPortSysTickHandler( void )
     /* Re-enable interrupts - see comments above the cpsid instruction()
        above. */
     __enable_irq();
-        }
+  } else {
-        else
-        {
     xTickCountBeforeSleep = xTaskGetTickCount();
 
     /* Set the new reload value. */
@@ -527,8 +505,7 @@ void xPortSysTickHandler( void )
     time variable must remain unmodified, so a copy is taken. */
     xModifiableIdleTime = xExpectedIdleTime;
     configPRE_SLEEP_PROCESSING(xModifiableIdleTime);
-            if( xModifiableIdleTime > 0 )
+    if (xModifiableIdleTime > 0) {
-            {
       __WFI();
     }
     configPOST_SLEEP_PROCESSING(xExpectedIdleTime);
@@ -558,16 +535,13 @@ void xPortSysTickHandler( void )
     /* Determine if SysTimer Interrupt is not yet happened,
     (in which case an interrupt other than the SysTick
     must have brought the system out of sleep mode). */
-            if (SysTimer_GetLoadValue() >= (XLastLoadValue + ulReloadValue))
+    if (SysTimer_GetLoadValue() >= (XLastLoadValue + ulReloadValue)) {
-            {
       /* As the pending tick will be processed as soon as this
       function exits, the tick value maintained by the tick is stepped
       forward by one less than the time spent waiting. */
       ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
       FREERTOS_PORT_DEBUG("TickLess - SysTimer Interrupt Entered!\n");
-            }
+    } else {
-            else
-            {
       /* Something other than the tick interrupt ended the sleep.
       Work out how long the sleep lasted rounded to complete tick
       periods (not the ulReload value which accounted for part
@@ -607,16 +581,15 @@ void xPortSysTickHandler( void )
  * Setup the systick timer to generate the tick interrupts at the required
  * frequency.
  */
-__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+__attribute__((weak)) void vPortSetupTimerInterrupt(void) {
-{
 /* Calculate the constants required to configure the tick interrupt. */
 #if (configUSE_TICKLESS_IDLE == 1)
   {
     ulTimerCountsForOneTick         = (SYSTICK_TICK_CONST);
     xMaximumPossibleSuppressedTicks = portMAX_BIT_NUMBER / ulTimerCountsForOneTick;
     ulStoppedTimerCompensation      = portMISSED_COUNTS_FACTOR / (configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ);
-        FREERTOS_PORT_DEBUG("CountsForOneTick, SuppressedTicks and TimerCompensation: %u, %u, %u\n", \
+    FREERTOS_PORT_DEBUG("CountsForOneTick, SuppressedTicks and TimerCompensation: %u, %u, %u\n", (uint32_t)ulTimerCountsForOneTick, (uint32_t)xMaximumPossibleSuppressedTicks,
-                (uint32_t)ulTimerCountsForOneTick, (uint32_t)xMaximumPossibleSuppressedTicks, (uint32_t)ulStoppedTimerCompensation);
+                        (uint32_t)ulStoppedTimerCompensation);
   }
 #endif /* configUSE_TICKLESS_IDLE */
   TickType_t ticks = SYSTICK_TICK_CONST;
@@ -640,8 +613,7 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
 
 #if (configASSERT_DEFINED == 1)
 
-    void vPortValidateInterruptPriority( void )
+void vPortValidateInterruptPriority(void) {
-    {
   uint32_t ulCurrentInterrupt;
   uint8_t  ucCurrentPriority;
 

source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/portmacro.h

@@ -25,7 +25,6 @@
  * 1 tab == 4 spaces!
  */
 
-
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
@@ -85,7 +84,9 @@ typedef unsigned long UBaseType_t;
     __RWMB();                                                                  \
   }
 
-#define portEND_SWITCHING_ISR( xSwitchRequired )    if ( xSwitchRequired != pdFALSE ) portYIELD()
+#define portEND_SWITCHING_ISR(xSwitchRequired) \
+  if (xSwitchRequired != pdFALSE)              \
+  portYIELD()
 #define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
 /*-----------------------------------------------------------*/
 
@@ -137,16 +138,14 @@ not necessary for to use this port.  They are defined so the common demo files
 extern uint8_t uxMaxSysCallMTH;
 
 /*-----------------------------------------------------------*/
-portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
-{
   ECLIC_SetMth(uxMaxSysCallMTH);
   __RWMB();
 }
 
 /*-----------------------------------------------------------*/
 
-portFORCE_INLINE static uint8_t ulPortRaiseBASEPRI( void )
+portFORCE_INLINE static uint8_t ulPortRaiseBASEPRI(void) {
-{
   uint8_t ulOriginalBASEPRI;
 
   ulOriginalBASEPRI = ECLIC_GetMth();
@@ -159,8 +158,7 @@ portFORCE_INLINE static uint8_t ulPortRaiseBASEPRI( void )
 }
 /*-----------------------------------------------------------*/
 
-portFORCE_INLINE static void vPortSetBASEPRI( uint8_t ulNewMaskValue )
+portFORCE_INLINE static void vPortSetBASEPRI(uint8_t ulNewMaskValue) {
-{
   ECLIC_SetMth(ulNewMaskValue);
   __RWMB();
 }
@@ -173,4 +171,3 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint8_t ulNewMaskValue )
 #endif
 
 #endif /* PORTMACRO_H */
-

source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/Include/nuclei_sdk_hal.h

@@ -8,7 +8,6 @@
 
 #include "gd32vf103v_eval.h"
 
-
 #ifndef NUCLEI_BANNER
 #define NUCLEI_BANNER 0
 #endif

source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/Source/gd32vf103v_eval.c

@@ -32,8 +32,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
 OF SUCH DAMAGE.
 */
 
-#include "nuclei_sdk_hal.h"
-#include "gd32vf103_usart.h"
-#include "gd32vf103_gpio.h"
 #include "gd32vf103_exti.h"
-
+#include "gd32vf103_gpio.h"
+#include "gd32vf103_usart.h"
+#include "nuclei_sdk_hal.h"