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Pinecilv2 adc v2 (#1916)

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* Updated NTC lookup

* remove float compute from adc (as we dont use it)

* Updated adc settings

* Updated ADC Init

* Custom max temp lookup

* Mask Timer around changing timer rate

* Use timer channels in sane order

* Update IRQ.cpp

* Remove ADC dummy wait on start/stop

* Dont use ADC IRQ

* Disable sampling delay

* Update Setup.cpp

* PinecilV2 disable ROM driver utils

Always use our source

* Force settings upgrade on PinecilV2

Fix forced settings upgrade on Pinecilv2

* Prevent ADC rollover

* Update Setup.cpp

* ADC cleanup

* Rollover prevention

* Measure tip temperature 2nd

* Rebase Buffalo SDK to 1.4.5 (#1923)

* Update bl702_adc.c

* Update board.c

* .

* Update bl702_adc.c

* Import updated hal_drv

* Remove accidental dupe of stack in linker

* First pass update BLE stack

* Update ReleaseNotes

* Update push.yml

* Drop BT Audio which we dont use

* .

* Reformat

* Update conn.c

* Update hog.c
This commit is contained in:
Ben V. Brown
2024-06-08 14:33:06 +10:00
committed by GitHub
parent 442dbd982e
commit 14b92cde08
121 changed files with 1989 additions and 11372 deletions
Download Patch File Download Diff File Expand all files Collapse all files

97
source/Core/BSP/Pinecilv2/Setup.cpp
View File

@@ -50,9 +50,10 @@ void hardware_init() {
gpio_set_mode(OLED_RESET_Pin, GPIO_OUTPUT_MODE);
gpio_set_mode(KEY_A_Pin, GPIO_INPUT_PD_MODE);
gpio_set_mode(KEY_B_Pin, GPIO_INPUT_PD_MODE);
gpio_set_mode(TMP36_INPUT_Pin, GPIO_INPUT_MODE);
gpio_set_mode(TIP_TEMP_Pin, GPIO_INPUT_MODE);
gpio_set_mode(VIN_Pin, GPIO_INPUT_MODE);
gpio_set_mode(TMP36_INPUT_Pin, GPIO_HZ_MODE);
gpio_set_mode(TIP_TEMP_Pin, GPIO_HZ_MODE);
gpio_set_mode(VIN_Pin, GPIO_HZ_MODE);
gpio_set_mode(TIP_RESISTANCE_SENSE, GPIO_OUTPUT_MODE);
gpio_write(TIP_RESISTANCE_SENSE, 0);
@@ -66,7 +67,7 @@ void hardware_init() {
// Note on I2C clock rate @ 100Khz the screen update == 20ms which is too long for USB-PD to work
// 200kHz and above works
I2C_ClockSet(I2C0_ID, 300000); // Sets clock to around 25 kHz less than set here
TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_1, 0);
TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_0, 0);
}
void setup_pwm(void) {
// Setup PWM we use for driving the tip
@@ -77,7 +78,7 @@ void setup_pwm(void) {
PWM_POL_NORMAL, // Normal Polarity
60, // Clock Div
100, // Period
0, // Thres 1 - start at beginng
0, // Thres 1 - start at beginning
50, // Thres 2 - turn off at 50%
0, // Interrupt pulse count
};
@@ -86,8 +87,8 @@ void setup_pwm(void) {
PWM_Channel_Disable(PWM_Channel);
}
const ADC_Chan_Type adc_tip_pos_chans[] = {TIP_TEMP_ADC_CHANNEL, TMP36_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL, VIN_ADC_CHANNEL,
TIP_TEMP_ADC_CHANNEL, TMP36_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL, VIN_ADC_CHANNEL};
const ADC_Chan_Type adc_tip_pos_chans[] = {TMP36_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL, VIN_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL,
TMP36_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL, VIN_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL};
const ADC_Chan_Type adc_tip_neg_chans[] = {ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND};
static_assert(sizeof(adc_tip_pos_chans) == sizeof(adc_tip_neg_chans));
@@ -96,21 +97,55 @@ void setup_adc(void) {
ADC_CFG_Type adc_cfg = {};
ADC_FIFO_Cfg_Type adc_fifo_cfg = {};
CPU_Interrupt_Disable(GPADC_DMA_IRQn);
// Please also see PR #1529 for even more context
ADC_IntMask(ADC_INT_ALL, MASK);
/*
A note on ADC settings
The bl70x ADC seems to be very sensitive to various analog settings.
It has been a challenge to determine what is the most correct way to
configure it in order to get accurate readings that can be transformed
into millivolts, for accurate measurements.
This latest set of ADC parameters, matches the latest configuration from
the upstream bl_mcu_sdk repository from commit hash:
9e189b69cbc0a75ffa170f600a28820848d56432
except for one difference.
(Note: bl_mcu_sdk has been heavily refactored since it has been imported into IronOS.)
You can make it match exactly by defining ENABLE_MIC2_DIFF, see the code
#ifdef ENABLE_MIC2_DIFF below.
I have decided to not apply this change because it appeared to make the
lower end of the input less precise.
Note that this configuration uses an ADC trimming value that is stored in the Efuse
of the bl70x chip. The actual reading is divided by this "coe" value.
We have found the following coe values on 3 different chips:
0.9629, 0.9438, 0.9876
Additional note for posterity:
PGA = programmable gain amplifier.
We would have expected to achieve the highest accuracy by disabling this amplifier,
however we found that not to be the case, and in almost all cases we have found
that there is a scaling error compared to the ideal Vref.
The only other configuration we have found to be accurate was if we had:
PGA disabled + Vref=2V + biasSel=AON + without trimming from the efuse.
But we can't use it because a Vref=2V limits the higher end of temperature and voltage readings.
Also we don't know if this other configuration is really accurate on all chips, or only
happened to be accurate on the one chip on which it has been found.
*/
adc_cfg.clkDiv = ADC_CLK_DIV_4;
adc_cfg.vref = ADC_VREF_3P2V;
adc_cfg.resWidth = ADC_DATA_WIDTH_14_WITH_16_AVERAGE;
adc_cfg.inputMode = ADC_INPUT_SINGLE_END;
adc_cfg.v18Sel = ADC_V18_SEL_1P72V;
adc_cfg.v18Sel = ADC_V18_SEL_1P82V;
adc_cfg.v11Sel = ADC_V11_SEL_1P1V;
adc_cfg.gain1 = ADC_PGA_GAIN_NONE;
adc_cfg.gain2 = ADC_PGA_GAIN_NONE;
adc_cfg.chopMode = ADC_CHOP_MOD_AZ_ON;
adc_cfg.gain1 = ADC_PGA_GAIN_1;
adc_cfg.gain2 = ADC_PGA_GAIN_1;
adc_cfg.chopMode = ADC_CHOP_MOD_AZ_PGA_ON;
adc_cfg.biasSel = ADC_BIAS_SEL_MAIN_BANDGAP;
adc_cfg.vcm = ADC_PGA_VCM_1P6V;
adc_cfg.vcm = ADC_PGA_VCM_1P2V;
adc_cfg.offsetCalibEn = DISABLE;
adc_cfg.offsetCalibVal = 0;
@@ -119,16 +154,32 @@ void setup_adc(void) {
ADC_Reset();
ADC_Init(&adc_cfg);
#ifdef ENABLE_MIC2_DIFF
// This is the change that enables MIC2_DIFF, for now deciding not to enable it, since it seems to make results slightly worse
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
}
#endif
#if 1
// this sets the CVSP field (ADC conversion speed)
{
uint32_t regCfg2;
regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x02);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2);
}
#endif
adc_fifo_cfg.dmaEn = DISABLE;
adc_fifo_cfg.fifoThreshold = ADC_FIFO_THRESHOLD_8; // Triger FIFO when all 8 measurements are done
adc_fifo_cfg.fifoThreshold = ADC_FIFO_THRESHOLD_1;
ADC_FIFO_Cfg(&adc_fifo_cfg);
ADC_MIC_Bias_Disable();
ADC_Tsen_Disable();
// Enable FiFo IRQ
Interrupt_Handler_Register(GPADC_DMA_IRQn, adc_fifo_irq);
ADC_IntMask(ADC_INT_FIFO_READY, UNMASK);
CPU_Interrupt_Enable(GPADC_DMA_IRQn);
ADC_Gain_Trim();
ADC_Stop();
ADC_FIFO_Clear();
ADC_Scan_Channel_Config(adc_tip_pos_chans, adc_tip_neg_chans, sizeof(adc_tip_pos_chans) / sizeof(ADC_Chan_Type), DISABLE);
@@ -143,10 +194,10 @@ void setup_timer_scheduler() {
TIMER_PRELOAD_TRIG_COMP2, // Trigger; reset after trigger 0
TIMER_COUNT_PRELOAD, // Counter mode
22, // Clock div
(uint16_t)(powerPWM + holdoffTicks), // CH0 compare (adc)
(uint16_t)(powerPWM), // CH1 compare (pwm out)
(uint16_t)(powerPWM), // CH0 compare (pwm out)
(uint16_t)(powerPWM + holdoffTicks), // CH1 compare (adc)
(uint16_t)(powerPWM + holdoffTicks + tempMeasureTicks), // CH2 compare end of cycle
0, // Preload
0, // Preload, copied to counter on trigger of comp2
};
TIMER_Init(&cfg);