From 0c13aae5f08889d965abb0d850907e2cc6b3bcf5 Mon Sep 17 00:00:00 2001 From: "Ben V. Brown" Date: Mon, 18 Apr 2022 19:24:23 +1000 Subject: [PATCH] Format adc headers --- source/Core/BSP/Magic/IRQ.cpp | 2 +- .../bl702_driver/std_drv/inc/bl702_adc.h | 531 ++-- .../bl702_driver/std_drv/src/bl702_adc.c | 2556 ++++++++--------- 3 files changed, 1491 insertions(+), 1598 deletions(-) diff --git a/source/Core/BSP/Magic/IRQ.cpp b/source/Core/BSP/Magic/IRQ.cpp index 731dd505..57252cb5 100644 --- a/source/Core/BSP/Magic/IRQ.cpp +++ b/source/Core/BSP/Magic/IRQ.cpp @@ -70,7 +70,7 @@ void start_adc_tip(void) { // The ADC has a 32 sample FiFo; we set this up to fire and interrupt at 16 samples // Then using that IRQ to know that sampling is done and can be stored ADC_Stop(); - ADC_Scan_Channel_Config((ADC_Chan_Type *)adc_tip_pos_chans, (ADC_Chan_Type *)adc_tip_neg_chans, 2, ENABLE); + ADC_Scan_Channel_Config((ADC_Chan_Type *)adc_tip_pos_chans, (ADC_Chan_Type *)adc_tip_neg_chans, 1, ENABLE); ADC_Start(); } const ADC_Chan_Type adc_misc_pos_chans[] = {TMP36_ADC_CHANNEL, VIN_ADC_CHANNEL}; diff --git a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h index 0fc12656..8619541f 100644 --- a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h +++ b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h @@ -1,44 +1,45 @@ /** - ****************************************************************************** - * @file bl702_adc.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file bl702_adc.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ #ifndef __BL702_ADC_H__ #define __BL702_ADC_H__ #include "aon_reg.h" -#include "gpip_reg.h" #include "bl702_common.h" +#include "gpip_reg.h" + /** @addtogroup BL702_Peripheral_Driver * @{ @@ -56,268 +57,263 @@ * @brief ADC channel type definition */ typedef enum { - ADC_CHAN0, /*!< ADC channel 0 */ - ADC_CHAN1, /*!< ADC channel 1 */ - ADC_CHAN2, /*!< ADC channel 2 */ - ADC_CHAN3, /*!< ADC channel 3 */ - ADC_CHAN4, /*!< ADC channel 4 */ - ADC_CHAN5, /*!< ADC channel 5 */ - ADC_CHAN6, /*!< ADC channel 6 */ - ADC_CHAN7, /*!< ADC channel 7 */ - ADC_CHAN8, /*!< ADC channel 8 */ - ADC_CHAN9, /*!< ADC channel 9 */ - ADC_CHAN10, /*!< ADC channel 10 */ - ADC_CHAN11, /*!< ADC channel 11 */ - ADC_CHAN_DAC_OUTA, /*!< DACA, ADC channel 12 */ - ADC_CHAN_DAC_OUTB, /*!< DACB, ADC channel 13 */ - ADC_CHAN_TSEN_P, /*!< TSenp, ADC channel 14 */ - ADC_CHAN_TSEN_N, /*!< TSenn, ADC channel 15 */ - ADC_CHAN_VREF, /*!< Vref, ADC channel 16 */ - ADC_CHAN_DCTEST, /*!< DCTest, ADC channel 17 */ - ADC_CHAN_VABT_HALF, /*!< VBAT/2, ADC channel 18 */ - ADC_CHAN_SENP3, /*!< SenVP3, ADC channel 19 */ - ADC_CHAN_SENP2, /*!< SenVP2, ADC channel 20 */ - ADC_CHAN_SENP1, /*!< SenVP1, ADC channel 21 */ - ADC_CHAN_SENP0, /*!< SenVP0, ADC channel 22 */ - ADC_CHAN_GND, /*!< GND, ADC channel 23 */ + ADC_CHAN0, /*!< ADC channel 0 */ + ADC_CHAN1, /*!< ADC channel 1 */ + ADC_CHAN2, /*!< ADC channel 2 */ + ADC_CHAN3, /*!< ADC channel 3 */ + ADC_CHAN4, /*!< ADC channel 4 */ + ADC_CHAN5, /*!< ADC channel 5 */ + ADC_CHAN6, /*!< ADC channel 6 */ + ADC_CHAN7, /*!< ADC channel 7 */ + ADC_CHAN8, /*!< ADC channel 8 */ + ADC_CHAN9, /*!< ADC channel 9 */ + ADC_CHAN10, /*!< ADC channel 10 */ + ADC_CHAN11, /*!< ADC channel 11 */ + ADC_CHAN_DAC_OUTA, /*!< DACA, ADC channel 12 */ + ADC_CHAN_DAC_OUTB, /*!< DACB, ADC channel 13 */ + ADC_CHAN_TSEN_P, /*!< TSenp, ADC channel 14 */ + ADC_CHAN_TSEN_N, /*!< TSenn, ADC channel 15 */ + ADC_CHAN_VREF, /*!< Vref, ADC channel 16 */ + ADC_CHAN_DCTEST, /*!< DCTest, ADC channel 17 */ + ADC_CHAN_VABT_HALF, /*!< VBAT/2, ADC channel 18 */ + ADC_CHAN_SENP3, /*!< SenVP3, ADC channel 19 */ + ADC_CHAN_SENP2, /*!< SenVP2, ADC channel 20 */ + ADC_CHAN_SENP1, /*!< SenVP1, ADC channel 21 */ + ADC_CHAN_SENP0, /*!< SenVP0, ADC channel 22 */ + ADC_CHAN_GND, /*!< GND, ADC channel 23 */ } ADC_Chan_Type; /** * @brief ADC V18 selection type definition */ typedef enum { - ADC_V18_SEL_1P62V, /*!< V18 select 1.62V */ - ADC_V18_SEL_1P72V, /*!< V18 select 1.72V */ - ADC_V18_SEL_1P82V, /*!< V18 select 1.82V */ - ADC_V18_SEL_1P92V, /*!< V18 select 1.92V */ + ADC_V18_SEL_1P62V, /*!< V18 select 1.62V */ + ADC_V18_SEL_1P72V, /*!< V18 select 1.72V */ + ADC_V18_SEL_1P82V, /*!< V18 select 1.82V */ + ADC_V18_SEL_1P92V, /*!< V18 select 1.92V */ } ADC_V18_SEL_Type; /** * @brief ADC V11 selection type definition */ typedef enum { - ADC_V11_SEL_1P0V, /*!< V11 select 1.0V */ - ADC_V11_SEL_1P1V, /*!< V11 select 1.1V */ - ADC_V11_SEL_1P18V, /*!< V11 select 1.18V */ - ADC_V11_SEL_1P26V, /*!< V11 select 1.26V */ + ADC_V11_SEL_1P0V, /*!< V11 select 1.0V */ + ADC_V11_SEL_1P1V, /*!< V11 select 1.1V */ + ADC_V11_SEL_1P18V, /*!< V11 select 1.18V */ + ADC_V11_SEL_1P26V, /*!< V11 select 1.26V */ } ADC_V11_SEL_Type; /** * @brief ADC clock type definition */ typedef enum { - ADC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ - ADC_CLK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ - ADC_CLK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ - ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ - ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ - ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ - ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ - ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ + ADC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ + ADC_CLK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ + ADC_CLK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ + ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ + ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ + ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ + ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ + ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ } ADC_CLK_Type; /** * @brief ADC conversion speed type definition */ typedef enum { - ADC_DELAY_SEL_0, /*!< Select delay 0 */ - ADC_DELAY_SEL_1, /*!< Select delay 1 */ - ADC_DELAY_SEL_2, /*!< Select delay 2 */ - ADC_DELAY_SEL_3, /*!< Select delay 3 */ - ADC_DELAY_SEL_4, /*!< Select delay 4, not recommend */ - ADC_DELAY_SEL_5, /*!< Select delay 5, not recommend */ - ADC_DELAY_SEL_6, /*!< Select delay 6, not recommend */ - ADC_DELAY_SEL_7, /*!< Select delay 7, not recommend */ + ADC_DELAY_SEL_0, /*!< Select delay 0 */ + ADC_DELAY_SEL_1, /*!< Select delay 1 */ + ADC_DELAY_SEL_2, /*!< Select delay 2 */ + ADC_DELAY_SEL_3, /*!< Select delay 3 */ + ADC_DELAY_SEL_4, /*!< Select delay 4, not recommend */ + ADC_DELAY_SEL_5, /*!< Select delay 5, not recommend */ + ADC_DELAY_SEL_6, /*!< Select delay 6, not recommend */ + ADC_DELAY_SEL_7, /*!< Select delay 7, not recommend */ } ADC_DELAY_SEL_Type; /** * @brief ADC PGA gain type definition */ typedef enum { - ADC_PGA_GAIN_NONE, /*!< No PGA gain */ - ADC_PGA_GAIN_1, /*!< PGA gain 1 */ - ADC_PGA_GAIN_2, /*!< PGA gain 2 */ - ADC_PGA_GAIN_4, /*!< PGA gain 4 */ - ADC_PGA_GAIN_8, /*!< PGA gain 8 */ - ADC_PGA_GAIN_16, /*!< PGA gain 16 */ - ADC_PGA_GAIN_32, /*!< PGA gain 32 */ + ADC_PGA_GAIN_NONE, /*!< No PGA gain */ + ADC_PGA_GAIN_1, /*!< PGA gain 1 */ + ADC_PGA_GAIN_2, /*!< PGA gain 2 */ + ADC_PGA_GAIN_4, /*!< PGA gain 4 */ + ADC_PGA_GAIN_8, /*!< PGA gain 8 */ + ADC_PGA_GAIN_16, /*!< PGA gain 16 */ + ADC_PGA_GAIN_32, /*!< PGA gain 32 */ } ADC_PGA_GAIN_Type; /** * @brief ADC analog portion low power mode selection type definition */ typedef enum { - ADC_BIAS_SEL_MAIN_BANDGAP, /*!< ADC current from main bandgap */ - ADC_BIAS_SEL_AON_BANDGAP, /*!< ADC current from aon bandgap for HBN mode */ + ADC_BIAS_SEL_MAIN_BANDGAP, /*!< ADC current from main bandgap */ + ADC_BIAS_SEL_AON_BANDGAP, /*!< ADC current from aon bandgap for HBN mode */ } ADC_BIAS_SEL_Type; /** * @brief ADC chop mode type definition */ typedef enum { - ADC_CHOP_MOD_ALL_OFF, /*!< all off */ - ADC_CHOP_MOD_AZ_ON, /*!< Vref AZ on */ - ADC_CHOP_MOD_AZ_PGA_ON, /*!< Vref AZ and PGA chop on */ - ADC_CHOP_MOD_AZ_PGA_RPC_ON, /*!< Vref AZ and PGA chop+RPC on */ + ADC_CHOP_MOD_ALL_OFF, /*!< all off */ + ADC_CHOP_MOD_AZ_ON, /*!< Vref AZ on */ + ADC_CHOP_MOD_AZ_PGA_ON, /*!< Vref AZ and PGA chop on */ + ADC_CHOP_MOD_AZ_PGA_RPC_ON, /*!< Vref AZ and PGA chop+RPC on */ } ADC_CHOP_MOD_Type; /** * @brief ADC audio PGA output common mode control type definition */ typedef enum { - ADC_PGA_VCM_1V, /*!< ADC VCM=1V */ - ADC_PGA_VCM_1P2V, /*!< ADC VCM=1.2V */ - ADC_PGA_VCM_1P4V, /*!< ADC VCM=1.4V */ - ADC_PGA_VCM_1P6V, /*!< ADC VCM=1.6V */ + ADC_PGA_VCM_1V, /*!< ADC VCM=1V */ + ADC_PGA_VCM_1P2V, /*!< ADC VCM=1.2V */ + ADC_PGA_VCM_1P4V, /*!< ADC VCM=1.4V */ + ADC_PGA_VCM_1P6V, /*!< ADC VCM=1.6V */ } ADC_PGA_VCM_Type; /** * @brief ADC tsen diode mode type definition */ typedef enum { - ADC_TSEN_MOD_INTERNAL_DIODE, /*!< Internal diode mode */ - ADC_TSEN_MOD_EXTERNAL_DIODE, /*!< External diode mode */ + ADC_TSEN_MOD_INTERNAL_DIODE, /*!< Internal diode mode */ + ADC_TSEN_MOD_EXTERNAL_DIODE, /*!< External diode mode */ } ADC_TSEN_MOD_Type; /** * @brief ADC voltage reference type definition */ typedef enum { - ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */ - ADC_VREF_2P0V, /*!< ADC select 2V as reference voltage */ + ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */ + ADC_VREF_2P0V, /*!< ADC select 2V as reference voltage */ } ADC_VREF_Type; /** * @brief ADC signal input type definition */ typedef enum { - ADC_INPUT_SINGLE_END, /*!< ADC signal is single end */ - ADC_INPUT_DIFF, /*!< ADC signal is differential */ + ADC_INPUT_SINGLE_END, /*!< ADC signal is single end */ + ADC_INPUT_DIFF, /*!< ADC signal is differential */ } ADC_SIG_INPUT_Type; /** * @brief ADC data width type definition */ typedef enum { - ADC_DATA_WIDTH_12, /*!< ADC 12 bits */ - ADC_DATA_WIDTH_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ - ADC_DATA_WIDTH_14_WITH_64_AVERAGE, /*!< ADC 14 bits,and the value is average of 64 converts */ - ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ - ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ + ADC_DATA_WIDTH_12, /*!< ADC 12 bits */ + ADC_DATA_WIDTH_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ + ADC_DATA_WIDTH_14_WITH_64_AVERAGE, /*!< ADC 14 bits,and the value is average of 64 converts */ + ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ + ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ } ADC_Data_Width_Type; /** * @brief ADC micboost 32db type definition */ typedef enum { - ADC_MICBOOST_DB_16DB, /*!< MIC boost 16db */ - ADC_MICBOOST_DB_32DB, /*!< MIC boost 32db */ + ADC_MICBOOST_DB_16DB, /*!< MIC boost 16db */ + ADC_MICBOOST_DB_32DB, /*!< MIC boost 32db */ } ADC_MICBOOST_DB_Type; /** * @brief ADC pga2 gain type definition */ typedef enum { - ADC_PGA2_GAIN_0DB, /*!< MIC pga2 gain 0db */ - ADC_PGA2_GAIN_6DB, /*!< MIC pga2 gain 6db */ - ADC_PGA2_GAIN_N6DB, /*!< MIC pga2 gain -6db */ - ADC_PGA2_GAIN_12DB, /*!< MIC pga2 gain 12db */ + ADC_PGA2_GAIN_0DB, /*!< MIC pga2 gain 0db */ + ADC_PGA2_GAIN_6DB, /*!< MIC pga2 gain 6db */ + ADC_PGA2_GAIN_N6DB, /*!< MIC pga2 gain -6db */ + ADC_PGA2_GAIN_12DB, /*!< MIC pga2 gain 12db */ } ADC_PGA2_GAIN_Type; /** * @brief ADC mic mode type definition */ typedef enum { - ADC_MIC_MODE_SINGLE, /*!< MIC single mode */ - ADC_MIC_MODE_DIFF, /*!< MIC diff mode */ + ADC_MIC_MODE_SINGLE, /*!< MIC single mode */ + ADC_MIC_MODE_DIFF, /*!< MIC diff mode */ } ADC_MIC_MODE_Type; /** * @brief ADC mic type definition */ -typedef struct -{ - ADC_MICBOOST_DB_Type micboostDb; /*!< MIC boost db */ - ADC_PGA2_GAIN_Type micPga2Gain; /*!< MIC pga2 gain */ - ADC_MIC_MODE_Type mic1Mode; /*!< MIC1 single or diff */ - ADC_MIC_MODE_Type mic2Mode; /*!< MIC2 single or diff */ - BL_Fun_Type dwaEn; /*!< Improve dynamic performance */ - BL_Fun_Type micboostBypassEn; /*!< MIC boost amp bypass enable or disable */ - BL_Fun_Type micPgaEn; /*!< MIC pga enable or disable */ - BL_Fun_Type micBiasEn; /*!< MIC bias enable or disable */ +typedef struct { + ADC_MICBOOST_DB_Type micboostDb; /*!< MIC boost db */ + ADC_PGA2_GAIN_Type micPga2Gain; /*!< MIC pga2 gain */ + ADC_MIC_MODE_Type mic1Mode; /*!< MIC1 single or diff */ + ADC_MIC_MODE_Type mic2Mode; /*!< MIC2 single or diff */ + BL_Fun_Type dwaEn; /*!< Improve dynamic performance */ + BL_Fun_Type micboostBypassEn; /*!< MIC boost amp bypass enable or disable */ + BL_Fun_Type micPgaEn; /*!< MIC pga enable or disable */ + BL_Fun_Type micBiasEn; /*!< MIC bias enable or disable */ } ADC_MIC_Type; /** * @brief ADC configuration type definition */ -typedef struct -{ - ADC_V18_SEL_Type v18Sel; /*!< ADC 1.8V select */ - ADC_V11_SEL_Type v11Sel; /*!< ADC 1.1V select */ - ADC_CLK_Type clkDiv; /*!< Clock divider */ - ADC_PGA_GAIN_Type gain1; /*!< PGA gain 1 */ - ADC_PGA_GAIN_Type gain2; /*!< PGA gain 2 */ - ADC_CHOP_MOD_Type chopMode; /*!< ADC chop mode select */ - ADC_BIAS_SEL_Type biasSel; /*!< ADC current form main bandgap or aon bandgap */ - ADC_PGA_VCM_Type vcm; /*!< ADC VCM value */ - ADC_VREF_Type vref; /*!< ADC voltage reference */ - ADC_SIG_INPUT_Type inputMode; /*!< ADC input signal type */ - ADC_Data_Width_Type resWidth; /*!< ADC resolution and oversample rate */ - BL_Fun_Type offsetCalibEn; /*!< Offset calibration enable */ - int16_t offsetCalibVal; /*!< Offset calibration value */ +typedef struct { + ADC_V18_SEL_Type v18Sel; /*!< ADC 1.8V select */ + ADC_V11_SEL_Type v11Sel; /*!< ADC 1.1V select */ + ADC_CLK_Type clkDiv; /*!< Clock divider */ + ADC_PGA_GAIN_Type gain1; /*!< PGA gain 1 */ + ADC_PGA_GAIN_Type gain2; /*!< PGA gain 2 */ + ADC_CHOP_MOD_Type chopMode; /*!< ADC chop mode select */ + ADC_BIAS_SEL_Type biasSel; /*!< ADC current form main bandgap or aon bandgap */ + ADC_PGA_VCM_Type vcm; /*!< ADC VCM value */ + ADC_VREF_Type vref; /*!< ADC voltage reference */ + ADC_SIG_INPUT_Type inputMode; /*!< ADC input signal type */ + ADC_Data_Width_Type resWidth; /*!< ADC resolution and oversample rate */ + BL_Fun_Type offsetCalibEn; /*!< Offset calibration enable */ + int16_t offsetCalibVal; /*!< Offset calibration value */ } ADC_CFG_Type; /** * @brief ADC configuration type definition */ -typedef struct -{ - int8_t posChan; /*!< Positive channel */ - int8_t negChan; /*!< Negative channel */ - uint16_t value; /*!< ADC value */ - float volt; /*!< ADC voltage result */ +typedef struct { + int8_t posChan; /*!< Positive channel */ + int8_t negChan; /*!< Negative channel */ + uint16_t value; /*!< ADC value */ + float volt; /*!< ADC voltage result */ } ADC_Result_Type; /** * @brief ADC FIFO threshold type definition */ typedef enum { - ADC_FIFO_THRESHOLD_1, /*!< ADC FIFO threshold is 1 */ - ADC_FIFO_THRESHOLD_4, /*!< ADC FIFO threshold is 4 */ - ADC_FIFO_THRESHOLD_8, /*!< ADC FIFO threshold is 8 */ - ADC_FIFO_THRESHOLD_16, /*!< ADC FIFO threshold is 16 */ + ADC_FIFO_THRESHOLD_1, /*!< ADC FIFO threshold is 1 */ + ADC_FIFO_THRESHOLD_4, /*!< ADC FIFO threshold is 4 */ + ADC_FIFO_THRESHOLD_8, /*!< ADC FIFO threshold is 8 */ + ADC_FIFO_THRESHOLD_16, /*!< ADC FIFO threshold is 16 */ } ADC_FIFO_Threshold_Type; /** * @brief ADC interrupt type definition */ typedef enum { - ADC_INT_POS_SATURATION, /*!< ADC positive channel saturation */ - ADC_INT_NEG_SATURATION, /*!< ADC negative channel saturation */ - ADC_INT_FIFO_UNDERRUN, /*!< ADC FIFO underrun interrupt */ - ADC_INT_FIFO_OVERRUN, /*!< ADC FIFO overrun interrupt */ - ADC_INT_ADC_READY, /*!< ADC data ready interrupt */ - ADC_INT_FIFO_READY, /*!< ADC FIFO count upper to threhold interrupt */ - ADC_INT_ALL, /*!< ADC all the interrupt */ + ADC_INT_POS_SATURATION, /*!< ADC positive channel saturation */ + ADC_INT_NEG_SATURATION, /*!< ADC negative channel saturation */ + ADC_INT_FIFO_UNDERRUN, /*!< ADC FIFO underrun interrupt */ + ADC_INT_FIFO_OVERRUN, /*!< ADC FIFO overrun interrupt */ + ADC_INT_ADC_READY, /*!< ADC data ready interrupt */ + ADC_INT_FIFO_READY, /*!< ADC FIFO count upper to threhold interrupt */ + ADC_INT_ALL, /*!< ADC all the interrupt */ } ADC_INT_Type; /** * @brief ADC FIFO configuration structure type definition */ -typedef struct -{ - ADC_FIFO_Threshold_Type fifoThreshold; /*!< ADC FIFO threshold */ - BL_Fun_Type dmaEn; /*!< ADC DMA enable */ +typedef struct { + ADC_FIFO_Threshold_Type fifoThreshold; /*!< ADC FIFO threshold */ + BL_Fun_Type dmaEn; /*!< ADC DMA enable */ } ADC_FIFO_Cfg_Type; /** * @brief ADC REG GAIN CAL */ -typedef struct -{ - BL_Fun_Type adcGainCoeffEnable; /*!< ADC_Gain_Coeff enable */ - uint16_t adcgainCoeffVal; /*!< ADC_Gain_Coeff value */ - float coe; /*!< ADC_Gain_Coeff result */ +typedef struct { + BL_Fun_Type adcGainCoeffEnable; /*!< ADC_Gain_Coeff enable */ + uint16_t adcgainCoeffVal; /*!< ADC_Gain_Coeff value */ + float coe; /*!< ADC_Gain_Coeff result */ } ADC_Gain_Coeff_Type; /*@} end of group ADC_Public_Types */ @@ -329,169 +325,106 @@ typedef struct /** @defgroup ADC_CHAN_TYPE * @{ */ -#define IS_ADC_CHAN_TYPE(type) (((type) == ADC_CHAN0) || \ - ((type) == ADC_CHAN1) || \ - ((type) == ADC_CHAN2) || \ - ((type) == ADC_CHAN3) || \ - ((type) == ADC_CHAN4) || \ - ((type) == ADC_CHAN5) || \ - ((type) == ADC_CHAN6) || \ - ((type) == ADC_CHAN7) || \ - ((type) == ADC_CHAN8) || \ - ((type) == ADC_CHAN9) || \ - ((type) == ADC_CHAN10) || \ - ((type) == ADC_CHAN11) || \ - ((type) == ADC_CHAN_DAC_OUTA) || \ - ((type) == ADC_CHAN_DAC_OUTB) || \ - ((type) == ADC_CHAN_TSEN_P) || \ - ((type) == ADC_CHAN_TSEN_N) || \ - ((type) == ADC_CHAN_VREF) || \ - ((type) == ADC_CHAN_DCTEST) || \ - ((type) == ADC_CHAN_VABT_HALF) || \ - ((type) == ADC_CHAN_SENP3) || \ - ((type) == ADC_CHAN_SENP2) || \ - ((type) == ADC_CHAN_SENP1) || \ - ((type) == ADC_CHAN_SENP0) || \ - ((type) == ADC_CHAN_GND)) +#define IS_ADC_CHAN_TYPE(type) \ + (((type) == ADC_CHAN0) || ((type) == ADC_CHAN1) || ((type) == ADC_CHAN2) || ((type) == ADC_CHAN3) || ((type) == ADC_CHAN4) || ((type) == ADC_CHAN5) || ((type) == ADC_CHAN6) \ + || ((type) == ADC_CHAN7) || ((type) == ADC_CHAN8) || ((type) == ADC_CHAN9) || ((type) == ADC_CHAN10) || ((type) == ADC_CHAN11) || ((type) == ADC_CHAN_DAC_OUTA) || ((type) == ADC_CHAN_DAC_OUTB) \ + || ((type) == ADC_CHAN_TSEN_P) || ((type) == ADC_CHAN_TSEN_N) || ((type) == ADC_CHAN_VREF) || ((type) == ADC_CHAN_DCTEST) || ((type) == ADC_CHAN_VABT_HALF) || ((type) == ADC_CHAN_SENP3) \ + || ((type) == ADC_CHAN_SENP2) || ((type) == ADC_CHAN_SENP1) || ((type) == ADC_CHAN_SENP0) || ((type) == ADC_CHAN_GND)) /** @defgroup ADC_V18_SEL_TYPE * @{ */ -#define IS_ADC_V18_SEL_TYPE(type) (((type) == ADC_V18_SEL_1P62V) || \ - ((type) == ADC_V18_SEL_1P72V) || \ - ((type) == ADC_V18_SEL_1P82V) || \ - ((type) == ADC_V18_SEL_1P92V)) +#define IS_ADC_V18_SEL_TYPE(type) (((type) == ADC_V18_SEL_1P62V) || ((type) == ADC_V18_SEL_1P72V) || ((type) == ADC_V18_SEL_1P82V) || ((type) == ADC_V18_SEL_1P92V)) /** @defgroup ADC_V11_SEL_TYPE * @{ */ -#define IS_ADC_V11_SEL_TYPE(type) (((type) == ADC_V11_SEL_1P0V) || \ - ((type) == ADC_V11_SEL_1P1V) || \ - ((type) == ADC_V11_SEL_1P18V) || \ - ((type) == ADC_V11_SEL_1P26V)) +#define IS_ADC_V11_SEL_TYPE(type) (((type) == ADC_V11_SEL_1P0V) || ((type) == ADC_V11_SEL_1P1V) || ((type) == ADC_V11_SEL_1P18V) || ((type) == ADC_V11_SEL_1P26V)) /** @defgroup ADC_CLK_TYPE * @{ */ -#define IS_ADC_CLK_TYPE(type) (((type) == ADC_CLK_DIV_1) || \ - ((type) == ADC_CLK_DIV_4) || \ - ((type) == ADC_CLK_DIV_8) || \ - ((type) == ADC_CLK_DIV_12) || \ - ((type) == ADC_CLK_DIV_16) || \ - ((type) == ADC_CLK_DIV_20) || \ - ((type) == ADC_CLK_DIV_24) || \ - ((type) == ADC_CLK_DIV_32)) +#define IS_ADC_CLK_TYPE(type) \ + (((type) == ADC_CLK_DIV_1) || ((type) == ADC_CLK_DIV_4) || ((type) == ADC_CLK_DIV_8) || ((type) == ADC_CLK_DIV_12) || ((type) == ADC_CLK_DIV_16) || ((type) == ADC_CLK_DIV_20) \ + || ((type) == ADC_CLK_DIV_24) || ((type) == ADC_CLK_DIV_32)) /** @defgroup ADC_DELAY_SEL_TYPE * @{ */ -#define IS_ADC_DELAY_SEL_TYPE(type) (((type) == ADC_DELAY_SEL_0) || \ - ((type) == ADC_DELAY_SEL_1) || \ - ((type) == ADC_DELAY_SEL_2) || \ - ((type) == ADC_DELAY_SEL_3) || \ - ((type) == ADC_DELAY_SEL_4) || \ - ((type) == ADC_DELAY_SEL_5) || \ - ((type) == ADC_DELAY_SEL_6) || \ - ((type) == ADC_DELAY_SEL_7)) +#define IS_ADC_DELAY_SEL_TYPE(type) \ + (((type) == ADC_DELAY_SEL_0) || ((type) == ADC_DELAY_SEL_1) || ((type) == ADC_DELAY_SEL_2) || ((type) == ADC_DELAY_SEL_3) || ((type) == ADC_DELAY_SEL_4) || ((type) == ADC_DELAY_SEL_5) \ + || ((type) == ADC_DELAY_SEL_6) || ((type) == ADC_DELAY_SEL_7)) /** @defgroup ADC_PGA_GAIN_TYPE * @{ */ -#define IS_ADC_PGA_GAIN_TYPE(type) (((type) == ADC_PGA_GAIN_NONE) || \ - ((type) == ADC_PGA_GAIN_1) || \ - ((type) == ADC_PGA_GAIN_2) || \ - ((type) == ADC_PGA_GAIN_4) || \ - ((type) == ADC_PGA_GAIN_8) || \ - ((type) == ADC_PGA_GAIN_16) || \ - ((type) == ADC_PGA_GAIN_32)) +#define IS_ADC_PGA_GAIN_TYPE(type) \ + (((type) == ADC_PGA_GAIN_NONE) || ((type) == ADC_PGA_GAIN_1) || ((type) == ADC_PGA_GAIN_2) || ((type) == ADC_PGA_GAIN_4) || ((type) == ADC_PGA_GAIN_8) || ((type) == ADC_PGA_GAIN_16) \ + || ((type) == ADC_PGA_GAIN_32)) /** @defgroup ADC_BIAS_SEL_TYPE * @{ */ -#define IS_ADC_BIAS_SEL_TYPE(type) (((type) == ADC_BIAS_SEL_MAIN_BANDGAP) || \ - ((type) == ADC_BIAS_SEL_AON_BANDGAP)) +#define IS_ADC_BIAS_SEL_TYPE(type) (((type) == ADC_BIAS_SEL_MAIN_BANDGAP) || ((type) == ADC_BIAS_SEL_AON_BANDGAP)) /** @defgroup ADC_CHOP_MOD_TYPE * @{ */ -#define IS_ADC_CHOP_MOD_TYPE(type) (((type) == ADC_CHOP_MOD_ALL_OFF) || \ - ((type) == ADC_CHOP_MOD_AZ_ON) || \ - ((type) == ADC_CHOP_MOD_AZ_PGA_ON) || \ - ((type) == ADC_CHOP_MOD_AZ_PGA_RPC_ON)) +#define IS_ADC_CHOP_MOD_TYPE(type) (((type) == ADC_CHOP_MOD_ALL_OFF) || ((type) == ADC_CHOP_MOD_AZ_ON) || ((type) == ADC_CHOP_MOD_AZ_PGA_ON) || ((type) == ADC_CHOP_MOD_AZ_PGA_RPC_ON)) /** @defgroup ADC_PGA_VCM_TYPE * @{ */ -#define IS_ADC_PGA_VCM_TYPE(type) (((type) == ADC_PGA_VCM_1V) || \ - ((type) == ADC_PGA_VCM_1P2V) || \ - ((type) == ADC_PGA_VCM_1P4V) || \ - ((type) == ADC_PGA_VCM_1P6V)) +#define IS_ADC_PGA_VCM_TYPE(type) (((type) == ADC_PGA_VCM_1V) || ((type) == ADC_PGA_VCM_1P2V) || ((type) == ADC_PGA_VCM_1P4V) || ((type) == ADC_PGA_VCM_1P6V)) /** @defgroup ADC_TSEN_MOD_TYPE * @{ */ -#define IS_ADC_TSEN_MOD_TYPE(type) (((type) == ADC_TSEN_MOD_INTERNAL_DIODE) || \ - ((type) == ADC_TSEN_MOD_EXTERNAL_DIODE)) +#define IS_ADC_TSEN_MOD_TYPE(type) (((type) == ADC_TSEN_MOD_INTERNAL_DIODE) || ((type) == ADC_TSEN_MOD_EXTERNAL_DIODE)) /** @defgroup ADC_VREF_TYPE * @{ */ -#define IS_ADC_VREF_TYPE(type) (((type) == ADC_VREF_3P3V) || \ - ((type) == ADC_VREF_2V)) +#define IS_ADC_VREF_TYPE(type) (((type) == ADC_VREF_3P3V) || ((type) == ADC_VREF_2V)) /** @defgroup ADC_SIG_INPUT_TYPE * @{ */ -#define IS_ADC_SIG_INPUT_TYPE(type) (((type) == ADC_INPUT_SINGLE_END) || \ - ((type) == ADC_INPUT_DIFF)) +#define IS_ADC_SIG_INPUT_TYPE(type) (((type) == ADC_INPUT_SINGLE_END) || ((type) == ADC_INPUT_DIFF)) /** @defgroup ADC_DATA_WIDTH_TYPE * @{ */ -#define IS_ADC_DATA_WIDTH_TYPE(type) (((type) == ADC_DATA_WIDTH_12) || \ - ((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || \ - ((type) == ADC_DATA_WIDTH_14_WITH_64_AVERAGE) || \ - ((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || \ - ((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) +#define IS_ADC_DATA_WIDTH_TYPE(type) \ + (((type) == ADC_DATA_WIDTH_12) || ((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || ((type) == ADC_DATA_WIDTH_14_WITH_64_AVERAGE) || ((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) \ + || ((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) /** @defgroup ADC_MICBOOST_DB_TYPE * @{ */ -#define IS_ADC_MICBOOST_DB_TYPE(type) (((type) == ADC_MICBOOST_DB_16DB) || \ - ((type) == ADC_MICBOOST_DB_32DB)) +#define IS_ADC_MICBOOST_DB_TYPE(type) (((type) == ADC_MICBOOST_DB_16DB) || ((type) == ADC_MICBOOST_DB_32DB)) /** @defgroup ADC_PGA2_GAIN_TYPE * @{ */ -#define IS_ADC_PGA2_GAIN_TYPE(type) (((type) == ADC_PGA2_GAIN_0DB) || \ - ((type) == ADC_PGA2_GAIN_6DB) || \ - ((type) == ADC_PGA2_GAIN_N6DB) || \ - ((type) == ADC_PGA2_GAIN_12DB)) +#define IS_ADC_PGA2_GAIN_TYPE(type) (((type) == ADC_PGA2_GAIN_0DB) || ((type) == ADC_PGA2_GAIN_6DB) || ((type) == ADC_PGA2_GAIN_N6DB) || ((type) == ADC_PGA2_GAIN_12DB)) /** @defgroup ADC_MIC_MODE_TYPE * @{ */ -#define IS_ADC_MIC_MODE_TYPE(type) (((type) == ADC_MIC_MODE_SINGLE) || \ - ((type) == ADC_MIC_MODE_DIFF)) +#define IS_ADC_MIC_MODE_TYPE(type) (((type) == ADC_MIC_MODE_SINGLE) || ((type) == ADC_MIC_MODE_DIFF)) /** @defgroup ADC_FIFO_THRESHOLD_TYPE * @{ */ -#define IS_ADC_FIFO_THRESHOLD_TYPE(type) (((type) == ADC_FIFO_THRESHOLD_1) || \ - ((type) == ADC_FIFO_THRESHOLD_4) || \ - ((type) == ADC_FIFO_THRESHOLD_8) || \ - ((type) == ADC_FIFO_THRESHOLD_16)) +#define IS_ADC_FIFO_THRESHOLD_TYPE(type) (((type) == ADC_FIFO_THRESHOLD_1) || ((type) == ADC_FIFO_THRESHOLD_4) || ((type) == ADC_FIFO_THRESHOLD_8) || ((type) == ADC_FIFO_THRESHOLD_16)) /** @defgroup ADC_INT_TYPE * @{ */ -#define IS_ADC_INT_TYPE(type) (((type) == ADC_INT_POS_SATURATION) || \ - ((type) == ADC_INT_NEG_SATURATION) || \ - ((type) == ADC_INT_FIFO_UNDERRUN) || \ - ((type) == ADC_INT_FIFO_OVERRUN) || \ - ((type) == ADC_INT_ADC_READY) || \ - ((type) == ADC_INT_FIFO_READY) || \ - ((type) == ADC_INT_ALL)) +#define IS_ADC_INT_TYPE(type) \ + (((type) == ADC_INT_POS_SATURATION) || ((type) == ADC_INT_NEG_SATURATION) || ((type) == ADC_INT_FIFO_UNDERRUN) || ((type) == ADC_INT_FIFO_OVERRUN) || ((type) == ADC_INT_ADC_READY) \ + || ((type) == ADC_INT_FIFO_READY) || ((type) == ADC_INT_ALL)) /*@} end of group ADC_Public_Constants */ @@ -507,41 +440,41 @@ typedef struct #ifndef BFLB_USE_HAL_DRIVER void GPADC_DMA_IRQHandler(void); #endif -void ADC_Vbat_Enable(void); -void ADC_Vbat_Disable(void); -void ADC_Reset(void); -void ADC_Enable(void); -void ADC_Disable(void); -void ADC_Init(ADC_CFG_Type *cfg); -void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn); -void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn); -void ADC_Start(void); -void ADC_Stop(void); -void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg); -uint8_t ADC_Get_FIFO_Count(void); -BL_Sts_Type ADC_FIFO_Is_Empty(void); -BL_Sts_Type ADC_FIFO_Is_Full(void); -void ADC_FIFO_Clear(void); -uint32_t ADC_Read_FIFO(void); -void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result); -void ADC_IntClr(ADC_INT_Type intType); +void ADC_Vbat_Enable(void); +void ADC_Vbat_Disable(void); +void ADC_Reset(void); +void ADC_Enable(void); +void ADC_Disable(void); +void ADC_Init(ADC_CFG_Type *cfg); +void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn); +void ADC_Scan_Channel_Config(const ADC_Chan_Type posChList[], const ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn); +void ADC_Start(void); +void ADC_Stop(void); +void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg); +uint8_t ADC_Get_FIFO_Count(void); +BL_Sts_Type ADC_FIFO_Is_Empty(void); +BL_Sts_Type ADC_FIFO_Is_Full(void); +void ADC_FIFO_Clear(void); +uint32_t ADC_Read_FIFO(void); +void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result); +void ADC_IntClr(ADC_INT_Type intType); BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType); -BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType); -void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun); -void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask); -void ADC_SET_TSVBE_LOW(void); -void ADC_SET_TSVBE_HIGH(void); -void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod); -void ADC_Tsen_Enable(void); -void ADC_Tsen_Disable(void); -void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal); -BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config); -void ADC_MIC_Bias_Disable(void); -void ADC_MIC_Bias_Enable(void); -BL_Err_Type ADC_Trim_TSEN(uint16_t *tsen_offset); -BL_Err_Type ADC_Gain_Trim(void); -uint32_t ADC_Cal_Reg_Coeff_Value(uint32_t raw_reg); -float TSEN_Get_Temp(uint32_t tsen_offset); +BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType); +void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun); +void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask); +void ADC_SET_TSVBE_LOW(void); +void ADC_SET_TSVBE_HIGH(void); +void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod); +void ADC_Tsen_Enable(void); +void ADC_Tsen_Disable(void); +void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal); +BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config); +void ADC_MIC_Bias_Disable(void); +void ADC_MIC_Bias_Enable(void); +BL_Err_Type ADC_Trim_TSEN(uint16_t *tsen_offset); +BL_Err_Type ADC_Gain_Trim(void); +uint32_t ADC_Cal_Reg_Coeff_Value(uint32_t raw_reg); +float TSEN_Get_Temp(uint32_t tsen_offset); /*@} end of group ADC_Public_Functions */ diff --git a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c index cee5cecc..a54ade3a 100644 --- a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c +++ b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c @@ -1,38 +1,38 @@ /** - ****************************************************************************** - * @file bl702_adc.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file bl702_adc.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ #include "bl702_adc.h" #include "bl702_ef_ctrl.h" @@ -51,16 +51,16 @@ #undef MSG #define MSG(...) #define AON_CLK_SET_DUMMY_WAIT \ - { \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - } + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } #define ADC_RESTART_DUMMY_WAIT BL702_Delay_US(100) /*@} end of group ADC_Private_Macros */ @@ -74,11 +74,11 @@ /** @defgroup ADC_Private_Variables * @{ */ -static intCallback_Type *adcIntCbfArra[ADC_INT_ALL] = { NULL }; -static ADC_Gain_Coeff_Type adcGainCoeffCal = { - .adcGainCoeffEnable = DISABLE, - .adcgainCoeffVal = 0, - .coe = 1, +static intCallback_Type *adcIntCbfArra[ADC_INT_ALL] = {NULL}; +static ADC_Gain_Coeff_Type adcGainCoeffCal = { + .adcGainCoeffEnable = DISABLE, + .adcgainCoeffVal = 0, + .coe = 1, }; /*@} end of group ADC_Private_Variables */ @@ -106,1413 +106,1373 @@ static ADC_Gain_Coeff_Type adcGainCoeffCal = { */ /****************************************************************************/ /** - * @brief Software reset the whole ADC - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Reset(void) -{ - uint32_t regCmd; + * @brief Software reset the whole ADC + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_Reset(void) { + uint32_t regCmd; - /* reset ADC */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_SET_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); - AON_CLK_SET_DUMMY_WAIT; - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_CLR_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); + /* reset ADC */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_SET_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); + AON_CLK_SET_DUMMY_WAIT; + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_CLR_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); } /****************************************************************************/ /** - * @brief ADC glable enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Enable(void) -{ - uint32_t tmpVal; + * @brief ADC glable enable + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_Enable(void) { + uint32_t tmpVal; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); } /****************************************************************************/ /** - * @brief ADC glable disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Disable(void) -{ - uint32_t tmpVal; + * @brief ADC glable disable + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_Disable(void) { + uint32_t tmpVal; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); } /****************************************************************************/ /** - * @brief ADC normal mode init - * - * @param cfg: ADC normal mode configuration - * - * @return None - * -*******************************************************************************/ -void ADC_Init(ADC_CFG_Type *cfg) -{ - uint32_t regCfg1; - uint32_t regCfg2; - uint32_t regCalib; + * @brief ADC normal mode init + * + * @param cfg: ADC normal mode configuration + * + * @return None + * + *******************************************************************************/ +void ADC_Init(ADC_CFG_Type *cfg) { + uint32_t regCfg1; + uint32_t regCfg2; + uint32_t regCalib; - CHECK_PARAM(IS_ADC_V18_SEL_TYPE(cfg->v18Sel)); - CHECK_PARAM(IS_ADC_V11_SEL_TYPE(cfg->v11Sel)); - CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv)); - CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1)); - CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2)); - CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode)); - CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel)); - CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm)); - CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref)); - CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode)); - CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth)); + CHECK_PARAM(IS_ADC_V18_SEL_TYPE(cfg->v18Sel)); + CHECK_PARAM(IS_ADC_V11_SEL_TYPE(cfg->v11Sel)); + CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv)); + CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1)); + CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2)); + CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode)); + CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel)); + CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm)); + CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref)); + CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode)); + CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth)); - /* config 1 */ - regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V18_SEL, cfg->v18Sel); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V11_SEL, cfg->v11Sel); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_DITHER_EN); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_SCAN_LENGTH, 0); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CLK_DIV_RATIO, cfg->clkDiv); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_CLK_ANA_INV); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CAL_OS_EN, cfg->offsetCalibEn); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_RES_SEL, cfg->resWidth); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); - AON_CLK_SET_DUMMY_WAIT; + /* config 1 */ + regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V18_SEL, cfg->v18Sel); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V11_SEL, cfg->v11Sel); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_DITHER_EN); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_SCAN_LENGTH, 0); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CLK_DIV_RATIO, cfg->clkDiv); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_CLK_ANA_INV); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CAL_OS_EN, cfg->offsetCalibEn); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_RES_SEL, cfg->resWidth); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); + AON_CLK_SET_DUMMY_WAIT; - /* config 2 */ - regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x02); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA1_GAIN, cfg->gain1); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA2_GAIN, cfg->gain2); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_BIAS_SEL, cfg->biasSel); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, cfg->chopMode); - /* pga_vcmi_en is for mic */ - regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_VCMI_EN); + /* config 2 */ + regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x02); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA1_GAIN, cfg->gain1); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA2_GAIN, cfg->gain2); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_BIAS_SEL, cfg->biasSel); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, cfg->chopMode); + /* pga_vcmi_en is for mic */ + regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_VCMI_EN); - if ((cfg->gain1 != ADC_PGA_GAIN_NONE) || (cfg->gain2 != ADC_PGA_GAIN_NONE)) { - regCfg2 = BL_SET_REG_BIT(regCfg2, AON_GPADC_PGA_EN); - } else { - regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_EN); - } + if ((cfg->gain1 != ADC_PGA_GAIN_NONE) || (cfg->gain2 != ADC_PGA_GAIN_NONE)) { + regCfg2 = BL_SET_REG_BIT(regCfg2, AON_GPADC_PGA_EN); + } else { + regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_EN); + } - /* pga_os_cal is for mic */ - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_OS_CAL, 8); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_VCM, cfg->vcm); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_VREF_SEL, cfg->vref); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DIFF_MODE, cfg->inputMode); + /* pga_os_cal is for mic */ + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_OS_CAL, 8); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_VCM, cfg->vcm); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_VREF_SEL, cfg->vref); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DIFF_MODE, cfg->inputMode); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2); - /* calibration offset */ - regCalib = BL_RD_REG(AON_BASE, AON_GPADC_REG_DEFINE); - regCalib = BL_SET_REG_BITS_VAL(regCalib, AON_GPADC_OS_CAL_DATA, cfg->offsetCalibVal); - BL_WR_REG(AON_BASE, AON_GPADC_REG_DEFINE, regCalib); + /* calibration offset */ + regCalib = BL_RD_REG(AON_BASE, AON_GPADC_REG_DEFINE); + regCalib = BL_SET_REG_BITS_VAL(regCalib, AON_GPADC_OS_CAL_DATA, cfg->offsetCalibVal); + BL_WR_REG(AON_BASE, AON_GPADC_REG_DEFINE, regCalib); #ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(GPADC_DMA_IRQn, GPADC_DMA_IRQHandler); + Interrupt_Handler_Register(GPADC_DMA_IRQn, GPADC_DMA_IRQHandler); #endif - ADC_Gain_Trim(); + ADC_Gain_Trim(); } /****************************************************************************/ /** - * @brief ADC normal mode channel config - * - * @param posCh: ADC pos channel type - * @param negCh: ADC neg channel type - * @param contEn: ENABLE or DISABLE continuous mode - * - * @return None - * -*******************************************************************************/ -void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn) -{ - uint32_t regCmd; - uint32_t regCfg1; + * @brief ADC normal mode channel config + * + * @param posCh: ADC pos channel type + * @param negCh: ADC neg channel type + * @param contEn: ENABLE or DISABLE continuous mode + * + * @return None + * + *******************************************************************************/ +void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn) { + uint32_t regCmd; + uint32_t regCfg1; - CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh)); - CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh)); + CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh)); + CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh)); - /* set channel */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_POS_SEL, posCh); - regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_NEG_SEL, negCh); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); + /* set channel */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_POS_SEL, posCh); + regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_NEG_SEL, negCh); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - /* set continuous mode */ - regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CONT_CONV_EN, contEn); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); + /* set continuous mode */ + regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CONT_CONV_EN, contEn); + regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); } /****************************************************************************/ /** - * @brief ADC scan mode channel config - * - * @param posChList[]: ADC pos channel list type - * @param negChList[]: ADC neg channel list type - * @param scanLength: ADC scan length - * @param contEn: ENABLE or DISABLE continuous mode - * - * @return None - * -*******************************************************************************/ -void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn) -{ - uint32_t tmpVal, i; - uint32_t dealLen; + * @brief ADC scan mode channel config + * + * @param posChList[]: ADC pos channel list type + * @param negChList[]: ADC neg channel list type + * @param scanLength: ADC scan length + * @param contEn: ENABLE or DISABLE continuous mode + * + * @return None + * + *******************************************************************************/ +void ADC_Scan_Channel_Config(const ADC_Chan_Type posChList[], const ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn) { + uint32_t tmpVal, i; + uint32_t dealLen; - CHECK_PARAM((scanLength < 13)); + CHECK_PARAM((scanLength < 13)); - /* Deal with the first 6 */ - dealLen = 6; + /* Deal with the first 6 */ + dealLen = 6; - if (scanLength < dealLen) { - dealLen = scanLength; + if (scanLength < dealLen) { + dealLen = scanLength; + } + + /* Set first 6 scan channels */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS1); + + for (i = 0; i < dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (posChList[i] << (i * 5)); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS1, tmpVal); + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1); + + for (i = 0; i < dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (negChList[i] << (i * 5)); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1, tmpVal); + + /* Set the left channels */ + if (scanLength > dealLen) { + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS2); + + for (i = 0; i < scanLength - dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (posChList[i + dealLen] << (i * 5)); } - /* Set first 6 scan channels */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS1); + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS2, tmpVal); - for (i = 0; i < dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (posChList[i] << (i * 5)); + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2); + + for (i = 0; i < scanLength - dealLen; i++) { + tmpVal = tmpVal & (~(0x1F << (i * 5))); + tmpVal |= (negChList[i + dealLen] << (i * 5)); } - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS1, tmpVal); + BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2, tmpVal); + } - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1); - - for (i = 0; i < dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (negChList[i] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1, tmpVal); - - /* Set the left channels */ - if (scanLength > dealLen) { - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS2); - - for (i = 0; i < scanLength - dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (posChList[i + dealLen] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS2, tmpVal); - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2); - - for (i = 0; i < scanLength - dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (negChList[i + dealLen] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2, tmpVal); - } - - /* Scan mode */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SCAN_LENGTH, scanLength - 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_CONT_CONV_EN, contEn); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_CLK_ANA_INV); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_SCAN_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); + /* Scan mode */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SCAN_LENGTH, scanLength - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_CONT_CONV_EN, contEn); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_CLK_ANA_INV); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_SCAN_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); } /****************************************************************************/ /** - * @brief ADC normal mode convert start - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Start(void) -{ - uint32_t regCmd; + * @brief ADC normal mode convert start + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_Start(void) { + uint32_t regCmd; - /* disable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); + /* disable convert start */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - ADC_RESTART_DUMMY_WAIT; + ADC_RESTART_DUMMY_WAIT; - /* enable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); + /* enable convert start */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); } /****************************************************************************/ /** - * @brief ADC normal mode convert stop - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Stop(void) -{ - uint32_t regCmd; + * @brief ADC normal mode convert stop + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_Stop(void) { + uint32_t regCmd; - /* disable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); + /* disable convert start */ + regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); } /****************************************************************************/ /** - * @brief ADC FIFO configuration - * - * @param fifoCfg: ADC FIFO confifuration pointer - * - * @return None - * -*******************************************************************************/ -void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg) -{ - uint32_t tmpVal; + * @brief ADC FIFO configuration + * + * @param fifoCfg: ADC FIFO confifuration pointer + * + * @return None + * + *******************************************************************************/ +void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg) { + uint32_t tmpVal; - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_FIFO_THRESHOLD_TYPE(fifoCfg->fifoThreshold)); + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_FIFO_THRESHOLD_TYPE(fifoCfg->fifoThreshold)); - /* - * DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur - * DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt - */ + /* + * DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur + * DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt + */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_THL, fifoCfg->fifoThreshold); + + /* Enable DMA */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_DMA_EN, fifoCfg->dmaEn); + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC get DMA FIFO data count + * + * @param None + * + * @return data count in FIFO + * + *******************************************************************************/ +uint8_t ADC_Get_FIFO_Count(void) { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + return BL_GET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_DATA_COUNT); +} + +/****************************************************************************/ /** + * @brief ADC get DMA FIFO full status + * + * @param None + * + * @return SET or RESET + * + *******************************************************************************/ +BL_Sts_Type ADC_FIFO_Is_Full(void) { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_FULL)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief ADC get DMA FIFO empty status + * + * @param None + * + * @return SET or RESET + * + *******************************************************************************/ +BL_Sts_Type ADC_FIFO_Is_Empty(void) { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + + if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_NE)) { + return RESET; + } else { + return SET; + } +} + +/****************************************************************************/ /** + * @brief ADC read DMA FIFO data + * + * @param None + * + * @return ADC result if return 0 that means this is error data,user should ignore this data. + * + *******************************************************************************/ +uint32_t ADC_Read_FIFO(void) { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_DMA_RDATA); + + return (tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC parse result + * + * @param orgVal: Original A to D value + * @param len: Original AD vaule count + * @param result: Final Result array pointer + * + * @return None + * + *******************************************************************************/ +void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result) { + uint8_t neg = 0; + uint32_t tmpVal1 = 0, tmpVal2 = 0; + ADC_Data_Width_Type dataType; + ADC_SIG_INPUT_Type sigType; + float ref = 2.0; + uint32_t i = 0; + + float coe = 1.0; + + if (adcGainCoeffCal.adcGainCoeffEnable) { + coe = adcGainCoeffCal.coe; + } + + tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + dataType = BL_GET_REG_BITS_VAL(tmpVal1, AON_GPADC_RES_SEL); + sigType = BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_DIFF_MODE); + + if (BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_VREF_SEL) == ADC_VREF_3P2V) { + ref = 3.2; + } + + if (sigType == ADC_INPUT_SINGLE_END) { + for (i = 0; i < len; i++) { + result[i].posChan = orgVal[i] >> 21; + result[i].negChan = -1; + + if (dataType == ADC_DATA_WIDTH_12) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); + result[i].volt = result[i].value / 4096.0 * ref; + } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); + result[i].volt = result[i].value / 16384.0 * ref; + } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) { + result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); + result[i].volt = result[i].value / 65536.0 * ref; + } + } + } else { + for (i = 0; i < len; i++) { + neg = 0; + result[i].posChan = orgVal[i] >> 21; + result[i].negChan = (orgVal[i] >> 16) & 0x1F; + + if (orgVal[i] & 0x8000) { + orgVal[i] = ~orgVal[i]; + orgVal[i] += 1; + neg = 1; + } + + if (dataType == ADC_DATA_WIDTH_12) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); + result[i].volt = result[i].value / 2048.0 * ref; + } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) { + result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); + result[i].volt = result[i].value / 8192.0 * ref; + } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) { + result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); + result[i].volt = result[i].value / 32768.0 * ref; + } + + if (neg) { + result[i].volt = -result[i].volt; + } + } + } +} + +/****************************************************************************/ /** + * @brief ADC mask or unmask certain or all interrupt + * + * @param intType: interrupt type + * @param intMask: mask or unmask + * + * @return None + * + *******************************************************************************/ +BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType) { + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR_MASK); + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR_MASK); + break; + + case ADC_INT_FIFO_UNDERRUN: + tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); + return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + break; + + case ADC_INT_FIFO_OVERRUN: + tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); + return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + break; + + case ADC_INT_ADC_READY: + tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); + return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY_MASK); + break; + + case ADC_INT_FIFO_READY: + tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); + return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY_MASK); + break; + default: + break; + } + return 0; +} + +/****************************************************************************/ /** + * @brief ADC mask or unmask certain or all interrupt + * + * @param intType: interrupt type + * @param intMask: mask or unmask + * + * @return None + * + *******************************************************************************/ +void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask) { + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); + + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + } + + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + break; + + case ADC_INT_FIFO_UNDERRUN: tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_THL, fifoCfg->fifoThreshold); - /* Enable DMA */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_DMA_EN, fifoCfg->dmaEn); + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + } BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + break; - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + case ADC_INT_FIFO_OVERRUN: tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + } + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC get DMA FIFO data count - * - * @param None - * - * @return data count in FIFO - * -*******************************************************************************/ -uint8_t ADC_Get_FIFO_Count(void) -{ - uint32_t tmpVal; + break; + case ADC_INT_ADC_READY: tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - return BL_GET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_DATA_COUNT); -} + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + } else { + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + } -/****************************************************************************/ /** - * @brief ADC get DMA FIFO full status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type ADC_FIFO_Is_Full(void) -{ - uint32_t tmpVal; + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + break; + case ADC_INT_FIFO_READY: tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_FULL)) { - return SET; + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY_MASK); } else { - return RESET; + /* Disable this interrupt */ + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY_MASK); } + + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + break; + + case ADC_INT_ALL: + if (intMask == UNMASK) { + /* Enable this interrupt */ + tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + } else { + /* Disable this interrupt */ + tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + } + + break; + + default: + break; + } } /****************************************************************************/ /** - * @brief ADC get DMA FIFO empty status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type ADC_FIFO_Is_Empty(void) -{ - uint32_t tmpVal; + * @brief ADC clear certain or all interrupt + * + * @param intType: interrupt type + * + * @return None + * + *******************************************************************************/ +void ADC_IntClr(ADC_INT_Type intType) { + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); + + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + break; + + case ADC_INT_FIFO_UNDERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_FIFO_OVERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_ADC_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_FIFO_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + case ADC_INT_ALL: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); + BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_NE)) { - return RESET; - } else { - return SET; - } + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + /*Manual reset*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + break; + + default: + break; + } } /****************************************************************************/ /** - * @brief ADC read DMA FIFO data - * - * @param None - * - * @return ADC result if return 0 that means this is error data,user should ignore this data. - * -*******************************************************************************/ -uint32_t ADC_Read_FIFO(void) -{ - uint32_t tmpVal; + * @brief ADC get interrupt status + * + * @param intType: interrupt type + * + * @return SET or RESET + * + *******************************************************************************/ +BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType) { + uint32_t tmpVal; + BL_Sts_Type bitStatus = RESET; - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_DMA_RDATA); + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - return (tmpVal); + switch (intType) { + case ADC_INT_POS_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR)) ? SET : RESET; + break; + + case ADC_INT_NEG_SATURATION: + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR)) ? SET : RESET; + break; + + case ADC_INT_FIFO_UNDERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN)) ? SET : RESET; + break; + + case ADC_INT_FIFO_OVERRUN: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN)) ? SET : RESET; + break; + + case ADC_INT_ADC_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY)) ? SET : RESET; + break; + + case ADC_INT_FIFO_READY: + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY)) ? SET : RESET; + break; + + case ADC_INT_ALL: + break; + + default: + break; + } + + return bitStatus; } /****************************************************************************/ /** - * @brief ADC parse result - * - * @param orgVal: Original A to D value - * @param len: Original AD vaule count - * @param result: Final Result array pointer - * - * @return None - * -*******************************************************************************/ -void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result) -{ - uint8_t neg = 0; - uint32_t tmpVal1 = 0, tmpVal2 = 0; - ADC_Data_Width_Type dataType; - ADC_SIG_INPUT_Type sigType; - float ref = 2.0; - uint32_t i = 0; + * @brief ADC install interrupt callback + * + * @param intType: ADC interrupt type + * @param cbFun: ADC interrupt callback + * + * @return None + * + *******************************************************************************/ +void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun) { + /* Check the parameters */ + CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - float coe = 1.0; - - if (adcGainCoeffCal.adcGainCoeffEnable) { - coe = adcGainCoeffCal.coe; - } - - tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - dataType = BL_GET_REG_BITS_VAL(tmpVal1, AON_GPADC_RES_SEL); - sigType = BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_DIFF_MODE); - - if (BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_VREF_SEL) == ADC_VREF_3P2V) { - ref = 3.2; - } - - if (sigType == ADC_INPUT_SINGLE_END) { - for (i = 0; i < len; i++) { - result[i].posChan = orgVal[i] >> 21; - result[i].negChan = -1; - - if (dataType == ADC_DATA_WIDTH_12) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); - result[i].volt = result[i].value / 4096.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || - (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); - result[i].volt = result[i].value / 16384.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || - (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) { - result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); - result[i].volt = result[i].value / 65536.0 * ref; - } - } - } else { - for (i = 0; i < len; i++) { - neg = 0; - result[i].posChan = orgVal[i] >> 21; - result[i].negChan = (orgVal[i] >> 16) & 0x1F; - - if (orgVal[i] & 0x8000) { - orgVal[i] = ~orgVal[i]; - orgVal[i] += 1; - neg = 1; - } - - if (dataType == ADC_DATA_WIDTH_12) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); - result[i].volt = result[i].value / 2048.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || - (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); - result[i].volt = result[i].value / 8192.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || - (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) { - result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); - result[i].volt = result[i].value / 32768.0 * ref; - } - - if (neg) { - result[i].volt = -result[i].volt; - } - } - } + adcIntCbfArra[intType] = cbFun; } /****************************************************************************/ /** - * @brief ADC mask or unmask certain or all interrupt - * - * @param intType: interrupt type - * @param intMask: mask or unmask - * - * @return None - * -*******************************************************************************/ -BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR_MASK); - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR_MASK); - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); - return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); - return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); - return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY_MASK); - break; - - case ADC_INT_FIFO_READY: - tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG); - return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY_MASK); - break; - default: - break; - } - return 0; -} - -/****************************************************************************/ /** - * @brief ADC mask or unmask certain or all interrupt - * - * @param intType: interrupt type - * @param intMask: mask or unmask - * - * @return None - * -*******************************************************************************/ -void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - } - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - } - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - } - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - break; - - case ADC_INT_FIFO_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY_MASK); - } - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - break; - - case ADC_INT_ALL: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - } else { - /* Disable this interrupt */ - tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief ADC clear certain or all interrupt - * - * @param intType: interrupt type - * - * @return None - * -*******************************************************************************/ -void ADC_IntClr(ADC_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - case ADC_INT_FIFO_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - case ADC_INT_ALL: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief ADC get interrupt status - * - * @param intType: interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType) -{ - uint32_t tmpVal; - BL_Sts_Type bitStatus = RESET; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR)) ? SET : RESET; - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR)) ? SET : RESET; - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN)) ? SET : RESET; - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN)) ? SET : RESET; - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY)) ? SET : RESET; - break; - - case ADC_INT_FIFO_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY)) ? SET : RESET; - break; - - case ADC_INT_ALL: - break; - - default: - break; - } - - return bitStatus; -} - -/****************************************************************************/ /** - * @brief ADC install interrupt callback - * - * @param intType: ADC interrupt type - * @param cbFun: ADC interrupt callback - * - * @return None - * -*******************************************************************************/ -void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - - adcIntCbfArra[intType] = cbFun; -} - -/****************************************************************************/ /** - * @brief ADC DMA interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ + * @brief ADC DMA interrupt handler + * + * @param None + * + * @return None + * + *******************************************************************************/ #ifndef BFLB_USE_HAL_DRIVER -void GPADC_DMA_IRQHandler(void) -{ - if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET) { - ADC_IntClr(ADC_INT_POS_SATURATION); +void GPADC_DMA_IRQHandler(void) { + if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET) { + ADC_IntClr(ADC_INT_POS_SATURATION); - if (adcIntCbfArra[ADC_INT_POS_SATURATION] != NULL) { - adcIntCbfArra[ADC_INT_POS_SATURATION](); - } + if (adcIntCbfArra[ADC_INT_POS_SATURATION] != NULL) { + adcIntCbfArra[ADC_INT_POS_SATURATION](); } + } - if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET) { - ADC_IntClr(ADC_INT_NEG_SATURATION); + if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET) { + ADC_IntClr(ADC_INT_NEG_SATURATION); - if (adcIntCbfArra[ADC_INT_NEG_SATURATION] != NULL) { - adcIntCbfArra[ADC_INT_NEG_SATURATION](); - } + if (adcIntCbfArra[ADC_INT_NEG_SATURATION] != NULL) { + adcIntCbfArra[ADC_INT_NEG_SATURATION](); } + } - if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET) { - ADC_IntClr(ADC_INT_FIFO_UNDERRUN); + if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET) { + ADC_IntClr(ADC_INT_FIFO_UNDERRUN); - if (adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL) { - adcIntCbfArra[ADC_INT_FIFO_UNDERRUN](); - } + if (adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL) { + adcIntCbfArra[ADC_INT_FIFO_UNDERRUN](); } + } - if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET) { - ADC_IntClr(ADC_INT_FIFO_OVERRUN); + if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET) { + ADC_IntClr(ADC_INT_FIFO_OVERRUN); - if (adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL) { - adcIntCbfArra[ADC_INT_FIFO_OVERRUN](); - } + if (adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL) { + adcIntCbfArra[ADC_INT_FIFO_OVERRUN](); } + } - if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) { - ADC_IntClr(ADC_INT_FIFO_READY); + if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) { + ADC_IntClr(ADC_INT_FIFO_READY); - if (adcIntCbfArra[ADC_INT_FIFO_READY] != NULL) { - adcIntCbfArra[ADC_INT_FIFO_READY](); - } + if (adcIntCbfArra[ADC_INT_FIFO_READY] != NULL) { + adcIntCbfArra[ADC_INT_FIFO_READY](); } + } - if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) { - ADC_IntClr(ADC_INT_FIFO_READY); + if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) { + ADC_IntClr(ADC_INT_FIFO_READY); - if (adcIntCbfArra[ADC_INT_FIFO_READY] != NULL) { - adcIntCbfArra[ADC_INT_FIFO_READY](); - } + if (adcIntCbfArra[ADC_INT_FIFO_READY] != NULL) { + adcIntCbfArra[ADC_INT_FIFO_READY](); } + } } #endif /****************************************************************************/ /** - * @brief ADC VBAT enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Vbat_Enable(void) -{ - uint32_t tmpVal; + * @brief ADC VBAT enable + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_Vbat_Enable(void) { + uint32_t tmpVal; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); } /****************************************************************************/ /** - * @brief ADC VBAT disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Vbat_Disable(void) -{ - uint32_t tmpVal; + * @brief ADC VBAT disable + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_Vbat_Disable(void) { + uint32_t tmpVal; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); } /****************************************************************************/ /** - * @brief ADC TSEN Config - * - * @param tsenMod: None - * - * @return None - * -*******************************************************************************/ -void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod) -{ - uint32_t tmpVal; + * @brief ADC TSEN Config + * + * @param tsenMod: None + * + * @return None + * + *******************************************************************************/ +void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod) { + uint32_t tmpVal; - CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type)); + CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type)); - /* config gpadc_reg_cmd */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - /* enable sensor dc test mux*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_SEN_TEST_EN); - /*selected sen output current channel*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SEN_SEL, 0); - /* enable chip sensor*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CHIP_SEN_PU); - /*dwa_en */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DWA_EN, 1); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); + /* config gpadc_reg_cmd */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + /* enable sensor dc test mux*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_SEN_TEST_EN); + /*selected sen output current channel*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SEN_SEL, 0); + /* enable chip sensor*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CHIP_SEN_PU); + /*dwa_en */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DWA_EN, 1); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - /* config 2 */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - /*tsvbe low=0*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); - /*dly_sel=2*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DLY_SEL, 2); - /*test_sel=0*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TEST_SEL, 0); - /*test_en=0*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TEST_EN); - /*ts_en*/ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); - /*select tsen ext or inner*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TSEXT_SEL, tsenMod); + /* config 2 */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + /*tsvbe low=0*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); + /*dly_sel=2*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DLY_SEL, 2); + /*test_sel=0*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TEST_SEL, 0); + /*test_en=0*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TEST_EN); + /*ts_en*/ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); + /*select tsen ext or inner*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TSEXT_SEL, tsenMod); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_VCM, 2); - /*pga vcmi enable*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_VCM, 2); + /*pga vcmi enable*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); + /*0:512uS;1:16mS;2:32mS;3:64mS*/ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, 0); + + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); + + /* config 3 */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + /* set gpadc_dither_en */ + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_DITHER_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); + + /* set 4000F90C[19](gpadc_mic2_diff) = 1 + * debug advise form Ran + * 2020.08.26 + */ + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC TSEN Enable + * + * @return None + * + *******************************************************************************/ +void ADC_Tsen_Enable(void) { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC TSEN Disable + * + * @return None + * + *******************************************************************************/ +void ADC_Tsen_Disable(void) { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TS_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} + +/****************************************************************************/ /** + * @brief ADC Clear fifo + * + * @return None + * + *******************************************************************************/ +void ADC_FIFO_Clear(void) { + uint32_t tmpVal; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); +} + +/****************************************************************************/ /** + * @brief config pga + * + * @param pga_vcmi_enable: enable or not vcmi + * @param pga_os_cal: pga os cal value + * @return None + * + *******************************************************************************/ +void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal) { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + + if (pga_vcmi_enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); + } else { tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); - /*0:512uS;1:16mS;2:32mS;3:64mS*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, 0); + } - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, pga_os_cal); - /* config 3 */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - /* set gpadc_dither_en */ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_DITHER_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} +/****************************************************************************/ /** + * @brief TSEN_Get_V_Error + * + * @param None + * + * @return None + * + *******************************************************************************/ +uint32_t TSEN_Get_V_Error(void) { + uint32_t v0 = 0, v1 = 0; + uint32_t v_error = 0; + uint32_t regVal = 0; + ADC_Result_Type result; + uint32_t tmpVal; + uint8_t gainCalEnabled = 0; - /* set 4000F90C[19](gpadc_mic2_diff) = 1 - * debug advise form Ran - * 2020.08.26 - */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_LOW(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v0 = result.value; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_HIGH(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v1 = result.value; + + v_error = v0 - v1; + + return v_error; } /****************************************************************************/ /** - * @brief ADC TSEN Enable - * - * @return None - * -*******************************************************************************/ -void ADC_Tsen_Enable(void) -{ - uint32_t tmpVal; + * @brief Trim TSEN + * + * @param tsen_offset: None + * + * @return SUCCESS or ERROR + * + *******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t *tsen_offset) { + Efuse_TSEN_Refcode_Corner_Type trim; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} + EF_Ctrl_Read_TSEN_Trim(&trim); + if (trim.tsenRefcodeCornerEn) { + if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) { + *tsen_offset = trim.tsenRefcodeCorner; -/****************************************************************************/ /** - * @brief ADC TSEN Disable - * - * @return None - * -*******************************************************************************/ -void ADC_Tsen_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC Clear fifo - * - * @return None - * -*******************************************************************************/ -void ADC_FIFO_Clear(void) -{ - uint32_t tmpVal; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief config pga - * - * @param pga_vcmi_enable: enable or not vcmi - * @param pga_os_cal: pga os cal value - * @return None - * -*******************************************************************************/ -void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - - if (pga_vcmi_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); + return SUCCESS; } + } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, pga_os_cal); - - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} -/****************************************************************************/ /** - * @brief TSEN_Get_V_Error - * - * @param None - * - * @return None - * -*******************************************************************************/ -uint32_t TSEN_Get_V_Error(void) -{ - uint32_t v0 = 0, v1 = 0; - uint32_t v_error = 0; - uint32_t regVal = 0; - ADC_Result_Type result; - uint32_t tmpVal; - uint8_t gainCalEnabled = 0; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_LOW(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v0 = result.value; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_HIGH(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v1 = result.value; - - v_error = v0 - v1; - - return v_error; + return ERROR; } /****************************************************************************/ /** - * @brief Trim TSEN - * - * @param tsen_offset: None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t *tsen_offset) -{ - Efuse_TSEN_Refcode_Corner_Type trim; + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_SET_TSVBE_LOW(void) { + uint32_t tmpVal; + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} - EF_Ctrl_Read_TSEN_Trim(&trim); - if (trim.tsenRefcodeCornerEn) { - if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) { - *tsen_offset = trim.tsenRefcodeCorner; +/****************************************************************************/ /** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_SET_TSVBE_HIGH(void) { + uint32_t tmpVal; + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); +} - return SUCCESS; - } - } +/****************************************************************************/ /** + * @brief SET ADC TSEN TSVBE LOW/HIGH + * + * @param tsen_offset: tsen_offset form efuse trim data + * + * @return tempture + * + *******************************************************************************/ +float TSEN_Get_Temp(uint32_t tsen_offset) { + uint32_t v0 = 0, v1 = 0; + float temp = 0; + uint32_t regVal = 0; + ADC_Result_Type result; + uint32_t tmpVal; + uint8_t gainCalEnabled = 0; + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_LOW(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v0 = result.value; + + /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); + BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + + ADC_SET_TSVBE_HIGH(); + + ADC_Start(); + + while (ADC_Get_FIFO_Count() == 0) + ; + + regVal = ADC_Read_FIFO(); + gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; + adcGainCoeffCal.adcGainCoeffEnable = 0; + ADC_Parse_Result(®Val, 1, &result); + adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; + v1 = result.value; + + if (v0 > v1) { + temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753; + } else { + temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753; + } + + return temp; +} + +/****************************************************************************/ /** + * @brief ADC MIC Config + * + * @param adc_mic_config: adc_mic_config + * + * @return success or not + * + *******************************************************************************/ +BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config) { + uint32_t tmpVal1 = 0, tmpVal2 = 0; + + CHECK_PARAM(IS_ADC_MICBOOST_DB_Type(adc_mic_config->micboostDb)); + CHECK_PARAM(IS_PGA2_GAIN_Type(adc_mic_config->micPga2Gain)); + CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic1Mode)); + CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic2Mode)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->dwaEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micboostBypassEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micPgaEn)); + CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micBiasEn)); + + tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); + + tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBOOST_32DB_EN, adc_mic_config->micboostDb); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC_PGA2_GAIN, adc_mic_config->micPga2Gain); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC1_DIFF, adc_mic_config->mic1Mode); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC2_DIFF, adc_mic_config->mic2Mode); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_DWA_EN, adc_mic_config->dwaEn); + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_BYP_MICBOOST, adc_mic_config->micboostBypassEn); + + if (BL_IS_REG_BIT_SET(tmpVal2, AON_GPADC_PGA_EN) && adc_mic_config->micPgaEn == ENABLE) { + /* 0x4000F914[13] and 0x4000F90c[15] Cannot be both Enable*/ return ERROR; + } else { + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICPGA_EN, adc_mic_config->micPgaEn); + } + + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBIAS_EN, adc_mic_config->micBiasEn); + + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal1); + + return SUCCESS; } /****************************************************************************/ /** - * @brief SET ADC TSEN TSVBE LOW/HIGH - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_SET_TSVBE_LOW(void) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); + * @brief ADC MIC bias control + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_MIC_Bias_Enable(void) { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); } /****************************************************************************/ /** - * @brief SET ADC TSEN TSVBE LOW/HIGH - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_SET_TSVBE_HIGH(void) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); + * @brief ADC MIC bias control + * + * @param None + * + * @return None + * + *******************************************************************************/ +void ADC_MIC_Bias_Disable(void) { + uint32_t tmpVal; + + tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); + BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); } /****************************************************************************/ /** - * @brief SET ADC TSEN TSVBE LOW/HIGH - * - * @param tsen_offset: tsen_offset form efuse trim data - * - * @return tempture - * -*******************************************************************************/ -float TSEN_Get_Temp(uint32_t tsen_offset) -{ - uint32_t v0 = 0, v1 = 0; - float temp = 0; - uint32_t regVal = 0; - ADC_Result_Type result; - uint32_t tmpVal; - uint8_t gainCalEnabled = 0; + * @brief Trim ADC Gain + * + * @param None + * + * @return SUCCESS or ERROR + * + *******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void) { + Efuse_ADC_Gain_Coeff_Type trim; + uint32_t tmp; - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); + EF_Ctrl_Read_ADC_Gain_Trim(&trim); - ADC_SET_TSVBE_LOW(); + if (trim.adcGainCoeffEn) { + if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) { + adcGainCoeffCal.adcGainCoeffEnable = ENABLE; + adcGainCoeffCal.adcgainCoeffVal = trim.adcGainCoeff; + tmp = adcGainCoeffCal.adcgainCoeffVal; - ADC_Start(); + if (tmp & 0x800) { + tmp = ~tmp; + tmp += 1; + tmp = tmp & 0xfff; + // printf("val==%08x\r\n",(unsigned int)tmp); + adcGainCoeffCal.coe = (1.0 + ((float)tmp / 2048.0)); + // printf("coe==%0f\r\n",adcGainCoeffCal.coe); + } else { + adcGainCoeffCal.coe = (1.0 - ((float)tmp / 2048.0)); + // printf("coe==%0f\r\n",adcGainCoeffCal.coe); + } - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v0 = result.value; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_HIGH(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v1 = result.value; - - if (v0 > v1) { - temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753; - } else { - temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753; + return SUCCESS; } + } - return temp; -} - -/****************************************************************************/ /** - * @brief ADC MIC Config - * - * @param adc_mic_config: adc_mic_config - * - * @return success or not - * -*******************************************************************************/ -BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config) -{ - uint32_t tmpVal1 = 0, tmpVal2 = 0; - - CHECK_PARAM(IS_ADC_MICBOOST_DB_Type(adc_mic_config->micboostDb)); - CHECK_PARAM(IS_PGA2_GAIN_Type(adc_mic_config->micPga2Gain)); - CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic1Mode)); - CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic2Mode)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->dwaEn)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micboostBypassEn)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micPgaEn)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micBiasEn)); - - tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - - tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBOOST_32DB_EN, adc_mic_config->micboostDb); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC_PGA2_GAIN, adc_mic_config->micPga2Gain); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC1_DIFF, adc_mic_config->mic1Mode); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC2_DIFF, adc_mic_config->mic2Mode); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_DWA_EN, adc_mic_config->dwaEn); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_BYP_MICBOOST, adc_mic_config->micboostBypassEn); - - if (BL_IS_REG_BIT_SET(tmpVal2, AON_GPADC_PGA_EN) && adc_mic_config->micPgaEn == ENABLE) { - /* 0x4000F914[13] and 0x4000F90c[15] Cannot be both Enable*/ - return ERROR; - } else { - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICPGA_EN, adc_mic_config->micPgaEn); - } - - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBIAS_EN, adc_mic_config->micBiasEn); - - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief ADC MIC bias control - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_MIC_Bias_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC MIC bias control - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_MIC_Bias_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief Trim ADC Gain - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void) -{ - Efuse_ADC_Gain_Coeff_Type trim; - uint32_t tmp; - - EF_Ctrl_Read_ADC_Gain_Trim(&trim); - - if (trim.adcGainCoeffEn) { - if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) { - adcGainCoeffCal.adcGainCoeffEnable = ENABLE; - adcGainCoeffCal.adcgainCoeffVal = trim.adcGainCoeff; - tmp = adcGainCoeffCal.adcgainCoeffVal; - - if (tmp & 0x800) { - tmp = ~tmp; - tmp += 1; - tmp = tmp & 0xfff; - //printf("val==%08x\r\n",(unsigned int)tmp); - adcGainCoeffCal.coe = (1.0 + ((float)tmp / 2048.0)); - //printf("coe==%0f\r\n",adcGainCoeffCal.coe); - } else { - adcGainCoeffCal.coe = (1.0 - ((float)tmp / 2048.0)); - //printf("coe==%0f\r\n",adcGainCoeffCal.coe); - } - - return SUCCESS; - } - } - - return ERROR; + return ERROR; } /*@} end of group ADC_Public_Functions */