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347968e4ef
Settings menu works Movement working & TMP calibrated Tip reading sensibily Accuracy seems ok Trimmed down overshoot by biasing integral Saving to flash working, detailed idle Sleep mode Description scrolls Building for DFU working Motion detection update Use manual alg instead, using highpass filter, then sum current change vs rolling average Re-shuffle the pwm code organisation
508 lines
16 KiB
C
508 lines
16 KiB
C
/**
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******************************************************************************
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* @file stm32f1xx_ll_rcc.c
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief RCC LL module driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_ll_rcc.h"
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#ifdef USE_FULL_ASSERT
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#include "stm32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif /* USE_FULL_ASSERT */
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/** @addtogroup STM32F1xx_LL_Driver
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* @{
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*/
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#if defined(RCC)
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/** @defgroup RCC_LL RCC
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup RCC_LL_Private_Macros
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* @{
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*/
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#if defined(RCC_PLLI2S_SUPPORT)
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#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
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|| ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
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#endif /* RCC_PLLI2S_SUPPORT */
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#if defined(USB) || defined(USB_OTG_FS)
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#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
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#endif /* USB */
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#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup RCC_LL_Private_Functions RCC Private functions
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* @{
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*/
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uint32_t RCC_GetSystemClockFreq(void);
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uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
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uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
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uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
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uint32_t RCC_PLL_GetFreqDomain_SYS(void);
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#if defined(RCC_PLLI2S_SUPPORT)
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uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
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#endif /* RCC_PLLI2S_SUPPORT */
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#if defined(RCC_PLL2_SUPPORT)
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uint32_t RCC_PLL2_GetFreqClockFreq(void);
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#endif /* RCC_PLL2_SUPPORT */
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup RCC_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup RCC_LL_EF_Init
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* @{
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*/
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/**
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* @brief Reset the RCC clock configuration to the default reset state.
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* @note The default reset state of the clock configuration is given below:
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* - HSI ON and used as system clock source
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* - HSE PLL, PLL2, PLL3 OFF
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* - AHB, APB1 and APB2 prescaler set to 1.
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* - CSS, MCO OFF
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* - All interrupts disabled
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* @note This function doesn't modify the configuration of the
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* - Peripheral clocks
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* - LSI, LSE and RTC clocks
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: RCC registers are de-initialized
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* - ERROR: not applicable
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*/
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ErrorStatus LL_RCC_DeInit(void)
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{
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uint32_t vl_mask = 0U;
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/* Set HSION bit */
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LL_RCC_HSI_Enable();
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/* Reset SW, HPRE, PPRE, MCOSEL, PLLXTPRE, PLLSRC and ADCPRE bits */
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vl_mask = 0xFFFFFFFFU;
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CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL |\
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RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_ADCPRE));
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#if defined(USB)
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/* Reset USBPRE bit */
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CLEAR_BIT(vl_mask, RCC_CFGR_USBPRE);
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#elif defined(USB_OTG_FS)
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/* Reset OTGFSPRE bit */
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CLEAR_BIT(vl_mask, RCC_CFGR_OTGFSPRE);
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#endif /* USB */
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#if defined(RCC_CFGR_PLLMULL2)
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/* Set PLL multiplication factor to 2 */
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vl_mask |= RCC_CFGR_PLLMULL2;
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#else
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/* Set PLL multiplication factor to 4 */
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vl_mask |= RCC_CFGR_PLLMULL4;
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#endif /* RCC_CFGR_PLLMULL2 */
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LL_RCC_WriteReg(CFGR, vl_mask);
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/* Reset HSEON, HSEBYP, CSSON, PLLON bits */
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vl_mask = 0xFFFFFFFFU;
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CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
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#if defined(RCC_CR_PLL2ON)
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/* Reset PLL2ON bit */
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CLEAR_BIT(vl_mask, RCC_CR_PLL2ON);
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#endif /* RCC_CR_PLL2ON */
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#if defined(RCC_CR_PLL3ON)
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/* Reset PLL3ON bit */
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CLEAR_BIT(vl_mask, RCC_CR_PLL3ON);
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#endif /* RCC_CR_PLL3ON */
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LL_RCC_WriteReg(CR, vl_mask);
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/* Set HSITRIM bits to the reset value */
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LL_RCC_HSI_SetCalibTrimming(0x10U);
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#if defined(RCC_CFGR2_PREDIV1)
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/* Reset CFGR2 register */
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vl_mask = 0x00000000U;
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#if defined(RCC_PLL2_SUPPORT)
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/* Set PLL2 multiplication factor to 8 */
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vl_mask |= RCC_CFGR2_PLL2MUL8;
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#endif /* RCC_PLL2_SUPPORT */
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#if defined(RCC_PLLI2S_SUPPORT)
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/* Set PLL3 multiplication factor to 8 */
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vl_mask |= RCC_CFGR2_PLL3MUL8;
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#endif /* RCC_PLLI2S_SUPPORT */
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LL_RCC_WriteReg(CFGR2, vl_mask);
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#endif /* RCC_CFGR2_PREDIV1 */
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/* Disable all interrupts */
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LL_RCC_WriteReg(CIR, 0x00000000U);
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return SUCCESS;
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}
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/**
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* @}
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*/
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/** @addtogroup RCC_LL_EF_Get_Freq
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* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
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* and different peripheral clocks available on the device.
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* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
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* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
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* @note If SYSCLK source is PLL, function returns values based on
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* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
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* @note (**) HSI_VALUE is a defined constant but the real value may vary
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* depending on the variations in voltage and temperature.
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* @note (***) HSE_VALUE is a defined constant, user has to ensure that
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* HSE_VALUE is same as the real frequency of the crystal used.
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* Otherwise, this function may have wrong result.
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* @note The result of this function could be incorrect when using fractional
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* value for HSE crystal.
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* @note This function can be used by the user application to compute the
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* baud-rate for the communication peripherals or configure other parameters.
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* @{
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*/
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/**
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* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
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* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
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* must be called to update structure fields. Otherwise, any
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* configuration based on this function will be incorrect.
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* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
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* @retval None
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*/
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void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
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{
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/* Get SYSCLK frequency */
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RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
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/* HCLK clock frequency */
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RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
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/* PCLK1 clock frequency */
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RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
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/* PCLK2 clock frequency */
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RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
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}
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#if defined(RCC_CFGR2_I2S2SRC)
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/**
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* @brief Return I2Sx clock frequency
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* @param I2SxSource This parameter can be one of the following values:
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* @arg @ref LL_RCC_I2S2_CLKSOURCE
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* @arg @ref LL_RCC_I2S3_CLKSOURCE
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* @retval I2S clock frequency (in Hz)
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*/
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uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
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{
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uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
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/* Check parameter */
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assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
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/* I2S1CLK clock frequency */
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switch (LL_RCC_GetI2SClockSource(I2SxSource))
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{
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case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
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case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
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i2s_frequency = RCC_GetSystemClockFreq();
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break;
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case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
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case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
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default:
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i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
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break;
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}
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return i2s_frequency;
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}
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#endif /* RCC_CFGR2_I2S2SRC */
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#if defined(USB) || defined(USB_OTG_FS)
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/**
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* @brief Return USBx clock frequency
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* @param USBxSource This parameter can be one of the following values:
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* @arg @ref LL_RCC_USB_CLKSOURCE
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* @retval USB clock frequency (in Hz)
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* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
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*/
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uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
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{
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uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
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/* Check parameter */
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assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
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/* USBCLK clock frequency */
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switch (LL_RCC_GetUSBClockSource(USBxSource))
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{
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#if defined(RCC_CFGR_USBPRE)
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case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
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if (LL_RCC_PLL_IsReady())
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{
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usb_frequency = RCC_PLL_GetFreqDomain_SYS();
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}
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break;
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case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
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default:
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if (LL_RCC_PLL_IsReady())
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{
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usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
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}
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break;
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#endif /* RCC_CFGR_USBPRE */
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#if defined(RCC_CFGR_OTGFSPRE)
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/* USBCLK = PLLVCO/2
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= (2 x PLLCLK) / 2
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= PLLCLK */
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case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
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if (LL_RCC_PLL_IsReady())
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{
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usb_frequency = RCC_PLL_GetFreqDomain_SYS();
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}
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break;
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/* USBCLK = PLLVCO/3
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= (2 x PLLCLK) / 3 */
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case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
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default:
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if (LL_RCC_PLL_IsReady())
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{
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usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
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}
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break;
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#endif /* RCC_CFGR_OTGFSPRE */
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}
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return usb_frequency;
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}
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#endif /* USB */
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/**
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* @brief Return ADCx clock frequency
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* @param ADCxSource This parameter can be one of the following values:
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* @arg @ref LL_RCC_ADC_CLKSOURCE
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* @retval ADC clock frequency (in Hz)
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*/
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uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
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{
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uint32_t adc_prescaler = 0U;
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uint32_t adc_frequency = 0U;
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/* Check parameter */
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assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
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/* Get ADC prescaler */
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adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
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/* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
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adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
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/ (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
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return adc_frequency;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @addtogroup RCC_LL_Private_Functions
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* @{
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*/
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/**
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* @brief Return SYSTEM clock frequency
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* @retval SYSTEM clock frequency (in Hz)
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*/
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uint32_t RCC_GetSystemClockFreq(void)
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{
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uint32_t frequency = 0U;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (LL_RCC_GetSysClkSource())
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{
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case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
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frequency = HSI_VALUE;
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break;
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case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
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frequency = HSE_VALUE;
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break;
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case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
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frequency = RCC_PLL_GetFreqDomain_SYS();
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break;
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default:
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frequency = HSI_VALUE;
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break;
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}
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return frequency;
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}
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/**
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* @brief Return HCLK clock frequency
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* @param SYSCLK_Frequency SYSCLK clock frequency
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* @retval HCLK clock frequency (in Hz)
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*/
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uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
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{
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/* HCLK clock frequency */
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return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
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}
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/**
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* @brief Return PCLK1 clock frequency
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* @param HCLK_Frequency HCLK clock frequency
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* @retval PCLK1 clock frequency (in Hz)
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*/
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uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
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{
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/* PCLK1 clock frequency */
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return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
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}
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/**
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* @brief Return PCLK2 clock frequency
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* @param HCLK_Frequency HCLK clock frequency
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* @retval PCLK2 clock frequency (in Hz)
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*/
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uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
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{
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/* PCLK2 clock frequency */
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return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
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}
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/**
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* @brief Return PLL clock frequency used for system domain
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* @retval PLL clock frequency (in Hz)
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*/
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uint32_t RCC_PLL_GetFreqDomain_SYS(void)
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{
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uint32_t pllinputfreq = 0U, pllsource = 0U;
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/* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
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/* Get PLL source */
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pllsource = LL_RCC_PLL_GetMainSource();
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switch (pllsource)
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{
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case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
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pllinputfreq = HSI_VALUE / 2U;
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break;
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case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
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pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
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break;
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#if defined(RCC_PLL2_SUPPORT)
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case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
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pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
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break;
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#endif /* RCC_PLL2_SUPPORT */
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default:
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pllinputfreq = HSI_VALUE / 2U;
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break;
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}
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return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
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}
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#if defined(RCC_PLL2_SUPPORT)
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/**
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* @brief Return PLL clock frequency used for system domain
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* @retval PLL clock frequency (in Hz)
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*/
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uint32_t RCC_PLL2_GetFreqClockFreq(void)
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{
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return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
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}
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#endif /* RCC_PLL2_SUPPORT */
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#if defined(RCC_PLLI2S_SUPPORT)
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/**
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* @brief Return PLL clock frequency used for system domain
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* @retval PLL clock frequency (in Hz)
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*/
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uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
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{
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return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
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}
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#endif /* RCC_PLLI2S_SUPPORT */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* defined(RCC) */
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/**
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* @}
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*/
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#endif /* USE_FULL_LL_DRIVER */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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