mirror of
https://github.com/Ralim/IronOS.git
synced 2025-02-26 07:53:55 +00:00
Drop git module
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@@ -24,32 +24,26 @@
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#ifndef _CLOCK_CONFIG_H
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#define _CLOCK_CONFIG_H
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#define XTAL_TYPE EXTERNAL_XTAL_40M
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#define XTAL_32K_TYPE INTERNAL_RC_32K
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#define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M
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#define XTAL_TYPE EXTERNAL_XTAL_32M
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#define XTAL_32K_TYPE INTERNAL_RC_32K
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#define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M
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#define ROOT_CLOCK_SOURCE_AUPLL 8 // Used to shut up compiler as its undefined for bl60x
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#define BSP_FCLK_DIV 0
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#define BSP_BCLK_DIV 1
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#define BSP_FCLK_DIV 0
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#define BSP_BCLK_DIV 1
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#define BSP_USING_UART0
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#define BSP_USING_I2C0
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#define BSP_USING_ADC0
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#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
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#define BSP_UART_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M
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#define BSP_UART_CLOCK_DIV 0
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#endif
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#if defined(BSP_USING_I2C0)
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#define BSP_I2C_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK
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#define BSP_I2C_CLOCK_DIV 0
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#endif
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#if defined(BSP_USING_SPI0)
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#define BSP_SPI_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK
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#define BSP_SPI_CLOCK_DIV 0
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#endif
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#if defined(BSP_USING_ADC0)
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#define BSP_ADC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
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#define BSP_ADC_CLOCK_DIV 0
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#endif
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#if defined(BSP_USING_DAC0)
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#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL
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#define BSP_DAC_CLOCK_DIV 1
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#endif
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#define BSP_I2C_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK
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#define BSP_I2C_CLOCK_DIV 0
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#define BSP_SPI_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK
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#define BSP_SPI_CLOCK_DIV 0
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#define BSP_ADC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
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#define BSP_ADC_CLOCK_DIV 0
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#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL
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#define BSP_DAC_CLOCK_DIV 1
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#endif
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