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Cleanup make includes and formatting rules (#1860)

Browse Source 
* Draft cleanup of the folder definition mess

* Move old startup

* Fixup! broken hacky includes

* Update Makefile

* Update Makefile

* Update Makefile

* Bulk format

* Who knew, header guards are a wise idea

* Squash some sizing warnings

* Drop broken usb stack

* Fix BLE headers to be sensible

* Cleaning up proper c styling

* We have newer clang, it does bracketing now

* Run clang-format brackets

* We can drop the old messy bracket-checker with newer clang format

* WiP formatter

* Align grids of scripts by right side

Massively easier to read in nearly all cases

* Excempt the table for compression from formatter
This commit is contained in:
Ben V. Brown
2023-12-27 09:23:12 +11:00
committed by GitHub
parent 849d1f7d40
commit ec5f07ec0c
248 changed files with 58306 additions and 70269 deletions
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4
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_dev.c vendored
View File

@@ -46,8 +46,8 @@ static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = {(uint16_t)TX0_FIFO_FS_
#elif defined(USB_HS_CORE)
uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT]
= {(uint16_t)TX0_FIFO_HS_SIZE, (uint16_t)TX1_FIFO_HS_SIZE, (uint16_t)TX2_FIFO_HS_SIZE, (uint16_t)TX3_FIFO_HS_SIZE, (uint16_t)TX4_FIFO_HS_SIZE, (uint16_t)TX5_FIFO_HS_SIZE};
uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = {(uint16_t)TX0_FIFO_HS_SIZE, (uint16_t)TX1_FIFO_HS_SIZE, (uint16_t)TX2_FIFO_HS_SIZE,
(uint16_t)TX3_FIFO_HS_SIZE, (uint16_t)TX4_FIFO_HS_SIZE, (uint16_t)TX5_FIFO_HS_SIZE};
#endif /* USBFS_CORE */

9
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbd_int.c vendored
View File

@@ -32,7 +32,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
OF SUCH DAMAGE.
*/
#include "gd32vf103_libopt.h"
//#include "usbd_conf.h"
// #include "usbd_conf.h"
#include "drv_usbd_int.h"
#include "usbd_transc.h"
@@ -45,8 +45,8 @@ static uint32_t usbd_int_suspend(usb_core_driver *udev);
static uint32_t usbd_emptytxfifo_write(usb_core_driver *udev, uint32_t ep_num);
static const uint8_t USB_SPEED[4]
= {[DSTAT_EM_HS_PHY_30MHZ_60MHZ] = USB_SPEED_HIGH, [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = USB_SPEED_FULL, [DSTAT_EM_FS_PHY_48MHZ] = USB_SPEED_FULL, [DSTAT_EM_LS_PHY_6MHZ] = USB_SPEED_LOW};
static const uint8_t USB_SPEED[4] = {
[DSTAT_EM_HS_PHY_30MHZ_60MHZ] = USB_SPEED_HIGH, [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = USB_SPEED_FULL, [DSTAT_EM_FS_PHY_48MHZ] = USB_SPEED_FULL, [DSTAT_EM_LS_PHY_6MHZ] = USB_SPEED_LOW};
__IO uint8_t setupc_flag = 0U;
@@ -230,7 +230,8 @@ void usbd_isr(usb_core_driver *udev) {
/* OTG mode interrupt */
if (intr & GINTF_OTGIF) {
if (udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) {}
if (udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) {
}
/* Clear OTG interrupt */
udev->regs.gr->GINTF = GINTF_OTGIF;

4
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_enum.c vendored
View File

@@ -70,8 +70,8 @@ static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = {
};
/* get standard descriptor handler */
static uint8_t *(*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len)
= {[USB_DESCTYPE_DEV - 1] = _usb_dev_desc_get, [USB_DESCTYPE_CONFIG - 1] = _usb_config_desc_get, [USB_DESCTYPE_STR - 1] = _usb_str_desc_get};
static uint8_t *(*std_desc_get[])(usb_core_driver *udev, uint8_t index,
uint16_t *len) = {[USB_DESCTYPE_DEV - 1] = _usb_dev_desc_get, [USB_DESCTYPE_CONFIG - 1] = _usb_config_desc_get, [USB_DESCTYPE_STR - 1] = _usb_str_desc_get};
/*!
\brief handle USB standard device request

88
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_enum.c vendored
View File

@@ -72,8 +72,8 @@ usbh_status usbh_devdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint8_t
usbh_control *usb_ctl = &puhost->control;
if (CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req
= (usb_req){.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_GET_DESCRIPTOR, .wValue = USBH_DESC(USB_DESCTYPE_DEV), .wIndex = 0U, .wLength = len};
usb_ctl->setup.req =
(usb_req){.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_GET_DESCRIPTOR, .wValue = USBH_DESC(USB_DESCTYPE_DEV), .wIndex = 0U, .wLength = len};
usbh_ctlstate_config(puhost, pudev->host.rx_buf, len);
}
@@ -102,8 +102,8 @@ usbh_status usbh_cfgdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint16_t
usbh_control *usb_ctl = &puhost->control;
if (CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req
= (usb_req){.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_GET_DESCRIPTOR, .wValue = USBH_DESC(USB_DESCTYPE_CONFIG), .wIndex = 0U, .wLength = len};
usb_ctl->setup.req =
(usb_req){.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_GET_DESCRIPTOR, .wValue = USBH_DESC(USB_DESCTYPE_CONFIG), .wIndex = 0U, .wLength = len};
usbh_ctlstate_config(puhost, pudev->host.rx_buf, len);
}
@@ -266,13 +266,15 @@ usbh_status usbh_clrfeature(usb_core_driver *pudev, usbh_host *puhost, uint8_t e
\retval operation status
*/
static void usbh_devdesc_parse(usb_desc_dev *dev_desc, uint8_t *buf, uint16_t len) {
*dev_desc = (usb_desc_dev){.header = {.bLength = *(uint8_t *)(buf + 0U), .bDescriptorType = *(uint8_t *)(buf + 1U)},
*dev_desc = (usb_desc_dev){
.header = {.bLength = *(uint8_t *)(buf + 0U), .bDescriptorType = *(uint8_t *)(buf + 1U)},
.bcdUSB = BYTE_SWAP(buf + 2U),
.bDeviceClass = *(uint8_t *)(buf + 4U),
.bDeviceSubClass = *(uint8_t *)(buf + 5U),
.bDeviceProtocol = *(uint8_t *)(buf + 6U),
.bMaxPacketSize0 = *(uint8_t *)(buf + 7U)};
.bcdUSB = BYTE_SWAP(buf + 2U),
.bDeviceClass = *(uint8_t *)(buf + 4U),
.bDeviceSubClass = *(uint8_t *)(buf + 5U),
.bDeviceProtocol = *(uint8_t *)(buf + 6U),
.bMaxPacketSize0 = *(uint8_t *)(buf + 7U)
};
if (len > 8U) {
/* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */
@@ -295,19 +297,20 @@ static void usbh_devdesc_parse(usb_desc_dev *dev_desc, uint8_t *buf, uint16_t le
*/
static void usbh_cfgdesc_parse(usb_desc_config *cfg_desc, uint8_t *buf) {
/* parse configuration descriptor */
*cfg_desc = (usb_desc_config) {
.header = {
.bLength = *(uint8_t *)(buf + 0U),
.bDescriptorType = *(uint8_t *)(buf + 1U),
},
*cfg_desc = (usb_desc_config){
.header =
{
.bLength = *(uint8_t *)(buf + 0U),
.bDescriptorType = *(uint8_t *)(buf + 1U),
},
.wTotalLength = BYTE_SWAP(buf + 2U),
.bNumInterfaces = *(uint8_t *)(buf + 4U),
.bConfigurationValue = *(uint8_t *)(buf + 5U),
.iConfiguration = *(uint8_t *)(buf + 6U),
.bmAttributes = *(uint8_t *)(buf + 7U),
.bMaxPower = *(uint8_t *)(buf + 8U)
};
.wTotalLength = BYTE_SWAP(buf + 2U),
.bNumInterfaces = *(uint8_t *)(buf + 4U),
.bConfigurationValue = *(uint8_t *)(buf + 5U),
.iConfiguration = *(uint8_t *)(buf + 6U),
.bmAttributes = *(uint8_t *)(buf + 7U),
.bMaxPower = *(uint8_t *)(buf + 8U)
};
}
/*!
@@ -318,7 +321,7 @@ static void usbh_cfgdesc_parse(usb_desc_config *cfg_desc, uint8_t *buf) {
\retval operation status
*/
static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf) {
usb_desc_ep * ep = NULL;
usb_desc_ep *ep = NULL;
usb_desc_itf *itf = NULL, itf_value;
usb_desc_header *pdesc = (usb_desc_header *)buf;
@@ -388,20 +391,21 @@ static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf) {
\retval operation status
*/
static void usbh_itfdesc_parse(usb_desc_itf *itf_desc, uint8_t *buf) {
*itf_desc = (usb_desc_itf) {
.header = {
.bLength = *(uint8_t *)(buf + 0U),
.bDescriptorType = *(uint8_t *)(buf + 1U),
},
*itf_desc = (usb_desc_itf){
.header =
{
.bLength = *(uint8_t *)(buf + 0U),
.bDescriptorType = *(uint8_t *)(buf + 1U),
},
.bInterfaceNumber = *(uint8_t *)(buf + 2U),
.bAlternateSetting = *(uint8_t *)(buf + 3U),
.bNumEndpoints = *(uint8_t *)(buf + 4U),
.bInterfaceClass = *(uint8_t *)(buf + 5U),
.bInterfaceSubClass = *(uint8_t *)(buf + 6U),
.bInterfaceProtocol = *(uint8_t *)(buf + 7U),
.iInterface = *(uint8_t *)(buf + 8U)
};
.bInterfaceNumber = *(uint8_t *)(buf + 2U),
.bAlternateSetting = *(uint8_t *)(buf + 3U),
.bNumEndpoints = *(uint8_t *)(buf + 4U),
.bInterfaceClass = *(uint8_t *)(buf + 5U),
.bInterfaceSubClass = *(uint8_t *)(buf + 6U),
.bInterfaceProtocol = *(uint8_t *)(buf + 7U),
.iInterface = *(uint8_t *)(buf + 8U)
};
}
/*!
@@ -412,12 +416,14 @@ static void usbh_itfdesc_parse(usb_desc_itf *itf_desc, uint8_t *buf) {
\retval operation status
*/
static void usbh_epdesc_parse(usb_desc_ep *ep_desc, uint8_t *buf) {
*ep_desc = (usb_desc_ep){.header = {.bLength = *(uint8_t *)(buf + 0U), .bDescriptorType = *(uint8_t *)(buf + 1U)},
*ep_desc = (usb_desc_ep){
.header = {.bLength = *(uint8_t *)(buf + 0U), .bDescriptorType = *(uint8_t *)(buf + 1U)},
.bEndpointAddress = *(uint8_t *)(buf + 2U),
.bmAttributes = *(uint8_t *)(buf + 3U),
.wMaxPacketSize = BYTE_SWAP(buf + 4U),
.bInterval = *(uint8_t *)(buf + 6U)};
.bEndpointAddress = *(uint8_t *)(buf + 2U),
.bmAttributes = *(uint8_t *)(buf + 3U),
.wMaxPacketSize = BYTE_SWAP(buf + 4U),
.bInterval = *(uint8_t *)(buf + 6U)
};
}
/*!

6
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_adc.c vendored
View File

@@ -199,11 +199,13 @@ void adc_calibration_enable(uint32_t adc_periph) {
/* reset the selected ADC1 calibration registers */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_RSTCLB;
/* check the RSTCLB bit state */
while ((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) {}
while ((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) {
}
/* enable ADC calibration process */
ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
/* check the CLB bit state */
while ((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) {}
while ((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) {
}
}
/*!

5
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dma.c vendored
View File

@@ -37,8 +37,9 @@ OF SUCH DAMAGE.
#include "gd32vf103_dma.h"
#include "gd32vf103_rcu.h"
#define DMA_WRONG_HANDLE \
while (1) {}
#define DMA_WRONG_HANDLE \
while (1) { \
}
/* check whether peripheral matches channels or not */
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx);

14
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exmc.c vendored
View File

@@ -114,14 +114,14 @@ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct)
/* clear relative bits */
snctl &= ((uint32_t) ~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX));
snctl |= (uint32_t)((uint32_t)exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | exmc_norsram_init_struct->memory_type | exmc_norsram_init_struct->databus_width
| exmc_norsram_init_struct->nwait_polarity | ((uint32_t)exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET)
| ((uint32_t)exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | ((uint32_t)exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET);
snctl |= (uint32_t)((uint32_t)exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | exmc_norsram_init_struct->memory_type | exmc_norsram_init_struct->databus_width |
exmc_norsram_init_struct->nwait_polarity | ((uint32_t)exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
((uint32_t)exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | ((uint32_t)exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET);
sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U) & EXMC_SNTCFG_ASET)
| (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET) & EXMC_SNTCFG_AHLD)
| (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNTCFG_DSET)
| (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U) << SNTCFG_BUSLAT_OFFSET) & EXMC_SNTCFG_BUSLAT);
sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U) & EXMC_SNTCFG_ASET) |
(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET) & EXMC_SNTCFG_AHLD) |
(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNTCFG_DSET) |
(((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U) << SNTCFG_BUSLAT_OFFSET) & EXMC_SNTCFG_BUSLAT);
/* nor flash access enable */
if (EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) {

3
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fmc.c vendored
View File

@@ -188,7 +188,8 @@ void ob_unlock(void) {
}
/* wait until OBWEN bit is set by hardware */
while (RESET == (FMC_CTL & FMC_CTL_OBWEN)) {}
while (RESET == (FMC_CTL & FMC_CTL_OBWEN)) {
}
}
/*!

4
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rcu.c vendored
View File

@@ -54,8 +54,8 @@ void rcu_deinit(void) {
RCU_CTL &= ~RCU_CTL_HXTALBPS;
RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN);
/* reset CFG0 register */
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL
| RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4);
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | RCU_CFG0_USBFSPSC |
RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4);
/* reset INT and CFG1 register */
RCU_INT = 0x00ff0000U;
RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL);

6
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rtc.c vendored
View File

@@ -97,7 +97,8 @@ void rtc_prescaler_set(uint32_t psc) {
*/
void rtc_lwoff_wait(void) {
/* loop until LWOFF flag is set */
while (RESET == (RTC_CTL & RTC_CTL_LWOFF)) {}
while (RESET == (RTC_CTL & RTC_CTL_LWOFF)) {
}
}
/*!
@@ -110,7 +111,8 @@ void rtc_register_sync_wait(void) {
/* clear RSYNF flag */
RTC_CTL &= ~RTC_CTL_RSYNF;
/* loop until RSYNF flag is set */
while (RESET == (RTC_CTL & RTC_CTL_RSYNF)) {}
while (RESET == (RTC_CTL & RTC_CTL_RSYNF)) {
}
}
/*!

4
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_timer.c vendored
View File

@@ -482,8 +482,8 @@ void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) {
\retval none
*/
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) {
TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | ((uint32_t)(breakpara->ideloffstate)) | ((uint32_t)(breakpara->deadtime)) | ((uint32_t)(breakpara->breakpolarity))
| ((uint32_t)(breakpara->outputautostate)) | ((uint32_t)(breakpara->protectmode)) | ((uint32_t)(breakpara->breakstate)));
TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | ((uint32_t)(breakpara->ideloffstate)) | ((uint32_t)(breakpara->deadtime)) | ((uint32_t)(breakpara->breakpolarity)) |
((uint32_t)(breakpara->outputautostate)) | ((uint32_t)(breakpara->protectmode)) | ((uint32_t)(breakpara->breakstate)));
}
/*!

7
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/n200_func.c vendored
View File

@@ -44,8 +44,9 @@ uint64_t get_timer_value(void) {
while (1) {
uint32_t hi = mtime_hi();
uint32_t lo = mtime_lo();
if (hi == mtime_hi())
if (hi == mtime_hi()) {
return ((uint64_t)hi << 32) | lo;
}
}
}
@@ -278,8 +279,8 @@ void eclic_mode_enable() {
write_csr(CSR_MTVEC, mtvec_value);
#elif defined(__GNUC__)
uint32_t mtvec_value = read_csr(mtvec);
mtvec_value = mtvec_value & 0xFFFFFFC0;
mtvec_value = mtvec_value | 0x00000003;
mtvec_value = mtvec_value & 0xFFFFFFC0;
mtvec_value = mtvec_value | 0x00000003;
write_csr(mtvec, mtvec_value);
#endif
}

25
source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/system_gd32vf103.c vendored
View File

@@ -110,7 +110,8 @@ static void system_clock_108m_hxtal(void) {
/* if fail */
if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while (1) {}
while (1) {
}
}
/* HXTAL is stable */
@@ -133,12 +134,14 @@ static void system_clock_108m_hxtal(void) {
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {}
while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {
}
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL2EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {}
while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {
}
} else if (HXTAL_VALUE == 8000000) {
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20);
@@ -146,25 +149,29 @@ static void system_clock_108m_hxtal(void) {
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {}
while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {
}
/* enable PLL2 */
RCU_CTL |= RCU_CTL_PLL2EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {}
while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {
}
}
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {}
while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {}
while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
}
}
/*!
@@ -343,8 +350,8 @@ static void system_default_exception_handler(unsigned long mcause, unsigned long
printf("MCAUSE: 0x%lx\r\n", mcause);
printf("MEPC : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC));
printf("MTVAL : 0x%lx\r\n", __RV_CSR_READ(CSR_MBADADDR));
while (1)
;
while (1) {
}
}
/**