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This commit is contained in:
Ben V. Brown
2021-05-03 22:10:14 +10:00
parent e3deb33d7f
commit dd5daf51e3
24 changed files with 14097 additions and 15594 deletions
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60
source/Core/BSP/MHP30/BSP.cpp
View File

@@ -18,9 +18,7 @@ uint16_t totalPWM = 255;
const uint16_t powerPWM = 255;
history<uint16_t, PID_TIM_HZ> rawTempFilter = {{0}, 0, 0};
void resetWatchdog() {
HAL_IWDG_Refresh(&hiwdg);
}
void resetWatchdog() { HAL_IWDG_Refresh(&hiwdg); }
#ifdef TEMP_NTC
// Lookup table for the NTC
@@ -188,8 +186,7 @@ static const uint16_t NTCHandleLookup[] = {
29104, 20, //
29272, 10, //
};
const int NTCHandleLookupItems = sizeof(NTCHandleLookup)
/ (2 * sizeof(uint16_t));
const int NTCHandleLookupItems = sizeof(NTCHandleLookup) / (2 * sizeof(uint16_t));
#endif
// These are called by the HAL after the corresponding events from the system
@@ -204,13 +201,10 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
}
uint16_t getHandleTemperature() {
int32_t result = getADC(0);
return Utils::InterpolateLookupTable(NTCHandleLookup, NTCHandleLookupItems,
result);
return Utils::InterpolateLookupTable(NTCHandleLookup, NTCHandleLookupItems, result);
}
uint16_t getTipInstantTemperature() {
return getADC(2);
}
uint16_t getTipInstantTemperature() { return getADC(2); }
uint16_t getTipRawTemp(uint8_t refresh) {
if (refresh) {
@@ -328,26 +322,14 @@ void unstick_I2C() {
HAL_I2C_Init(&hi2c1);
}
uint8_t getButtonA() {
return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ?
1 : 0;
}
uint8_t getButtonB() {
return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ?
1 : 0;
}
uint8_t getButtonA() { return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ? 1 : 0; }
uint8_t getButtonB() { return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ? 1 : 0; }
void BSPInit(void) {
WS2812::init();
}
void BSPInit(void) { WS2812::init(); }
void reboot() {
NVIC_SystemReset();
}
void reboot() { NVIC_SystemReset(); }
void delay_ms(uint16_t count) {
HAL_Delay(count);
}
void delay_ms(uint16_t count) { HAL_Delay(count); }
void setPlatePullup(bool pullingUp) {
GPIO_InitTypeDef GPIO_InitStruct;
@@ -356,13 +338,11 @@ void setPlatePullup(bool pullingUp) {
GPIO_InitStruct.Pull = GPIO_NOPULL;
if (pullingUp) {
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
HAL_GPIO_WritePin(PLATE_SENSOR_PULLUP_GPIO_Port,
PLATE_SENSOR_PULLUP_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(PLATE_SENSOR_PULLUP_GPIO_Port, PLATE_SENSOR_PULLUP_Pin, GPIO_PIN_SET);
} else {
// Hi-z
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
HAL_GPIO_WritePin(PLATE_SENSOR_PULLUP_GPIO_Port,
PLATE_SENSOR_PULLUP_Pin, GPIO_PIN_RESET);
HAL_GPIO_WritePin(PLATE_SENSOR_PULLUP_GPIO_Port, PLATE_SENSOR_PULLUP_Pin, GPIO_PIN_RESET);
}
HAL_GPIO_Init(PLATE_SENSOR_PULLUP_GPIO_Port, &GPIO_InitStruct);
}
@@ -381,8 +361,7 @@ bool isTipDisconnected() {
bool tipDisconnected = getADC(2) > (4090 * 8);
// We have to handle here that this ^ will trip while measuring the gain resistor
if (xTaskGetTickCount() - lastMeas
< (TICKS_100MS * 2 + (TICKS_100MS / 2))) {
if (xTaskGetTickCount() - lastMeas < (TICKS_100MS * 2 + (TICKS_100MS / 2))) {
tipDisconnected = false;
}
@@ -410,19 +389,15 @@ bool isTipDisconnected() {
} else {
// We have taken reading one
uint16_t adcReadingPD1Cleared = getADC(3);
uint32_t a = ((int) adcReadingPD1Set
- (int) adcReadingPD1Cleared);
uint32_t a = ((int)adcReadingPD1Set - (int)adcReadingPD1Cleared);
a *= 10000;
uint32_t b = ((int) adcReadingPD1Cleared
+ (32768 - (int) adcReadingPD1Set));
uint32_t b = ((int)adcReadingPD1Cleared + (32768 - (int)adcReadingPD1Set));
if (b) {
tipSenseResistancex10Ohms = a / b;
} else {
tipSenseResistancex10Ohms = adcReadingPD1Set =
lastMeas = 0;
tipSenseResistancex10Ohms = adcReadingPD1Set = lastMeas = 0;
}
if (tipSenseResistancex10Ohms > 1100
|| tipSenseResistancex10Ohms < 900) {
if (tipSenseResistancex10Ohms > 1100 || tipSenseResistancex10Ohms < 900) {
tipSenseResistancex10Ohms = 0; // out of range
adcReadingPD1Set = 0;
lastMeas = 0;
@@ -450,8 +425,7 @@ void setStatusLED(const enum StatusLED state) {
case LED_HEATING: {
WS2812::led_set_color(0, ((HAL_GetTick() / 10) % 192) + 64, 0,
0); // Red fade
}
break;
} break;
case LED_HOT:
WS2812::led_set_color(0, 0xFF, 0, 0); // red
break;

362
source/Core/BSP/MHP30/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h vendored
View File

@@ -25,7 +25,6 @@
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
@@ -66,8 +65,7 @@
*/
/*!< Interrupt Number Definition */
typedef enum
{
typedef enum {
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
@@ -141,8 +139,7 @@ typedef enum
* @brief Analog to Digital Converter
*/
typedef struct
{
typedef struct {
__IO uint32_t SR;
__IO uint32_t CR1;
__IO uint32_t CR2;
@@ -165,8 +162,7 @@ typedef struct
__IO uint32_t DR;
} ADC_TypeDef;
typedef struct
{
typedef struct {
__IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
__IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
@@ -178,8 +174,7 @@ typedef struct
* @brief Backup Registers
*/
typedef struct
{
typedef struct {
uint32_t RESERVED0;
__IO uint32_t DR1;
__IO uint32_t DR2;
@@ -200,8 +195,7 @@ typedef struct
* @brief Controller Area Network TxMailBox
*/
typedef struct
{
typedef struct {
__IO uint32_t TIR;
__IO uint32_t TDTR;
__IO uint32_t TDLR;
@@ -212,8 +206,7 @@ typedef struct
* @brief Controller Area Network FIFOMailBox
*/
typedef struct
{
typedef struct {
__IO uint32_t RIR;
__IO uint32_t RDTR;
__IO uint32_t RDLR;
@@ -224,8 +217,7 @@ typedef struct
* @brief Controller Area Network FilterRegister
*/
typedef struct
{
typedef struct {
__IO uint32_t FR1;
__IO uint32_t FR2;
} CAN_FilterRegister_TypeDef;
@@ -234,8 +226,7 @@ typedef struct
* @brief Controller Area Network
*/
typedef struct
{
typedef struct {
__IO uint32_t MCR;
__IO uint32_t MSR;
__IO uint32_t TSR;
@@ -264,8 +255,7 @@ typedef struct
* @brief CRC calculation unit
*/
typedef struct
{
typedef struct {
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
@@ -273,13 +263,11 @@ typedef struct
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
} CRC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
typedef struct {
__IO uint32_t IDCODE;
__IO uint32_t CR;
} DBGMCU_TypeDef;
@@ -288,28 +276,23 @@ typedef struct
* @brief DMA Controller
*/
typedef struct
{
typedef struct {
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
} DMA_Channel_TypeDef;
typedef struct
{
typedef struct {
__IO uint32_t ISR;
__IO uint32_t IFCR;
} DMA_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
typedef struct {
__IO uint32_t IMR;
__IO uint32_t EMR;
__IO uint32_t RTSR;
@@ -322,8 +305,7 @@ typedef struct
* @brief FLASH Registers
*/
typedef struct
{
typedef struct {
__IO uint32_t ACR;
__IO uint32_t KEYR;
__IO uint32_t OPTKEYR;
@@ -339,8 +321,7 @@ typedef struct
* @brief Option Bytes Registers
*/
typedef struct
{
typedef struct {
__IO uint16_t RDP;
__IO uint16_t USER;
__IO uint16_t Data0;
@@ -355,8 +336,7 @@ typedef struct
* @brief General Purpose I/O
*/
typedef struct
{
typedef struct {
__IO uint32_t CRL;
__IO uint32_t CRH;
__IO uint32_t IDR;
@@ -370,8 +350,7 @@ typedef struct
* @brief Alternate Function I/O
*/
typedef struct
{
typedef struct {
__IO uint32_t EVCR;
__IO uint32_t MAPR;
__IO uint32_t EXTICR[4];
@@ -382,8 +361,7 @@ typedef struct
* @brief Inter Integrated Circuit Interface
*/
typedef struct
{
typedef struct {
__IO uint32_t CR1;
__IO uint32_t CR2;
__IO uint32_t OAR1;
@@ -399,8 +377,7 @@ typedef struct
* @brief Independent WATCHDOG
*/
typedef struct
{
typedef struct {
__IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
@@ -411,8 +388,7 @@ typedef struct
* @brief Power Control
*/
typedef struct
{
typedef struct {
__IO uint32_t CR;
__IO uint32_t CSR;
} PWR_TypeDef;
@@ -421,8 +397,7 @@ typedef struct
* @brief Reset and Clock Control
*/
typedef struct
{
typedef struct {
__IO uint32_t CR;
__IO uint32_t CFGR;
__IO uint32_t CIR;
@@ -434,15 +409,13 @@ typedef struct
__IO uint32_t BDCR;
__IO uint32_t CSR;
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
typedef struct
{
typedef struct {
__IO uint32_t CRH;
__IO uint32_t CRL;
__IO uint32_t PRLH;
@@ -459,8 +432,7 @@ typedef struct
* @brief Serial Peripheral Interface
*/
typedef struct
{
typedef struct {
__IO uint32_t CR1;
__IO uint32_t CR2;
__IO uint32_t SR;
@@ -474,8 +446,7 @@ typedef struct
/**
* @brief TIM Timers
*/
typedef struct
{
typedef struct {
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
@@ -499,13 +470,11 @@ typedef struct
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
typedef struct {
__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
@@ -519,8 +488,7 @@ typedef struct
* @brief Universal Serial Bus Full Speed Device
*/
typedef struct
{
typedef struct {
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
@@ -549,13 +517,11 @@ typedef struct
__IO uint16_t RESERVEDC; /*!< Reserved */
} USB_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
typedef struct {
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
@@ -569,7 +535,6 @@ typedef struct
* @{
*/
#define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */
#define FLASH_BANK1_END 0x0801FFFFUL /*!< FLASH END address of bank1 */
#define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */
@@ -578,7 +543,6 @@ typedef struct
#define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
@@ -611,7 +575,6 @@ typedef struct
#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
@@ -628,15 +591,12 @@ typedef struct
#define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */
#define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */
#define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */
/* USB device FS */
#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
/**
* @}
*/
@@ -687,7 +647,6 @@ typedef struct
#define OB ((OB_TypeDef *)OB_BASE)
#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
* @}
*/
@@ -779,7 +738,6 @@ typedef struct
#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
/******************* Bit definition for PWR_CSR register ********************/
#define PWR_CSR_WUF_Pos (0U)
#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
@@ -929,7 +887,6 @@ typedef struct
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
/******************* Bit definition for RCC_CFGR register *******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
@@ -1157,7 +1114,6 @@ typedef struct
#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
/***************** Bit definition for RCC_APB2RSTR register *****************/
#define RCC_APB2RSTR_AFIORST_Pos (0U)
#define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
@@ -1192,14 +1148,10 @@ typedef struct
#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_IOPERST_Pos (6U)
#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
/***************** Bit definition for RCC_APB1RSTR register *****************/
#define RCC_APB1RSTR_TIM2RST_Pos (0U)
#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
@@ -1245,11 +1197,6 @@ typedef struct
#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
/****************** Bit definition for RCC_AHBENR register ******************/
#define RCC_AHBENR_DMA1EN_Pos (0U)
#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
@@ -1264,9 +1211,6 @@ typedef struct
#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
/****************** Bit definition for RCC_APB2ENR register *****************/
#define RCC_APB2ENR_AFIOEN_Pos (0U)
#define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
@@ -1301,14 +1245,10 @@ typedef struct
#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
#define RCC_APB2ENR_IOPEEN_Pos (6U)
#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
/***************** Bit definition for RCC_APB1ENR register ******************/
#define RCC_APB1ENR_TIM2EN_Pos (0U)
#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
@@ -1354,11 +1294,6 @@ typedef struct
#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
/******************* Bit definition for RCC_BDCR register *******************/
#define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
@@ -1418,8 +1353,6 @@ typedef struct
#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
/******************************************************************************/
/* */
/* General Purpose and Alternate Function I/O */
@@ -2142,7 +2075,6 @@ typedef struct
#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
/***************** Bit definition for AFIO_EXTICR1 register *****************/
#define AFIO_EXTICR1_EXTI0_Pos (0U)
#define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
@@ -2537,8 +2469,6 @@ typedef struct
/****************** Bit definition for AFIO_MAPR2 register ******************/
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
@@ -3795,7 +3725,6 @@ typedef struct
#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
/*****************************************************************************/
/* */
/* Timers (TIM) */
@@ -9863,8 +9792,6 @@ typedef struct
#define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
/**
* @}
*/
@@ -9878,8 +9805,7 @@ typedef struct
*/
/****************************** ADC Instances *********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || ((INSTANCE) == ADC2))
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
@@ -9896,20 +9822,12 @@ typedef struct
/****************************** DAC Instances *********************************/
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
((INSTANCE) == DMA1_Channel2) || \
((INSTANCE) == DMA1_Channel3) || \
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5) || \
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA1_Channel7))
#define IS_DMA_ALL_INSTANCE(INSTANCE) \
(((INSTANCE) == DMA1_Channel1) || ((INSTANCE) == DMA1_Channel2) || ((INSTANCE) == DMA1_Channel3) || ((INSTANCE) == DMA1_Channel4) || ((INSTANCE) == DMA1_Channel5) || ((INSTANCE) == DMA1_Channel6) \
|| ((INSTANCE) == DMA1_Channel7))
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE))
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE))
/**************************** GPIO Alternate Function Instances ***************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
@@ -9918,8 +9836,7 @@ typedef struct
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2))
/******************************* SMBUS Instances ******************************/
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
@@ -9928,226 +9845,98 @@ typedef struct
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2))
/****************************** START TIM Instances ***************************/
/****************************** TIM Instances *********************************/
#define IS_TIM_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_CC2_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_CC3_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_CC4_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
#define IS_TIM_BREAK_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
((((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
|| (((INSTANCE) == TIM2) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
|| (((INSTANCE) == TIM3) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
|| (((INSTANCE) == TIM4) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))))
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
(((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3)))
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3)))
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
/********************* UART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
/***************** UART Instances : Multi-Processor mode **********************/
#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
/***************** UART Instances : DMA mode available **********************/
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -10158,8 +9947,6 @@ typedef struct
/****************************** USB Instances ********************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
#define RCC_HSE_MIN 4000000U
#define RCC_HSE_MAX 16000000U
@@ -10194,7 +9981,6 @@ typedef struct
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
@@ -10213,7 +9999,6 @@ typedef struct
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
/**
* @}
*/
@@ -10222,13 +10007,10 @@ typedef struct
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F103xB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

34
source/Core/BSP/MHP30/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h vendored
View File

@@ -57,9 +57,8 @@
application
*/
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
#if !defined(STM32F100xB) && !defined(STM32F100xE) && !defined(STM32F101x6) && !defined(STM32F101xB) && !defined(STM32F101xE) && !defined(STM32F101xG) && !defined(STM32F102x6) \
&& !defined(STM32F102xB) && !defined(STM32F103x6) && !defined(STM32F103xB) && !defined(STM32F103xE) && !defined(STM32F103xG) && !defined(STM32F105xC) && !defined(STM32F107xC)
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
@@ -96,10 +95,7 @@
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) | (__STM32F1_CMSIS_VERSION_SUB1 << 16) | (__STM32F1_CMSIS_VERSION_SUB2 << 8) | (__STM32F1_CMSIS_VERSION_RC))
/**
* @}
@@ -148,30 +144,17 @@
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0U,
ERROR = !SUCCESS
} ErrorStatus;
typedef enum { SUCCESS = 0U, ERROR = !SUCCESS } ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
@@ -191,7 +174,6 @@ typedef enum
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
@@ -200,7 +182,6 @@ typedef enum
#include "stm32f1xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
@@ -214,7 +195,4 @@ typedef enum
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1
source/Core/BSP/MHP30/Vendor/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h vendored
View File

@@ -43,7 +43,6 @@
* @}
*/
/** @addtogroup STM32F10x_System_Exported_types
* @{
*/

193
source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_armcc.h vendored
View File

@@ -25,14 +25,12 @@
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#if ((defined(__TARGET_ARCH_6_M) && (__TARGET_ARCH_6_M == 1)) || (defined(__TARGET_ARCH_6S_M) && (__TARGET_ARCH_6S_M == 1)))
#define __ARM_ARCH_6M__ 1
#endif
@@ -47,7 +45,6 @@
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
@@ -114,7 +111,6 @@
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
@@ -127,135 +123,112 @@
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
__STATIC_INLINE uint32_t __get_CONTROL(void) {
register uint32_t __regControl __ASM("control");
return (__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__STATIC_INLINE void __set_CONTROL(uint32_t control) {
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
__STATIC_INLINE uint32_t __get_IPSR(void) {
register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
__STATIC_INLINE uint32_t __get_APSR(void) {
register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
__STATIC_INLINE uint32_t __get_xPSR(void) {
register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
__STATIC_INLINE uint32_t __get_PSP(void) {
register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) {
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
__STATIC_INLINE uint32_t __get_MSP(void) {
register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) {
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
__STATIC_INLINE uint32_t __get_PRIMASK(void) {
register uint32_t __regPriMask __ASM("primask");
return (__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) {
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)))
/**
\brief Enable FIQ
@@ -264,7 +237,6 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
@@ -272,63 +244,53 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
__STATIC_INLINE uint32_t __get_BASEPRI(void) {
register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) {
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) {
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
__STATIC_INLINE uint32_t __get_FAULTMASK(void) {
register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) {
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
@@ -336,16 +298,13 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
__STATIC_INLINE uint32_t __get_FPSCR(void) {
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U)))
register uint32_t __regfpscr __ASM("fpscr");
return (__regfpscr);
#else
@@ -353,16 +312,13 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) {
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U)))
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
@@ -370,10 +326,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@@ -386,14 +340,12 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
@@ -401,21 +353,20 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
#define __ISB() \
do { \
__schedule_barrier(); \
__isb(0xF); \
__schedule_barrier(); \
@@ -426,7 +377,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
#define __DSB() \
do { \
__schedule_barrier(); \
__dsb(0xF); \
__schedule_barrier(); \
@@ -437,13 +389,13 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
#define __DMB() \
do { \
__schedule_barrier(); \
__dmb(0xF); \
__schedule_barrier(); \
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
@@ -452,7 +404,6 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
@@ -460,14 +411,9 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr }
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
@@ -475,14 +421,9 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) { revsh r0, r0 bx lr }
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@@ -492,7 +433,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
@@ -502,25 +442,21 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)))
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
for (value >>= 1U; value != 0U; value >>= 1U) {
result <<= 1U;
result |= value & 1U;
s--;
@@ -530,7 +466,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
@@ -539,9 +474,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)))
/**
\brief LDR Exclusive (8 bit)
@@ -555,7 +488,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
@@ -568,7 +500,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
@@ -581,7 +512,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
@@ -596,7 +526,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
@@ -611,7 +540,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
@@ -626,14 +554,12 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
@@ -643,7 +569,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
@@ -653,7 +578,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
@@ -662,14 +586,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr }
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
@@ -678,7 +597,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/
#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
@@ -687,7 +605,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/
#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
@@ -696,7 +613,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/
#define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
@@ -705,7 +621,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
@@ -714,7 +629,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
@@ -733,18 +647,13 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) {
if ((sat >= 1U) && (sat <= 32U)) {
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max;
if (val > max)
{
if (val > max) {
return max;
}
else if (val < min)
{
} else if (val < min) {
return min;
}
}
@@ -758,17 +667,12 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint3
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) {
if (sat <= 31U) {
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
if (val > (int32_t)max) {
return max;
}
else if (val < 0)
{
} else if (val < 0) {
return 0U;
}
}
@@ -780,7 +684,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@@ -849,17 +752,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U)) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

532
source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_armclang.h vendored
View File

File diff suppressed because it is too large Load Diff

21
source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_compiler.h vendored
View File

@@ -33,28 +33,24 @@
#if defined(__CC_ARM)
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined(__GNUC__)
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined(__ICCARM__)
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
@@ -92,7 +88,9 @@
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
struct __attribute__((packed)) T_UINT32 {
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
@@ -119,7 +117,6 @@
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
@@ -161,7 +158,9 @@
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
struct __packed__ T_UINT32 {
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
@@ -188,7 +187,6 @@
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
@@ -228,7 +226,9 @@
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
@packed struct T_UINT32 {
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
@@ -256,11 +256,8 @@
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

643
source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_gcc.h vendored
View File

File diff suppressed because it is too large Load Diff

307
source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_iccarm.h vendored
View File

@@ -22,7 +22,6 @@
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
@@ -52,7 +51,6 @@
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
@@ -76,8 +74,7 @@
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
@@ -95,8 +92,6 @@
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__ == 1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__ == 1
@@ -105,7 +100,6 @@
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
@@ -168,21 +162,17 @@
#ifndef __UNALIGNED_UINT16_READ
#pragma language = save
#pragma language = extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
__IAR_FT uint16_t __iar_uint16_read(void const *ptr) { return *(__packed uint16_t *)(ptr); }
#pragma language = restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language = save
#pragma language = extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) {
*(__packed uint16_t *)(ptr) = val;
;
}
#pragma language = restore
#define __UNALIGNED_UINT16_WRITE(PTR, VAL) __iar_uint16_write(PTR, VAL)
@@ -191,10 +181,7 @@ __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
#ifndef __UNALIGNED_UINT32_READ
#pragma language = save
#pragma language = extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
__IAR_FT uint32_t __iar_uint32_read(void const *ptr) { return *(__packed uint32_t *)(ptr); }
#pragma language = restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
@@ -202,9 +189,9 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language = save
#pragma language = extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) {
*(__packed uint32_t *)(ptr) = val;
;
}
#pragma language = restore
#define __UNALIGNED_UINT32_WRITE(PTR, VAL) __iar_uint32_write(PTR, VAL)
@@ -234,7 +221,6 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
@@ -266,14 +252,12 @@ __packed struct __iar_u32 { uint32_t v; };
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U)))
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
@@ -283,8 +267,7 @@ __packed struct __iar_u32 { uint32_t v; };
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
@@ -293,8 +276,7 @@ __packed struct __iar_u32 { uint32_t v; };
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
@@ -309,8 +291,7 @@ __packed struct __iar_u32 { uint32_t v; };
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
@@ -318,8 +299,7 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
@@ -341,8 +321,7 @@ __packed struct __iar_u32 { uint32_t v; };
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE) (__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
@@ -371,10 +350,7 @@ __packed struct __iar_u32 { uint32_t v; };
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
__IAR_FT int16_t __REVSH(int16_t val) { return (int16_t)__iar_builtin_REVSH(val); }
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
@@ -472,9 +448,7 @@ __packed struct __iar_u32 { uint32_t v; };
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#if (!((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
@@ -493,27 +467,25 @@ __packed struct __iar_u32 { uint32_t v; };
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
__STATIC_INLINE uint8_t __CLZ(uint32_t data) {
if (data == 0U) {
return 32U;
}
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
while ((data & mask) == 0U) {
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
__STATIC_INLINE uint32_t __RBIT(uint32_t v) {
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
for (v >>= 1U; v; v >>= 1U) {
r <<= 1U;
r |= v & 1U;
sc--;
@@ -521,8 +493,7 @@ __packed struct __iar_u32 { uint32_t v; };
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
__STATIC_INLINE uint32_t __get_APSR(void) {
uint32_t res;
__asm("MRS %0,APSR" : "=r"(res));
return res;
@@ -530,8 +501,7 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#if (!((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
@@ -549,53 +519,34 @@ __packed struct __iar_u32 { uint32_t v; };
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__ == 0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { return __LDREX((unsigned long *)ptr); }
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { return __STREX(value, (unsigned long *)ptr); }
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
__IAR_FT uint32_t __RRX(uint32_t value) {
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r"(value) : "cc");
return (result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value) { __asm volatile("MSR BASEPRI_MAX,%0" ::"r"(value)); }
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << ((sizeof(op1) * 8) - op2)); }
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
__IAR_FT uint32_t __get_MSPLIM(void)
{
__IAR_FT uint32_t __get_MSPLIM(void) {
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
@@ -604,10 +555,8 @@ __packed struct __iar_u32 { uint32_t v; };
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
__IAR_FT void __set_MSPLIM(uint32_t value) {
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
@@ -615,11 +564,9 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
__IAR_FT uint32_t __get_PSPLIM(void) {
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
@@ -628,10 +575,8 @@ __packed struct __iar_u32 { uint32_t v; };
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
__IAR_FT void __set_PSPLIM(uint32_t value) {
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
@@ -639,94 +584,64 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void) {
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { __asm volatile("MSR CONTROL_NS,%0" ::"r"(value)); }
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
__IAR_FT uint32_t __TZ_get_PSP_NS(void) {
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value) { __asm volatile("MSR PSP_NS,%0" ::"r"(value)); }
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
__IAR_FT uint32_t __TZ_get_MSP_NS(void) {
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value) { __asm volatile("MSR MSP_NS,%0" ::"r"(value)); }
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
__IAR_FT uint32_t __TZ_get_SP_NS(void) {
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value) { __asm volatile("MSR SP_NS,%0" ::"r"(value)); }
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) {
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { __asm volatile("MSR PRIMASK_NS,%0" ::"r"(value)); }
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) {
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { __asm volatile("MSR BASEPRI_NS,%0" ::"r"(value)); }
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) {
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { __asm volatile("MSR FAULTMASK_NS,%0" ::"r"(value)); }
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) {
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
@@ -735,10 +650,8 @@ __packed struct __iar_u32 { uint32_t v; };
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) {
#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
@@ -746,17 +659,13 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) {
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { __asm volatile("MSR MSPLIM_NS,%0" ::"r"(value)); }
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
@@ -765,35 +674,25 @@ __packed struct __iar_u32 { uint32_t v; };
#define __BKPT(value) __asm volatile("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) {
if ((sat >= 1U) && (sat <= 32U)) {
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max;
if (val > max)
{
if (val > max) {
return max;
}
else if (val < min)
{
} else if (val < min) {
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) {
if (sat <= 31U) {
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
if (val > (int32_t)max) {
return max;
}
else if (val < 0)
{
} else if (val < 0) {
return 0U;
}
}
@@ -803,121 +702,89 @@ __packed struct __iar_u32 { uint32_t v; };
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) {
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) {
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr) {
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM("STRBT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory"); }
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM("STRHT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory"); }
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM("STRT %1, [%0]" : : "r"(addr), "r"(value) : "memory"); }
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) {
uint32_t res;
__ASM volatile("LDAB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) {
uint32_t res;
__ASM volatile("LDAH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr) {
uint32_t res;
__ASM volatile("LDA %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("STLB %1, [%0]" ::"r"(ptr), "r"(value) : "memory"); }
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("STLH %1, [%0]" ::"r"(ptr), "r"(value) : "memory"); }
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("STL %1, [%0]" ::"r"(ptr), "r"(value) : "memory"); }
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) {
uint32_t res;
__ASM volatile("LDAEXB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) {
uint32_t res;
__ASM volatile("LDAEXH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) {
uint32_t res;
__ASM volatile("LDAEX %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) {
uint32_t res;
__ASM volatile("STLEXB %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) {
uint32_t res;
__ASM volatile("STLEXH %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) {
uint32_t res;
__ASM volatile("STLEX %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
return res;

3
source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_version.h vendored
View File

@@ -34,6 +34,5 @@
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN (5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB (1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB) /*!< CMSIS Core(M) version number */
#endif

254
source/Core/BSP/MHP30/Vendor/CMSIS/Include/core_cm3.h vendored
View File

@@ -51,7 +51,6 @@
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
@@ -65,8 +64,7 @@
/* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
__CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (3U) /*!< Cortex-M Core */
@@ -114,7 +112,6 @@
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
@@ -176,8 +173,6 @@
/*@} end of group Cortex_M3 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
@@ -203,10 +198,8 @@
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */
uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
@@ -233,14 +226,11 @@ typedef union
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
@@ -251,14 +241,11 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 1; /*!< bit: 9 Reserved */
uint32_t ICI_IT_1 : 6; /*!< bit: 10..15 ICI/IT part 1 */
@@ -302,14 +289,11 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
@@ -326,7 +310,6 @@ typedef union
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -337,8 +320,7 @@ typedef union
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
typedef struct {
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -360,7 +342,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
@@ -371,8 +352,7 @@ typedef struct
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
typedef struct {
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -641,7 +621,6 @@ typedef struct
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -652,8 +631,7 @@ typedef struct
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
typedef struct {
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
#if defined(__CM3_REV) && (__CM3_REV >= 0x200U)
@@ -680,7 +658,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -691,8 +668,7 @@ typedef struct
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -732,7 +708,6 @@ typedef struct
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
@@ -743,10 +718,8 @@ typedef struct
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
typedef struct {
__OM union {
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
@@ -835,7 +808,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
@@ -846,8 +818,7 @@ typedef struct
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
@@ -982,7 +953,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
@@ -993,8 +963,7 @@ typedef struct
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
typedef struct {
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
@@ -1143,7 +1112,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_TPI */
#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
@@ -1155,8 +1123,7 @@ typedef struct
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
typedef struct {
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -1240,7 +1207,6 @@ typedef struct
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -1251,8 +1217,7 @@ typedef struct
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
typedef struct {
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
@@ -1345,7 +1310,6 @@ typedef struct
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
@@ -1371,7 +1335,6 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
@@ -1405,8 +1368,6 @@ typedef struct
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
@@ -1419,8 +1380,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
@@ -1461,13 +1420,11 @@ typedef struct
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
@@ -1477,30 +1434,22 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
/**
\brief Enable Interrupt
@@ -1508,15 +1457,12 @@ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
@@ -1525,36 +1471,28 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
@@ -1563,49 +1501,38 @@ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
@@ -1614,19 +1541,14 @@ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
@@ -1636,19 +1558,14 @@ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
if ((int32_t)(IRQn) >= 0) {
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
} else {
SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
@@ -1658,20 +1575,15 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0)
{
if ((int32_t)(IRQn) >= 0) {
return (((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
} else {
return (((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
@@ -1683,8 +1595,7 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
@@ -1692,13 +1603,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
@@ -1710,8 +1617,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
@@ -1723,7 +1629,6 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
@@ -1733,13 +1638,11 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
@@ -1748,24 +1651,19 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) {
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */
@@ -1800,16 +1698,10 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
__STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ }
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
@@ -1831,19 +1723,15 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
@@ -1851,8 +1739,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
@@ -1864,7 +1750,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
@@ -1873,13 +1758,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
while (ITM->PORT[0U].u32 == 0UL) {
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -1887,19 +1770,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
@@ -1907,31 +1787,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
__STATIC_INLINE int32_t ITM_CheckChar(void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
}
else
{
} else {
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif

177
source/Core/BSP/MHP30/Vendor/CMSIS/Include/core_sc000.h vendored
View File

@@ -51,7 +51,6 @@
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
@@ -65,8 +64,7 @@
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
__SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | __SC000_CMSIS_VERSION_SUB) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_SC (000U) /*!< Cortex secure core */
@@ -114,7 +112,6 @@
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
@@ -176,8 +173,6 @@
/*@} end of group SC000 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
@@ -202,10 +197,8 @@
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
@@ -228,14 +221,11 @@ typedef union
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
@@ -246,14 +236,11 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
@@ -285,14 +272,11 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
@@ -306,7 +290,6 @@ typedef union
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -317,8 +300,7 @@ typedef union
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
typedef struct {
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -333,7 +315,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
@@ -344,8 +325,7 @@ typedef struct
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
typedef struct {
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -446,7 +426,6 @@ typedef struct
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -457,8 +436,7 @@ typedef struct
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
typedef struct {
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
@@ -469,7 +447,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -480,8 +457,7 @@ typedef struct
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -532,8 +508,7 @@ typedef struct
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
typedef struct {
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -609,7 +584,6 @@ typedef struct
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -619,7 +593,6 @@ typedef struct
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
@@ -645,7 +618,6 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
@@ -671,8 +643,6 @@ typedef struct
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
@@ -684,8 +654,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
@@ -726,35 +694,29 @@ typedef struct
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
@@ -763,36 +725,28 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
@@ -801,49 +755,38 @@ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
@@ -853,21 +796,14 @@ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
if ((int32_t)(IRQn) >= 0) {
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} else {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
@@ -877,20 +813,15 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0)
{
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
} else {
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
@@ -900,13 +831,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
@@ -915,23 +844,19 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) {
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */
@@ -942,7 +867,6 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
@@ -959,16 +883,10 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
__STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ }
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
@@ -990,19 +908,15 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
@@ -1010,9 +924,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif

256
source/Core/BSP/MHP30/Vendor/CMSIS/Include/core_sc300.h vendored
View File

@@ -51,7 +51,6 @@
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
@@ -65,8 +64,7 @@
/* CMSIS SC300 definitions */
#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
__SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | __SC300_CMSIS_VERSION_SUB) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_SC (300U) /*!< Cortex secure core */
@@ -114,7 +112,6 @@
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
@@ -176,8 +173,6 @@
/*@} end of group SC300 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
@@ -203,10 +198,8 @@
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */
uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
@@ -233,14 +226,11 @@ typedef union
#define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
@@ -251,14 +241,11 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 1; /*!< bit: 9 Reserved */
uint32_t ICI_IT_1 : 6; /*!< bit: 10..15 ICI/IT part 1 */
@@ -302,14 +289,11 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
@@ -326,7 +310,6 @@ typedef union
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -337,8 +320,7 @@ typedef union
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
typedef struct {
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -360,7 +342,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
@@ -371,8 +352,7 @@ typedef struct
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
typedef struct {
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -638,7 +618,6 @@ typedef struct
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -649,8 +628,7 @@ typedef struct
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
typedef struct {
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
uint32_t RESERVED1[1U];
@@ -662,7 +640,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -673,8 +650,7 @@ typedef struct
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -714,7 +690,6 @@ typedef struct
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
@@ -725,10 +700,8 @@ typedef struct
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
typedef struct {
__OM union {
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
@@ -817,7 +790,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_ITM */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
@@ -828,8 +800,7 @@ typedef struct
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
@@ -964,7 +935,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI)
@@ -975,8 +945,7 @@ typedef struct
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
typedef struct {
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
@@ -1125,7 +1094,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_TPI */
#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
@@ -1137,8 +1105,7 @@ typedef struct
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
typedef struct {
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -1220,7 +1187,6 @@ typedef struct
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -1231,8 +1197,7 @@ typedef struct
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
typedef struct {
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
@@ -1325,7 +1290,6 @@ typedef struct
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
@@ -1351,7 +1315,6 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
@@ -1385,8 +1348,6 @@ typedef struct
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
@@ -1399,8 +1360,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
@@ -1441,14 +1400,11 @@ typedef struct
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/**
\brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence.
@@ -1458,30 +1414,22 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
/**
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
/**
\brief Enable Interrupt
@@ -1489,15 +1437,12 @@ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
@@ -1506,36 +1451,28 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
@@ -1544,49 +1481,38 @@ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Active Interrupt
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
@@ -1595,19 +1521,14 @@ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
@@ -1617,19 +1538,14 @@ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
if ((int32_t)(IRQn) >= 0) {
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
} else {
SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
@@ -1639,20 +1555,15 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0)
{
if ((int32_t)(IRQn) >= 0) {
return (((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
} else {
return (((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
@@ -1664,8 +1575,7 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
@@ -1673,13 +1583,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
@@ -1691,8 +1597,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
@@ -1704,7 +1609,6 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
@@ -1714,13 +1618,11 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
@@ -1729,24 +1631,19 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) {
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */
@@ -1757,7 +1654,6 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
@@ -1774,16 +1670,10 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
__STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ }
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
@@ -1805,19 +1695,15 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
@@ -1825,8 +1711,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
@@ -1838,7 +1722,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/**
\brief ITM Send Character
\details Transmits a character via the ITM channel 0, and
@@ -1847,13 +1730,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
while (ITM->PORT[0U].u32 == 0UL) {
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -1861,19 +1742,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
return (ch);
}
/**
\brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
@@ -1881,31 +1759,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
return (ch);
}
/**
\brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
__STATIC_INLINE int32_t ITM_CheckChar(void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
}
else
{
} else {
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus
}
#endif

3
source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h vendored
View File

@@ -90,7 +90,8 @@ typedef struct {
* ADC can be either disabled or enabled without conversion on going on regular group.
*/
typedef struct {
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
uint32_t
Channel; /*!< Specifies the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)

8
source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h vendored
View File

@@ -53,13 +53,13 @@ extern "C" {
* - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
*/
typedef struct {
uint32_t
InjectedChannel; /*!< Selection of ADC channel to configure
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection
trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with
injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata
sheet of these devices for more details. */
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
This parameter must be a value of @ref ADCEx_injected_rank
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel

4
source/Core/BSP/MHP30/postRTOS.cpp
View File

@@ -11,6 +11,4 @@
#include "task.h"
// Initialisation to be performed with scheduler active
void postRToSInit() {
}
void postRToSInit() {}

7
source/Core/Drivers/WS2812.cpp
View File

@@ -5,15 +5,12 @@
* Author: Ralim
*/
#include <WS2812.h>
#include "Pins.h"
#include <WS2812.h>
#include <string.h>
uint8_t WS2812::leds_colors[WS2812_LED_CHANNEL_COUNT * WS2812_LED_COUNT];
void WS2812::init(void) {
memset(leds_colors, 0, sizeof(leds_colors));
}
void WS2812::init(void) { memset(leds_colors, 0, sizeof(leds_colors)); }
void WS2812::led_update() {
__disable_irq();

1
source/Core/Drivers/WS2812.h
View File

@@ -25,7 +25,6 @@ public:
static void led_set_color_all(uint8_t r, uint8_t g, uint8_t b);
private:
static uint8_t leds_colors[WS2812_LED_CHANNEL_COUNT * WS2812_LED_COUNT];
};

173
source/Core/Threads/GUIThread.cpp
View File

@@ -199,14 +199,11 @@ static void gui_solderingTempAdjust() {
return;
break;
case BUTTON_B_LONG:
if (xTaskGetTickCount() - autoRepeatTimer
+ autoRepeatAcceleration> PRESS_ACCEL_INTERVAL_MAX) {
if (xTaskGetTickCount() - autoRepeatTimer + autoRepeatAcceleration > PRESS_ACCEL_INTERVAL_MAX) {
if (systemSettings.ReverseButtonTempChangeEnabled) {
systemSettings.SolderingTemp +=
systemSettings.TempChangeLongStep;
systemSettings.SolderingTemp += systemSettings.TempChangeLongStep;
} else
systemSettings.SolderingTemp -=
systemSettings.TempChangeLongStep;
systemSettings.SolderingTemp -= systemSettings.TempChangeLongStep;
autoRepeatTimer = xTaskGetTickCount();
autoRepeatAcceleration += PRESS_ACCEL_STEP;
@@ -214,40 +211,31 @@ static void gui_solderingTempAdjust() {
break;
case BUTTON_B_SHORT:
if (systemSettings.ReverseButtonTempChangeEnabled) {
systemSettings.SolderingTemp +=
systemSettings.TempChangeShortStep;
systemSettings.SolderingTemp += systemSettings.TempChangeShortStep;
} else
systemSettings.SolderingTemp -=
systemSettings.TempChangeShortStep;
systemSettings.SolderingTemp -= systemSettings.TempChangeShortStep;
break;
case BUTTON_F_LONG:
if (xTaskGetTickCount() - autoRepeatTimer
+ autoRepeatAcceleration> PRESS_ACCEL_INTERVAL_MAX) {
if (xTaskGetTickCount() - autoRepeatTimer + autoRepeatAcceleration > PRESS_ACCEL_INTERVAL_MAX) {
if (systemSettings.ReverseButtonTempChangeEnabled) {
systemSettings.SolderingTemp -=
systemSettings.TempChangeLongStep;
systemSettings.SolderingTemp -= systemSettings.TempChangeLongStep;
} else
systemSettings.SolderingTemp +=
systemSettings.TempChangeLongStep;
systemSettings.SolderingTemp += systemSettings.TempChangeLongStep;
autoRepeatTimer = xTaskGetTickCount();
autoRepeatAcceleration += PRESS_ACCEL_STEP;
}
break;
case BUTTON_F_SHORT:
if (systemSettings.ReverseButtonTempChangeEnabled) {
systemSettings.SolderingTemp -=
systemSettings.TempChangeShortStep; // add 10
systemSettings.SolderingTemp -= systemSettings.TempChangeShortStep; // add 10
} else
systemSettings.SolderingTemp +=
systemSettings.TempChangeShortStep; // add 10
systemSettings.SolderingTemp += systemSettings.TempChangeShortStep; // add 10
break;
default:
break;
}
if ((PRESS_ACCEL_INTERVAL_MAX - autoRepeatAcceleration)
< PRESS_ACCEL_INTERVAL_MIN) {
autoRepeatAcceleration = PRESS_ACCEL_INTERVAL_MAX
- PRESS_ACCEL_INTERVAL_MIN;
if ((PRESS_ACCEL_INTERVAL_MAX - autoRepeatAcceleration) < PRESS_ACCEL_INTERVAL_MIN) {
autoRepeatAcceleration = PRESS_ACCEL_INTERVAL_MAX - PRESS_ACCEL_INTERVAL_MIN;
}
// constrain between 10-450 C
if (systemSettings.temperatureInF) {
@@ -270,13 +258,9 @@ static void gui_solderingTempAdjust() {
#else
if (OLED::getRotation()) {
#endif
OLED::print(
systemSettings.ReverseButtonTempChangeEnabled ?
SymbolPlus : SymbolMinus, FontStyle::LARGE);
OLED::print(systemSettings.ReverseButtonTempChangeEnabled ? SymbolPlus : SymbolMinus, FontStyle::LARGE);
} else {
OLED::print(
systemSettings.ReverseButtonTempChangeEnabled ?
SymbolMinus : SymbolPlus, FontStyle::LARGE);
OLED::print(systemSettings.ReverseButtonTempChangeEnabled ? SymbolMinus : SymbolPlus, FontStyle::LARGE);
}
OLED::print(SymbolSpace, FontStyle::LARGE);
@@ -292,13 +276,9 @@ static void gui_solderingTempAdjust() {
#else
if (OLED::getRotation()) {
#endif
OLED::print(
systemSettings.ReverseButtonTempChangeEnabled ?
SymbolMinus : SymbolPlus, FontStyle::LARGE);
OLED::print(systemSettings.ReverseButtonTempChangeEnabled ? SymbolMinus : SymbolPlus, FontStyle::LARGE);
} else {
OLED::print(
systemSettings.ReverseButtonTempChangeEnabled ?
SymbolPlus : SymbolMinus, FontStyle::LARGE);
OLED::print(systemSettings.ReverseButtonTempChangeEnabled ? SymbolPlus : SymbolMinus, FontStyle::LARGE);
}
OLED::refresh();
GUIDelay();
@@ -307,14 +287,12 @@ static void gui_solderingTempAdjust() {
static bool shouldShutdown() {
if (systemSettings.ShutdownTime) { // only allow shutdown exit if time > 0
if (lastMovementTime) {
if (((TickType_t) (xTaskGetTickCount() - lastMovementTime))
> (TickType_t) (systemSettings.ShutdownTime * TICKS_MIN)) {
if (((TickType_t)(xTaskGetTickCount() - lastMovementTime)) > (TickType_t)(systemSettings.ShutdownTime * TICKS_MIN)) {
return true;
}
}
if (lastHallEffectSleepStart) {
if (((TickType_t) (xTaskGetTickCount() - lastHallEffectSleepStart))
> (TickType_t) (systemSettings.ShutdownTime * TICKS_MIN)) {
if (((TickType_t)(xTaskGetTickCount() - lastHallEffectSleepStart)) > (TickType_t)(systemSettings.ShutdownTime * TICKS_MIN)) {
return true;
}
}
@@ -333,18 +311,9 @@ static int gui_SolderingSleepingMode(bool stayOff, bool autoStarted) {
return 1; // return non-zero on error
#endif
if (systemSettings.temperatureInF) {
currentTempTargetDegC =
stayOff ?
0 :
TipThermoModel::convertFtoC(
min(systemSettings.SleepTemp,
systemSettings.SolderingTemp));
currentTempTargetDegC = stayOff ? 0 : TipThermoModel::convertFtoC(min(systemSettings.SleepTemp, systemSettings.SolderingTemp));
} else {
currentTempTargetDegC =
stayOff ?
0 :
min(systemSettings.SleepTemp,
systemSettings.SolderingTemp);
currentTempTargetDegC = stayOff ? 0 : min(systemSettings.SleepTemp, systemSettings.SolderingTemp);
}
// draw the lcd
uint16_t tipTemp;
@@ -357,11 +326,9 @@ static int gui_SolderingSleepingMode(bool stayOff, bool autoStarted) {
OLED::clearScreen();
OLED::setCursor(0, 0);
if (systemSettings.detailedSoldering) {
OLED::print(translatedString(Tr->SleepingAdvancedString),
FontStyle::SMALL);
OLED::print(translatedString(Tr->SleepingAdvancedString), FontStyle::SMALL);
OLED::setCursor(0, 8);
OLED::print(translatedString(Tr->SleepingTipAdvancedString),
FontStyle::SMALL);
OLED::print(translatedString(Tr->SleepingTipAdvancedString), FontStyle::SMALL);
OLED::printNumber(tipTemp, 3, FontStyle::SMALL);
if (systemSettings.temperatureInF)
OLED::print(SymbolDegF, FontStyle::SMALL);
@@ -373,8 +340,7 @@ static int gui_SolderingSleepingMode(bool stayOff, bool autoStarted) {
printVoltage();
OLED::print(SymbolVolts, FontStyle::SMALL);
} else {
OLED::print(translatedString(Tr->SleepingSimpleString),
FontStyle::LARGE);
OLED::print(translatedString(Tr->SleepingSimpleString), FontStyle::LARGE);
OLED::printNumber(tipTemp, 3, FontStyle::LARGE);
if (systemSettings.temperatureInF)
OLED::drawSymbol(0);
@@ -393,8 +359,7 @@ static int gui_SolderingSleepingMode(bool stayOff, bool autoStarted) {
// If we have moved recently; in the last second
// Then exit soldering mode
if (((TickType_t) (xTaskGetTickCount() - lastMovementTime))
< (TickType_t) (TICKS_SECOND)) {
if (((TickType_t)(xTaskGetTickCount() - lastMovementTime)) < (TickType_t)(TICKS_SECOND)) {
currentTempTargetDegC = 0;
return 1;
}
@@ -521,13 +486,11 @@ static void gui_solderingMode(uint8_t jumpToSleep) {
case BUTTON_BOTH_LONG:
// Unlock buttons
buttonsLocked = false;
warnUser(translatedString(Tr->UnlockingKeysString),
TICKS_SECOND);
warnUser(translatedString(Tr->UnlockingKeysString), TICKS_SECOND);
break;
case BUTTON_F_LONG:
// if boost mode is enabled turn it on
if (systemSettings.BoostTemp
&& (systemSettings.lockingMode == 1)) {
if (systemSettings.BoostTemp && (systemSettings.lockingMode == 1)) {
boostModeOn = true;
}
break;
@@ -537,8 +500,7 @@ static void gui_solderingMode(uint8_t jumpToSleep) {
case BUTTON_F_SHORT:
case BUTTON_B_SHORT:
// Do nothing and display a lock warming
warnUser(translatedString(Tr->WarningKeysLockedString),
TICKS_SECOND / 2);
warnUser(translatedString(Tr->WarningKeysLockedString), TICKS_SECOND / 2);
break;
default:
break;
@@ -568,14 +530,12 @@ static void gui_solderingMode(uint8_t jumpToSleep) {
if (oldTemp != systemSettings.SolderingTemp) {
saveSettings(); // only save on change
}
}
break;
} break;
case BUTTON_BOTH_LONG:
if (systemSettings.lockingMode != 0) {
// Lock buttons
buttonsLocked = true;
warnUser(translatedString(Tr->LockingKeysString),
TICKS_SECOND);
warnUser(translatedString(Tr->LockingKeysString), TICKS_SECOND);
}
break;
default:
@@ -589,11 +549,9 @@ static void gui_solderingMode(uint8_t jumpToSleep) {
if (systemSettings.detailedSoldering) {
OLED::print(translatedString(Tr->SolderingAdvancedPowerPrompt),
FontStyle::SMALL); // Power:
OLED::printNumber(x10WattHistory.average() / 10, 2,
FontStyle::SMALL);
OLED::printNumber(x10WattHistory.average() / 10, 2, FontStyle::SMALL);
OLED::print(SymbolDot, FontStyle::SMALL);
OLED::printNumber(x10WattHistory.average() % 10, 1,
FontStyle::SMALL);
OLED::printNumber(x10WattHistory.average() % 10, 1, FontStyle::SMALL);
OLED::print(SymbolWatts, FontStyle::SMALL);
#ifndef NO_SLEEP_MODE
if (systemSettings.sensitivity && systemSettings.SleepTime) {
@@ -602,8 +560,7 @@ static void gui_solderingMode(uint8_t jumpToSleep) {
}
#endif
OLED::setCursor(0, 8);
OLED::print(translatedString(Tr->SleepingTipAdvancedString),
FontStyle::SMALL);
OLED::print(translatedString(Tr->SleepingTipAdvancedString), FontStyle::SMALL);
gui_drawTipTemp(true, FontStyle::SMALL);
if (boostModeOn) {
@@ -652,15 +609,13 @@ static void gui_solderingMode(uint8_t jumpToSleep) {
// Update the setpoints for the temperature
if (boostModeOn) {
if (systemSettings.temperatureInF)
currentTempTargetDegC = TipThermoModel::convertFtoC(
systemSettings.BoostTemp);
currentTempTargetDegC = TipThermoModel::convertFtoC(systemSettings.BoostTemp);
else {
currentTempTargetDegC = (systemSettings.BoostTemp);
}
} else {
if (systemSettings.temperatureInF)
currentTempTargetDegC = TipThermoModel::convertFtoC(
systemSettings.SolderingTemp);
currentTempTargetDegC = TipThermoModel::convertFtoC(systemSettings.SolderingTemp);
else {
currentTempTargetDegC = (systemSettings.SolderingTemp);
}
@@ -706,36 +661,27 @@ void showDebugMenu(void) {
break;
case 1:
// High water mark for GUI
OLED::printNumber(uxTaskGetStackHighWaterMark(GUITaskHandle), 5,
FontStyle::SMALL);
OLED::printNumber(uxTaskGetStackHighWaterMark(GUITaskHandle), 5, FontStyle::SMALL);
break;
case 2:
// High water mark for the Movement task
OLED::printNumber(uxTaskGetStackHighWaterMark(MOVTaskHandle), 5,
FontStyle::SMALL);
OLED::printNumber(uxTaskGetStackHighWaterMark(MOVTaskHandle), 5, FontStyle::SMALL);
break;
case 3:
// High water mark for the PID task
OLED::printNumber(uxTaskGetStackHighWaterMark(PIDTaskHandle), 5,
FontStyle::SMALL);
OLED::printNumber(uxTaskGetStackHighWaterMark(PIDTaskHandle), 5, FontStyle::SMALL);
break;
case 4:
// system up time stamp
OLED::printNumber(xTaskGetTickCount() / TICKS_100MS, 5,
FontStyle::SMALL);
OLED::printNumber(xTaskGetTickCount() / TICKS_100MS, 5, FontStyle::SMALL);
break;
case 5:
// Movement time stamp
OLED::printNumber(lastMovementTime / TICKS_100MS, 5,
FontStyle::SMALL);
OLED::printNumber(lastMovementTime / TICKS_100MS, 5, FontStyle::SMALL);
break;
case 6:
// Raw Tip
{
OLED::printNumber(
TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0),
true), 6, FontStyle::SMALL);
}
{ OLED::printNumber(TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0), true), 6, FontStyle::SMALL); }
break;
case 7:
// Temp in C
@@ -751,8 +697,7 @@ void showDebugMenu(void) {
break;
case 10:
// Print PCB ID number
OLED::printNumber(DetectedAccelerometerVersion, 2,
FontStyle::SMALL);
OLED::printNumber(DetectedAccelerometerVersion, 2, FontStyle::SMALL);
break;
case 11:
// Power negotiation status
@@ -780,8 +725,7 @@ void showDebugMenu(void) {
break;
case 12:
// Max deg C limit
OLED::printNumber(TipThermoModel::getTipMaxInC(), 3,
FontStyle::SMALL);
OLED::printNumber(TipThermoModel::getTipMaxInC(), 3, FontStyle::SMALL);
break;
default:
break;
@@ -816,8 +760,7 @@ void showWarnings() {
if (systemSettings.accelMissingWarningCounter < 2) {
systemSettings.accelMissingWarningCounter++;
saveSettings();
warnUser(translatedString(Tr->NoAccelerometerMessage),
10 * TICKS_SECOND);
warnUser(translatedString(Tr->NoAccelerometerMessage), 10 * TICKS_SECOND);
}
}
#ifdef POW_PD
@@ -826,8 +769,7 @@ void showWarnings() {
if (systemSettings.pdMissingWarningCounter < 2) {
systemSettings.pdMissingWarningCounter++;
saveSettings();
warnUser(translatedString(Tr->NoPowerDeliveryMessage),
10 * TICKS_SECOND);
warnUser(translatedString(Tr->NoPowerDeliveryMessage), 10 * TICKS_SECOND);
}
}
#endif
@@ -850,8 +792,7 @@ void startGUITask(void const *argument __unused) {
// flipped is generated by flipping each row
for (int row = 0; row < 2; row++) {
for (int x = 0; x < 84; x++) {
idleScreenBGF[(row * 84) + x] = idleScreenBG[(row * 84)
+ (83 - x)];
idleScreenBGF[(row * 84) + x] = idleScreenBG[(row * 84) + (83 - x)];
}
}
}
@@ -935,11 +876,7 @@ void startGUITask(void const *argument __unused) {
// This is zero cost really as state is only changed on display updates
OLED::setDisplayState(OLED::DisplayState::ON);
if ((tipTemp < 50) && systemSettings.sensitivity
&& (((xTaskGetTickCount() - lastMovementTime)
> MOVEMENT_INACTIVITY_TIME)
&& ((xTaskGetTickCount() - lastButtonTime)
> BUTTON_INACTIVITY_TIME))) {
if ((tipTemp < 50) && systemSettings.sensitivity && (((xTaskGetTickCount() - lastMovementTime) > MOVEMENT_INACTIVITY_TIME) && ((xTaskGetTickCount() - lastButtonTime) > BUTTON_INACTIVITY_TIME))) {
OLED::setDisplayState(OLED::DisplayState::OFF);
setStatusLED(LED_OFF);
}
@@ -948,21 +885,16 @@ void startGUITask(void const *argument __unused) {
OLED::setCursor(0, 0);
if (systemSettings.detailedIDLE) {
if (isTipDisconnected()) {
OLED::print(translatedString(Tr->TipDisconnectedString),
FontStyle::SMALL);
OLED::print(translatedString(Tr->TipDisconnectedString), FontStyle::SMALL);
} else {
OLED::print(translatedString(Tr->IdleTipString),
FontStyle::SMALL);
OLED::print(translatedString(Tr->IdleTipString), FontStyle::SMALL);
gui_drawTipTemp(false, FontStyle::SMALL);
OLED::print(translatedString(Tr->IdleSetString),
FontStyle::SMALL);
OLED::printNumber(systemSettings.SolderingTemp, 3,
FontStyle::SMALL);
OLED::print(translatedString(Tr->IdleSetString), FontStyle::SMALL);
OLED::printNumber(systemSettings.SolderingTemp, 3, FontStyle::SMALL);
}
OLED::setCursor(0, 8);
OLED::print(translatedString(Tr->InputVoltageString),
FontStyle::SMALL);
OLED::print(translatedString(Tr->InputVoltageString), FontStyle::SMALL);
printVoltage();
} else {
@@ -1008,8 +940,7 @@ void startGUITask(void const *argument __unused) {
// If we have a tip connected draw the temp, if not we leave it blank
if (!tipDisconnectedDisplay) {
// draw in the temp
if (!(systemSettings.coolingTempBlink
&& (xTaskGetTickCount() % 260 < 160)))
if (!(systemSettings.coolingTempBlink && (xTaskGetTickCount() % 260 < 160)))
gui_drawTipTemp(false, FontStyle::LARGE); // draw in the temp
} else {
// Draw in missing tip symbol