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Update peripheral_config.h
This commit is contained in:
Ben V. Brown
@@ -26,12 +26,12 @@
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/* PERIPHERAL USING LIST */
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/* PERIPHERAL USING LIST */
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#define BSP_USING_ADC0
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#define BSP_USING_ADC0
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#define BSP_USING_DAC0
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// #define BSP_USING_DAC0
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#define BSP_USING_UART0
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#define BSP_USING_UART0
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#define BSP_USING_UART1
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// #define BSP_USING_UART1
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#define BSP_USING_SPI0
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// #define BSP_USING_SPI0
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#define BSP_USING_I2C0
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#define BSP_USING_I2C0
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#define BSP_USING_I2S0
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// #define BSP_USING_I2S0
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#define BSP_USING_PWM_CH0
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#define BSP_USING_PWM_CH0
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#define BSP_USING_PWM_CH1
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#define BSP_USING_PWM_CH1
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#define BSP_USING_PWM_CH2
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#define BSP_USING_PWM_CH2
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@@ -40,11 +40,11 @@
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#define BSP_USING_TIMER0
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#define BSP_USING_TIMER0
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#define BSP_USING_TIMER1
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#define BSP_USING_TIMER1
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#define BSP_USING_WDT
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#define BSP_USING_WDT
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#define BSP_USING_KEYSCAN
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// #define BSP_USING_KEYSCAN
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#define BSP_USING_QDEC0
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// #define BSP_USING_QDEC0
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#define BSP_USING_QDEC1
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// #define BSP_USING_QDEC1
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#define BSP_USING_QDEC2
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// #define BSP_USING_QDEC2
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#define BSP_USING_USB
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// #define BSP_USING_USB
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/* ----------------------*/
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/* ----------------------*/
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/* PERIPHERAL With DMA LIST */
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/* PERIPHERAL With DMA LIST */
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@@ -61,438 +61,205 @@
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/* PERIPHERAL CONFIG */
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/* PERIPHERAL CONFIG */
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#if defined(BSP_USING_ADC0)
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#if defined(BSP_USING_ADC0)
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#ifndef ADC0_CONFIG
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#ifndef ADC0_CONFIG
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#define ADC0_CONFIG \
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#define ADC0_CONFIG \
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{ \
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{ \
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.clk_div = ADC_CLOCK_DIV_32, \
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.clk_div = ADC_CLOCK_DIV_32, .vref = ADC_VREF_3V2, .continuous_conv_mode = DISABLE, .differential_mode = DISABLE, .data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, \
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.vref = ADC_VREF_3V2, \
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.fifo_threshold = ADC_FIFO_THRESHOLD_1BYTE, .gain = ADC_GAIN_1 \
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.continuous_conv_mode = DISABLE, \
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}
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.differential_mode = DISABLE, \
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.data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, \
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.fifo_threshold = ADC_FIFO_THRESHOLD_1BYTE, \
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.gain = ADC_GAIN_1 \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_DAC0)
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#if defined(BSP_USING_DAC0)
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#ifndef DAC_CONFIG
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#ifndef DAC_CONFIG
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#define DAC_CONFIG \
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#define DAC_CONFIG \
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{ \
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{ .channels = DAC_CHANNEL_0, .sample_freq = DAC_SAMPLE_FREQ_500KHZ, .vref = DAC_VREF_INTERNAL, }
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.channels = DAC_CHANNEL_0, \
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.sample_freq = DAC_SAMPLE_FREQ_500KHZ, \
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.vref = DAC_VREF_INTERNAL, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_UART0)
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#if defined(BSP_USING_UART0)
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#ifndef UART0_CONFIG
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#ifndef UART0_CONFIG
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#define UART0_CONFIG \
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#define UART0_CONFIG \
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{ \
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{ .id = 0, .baudrate = 2000000, .databits = UART_DATA_LEN_8, .stopbits = UART_STOP_ONE, .parity = UART_PAR_NONE, .fifo_threshold = 0, }
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.id = 0, \
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.baudrate = 2000000, \
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.databits = UART_DATA_LEN_8, \
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.stopbits = UART_STOP_ONE, \
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.parity = UART_PAR_NONE, \
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.fifo_threshold = 0, \
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}
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#endif
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#endif
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#if defined(BSP_USING_UART1)
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#ifndef UART1_CONFIG
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#define UART1_CONFIG \
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{ \
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.id = 1, \
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.baudrate = 2000000, \
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.databits = UART_DATA_LEN_8, \
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.stopbits = UART_STOP_ONE, \
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.parity = UART_PAR_NONE, \
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.fifo_threshold = 63, \
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}
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#endif
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#endif
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#if defined(BSP_USING_SPI0)
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#ifndef SPI0_CONFIG
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#define SPI0_CONFIG \
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{ \
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.id = 0, \
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.clk = 18000000, \
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.mode = SPI_MASTER_MODE, \
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.direction = SPI_MSB_BYTE0_DIRECTION_FIRST, \
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.clk_polaraity = SPI_POLARITY_LOW, \
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.clk_phase = SPI_PHASE_1EDGE, \
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.datasize = SPI_DATASIZE_8BIT, \
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.fifo_threshold = 1, \
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.pin_swap_enable = 1, \
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.delitch_cnt = 0, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_PWM_CH0)
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#if defined(BSP_USING_PWM_CH0)
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#ifndef PWM_CH0_CONFIG
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#ifndef PWM_CH0_CONFIG
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#define PWM_CH0_CONFIG \
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#define PWM_CH0_CONFIG \
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{ \
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{ .ch = 0, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
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.ch = 0, \
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.polarity_invert_mode = DISABLE, \
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.period = 0, \
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.threshold_low = 0, \
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.threshold_high = 0, \
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.it_pulse_count = 0, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_PWM_CH1)
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#if defined(BSP_USING_PWM_CH1)
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#ifndef PWM_CH1_CONFIG
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#ifndef PWM_CH1_CONFIG
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#define PWM_CH1_CONFIG \
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#define PWM_CH1_CONFIG \
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{ \
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{ .ch = 1, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
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.ch = 1, \
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.polarity_invert_mode = DISABLE, \
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.period = 0, \
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.threshold_low = 0, \
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.threshold_high = 0, \
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.it_pulse_count = 0, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_PWM_CH2)
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#if defined(BSP_USING_PWM_CH2)
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#ifndef PWM_CH2_CONFIG
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#ifndef PWM_CH2_CONFIG
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#define PWM_CH2_CONFIG \
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#define PWM_CH2_CONFIG \
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{ \
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{ .ch = 2, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
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.ch = 2, \
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.polarity_invert_mode = DISABLE, \
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.period = 0, \
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.threshold_low = 0, \
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.threshold_high = 0, \
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.it_pulse_count = 0, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_PWM_CH3)
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#if defined(BSP_USING_PWM_CH3)
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#ifndef PWM_CH3_CONFIG
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#ifndef PWM_CH3_CONFIG
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#define PWM_CH3_CONFIG \
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#define PWM_CH3_CONFIG \
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{ \
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{ .ch = 3, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
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.ch = 3, \
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.polarity_invert_mode = DISABLE, \
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.period = 0, \
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.threshold_low = 0, \
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.threshold_high = 0, \
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.it_pulse_count = 0, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_PWM_CH4)
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#if defined(BSP_USING_PWM_CH4)
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#ifndef PWM_CH4_CONFIG
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#ifndef PWM_CH4_CONFIG
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#define PWM_CH4_CONFIG \
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#define PWM_CH4_CONFIG \
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{ \
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{ .ch = 4, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
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.ch = 4, \
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.polarity_invert_mode = DISABLE, \
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.period = 0, \
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.threshold_low = 0, \
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.threshold_high = 0, \
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.it_pulse_count = 0, \
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}
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#endif
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#endif
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#if defined(BSP_USING_I2S0)
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#ifndef I2S0_CONFIG
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#define I2S0_CONFIG \
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{ \
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.id = 0, \
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.iis_mode = I2S_MODE_MASTER, \
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.interface_mode = I2S_MODE_LEFT, \
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.sampl_freq_hz = 16 * 1000, \
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.channel_num = I2S_FS_CHANNELS_NUM_MONO, \
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.frame_size = I2S_FRAME_LEN_16, \
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.data_size = I2S_DATA_LEN_16, \
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.fifo_threshold = 8, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH0)
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#if defined(BSP_USING_DMA0_CH0)
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#ifndef DMA0_CH0_CONFIG
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#ifndef DMA0_CH0_CONFIG
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#define DMA0_CH0_CONFIG \
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#define DMA0_CH0_CONFIG \
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{ \
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{ \
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.id = 0, \
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.id = 0, .ch = 0, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.ch = 0, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_4BYTE, .dst_burst_size = DMA_BURST_4BYTE, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
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.direction = DMA_MEMORY_TO_MEMORY, \
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}
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_NONE, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.src_burst_size = DMA_BURST_4BYTE, \
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.dst_burst_size = DMA_BURST_4BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_32BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH1)
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#if defined(BSP_USING_DMA0_CH1)
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#ifndef DMA0_CH1_CONFIG
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#ifndef DMA0_CH1_CONFIG
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#define DMA0_CH1_CONFIG \
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#define DMA0_CH1_CONFIG \
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{ \
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{ \
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.id = 0, \
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.id = 0, .ch = 1, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.ch = 1, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_4BYTE, .dst_burst_size = DMA_BURST_4BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
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.direction = DMA_MEMORY_TO_MEMORY, \
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}
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_NONE, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.src_burst_size = DMA_BURST_4BYTE, \
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.dst_burst_size = DMA_BURST_4BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_16BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH2)
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#if defined(BSP_USING_DMA0_CH2)
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#ifndef DMA0_CH2_CONFIG
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#ifndef DMA0_CH2_CONFIG
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#define DMA0_CH2_CONFIG \
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#define DMA0_CH2_CONFIG \
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{ \
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{ \
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.id = 0, \
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.id = 0, .ch = 2, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_UART1_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.ch = 2, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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.direction = DMA_MEMORY_TO_PERIPH, \
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}
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_UART1_TX, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
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.src_burst_size = DMA_BURST_1BYTE, \
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.dst_burst_size = DMA_BURST_1BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_8BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH3)
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#if defined(BSP_USING_DMA0_CH3)
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#ifndef DMA0_CH3_CONFIG
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#ifndef DMA0_CH3_CONFIG
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#define DMA0_CH3_CONFIG \
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#define DMA0_CH3_CONFIG \
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{ \
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{ \
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.id = 0, \
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.id = 0, .ch = 3, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_SPI0_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.ch = 3, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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.direction = DMA_MEMORY_TO_PERIPH, \
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}
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_NONE, \
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.dst_req = DMA_REQUEST_SPI0_TX, \
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
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.src_burst_size = DMA_BURST_1BYTE, \
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.dst_burst_size = DMA_BURST_1BYTE, \
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.src_width = DMA_TRANSFER_WIDTH_8BIT, \
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.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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}
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#endif
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#endif
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH4)
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#if defined(BSP_USING_DMA0_CH4)
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#ifndef DMA0_CH4_CONFIG
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#ifndef DMA0_CH4_CONFIG
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#define DMA0_CH4_CONFIG \
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#define DMA0_CH4_CONFIG \
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{ \
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{ \
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.id = 0, \
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.id = 0, .ch = 4, .direction = DMA_PERIPH_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_SPI0_RX, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
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.ch = 4, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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.direction = DMA_PERIPH_TO_MEMORY, \
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}
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.transfer_mode = DMA_LLI_ONCE_MODE, \
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.src_req = DMA_REQUEST_SPI0_RX, \
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.dst_req = DMA_REQUEST_NONE, \
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|
||||||
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
|
|
||||||
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
|
|
||||||
.src_burst_size = DMA_BURST_1BYTE, \
|
|
||||||
.dst_burst_size = DMA_BURST_1BYTE, \
|
|
||||||
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
|
|
||||||
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_DMA0_CH5)
|
#if defined(BSP_USING_DMA0_CH5)
|
||||||
#ifndef DMA0_CH5_CONFIG
|
#ifndef DMA0_CH5_CONFIG
|
||||||
#define DMA0_CH5_CONFIG \
|
#define DMA0_CH5_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.id = 0, \
|
.id = 0, .ch = 5, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
|
||||||
.ch = 5, \
|
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
|
||||||
.direction = DMA_MEMORY_TO_PERIPH, \
|
}
|
||||||
.transfer_mode = DMA_LLI_CYCLE_MODE, \
|
|
||||||
.src_req = DMA_REQUEST_NONE, \
|
|
||||||
.dst_req = DMA_REQUEST_I2S_TX, \
|
|
||||||
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
|
|
||||||
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
|
|
||||||
.src_burst_size = DMA_BURST_1BYTE, \
|
|
||||||
.dst_burst_size = DMA_BURST_1BYTE, \
|
|
||||||
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
|
|
||||||
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_DMA0_CH6)
|
#if defined(BSP_USING_DMA0_CH6)
|
||||||
#ifndef DMA0_CH6_CONFIG
|
#ifndef DMA0_CH6_CONFIG
|
||||||
#define DMA0_CH6_CONFIG \
|
#define DMA0_CH6_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.id = 0, \
|
.id = 0, .ch = 6, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
|
||||||
.ch = 6, \
|
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
|
||||||
.direction = DMA_MEMORY_TO_PERIPH, \
|
}
|
||||||
.transfer_mode = DMA_LLI_CYCLE_MODE, \
|
|
||||||
.src_req = DMA_REQUEST_NONE, \
|
|
||||||
.dst_req = DMA_REQUEST_I2S_TX, \
|
|
||||||
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
|
|
||||||
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
|
|
||||||
.src_burst_size = DMA_BURST_1BYTE, \
|
|
||||||
.dst_burst_size = DMA_BURST_1BYTE, \
|
|
||||||
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
|
|
||||||
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_DMA0_CH7)
|
#if defined(BSP_USING_DMA0_CH7)
|
||||||
#ifndef DMA0_CH7_CONFIG
|
#ifndef DMA0_CH7_CONFIG
|
||||||
#define DMA0_CH7_CONFIG \
|
#define DMA0_CH7_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.id = 0, \
|
.id = 0, .ch = 7, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
|
||||||
.ch = 7, \
|
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
|
||||||
.direction = DMA_MEMORY_TO_MEMORY, \
|
}
|
||||||
.transfer_mode = DMA_LLI_ONCE_MODE, \
|
|
||||||
.src_req = DMA_REQUEST_NONE, \
|
|
||||||
.dst_req = DMA_REQUEST_NONE, \
|
|
||||||
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
|
|
||||||
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
|
|
||||||
.src_burst_size = DMA_BURST_1BYTE, \
|
|
||||||
.dst_burst_size = DMA_BURST_1BYTE, \
|
|
||||||
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
|
|
||||||
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_I2C0)
|
#if defined(BSP_USING_I2C0)
|
||||||
#ifndef I2C0_CONFIG
|
#ifndef I2C0_CONFIG
|
||||||
#define I2C0_CONFIG \
|
#define I2C0_CONFIG \
|
||||||
{ \
|
{ .id = 0, .mode = I2C_HW_MODE, .phase = 15, }
|
||||||
.id = 0, \
|
|
||||||
.mode = I2C_HW_MODE, \
|
|
||||||
.phase = 15, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_TIMER0)
|
#if defined(BSP_USING_TIMER0)
|
||||||
#ifndef TIMER0_CONFIG
|
#ifndef TIMER0_CONFIG
|
||||||
#define TIMER0_CONFIG \
|
#define TIMER0_CONFIG \
|
||||||
{ \
|
{ .id = 0, .cnt_mode = TIMER_CNT_PRELOAD, .trigger = TIMER_PRELOAD_TRIGGER_COMP2, .reload = 0, .timeout1 = 1000000, .timeout2 = 2000000, .timeout3 = 3000000, }
|
||||||
.id = 0, \
|
|
||||||
.cnt_mode = TIMER_CNT_PRELOAD, \
|
|
||||||
.trigger = TIMER_PRELOAD_TRIGGER_COMP2, \
|
|
||||||
.reload = 0, \
|
|
||||||
.timeout1 = 1000000, \
|
|
||||||
.timeout2 = 2000000, \
|
|
||||||
.timeout3 = 3000000, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_TIMER1)
|
#if defined(BSP_USING_TIMER1)
|
||||||
#ifndef TIMER1_CONFIG
|
#ifndef TIMER1_CONFIG
|
||||||
#define TIMER1_CONFIG \
|
#define TIMER1_CONFIG \
|
||||||
{ \
|
{ .id = 1, .cnt_mode = TIMER_CNT_PRELOAD, .trigger = TIMER_PRELOAD_TRIGGER_COMP0, .reload = 0, .timeout1 = 1000000, .timeout2 = 2000000, .timeout3 = 3000000, }
|
||||||
.id = 1, \
|
|
||||||
.cnt_mode = TIMER_CNT_PRELOAD, \
|
|
||||||
.trigger = TIMER_PRELOAD_TRIGGER_COMP0, \
|
|
||||||
.reload = 0, \
|
|
||||||
.timeout1 = 1000000, \
|
|
||||||
.timeout2 = 2000000, \
|
|
||||||
.timeout3 = 3000000, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_WDT)
|
#if defined(BSP_USING_WDT)
|
||||||
#ifndef WDT_CONFIG
|
#ifndef WDT_CONFIG
|
||||||
#define WDT_CONFIG \
|
#define WDT_CONFIG \
|
||||||
{ \
|
{ .id = 0, .wdt_timeout = 6000, }
|
||||||
.id = 0, \
|
|
||||||
.wdt_timeout = 6000, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_KEYSCAN)
|
#if defined(BSP_USING_KEYSCAN)
|
||||||
#ifndef KEYSCAN_CONFIG
|
#ifndef KEYSCAN_CONFIG
|
||||||
#define KEYSCAN_CONFIG \
|
#define KEYSCAN_CONFIG \
|
||||||
{ \
|
{ .col_num = COL_NUM_4, .row_num = ROW_NUM_4, .deglitch_count = 0, }
|
||||||
.col_num = COL_NUM_4, \
|
|
||||||
.row_num = ROW_NUM_4, \
|
|
||||||
.deglitch_count = 0, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_QDEC0)
|
#if defined(BSP_USING_QDEC0)
|
||||||
#ifndef QDEC0_CONFIG
|
#ifndef QDEC0_CONFIG
|
||||||
#define QDEC0_CONFIG \
|
#define QDEC0_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.id = 0, \
|
.id = 0, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
|
||||||
.acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, \
|
.led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0, \
|
||||||
.sample_mode = QDEC_SAMPLE_SINGLE_MOD, \
|
}
|
||||||
.sample_period = QDEC_SAMPLE_PERIOD_256US, \
|
|
||||||
.report_mode = QDEC_REPORT_TIME_MOD, \
|
|
||||||
.report_period = 2000, \
|
|
||||||
.led_en = ENABLE, \
|
|
||||||
.led_swap = DISABLE, \
|
|
||||||
.led_period = 7, \
|
|
||||||
.deglitch_en = DISABLE, \
|
|
||||||
.deglitch_strength = 0x0, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_QDEC1)
|
#if defined(BSP_USING_QDEC1)
|
||||||
#ifndef QDEC1_CONFIG
|
#ifndef QDEC1_CONFIG
|
||||||
#define QDEC1_CONFIG \
|
#define QDEC1_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.id = 1, \
|
.id = 1, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
|
||||||
.acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, \
|
.led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0, \
|
||||||
.sample_mode = QDEC_SAMPLE_SINGLE_MOD, \
|
}
|
||||||
.sample_period = QDEC_SAMPLE_PERIOD_256US, \
|
|
||||||
.report_mode = QDEC_REPORT_TIME_MOD, \
|
|
||||||
.report_period = 2000, \
|
|
||||||
.led_en = ENABLE, \
|
|
||||||
.led_swap = DISABLE, \
|
|
||||||
.led_period = 7, \
|
|
||||||
.deglitch_en = DISABLE, \
|
|
||||||
.deglitch_strength = 0x0, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(BSP_USING_QDEC2)
|
#if defined(BSP_USING_QDEC2)
|
||||||
#ifndef QDEC2_CONFIG
|
#ifndef QDEC2_CONFIG
|
||||||
#define QDEC2_CONFIG \
|
#define QDEC2_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.id = 2, \
|
.id = 2, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
|
||||||
.acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, \
|
.led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0, \
|
||||||
.sample_mode = QDEC_SAMPLE_SINGLE_MOD, \
|
}
|
||||||
.sample_period = QDEC_SAMPLE_PERIOD_256US, \
|
|
||||||
.report_mode = QDEC_REPORT_TIME_MOD, \
|
|
||||||
.report_period = 2000, \
|
|
||||||
.led_en = ENABLE, \
|
|
||||||
.led_swap = DISABLE, \
|
|
||||||
.led_period = 7, \
|
|
||||||
.deglitch_en = DISABLE, \
|
|
||||||
.deglitch_strength = 0x0, \
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|||||||
Reference in New Issue
Block a user