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This commit is contained in:
Ben V. Brown
2021-01-17 10:53:49 +11:00
parent f786901da0
commit bf5055edaa
173 changed files with 42831 additions and 47623 deletions
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12
source/Core/BSP/BSP.h
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@@ -1,10 +1,10 @@
#include <stdint.h>
#include <stdbool.h>
#include "BSP_Flash.h" #include "BSP_Flash.h"
#include "BSP_Power.h" #include "BSP_Power.h"
#include "BSP_QC.h" #include "BSP_QC.h"
#include "Defines.h" #include "Defines.h"
#include "Model_Config.h" #include "Model_Config.h"
#include <stdbool.h>
#include <stdint.h>
/* /*
* BSP.h -- Board Support * BSP.h -- Board Support
* *
@@ -59,16 +59,16 @@ void reboot();
// If the user has programmed in a bootup logo, draw it to the screen from flash // If the user has programmed in a bootup logo, draw it to the screen from flash
// Returns 1 if the logo was printed so that the unit waits for the timeout or button // Returns 1 if the logo was printed so that the unit waits for the timeout or button
uint8_t showBootLogoIfavailable(); uint8_t showBootLogoIfavailable();
//delay wrapper for delay using the hardware timer (used before RTOS) // delay wrapper for delay using the hardware timer (used before RTOS)
void delay_ms(uint16_t count) ; void delay_ms(uint16_t count);
//Used to allow knowledge of if usb_pd is being used // Used to allow knowledge of if usb_pd is being used
uint8_t usb_pd_detect(); uint8_t usb_pd_detect();
bool getHallSensorFitted(); bool getHallSensorFitted();
// If the iron has a hall effect sensor in the handle, return an signed count of the reading // If the iron has a hall effect sensor in the handle, return an signed count of the reading
// If the sensor is single polarity (or polarity insensitive) just return 0..32768 // If the sensor is single polarity (or polarity insensitive) just return 0..32768
int16_t getRawHallEffect(); int16_t getRawHallEffect();
//Returns true if power is from dumb "DC" input rather than "smart" QC or PD // Returns true if power is from dumb "DC" input rather than "smart" QC or PD
bool getIsPoweredByDCIN(); bool getIsPoweredByDCIN();
#ifdef __cplusplus #ifdef __cplusplus

2
source/Core/BSP/BSP_Flash.h
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@@ -16,7 +16,7 @@ extern "C" {
* Should allow reading and writing to the flash * Should allow reading and writing to the flash
*/ */
//Erase the flash, then save the buffer. Returns 1 if worked // Erase the flash, then save the buffer. Returns 1 if worked
uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length); uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length);
void flash_read_buffer(uint8_t *buffer, const uint16_t length); void flash_read_buffer(uint8_t *buffer, const uint16_t length);

1
source/Core/BSP/BSP_Power.h
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@@ -12,7 +12,6 @@
extern "C" { extern "C" {
#endif #endif
// Called periodically in the movement handling thread // Called periodically in the movement handling thread
// Can be used to check any details for the power system // Can be used to check any details for the power system
void power_check(); void power_check();

11
source/Core/BSP/Defines.h
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@@ -8,14 +8,11 @@
#ifndef BSP_DEFINES_H_ #ifndef BSP_DEFINES_H_
#define BSP_DEFINES_H_ #define BSP_DEFINES_H_
enum Orientation { ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3 };
enum Orientation { // It is assumed that all hardware implements an 8Hz update period at this time
ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3
};
//It is assumed that all hardware implements an 8Hz update period at this time
#define PID_TIM_HZ (8) #define PID_TIM_HZ (8)
#define TICKS_SECOND configTICK_RATE_HZ #define TICKS_SECOND configTICK_RATE_HZ
#define TICKS_MIN (60*TICKS_SECOND) #define TICKS_MIN (60 * TICKS_SECOND)
#define TICKS_100MS (TICKS_SECOND/10) #define TICKS_100MS (TICKS_SECOND / 10)
#endif /* BSP_DEFINES_H_ */ #endif /* BSP_DEFINES_H_ */

27
source/Core/BSP/Miniware/FreeRTOSConfig.h
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@@ -97,12 +97,12 @@ extern uint32_t SystemCoreClock;
#define configSUPPORT_DYNAMIC_ALLOCATION 0 #define configSUPPORT_DYNAMIC_ALLOCATION 0
#define configUSE_IDLE_HOOK 1 #define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0 #define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock ) #define configCPU_CLOCK_HZ (SystemCoreClock)
#define configTICK_RATE_HZ ((TickType_t)1000) #define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES ( 6 ) #define configMAX_PRIORITIES (6)
#define configMINIMAL_STACK_SIZE ((uint16_t)256) #define configMINIMAL_STACK_SIZE ((uint16_t)256)
#define configTOTAL_HEAP_SIZE ((size_t)1024*14) /*Currently use about 9000*/ #define configTOTAL_HEAP_SIZE ((size_t)1024 * 14) /*Currently use about 9000*/
#define configMAX_TASK_NAME_LEN ( 32 ) #define configMAX_TASK_NAME_LEN (32)
#define configUSE_16_BIT_TICKS 0 #define configUSE_16_BIT_TICKS 0
#define configUSE_MUTEXES 1 #define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8 #define configQUEUE_REGISTRY_SIZE 8
@@ -112,7 +112,7 @@ extern uint32_t SystemCoreClock;
/* Co-routine definitions. */ /* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0 #define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) #define configMAX_CO_ROUTINE_PRIORITIES (2)
/* Set the following definitions to 1 to include the API function, or zero /* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */ to exclude the API function. */
@@ -128,8 +128,8 @@ extern uint32_t SystemCoreClock;
/* Cortex-M specific definitions. */ /* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS #ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS #define configPRIO_BITS __NVIC_PRIO_BITS
#else #else
#define configPRIO_BITS 4 #define configPRIO_BITS 4
#endif #endif
@@ -146,15 +146,20 @@ extern uint32_t SystemCoreClock;
/* Interrupt priorities used by the kernel port layer itself. These are generic /* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */ to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) #define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) #define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* Normal assert() semantics without relying on the provision of an assert.h /* Normal assert() semantics without relying on the provision of an assert.h
header file. */ header file. */
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} #define configASSERT(x) \
if ((x) == 0) { \
taskDISABLE_INTERRUPTS(); \
for (;;) \
; \
}
/* USER CODE END 1 */ /* USER CODE END 1 */
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
@@ -165,7 +170,7 @@ extern uint32_t SystemCoreClock;
#if configUSE_TIMERS #if configUSE_TIMERS
#define configTIMER_TASK_PRIORITY 2 #define configTIMER_TASK_PRIORITY 2
#define configTIMER_QUEUE_LENGTH 8 #define configTIMER_QUEUE_LENGTH 8
#define configTIMER_TASK_STACK_DEPTH (512/4) #define configTIMER_TASK_STACK_DEPTH (512 / 4)
#endif #endif
#endif /* FREERTOS_CONFIG_H */ #endif /* FREERTOS_CONFIG_H */

2
source/Core/BSP/Miniware/IRQ.h
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@@ -9,10 +9,10 @@
#define BSP_MINIWARE_IRQ_H_ #define BSP_MINIWARE_IRQ_H_
#include "BSP.h" #include "BSP.h"
#include "stm32f1xx_hal.h"
#include "I2C_Wrapper.hpp" #include "I2C_Wrapper.hpp"
#include "Setup.h" #include "Setup.h"
#include "main.hpp" #include "main.hpp"
#include "stm32f1xx_hal.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

4
source/Core/BSP/Miniware/Model_Config.h
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@@ -11,9 +11,9 @@
* Lookup for mapping features <-> Models * Lookup for mapping features <-> Models
*/ */
#if defined(MODEL_TS100) + defined(MODEL_TS80)+defined(MODEL_TS80P) > 1 #if defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) > 1
#error "Multiple models defined!" #error "Multiple models defined!"
#elif defined(MODEL_TS100) + defined(MODEL_TS80)+ defined(MODEL_TS80P) == 0 #elif defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) == 0
#error "No model defined!" #error "No model defined!"
#endif #endif

2
source/Core/BSP/Miniware/Setup.h
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@@ -29,7 +29,7 @@ extern TIM_HandleTypeDef htim3;
void Setup_HAL(); void Setup_HAL();
uint16_t getADC(uint8_t channel); uint16_t getADC(uint8_t channel);
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); //Since the hal header file does not define this one void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); // Since the hal header file does not define this one
#ifdef __cplusplus #ifdef __cplusplus
} }

13
source/Core/BSP/Miniware/Software_I2C.h
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@@ -7,8 +7,8 @@
#ifndef BSP_MINIWARE_SOFTWARE_I2C_H_ #ifndef BSP_MINIWARE_SOFTWARE_I2C_H_
#define BSP_MINIWARE_SOFTWARE_I2C_H_ #define BSP_MINIWARE_SOFTWARE_I2C_H_
#include "Model_Config.h"
#include "BSP.h" #include "BSP.h"
#include "Model_Config.h"
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
#ifdef I2C_SOFT #ifdef I2C_SOFT
@@ -16,9 +16,14 @@
#define SOFT_SCL_LOW() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_RESET) #define SOFT_SCL_LOW() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_RESET)
#define SOFT_SDA_HIGH() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_SET) #define SOFT_SDA_HIGH() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_SET)
#define SOFT_SDA_LOW() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET) #define SOFT_SDA_LOW() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET)
#define SOFT_SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port,SDA2_Pin)==GPIO_PIN_SET?1:0) #define SOFT_SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port, SDA2_Pin) == GPIO_PIN_SET ? 1 : 0)
#define SOFT_SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port,SCL2_Pin)==GPIO_PIN_SET?1:0) #define SOFT_SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port, SCL2_Pin) == GPIO_PIN_SET ? 1 : 0)
#define SOFT_I2C_DELAY() {for(int xx=0;xx<40;xx++){asm("nop");}} #define SOFT_I2C_DELAY() \
{ \
for (int xx = 0; xx < 40; xx++) { \
asm("nop"); \
} \
}
#endif #endif

424
source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h vendored
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@@ -43,7 +43,6 @@
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
@@ -56,7 +55,7 @@
#define __STM32F103xB_H #define __STM32F103xB_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** @addtogroup Configuration_section_for_CMSIS /** @addtogroup Configuration_section_for_CMSIS
@@ -66,7 +65,7 @@
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/ */
#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
#define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -83,10 +82,9 @@
* in @ref Library_configuration_section * in @ref Library_configuration_section
*/ */
/*!< Interrupt Number Definition */ /*!< Interrupt Number Definition */
typedef enum typedef enum {
{ /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
@@ -97,7 +95,7 @@ typedef enum
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers *********************************************************/ /****** STM32 specific Interrupt Numbers *********************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMPER_IRQn = 2, /*!< Tamper Interrupt */ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
@@ -159,8 +157,7 @@ typedef enum
* @brief Analog to Digital Converter * @brief Analog to Digital Converter
*/ */
typedef struct typedef struct {
{
__IO uint32_t SR; __IO uint32_t SR;
__IO uint32_t CR1; __IO uint32_t CR1;
__IO uint32_t CR2; __IO uint32_t CR2;
@@ -183,8 +180,7 @@ typedef struct
__IO uint32_t DR; __IO uint32_t DR;
} ADC_TypeDef; } ADC_TypeDef;
typedef struct typedef struct {
{
__IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
__IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
@@ -196,8 +192,7 @@ typedef struct
* @brief Backup Registers * @brief Backup Registers
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0; uint32_t RESERVED0;
__IO uint32_t DR1; __IO uint32_t DR1;
__IO uint32_t DR2; __IO uint32_t DR2;
@@ -218,8 +213,7 @@ typedef struct
* @brief Controller Area Network TxMailBox * @brief Controller Area Network TxMailBox
*/ */
typedef struct typedef struct {
{
__IO uint32_t TIR; __IO uint32_t TIR;
__IO uint32_t TDTR; __IO uint32_t TDTR;
__IO uint32_t TDLR; __IO uint32_t TDLR;
@@ -230,8 +224,7 @@ typedef struct
* @brief Controller Area Network FIFOMailBox * @brief Controller Area Network FIFOMailBox
*/ */
typedef struct typedef struct {
{
__IO uint32_t RIR; __IO uint32_t RIR;
__IO uint32_t RDTR; __IO uint32_t RDTR;
__IO uint32_t RDLR; __IO uint32_t RDLR;
@@ -242,8 +235,7 @@ typedef struct
* @brief Controller Area Network FilterRegister * @brief Controller Area Network FilterRegister
*/ */
typedef struct typedef struct {
{
__IO uint32_t FR1; __IO uint32_t FR1;
__IO uint32_t FR2; __IO uint32_t FR2;
} CAN_FilterRegister_TypeDef; } CAN_FilterRegister_TypeDef;
@@ -252,8 +244,7 @@ typedef struct
* @brief Controller Area Network * @brief Controller Area Network
*/ */
typedef struct typedef struct {
{
__IO uint32_t MCR; __IO uint32_t MCR;
__IO uint32_t MSR; __IO uint32_t MSR;
__IO uint32_t TSR; __IO uint32_t TSR;
@@ -282,8 +273,7 @@ typedef struct
* @brief CRC calculation unit * @brief CRC calculation unit
*/ */
typedef struct typedef struct {
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
@@ -291,43 +281,36 @@ typedef struct
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
} CRC_TypeDef; } CRC_TypeDef;
/** /**
* @brief Debug MCU * @brief Debug MCU
*/ */
typedef struct typedef struct {
{
__IO uint32_t IDCODE; __IO uint32_t IDCODE;
__IO uint32_t CR; __IO uint32_t CR;
}DBGMCU_TypeDef; } DBGMCU_TypeDef;
/** /**
* @brief DMA Controller * @brief DMA Controller
*/ */
typedef struct typedef struct {
{
__IO uint32_t CCR; __IO uint32_t CCR;
__IO uint32_t CNDTR; __IO uint32_t CNDTR;
__IO uint32_t CPAR; __IO uint32_t CPAR;
__IO uint32_t CMAR; __IO uint32_t CMAR;
} DMA_Channel_TypeDef; } DMA_Channel_TypeDef;
typedef struct typedef struct {
{
__IO uint32_t ISR; __IO uint32_t ISR;
__IO uint32_t IFCR; __IO uint32_t IFCR;
} DMA_TypeDef; } DMA_TypeDef;
/** /**
* @brief External Interrupt/Event Controller * @brief External Interrupt/Event Controller
*/ */
typedef struct typedef struct {
{
__IO uint32_t IMR; __IO uint32_t IMR;
__IO uint32_t EMR; __IO uint32_t EMR;
__IO uint32_t RTSR; __IO uint32_t RTSR;
@@ -340,8 +323,7 @@ typedef struct
* @brief FLASH Registers * @brief FLASH Registers
*/ */
typedef struct typedef struct {
{
__IO uint32_t ACR; __IO uint32_t ACR;
__IO uint32_t KEYR; __IO uint32_t KEYR;
__IO uint32_t OPTKEYR; __IO uint32_t OPTKEYR;
@@ -357,8 +339,7 @@ typedef struct
* @brief Option Bytes Registers * @brief Option Bytes Registers
*/ */
typedef struct typedef struct {
{
__IO uint16_t RDP; __IO uint16_t RDP;
__IO uint16_t USER; __IO uint16_t USER;
__IO uint16_t Data0; __IO uint16_t Data0;
@@ -373,8 +354,7 @@ typedef struct
* @brief General Purpose I/O * @brief General Purpose I/O
*/ */
typedef struct typedef struct {
{
__IO uint32_t CRL; __IO uint32_t CRL;
__IO uint32_t CRH; __IO uint32_t CRH;
__IO uint32_t IDR; __IO uint32_t IDR;
@@ -388,8 +368,7 @@ typedef struct
* @brief Alternate Function I/O * @brief Alternate Function I/O
*/ */
typedef struct typedef struct {
{
__IO uint32_t EVCR; __IO uint32_t EVCR;
__IO uint32_t MAPR; __IO uint32_t MAPR;
__IO uint32_t EXTICR[4]; __IO uint32_t EXTICR[4];
@@ -400,8 +379,7 @@ typedef struct
* @brief Inter Integrated Circuit Interface * @brief Inter Integrated Circuit Interface
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR1; __IO uint32_t CR1;
__IO uint32_t CR2; __IO uint32_t CR2;
__IO uint32_t OAR1; __IO uint32_t OAR1;
@@ -417,8 +395,7 @@ typedef struct
* @brief Independent WATCHDOG * @brief Independent WATCHDOG
*/ */
typedef struct typedef struct {
{
__IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
@@ -429,8 +406,7 @@ typedef struct
* @brief Power Control * @brief Power Control
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR; __IO uint32_t CR;
__IO uint32_t CSR; __IO uint32_t CSR;
} PWR_TypeDef; } PWR_TypeDef;
@@ -439,8 +415,7 @@ typedef struct
* @brief Reset and Clock Control * @brief Reset and Clock Control
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR; __IO uint32_t CR;
__IO uint32_t CFGR; __IO uint32_t CFGR;
__IO uint32_t CIR; __IO uint32_t CIR;
@@ -452,15 +427,13 @@ typedef struct
__IO uint32_t BDCR; __IO uint32_t BDCR;
__IO uint32_t CSR; __IO uint32_t CSR;
} RCC_TypeDef; } RCC_TypeDef;
/** /**
* @brief Real-Time Clock * @brief Real-Time Clock
*/ */
typedef struct typedef struct {
{
__IO uint32_t CRH; __IO uint32_t CRH;
__IO uint32_t CRL; __IO uint32_t CRL;
__IO uint32_t PRLH; __IO uint32_t PRLH;
@@ -477,8 +450,7 @@ typedef struct
* @brief SD host Interface * @brief SD host Interface
*/ */
typedef struct typedef struct {
{
__IO uint32_t POWER; __IO uint32_t POWER;
__IO uint32_t CLKCR; __IO uint32_t CLKCR;
__IO uint32_t ARG; __IO uint32_t ARG;
@@ -505,8 +477,7 @@ typedef struct
* @brief Serial Peripheral Interface * @brief Serial Peripheral Interface
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR1; __IO uint32_t CR1;
__IO uint32_t CR2; __IO uint32_t CR2;
__IO uint32_t SR; __IO uint32_t SR;
@@ -520,8 +491,7 @@ typedef struct
/** /**
* @brief TIM Timers * @brief TIM Timers
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
@@ -543,15 +513,13 @@ typedef struct
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
}TIM_TypeDef; } TIM_TypeDef;
/** /**
* @brief Universal Synchronous Asynchronous Receiver Transmitter * @brief Universal Synchronous Asynchronous Receiver Transmitter
*/ */
typedef struct typedef struct {
{
__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
@@ -565,8 +533,7 @@ typedef struct
* @brief Universal Serial Bus Full Speed Device * @brief Universal Serial Bus Full Speed Device
*/ */
typedef struct typedef struct {
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
@@ -595,13 +562,11 @@ typedef struct
__IO uint16_t RESERVEDC; /*!< Reserved */ __IO uint16_t RESERVEDC; /*!< Reserved */
} USB_TypeDef; } USB_TypeDef;
/** /**
* @brief Window WATCHDOG * @brief Window WATCHDOG
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
@@ -615,7 +580,6 @@ typedef struct
* @{ * @{
*/ */
#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ #define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */ #define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ #define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
@@ -624,7 +588,6 @@ typedef struct
#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ #define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */ /*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE #define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
@@ -675,15 +638,12 @@ typedef struct
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ #define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */ #define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ #define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/* USB device FS */ /* USB device FS */
#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
/** /**
* @} * @}
*/ */
@@ -735,7 +695,6 @@ typedef struct
#define OB ((OB_TypeDef *)OB_BASE) #define OB ((OB_TypeDef *)OB_BASE)
#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/** /**
* @} * @}
*/ */
@@ -744,7 +703,7 @@ typedef struct
* @{ * @{
*/ */
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -827,7 +786,6 @@ typedef struct
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
/******************* Bit definition for PWR_CSR register ********************/ /******************* Bit definition for PWR_CSR register ********************/
#define PWR_CSR_WUF_Pos (0U) #define PWR_CSR_WUF_Pos (0U)
#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
@@ -977,7 +935,6 @@ typedef struct
#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
/******************* Bit definition for RCC_CFGR register *******************/ /******************* Bit definition for RCC_CFGR register *******************/
/*!< SW configuration */ /*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U) #define RCC_CFGR_SW_Pos (0U)
@@ -1141,16 +1098,16 @@ typedef struct
#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */ /* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
/*!<****************** Bit definition for RCC_CIR register ********************/ /*!<****************** Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF_Pos (0U) #define RCC_CIR_LSIRDYF_Pos (0U)
@@ -1205,7 +1162,6 @@ typedef struct
#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
/***************** Bit definition for RCC_APB2RSTR register *****************/ /***************** Bit definition for RCC_APB2RSTR register *****************/
#define RCC_APB2RSTR_AFIORST_Pos (0U) #define RCC_APB2RSTR_AFIORST_Pos (0U)
#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
@@ -1240,14 +1196,10 @@ typedef struct
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_IOPERST_Pos (6U) #define RCC_APB2RSTR_IOPERST_Pos (6U)
#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
/***************** Bit definition for RCC_APB1RSTR register *****************/ /***************** Bit definition for RCC_APB1RSTR register *****************/
#define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Pos (0U)
#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
@@ -1293,11 +1245,6 @@ typedef struct
#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
/****************** Bit definition for RCC_AHBENR register ******************/ /****************** Bit definition for RCC_AHBENR register ******************/
#define RCC_AHBENR_DMA1EN_Pos (0U) #define RCC_AHBENR_DMA1EN_Pos (0U)
#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
@@ -1312,9 +1259,6 @@ typedef struct
#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
/****************** Bit definition for RCC_APB2ENR register *****************/ /****************** Bit definition for RCC_APB2ENR register *****************/
#define RCC_APB2ENR_AFIOEN_Pos (0U) #define RCC_APB2ENR_AFIOEN_Pos (0U)
#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
@@ -1349,14 +1293,10 @@ typedef struct
#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
#define RCC_APB2ENR_IOPEEN_Pos (6U) #define RCC_APB2ENR_IOPEEN_Pos (6U)
#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
/***************** Bit definition for RCC_APB1ENR register ******************/ /***************** Bit definition for RCC_APB1ENR register ******************/
#define RCC_APB1ENR_TIM2EN_Pos (0U) #define RCC_APB1ENR_TIM2EN_Pos (0U)
#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
@@ -1402,11 +1342,6 @@ typedef struct
#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
/******************* Bit definition for RCC_BDCR register *******************/ /******************* Bit definition for RCC_BDCR register *******************/
#define RCC_BDCR_LSEON_Pos (0U) #define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
@@ -1466,8 +1401,6 @@ typedef struct
#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* General Purpose and Alternate Function I/O */ /* General Purpose and Alternate Function I/O */
@@ -2190,7 +2123,6 @@ typedef struct
#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
/***************** Bit definition for AFIO_EXTICR1 register *****************/ /***************** Bit definition for AFIO_EXTICR1 register *****************/
#define AFIO_EXTICR1_EXTI0_Pos (0U) #define AFIO_EXTICR1_EXTI0_Pos (0U)
#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
@@ -2585,8 +2517,6 @@ typedef struct
/****************** Bit definition for AFIO_MAPR2 register ******************/ /****************** Bit definition for AFIO_MAPR2 register ******************/
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* External Interrupt/Event Controller */ /* External Interrupt/Event Controller */
@@ -3843,7 +3773,6 @@ typedef struct
#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
/*****************************************************************************/ /*****************************************************************************/
/* */ /* */
/* Timers (TIM) */ /* Timers (TIM) */
@@ -4560,7 +4489,6 @@ typedef struct
#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* SD host Interface */ /* SD host Interface */
@@ -4967,8 +4895,8 @@ typedef struct
#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */ /* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) #define USB_EPREG_MASK (USB_EP_CTR_RX | USB_EP_SETUP | USB_EP_T_FIELD | USB_EP_KIND | USB_EP_CTR_TX | USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */ /*!< EP_TYPE[1:0] EndPoint TYPE */
#define USB_EP_TYPE_MASK_Pos (9U) #define USB_EP_TYPE_MASK_Pos (9U)
#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
@@ -4986,15 +4914,15 @@ typedef struct
#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */ #define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */ #define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */ #define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) #define USB_EPTX_DTOGMASK (USB_EPTX_STAT | USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */ /*!< STAT_RX[1:0] STATus for RX transfer */
#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */ #define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */ #define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */ #define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */ #define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */ #define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */ #define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) #define USB_EPRX_DTOGMASK (USB_EPRX_STAT | USB_EPREG_MASK)
/******************* Bit definition for USB_EP0R register *******************/ /******************* Bit definition for USB_EP0R register *******************/
#define USB_EP0R_EA_Pos (0U) #define USB_EP0R_EA_Pos (0U)
@@ -9601,7 +9529,6 @@ typedef struct
#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* Inter-integrated Circuit Interface */ /* Inter-integrated Circuit Interface */
@@ -10271,23 +10198,20 @@ typedef struct
#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ #define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
/**
* @}
*/
/** /**
* @} * @}
*/ */
/**
* @}
*/
/** @addtogroup Exported_macro /** @addtogroup Exported_macro
* @{ * @{
*/ */
/****************************** ADC Instances *********************************/ /****************************** ADC Instances *********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || ((INSTANCE) == ADC2))
((INSTANCE) == ADC2))
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
@@ -10304,20 +10228,12 @@ typedef struct
/****************************** DAC Instances *********************************/ /****************************** DAC Instances *********************************/
/****************************** DMA Instances *********************************/ /****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ #define IS_DMA_ALL_INSTANCE(INSTANCE) \
((INSTANCE) == DMA1_Channel2) || \ (((INSTANCE) == DMA1_Channel1) || ((INSTANCE) == DMA1_Channel2) || ((INSTANCE) == DMA1_Channel3) || ((INSTANCE) == DMA1_Channel4) || ((INSTANCE) == DMA1_Channel5) || ((INSTANCE) == DMA1_Channel6) \
((INSTANCE) == DMA1_Channel3) || \ || ((INSTANCE) == DMA1_Channel7))
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5) || \
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA1_Channel7))
/******************************* GPIO Instances *******************************/ /******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE))
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE))
/**************************** GPIO Alternate Function Instances ***************/ /**************************** GPIO Alternate Function Instances ***************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
@@ -10326,8 +10242,7 @@ typedef struct
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/ /******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2))
((INSTANCE) == I2C2))
/******************************* SMBUS Instances ******************************/ /******************************* SMBUS Instances ******************************/
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
@@ -10336,228 +10251,100 @@ typedef struct
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/******************************** SPI Instances *******************************/ /******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2))
((INSTANCE) == SPI2))
/****************************** START TIM Instances ***************************/ /****************************** START TIM Instances ***************************/
/****************************** TIM Instances *********************************/ /****************************** TIM Instances *********************************/
#define IS_TIM_INSTANCE(INSTANCE)\ #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
#define IS_TIM_CC1_INSTANCE(INSTANCE)\ #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CC2_INSTANCE(INSTANCE)\ #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CC3_INSTANCE(INSTANCE)\ #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CC4_INSTANCE(INSTANCE)\ #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_XOR_INSTANCE(INSTANCE)\ #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_MASTER_INSTANCE(INSTANCE)\ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_BREAK_INSTANCE(INSTANCE)\ #define IS_TIM_BREAK_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
((INSTANCE) == TIM1)
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \ ((((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
(((CHANNEL) == TIM_CHANNEL_1) || \ || (((INSTANCE) == TIM2) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
((CHANNEL) == TIM_CHANNEL_2) || \ || (((INSTANCE) == TIM3) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
((CHANNEL) == TIM_CHANNEL_3) || \ || (((INSTANCE) == TIM4) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))))
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3)))
(((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3)))
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
((INSTANCE) == TIM1)
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_DMA_INSTANCE(INSTANCE)\ #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
((INSTANCE) == TIM1)
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/ /****************************** END TIM Instances *****************************/
/******************** USART Instances : Synchronous mode **********************/ /******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Asynchronous mode **********************/ /******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Half-Duplex mode **********************/ /******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : LIN mode **********************/ /******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************** UART Instances : Hardware Flow control ********************/ /****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/********************* UART Instances : Smard card mode ***********************/ /********************* UART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/*********************** UART Instances : IRDA mode ***************************/ /*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/***************** UART Instances : Multi-Processor mode **********************/ /***************** UART Instances : Multi-Processor mode **********************/
#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/***************** UART Instances : DMA mode available **********************/ /***************** UART Instances : DMA mode available **********************/
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************************** RTC Instances *********************************/ /****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -10568,8 +10355,6 @@ typedef struct
/****************************** USB Instances ********************************/ /****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
#define RCC_HSE_MIN 4000000U #define RCC_HSE_MIN 4000000U
#define RCC_HSE_MAX 16000000U #define RCC_HSE_MAX 16000000U
@@ -10604,7 +10389,6 @@ typedef struct
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
/* Aliases for __IRQHandler */ /* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler #define ADC1_IRQHandler ADC1_2_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM9_IRQHandler TIM1_BRK_IRQHandler
@@ -10623,7 +10407,6 @@ typedef struct
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
/** /**
* @} * @}
*/ */
@@ -10632,13 +10415,10 @@ typedef struct
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */
#endif /* __STM32F103xB_H */ #endif /* __STM32F103xB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

104
source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h vendored
View File

@@ -57,7 +57,7 @@
#define __STM32F1XX_H #define __STM32F1XX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif /* __cplusplus */ #endif /* __cplusplus */
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
@@ -67,7 +67,7 @@
/** /**
* @brief STM32 Family * @brief STM32 Family
*/ */
#if !defined (STM32F1) #if !defined(STM32F1)
#define STM32F1 #define STM32F1
#endif /* STM32F1 */ #endif /* STM32F1 */
@@ -75,36 +75,35 @@
application application
*/ */
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ #if !defined(STM32F100xB) && !defined(STM32F100xE) && !defined(STM32F101x6) && !defined(STM32F101xB) && !defined(STM32F101xE) && !defined(STM32F101xG) && !defined(STM32F102x6) \
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ && !defined(STM32F102xB) && !defined(STM32F103x6) && !defined(STM32F103xB) && !defined(STM32F103xE) && !defined(STM32F103xG) && !defined(STM32F105xC) && !defined(STM32F107xC)
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor. devices, you can define the device in your toolchain compiler preprocessor.
*/ */
#if !defined (USE_HAL_DRIVER) #if !defined(USE_HAL_DRIVER)
/** /**
* @brief Comment the line below if you will not use the peripherals drivers. * @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
/*#define USE_HAL_DRIVER */ /*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
@@ -114,10 +113,7 @@
#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) | (__STM32F1_CMSIS_VERSION_SUB1 << 16) | (__STM32F1_CMSIS_VERSION_SUB2 << 8) | (__STM32F1_CMSIS_VERSION_RC))
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
/** /**
* @} * @}
@@ -128,35 +124,35 @@
*/ */
#if defined(STM32F100xB) #if defined(STM32F100xB)
#include "stm32f100xb.h" #include "stm32f100xb.h"
#elif defined(STM32F100xE) #elif defined(STM32F100xE)
#include "stm32f100xe.h" #include "stm32f100xe.h"
#elif defined(STM32F101x6) #elif defined(STM32F101x6)
#include "stm32f101x6.h" #include "stm32f101x6.h"
#elif defined(STM32F101xB) #elif defined(STM32F101xB)
#include "stm32f101xb.h" #include "stm32f101xb.h"
#elif defined(STM32F101xE) #elif defined(STM32F101xE)
#include "stm32f101xe.h" #include "stm32f101xe.h"
#elif defined(STM32F101xG) #elif defined(STM32F101xG)
#include "stm32f101xg.h" #include "stm32f101xg.h"
#elif defined(STM32F102x6) #elif defined(STM32F102x6)
#include "stm32f102x6.h" #include "stm32f102x6.h"
#elif defined(STM32F102xB) #elif defined(STM32F102xB)
#include "stm32f102xb.h" #include "stm32f102xb.h"
#elif defined(STM32F103x6) #elif defined(STM32F103x6)
#include "stm32f103x6.h" #include "stm32f103x6.h"
#elif defined(STM32F103xB) #elif defined(STM32F103xB)
#include "stm32f103xb.h" #include "stm32f103xb.h"
#elif defined(STM32F103xE) #elif defined(STM32F103xE)
#include "stm32f103xe.h" #include "stm32f103xe.h"
#elif defined(STM32F103xG) #elif defined(STM32F103xG)
#include "stm32f103xg.h" #include "stm32f103xg.h"
#elif defined(STM32F105xC) #elif defined(STM32F105xC)
#include "stm32f105xc.h" #include "stm32f105xc.h"
#elif defined(STM32F107xC) #elif defined(STM32F107xC)
#include "stm32f107xc.h" #include "stm32f107xc.h"
#else #else
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
#endif #endif
/** /**
@@ -166,30 +162,17 @@
/** @addtogroup Exported_types /** @addtogroup Exported_types
* @{ * @{
*/ */
typedef enum typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState;
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrorStatus;
{
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
/** /**
* @} * @}
*/ */
/** @addtogroup Exported_macros /** @addtogroup Exported_macros
* @{ * @{
*/ */
@@ -209,16 +192,14 @@ typedef enum
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/** /**
* @} * @}
*/ */
#if defined (USE_HAL_DRIVER) #if defined(USE_HAL_DRIVER)
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */
@@ -232,7 +213,4 @@ typedef enum
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

3
source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h vendored
View File

@@ -50,7 +50,7 @@
#define __SYSTEM_STM32F10X_H #define __SYSTEM_STM32F10X_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** @addtogroup STM32F10x_System_Includes /** @addtogroup STM32F10x_System_Includes
@@ -61,7 +61,6 @@
* @} * @}
*/ */
/** @addtogroup STM32F10x_System_Exported_types /** @addtogroup STM32F10x_System_Exported_types
* @{ * @{
*/ */

103
source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_common_tables.h vendored
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@@ -1,42 +1,42 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
* *
* $Date: 19. October 2015 * $Date: 19. October 2015
* $Revision: V.1.4.5 a * $Revision: V.1.4.5 a
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_common_tables.h * Title: arm_common_tables.h
* *
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
* *
* Target Processor: Cortex-M4/Cortex-M3 * Target Processor: Cortex-M4/Cortex-M3
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
* are met: * are met:
* - Redistributions of source code must retain the above copyright * - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer. * notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright * - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in * notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the * the documentation and/or other materials provided with the
* distribution. * distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors * - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this * may be used to endorse or promote products derived from this
* software without specific prior written permission. * software without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H #ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H #define _ARM_COMMON_TABLES_H
@@ -85,14 +85,13 @@ extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048]; extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096]; extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */ /* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) #define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
@@ -108,13 +107,13 @@ extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENG
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */ /* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) #define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) #define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) #define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) #define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) #define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) #define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)

136
source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_const_structs.h vendored
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@@ -1,79 +1,79 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
* *
* $Date: 19. March 2015 * $Date: 19. March 2015
* $Revision: V.1.4.5 * $Revision: V.1.4.5
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_const_structs.h * Title: arm_const_structs.h
* *
* Description: This file has constant structs that are initialized for * Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as * user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function. * arguments to the arm_cfft_f32() function.
* *
* Target Processor: Cortex-M4/Cortex-M3 * Target Processor: Cortex-M4/Cortex-M3
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
* are met: * are met:
* - Redistributions of source code must retain the above copyright * - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer. * notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright * - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in * notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the * the documentation and/or other materials provided with the
* distribution. * distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors * - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this * may be used to endorse or promote products derived from this
* software without specific prior written permission. * software without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H #ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H #define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h" #include "arm_common_tables.h"
#include "arm_math.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif #endif

4391
source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_math.h vendored
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File diff suppressed because it is too large Load Diff

225
source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_armcc.h vendored
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@@ -1,4 +1,4 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file cmsis_armcc.h * @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File * @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30 * @version V4.30
@@ -31,13 +31,11 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H #ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!" #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif #endif
/* ########################### Core Function Access ########################### */ /* ########################### Core Function Access ########################### */
@@ -54,133 +52,111 @@
\details Returns the content of the Control Register. \details Returns the content of the Control Register.
\return Control Register value \return Control Register value
*/ */
__STATIC_INLINE uint32_t __get_CONTROL(void) __STATIC_INLINE uint32_t __get_CONTROL(void) {
{
register uint32_t __regControl __ASM("control"); register uint32_t __regControl __ASM("control");
return(__regControl); return (__regControl);
} }
/** /**
\brief Set Control Register \brief Set Control Register
\details Writes the given value to the Control Register. \details Writes the given value to the Control Register.
\param [in] control Control Register value to set \param [in] control Control Register value to set
*/ */
__STATIC_INLINE void __set_CONTROL(uint32_t control) __STATIC_INLINE void __set_CONTROL(uint32_t control) {
{
register uint32_t __regControl __ASM("control"); register uint32_t __regControl __ASM("control");
__regControl = control; __regControl = control;
} }
/** /**
\brief Get IPSR Register \brief Get IPSR Register
\details Returns the content of the IPSR Register. \details Returns the content of the IPSR Register.
\return IPSR Register value \return IPSR Register value
*/ */
__STATIC_INLINE uint32_t __get_IPSR(void) __STATIC_INLINE uint32_t __get_IPSR(void) {
{
register uint32_t __regIPSR __ASM("ipsr"); register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR); return (__regIPSR);
} }
/** /**
\brief Get APSR Register \brief Get APSR Register
\details Returns the content of the APSR Register. \details Returns the content of the APSR Register.
\return APSR Register value \return APSR Register value
*/ */
__STATIC_INLINE uint32_t __get_APSR(void) __STATIC_INLINE uint32_t __get_APSR(void) {
{
register uint32_t __regAPSR __ASM("apsr"); register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR); return (__regAPSR);
} }
/** /**
\brief Get xPSR Register \brief Get xPSR Register
\details Returns the content of the xPSR Register. \details Returns the content of the xPSR Register.
\return xPSR Register value \return xPSR Register value
*/ */
__STATIC_INLINE uint32_t __get_xPSR(void) __STATIC_INLINE uint32_t __get_xPSR(void) {
{
register uint32_t __regXPSR __ASM("xpsr"); register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR); return (__regXPSR);
} }
/** /**
\brief Get Process Stack Pointer \brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP). \details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value \return PSP Register value
*/ */
__STATIC_INLINE uint32_t __get_PSP(void) __STATIC_INLINE uint32_t __get_PSP(void) {
{
register uint32_t __regProcessStackPointer __ASM("psp"); register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer); return (__regProcessStackPointer);
} }
/** /**
\brief Set Process Stack Pointer \brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP). \details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set \param [in] topOfProcStack Process Stack Pointer value to set
*/ */
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) {
{
register uint32_t __regProcessStackPointer __ASM("psp"); register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack; __regProcessStackPointer = topOfProcStack;
} }
/** /**
\brief Get Main Stack Pointer \brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP). \details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value \return MSP Register value
*/ */
__STATIC_INLINE uint32_t __get_MSP(void) __STATIC_INLINE uint32_t __get_MSP(void) {
{
register uint32_t __regMainStackPointer __ASM("msp"); register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer); return (__regMainStackPointer);
} }
/** /**
\brief Set Main Stack Pointer \brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP). \details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set \param [in] topOfMainStack Main Stack Pointer value to set
*/ */
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) {
{
register uint32_t __regMainStackPointer __ASM("msp"); register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack; __regMainStackPointer = topOfMainStack;
} }
/** /**
\brief Get Priority Mask \brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register. \details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value \return Priority Mask value
*/ */
__STATIC_INLINE uint32_t __get_PRIMASK(void) __STATIC_INLINE uint32_t __get_PRIMASK(void) {
{
register uint32_t __regPriMask __ASM("primask"); register uint32_t __regPriMask __ASM("primask");
return(__regPriMask); return (__regPriMask);
} }
/** /**
\brief Set Priority Mask \brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register. \details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask \param [in] priMask Priority Mask
*/ */
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) {
{
register uint32_t __regPriMask __ASM("primask"); register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask); __regPriMask = (priMask);
} }
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/** /**
@@ -190,7 +166,6 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
*/ */
#define __enable_fault_irq __enable_fiq #define __enable_fault_irq __enable_fiq
/** /**
\brief Disable FIQ \brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR. \details Disables FIQ interrupts by setting the F-bit in the CPSR.
@@ -198,70 +173,59 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
*/ */
#define __disable_fault_irq __disable_fiq #define __disable_fault_irq __disable_fiq
/** /**
\brief Get Base Priority \brief Get Base Priority
\details Returns the current value of the Base Priority register. \details Returns the current value of the Base Priority register.
\return Base Priority register value \return Base Priority register value
*/ */
__STATIC_INLINE uint32_t __get_BASEPRI(void) __STATIC_INLINE uint32_t __get_BASEPRI(void) {
{
register uint32_t __regBasePri __ASM("basepri"); register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri); return (__regBasePri);
} }
/** /**
\brief Set Base Priority \brief Set Base Priority
\details Assigns the given value to the Base Priority register. \details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set \param [in] basePri Base Priority value to set
*/ */
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) {
{
register uint32_t __regBasePri __ASM("basepri"); register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU); __regBasePri = (basePri & 0xFFU);
} }
/** /**
\brief Set Base Priority with condition \brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level. or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set \param [in] basePri Base Priority value to set
*/ */
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) {
{
register uint32_t __regBasePriMax __ASM("basepri_max"); register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU); __regBasePriMax = (basePri & 0xFFU);
} }
/** /**
\brief Get Fault Mask \brief Get Fault Mask
\details Returns the current value of the Fault Mask register. \details Returns the current value of the Fault Mask register.
\return Fault Mask register value \return Fault Mask register value
*/ */
__STATIC_INLINE uint32_t __get_FAULTMASK(void) __STATIC_INLINE uint32_t __get_FAULTMASK(void) {
{
register uint32_t __regFaultMask __ASM("faultmask"); register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask); return (__regFaultMask);
} }
/** /**
\brief Set Fault Mask \brief Set Fault Mask
\details Assigns the given value to the Fault Mask register. \details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set \param [in] faultMask Fault Mask value to set
*/ */
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) {
{
register uint32_t __regFaultMask __ASM("faultmask"); register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1); __regFaultMask = (faultMask & (uint32_t)1);
} }
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/** /**
@@ -269,24 +233,21 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
\details Returns the current value of the Floating Point Status/Control register. \details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value \return Floating Point Status/Control register value
*/ */
__STATIC_INLINE uint32_t __get_FPSCR(void) __STATIC_INLINE uint32_t __get_FPSCR(void) {
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr"); register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr); return (__regfpscr);
#else #else
return(0U); return (0U);
#endif #endif
} }
/** /**
\brief Set FPSCR \brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register. \details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set \param [in] fpscr Floating Point Status/Control value to set
*/ */
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) {
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr"); register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr); __regfpscr = (fpscr);
@@ -295,11 +256,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */ /*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */ /* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions Access to dedicated instructions
@@ -312,14 +270,12 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/ */
#define __NOP __nop #define __NOP __nop
/** /**
\brief Wait For Interrupt \brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/ */
#define __WFI __wfi #define __WFI __wfi
/** /**
\brief Wait For Event \brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter \details Wait For Event is a hint instruction that permits the processor to enter
@@ -327,24 +283,23 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/ */
#define __WFE __wfe #define __WFE __wfe
/** /**
\brief Send Event \brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU. \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/ */
#define __SEV __sev #define __SEV __sev
/** /**
\brief Instruction Synchronization Barrier \brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor, \details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory, so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed. after the instruction has been completed.
*/ */
#define __ISB() do {\ #define __ISB() \
__schedule_barrier();\ do { \
__isb(0xF);\ __schedule_barrier(); \
__schedule_barrier();\ __isb(0xF); \
__schedule_barrier(); \
} while (0U) } while (0U)
/** /**
@@ -352,10 +307,11 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\details Acts as a special kind of Data Memory Barrier. \details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete. It completes when all explicit memory accesses before this instruction complete.
*/ */
#define __DSB() do {\ #define __DSB() \
__schedule_barrier();\ do { \
__dsb(0xF);\ __schedule_barrier(); \
__schedule_barrier();\ __dsb(0xF); \
__schedule_barrier(); \
} while (0U) } while (0U)
/** /**
@@ -363,10 +319,11 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\details Ensures the apparent order of the explicit memory operations before \details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion. and after the instruction, without ensuring their completion.
*/ */
#define __DMB() do {\ #define __DMB() \
__schedule_barrier();\ do { \
__dmb(0xF);\ __schedule_barrier(); \
__schedule_barrier();\ __dmb(0xF); \
__schedule_barrier(); \
} while (0U) } while (0U)
/** /**
@@ -377,7 +334,6 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/ */
#define __REV __rev #define __REV __rev
/** /**
\brief Reverse byte order (16 bit) \brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values. \details Reverses the byte order in two unsigned short values.
@@ -385,11 +341,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\return Reversed value \return Reversed value
*/ */
#ifndef __NO_EMBEDDED_ASM #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr }
{
rev16 r0, r0
bx lr
}
#endif #endif
/** /**
@@ -399,14 +351,9 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
\return Reversed value \return Reversed value
*/ */
#ifndef __NO_EMBEDDED_ASM #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr }
{
revsh r0, r0
bx lr
}
#endif #endif
/** /**
\brief Rotate Right in unsigned value (32 bit) \brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@@ -416,7 +363,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
*/ */
#define __ROR __ror #define __ROR __ror
/** /**
\brief Breakpoint \brief Breakpoint
\details Causes the processor to enter Debug state. \details Causes the processor to enter Debug state.
@@ -426,7 +372,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
*/ */
#define __BKPT(value) __breakpoint(value) #define __BKPT(value) __breakpoint(value)
/** /**
\brief Reverse bit order of value \brief Reverse bit order of value
\details Reverses the bit order of the given value. \details Reverses the bit order of the given value.
@@ -434,26 +379,23 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\return Reversed value \return Reversed value
*/ */
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit #define __RBIT __rbit
#else #else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
{
uint32_t result; uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */ result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) for (value >>= 1U; value; value >>= 1U) {
{
result <<= 1U; result <<= 1U;
result |= value & 1U; result |= value & 1U;
s--; s--;
} }
result <<= s; /* shift when v's highest bits are zero */ result <<= s; /* shift when v's highest bits are zero */
return(result); return (result);
} }
#endif #endif
/** /**
\brief Count leading zeros \brief Count leading zeros
\details Counts the number of leading zeros of a data value. \details Counts the number of leading zeros of a data value.
@@ -462,7 +404,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
*/ */
#define __CLZ __clz #define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/** /**
@@ -472,12 +413,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return value of type uint8_t at (*ptr) \return value of type uint8_t at (*ptr)
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) #define __LDREXB(ptr) ((uint8_t)__ldrex(ptr))
#else #else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop")
#endif #endif
/** /**
\brief LDR Exclusive (16 bit) \brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values. \details Executes a exclusive LDR instruction for 16 bit values.
@@ -485,12 +425,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return value of type uint16_t at (*ptr) \return value of type uint16_t at (*ptr)
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) #define __LDREXH(ptr) ((uint16_t)__ldrex(ptr))
#else #else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop")
#endif #endif
/** /**
\brief LDR Exclusive (32 bit) \brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values. \details Executes a exclusive LDR instruction for 32 bit values.
@@ -498,12 +437,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return value of type uint32_t at (*ptr) \return value of type uint32_t at (*ptr)
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) #define __LDREXW(ptr) ((uint32_t)__ldrex(ptr))
#else #else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop")
#endif #endif
/** /**
\brief STR Exclusive (8 bit) \brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values. \details Executes a exclusive STR instruction for 8 bit values.
@@ -513,12 +451,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return 1 Function failed \return 1 Function failed
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr) #define __STREXB(value, ptr) __strex(value, ptr)
#else #else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif #endif
/** /**
\brief STR Exclusive (16 bit) \brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values. \details Executes a exclusive STR instruction for 16 bit values.
@@ -528,12 +465,11 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return 1 Function failed \return 1 Function failed
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr) #define __STREXH(value, ptr) __strex(value, ptr)
#else #else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif #endif
/** /**
\brief STR Exclusive (32 bit) \brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values. \details Executes a exclusive STR instruction for 32 bit values.
@@ -543,19 +479,17 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return 1 Function failed \return 1 Function failed
*/ */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr) #define __STREXW(value, ptr) __strex(value, ptr)
#else #else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif #endif
/** /**
\brief Remove the exclusive lock \brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX. \details Removes the exclusive lock which is created by LDREX.
*/ */
#define __CLREX __clrex #define __CLREX __clrex
/** /**
\brief Signed Saturate \brief Signed Saturate
\details Saturates a signed value. \details Saturates a signed value.
@@ -565,7 +499,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
*/ */
#define __SSAT __ssat #define __SSAT __ssat
/** /**
\brief Unsigned Saturate \brief Unsigned Saturate
\details Saturates an unsigned value. \details Saturates an unsigned value.
@@ -575,7 +508,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
*/ */
#define __USAT __usat #define __USAT __usat
/** /**
\brief Rotate Right with Extend (32 bit) \brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit. \details Moves each bit of a bitstring right by one bit.
@@ -584,22 +516,16 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return Rotated value \return Rotated value
*/ */
#ifndef __NO_EMBEDDED_ASM #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr }
{
rrx r0, r0
bx lr
}
#endif #endif
/** /**
\brief LDRT Unprivileged (8 bit) \brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value. \details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data \param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr) \return value of type uint8_t at (*ptr)
*/ */
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) #define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
/** /**
\brief LDRT Unprivileged (16 bit) \brief LDRT Unprivileged (16 bit)
@@ -607,8 +533,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] ptr Pointer to data \param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr) \return value of type uint16_t at (*ptr)
*/ */
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) #define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
/** /**
\brief LDRT Unprivileged (32 bit) \brief LDRT Unprivileged (32 bit)
@@ -616,8 +541,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] ptr Pointer to data \param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr) \return value of type uint32_t at (*ptr)
*/ */
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) #define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
/** /**
\brief STRT Unprivileged (8 bit) \brief STRT Unprivileged (8 bit)
@@ -627,7 +551,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/ */
#define __STRBT(value, ptr) __strt(value, ptr) #define __STRBT(value, ptr) __strt(value, ptr)
/** /**
\brief STRT Unprivileged (16 bit) \brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values. \details Executes a Unprivileged STRT instruction for 16 bit values.
@@ -636,7 +559,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/ */
#define __STRHT(value, ptr) __strt(value, ptr) #define __STRHT(value, ptr) __strt(value, ptr)
/** /**
\brief STRT Unprivileged (32 bit) \brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values. \details Executes a Unprivileged STRT instruction for 32 bit values.
@@ -649,7 +571,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */ /* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions Access to dedicated SIMD instructions
@@ -718,17 +639,13 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
#define __QADD __qadd #define __QADD __qadd
#define __QSUB __qsub #define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ #define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ #define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ #define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U)) >> 32U))
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */ #endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */ /*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */ #endif /* __CMSIS_ARMCC_H */

983
source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_armcc_V6.h vendored
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File diff suppressed because it is too large Load Diff

846
source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_gcc.h vendored
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File diff suppressed because it is too large Load Diff

347
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0.h vendored
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@@ -1,4 +1,4 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_cm0.h * @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.30 * @version V4.30
@@ -31,11 +31,10 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CM0_H_GENERIC #ifndef __CORE_CM0_H_GENERIC
@@ -44,7 +43,7 @@
#include <stdint.h> #include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** /**
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,49 +71,47 @@
/* CMSIS CM0 definitions */ /* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ #define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined(__CC_ARM)
#if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline #define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#define __packed #define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#else #else
#error Unknown compiler #error Unknown compiler
#endif #endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
@@ -123,45 +119,45 @@
*/ */
#define __FPU_USED 0U #define __FPU_USED 0U
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP #if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#if defined __ARMVFP__ #if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#if defined __FPU_VFP__ #if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#if ( __CSMC__ & 0x400U) #if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -175,25 +171,25 @@
#define __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* check device defines and use defaults */ /* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES #if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV #ifndef __CM0_REV
#define __CM0_REV 0x0000U #define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!" #warning "__CM0_REV not defined in device header file; using default!"
#endif #endif
#ifndef __NVIC_PRIO_BITS #ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U #define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif #endif
#ifndef __Vendor_SysTickConfig #ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U #define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif #endif
#endif #endif
/* IO definitions (access restrictions to peripheral registers) */ /* IO definitions (access restrictions to peripheral registers) */
@@ -205,9 +201,9 @@
\li for automatic generation of peripheral register debug information. \li for automatic generation of peripheral register debug information.
*/ */
#ifdef __cplusplus #ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */ #define __I volatile /*!< Defines 'read only' permissions */
#else #else
#define __I volatile const /*!< Defines 'read only' permissions */ #define __I volatile const /*!< Defines 'read only' permissions */
#endif #endif
#define __O volatile /*!< Defines 'write only' permissions */ #define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */
@@ -219,8 +215,6 @@
/*@} end of group Cortex_M0 */ /*@} end of group Cortex_M0 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -244,15 +238,13 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */
{ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} APSR_Type; } APSR_Type;
@@ -270,16 +262,13 @@ typedef union
#define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} IPSR_Type; } IPSR_Type;
@@ -288,22 +277,19 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t _reserved1 : 3; /*!< bit: 25..27 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} xPSR_Type; } xPSR_Type;
@@ -327,17 +313,14 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */
{ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} CONTROL_Type; } CONTROL_Type;
@@ -348,7 +331,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -359,8 +341,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U]; uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -375,7 +356,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -386,8 +366,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0; uint32_t RESERVED0;
@@ -482,7 +461,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -493,8 +471,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -534,7 +511,6 @@ typedef struct
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -544,7 +520,6 @@ typedef struct
*/ */
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -558,7 +533,7 @@ typedef struct
\param[in] value Value of the bit field. \param[in] value Value of the bit field.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
@@ -566,11 +541,10 @@ typedef struct
\param[in] value Value of register. \param[in] value Value of register.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -584,15 +558,12 @@ typedef struct
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -604,8 +575,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -616,32 +585,23 @@ typedef struct
/* Interrupt Priorities are WORD accessible only under ARMv6M */ /* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */ /* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -650,33 +610,21 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -685,21 +633,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0) SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
{ } else {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -709,33 +650,26 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{ return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else {
} return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */ for (;;) /* wait until reset */
{ {
__NOP(); __NOP();
} }
@@ -743,8 +677,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -766,19 +698,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -786,9 +714,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

369
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0plus.h vendored
View File

@@ -1,4 +1,4 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_cm0plus.h * @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.30 * @version V4.30
@@ -31,11 +31,10 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CM0PLUS_H_GENERIC #ifndef __CORE_CM0PLUS_H_GENERIC
@@ -44,7 +43,7 @@
#include <stdint.h> #include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** /**
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,49 +71,47 @@
/* CMSIS CM0+ definitions */ /* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ #define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined(__CC_ARM)
#if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline #define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#define __packed #define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#else #else
#error Unknown compiler #error Unknown compiler
#endif #endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
@@ -123,45 +119,45 @@
*/ */
#define __FPU_USED 0U #define __FPU_USED 0U
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP #if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#if defined __ARMVFP__ #if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#if defined __FPU_VFP__ #if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#if ( __CSMC__ & 0x400U) #if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -175,35 +171,35 @@
#define __CORE_CM0PLUS_H_DEPENDANT #define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* check device defines and use defaults */ /* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES #if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV #ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U #define __CM0PLUS_REV 0x0000U
#warning "__CM0PLUS_REV not defined in device header file; using default!" #warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif #endif
#ifndef __MPU_PRESENT #ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U #define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!" #warning "__MPU_PRESENT not defined in device header file; using default!"
#endif #endif
#ifndef __VTOR_PRESENT #ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U #define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!" #warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif #endif
#ifndef __NVIC_PRIO_BITS #ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U #define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif #endif
#ifndef __Vendor_SysTickConfig #ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U #define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif #endif
#endif #endif
/* IO definitions (access restrictions to peripheral registers) */ /* IO definitions (access restrictions to peripheral registers) */
@@ -215,9 +211,9 @@
\li for automatic generation of peripheral register debug information. \li for automatic generation of peripheral register debug information.
*/ */
#ifdef __cplusplus #ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */ #define __I volatile /*!< Defines 'read only' permissions */
#else #else
#define __I volatile const /*!< Defines 'read only' permissions */ #define __I volatile const /*!< Defines 'read only' permissions */
#endif #endif
#define __O volatile /*!< Defines 'write only' permissions */ #define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */
@@ -229,8 +225,6 @@
/*@} end of group Cortex-M0+ */ /*@} end of group Cortex-M0+ */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -255,15 +249,13 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */
{ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} APSR_Type; } APSR_Type;
@@ -281,16 +273,13 @@ typedef union
#define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} IPSR_Type; } IPSR_Type;
@@ -299,22 +288,19 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t _reserved1 : 3; /*!< bit: 25..27 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} xPSR_Type; } xPSR_Type;
@@ -338,17 +324,14 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
{ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} CONTROL_Type; } CONTROL_Type;
@@ -362,7 +345,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -373,8 +355,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U]; uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -389,7 +370,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -400,8 +380,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1U) #if (__VTOR_PRESENT == 1U)
@@ -506,7 +485,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -517,8 +495,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -569,8 +546,7 @@ typedef struct
/** /**
\brief Structure type to access the Memory Protection Unit (MPU). \brief Structure type to access the Memory Protection Unit (MPU).
*/ */
typedef struct typedef struct {
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -646,7 +622,6 @@ typedef struct
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -656,7 +631,6 @@ typedef struct
*/ */
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -670,7 +644,7 @@ typedef struct
\param[in] value Value of the bit field. \param[in] value Value of the bit field.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
@@ -678,11 +652,10 @@ typedef struct
\param[in] value Value of register. \param[in] value Value of register.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -696,19 +669,17 @@ typedef struct
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif #endif
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -720,8 +691,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -732,32 +701,23 @@ typedef struct
/* Interrupt Priorities are WORD accessible only under ARMv6M */ /* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */ /* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -766,33 +726,21 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -801,21 +749,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0) SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
{ } else {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -825,33 +766,26 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{ return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else {
} return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */ for (;;) /* wait until reset */
{ {
__NOP(); __NOP();
} }
@@ -859,8 +793,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -882,19 +814,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -902,9 +830,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

454
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm3.h vendored
View File

@@ -1,4 +1,4 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_cm3.h * @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V4.30 * @version V4.30
@@ -31,11 +31,10 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CM3_H_GENERIC #ifndef __CORE_CM3_H_GENERIC
@@ -44,7 +43,7 @@
#include <stdint.h> #include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** /**
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,49 +71,47 @@
/* CMSIS CM3 definitions */ /* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ #define __CORTEX_M (0x03U) /*!< Cortex-M Core */
#if defined(__CC_ARM)
#if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline #define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#define __packed #define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#else #else
#error Unknown compiler #error Unknown compiler
#endif #endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
@@ -123,45 +119,45 @@
*/ */
#define __FPU_USED 0U #define __FPU_USED 0U
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP #if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#if defined __ARMVFP__ #if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#if defined __FPU_VFP__ #if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#if ( __CSMC__ & 0x400U) #if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -175,30 +171,30 @@
#define __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* check device defines and use defaults */ /* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES #if defined __CHECK_DEVICE_DEFINES
#ifndef __CM3_REV #ifndef __CM3_REV
#define __CM3_REV 0x0200U #define __CM3_REV 0x0200U
#warning "__CM3_REV not defined in device header file; using default!" #warning "__CM3_REV not defined in device header file; using default!"
#endif #endif
#ifndef __MPU_PRESENT #ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U #define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!" #warning "__MPU_PRESENT not defined in device header file; using default!"
#endif #endif
#ifndef __NVIC_PRIO_BITS #ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4U #define __NVIC_PRIO_BITS 4U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif #endif
#ifndef __Vendor_SysTickConfig #ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U #define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif #endif
#endif #endif
/* IO definitions (access restrictions to peripheral registers) */ /* IO definitions (access restrictions to peripheral registers) */
@@ -210,9 +206,9 @@
\li for automatic generation of peripheral register debug information. \li for automatic generation of peripheral register debug information.
*/ */
#ifdef __cplusplus #ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */ #define __I volatile /*!< Defines 'read only' permissions */
#else #else
#define __I volatile const /*!< Defines 'read only' permissions */ #define __I volatile const /*!< Defines 'read only' permissions */
#endif #endif
#define __O volatile /*!< Defines 'write only' permissions */ #define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */
@@ -224,8 +220,6 @@
/*@} end of group Cortex_M3 */ /*@} end of group Cortex_M3 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -251,16 +245,14 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */
{ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} APSR_Type; } APSR_Type;
@@ -281,16 +273,13 @@ typedef union
#define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} IPSR_Type; } IPSR_Type;
@@ -299,23 +288,20 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} xPSR_Type; } xPSR_Type;
@@ -345,17 +331,14 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
{ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} CONTROL_Type; } CONTROL_Type;
@@ -369,7 +352,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -380,8 +362,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U]; uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -403,7 +384,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -414,8 +394,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -630,7 +609,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -641,8 +619,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control and ID Register not in the SCB. \brief Structure type to access the System Control and ID Register not in the SCB.
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0[1U]; uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) #if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
@@ -669,7 +646,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */ /*@} end of group CMSIS_SCnotSCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -680,8 +656,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -721,7 +696,6 @@ typedef struct
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
@@ -732,14 +706,12 @@ typedef struct
/** /**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/ */
typedef struct typedef struct {
{ __OM union {
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U]; uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U]; uint32_t RESERVED1[15U];
@@ -824,7 +796,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_ITM */ /*@}*/ /* end of group CMSIS_ITM */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
@@ -835,8 +806,7 @@ typedef struct
/** /**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT). \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
@@ -971,7 +941,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */ /*@}*/ /* end of group CMSIS_DWT */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI) \defgroup CMSIS_TPI Trace Port Interface (TPI)
@@ -982,8 +951,7 @@ typedef struct
/** /**
\brief Structure type to access the Trace Port Interface Register (TPI). \brief Structure type to access the Trace Port Interface Register (TPI).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
@@ -1126,7 +1094,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_TPI */ /*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
@@ -1138,8 +1105,7 @@ typedef struct
/** /**
\brief Structure type to access the Memory Protection Unit (MPU). \brief Structure type to access the Memory Protection Unit (MPU).
*/ */
typedef struct typedef struct {
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -1221,7 +1187,6 @@ typedef struct
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -1232,8 +1197,7 @@ typedef struct
/** /**
\brief Structure type to access the Core Debug Register (CoreDebug). \brief Structure type to access the Core Debug Register (CoreDebug).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
@@ -1326,7 +1290,6 @@ typedef struct
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -1340,7 +1303,7 @@ typedef struct
\param[in] value Value of the bit field. \param[in] value Value of the bit field.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
@@ -1348,11 +1311,10 @@ typedef struct
\param[in] value Value of register. \param[in] value Value of register.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -1370,24 +1332,22 @@ typedef struct
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif #endif
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -1400,8 +1360,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1419,52 +1377,36 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field. \param [in] PriorityGroup Priority grouping field.
*/ */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
{
uint32_t reg_value; uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */ reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value | reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value; SCB->AIRCR = reg_value;
} }
/** /**
\brief Get Priority Grouping \brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller. \details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -1473,33 +1415,23 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
{ return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Active Interrupt \brief Get Active Interrupt
@@ -1508,11 +1440,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not active. \return 0 Interrupt status is not active.
\return 1 Interrupt status is active. \return 1 Interrupt status is active.
*/ */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -1521,19 +1449,14 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0) SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
{ } else {
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -1543,20 +1466,15 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{ return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } else {
} return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
else
{
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief Encode Priority \brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group, \details Encodes the priority for an interrupt with the given priority group,
@@ -1568,8 +1486,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\param [in] SubPriority Subpriority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/ */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1577,13 +1494,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return ( return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
} }
/** /**
\brief Decode Priority \brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to \details Decodes an interrupt priority value with a given priority group to
@@ -1595,8 +1508,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
\param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0).
*/ */
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1605,24 +1517,20 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */ for (;;) /* wait until reset */
{ {
__NOP(); __NOP();
} }
@@ -1630,8 +1538,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1653,19 +1559,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -1673,8 +1575,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */ /* ##################################### Debug In/Output function ########################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1686,7 +1586,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** /**
\brief ITM Send Character \brief ITM Send Character
\details Transmits a character via the ITM channel 0, and \details Transmits a character via the ITM channel 0, and
@@ -1695,13 +1594,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
\param [in] ch Character to transmit. \param [in] ch Character to transmit.
\returns Character to transmit. \returns Character to transmit.
*/ */
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{ {
while (ITM->PORT[0U].u32 == 0UL) {
__NOP(); __NOP();
} }
ITM->PORT[0U].u8 = (uint8_t)ch; ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -1709,19 +1606,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
return (ch); return (ch);
} }
/** /**
\brief ITM Receive Character \brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer. \details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character. \return Received character.
\return -1 No character pending. \return -1 No character pending.
*/ */
__STATIC_INLINE int32_t ITM_ReceiveChar (void) __STATIC_INLINE int32_t ITM_ReceiveChar(void) {
{
int32_t ch = -1; /* no character available */ int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
{
ch = ITM_RxBuffer; ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
} }
@@ -1729,31 +1623,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
return (ch); return (ch);
} }
/** /**
\brief ITM Check Character \brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available. \return 0 No character available.
\return 1 Character available. \return 1 Character available.
*/ */
__STATIC_INLINE int32_t ITM_CheckChar (void) __STATIC_INLINE int32_t ITM_CheckChar(void) {
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
{
return (0); /* no character available */ return (0); /* no character available */
} } else {
else
{
return (1); /* character available */ return (1); /* character available */
} }
} }
/*@} end of CMSIS_core_DebugFunctions */ /*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

578
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm4.h vendored
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File diff suppressed because it is too large Load Diff

762
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm7.h vendored
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File diff suppressed because it is too large Load Diff

36
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmFunc.h vendored
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@@ -1,4 +1,4 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_cmFunc.h * @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File * @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30 * @version V4.30
@@ -31,17 +31,15 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CMFUNC_H #ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H #define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */ /* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface /** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@@ -49,36 +47,36 @@
*/ */
/*------------------ RealView Compiler -----------------*/ /*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#include "cmsis_armcc.h" #include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/ /*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h" #include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/ /*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#include "cmsis_gcc.h" #include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/ /*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#include <cmsis_iar.h> #include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/ /*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/ /*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
/*------------------ COSMIC Compiler -------------------*/ /*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#include <cmsis_csm.h> #include <cmsis_csm.h>
#endif #endif

36
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmInstr.h vendored
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@@ -1,4 +1,4 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_cmInstr.h * @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File * @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30 * @version V4.30
@@ -31,17 +31,15 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CMINSTR_H #ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H #define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */ /* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions Access to dedicated instructions
@@ -49,36 +47,36 @@
*/ */
/*------------------ RealView Compiler -----------------*/ /*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#include "cmsis_armcc.h" #include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/ /*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h" #include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/ /*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#include "cmsis_gcc.h" #include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/ /*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#include <cmsis_iar.h> #include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/ /*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/ /*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
/*------------------ COSMIC Compiler -------------------*/ /*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#include <cmsis_csm.h> #include <cmsis_csm.h>
#endif #endif

39
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmSimd.h vendored
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@@ -1,4 +1,4 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_cmSimd.h * @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File * @brief CMSIS Cortex-M SIMD Header File
* @version V4.30 * @version V4.30
@@ -31,21 +31,19 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_CMSIMD_H #ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H #define __CORE_CMSIMD_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ################### Compiler specific Intrinsics ########################### */ /* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions Access to dedicated SIMD instructions
@@ -53,42 +51,41 @@
*/ */
/*------------------ RealView Compiler -----------------*/ /*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#include "cmsis_armcc.h" #include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/ /*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h" #include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/ /*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#include "cmsis_gcc.h" #include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/ /*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#include <cmsis_iar.h> #include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/ /*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/ /*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
/*------------------ COSMIC Compiler -------------------*/ /*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#include <cmsis_csm.h> #include <cmsis_csm.h>
#endif #endif
/*@} end of group CMSIS_SIMD_intrinsics */ /*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

367
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_sc000.h vendored
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@@ -1,4 +1,4 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_sc000.h * @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File * @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V4.30 * @version V4.30
@@ -31,11 +31,10 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_SC000_H_GENERIC #ifndef __CORE_SC000_H_GENERIC
@@ -44,7 +43,7 @@
#include <stdint.h> #include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** /**
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,49 +71,47 @@
/* CMSIS SC000 definitions */ /* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | __SC000_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_SC (000U) /*!< Cortex secure core */ #define __CORTEX_SC (000U) /*!< Cortex secure core */
#if defined(__CC_ARM)
#if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline #define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#define __packed #define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#else #else
#error Unknown compiler #error Unknown compiler
#endif #endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
@@ -123,45 +119,45 @@
*/ */
#define __FPU_USED 0U #define __FPU_USED 0U
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP #if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#if defined __ARMVFP__ #if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#if defined __FPU_VFP__ #if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#if ( __CSMC__ & 0x400U) #if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -175,30 +171,30 @@
#define __CORE_SC000_H_DEPENDANT #define __CORE_SC000_H_DEPENDANT
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* check device defines and use defaults */ /* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES #if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV #ifndef __SC000_REV
#define __SC000_REV 0x0000U #define __SC000_REV 0x0000U
#warning "__SC000_REV not defined in device header file; using default!" #warning "__SC000_REV not defined in device header file; using default!"
#endif #endif
#ifndef __MPU_PRESENT #ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U #define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!" #warning "__MPU_PRESENT not defined in device header file; using default!"
#endif #endif
#ifndef __NVIC_PRIO_BITS #ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U #define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif #endif
#ifndef __Vendor_SysTickConfig #ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U #define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif #endif
#endif #endif
/* IO definitions (access restrictions to peripheral registers) */ /* IO definitions (access restrictions to peripheral registers) */
@@ -210,9 +206,9 @@
\li for automatic generation of peripheral register debug information. \li for automatic generation of peripheral register debug information.
*/ */
#ifdef __cplusplus #ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */ #define __I volatile /*!< Defines 'read only' permissions */
#else #else
#define __I volatile const /*!< Defines 'read only' permissions */ #define __I volatile const /*!< Defines 'read only' permissions */
#endif #endif
#define __O volatile /*!< Defines 'write only' permissions */ #define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */
@@ -224,8 +220,6 @@
/*@} end of group SC000 */ /*@} end of group SC000 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -250,15 +244,13 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */
{ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} APSR_Type; } APSR_Type;
@@ -276,16 +268,13 @@ typedef union
#define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} IPSR_Type; } IPSR_Type;
@@ -294,22 +283,19 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t _reserved1 : 3; /*!< bit: 25..27 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} xPSR_Type; } xPSR_Type;
@@ -333,17 +319,14 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */
{ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} CONTROL_Type; } CONTROL_Type;
@@ -354,7 +337,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -365,8 +347,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U]; uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -381,7 +362,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -392,8 +372,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -494,7 +473,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -505,8 +483,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control and ID Register not in the SCB. \brief Structure type to access the System Control and ID Register not in the SCB.
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type; } SCnSCB_Type;
@@ -517,7 +494,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */ /*@} end of group CMSIS_SCnotSCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -528,8 +504,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -580,8 +555,7 @@ typedef struct
/** /**
\brief Structure type to access the Memory Protection Unit (MPU). \brief Structure type to access the Memory Protection Unit (MPU).
*/ */
typedef struct typedef struct {
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -657,7 +631,6 @@ typedef struct
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -667,7 +640,6 @@ typedef struct
*/ */
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -681,7 +653,7 @@ typedef struct
\param[in] value Value of the bit field. \param[in] value Value of the bit field.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
@@ -689,11 +661,10 @@ typedef struct
\param[in] value Value of register. \param[in] value Value of register.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -707,20 +678,18 @@ typedef struct
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif #endif
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -732,8 +701,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -744,32 +711,23 @@ typedef struct
/* Interrupt Priorities are WORD accessible only under ARMv6M */ /* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */ /* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -778,33 +736,21 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -813,21 +759,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0) SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
{ } else {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -837,33 +776,26 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{ return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else {
} return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */ for (;;) /* wait until reset */
{ {
__NOP(); __NOP();
} }
@@ -871,8 +803,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -894,19 +824,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -914,9 +840,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

454
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_sc300.h vendored
View File

@@ -1,4 +1,4 @@
/**************************************************************************//** /**************************************************************************/ /**
* @file core_sc300.h * @file core_sc300.h
* @brief CMSIS SC300 Core Peripheral Access Layer Header File * @brief CMSIS SC300 Core Peripheral Access Layer Header File
* @version V4.30 * @version V4.30
@@ -31,11 +31,10 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CORE_SC300_H_GENERIC #ifndef __CORE_SC300_H_GENERIC
@@ -44,7 +43,7 @@
#include <stdint.h> #include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** /**
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,49 +71,47 @@
/* CMSIS SC300 definitions */ /* CMSIS SC300 definitions */
#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | __SC300_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_SC (300U) /*!< Cortex secure core */ #define __CORTEX_SC (300U) /*!< Cortex secure core */
#if defined(__CC_ARM)
#if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline #define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#define __packed #define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#else #else
#error Unknown compiler #error Unknown compiler
#endif #endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
@@ -123,45 +119,45 @@
*/ */
#define __FPU_USED 0U #define __FPU_USED 0U
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP #if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
#if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
#if defined __ARMVFP__ #if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TASKING__ ) #elif defined(__TASKING__)
#if defined __FPU_VFP__ #if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __CSMC__ ) #elif defined(__CSMC__)
#if ( __CSMC__ & 0x400U) #if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -175,30 +171,30 @@
#define __CORE_SC300_H_DEPENDANT #define __CORE_SC300_H_DEPENDANT
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* check device defines and use defaults */ /* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES #if defined __CHECK_DEVICE_DEFINES
#ifndef __SC300_REV #ifndef __SC300_REV
#define __SC300_REV 0x0000U #define __SC300_REV 0x0000U
#warning "__SC300_REV not defined in device header file; using default!" #warning "__SC300_REV not defined in device header file; using default!"
#endif #endif
#ifndef __MPU_PRESENT #ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U #define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!" #warning "__MPU_PRESENT not defined in device header file; using default!"
#endif #endif
#ifndef __NVIC_PRIO_BITS #ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4U #define __NVIC_PRIO_BITS 4U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif #endif
#ifndef __Vendor_SysTickConfig #ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U #define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif #endif
#endif #endif
/* IO definitions (access restrictions to peripheral registers) */ /* IO definitions (access restrictions to peripheral registers) */
@@ -210,9 +206,9 @@
\li for automatic generation of peripheral register debug information. \li for automatic generation of peripheral register debug information.
*/ */
#ifdef __cplusplus #ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */ #define __I volatile /*!< Defines 'read only' permissions */
#else #else
#define __I volatile const /*!< Defines 'read only' permissions */ #define __I volatile const /*!< Defines 'read only' permissions */
#endif #endif
#define __O volatile /*!< Defines 'write only' permissions */ #define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */
@@ -224,8 +220,6 @@
/*@} end of group SC300 */ /*@} end of group SC300 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -251,16 +245,14 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */
{ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} APSR_Type; } APSR_Type;
@@ -281,16 +273,13 @@ typedef union
#define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} IPSR_Type; } IPSR_Type;
@@ -299,23 +288,20 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
{ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} xPSR_Type; } xPSR_Type;
@@ -345,17 +331,14 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
{ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} CONTROL_Type; } CONTROL_Type;
@@ -369,7 +352,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -380,8 +362,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U]; uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -403,7 +384,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -414,8 +394,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -627,7 +606,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -638,8 +616,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control and ID Register not in the SCB. \brief Structure type to access the System Control and ID Register not in the SCB.
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0[1U]; uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
uint32_t RESERVED1[1U]; uint32_t RESERVED1[1U];
@@ -651,7 +628,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */ /*@} end of group CMSIS_SCnotSCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -662,8 +638,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -703,7 +678,6 @@ typedef struct
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
@@ -714,14 +688,12 @@ typedef struct
/** /**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/ */
typedef struct typedef struct {
{ __OM union {
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U]; uint32_t RESERVED0[864U];
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U]; uint32_t RESERVED1[15U];
@@ -806,7 +778,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_ITM */ /*@}*/ /* end of group CMSIS_ITM */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
@@ -817,8 +788,7 @@ typedef struct
/** /**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT). \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
@@ -953,7 +923,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */ /*@}*/ /* end of group CMSIS_DWT */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI) \defgroup CMSIS_TPI Trace Port Interface (TPI)
@@ -964,8 +933,7 @@ typedef struct
/** /**
\brief Structure type to access the Trace Port Interface Register (TPI). \brief Structure type to access the Trace Port Interface Register (TPI).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
@@ -1108,7 +1076,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_TPI */ /*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
@@ -1120,8 +1087,7 @@ typedef struct
/** /**
\brief Structure type to access the Memory Protection Unit (MPU). \brief Structure type to access the Memory Protection Unit (MPU).
*/ */
typedef struct typedef struct {
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -1203,7 +1169,6 @@ typedef struct
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -1214,8 +1179,7 @@ typedef struct
/** /**
\brief Structure type to access the Core Debug Register (CoreDebug). \brief Structure type to access the Core Debug Register (CoreDebug).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
@@ -1308,7 +1272,6 @@ typedef struct
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -1322,7 +1285,7 @@ typedef struct
\param[in] value Value of the bit field. \param[in] value Value of the bit field.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
@@ -1330,11 +1293,10 @@ typedef struct
\param[in] value Value of register. \param[in] value Value of register.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -1352,24 +1314,22 @@ typedef struct
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif #endif
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -1382,8 +1342,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1401,52 +1359,36 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field. \param [in] PriorityGroup Priority grouping field.
*/ */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
{
uint32_t reg_value; uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */ reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value | reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value; SCB->AIRCR = reg_value;
} }
/** /**
\brief Get Priority Grouping \brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller. \details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -1455,33 +1397,23 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
{ return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Active Interrupt \brief Get Active Interrupt
@@ -1490,11 +1422,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not active. \return 0 Interrupt status is not active.
\return 1 Interrupt status is active. \return 1 Interrupt status is active.
*/ */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -1503,19 +1431,14 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0) SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
{ } else {
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -1525,20 +1448,15 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{ return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } else {
} return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
else
{
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief Encode Priority \brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group, \details Encodes the priority for an interrupt with the given priority group,
@@ -1550,8 +1468,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\param [in] SubPriority Subpriority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/ */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1559,13 +1476,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return ( return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
} }
/** /**
\brief Decode Priority \brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to \details Decodes an interrupt priority value with a given priority group to
@@ -1577,8 +1490,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
\param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0).
*/ */
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1587,24 +1499,20 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */ for (;;) /* wait until reset */
{ {
__NOP(); __NOP();
} }
@@ -1612,8 +1520,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1635,19 +1541,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -1655,8 +1557,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */ /* ##################################### Debug In/Output function ########################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1668,7 +1568,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** /**
\brief ITM Send Character \brief ITM Send Character
\details Transmits a character via the ITM channel 0, and \details Transmits a character via the ITM channel 0, and
@@ -1677,13 +1576,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
\param [in] ch Character to transmit. \param [in] ch Character to transmit.
\returns Character to transmit. \returns Character to transmit.
*/ */
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{ {
while (ITM->PORT[0U].u32 == 0UL) {
__NOP(); __NOP();
} }
ITM->PORT[0U].u8 = (uint8_t)ch; ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -1691,19 +1588,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
return (ch); return (ch);
} }
/** /**
\brief ITM Receive Character \brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer. \details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character. \return Received character.
\return -1 No character pending. \return -1 No character pending.
*/ */
__STATIC_INLINE int32_t ITM_ReceiveChar (void) __STATIC_INLINE int32_t ITM_ReceiveChar(void) {
{
int32_t ch = -1; /* no character available */ int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
{
ch = ITM_RxBuffer; ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
} }
@@ -1711,31 +1605,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
return (ch); return (ch);
} }
/** /**
\brief ITM Check Character \brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available. \return 0 No character available.
\return 1 Character available. \return 1 Character available.
*/ */
__STATIC_INLINE int32_t ITM_CheckChar (void) __STATIC_INLINE int32_t ITM_CheckChar(void) {
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
{
return (0); /* no character available */ return (0); /* no character available */
} } else {
else
{
return (1); /* character available */ return (1); /* character available */
} }
} }
/*@} end of CMSIS_core_DebugFunctions */ /*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

454
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h vendored
View File

@@ -41,7 +41,7 @@
#define __STM32_HAL_LEGACY #define __STM32_HAL_LEGACY
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -275,8 +275,6 @@
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
/** /**
* @} * @}
*/ */
@@ -378,7 +376,6 @@
* @} * @}
*/ */
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{ * @{
*/ */
@@ -440,16 +437,16 @@
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
#if defined(STM32L1) #if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */ #endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */ #endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
@@ -462,20 +459,18 @@
*/ */
#if defined(STM32H7) #if defined(STM32H7)
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
#endif /* STM32H7 */ #endif /* STM32H7 */
/** /**
* @} * @}
*/ */
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -645,7 +640,7 @@
*/ */
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32F7) #if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif #endif
/** /**
* @} * @}
@@ -720,7 +715,6 @@
* @} * @}
*/ */
/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@@ -741,7 +735,6 @@
* @} * @}
*/ */
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@@ -882,7 +875,6 @@
* @} * @}
*/ */
/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@@ -996,8 +988,7 @@
* @} * @}
*/ */
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@@ -1076,15 +1067,15 @@
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd) == ENABLE) ? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #define HAL_Lock_Cmd(cmd) (((cmd) == ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0) #if defined(STM32L0)
#else #else
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #define HAL_VREFINT_Cmd(cmd) (((cmd) == ENABLE) ? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif #endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
/** /**
* @} * @}
*/ */
@@ -1100,7 +1091,7 @@
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
/** /**
* @} * @}
*/ */
@@ -1112,8 +1103,8 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE) ? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus) : HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
/** /**
* @} * @}
*/ */
@@ -1161,7 +1152,7 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
/** /**
* @} * @}
*/ */
@@ -1213,7 +1204,6 @@
* @} * @}
*/ */
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
* @{ * @{
*/ */
@@ -1262,7 +1252,6 @@
* @} * @}
*/ */
/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -1395,7 +1384,6 @@
#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
@@ -1434,158 +1422,176 @@
#define COMP_LOCK __HAL_COMP_LOCK #define COMP_LOCK __HAL_COMP_LOCK
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
__HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
__HAL_COMP_COMP6_EXTI_DISABLE_IT()) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
__HAL_COMP_COMP6_EXTI_GET_FLAG()) #endif
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ #if defined(STM32F302xE) || defined(STM32F302xC)
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
# endif ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
# if defined(STM32F302xE) || defined(STM32F302xC) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
__HAL_COMP_COMP6_EXTI_ENABLE_IT()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
__HAL_COMP_COMP6_EXTI_DISABLE_IT()) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
__HAL_COMP_COMP6_EXTI_GET_FLAG()) (((__FLAG__) == COMP_EXTI_LINE_COMP1) \
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG())
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) (((__FLAG__) == COMP_EXTI_LINE_COMP1) \
# endif ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ #endif
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ : __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \
__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ : __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \
__HAL_COMP_COMP7_EXTI_ENABLE_IT()) : __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
__HAL_COMP_COMP7_EXTI_DISABLE_IT()) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ : __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
__HAL_COMP_COMP7_EXTI_GET_FLAG()) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \
# endif : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : __HAL_COMP_COMP7_EXTI_ENABLE_IT())
# if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \
__HAL_COMP_COMP2_EXTI_ENABLE_IT()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : __HAL_COMP_COMP7_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
__HAL_COMP_COMP2_EXTI_DISABLE_IT()) (((__FLAG__) == COMP_EXTI_LINE_COMP1) \
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
__HAL_COMP_COMP2_EXTI_GET_FLAG()) : ((__FLAG__) == COMP_EXTI_LINE_COMP2) \
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) : ((__FLAG__) == COMP_EXTI_LINE_COMP3) \
# endif ? __HAL_COMP_COMP3_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : __HAL_COMP_COMP7_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
#endif
#if defined(STM32F373xC) || defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#endif
#else #else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG())
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#endif #endif
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
@@ -1616,9 +1622,7 @@
* @{ * @{
*/ */
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
((WAVE) == DAC_WAVE_NOISE)|| \
((WAVE) == DAC_WAVE_TRIANGLE))
/** /**
* @} * @}
@@ -1691,12 +1695,10 @@
#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
/** /**
* @} * @}
*/ */
/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -1706,7 +1708,6 @@
* @} * @}
*/ */
/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -1719,7 +1720,6 @@
* @} * @}
*/ */
/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -1741,7 +1741,6 @@
* @} * @}
*/ */
/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -1761,7 +1760,11 @@
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() \
do { \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while (0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -1770,8 +1773,20 @@
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) #define __HAL_PWR_PVM_DISABLE() \
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) do { \
HAL_PWREx_DisablePVM1(); \
HAL_PWREx_DisablePVM2(); \
HAL_PWREx_DisablePVM3(); \
HAL_PWREx_DisablePVM4(); \
} while (0)
#define __HAL_PWR_PVM_ENABLE() \
do { \
HAL_PWREx_EnablePVM1(); \
HAL_PWREx_EnablePVM2(); \
HAL_PWREx_EnablePVM3(); \
HAL_PWREx_EnablePVM4(); \
} while (0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@@ -1781,7 +1796,7 @@
#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
#if defined (STM32F4) #if defined(STM32F4)
#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
@@ -1798,7 +1813,6 @@
* @} * @}
*/ */
/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
* @{ * @{
*/ */
@@ -1807,7 +1821,7 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd) == ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -2870,7 +2884,7 @@
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
#if defined (STM32F1) #if defined(STM32F1)
#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
@@ -2881,21 +2895,22 @@
#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
#else #else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() \
: (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */ #endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM #define IS_ALARM IS_RTC_ALARM
@@ -3055,7 +3070,6 @@
* @} * @}
*/ */
/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -3200,7 +3214,6 @@
* @} * @}
*/ */
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -3216,4 +3229,3 @@
#endif /* ___STM32_HAL_LEGACY */ #endif /* ___STM32_HAL_LEGACY */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

49
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h vendored
View File

@@ -62,13 +62,7 @@ extern "C" {
/** @defgroup HAL_TICK_FREQ Tick Frequency /** @defgroup HAL_TICK_FREQ Tick Frequency
* @{ * @{
*/ */
typedef enum typedef enum { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef;
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/** /**
* @} * @}
*/ */
@@ -109,7 +103,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
#if defined (DBGMCU_CR_DBG_TIM4_STOP) #if defined(DBGMCU_CR_DBG_TIM4_STOP)
/** /**
* @brief TIM4 Peripherals Debug mode * @brief TIM4 Peripherals Debug mode
*/ */
@@ -117,7 +111,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM5_STOP) #if defined(DBGMCU_CR_DBG_TIM5_STOP)
/** /**
* @brief TIM5 Peripherals Debug mode * @brief TIM5 Peripherals Debug mode
*/ */
@@ -125,7 +119,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM6_STOP) #if defined(DBGMCU_CR_DBG_TIM6_STOP)
/** /**
* @brief TIM6 Peripherals Debug mode * @brief TIM6 Peripherals Debug mode
*/ */
@@ -133,7 +127,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM7_STOP) #if defined(DBGMCU_CR_DBG_TIM7_STOP)
/** /**
* @brief TIM7 Peripherals Debug mode * @brief TIM7 Peripherals Debug mode
*/ */
@@ -141,7 +135,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM12_STOP) #if defined(DBGMCU_CR_DBG_TIM12_STOP)
/** /**
* @brief TIM12 Peripherals Debug mode * @brief TIM12 Peripherals Debug mode
*/ */
@@ -149,7 +143,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM13_STOP) #if defined(DBGMCU_CR_DBG_TIM13_STOP)
/** /**
* @brief TIM13 Peripherals Debug mode * @brief TIM13 Peripherals Debug mode
*/ */
@@ -157,7 +151,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM14_STOP) #if defined(DBGMCU_CR_DBG_TIM14_STOP)
/** /**
* @brief TIM14 Peripherals Debug mode * @brief TIM14 Peripherals Debug mode
*/ */
@@ -183,7 +177,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
/** /**
* @brief I2C2 Peripherals Debug mode * @brief I2C2 Peripherals Debug mode
*/ */
@@ -191,7 +185,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#endif #endif
#if defined (DBGMCU_CR_DBG_CAN1_STOP) #if defined(DBGMCU_CR_DBG_CAN1_STOP)
/** /**
* @brief CAN1 Peripherals Debug mode * @brief CAN1 Peripherals Debug mode
*/ */
@@ -199,7 +193,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_CAN2_STOP) #if defined(DBGMCU_CR_DBG_CAN2_STOP)
/** /**
* @brief CAN2 Peripherals Debug mode * @brief CAN2 Peripherals Debug mode
*/ */
@@ -208,7 +202,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#endif #endif
/* Peripherals on APB2 */ /* Peripherals on APB2 */
#if defined (DBGMCU_CR_DBG_TIM1_STOP) #if defined(DBGMCU_CR_DBG_TIM1_STOP)
/** /**
* @brief TIM1 Peripherals Debug mode * @brief TIM1 Peripherals Debug mode
*/ */
@@ -216,7 +210,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM8_STOP) #if defined(DBGMCU_CR_DBG_TIM8_STOP)
/** /**
* @brief TIM8 Peripherals Debug mode * @brief TIM8 Peripherals Debug mode
*/ */
@@ -224,7 +218,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM9_STOP) #if defined(DBGMCU_CR_DBG_TIM9_STOP)
/** /**
* @brief TIM9 Peripherals Debug mode * @brief TIM9 Peripherals Debug mode
*/ */
@@ -232,7 +226,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM10_STOP) #if defined(DBGMCU_CR_DBG_TIM10_STOP)
/** /**
* @brief TIM10 Peripherals Debug mode * @brief TIM10 Peripherals Debug mode
*/ */
@@ -240,7 +234,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM11_STOP) #if defined(DBGMCU_CR_DBG_TIM11_STOP)
/** /**
* @brief TIM11 Peripherals Debug mode * @brief TIM11 Peripherals Debug mode
*/ */
@@ -248,8 +242,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
#endif #endif
#if defined(DBGMCU_CR_DBG_TIM15_STOP)
#if defined (DBGMCU_CR_DBG_TIM15_STOP)
/** /**
* @brief TIM15 Peripherals Debug mode * @brief TIM15 Peripherals Debug mode
*/ */
@@ -257,7 +250,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM16_STOP) #if defined(DBGMCU_CR_DBG_TIM16_STOP)
/** /**
* @brief TIM16 Peripherals Debug mode * @brief TIM16 Peripherals Debug mode
*/ */
@@ -265,7 +258,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM17_STOP) #if defined(DBGMCU_CR_DBG_TIM17_STOP)
/** /**
* @brief TIM17 Peripherals Debug mode * @brief TIM17 Peripherals Debug mode
*/ */
@@ -280,9 +273,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
/** @defgroup HAL_Private_Macros HAL Private Macros /** @defgroup HAL_Private_Macros HAL Private Macros
* @{ * @{
*/ */
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/** /**
* @} * @}
*/ */

339
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_ADC_H #define __STM32F1xx_HAL_ADC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -64,11 +64,10 @@
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
* ADC can be either disabled or enabled without conversion on going on regular group. * ADC can be either disabled or enabled without conversion on going on regular group.
*/ */
typedef struct typedef struct {
{
uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset
This parameter can be a value of @ref ADC_Data_align */ application): MSB on register bit 14 and LSB on register bit 3). This parameter can be a value of @ref ADC_Data_align */
uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
@@ -86,7 +85,8 @@ typedef struct
uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). uint32_t
DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */ This parameter can be set to ENABLE or DISABLE. */
@@ -97,25 +97,24 @@ typedef struct
If set to ADC_SOFTWARE_START, external triggers are disabled. If set to ADC_SOFTWARE_START, external triggers are disabled.
If set to external trigger source, triggering is on event rising edge. If set to external trigger source, triggering is on event rising edge.
This parameter can be a value of @ref ADC_External_trigger_source_Regular */ This parameter can be a value of @ref ADC_External_trigger_source_Regular */
}ADC_InitTypeDef; } ADC_InitTypeDef;
/** /**
* @brief Structure definition of ADC channel for regular group * @brief Structure definition of ADC channel for regular group
* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
* ADC can be either disabled or enabled without conversion on going on regular group. * ADC can be either disabled or enabled without conversion on going on regular group.
*/ */
typedef struct typedef struct {
{
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection
It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */
Refer to errata sheet of these devices for more details. */
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
This parameter can be a value of @ref ADC_regular_rank This parameter can be a value of @ref ADC_regular_rank
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or
parameter number of conversions can be adjusted) */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
@@ -125,15 +124,14 @@ typedef struct
Note: In case of usage of internal measurement channels (VrefInt/TempSensor), Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
}ADC_ChannelConfTypeDef; } ADC_ChannelConfTypeDef;
/** /**
* @brief ADC Configuration analog watchdog definition * @brief ADC Configuration analog watchdog definition
* @note The setting of these parameters with function is conditioned to ADC state. * @note The setting of these parameters with function is conditioned to ADC state.
* ADC state can be either disabled or enabled without conversion on going on regular and injected groups. * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
*/ */
typedef struct typedef struct {
{
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
This parameter can be a value of @ref ADC_analog_watchdog_mode. */ This parameter can be a value of @ref ADC_analog_watchdog_mode. */
uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
@@ -146,7 +144,7 @@ typedef struct
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
}ADC_AnalogWDGConfTypeDef; } ADC_AnalogWDGConfTypeDef;
/** /**
* @brief HAL ADC state machine: ADC states definition (bitfields) * @brief HAL ADC state machine: ADC states definition (bitfields)
@@ -163,14 +161,16 @@ typedef struct
#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
/* States of ADC group regular */ /* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, #define HAL_ADC_STATE_REG_BUSY \
0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, \
external trigger, low power auto power-on, multimode ADC master control) */ external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ #define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */
/* States of ADC group injected */ /* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, #define HAL_ADC_STATE_INJ_BUSY \
0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, \
external trigger, low power auto power-on, multimode ADC master control) */ external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ #define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
@@ -183,12 +183,10 @@ typedef struct
/* States of ADC multi-mode */ /* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */
/** /**
* @brief ADC handle Structure definition * @brief ADC handle Structure definition
*/ */
typedef struct typedef struct {
{
ADC_TypeDef *Instance; /*!< Register base address */ ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC required parameters */ ADC_InitTypeDef Init; /*!< ADC required parameters */
@@ -200,13 +198,11 @@ typedef struct
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */ __IO uint32_t ErrorCode; /*!< ADC Error code */
}ADC_HandleTypeDef; } ADC_HandleTypeDef;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants ADC Exported Constants /** @defgroup ADC_Exported_Constants ADC Exported Constants
@@ -217,7 +213,8 @@ typedef struct
* @{ * @{
*/ */
#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, #define HAL_ADC_ERROR_INTERNAL \
0x01U /*!< ADC IP internal error: if problem of clocking, \
enable/disable, erroneous state */ enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
@@ -226,7 +223,6 @@ typedef struct
* @} * @}
*/ */
/** @defgroup ADC_Data_align ADC data alignment /** @defgroup ADC_Data_align ADC data alignment
* @{ * @{
*/ */
@@ -263,22 +259,22 @@ typedef struct
/* Note: Depending on devices, some channels may not be available on package */ /* Note: Depending on devices, some channels may not be available on package */
/* pins. Refer to device datasheet for channels availability. */ /* pins. Refer to device datasheet for channels availability. */
#define ADC_CHANNEL_0 0x00000000U #define ADC_CHANNEL_0 0x00000000U
#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 )) #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1))
#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 )) #define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2))
#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) #define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 )) #define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3))
#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 )) #define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 )) #define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 )) #define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 )) #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
@@ -291,12 +287,12 @@ typedef struct
* @{ * @{
*/ */
#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ #define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */
#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */ #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1)) /*!< Sampling time 13.5 ADC clock cycles */
#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */ #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2)) /*!< Sampling time 41.5 ADC clock cycles */
#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */ #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)) /*!< Sampling time 71.5 ADC clock cycles */
#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
/** /**
* @} * @}
@@ -381,7 +377,6 @@ typedef struct
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@@ -414,28 +409,19 @@ typedef struct
* @{ * @{
*/ */
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
(ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
(ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2)
ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
(ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
(ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1)
ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
(ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
(ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0)
ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
@@ -459,13 +445,12 @@ typedef struct
*/ */
/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD)
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Macros ADC Exported Macros /** @defgroup ADC_Exported_Macros ADC Exported Macros
@@ -483,16 +468,14 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval None * @retval None
*/ */
#define __HAL_ADC_ENABLE(__HANDLE__) \ #define __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
(SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
/** /**
* @brief Disable the ADC peripheral * @brief Disable the ADC peripheral
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval None * @retval None
*/ */
#define __HAL_ADC_DISABLE(__HANDLE__) \ #define __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
(CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
/** @brief Enable the ADC end of conversion interrupt. /** @brief Enable the ADC end of conversion interrupt.
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
@@ -503,8 +486,7 @@ typedef struct
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
* @retval None * @retval None
*/ */
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
/** @brief Disable the ADC end of conversion interrupt. /** @brief Disable the ADC end of conversion interrupt.
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
@@ -515,8 +497,7 @@ typedef struct
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
* @retval None * @retval None
*/ */
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
/** @brief Checks if the specified ADC interrupt source is enabled or disabled. /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
@@ -527,8 +508,7 @@ typedef struct
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
* @retval None * @retval None
*/ */
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected ADC's flag status. /** @brief Get the selected ADC's flag status.
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
@@ -541,8 +521,7 @@ typedef struct
* @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
* @retval None * @retval None
*/ */
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the ADC's pending flags /** @brief Clear the ADC's pending flags
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
@@ -555,15 +534,13 @@ typedef struct
* @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
* @retval None * @retval None
*/ */
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
(WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
/** @brief Reset ADC handle state /** @brief Reset ADC handle state
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval None * @retval None
*/ */
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
/** /**
* @} * @}
@@ -582,9 +559,7 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval SET (ADC enabled) or RESET (ADC disabled) * @retval SET (ADC enabled) or RESET (ADC disabled)
*/ */
#define ADC_IS_ENABLE(__HANDLE__) \ #define ADC_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON)) ? SET : RESET)
((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
) ? SET : RESET)
/** /**
* @brief Test if conversion trigger of regular group is software start * @brief Test if conversion trigger of regular group is software start
@@ -592,8 +567,7 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval SET (software start) or RESET (external trigger) * @retval SET (software start) or RESET (external trigger)
*/ */
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
/** /**
* @brief Test if conversion trigger of injected group is software start * @brief Test if conversion trigger of injected group is software start
@@ -601,8 +575,7 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval SET (software start) or RESET (external trigger) * @retval SET (software start) or RESET (external trigger)
*/ */
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
/** /**
* @brief Simultaneously clears and sets specific bits of the handle State * @brief Simultaneously clears and sets specific bits of the handle State
@@ -618,16 +591,14 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval None * @retval None
*/ */
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
/** /**
* @brief Set ADC number of conversions into regular channel sequence length. * @brief Set ADC number of conversions into regular channel sequence length.
* @param _NbrOfConversion_: Regular channel sequence length * @param _NbrOfConversion_: Regular channel sequence length
* @retval None * @retval None
*/ */
#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
(((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
/** /**
* @brief Set the ADC's sample time for channel numbers between 10 and 18. * @brief Set the ADC's sample time for channel numbers between 10 and 18.
@@ -635,8 +606,7 @@ typedef struct
* @param _CHANNELNB_: Channel number. * @param _CHANNELNB_: Channel number.
* @retval None * @retval None
*/ */
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_)-10)))
((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
/** /**
* @brief Set the ADC's sample time for channel numbers between 0 and 9. * @brief Set the ADC's sample time for channel numbers between 0 and 9.
@@ -644,8 +614,7 @@ typedef struct
* @param _CHANNELNB_: Channel number. * @param _CHANNELNB_: Channel number.
* @retval None * @retval None
*/ */
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
/** /**
* @brief Set the selected regular channel rank for rank between 1 and 6. * @brief Set the selected regular channel rank for rank between 1 and 6.
@@ -653,8 +622,7 @@ typedef struct
* @param _RANKNB_: Rank number. * @param _RANKNB_: Rank number.
* @retval None * @retval None
*/ */
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_)-1)))
((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
/** /**
* @brief Set the selected regular channel rank for rank between 7 and 12. * @brief Set the selected regular channel rank for rank between 7 and 12.
@@ -662,8 +630,7 @@ typedef struct
* @param _RANKNB_: Rank number. * @param _RANKNB_: Rank number.
* @retval None * @retval None
*/ */
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_)-7)))
((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
/** /**
* @brief Set the selected regular channel rank for rank between 13 and 16. * @brief Set the selected regular channel rank for rank between 13 and 16.
@@ -671,16 +638,14 @@ typedef struct
* @param _RANKNB_: Rank number. * @param _RANKNB_: Rank number.
* @retval None * @retval None
*/ */
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_)-13)))
((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
/** /**
* @brief Set the injected sequence length. * @brief Set the injected sequence length.
* @param _JSQR_JL_: Sequence length. * @param _JSQR_JL_: Sequence length.
* @retval None * @retval None
*/ */
#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_)-1) << ADC_JSQR_JL_Pos)
(((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
/** /**
* @brief Set the selected injected channel rank * @brief Set the selected injected channel rank
@@ -692,24 +657,21 @@ typedef struct
* @param _JSQR_JL_: Sequence length. * @param _JSQR_JL_: Sequence length.
* @retval None * @retval None
*/ */
#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
/** /**
* @brief Enable ADC continuous conversion mode. * @brief Enable ADC continuous conversion mode.
* @param _CONTINUOUS_MODE_: Continuous mode. * @param _CONTINUOUS_MODE_: Continuous mode.
* @retval None * @retval None
*/ */
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
/** /**
* @brief Configures the number of discontinuous conversions for the regular group channels. * @brief Configures the number of discontinuous conversions for the regular group channels.
* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
* @retval None * @retval None
*/ */
#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_)-1) << ADC_CR1_DISCNUM_Pos)
(((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
/** /**
* @brief Enable ADC scan mode to convert multiple ranks with sequencer. * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
@@ -718,10 +680,7 @@ typedef struct
*/ */
/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
/* is equivalent to ADC_SCAN_ENABLE. */ /* is equivalent to ADC_SCAN_ENABLE. */
#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ #define ADC_CR1_SCAN_SET(_SCAN_MODE_) ((((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)) ? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE))
(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
)
/** /**
* @brief Get the maximum ADC conversion cycles on all channels. * @brief Get the maximum ADC conversion cycles on all channels.
@@ -736,89 +695,47 @@ typedef struct
* @retval ADC conversion cycles on all channels * @retval ADC conversion cycles on all channels
*/ */
#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET)) \
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ ? \
\ \
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 \
ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
: \ : ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \
((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ || ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) \
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 \
((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5))
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT))
((ALIGN) == ADC_DATAALIGN_LEFT) )
#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || ((SCAN_MODE) == ADC_SCAN_ENABLE))
((SCAN_MODE) == ADC_SCAN_ENABLE) )
#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING))
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ #define IS_ADC_CHANNEL(CHANNEL) \
((CHANNEL) == ADC_CHANNEL_1) || \ (((CHANNEL) == ADC_CHANNEL_0) || ((CHANNEL) == ADC_CHANNEL_1) || ((CHANNEL) == ADC_CHANNEL_2) || ((CHANNEL) == ADC_CHANNEL_3) || ((CHANNEL) == ADC_CHANNEL_4) || ((CHANNEL) == ADC_CHANNEL_5) \
((CHANNEL) == ADC_CHANNEL_2) || \ || ((CHANNEL) == ADC_CHANNEL_6) || ((CHANNEL) == ADC_CHANNEL_7) || ((CHANNEL) == ADC_CHANNEL_8) || ((CHANNEL) == ADC_CHANNEL_9) || ((CHANNEL) == ADC_CHANNEL_10) || ((CHANNEL) == ADC_CHANNEL_11) \
((CHANNEL) == ADC_CHANNEL_3) || \ || ((CHANNEL) == ADC_CHANNEL_12) || ((CHANNEL) == ADC_CHANNEL_13) || ((CHANNEL) == ADC_CHANNEL_14) || ((CHANNEL) == ADC_CHANNEL_15) || ((CHANNEL) == ADC_CHANNEL_16) \
((CHANNEL) == ADC_CHANNEL_4) || \ || ((CHANNEL) == ADC_CHANNEL_17))
((CHANNEL) == ADC_CHANNEL_5) || \
((CHANNEL) == ADC_CHANNEL_6) || \
((CHANNEL) == ADC_CHANNEL_7) || \
((CHANNEL) == ADC_CHANNEL_8) || \
((CHANNEL) == ADC_CHANNEL_9) || \
((CHANNEL) == ADC_CHANNEL_10) || \
((CHANNEL) == ADC_CHANNEL_11) || \
((CHANNEL) == ADC_CHANNEL_12) || \
((CHANNEL) == ADC_CHANNEL_13) || \
((CHANNEL) == ADC_CHANNEL_14) || \
((CHANNEL) == ADC_CHANNEL_15) || \
((CHANNEL) == ADC_CHANNEL_16) || \
((CHANNEL) == ADC_CHANNEL_17) )
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ #define IS_ADC_SAMPLE_TIME(TIME) \
((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || ((TIME) == ADC_SAMPLETIME_28CYCLES_5) \
((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ || ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ #define IS_ADC_REGULAR_RANK(CHANNEL) \
((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ (((CHANNEL) == ADC_REGULAR_RANK_1) || ((CHANNEL) == ADC_REGULAR_RANK_2) || ((CHANNEL) == ADC_REGULAR_RANK_3) || ((CHANNEL) == ADC_REGULAR_RANK_4) || ((CHANNEL) == ADC_REGULAR_RANK_5) \
((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ || ((CHANNEL) == ADC_REGULAR_RANK_6) || ((CHANNEL) == ADC_REGULAR_RANK_7) || ((CHANNEL) == ADC_REGULAR_RANK_8) || ((CHANNEL) == ADC_REGULAR_RANK_9) || ((CHANNEL) == ADC_REGULAR_RANK_10) \
((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ || ((CHANNEL) == ADC_REGULAR_RANK_11) || ((CHANNEL) == ADC_REGULAR_RANK_12) || ((CHANNEL) == ADC_REGULAR_RANK_13) || ((CHANNEL) == ADC_REGULAR_RANK_14) || ((CHANNEL) == ADC_REGULAR_RANK_15) \
((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ || ((CHANNEL) == ADC_REGULAR_RANK_16))
((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
((CHANNEL) == ADC_REGULAR_RANK_10) || \
((CHANNEL) == ADC_REGULAR_RANK_11) || \
((CHANNEL) == ADC_REGULAR_RANK_12) || \
((CHANNEL) == ADC_REGULAR_RANK_13) || \
((CHANNEL) == ADC_REGULAR_RANK_14) || \
((CHANNEL) == ADC_REGULAR_RANK_15) || \
((CHANNEL) == ADC_REGULAR_RANK_16) )
#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) \
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC))
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || ((CONVERSION) == ADC_INJECTED_GROUP) || ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP))
((CONVERSION) == ADC_INJECTED_GROUP) || \
((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
/** @defgroup ADC_range_verification ADC range verification /** @defgroup ADC_range_verification ADC range verification
* For a unique ADC resolution: 12 bits * For a unique ADC resolution: 12 bits
* @{ * @{
@@ -860,12 +777,11 @@ typedef struct
* @{ * @{
*/ */
/* Initialization and de-initialization functions **********************************/ /* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
/** /**
* @} * @}
*/ */
@@ -876,68 +792,63 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
* @{ * @{
*/ */
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
/* Non-blocking mode: Interruption */ /* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
/* Non-blocking mode: DMA */ /* Non-blocking mode: DMA */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */ /* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/** /**
* @} * @}
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
/** @addtogroup ADC_Exported_Functions_Group3 /** @addtogroup ADC_Exported_Functions_Group3
* @{ * @{
*/ */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
/** /**
* @} * @}
*/ */
/* Peripheral State functions *************************************************/ /* Peripheral State functions *************************************************/
/** @addtogroup ADC_Exported_Functions_Group4 /** @addtogroup ADC_Exported_Functions_Group4
* @{ * @{
*/ */
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Internal HAL driver functions **********************************************/ /* Internal HAL driver functions **********************************************/
/** @addtogroup ADC_Private_Functions /** @addtogroup ADC_Private_Functions
* @{ * @{
*/ */
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef *hadc);
void ADC_StabilizationTime(uint32_t DelayUs); void ADC_StabilizationTime(uint32_t DelayUs);
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
@@ -946,7 +857,6 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma);
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@@ -959,7 +869,6 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma);
} }
#endif #endif
#endif /* __STM32F1xx_HAL_ADC_H */ #endif /* __STM32F1xx_HAL_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

389
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_ADC_EX_H #define __STM32F1xx_HAL_ADC_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -68,18 +68,18 @@
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv') * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
* - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group. * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
*/ */
typedef struct typedef struct {
{ uint32_t
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure InjectedChannel; /*!< Selection of ADC channel to configure
This parameter can be a value of @ref ADC_channels This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection
It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */
Refer to errata sheet of these devices for more details. */
uint32_t InjectedRank; /*!< Rank in the injected group sequencer uint32_t InjectedRank; /*!< Rank in the injected group sequencer
This parameter must be a value of @ref ADCEx_injected_rank This parameter must be a value of @ref ADCEx_injected_rank
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel
setting (or parameter number of conversions can be adjusted) */
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
@@ -98,13 +98,12 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 4. This parameter must be a number between Min_Data = 1 and Max_Data = 4.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */ configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). uint32_t
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous
This parameter can be set to ENABLE or DISABLE. mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */
configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
This parameter can be set to ENABLE or DISABLE. This parameter can be set to ENABLE or DISABLE.
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
@@ -118,38 +117,37 @@ typedef struct
If set to external trigger source, triggering is on event rising edge. If set to external trigger source, triggering is on event rising edge.
This parameter can be a value of @ref ADCEx_External_trigger_source_Injected This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to the fly) Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */ configure a channel on injected group can impact the configuration of other channels previously set. */
}ADC_InjectionConfTypeDef; } ADC_InjectionConfTypeDef;
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/** /**
* @brief Structure definition of ADC multimode * @brief Structure definition of ADC multimode
* @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
* State of ADCs of the common group must be: disabled. * State of ADCs of the common group must be: disabled.
*/ */
typedef struct typedef struct {
{
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
This parameter can be a value of @ref ADCEx_Common_mode This parameter can be a value of @ref ADCEx_Common_mode
Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any
Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2. configuration change. Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1
Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode. and ADC2. Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC
Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters). clock cycles for slow interleaved mode. Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration
The equivalences are: structure can have additional parameters). The equivalences are:
- Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'. - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several
- Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */ ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
- Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32
devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
} ADC_MultiModeTypeDef;
}ADC_MultiModeTypeDef;
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
@@ -190,7 +188,7 @@ typedef struct
#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
#if defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
/*!< External triggers of regular group for ADC3 only */ /*!< External triggers of regular group for ADC3 only */
#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3
#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1
@@ -202,7 +200,7 @@ typedef struct
/*!< External triggers of regular group for all ADC instances */ /*!< External triggers of regular group for all ADC instances */
#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ /*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */ /* XL-density devices. */
/* To use it on ADC or ADC2, a remap of trigger must be done from */ /* To use it on ADC or ADC2, a remap of trigger must be done from */
@@ -234,7 +232,7 @@ typedef struct
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
#if defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
/*!< External triggers of injected group for ADC3 only */ /*!< External triggers of injected group for ADC3 only */
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2
@@ -246,7 +244,7 @@ typedef struct
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ /*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */ /* XL-density devices. */
/* To use it on ADC1 or ADC2, a remap of trigger must be done from */ /* To use it on ADC1 or ADC2, a remap of trigger must be done from */
@@ -265,19 +263,27 @@ typedef struct
* @} * @}
*/ */
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
* @{ * @{
*/ */
#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ #define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */ #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */ #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INJECSIMULT_INTERLFAST \
#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ ((uint32_t)(ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling \
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */ phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */ #define ADC_DUALMODE_INJECSIMULT_INTERLSLOW \
#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ ((uint32_t)(ADC_CR1_DUALMOD_2)) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock \
#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
#define ADC_DUALMODE_INTERLFAST \
((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles \
(equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INTERLSLOW \
((uint32_t)(ADC_CR1_DUALMOD_3)) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter \
"TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */ #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
/** /**
* @} * @}
@@ -288,7 +294,6 @@ typedef struct
* @} * @}
*/ */
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
@@ -304,18 +309,18 @@ typedef struct
/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */ /* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U #define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U
#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)(ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 )) #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2))
#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG)
/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */ /* XL-density devices. */
#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11 #define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
#endif #endif
#if defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
/* External triggers of regular group for ADC3 */ /* External triggers of regular group for ADC3 */
#define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
#define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2
@@ -326,7 +331,7 @@ typedef struct
#endif #endif
/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */ /* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) #define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)(ADC_CR2_EXTSEL_1))
#define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) #define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
/** /**
* @} * @}
@@ -340,18 +345,18 @@ typedef struct
/* (used internally by HAL driver. To not use into HAL structure parameters) */ /* (used internally by HAL driver. To not use into HAL structure parameters) */
/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */ /* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1))
#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 )) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2))
#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG)
/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ /* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */ /* XL-density devices. */
#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
#endif #endif
#if defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
/* External triggers of injected group for ADC3 */ /* External triggers of injected group for ADC3 */
#define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
#define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
@@ -362,7 +367,7 @@ typedef struct
/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */ /* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U #define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0)) #define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_0))
#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) #define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
/** /**
* @} * @}
@@ -372,7 +377,6 @@ typedef struct
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
@@ -383,7 +387,6 @@ typedef struct
/* Macro reserved for internal HAL driver usage, not intended to be used in */ /* Macro reserved for internal HAL driver usage, not intended to be used in */
/* code of final user. */ /* code of final user. */
/** /**
* @brief For devices with 3 ADCs: Defines the external trigger source * @brief For devices with 3 ADCs: Defines the external trigger source
* for regular group according to ADC into common group ADC1&ADC2 or * for regular group according to ADC into common group ADC1&ADC2 or
@@ -394,22 +397,11 @@ typedef struct
* @param __EXT_TRIG_CONV__: External trigger selected for regular group. * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
* @retval External trigger to be programmed into EXTSEL bits of CR2 register * @retval External trigger to be programmed into EXTSEL bits of CR2 register
*/ */
#if defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
(( (((__HANDLE__)->Instance) == ADC3) \ (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO) ? (ADC3_EXTERNALTRIG_T8_TRGO) : (__EXT_TRIG_CONV__)) : (__EXT_TRIG_CONV__))
)? \
( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
)? \
(ADC3_EXTERNALTRIG_T8_TRGO) \
: \
(__EXT_TRIG_CONV__) \
) \
: \
(__EXT_TRIG_CONV__) \
)
#else #else
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) (__EXT_TRIG_CONV__)
(__EXT_TRIG_CONV__)
#endif /* STM32F103xE || STM32F103xG */ #endif /* STM32F103xE || STM32F103xG */
/** /**
@@ -422,41 +414,22 @@ typedef struct
* @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group. * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
* @retval External trigger to be programmed into JEXTSEL bits of CR2 register * @retval External trigger to be programmed into JEXTSEL bits of CR2 register
*/ */
#if defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
(( (((__HANDLE__)->Instance) == ADC3) \ (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) ? (ADC3_EXTERNALTRIGINJEC_T8_CC4) : (__EXT_TRIG_INJECTCONV__)) : (__EXT_TRIG_INJECTCONV__))
)? \
( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
)? \
(ADC3_EXTERNALTRIGINJEC_T8_CC4) \
: \
(__EXT_TRIG_INJECTCONV__) \
) \
: \
(__EXT_TRIG_INJECTCONV__) \
)
#else #else
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) (__EXT_TRIG_INJECTCONV__)
(__EXT_TRIG_INJECTCONV__)
#endif /* STM32F103xE || STM32F103xG */ #endif /* STM32F103xE || STM32F103xG */
/** /**
* @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs) * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
*/ */
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_DUALMOD) : (RESET))
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
)? \
(ADC1->CR1 & ADC_CR1_DUALMOD) \
: \
(RESET) \
)
#else #else
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (RESET)
(RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/** /**
@@ -464,17 +437,10 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval None * @retval None
*/ */
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (((((__HANDLE__)->Instance) == ADC2)) ? ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) : (!RESET))
(( (((__HANDLE__)->Instance) == ADC2) \
)? \
((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \
: \
(!RESET) \
)
#else #else
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (!RESET)
(!RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/** /**
@@ -482,28 +448,20 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval None * @retval None
*/ */
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_JAUTO) : (RESET))
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
)? \
(ADC1->CR1 & ADC_CR1_JAUTO) \
: \
(RESET) \
)
#else #else
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (RESET)
(RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/** /**
* @brief Set handle of the other ADC sharing the common multimode settings * @brief Set handle of the other ADC sharing the common multimode settings
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @param __HANDLE_OTHER_ADC__: other ADC handle * @param __HANDLE_OTHER_ADC__: other ADC handle
* @retval None * @retval None
*/ */
#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
((__HANDLE_OTHER_ADC__)->Instance = ADC2)
/** /**
* @brief Set handle of the ADC slave associated to the ADC master * @brief Set handle of the ADC slave associated to the ADC master
@@ -513,18 +471,13 @@ typedef struct
* @param __HANDLE_SLAVE__: ADC slave handle * @param __HANDLE_SLAVE__: ADC slave handle
* @retval None * @retval None
*/ */
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ((__HANDLE_SLAVE__)->Instance = ADC2)
((__HANDLE_SLAVE__)->Instance = ADC2)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || ((CHANNEL) == ADC_INJECTED_RANK_2) || ((CHANNEL) == ADC_INJECTED_RANK_3) || ((CHANNEL) == ADC_INJECTED_RANK_4))
((CHANNEL) == ADC_INJECTED_RANK_2) || \
((CHANNEL) == ADC_INJECTED_RANK_3) || \
((CHANNEL) == ADC_INJECTED_RANK_4))
#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
* @{ * @{
@@ -534,121 +487,69 @@ typedef struct
* @} * @}
*/ */
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ || defined(STM32F105xC) || defined(STM32F107xC)
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ #define IS_ADC_EXTTRIG(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif #endif
#if defined (STM32F101xE) #if defined(STM32F101xE)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ #define IS_ADC_EXTTRIG(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif #endif
#if defined (STM32F101xG) #if defined(STM32F101xG)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ #define IS_ADC_EXTTRIG(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif #endif
#if defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ #define IS_ADC_EXTTRIG(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif #endif
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ || defined(STM32F105xC) || defined(STM32F107xC)
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ #define IS_ADC_EXTTRIGINJEC(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif #endif
#if defined (STM32F101xE) #if defined(STM32F101xE)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ #define IS_ADC_EXTTRIGINJEC(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif #endif
#if defined (STM32F101xG) #if defined(STM32F101xG)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ #define IS_ADC_EXTTRIGINJEC(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif #endif
#if defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ #define IS_ADC_EXTTRIGINJEC(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif #endif
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ #define IS_ADC_MODE(MODE) \
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ (((MODE) == ADC_MODE_INDEPENDENT) || ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) \
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || ((MODE) == ADC_DUALMODE_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT) || ((MODE) == ADC_DUALMODE_INTERLFAST) \
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \ || ((MODE) == ADC_DUALMODE_INTERLSLOW) || ((MODE) == ADC_DUALMODE_ALTERTRIG))
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
((MODE) == ADC_DUALMODE_INJECSIMULT) || \
((MODE) == ADC_DUALMODE_REGSIMULT) || \
((MODE) == ADC_DUALMODE_INTERLFAST) || \
((MODE) == ADC_DUALMODE_INTERLSLOW) || \
((MODE) == ADC_DUALMODE_ALTERTRIG) )
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/** /**
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup ADCEx_Exported_Functions /** @addtogroup ADCEx_Exported_Functions
* @{ * @{
@@ -660,54 +561,51 @@ typedef struct
*/ */
/* ADC calibration */ /* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc);
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
/* Non-blocking mode: Interruption */ /* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/* ADC multimode */ /* ADC multimode */
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/* ADC retrieve conversion value intended to be used with polling or interruption */ /* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
/** /**
* @} * @}
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
/** @addtogroup ADCEx_Exported_Functions_Group2 /** @addtogroup ADCEx_Exported_Functions_Group2
* @{ * @{
*/ */
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected);
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@@ -722,5 +620,4 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc
#endif /* __STM32F1xx_HAL_ADC_EX_H */ #endif /* __STM32F1xx_HAL_ADC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

110
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_CORTEX_H #define __STM32F1xx_HAL_CORTEX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -61,8 +61,7 @@
* @brief MPU Region initialization structure * @brief MPU Region initialization structure
* @{ * @{
*/ */
typedef struct typedef struct {
{
uint8_t Enable; /*!< Specifies the status of the region. uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect. uint8_t Number; /*!< Specifies the number of the region to protect.
@@ -84,7 +83,7 @@ typedef struct
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef; } MPU_Region_InitTypeDef;
/** /**
* @} * @}
*/ */
@@ -103,15 +102,20 @@ typedef struct
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{ * @{
*/ */
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority #define NVIC_PRIORITYGROUP_0 \
0x00000007U /*!< 0 bits for pre-emption priority \
4 bits for subpriority */ 4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority #define NVIC_PRIORITYGROUP_1 \
0x00000006U /*!< 1 bits for pre-emption priority \
3 bits for subpriority */ 3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority #define NVIC_PRIORITYGROUP_2 \
0x00000005U /*!< 2 bits for pre-emption priority \
2 bits for subpriority */ 2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority #define NVIC_PRIORITYGROUP_3 \
0x00000004U /*!< 3 bits for pre-emption priority \
1 bits for subpriority */ 1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority #define NVIC_PRIORITYGROUP_4 \
0x00000003U /*!< 4 bits for pre-emption priority \
0 bits for subpriority */ 0 bits for subpriority */
/** /**
* @} * @}
@@ -263,7 +267,6 @@ typedef struct
* @} * @}
*/ */
/* Exported Macros -----------------------------------------------------------*/ /* Exported Macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
@@ -290,7 +293,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void); uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
@@ -319,11 +322,8 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{ * @{
*/ */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ #define IS_NVIC_PRIORITY_GROUP(GROUP) \
((GROUP) == NVIC_PRIORITYGROUP_1) || \ (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
@@ -331,73 +331,36 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2))
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) \
((TYPE) == MPU_REGION_PRIV_RW) || \ (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \ || ((TYPE) == MPU_REGION_PRIV_RO_URO))
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ #define IS_MPU_REGION_NUMBER(NUMBER) \
((NUMBER) == MPU_REGION_NUMBER1) || \ (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) \
((NUMBER) == MPU_REGION_NUMBER2) || \ || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ #define IS_MPU_REGION_SIZE(SIZE) \
((SIZE) == MPU_REGION_SIZE_64B) || \ (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B) \
((SIZE) == MPU_REGION_SIZE_128B) || \ || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) \
((SIZE) == MPU_REGION_SIZE_256B) || \ || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) \
((SIZE) == MPU_REGION_SIZE_512B) || \ || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) \
((SIZE) == MPU_REGION_SIZE_1KB) || \ || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) \
((SIZE) == MPU_REGION_SIZE_2KB) || \ || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
@@ -422,5 +385,4 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __STM32F1xx_HAL_CORTEX_H */ #endif /* __STM32F1xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

57
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h vendored
View File

@@ -54,22 +54,12 @@ extern "C" {
/** /**
* @brief HAL Status structures definition * @brief HAL Status structures definition
*/ */
typedef enum typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef;
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/** /**
* @brief HAL Lock structures definition * @brief HAL Lock structures definition
*/ */
typedef enum typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef;
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_MAX_DELAY 0xFFFFFFFFU
@@ -78,10 +68,10 @@ typedef enum
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \ do { \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \ (__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0U) } while (0U)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
@@ -107,24 +97,21 @@ typedef enum
#error "USE_RTOS should be 0 in the current HAL release" #error "USE_RTOS should be 0 in the current HAL release"
#else #else
#define __HAL_LOCK(__HANDLE__) \ #define __HAL_LOCK(__HANDLE__) \
do{ \ do { \
if((__HANDLE__)->Lock == HAL_LOCKED) \ if ((__HANDLE__)->Lock == HAL_LOCKED) { \
{ \
return HAL_BUSY; \ return HAL_BUSY; \
} \ } else { \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \ (__HANDLE__)->Lock = HAL_LOCKED; \
} \ } \
}while (0U) } while (0U)
#define __HAL_UNLOCK(__HANDLE__) \ #define __HAL_UNLOCK(__HANDLE__) \
do{ \ do { \
(__HANDLE__)->Lock = HAL_UNLOCKED; \ (__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0U) } while (0U)
#endif /* USE_RTOS */ #endif /* USE_RTOS */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __weak #ifndef __weak
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#endif /* __weak */ #endif /* __weak */
@@ -133,11 +120,10 @@ typedef enum
#endif /* __packed */ #endif /* __packed */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END #ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4))) #define __ALIGN_END __attribute__((aligned(4)))
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
@@ -147,19 +133,18 @@ typedef enum
#define __ALIGN_END #define __ALIGN_END
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */ #if defined(__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4) #define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */ #elif defined(__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
#endif /* __CC_ARM */ #endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */ #endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/** /**
* @brief __RAM_FUNC definition * @brief __RAM_FUNC definition
*/ */
#if defined ( __CC_ARM ) #if defined(__CC_ARM)
/* ARM Compiler /* ARM Compiler
------------ ------------
RAM functions are defined using the toolchain options. RAM functions are defined using the toolchain options.
@@ -171,14 +156,14 @@ typedef enum
*/ */
#define __RAM_FUNC #define __RAM_FUNC
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
/* ICCARM Compiler /* ICCARM Compiler
--------------- ---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc". RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/ */
#define __RAM_FUNC __ramfunc #define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ ) #elif defined(__GNUC__)
/* GNU Compiler /* GNU Compiler
------------ ------------
RAM functions are defined using a specific toolchain attribute RAM functions are defined using a specific toolchain attribute
@@ -191,13 +176,13 @@ typedef enum
/** /**
* @brief __NOINLINE definition * @brief __NOINLINE definition
*/ */
#if defined ( __CC_ARM ) || defined ( __GNUC__ ) #if defined(__CC_ARM) || defined(__GNUC__)
/* ARM & GNUCompiler /* ARM & GNUCompiler
---------------- ----------------
*/ */
#define __NOINLINE __attribute__ ( (noinline) ) #define __NOINLINE __attribute__((noinline))
#elif defined ( __ICCARM__ ) #elif defined(__ICCARM__)
/* ICCARM Compiler /* ICCARM Compiler
--------------- ---------------
*/ */

68
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_DMA_H #define __STM32F1xx_HAL_DMA_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -61,8 +61,7 @@
/** /**
* @brief DMA Configuration Structure definition * @brief DMA Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory. from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */ This parameter can be a value of @ref DMA_Data_transfer_direction */
@@ -91,41 +90,37 @@ typedef struct
/** /**
* @brief HAL DMA State structures definition * @brief HAL DMA State structures definition
*/ */
typedef enum typedef enum {
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
}HAL_DMA_StateTypeDef; } HAL_DMA_StateTypeDef;
/** /**
* @brief HAL DMA Error Code structure definition * @brief HAL DMA Error Code structure definition
*/ */
typedef enum typedef enum {
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef; } HAL_DMA_LevelCompleteTypeDef;
/** /**
* @brief HAL DMA Callback ID structure definition * @brief HAL DMA Callback ID structure definition
*/ */
typedef enum typedef enum {
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
}HAL_DMA_CallbackIDTypeDef; } HAL_DMA_CallbackIDTypeDef;
/** /**
* @brief DMA handle Structure definition * @brief DMA handle Structure definition
*/ */
typedef struct __DMA_HandleTypeDef typedef struct __DMA_HandleTypeDef {
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */ DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */ DMA_InitTypeDef Init; /*!< DMA communication parameters */
@@ -136,13 +131,13 @@ typedef struct __DMA_HandleTypeDef
void *Parent; /*!< Parent object state */ void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ void (*XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ void (*XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ void (*XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ void (*XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */ __IO uint32_t ErrorCode; /*!< DMA Error code */
@@ -242,7 +237,6 @@ typedef struct __DMA_HandleTypeDef
* @} * @}
*/ */
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{ * @{
*/ */
@@ -292,7 +286,6 @@ typedef struct __DMA_HandleTypeDef
* @} * @}
*/ */
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros /** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{ * @{
@@ -318,7 +311,6 @@ typedef struct __DMA_HandleTypeDef
*/ */
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
/* Interrupt & Flag management */ /* Interrupt & Flag management */
/** /**
@@ -343,7 +335,7 @@ typedef struct __DMA_HandleTypeDef
* @arg DMA_IT_TE: Transfer error interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None * @retval None
*/ */
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
/** /**
* @brief Check whether the specified DMA Channel interrupt is enabled or not. * @brief Check whether the specified DMA Channel interrupt is enabled or not.
@@ -381,7 +373,7 @@ typedef struct __DMA_HandleTypeDef
*/ */
/* Initialization and de-initialization functions *****************************/ /* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
@@ -390,13 +382,13 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/** /**
@@ -422,33 +414,21 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
* @{ * @{
*/ */
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))
((STATE) == DMA_MINC_DISABLE))
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD))
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD))
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR))
((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/** /**
* @} * @}

225
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_DMA_EX_H #define __STM32F1xx_HAL_DMA_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -59,8 +59,7 @@
* @{ * @{
*/ */
/* Interrupt & Flag management */ /* Interrupt & Flag management */
#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
* @{ * @{
*/ */
@@ -71,75 +70,111 @@
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ? DMA_FLAG_TC1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ? DMA_FLAG_TC2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ? DMA_FLAG_TC3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ ? DMA_FLAG_TC4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ ? DMA_FLAG_TC5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_TC5) ? DMA_FLAG_TC6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_TC7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 : DMA_FLAG_TC5)
/** /**
* @brief Returns the current DMA Channel half transfer complete flag. * @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ? DMA_FLAG_HT1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ? DMA_FLAG_HT2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ? DMA_FLAG_HT3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ ? DMA_FLAG_HT4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ ? DMA_FLAG_HT5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_HT5) ? DMA_FLAG_HT6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_HT7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 : DMA_FLAG_HT5)
/** /**
* @brief Returns the current DMA Channel transfer error flag. * @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ? DMA_FLAG_TE1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ? DMA_FLAG_TE2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ? DMA_FLAG_TE3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ ? DMA_FLAG_TE4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ ? DMA_FLAG_TE5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_TE5) ? DMA_FLAG_TE6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_TE7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 : DMA_FLAG_TE5)
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ ? DMA_FLAG_GL1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ ? DMA_FLAG_GL2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ ? DMA_FLAG_GL3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ ? DMA_FLAG_GL4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ ? DMA_FLAG_GL5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_GL5) ? DMA_FLAG_GL6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_GL7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 : DMA_FLAG_GL5)
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.
@@ -152,9 +187,7 @@
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET). * @retval The state of FLAG (SET or RESET).
*/ */
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
(DMA1->ISR & (__FLAG__)))
/** /**
* @brief Clears the DMA Channel pending flags. * @brief Clears the DMA Channel pending flags.
@@ -167,9 +200,7 @@
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval None * @retval None
*/ */
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
(DMA1->IFCR = (__FLAG__)))
/** /**
* @} * @}
@@ -186,55 +217,67 @@
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ? DMA_FLAG_TC1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ? DMA_FLAG_TC2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ? DMA_FLAG_TC3 \
DMA_FLAG_TC7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 : DMA_FLAG_TC7)
/** /**
* @brief Return the current DMA Channel half transfer complete flag. * @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ? DMA_FLAG_HT1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ? DMA_FLAG_HT2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ? DMA_FLAG_HT3 \
DMA_FLAG_HT7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 : DMA_FLAG_HT7)
/** /**
* @brief Return the current DMA Channel transfer error flag. * @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ? DMA_FLAG_TE1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ? DMA_FLAG_TE2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ? DMA_FLAG_TE3 \
DMA_FLAG_TE7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 : DMA_FLAG_TE7)
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ ? DMA_FLAG_GL1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ ? DMA_FLAG_GL2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ ? DMA_FLAG_GL3 \
DMA_FLAG_GL7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 : DMA_FLAG_GL7)
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.

20
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_FLASH_H #define __STM32F1xx_HAL_FLASH_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -64,14 +64,10 @@
* @{ * @{
*/ */
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
#if defined(FLASH_ACR_LATENCY) #if defined(FLASH_ACR_LATENCY)
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1) || ((__LATENCY__) == FLASH_LATENCY_2))
((__LATENCY__) == FLASH_LATENCY_1) || \
((__LATENCY__) == FLASH_LATENCY_2))
#else #else
#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
@@ -88,8 +84,7 @@
/** /**
* @brief FLASH Procedure structure definition * @brief FLASH Procedure structure definition
*/ */
typedef enum typedef enum {
{
FLASH_PROC_NONE = 0U, FLASH_PROC_NONE = 0U,
FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_PAGEERASE = 1U,
FLASH_PROC_MASSERASE = 2U, FLASH_PROC_MASSERASE = 2U,
@@ -101,8 +96,7 @@ typedef enum
/** /**
* @brief FLASH handle Structure definition * @brief FLASH handle Structure definition
*/ */
typedef struct typedef struct {
{
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
@@ -221,8 +215,7 @@ typedef struct
* The value of this parameter depend on device used within the same series * The value of this parameter depend on device used within the same series
* @retval None * @retval None
*/ */
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__))
/** /**
* @brief Get the FLASH Latency. * @brief Get the FLASH Latency.
@@ -341,4 +334,3 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
#endif /* __STM32F1xx_HAL_FLASH_H */ #endif /* __STM32F1xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

191
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_FLASH_EX_H #define __STM32F1xx_HAL_FLASH_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -90,84 +90,88 @@
/* Low Density */ /* Low Density */
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \ #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU)) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
/* Medium Density */ /* Medium Density */
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \ ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU)))) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) \
? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))))
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
/* High Density */ /* High Density */
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \ #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU))) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0807FFFFU) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0805FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU)))
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
/* XL Density */ /* XL Density */
#if defined(FLASH_BANK2_END) #if defined(FLASH_BANK2_END)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \ #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU)) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080FFFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080BFFFFU))
#endif /* FLASH_BANK2_END */ #endif /* FLASH_BANK2_END */
/* Connectivity Line */ /* Connectivity Line */
#if (defined(STM32F105xC) || defined(STM32F107xC)) #if (defined(STM32F105xC) || defined(STM32F107xC))
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \ #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU))) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU)))
#endif /* STM32F105xC || STM32F107xC */ #endif /* STM32F105xC || STM32F107xC */
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#if defined(FLASH_BANK2_END) #if defined(FLASH_BANK2_END)
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || ((BANK) == FLASH_BANK_BOTH))
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
#else #else
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
#endif /* FLASH_BANK2_END */ #endif /* FLASH_BANK2_END */
/* Low Density */ /* Low Density */
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
/* Medium Density */ /* Medium Density */
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \ (((ADDRESS) >= FLASH_BASE) \
((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) \
((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) ? ((ADDRESS) <= FLASH_BANK1_END) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS) <= 0x0800FFFF) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
/* High Density */ /* High Density */
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \ (((ADDRESS) >= FLASH_BASE) \
((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS) <= FLASH_BANK1_END) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
/* XL Density */ /* XL Density */
#if defined(FLASH_BANK2_END) #if defined(FLASH_BANK2_END)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
#endif /* FLASH_BANK2_END */ #endif /* FLASH_BANK2_END */
/* Connectivity Line */ /* Connectivity Line */
#if (defined(STM32F105xC) || defined(STM32F107xC)) #if (defined(STM32F105xC) || defined(STM32F107xC))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ (((ADDRESS) >= FLASH_BASE) \
((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS) <= FLASH_BANK1_END) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
#endif /* STM32F105xC || STM32F107xC */ #endif /* STM32F105xC || STM32F107xC */
@@ -183,8 +187,7 @@
/** /**
* @brief FLASH Erase structure definition * @brief FLASH Erase structure definition
*/ */
typedef struct typedef struct {
{
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
This parameter can be a value of @ref FLASHEx_Type_Erase */ This parameter can be a value of @ref FLASHEx_Type_Erase */
@@ -203,8 +206,7 @@ typedef struct
/** /**
* @brief FLASH Options bytes program structure definition * @brief FLASH Options bytes program structure definition
*/ */
typedef struct typedef struct {
{
uint32_t OptionType; /*!< OptionType: Option byte to be configured. uint32_t OptionType; /*!< OptionType: Option byte to be configured.
This parameter can be a value of @ref FLASHEx_OB_Type */ This parameter can be a value of @ref FLASHEx_OB_Type */
@@ -329,9 +331,7 @@ typedef struct
* @{ * @{
*/ */
/* STM32 Low and Medium density devices */ /* STM32 Low and Medium density devices */
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \ #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
|| defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
|| defined(STM32F103xB)
#define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */ #define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */
#define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */ #define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */
#define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */ #define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */
@@ -371,11 +371,8 @@ typedef struct
#define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */ #define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
/* STM32 High-density, XL-density and Connectivity line devices */ /* STM32 High-density, XL-density and Connectivity line devices */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|| defined(STM32F101xG) || defined(STM32F103xG) \
|| defined(STM32F105xC) || defined(STM32F107xC)
#define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */ #define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */
#define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */ #define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */
#define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */ #define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */
@@ -526,30 +523,30 @@ typedef struct
* @{ * @{
*/ */
#if defined(FLASH_BANK2_END) #if defined(FLASH_BANK2_END)
#define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */ #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */
#define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */ #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */
#define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */ #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */
#define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */ #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */
#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */ #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */
#define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */ #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */
#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */ #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */
#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */ #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */
#define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U) /*!< FLASH Bank2 Busy flag */ #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U) /*!< FLASH Bank2 Busy flag */
#define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U) /*!< FLASH Bank2 Programming error flag */ #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U) /*!< FLASH Bank2 Programming error flag */
#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag */ #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag */
#define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U) /*!< FLASH Bank2 End of Operation flag */ #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U) /*!< FLASH Bank2 End of Operation flag */
#else #else
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */ #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
#endif #endif
#define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error */ #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error */
/** /**
* @} * @}
*/ */
@@ -559,19 +556,19 @@ typedef struct
* @{ * @{
*/ */
#if defined(FLASH_BANK2_END) #if defined(FLASH_BANK2_END)
#define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */ #define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */
#define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */ #define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */
#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */ #define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */
#define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */ #define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */
#define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */ #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */
#define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2 */ #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2 */
#else #else
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */ #define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
#endif #endif
/** /**
@@ -582,7 +579,6 @@ typedef struct
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@@ -608,12 +604,13 @@ typedef struct
* @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
* @retval none * @retval none
*/ */
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) \
do { \
/* Enable Bank1 IT */ \ /* Enable Bank1 IT */ \
SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ SET_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
/* Enable Bank2 IT */ \ /* Enable Bank2 IT */ \
SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
} while(0U) } while (0U)
/** /**
* @brief Disable the specified FLASH interrupt. * @brief Disable the specified FLASH interrupt.
@@ -625,12 +622,13 @@ typedef struct
* @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
* @retval none * @retval none
*/ */
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) \
do { \
/* Disable Bank1 IT */ \ /* Disable Bank1 IT */ \
CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ CLEAR_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
/* Disable Bank2 IT */ \ /* Disable Bank2 IT */ \
CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
} while(0U) } while (0U)
/** /**
* @brief Get the specified FLASH flag status. * @brief Get the specified FLASH flag status.
@@ -647,11 +645,8 @@ typedef struct
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
* @retval The new state of __FLAG__ (SET or RESET). * @retval The new state of __FLAG__ (SET or RESET).
*/ */
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ #define __HAL_FLASH_GET_FLAG(__FLAG__) \
(FLASH->OBR & FLASH_OBR_OPTERR) : \ (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : ((((__FLAG__)&SR_FLAG_MASK) != RESET) ? (FLASH->SR & ((__FLAG__)&SR_FLAG_MASK)) : (FLASH->SR2 & ((__FLAG__) >> 16U))))
((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
(FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
(FLASH->SR2 & ((__FLAG__) >> 16U))))
/** /**
* @brief Clear the specified FLASH flag. * @brief Clear the specified FLASH flag.
@@ -668,27 +663,24 @@ typedef struct
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
* @retval none * @retval none
*/ */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) \
do { \
/* Clear FLASH_FLAG_OPTVERR flag */ \ /* Clear FLASH_FLAG_OPTVERR flag */ \
if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ if ((__FLAG__) == FLASH_FLAG_OPTVERR) { \
{ \
CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
} \ } else { \
else { \
/* Clear Flag in Bank1 */ \ /* Clear Flag in Bank1 */ \
if (((__FLAG__) & SR_FLAG_MASK) != RESET) \ if (((__FLAG__)&SR_FLAG_MASK) != RESET) { \
{ \ FLASH->SR = ((__FLAG__)&SR_FLAG_MASK); \
FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
} \ } \
/* Clear Flag in Bank2 */ \ /* Clear Flag in Bank2 */ \
if (((__FLAG__) >> 16U) != RESET) \ if (((__FLAG__) >> 16U) != RESET) { \
{ \
FLASH->SR2 = ((__FLAG__) >> 16U); \ FLASH->SR2 = ((__FLAG__) >> 16U); \
} \ } \
} \ } \
} while(0U) } while (0U)
#else #else
/** /**
* @brief Enable the specified FLASH interrupt. * @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt * @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
@@ -719,9 +711,7 @@ typedef struct
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
* @retval The new state of __FLAG__ (SET or RESET). * @retval The new state of __FLAG__ (SET or RESET).
*/ */
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : (FLASH->SR & (__FLAG__)))
(FLASH->OBR & FLASH_OBR_OPTERR) : \
(FLASH->SR & (__FLAG__)))
/** /**
* @brief Clear the specified FLASH flag. * @brief Clear the specified FLASH flag.
* @param __FLAG__ specifies the FLASH flags to clear. * @param __FLAG__ specifies the FLASH flags to clear.
@@ -732,17 +722,16 @@ typedef struct
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
* @retval none * @retval none
*/ */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) \
do { \
/* Clear FLASH_FLAG_OPTVERR flag */ \ /* Clear FLASH_FLAG_OPTVERR flag */ \
if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ if ((__FLAG__) == FLASH_FLAG_OPTVERR) { \
{ \
CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
} \ } else { \
else { \
/* Clear Flag in Bank1 */ \ /* Clear Flag in Bank1 */ \
FLASH->SR = (__FLAG__); \ FLASH->SR = (__FLAG__); \
} \ } \
} while(0U) } while (0U)
#endif #endif

33
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h vendored
View File

@@ -60,8 +60,7 @@ extern "C" {
/** /**
* @brief GPIO Init structure definition * @brief GPIO Init structure definition
*/ */
typedef struct typedef struct {
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured. uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */ This parameter can be any value of @ref GPIO_pins_define */
@@ -78,11 +77,7 @@ typedef struct
/** /**
* @brief GPIO Bit SET and Bit RESET enumeration * @brief GPIO Bit SET and Bit RESET enumeration
*/ */
typedef enum typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState;
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
} GPIO_PinState;
/** /**
* @} * @}
*/ */
@@ -277,23 +272,13 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
* @{ * @{
*/ */
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_PIN(PIN) ((((PIN)&GPIO_PIN_MASK) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ #define IS_GPIO_MODE(MODE) \
((MODE) == GPIO_MODE_OUTPUT_PP) ||\ (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) \
((MODE) == GPIO_MODE_OUTPUT_OD) ||\ || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) \
((MODE) == GPIO_MODE_AF_PP) ||\ || ((MODE) == GPIO_MODE_ANALOG))
((MODE) == GPIO_MODE_AF_OD) ||\ #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
((MODE) == GPIO_MODE_IT_RISING) ||\ #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN))
((MODE) == GPIO_MODE_IT_FALLING) ||\
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING) ||\
((MODE) == GPIO_MODE_EVT_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
((PULL) == GPIO_PULLDOWN))
/** /**
* @} * @}
*/ */

71
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h vendored
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@@ -84,22 +84,11 @@ extern "C" {
#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ #define IS_AFIO_EVENTOUT_PIN(__PIN__) \
((__PIN__) == AFIO_EVENTOUT_PIN_1) || \ (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4) \
((__PIN__) == AFIO_EVENTOUT_PIN_2) || \ || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9) \
((__PIN__) == AFIO_EVENTOUT_PIN_3) || \ || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) \
((__PIN__) == AFIO_EVENTOUT_PIN_4) || \ || ((__PIN__) == AFIO_EVENTOUT_PIN_15))
((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
((__PIN__) == AFIO_EVENTOUT_PIN_15))
/** /**
* @} * @}
*/ */
@@ -114,11 +103,8 @@ extern "C" {
#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ #define IS_AFIO_EVENTOUT_PORT(__PORT__) \
((__PORT__) == AFIO_EVENTOUT_PORT_B) || \ (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))
((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
((__PORT__) == AFIO_EVENTOUT_PORT_E))
/** /**
* @} * @}
*/ */
@@ -461,7 +447,7 @@ extern "C" {
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
#endif #endif
#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) #if defined(AFIO_MAPR_ADC2_ETRGREG_REMAP)
/** /**
* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
@@ -825,47 +811,46 @@ extern "C" {
* @{ * @{
*/ */
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : 3U)
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :3U)
#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : 4U)
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :4U)
#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ #define GPIO_GET_INDEX(__GPIOx__) \
((__GPIOx__) == (GPIOB))? 1U :\ (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : ((__GPIOx__) == (GPIOE)) ? 4U : ((__GPIOx__) == (GPIOF)) ? 5U : 6U)
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :\
((__GPIOx__) == (GPIOE))? 4U :\
((__GPIOx__) == (GPIOF))? 5U :6U)
#endif #endif
#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ #define AFIO_REMAP_ENABLE(REMAP_PIN) \
do { \
uint32_t tmpreg = AFIO->MAPR; \
tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \
tmpreg |= REMAP_PIN; \ tmpreg |= REMAP_PIN; \
AFIO->MAPR = tmpreg; \ AFIO->MAPR = tmpreg; \
}while(0U) } while (0U)
#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ #define AFIO_REMAP_DISABLE(REMAP_PIN) \
do { \
uint32_t tmpreg = AFIO->MAPR; \
tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \
tmpreg &= ~REMAP_PIN; \ tmpreg &= ~REMAP_PIN; \
AFIO->MAPR = tmpreg; \ AFIO->MAPR = tmpreg; \
}while(0U) } while (0U)
#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \ #define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) \
do { \
uint32_t tmpreg = AFIO->MAPR; \
tmpreg &= ~REMAP_PIN_MASK; \ tmpreg &= ~REMAP_PIN_MASK; \
tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \
tmpreg |= REMAP_PIN; \ tmpreg |= REMAP_PIN; \
AFIO->MAPR = tmpreg; \ AFIO->MAPR = tmpreg; \
}while(0U) } while (0U)
#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \ #define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) \
do { \
uint32_t tmpreg = AFIO->MAPR; \
tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \ tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
tmpreg |= DBGAFR_SWJCFG; \ tmpreg |= DBGAFR_SWJCFG; \
AFIO->MAPR = tmpreg; \ AFIO->MAPR = tmpreg; \
}while(0U) } while (0U)
/** /**
* @} * @}

80
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_I2C_H #define __STM32F1xx_HAL_I2C_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -60,8 +60,7 @@
/** /**
* @brief I2C Configuration Structure definition * @brief I2C Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t ClockSpeed; /*!< Specifies the clock frequency. uint32_t ClockSpeed; /*!< Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */ This parameter must be set to a value lower than 400kHz */
@@ -86,7 +85,7 @@ typedef struct
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_nostretch_mode */ This parameter can be a value of @ref I2C_nostretch_mode */
}I2C_InitTypeDef; } I2C_InitTypeDef;
/** /**
* @brief HAL State structure definition * @brief HAL State structure definition
@@ -114,8 +113,7 @@ typedef struct
* 0 : Ready (no Tx operation ongoing) * 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing) * 1 : Busy (Tx operation ongoing)
*/ */
typedef enum typedef enum {
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
@@ -130,7 +128,7 @@ typedef enum
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
}HAL_I2C_StateTypeDef; } HAL_I2C_StateTypeDef;
/** /**
* @brief HAL Mode structure definition * @brief HAL Mode structure definition
@@ -149,20 +147,18 @@ typedef enum
* b3-b2-b1-b0 (not used) * b3-b2-b1-b0 (not used)
* xxxx : Should be set to 0000 * xxxx : Should be set to 0000
*/ */
typedef enum typedef enum {
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
}HAL_I2C_ModeTypeDef; } HAL_I2C_ModeTypeDef;
/** /**
* @brief I2C handle Structure definition * @brief I2C handle Structure definition
*/ */
typedef struct typedef struct {
{
I2C_TypeDef *Instance; /*!< I2C registers base address */ I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */ I2C_InitTypeDef Init; /*!< I2C communication parameters */
@@ -198,7 +194,7 @@ typedef struct
__IO uint32_t EventCount; /*!< I2C Event counter */ __IO uint32_t EventCount; /*!< I2C Event counter */
}I2C_HandleTypeDef; } I2C_HandleTypeDef;
/** /**
* @} * @}
@@ -406,8 +402,9 @@ typedef struct
* @arg I2C_FLAG_MSL: Master/Slave flag * @arg I2C_FLAG_MSL: Master/Slave flag
* @retval The new state of __FLAG__ (TRUE or FALSE). * @retval The new state of __FLAG__ (TRUE or FALSE).
*/ */
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) \
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? ((((__HANDLE__)->Instance->SR1) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)) \
: ((((__HANDLE__)->Instance->SR2) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)))
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. /** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
* @param __HANDLE__: specifies the I2C Handle. * @param __HANDLE__: specifies the I2C Handle.
@@ -423,7 +420,7 @@ typedef struct
* @arg I2C_FLAG_BERR: Bus error flag * @arg I2C_FLAG_BERR: Bus error flag
* @retval None * @retval None
*/ */
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__)&I2C_FLAG_MASK))
/** @brief Clears the I2C ADDR pending flag. /** @brief Clears the I2C ADDR pending flag.
* @param __HANDLE__: specifies the I2C Handle. * @param __HANDLE__: specifies the I2C Handle.
@@ -431,12 +428,12 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ #define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
do{ \ do { \
__IO uint32_t tmpreg = 0x00U; \ __IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR1; \ tmpreg = (__HANDLE__)->Instance->SR1; \
tmpreg = (__HANDLE__)->Instance->SR2; \ tmpreg = (__HANDLE__)->Instance->SR2; \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
/** @brief Clears the I2C STOPF pending flag. /** @brief Clears the I2C STOPF pending flag.
* @param __HANDLE__: specifies the I2C Handle. * @param __HANDLE__: specifies the I2C Handle.
@@ -444,12 +441,12 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ #define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
do{ \ do { \
__IO uint32_t tmpreg = 0x00U; \ __IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR1; \ tmpreg = (__HANDLE__)->Instance->SR1; \
(__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
/** @brief Enable the I2C peripheral. /** @brief Enable the I2C peripheral.
* @param __HANDLE__: specifies the I2C Handle. * @param __HANDLE__: specifies the I2C Handle.
@@ -479,7 +476,7 @@ typedef struct
*/ */
/* Initialization/de-initialization functions **********************************/ /* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/** /**
@@ -574,14 +571,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
*/ */
#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST)) #define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR) #define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__)-1U) / ((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) #define I2C_FREQRANGE(__PCLK__) ((__PCLK__) / 1000000U)
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) #define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__)*300U) / 1000U) + 1U))
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U)) #define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U) ? 4U : I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9)) #define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) \
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2) ? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ #define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) (((__SPEED__) <= 100000U) ? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) \
: ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U) ? 1U : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) #define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) #define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
@@ -596,25 +594,16 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters /** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
* @{ * @{
*/ */
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || ((CYCLE) == I2C_DUTYCYCLE_16_9))
((CYCLE) == I2C_DUTYCYCLE_16_9)) #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || ((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || ((STRETCH) == I2C_NOSTRETCH_ENABLE))
((ADDRESS) == I2C_DUALADDRESS_ENABLE)) #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || ((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U)) #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U) #define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || ((REQUEST) == I2C_NEXT_FRAME) || ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME))
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))
/** /**
* @} * @}
*/ */
@@ -644,7 +633,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
} }
#endif #endif
#endif /* __STM32F1xx_HAL_I2C_H */ #endif /* __STM32F1xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

18
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h vendored
View File

@@ -60,8 +60,7 @@ extern "C" {
/** /**
* @brief IWDG Init structure definition * @brief IWDG Init structure definition
*/ */
typedef struct typedef struct {
{
uint32_t Prescaler; /*!< Select the prescaler of the IWDG. uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
This parameter can be a value of @ref IWDG_Prescaler */ This parameter can be a value of @ref IWDG_Prescaler */
@@ -73,8 +72,7 @@ typedef struct
/** /**
* @brief IWDG Handle Structure definition * @brief IWDG Handle Structure definition
*/ */
typedef struct typedef struct {
{
IWDG_TypeDef *Instance; /*!< Register base address */ IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
@@ -108,7 +106,6 @@ typedef struct
* @} * @}
*/ */
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{ * @{
@@ -201,13 +198,9 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
* @param __PRESCALER__ IWDG prescaler value * @param __PRESCALER__ IWDG prescaler value
* @retval None * @retval None
*/ */
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ #define IS_IWDG_PRESCALER(__PRESCALER__) \
((__PRESCALER__) == IWDG_PRESCALER_8) || \ (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) \
((__PRESCALER__) == IWDG_PRESCALER_16) || \ || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128) || ((__PRESCALER__) == IWDG_PRESCALER_256))
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
/** /**
* @brief Check IWDG reload value. * @brief Check IWDG reload value.
@@ -228,7 +221,6 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

48
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_PWR_H #define __STM32F1xx_HAL_PWR_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -61,21 +61,18 @@
/** /**
* @brief PWR PVD configuration structure definition * @brief PWR PVD configuration structure definition
*/ */
typedef struct typedef struct {
{
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level */ This parameter can be a value of @ref PWR_PVD_detection_level */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode */ This parameter can be a value of @ref PWR_PVD_Mode */
}PWR_PVDTypeDef; } PWR_PVDTypeDef;
/** /**
* @} * @}
*/ */
/* Internal constants --------------------------------------------------------*/ /* Internal constants --------------------------------------------------------*/
/** @addtogroup PWR_Private_Constants /** @addtogroup PWR_Private_Constants
@@ -88,7 +85,6 @@ typedef struct
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants /** @defgroup PWR_Exported_Constants PWR Exported Constants
@@ -126,7 +122,6 @@ typedef struct
* @} * @}
*/ */
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{ * @{
*/ */
@@ -174,7 +169,6 @@ typedef struct
#define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO #define PWR_FLAG_PVDO PWR_CSR_PVDO
/** /**
* @} * @}
*/ */
@@ -237,21 +231,18 @@ typedef struct
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
/** /**
* @brief PVD EXTI line configuration: set falling edge trigger. * @brief PVD EXTI line configuration: set falling edge trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Disable the PVD Extended Interrupt Falling Trigger. * @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief PVD EXTI line configuration: set rising edge trigger. * @brief PVD EXTI line configuration: set rising edge trigger.
* @retval None. * @retval None.
@@ -269,16 +260,18 @@ typedef struct
* @brief PVD EXTI line configuration: set rising & falling edge trigger. * @brief PVD EXTI line configuration: set rising & falling edge trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
/** /**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* This parameter can be: * This parameter can be:
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/** /**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not. * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
@@ -305,21 +298,17 @@ typedef struct
/** @defgroup PWR_Private_Macros PWR Private Macros /** @defgroup PWR_Private_Macros PWR Private Macros
* @{ * @{
*/ */
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ #define IS_PWR_PVD_LEVEL(LEVEL) \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) \
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) \
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_PVD_MODE_NORMAL))
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
@@ -329,8 +318,6 @@ typedef struct
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions /** @addtogroup PWR_Exported_Functions PWR Exported Functions
@@ -374,8 +361,6 @@ void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void); void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void); void HAL_PWR_DisableSEVOnPend(void);
void HAL_PWR_PVD_IRQHandler(void); void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void); void HAL_PWR_PVDCallback(void);
/** /**
@@ -398,7 +383,6 @@ void HAL_PWR_PVDCallback(void);
} }
#endif #endif
#endif /* __STM32F1xx_HAL_PWR_H */ #endif /* __STM32F1xx_HAL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

368
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_RCC_H #define __STM32F1xx_HAL_RCC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -61,8 +61,7 @@
/** /**
* @brief RCC PLL configuration structure definition * @brief RCC PLL configuration structure definition
*/ */
typedef struct typedef struct {
{
uint32_t PLLState; /*!< PLLState: The new state of the PLL. uint32_t PLLState; /*!< PLLState: The new state of the PLL.
This parameter can be a value of @ref RCC_PLL_Config */ This parameter can be a value of @ref RCC_PLL_Config */
@@ -76,8 +75,7 @@ typedef struct
/** /**
* @brief RCC System, AHB and APB busses clock configuration structure definition * @brief RCC System, AHB and APB busses clock configuration structure definition
*/ */
typedef struct typedef struct {
{
uint32_t ClockType; /*!< The clock to be configured. uint32_t ClockType; /*!< The clock to be configured.
This parameter can be a value of @ref RCC_System_Clock_Type */ This parameter can be a value of @ref RCC_System_Clock_Type */
@@ -255,7 +253,6 @@ typedef struct
* @} * @}
*/ */
/** @defgroup RCC_MCO_Index MCO Index /** @defgroup RCC_MCO_Index MCO Index
* @{ * @{
*/ */
@@ -335,37 +332,41 @@ typedef struct
* using it. * using it.
* @{ * @{
*/ */
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ #define __HAL_RCC_DMA1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ #define __HAL_RCC_SRAM_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ #define __HAL_RCC_FLITF_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_CRC_CLK_ENABLE() do { \ #define __HAL_RCC_CRC_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
@@ -404,61 +405,68 @@ typedef struct
* using it. * using it.
* @{ * @{
*/ */
#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ #define __HAL_RCC_TIM2_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ #define __HAL_RCC_TIM3_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ #define __HAL_RCC_WWDG_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_USART2_CLK_ENABLE() do { \ #define __HAL_RCC_USART2_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ #define __HAL_RCC_I2C1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_BKP_CLK_ENABLE() do { \ #define __HAL_RCC_BKP_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \ #define __HAL_RCC_PWR_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
@@ -507,77 +515,86 @@ typedef struct
* using it. * using it.
* @{ * @{
*/ */
#define __HAL_RCC_AFIO_CLK_ENABLE() do { \ #define __HAL_RCC_AFIO_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ #define __HAL_RCC_GPIOA_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ #define __HAL_RCC_GPIOB_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ #define __HAL_RCC_GPIOC_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ #define __HAL_RCC_GPIOD_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ #define __HAL_RCC_ADC1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ #define __HAL_RCC_TIM1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ #define __HAL_RCC_SPI1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_USART1_CLK_ENABLE() do { \ #define __HAL_RCC_USART1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
/* Delay after an RCC peripheral clock enabling */\ /* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while (0U)
#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
@@ -699,8 +716,8 @@ typedef struct
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
* clock cycles. * clock cycles.
*/ */
#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *)RCC_CR_HSION_BB = ENABLE)
#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *)RCC_CR_HSION_BB = DISABLE)
/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage * @note The calibration is used to compensate for the variations in voltage
@@ -709,8 +726,7 @@ typedef struct
* (default is RCC_HSICALIBRATION_DEFAULT). * (default is RCC_HSICALIBRATION_DEFAULT).
* This parameter must be a number between 0 and 0x1F. * This parameter must be a number between 0 and 0x1F.
*/ */
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
/** /**
* @} * @}
@@ -725,14 +741,14 @@ typedef struct
* LSIRDY flag to be set indicating that LSI clock is stable and can * LSIRDY flag to be set indicating that LSI clock is stable and can
* be used to clock the IWDG and/or the RTC. * be used to clock the IWDG and/or the RTC.
*/ */
#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *)RCC_CSR_LSION_BB = ENABLE)
/** @brief Macro to disable the Internal Low Speed oscillator (LSI). /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
* @note LSI can not be disabled if the IWDG is running. * @note LSI can not be disabled if the IWDG is running.
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
* clock cycles. * clock cycles.
*/ */
#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *)RCC_CSR_LSION_BB = DISABLE)
/** /**
* @} * @}
@@ -765,27 +781,20 @@ typedef struct
* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
*/ */
#define __HAL_RCC_HSE_CONFIG(__STATE__) \ #define __HAL_RCC_HSE_CONFIG(__STATE__) \
do{ \ do { \
if ((__STATE__) == RCC_HSE_ON) \ if ((__STATE__) == RCC_HSE_ON) { \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEON); \ SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \ } else if ((__STATE__) == RCC_HSE_OFF) { \
else if ((__STATE__) == RCC_HSE_OFF) \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \ } else if ((__STATE__) == RCC_HSE_BYPASS) { \
else if ((__STATE__) == RCC_HSE_BYPASS) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
SET_BIT(RCC->CR, RCC_CR_HSEON); \ SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \ } else { \
else \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \ } \
}while(0U) } while (0U)
/** /**
* @} * @}
@@ -813,27 +822,20 @@ typedef struct
* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
*/ */
#define __HAL_RCC_LSE_CONFIG(__STATE__) \ #define __HAL_RCC_LSE_CONFIG(__STATE__) \
do{ \ do { \
if ((__STATE__) == RCC_LSE_ON) \ if ((__STATE__) == RCC_LSE_ON) { \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \ } else if ((__STATE__) == RCC_LSE_OFF) { \
else if ((__STATE__) == RCC_LSE_OFF) \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \ } else if ((__STATE__) == RCC_LSE_BYPASS) { \
else if ((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \ } else { \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \ } \
}while(0U) } while (0U)
/** /**
* @} * @}
@@ -849,12 +851,12 @@ typedef struct
* be used as system clock source. * be used as system clock source.
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
*/ */
#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *)RCC_CR_PLLON_BB = ENABLE)
/** @brief Macro to disable the main PLL. /** @brief Macro to disable the main PLL.
* @note The main PLL can not be disabled if it is used as system clock source * @note The main PLL can not be disabled if it is used as system clock source
*/ */
#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *)RCC_CR_PLLON_BB = DISABLE)
/** @brief Macro to configure the main PLL clock source and multiplication factors. /** @brief Macro to configure the main PLL clock source and multiplication factors.
* @note This function must be used only when the main PLL is disabled. * @note This function must be used only when the main PLL is disabled.
@@ -886,8 +888,7 @@ typedef struct
* @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
* *
*/ */
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL), ((__RCC_PLLSOURCE__) | (__PLLMUL__)))
MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
/** @brief Get oscillator clock selected as PLL input clock /** @brief Get oscillator clock selected as PLL input clock
* @retval The clock source used for PLL entry. The returned value can be one * @retval The clock source used for PLL entry. The returned value can be one
@@ -913,8 +914,7 @@ typedef struct
* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
*/ */
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
/** @brief Macro to get the clock source used as system clock. /** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one * @retval The clock source used as system clock. The returned value can be one
@@ -923,7 +923,7 @@ typedef struct
* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
*/ */
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
/** /**
* @} * @}
@@ -965,15 +965,13 @@ typedef struct
*/ */
#endif #endif
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
/** /**
* @} * @}
*/ */
/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
* @{ * @{
*/ */
@@ -1013,22 +1011,22 @@ typedef struct
/** @brief Macro to enable the the RTC clock. /** @brief Macro to enable the the RTC clock.
* @note These macros must be used only after the RTC clock source was selected. * @note These macros must be used only after the RTC clock source was selected.
*/ */
#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *)RCC_BDCR_RTCEN_BB = ENABLE)
/** @brief Macro to disable the the RTC clock. /** @brief Macro to disable the the RTC clock.
* @note These macros must be used only after the RTC clock source was selected. * @note These macros must be used only after the RTC clock source was selected.
*/ */
#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *)RCC_BDCR_RTCEN_BB = DISABLE)
/** @brief Macro to force the Backup domain reset. /** @brief Macro to force the Backup domain reset.
* @note This function resets the RTC peripheral (including the backup registers) * @note This function resets the RTC peripheral (including the backup registers)
* and the RTC clock source selection in RCC_BDCR register. * and the RTC clock source selection in RCC_BDCR register.
*/ */
#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *)RCC_BDCR_BDRST_BB = ENABLE)
/** @brief Macros to release the Backup domain reset. /** @brief Macros to release the Backup domain reset.
*/ */
#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *)RCC_BDCR_BDRST_BB = DISABLE)
/** /**
* @} * @}
@@ -1055,7 +1053,7 @@ typedef struct
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
@endif @endif
*/ */
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
/** @brief Disable RCC interrupt. /** @brief Disable RCC interrupt.
* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
@@ -1073,7 +1071,7 @@ typedef struct
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
@endif @endif
*/ */
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
/** @brief Clear the RCC's interrupt pending bits. /** @brief Clear the RCC's interrupt pending bits.
* @param __INTERRUPT__ specifies the interrupt pending bit to clear. * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
@@ -1092,7 +1090,7 @@ typedef struct
@endif @endif
* @arg @ref RCC_IT_CSS Clock Security System interrupt * @arg @ref RCC_IT_CSS Clock Security System interrupt
*/ */
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
/** @brief Check the RCC's interrupt has occurred or not. /** @brief Check the RCC's interrupt has occurred or not.
* @param __INTERRUPT__ specifies the RCC interrupt source to check. * @param __INTERRUPT__ specifies the RCC interrupt source to check.
@@ -1143,9 +1141,7 @@ typedef struct
* @arg @ref RCC_FLAG_LPWRRST Low Power reset. * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
* @retval The new state of __FLAG__ (TRUE or FALSE). * @retval The new state of __FLAG__ (TRUE or FALSE).
*/ */
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) & (1U << ((__FLAG__)&RCC_FLAG_MASK)))
((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
/** /**
* @} * @}
@@ -1329,47 +1325,30 @@ void HAL_RCC_CSSCallback(void);
* @} * @}
*/ */
#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))
((__SOURCE__) == RCC_PLLSOURCE_HSE)) #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS))
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
((__HSE__) == RCC_HSE_BYPASS))
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
((__LSE__) == RCC_LSE_BYPASS))
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
((__PLL__) == RCC_PLL_ON))
#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ #define IS_RCC_CLOCKTYPE(CLK) \
(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ ((((CLK)&RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK)&RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK)&RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \
(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ || (((CLK)&RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ #define IS_RCC_HCLK(__HCLK__) \
((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) \
#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))
((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))
((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
((__HCLK__) == RCC_SYSCLK_DIV512))
#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
((__PCLK__) == RCC_HCLK_DIV16))
#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ #define IS_RCC_RTCCLKSOURCE(__SOURCE__) \
((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
/** /**
* @} * @}
@@ -1390,4 +1369,3 @@ void HAL_RCC_CSSCallback(void);
#endif /* __STM32F1xx_HAL_RCC_H */ #endif /* __STM32F1xx_HAL_RCC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

756
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h vendored
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File diff suppressed because it is too large Load Diff

427
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h vendored
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@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_TIM_H #define __STM32F1xx_HAL_TIM_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -59,8 +59,7 @@
/** /**
* @brief TIM Time base Configuration Structure definition * @brief TIM Time base Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
@@ -90,8 +89,7 @@ typedef struct
/** /**
* @brief TIM Output Compare Configuration Structure definition * @brief TIM Output Compare Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t OCMode; /*!< Specifies the TIM mode. uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
@@ -109,7 +107,6 @@ typedef struct
This parameter can be a value of @ref TIM_Output_Fast_State This parameter can be a value of @ref TIM_Output_Fast_State
@note This parameter is valid only in PWM1 and PWM2 mode. */ @note This parameter is valid only in PWM1 and PWM2 mode. */
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */ @note This parameter is valid only for TIM1 and TIM8. */
@@ -122,8 +119,7 @@ typedef struct
/** /**
* @brief TIM One Pulse Mode Configuration Structure definition * @brief TIM One Pulse Mode Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t OCMode; /*!< Specifies the TIM mode. uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
@@ -155,12 +151,10 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_OnePulse_InitTypeDef; } TIM_OnePulse_InitTypeDef;
/** /**
* @brief TIM Input Capture Configuration Structure definition * @brief TIM Input Capture Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -177,8 +171,7 @@ typedef struct
/** /**
* @brief TIM Encoder Configuration Structure definition * @brief TIM Encoder Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Encoder_Mode */ This parameter can be a value of @ref TIM_Encoder_Mode */
@@ -207,12 +200,10 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_Encoder_InitTypeDef; } TIM_Encoder_InitTypeDef;
/** /**
* @brief TIM Clock Configuration Handle Structure definition * @brief TIM Clock Configuration Handle Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t ClockSource; /*!< TIM clock sources uint32_t ClockSource; /*!< TIM clock sources
This parameter can be a value of @ref TIM_Clock_Source */ This parameter can be a value of @ref TIM_Clock_Source */
uint32_t ClockPolarity; /*!< TIM clock polarity uint32_t ClockPolarity; /*!< TIM clock polarity
@@ -221,13 +212,12 @@ typedef struct
This parameter can be a value of @ref TIM_Clock_Prescaler */ This parameter can be a value of @ref TIM_Clock_Prescaler */
uint32_t ClockFilter; /*!< TIM clock filter uint32_t ClockFilter; /*!< TIM clock filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_ClockConfigTypeDef; } TIM_ClockConfigTypeDef;
/** /**
* @brief TIM Clear Input Configuration Handle Structure definition * @brief TIM Clear Input Configuration Handle Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t ClearInputState; /*!< TIM clear Input state uint32_t ClearInputState; /*!< TIM clear Input state
This parameter can be ENABLE or DISABLE */ This parameter can be ENABLE or DISABLE */
uint32_t ClearInputSource; /*!< TIM clear Input sources uint32_t ClearInputSource; /*!< TIM clear Input sources
@@ -238,7 +228,7 @@ typedef struct
This parameter can be a value of @ref TIM_ClearInput_Prescaler */ This parameter can be a value of @ref TIM_ClearInput_Prescaler */
uint32_t ClearInputFilter; /*!< TIM Clear Input filter uint32_t ClearInputFilter; /*!< TIM Clear Input filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_ClearInputConfigTypeDef; } TIM_ClearInputConfigTypeDef;
/** /**
* @brief TIM Slave configuration Structure definition * @brief TIM Slave configuration Structure definition
@@ -255,45 +245,42 @@ typedef struct {
uint32_t TriggerFilter; /*!< Input trigger filter uint32_t TriggerFilter; /*!< Input trigger filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_SlaveConfigTypeDef; } TIM_SlaveConfigTypeDef;
/** /**
* @brief HAL State structures definition * @brief HAL State structures definition
*/ */
typedef enum typedef enum {
{
HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
}HAL_TIM_StateTypeDef; } HAL_TIM_StateTypeDef;
/** /**
* @brief HAL Active channel structures definition * @brief HAL Active channel structures definition
*/ */
typedef enum typedef enum {
{
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
}HAL_TIM_ActiveChannel; } HAL_TIM_ActiveChannel;
/** /**
* @brief TIM Time Base Handle Structure definition * @brief TIM Time Base Handle Structure definition
*/ */
typedef struct typedef struct {
{ TIM_TypeDef * Instance; /*!< Register base address */
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7U]; /*!< DMA Handlers array DMA_HandleTypeDef * hdma[7U]; /*!< DMA Handlers array
This array is accessed by a @ref TIM_DMA_Handle_index */ This array is accessed by a @ref TIM_DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */ HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
}TIM_HandleTypeDef; } TIM_HandleTypeDef;
/** /**
* @} * @}
@@ -468,9 +455,11 @@ typedef struct
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{ * @{
*/ */
#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be #define TIM_ICSELECTION_DIRECTTI \
(TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
connected to IC1, IC2, IC3 or IC4, respectively */ connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be #define TIM_ICSELECTION_INDIRECTTI \
(TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
connected to IC2, IC1, IC4 or IC3, respectively */ connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/** /**
@@ -887,225 +876,123 @@ typedef struct
* @{ * @{
*/ */
#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ #define IS_TIM_COUNTER_MODE(MODE) \
((MODE) == TIM_COUNTERMODE_DOWN) || \ (((MODE) == TIM_COUNTERMODE_UP) || ((MODE) == TIM_COUNTERMODE_DOWN) || ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \
((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ || ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || ((DIV) == TIM_CLOCKDIVISION_DIV2) || ((DIV) == TIM_CLOCKDIVISION_DIV4))
((DIV) == TIM_CLOCKDIVISION_DIV2) || \
((DIV) == TIM_CLOCKDIVISION_DIV4))
#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2))
((MODE) == TIM_OCMODE_PWM2))
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ #define IS_TIM_OC_MODE(MODE) \
((MODE) == TIM_OCMODE_ACTIVE) || \ (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_FORCED_ACTIVE) \
((MODE) == TIM_OCMODE_INACTIVE) || \ || ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
((MODE) == TIM_OCMODE_TOGGLE) || \
((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
((MODE) == TIM_OCMODE_FORCED_INACTIVE))
#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || ((STATE) == TIM_OCFAST_ENABLE))
((STATE) == TIM_OCFAST_ENABLE))
#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || ((POLARITY) == TIM_OCPOLARITY_LOW))
((POLARITY) == TIM_OCPOLARITY_LOW))
#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || ((POLARITY) == TIM_OCNPOLARITY_LOW))
((POLARITY) == TIM_OCNPOLARITY_LOW))
#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || ((STATE) == TIM_OCIDLESTATE_RESET))
((STATE) == TIM_OCIDLESTATE_RESET))
#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || ((STATE) == TIM_OCNIDLESTATE_RESET))
((STATE) == TIM_OCNIDLESTATE_RESET))
#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4) || ((CHANNEL) == TIM_CHANNEL_ALL))
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_ALL))
#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))
((CHANNEL) == TIM_CHANNEL_2))
#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3))
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || ((SELECTION) == TIM_ICSELECTION_TRC))
((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
((SELECTION) == TIM_ICSELECTION_TRC))
#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || ((PRESCALER) == TIM_ICPSC_DIV2) || ((PRESCALER) == TIM_ICPSC_DIV4) || ((PRESCALER) == TIM_ICPSC_DIV8))
((PRESCALER) == TIM_ICPSC_DIV2) || \
((PRESCALER) == TIM_ICPSC_DIV4) || \
((PRESCALER) == TIM_ICPSC_DIV8))
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPETITIVE))
((MODE) == TIM_OPMODE_REPETITIVE))
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || ((MODE) == TIM_ENCODERMODE_TI2) || ((MODE) == TIM_ENCODERMODE_TI12))
((MODE) == TIM_ENCODERMODE_TI2) || \
((MODE) == TIM_ENCODERMODE_TI12))
#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE)&0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE)&0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ #define IS_TIM_CLOCKSOURCE(CLOCK) \
((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || ((CLOCK) == TIM_CLOCKSOURCE_ITR2) \
((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ || ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || ((CLOCK) == TIM_CLOCKSOURCE_TI1) || ((CLOCK) == TIM_CLOCKSOURCE_TI2) || ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ #define IS_TIM_CLOCKPOLARITY(POLARITY) \
((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \
((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ || ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ #define IS_TIM_CLOCKPRESCALER(PRESCALER) \
((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) \
((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || ((STATE) == TIM_OSSR_DISABLE))
((STATE) == TIM_OSSR_DISABLE))
#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || ((STATE) == TIM_OSSI_DISABLE))
((STATE) == TIM_OSSI_DISABLE))
#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || ((LEVEL) == TIM_LOCKLEVEL_1) || ((LEVEL) == TIM_LOCKLEVEL_2) || ((LEVEL) == TIM_LOCKLEVEL_3))
((LEVEL) == TIM_LOCKLEVEL_1) || \
((LEVEL) == TIM_LOCKLEVEL_2) || \
((LEVEL) == TIM_LOCKLEVEL_3))
#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || ((STATE) == TIM_BREAK_DISABLE))
((STATE) == TIM_BREAK_DISABLE))
#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
((POLARITY) == TIM_BREAKPOLARITY_HIGH))
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ #define IS_TIM_TRGO_SOURCE(SOURCE) \
((SOURCE) == TIM_TRGO_ENABLE) || \ (((SOURCE) == TIM_TRGO_RESET) || ((SOURCE) == TIM_TRGO_ENABLE) || ((SOURCE) == TIM_TRGO_UPDATE) || ((SOURCE) == TIM_TRGO_OC1) || ((SOURCE) == TIM_TRGO_OC1REF) || ((SOURCE) == TIM_TRGO_OC2REF) \
((SOURCE) == TIM_TRGO_UPDATE) || \ || ((SOURCE) == TIM_TRGO_OC3REF) || ((SOURCE) == TIM_TRGO_OC4REF))
((SOURCE) == TIM_TRGO_OC1) || \
((SOURCE) == TIM_TRGO_OC1REF) || \
((SOURCE) == TIM_TRGO_OC2REF) || \
((SOURCE) == TIM_TRGO_OC3REF) || \
((SOURCE) == TIM_TRGO_OC4REF))
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ #define IS_TIM_SLAVE_MODE(MODE) \
((MODE) == TIM_SLAVEMODE_GATED) || \ (((MODE) == TIM_SLAVEMODE_DISABLE) || ((MODE) == TIM_SLAVEMODE_GATED) || ((MODE) == TIM_SLAVEMODE_RESET) || ((MODE) == TIM_SLAVEMODE_TRIGGER) || ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
((MODE) == TIM_SLAVEMODE_RESET) || \
((MODE) == TIM_SLAVEMODE_TRIGGER) || \
((MODE) == TIM_SLAVEMODE_EXTERNAL1))
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ #define IS_TIM_TRIGGER_SELECTION(SELECTION) \
((SELECTION) == TIM_TS_ITR1) || \ (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3) || ((SELECTION) == TIM_TS_TI1F_ED) || ((SELECTION) == TIM_TS_TI1FP1) \
((SELECTION) == TIM_TS_ITR2) || \ || ((SELECTION) == TIM_TS_TI2FP2) || ((SELECTION) == TIM_TS_ETRF))
((SELECTION) == TIM_TS_ITR3) || \
((SELECTION) == TIM_TS_TI1F_ED) || \
((SELECTION) == TIM_TS_TI1FP1) || \
((SELECTION) == TIM_TS_TI2FP2) || \
((SELECTION) == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) \
((SELECTION) == TIM_TS_ITR1) || \ (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3) || ((SELECTION) == TIM_TS_NONE))
((SELECTION) == TIM_TS_ITR2) || \
((SELECTION) == TIM_TS_ITR3) || \
((SELECTION) == TIM_TS_NONE))
#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ #define IS_TIM_TRIGGERPOLARITY(POLARITY) \
((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED) || ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || ((POLARITY) == TIM_TRIGGERPOLARITY_RISING) || ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING) \
((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ || ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE))
((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ #define IS_TIM_TRIGGERPRESCALER(PRESCALER) \
((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ #define IS_TIM_DMA_BASE(BASE) \
((BASE) == TIM_DMABASE_CR2) || \ (((BASE) == TIM_DMABASE_CR1) || ((BASE) == TIM_DMABASE_CR2) || ((BASE) == TIM_DMABASE_SMCR) || ((BASE) == TIM_DMABASE_DIER) || ((BASE) == TIM_DMABASE_SR) || ((BASE) == TIM_DMABASE_EGR) \
((BASE) == TIM_DMABASE_SMCR) || \ || ((BASE) == TIM_DMABASE_CCMR1) || ((BASE) == TIM_DMABASE_CCMR2) || ((BASE) == TIM_DMABASE_CCER) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) || ((BASE) == TIM_DMABASE_ARR) \
((BASE) == TIM_DMABASE_DIER) || \ || ((BASE) == TIM_DMABASE_RCR) || ((BASE) == TIM_DMABASE_CCR1) || ((BASE) == TIM_DMABASE_CCR2) || ((BASE) == TIM_DMABASE_CCR3) || ((BASE) == TIM_DMABASE_CCR4) || ((BASE) == TIM_DMABASE_BDTR) \
((BASE) == TIM_DMABASE_SR) || \ || ((BASE) == TIM_DMABASE_DCR))
((BASE) == TIM_DMABASE_EGR) || \
((BASE) == TIM_DMABASE_CCMR1) || \
((BASE) == TIM_DMABASE_CCMR2) || \
((BASE) == TIM_DMABASE_CCER) || \
((BASE) == TIM_DMABASE_CNT) || \
((BASE) == TIM_DMABASE_PSC) || \
((BASE) == TIM_DMABASE_ARR) || \
((BASE) == TIM_DMABASE_RCR) || \
((BASE) == TIM_DMABASE_CCR1) || \
((BASE) == TIM_DMABASE_CCR2) || \
((BASE) == TIM_DMABASE_CCR3) || \
((BASE) == TIM_DMABASE_CCR4) || \
((BASE) == TIM_DMABASE_BDTR) || \
((BASE) == TIM_DMABASE_DCR))
#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ #define IS_TIM_DMA_LENGTH(LENGTH) \
((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \
((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ || ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \
((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ || ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \
((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ || ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \
((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ || ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
@@ -1116,10 +1003,10 @@ typedef struct
* @retval None * @retval None
*/ */
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
/** @brief Reset TIM IC prescaler /** @brief Reset TIM IC prescaler
* @param __HANDLE__: TIM handle * @param __HANDLE__: TIM handle
@@ -1127,11 +1014,10 @@ typedef struct
* @retval None * @retval None
*/ */
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ (((__CHANNEL__) == TIM_CHANNEL_1) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
/** @brief Set TIM IC polarity /** @brief Set TIM IC polarity
* @param __HANDLE__: TIM handle * @param __HANDLE__: TIM handle
@@ -1140,10 +1026,10 @@ typedef struct
* @retval None * @retval None
*/ */
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) \
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P))) : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
/** @brief Reset TIM IC polarity /** @brief Reset TIM IC polarity
* @param __HANDLE__: TIM handle * @param __HANDLE__: TIM handle
@@ -1151,10 +1037,10 @@ typedef struct
* @retval None * @retval None
*/ */
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t) ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t) ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t) ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) \
((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) : ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
/** /**
* @} * @}
@@ -1170,7 +1056,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
/** /**
* @} * @}
*/ */
@@ -1191,14 +1077,14 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat
* @param __HANDLE__: TIM handle * @param __HANDLE__: TIM handle
* @retval None * @retval None
*/ */
#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= (TIM_CR1_CEN))
/** /**
* @brief Enable the TIM main Output. * @brief Enable the TIM main Output.
* @param __HANDLE__: TIM handle * @param __HANDLE__: TIM handle
* @retval None * @retval None
*/ */
#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR |= (TIM_BDTR_MOE))
/** /**
* @brief Disable the TIM peripheral. * @brief Disable the TIM peripheral.
@@ -1207,14 +1093,12 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat
*/ */
#define __HAL_TIM_DISABLE(__HANDLE__) \ #define __HAL_TIM_DISABLE(__HANDLE__) \
do { \ do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) { \
{ \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) { \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \ } \
} \ } \
} while(0U) } while (0U)
/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
channels have been disabled */ channels have been disabled */
/** /**
@@ -1225,14 +1109,12 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat
*/ */
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \ do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) { \
{ \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) { \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \ } \
} \ } \
} while(0U) } while (0U)
/** /**
* @brief Disable the TIM main Output. * @brief Disable the TIM main Output.
@@ -1327,7 +1209,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat
* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
* @retval The new state of __FLAG__ (TRUE or FALSE). * @retval The new state of __FLAG__ (TRUE or FALSE).
*/ */
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** /**
* @brief Clears the specified TIM interrupt flag. * @brief Clears the specified TIM interrupt flag.
@@ -1396,8 +1278,7 @@ mode.
* @param __COMPARE__: specifies the Capture Compare register new value. * @param __COMPARE__: specifies the Capture Compare register new value.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
/** /**
* @brief Gets the TIM Capture Compare Register value on runtime * @brief Gets the TIM Capture Compare Register value on runtime
@@ -1410,8 +1291,7 @@ mode.
* @arg TIM_CHANNEL_4: get capture/compare 4 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/ */
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
/** /**
* @brief Sets the TIM Counter Register value on runtime. * @brief Sets the TIM Counter Register value on runtime.
@@ -1426,8 +1306,7 @@ mode.
* @param __HANDLE__: TIM handle. * @param __HANDLE__: TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/ */
#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
((__HANDLE__)->Instance->CNT)
/** /**
* @brief Sets the TIM Autoreload Register value on runtime without calling * @brief Sets the TIM Autoreload Register value on runtime without calling
@@ -1437,18 +1316,17 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
do{ \ do { \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0U) } while (0U)
/** /**
* @brief Gets the TIM Autoreload Register value on runtime * @brief Gets the TIM Autoreload Register value on runtime
* @param __HANDLE__: TIM handle. * @param __HANDLE__: TIM handle.
* @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/ */
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
((__HANDLE__)->Instance->ARR)
/** /**
* @brief Sets the TIM Clock Division value on runtime without calling * @brief Sets the TIM Clock Division value on runtime without calling
@@ -1462,11 +1340,11 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
do{ \ do { \
(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0U) } while (0U)
/** /**
* @brief Gets the TIM Clock Division value on runtime * @brief Gets the TIM Clock Division value on runtime
@@ -1476,8 +1354,7 @@ mode.
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/ */
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/** /**
* @brief Sets the TIM Input Capture prescaler on runtime without calling * @brief Sets the TIM Input Capture prescaler on runtime without calling
@@ -1498,10 +1375,10 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
do{ \ do { \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
} while(0U) } while (0U)
/** /**
* @brief Gets the TIM Input Capture prescaler on runtime * @brief Gets the TIM Input Capture prescaler on runtime
@@ -1519,10 +1396,10 @@ mode.
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
*/ */
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ (((__CHANNEL__) == TIM_CHANNEL_1) \
((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \
(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
/** /**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
@@ -1532,8 +1409,7 @@ mode.
* enabled) * enabled)
* @retval None * @retval None
*/ */
#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= (TIM_CR1_URS))
((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
/** /**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
@@ -1546,8 +1422,7 @@ mode.
* (+) Update generation through the slave mode controller * (+) Update generation through the slave mode controller
* @retval None * @retval None
*/ */
#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_URS))
((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
/** /**
* @brief Sets the TIM Capture x input polarity on runtime. * @brief Sets the TIM Capture x input polarity on runtime.
@@ -1566,10 +1441,10 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
do{ \ do { \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0U) } while (0U)
/** /**
* @} * @}
@@ -1690,11 +1565,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
* @{ * @{
*/ */
/* Timer Encoder functions *****************************************************/ /* Timer Encoder functions *****************************************************/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */ /* Non-Blocking mode: Interrupt */
@@ -1721,20 +1596,18 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
* @{ * @{
*/ */
/* Control functions *********************************************************/ /* Control functions *********************************************************/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);

63
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h vendored
View File

@@ -38,7 +38,7 @@
#define __STM32F1xx_HAL_TIM_EX_H #define __STM32F1xx_HAL_TIM_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -57,13 +57,11 @@
* @{ * @{
*/ */
/** /**
* @brief TIM Hall sensor Configuration Structure definition * @brief TIM Hall sensor Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -77,16 +75,12 @@ typedef struct
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef; } TIM_HallSensor_InitTypeDef;
#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#if defined (STM32F100xB) || defined (STM32F100xE) || \
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** /**
* @brief TIM Break and Dead time configuration Structure definition * @brief TIM Break and Dead time configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t OffStateRunMode; /*!< TIM off state in run mode uint32_t OffStateRunMode; /*!< TIM off state in run mode
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
@@ -115,16 +109,14 @@ typedef struct {
This parameter can be a value of @ref TIM_Master_Mode_Selection */ This parameter can be a value of @ref TIM_Master_Mode_Selection */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection uint32_t MasterSlaveMode; /*!< Master/slave mode selection
This parameter can be a value of @ref TIM_Master_Slave_Mode */ This parameter can be a value of @ref TIM_Master_Slave_Mode */
}TIM_MasterConfigTypeDef; } TIM_MasterConfigTypeDef;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
* @{ * @{
*/ */
@@ -157,10 +149,10 @@ typedef struct {
* @retval None * @retval None
*/ */
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ (((__CHANNEL__) == TIM_CHANNEL_1) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
/** /**
* @brief Resets the TIM Output compare preload. * @brief Resets the TIM Output compare preload.
@@ -174,10 +166,10 @@ typedef struct {
* @retval None * @retval None
*/ */
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) \
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) : ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions /** @addtogroup TIMEx_Exported_Functions
@@ -188,13 +180,13 @@ typedef struct {
* @{ * @{
*/ */
/* Timer Hall Sensor functions **********************************************/ /* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */ /* Non-Blocking mode: Interrupt */
@@ -207,9 +199,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
* @} * @}
*/ */
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @addtogroup TIMEx_Exported_Functions_Group2 /** @addtogroup TIMEx_Exported_Functions_Group2
* @{ * @{
@@ -270,9 +260,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* @{ * @{
*/ */
/* Extended Control functions ************************************************/ /* Extended Control functions ************************************************/
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
@@ -280,7 +268,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_Bre
#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
/* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
/* defined(STM32F105xC) || defined(STM32F107xC) */ /* defined(STM32F105xC) || defined(STM32F107xC) */
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
/** /**
* @} * @}
*/ */
@@ -295,9 +283,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
* @} * @}
*/ */
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @addtogroup TIMEx_Exported_Functions_Group7 /** @addtogroup TIMEx_Exported_Functions_Group7
* @{ * @{
*/ */
@@ -317,12 +303,12 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/* Private functions----------------------------------------------------------*/ /* Private functions----------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{ * @{
*/ */
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
/* End of private functions --------------------------------------------------*/ /* End of private functions --------------------------------------------------*/
/** /**
@@ -337,7 +323,6 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
} }
#endif #endif
#endif /* __STM32F1xx_HAL_TIM_EX_H */ #endif /* __STM32F1xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

83
source/Core/BSP/Miniware/portmacro.h
View File

@@ -55,12 +55,12 @@ typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t; typedef long BaseType_t;
typedef unsigned long UBaseType_t; typedef unsigned long UBaseType_t;
#if( configUSE_16_BIT_TICKS == 1 ) #if (configUSE_16_BIT_TICKS == 1)
typedef uint16_t TickType_t; typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff #define portMAX_DELAY (TickType_t)0xffff
#else #else
typedef uint32_t TickType_t; typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL #define portMAX_DELAY (TickType_t)0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */ not need to be guarded with a critical section. */
@@ -69,27 +69,29 @@ typedef uint32_t TickType_t;
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Architecture specifics. */ /* Architecture specifics. */
#define portSTACK_GROWTH ( -1 ) #define portSTACK_GROWTH (-1)
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
#define portBYTE_ALIGNMENT 8 #define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Scheduler utilities. */ /* Scheduler utilities. */
#define portYIELD() \ #define portYIELD() \
{ \ { \
/* Set a PendSV to request a context switch. */ \ /* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
\ \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
within the specified behaviour for the architecture. */ \ within the specified behaviour for the architecture. */ \
__asm volatile( "dsb" ::: "memory" ); \ __asm volatile("dsb" ::: "memory"); \
__asm volatile( "isb" ); \ __asm volatile("isb"); \
} }
#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_INT_CTRL_REG (*((volatile uint32_t *)0xe000ed04))
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) #define portNVIC_PENDSVSET_BIT (1UL << 28UL)
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD() #define portEND_SWITCHING_ISR(xSwitchRequired) \
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) if (xSwitchRequired != pdFALSE) \
portYIELD()
#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Critical section management. */ /* Critical section management. */
@@ -107,14 +109,14 @@ extern void vPortExitCritical(void);
/* Task function macros as described on the FreeRTOS.org WEB site. These are /* Task function macros as described on the FreeRTOS.org WEB site. These are
not necessary for to use this port. They are defined so the common demo files not necessary for to use this port. They are defined so the common demo files
(which build with all the ports) will build. */ (which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */ /* Tickless idle/low power functionality. */
#ifndef portSUPPRESS_TICKS_AND_SLEEP #ifndef portSUPPRESS_TICKS_AND_SLEEP
extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime); extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime)
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@@ -126,33 +128,32 @@ extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Generic helper function. */ /* Generic helper function. */
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( __attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros(uint32_t ulBitmap) {
uint32_t ulBitmap) {
uint8_t ucReturn; uint8_t ucReturn;
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); __asm volatile("clz %0, %1" : "=r"(ucReturn) : "r"(ulBitmap) : "memory");
return ucReturn; return ucReturn;
} }
/* Check the configuration. */ /* Check the configuration. */
#if( configMAX_PRIORITIES > 32 ) #if (configMAX_PRIORITIES > 32)
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
#endif #endif
/* Store/clear the ready priorities in a bit map. */ /* Store/clear the ready priorities in a bit map. */
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) #define portRECORD_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) |= (1UL << (uxPriority))
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) #define portRESET_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) &= ~(1UL << (uxPriority))
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) #define portGET_HIGHEST_PRIORITY(uxTopPriority, uxReadyPriorities) uxTopPriority = (31UL - (uint32_t)ucPortCountLeadingZeros((uxReadyPriorities)))
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#ifdef configASSERT #ifdef configASSERT
void vPortValidateInterruptPriority( void ); void vPortValidateInterruptPriority(void);
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif #endif
@@ -162,7 +163,7 @@ void vPortValidateInterruptPriority( void );
#define portINLINE __inline #define portINLINE __inline
#ifndef portFORCE_INLINE #ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__(( always_inline)) #define portFORCE_INLINE inline __attribute__((always_inline))
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@@ -172,7 +173,7 @@ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) {
BaseType_t xReturn; BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */ /* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory");
if (ulCurrentInterrupt == 0) { if (ulCurrentInterrupt == 0) {
xReturn = pdFALSE; xReturn = pdFALSE;
@@ -188,14 +189,13 @@ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) {
portFORCE_INLINE static void vPortRaiseBASEPRI(void) { portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
uint32_t ulNewBASEPRI; uint32_t ulNewBASEPRI;
__asm volatile __asm volatile(" mov %0, %1 \n"
(
" mov %0, %1 \n"
" msr basepri, %0 \n" " msr basepri, %0 \n"
" isb \n" " isb \n"
" dsb \n" " dsb \n"
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" : "=r"(ulNewBASEPRI)
); : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
: "memory");
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@@ -203,15 +203,14 @@ portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) { portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) {
uint32_t ulOriginalBASEPRI, ulNewBASEPRI; uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile __asm volatile(" mrs %0, basepri \n"
(
" mrs %0, basepri \n"
" mov %1, %2 \n" " mov %1, %2 \n"
" msr basepri, %1 \n" " msr basepri, %1 \n"
" isb \n" " isb \n"
" dsb \n" " dsb \n"
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" : "=r"(ulOriginalBASEPRI), "=r"(ulNewBASEPRI)
); : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
: "memory");
/* This return will not be reached but is necessary to prevent compiler /* This return will not be reached but is necessary to prevent compiler
warnings. */ warnings. */
@@ -219,19 +218,13 @@ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) {
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { __asm volatile(" msr basepri, %0 " ::"r"(ulNewMaskValue) : "memory"); }
__asm volatile
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
);
}
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) #define portMEMORY_BARRIER() __asm volatile("" ::: "memory")
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* PORTMACRO_H */ #endif /* PORTMACRO_H */

7
source/Core/BSP/Pine64/FreeRTOSConfig.h
View File

@@ -1,8 +1,8 @@
#ifndef FREERTOS_CONFIG_H #ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H
#include <stdint.h>
#include "nuclei_sdk_soc.h" #include "nuclei_sdk_soc.h"
//RISC-V configuration #include <stdint.h>
// RISC-V configuration
#define USER_MODE_TASKS 0 #define USER_MODE_TASKS 0
#define configUSE_PREEMPTION 1 #define configUSE_PREEMPTION 1
@@ -67,8 +67,7 @@
/* Define to trap errors during development. */ /* Define to trap errors during development. */
#define configASSERT(x) \ #define configASSERT(x) \
if ((x) == 0) \ if ((x) == 0) { \
{ \
taskDISABLE_INTERRUPTS(); \ taskDISABLE_INTERRUPTS(); \
for (;;) \ for (;;) \
; \ ; \

20
source/Core/BSP/Pine64/IRQ.h
View File

@@ -25,16 +25,16 @@ void I2C0_EV_IRQHandler(void);
/* handle I2C0 error interrupt request */ /* handle I2C0 error interrupt request */
void I2C0_ER_IRQHandler(void); void I2C0_ER_IRQHandler(void);
typedef enum { typedef enum {
I2C_SEND_ADDRESS_FIRST = 0, //Sending slave address I2C_SEND_ADDRESS_FIRST = 0, // Sending slave address
I2C_CLEAR_ADDRESS_FLAG_FIRST, // Clear address send I2C_CLEAR_ADDRESS_FLAG_FIRST, // Clear address send
I2C_TRANSMIT_WRITE_READ_ADD, //Transmit the memory address to read/write from I2C_TRANSMIT_WRITE_READ_ADD, // Transmit the memory address to read/write from
I2C_SEND_ADDRESS_SECOND, //Send address again for read I2C_SEND_ADDRESS_SECOND, // Send address again for read
I2C_CLEAR_ADDRESS_FLAG_SECOND, //Clear address again I2C_CLEAR_ADDRESS_FLAG_SECOND, // Clear address again
I2C_TRANSMIT_DATA, //Transmit recieve data I2C_TRANSMIT_DATA, // Transmit recieve data
I2C_STOP, //Send stop I2C_STOP, // Send stop
I2C_ABORTED, // I2C_ABORTED, //
I2C_DONE,// I2C transfer is complete I2C_DONE, // I2C transfer is complete
I2C_START , I2C_START,
I2C_END, I2C_END,
I2C_OK, I2C_OK,
I2C_SEND_ADDRESS, I2C_SEND_ADDRESS,
@@ -44,8 +44,8 @@ extern volatile uint8_t i2c_slave_address;
extern volatile uint8_t i2c_read_process; extern volatile uint8_t i2c_read_process;
extern volatile uint8_t i2c_write_process; extern volatile uint8_t i2c_write_process;
extern volatile uint8_t i2c_error_code; extern volatile uint8_t i2c_error_code;
extern volatile uint8_t* i2c_write; extern volatile uint8_t *i2c_write;
extern volatile uint8_t* i2c_read; extern volatile uint8_t *i2c_read;
extern volatile uint16_t i2c_nbytes; extern volatile uint16_t i2c_nbytes;
extern volatile uint16_t i2c_write_dress; extern volatile uint16_t i2c_write_dress;
extern volatile uint16_t i2c_read_dress; extern volatile uint16_t i2c_read_dress;

1
source/Core/BSP/Pine64/Pins.h
View File

@@ -35,7 +35,6 @@
#define SDA_Pin BIT(7) #define SDA_Pin BIT(7)
#define SDA_GPIO_Port GPIOB #define SDA_GPIO_Port GPIOB
#define USB_DM_Pin BIT(11) #define USB_DM_Pin BIT(11)
#define USB_DM_LOW_GPIO_Port GPIOA #define USB_DM_LOW_GPIO_Port GPIOA

42
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_compatiable.h vendored
View File

@@ -22,7 +22,7 @@
* @brief ARM compatiable function definitions header file * @brief ARM compatiable function definitions header file
*/ */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ===== ARM Compatiable Functions ===== */ /* ===== ARM Compatiable Functions ===== */
@@ -68,13 +68,12 @@
* \return Saturated value * \return Saturated value
*/ */
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __SSAT(val, sat) __RV_SCLIP32((val), (sat-1)) #define __SSAT(val, sat) __RV_SCLIP32((val), (sat - 1))
#else #else
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) {
{
if ((sat >= 1U) && (sat <= 32U)) { if ((sat >= 1U) && (sat <= 32U)) {
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ; const int32_t min = -1 - max;
if (val > max) { if (val > max) {
return max; return max;
} else if (val < min) { } else if (val < min) {
@@ -93,10 +92,9 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
* \return Saturated value * \return Saturated value
*/ */
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __USAT(val, sat) __RV_UCLIP32((val), (sat-1)) #define __USAT(val, sat) __RV_UCLIP32((val), (sat - 1))
#else #else
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) {
{
if (sat <= 31U) { if (sat <= 31U) {
const uint32_t max = ((1U << sat) - 1U); const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max) { if (val > (int32_t)max) {
@@ -117,14 +115,10 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
* \param [in] value Value to reverse * \param [in] value Value to reverse
* \return Reversed value * \return Reversed value
*/ */
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) {
{
uint32_t result; uint32_t result;
result = ((value & 0xff000000) >> 24) result = ((value & 0xff000000) >> 24) | ((value & 0x00ff0000) >> 8) | ((value & 0x0000ff00) << 8) | ((value & 0x000000ff) << 24);
| ((value & 0x00ff0000) >> 8 )
| ((value & 0x0000ff00) << 8 )
| ((value & 0x000000ff) << 24);
return result; return result;
} }
@@ -135,13 +129,9 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
* \param [in] value Value to reverse * \param [in] value Value to reverse
* \return Reversed value * \return Reversed value
*/ */
__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) {
{
uint32_t result; uint32_t result;
result = ((value & 0xff000000) >> 8) result = ((value & 0xff000000) >> 8) | ((value & 0x00ff00000) << 8) | ((value & 0x0000ff00) >> 8) | ((value & 0x000000ff) << 8);
| ((value & 0x00ff00000) << 8 )
| ((value & 0x0000ff00) >> 8 )
| ((value & 0x000000ff) << 8) ;
return result; return result;
} }
@@ -154,8 +144,7 @@ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
* \param [in] value Value to reverse * \param [in] value Value to reverse
* \return Reversed value * \return Reversed value
*/ */
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) {
{
int16_t result; int16_t result;
result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8); result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8);
return result; return result;
@@ -169,8 +158,7 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
* \param [in] op2 Number of Bits to rotate(0-31) * \param [in] op2 Number of Bits to rotate(0-31)
* \return Rotated value * \return Rotated value
*/ */
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) {
{
op2 = op2 & 0x1F; op2 = op2 & 0x1F;
if (op2 == 0U) { if (op2 == 0U) {
return op1; return op1;
@@ -187,8 +175,7 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __RBIT(value) __RV_BITREVI((value), 31) #define __RBIT(value) __RV_BITREVI((value), 31)
#else #else
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) {
{
uint32_t result; uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
@@ -212,8 +199,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __CLZ(data) __RV_CLZ32(data) #define __CLZ(data) __RV_CLZ32(data)
#else #else
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) {
{
uint8_t ret = 0; uint8_t ret = 0;
uint32_t temp = ~data; uint32_t temp = ~data;
while (temp & 0x80000000) { while (temp & 0x80000000) {

541
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_base.h vendored
View File

File diff suppressed because it is too large Load Diff

26
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_cache.h vendored
View File

@@ -31,7 +31,7 @@
* * 1: Present * * 1: Present
*/ */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)
@@ -59,11 +59,8 @@
* - This \ref CSR_MCACHE_CTL register control I Cache enable. * - This \ref CSR_MCACHE_CTL register control I Cache enable.
* \sa * \sa
* - \ref DisableICache * - \ref DisableICache
*/ */
__STATIC_FORCEINLINE void EnableICache (void) __STATIC_FORCEINLINE void EnableICache(void) { __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); }
{
__RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
}
/** /**
* \brief Disable ICache * \brief Disable ICache
@@ -74,10 +71,7 @@ __STATIC_FORCEINLINE void EnableICache (void)
* \sa * \sa
* - \ref EnableICache * - \ref EnableICache
*/ */
__STATIC_FORCEINLINE void DisableICache (void) __STATIC_FORCEINLINE void DisableICache(void) { __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); }
{
__RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
}
/** @} */ /* End of Doxygen Group NMSIS_Core_ICache */ /** @} */ /* End of Doxygen Group NMSIS_Core_ICache */
#endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */ #endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */
@@ -96,11 +90,8 @@ __STATIC_FORCEINLINE void DisableICache (void)
* - This \ref CSR_MCACHE_CTL register control D Cache enable. * - This \ref CSR_MCACHE_CTL register control D Cache enable.
* \sa * \sa
* - \ref DisableDCache * - \ref DisableDCache
*/ */
__STATIC_FORCEINLINE void EnableDCache (void) __STATIC_FORCEINLINE void EnableDCache(void) { __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); }
{
__RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
}
/** /**
* \brief Disable DCache * \brief Disable DCache
@@ -111,10 +102,7 @@ __STATIC_FORCEINLINE void EnableDCache (void)
* \sa * \sa
* - \ref EnableDCache * - \ref EnableDCache
*/ */
__STATIC_FORCEINLINE void DisableDCache (void) __STATIC_FORCEINLINE void DisableDCache(void) { __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); }
{
__RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
}
/** @} */ /* End of Doxygen Group NMSIS_Core_DCache */ /** @} */ /* End of Doxygen Group NMSIS_Core_DCache */
#endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */ #endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */

1026
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_dsp.h vendored
View File

File diff suppressed because it is too large Load Diff

236
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_eclic.h vendored
View File

@@ -33,7 +33,7 @@
* *
*/ */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
@@ -48,13 +48,12 @@
/** /**
* \brief Union type to access CLICFG configure register. * \brief Union type to access CLICFG configure register.
*/ */
typedef union typedef union {
{
struct { struct {
uint8_t _reserved0:1; /*!< bit: 0 Overflow condition code flag */ uint8_t _reserved0 : 1; /*!< bit: 0 Overflow condition code flag */
uint8_t nlbits:4; /*!< bit: 29 Carry condition code flag */ uint8_t nlbits : 4; /*!< bit: 29 Carry condition code flag */
uint8_t _reserved1:2; /*!< bit: 30 Zero condition code flag */ uint8_t _reserved1 : 2; /*!< bit: 30 Zero condition code flag */
uint8_t _reserved2:1; /*!< bit: 31 Negative condition code flag */ uint8_t _reserved2 : 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint8_t w; /*!< Type used for byte access */ uint8_t w; /*!< Type used for byte access */
} CLICCFG_Type; } CLICCFG_Type;
@@ -64,10 +63,10 @@ typedef union
*/ */
typedef union { typedef union {
struct { struct {
uint32_t numint:13; /*!< bit: 0..12 number of maximum interrupt inputs supported */ uint32_t numint : 13; /*!< bit: 0..12 number of maximum interrupt inputs supported */
uint32_t version:8; /*!< bit: 13..20 20:17 for architecture version,16:13 for implementation version */ uint32_t version : 8; /*!< bit: 13..20 20:17 for architecture version,16:13 for implementation version */
uint32_t intctlbits:4; /*!< bit: 21..24 specifies how many hardware bits are actually implemented in the clicintctl registers */ uint32_t intctlbits : 4; /*!< bit: 21..24 specifies how many hardware bits are actually implemented in the clicintctl registers */
uint32_t _reserved0:8; /*!< bit: 25..31 Reserved */ uint32_t _reserved0 : 8; /*!< bit: 25..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */ uint32_t w; /*!< Type used for word access */
} CLICINFO_Type; } CLICINFO_Type;
@@ -142,7 +141,7 @@ typedef enum ECLIC_TRIGGER {
/* ECLIC Memory mapping of Device */ /* ECLIC Memory mapping of Device */
#define ECLIC_BASE __ECLIC_BASEADDR /*!< ECLIC Base Address */ #define ECLIC_BASE __ECLIC_BASEADDR /*!< ECLIC Base Address */
#define ECLIC ((CLIC_Type *) ECLIC_BASE) /*!< CLIC configuration struct */ #define ECLIC ((CLIC_Type *)ECLIC_BASE) /*!< CLIC configuration struct */
/** @} */ /* end of group NMSIS_Core_ECLIC_Registers */ /** @} */ /* end of group NMSIS_Core_ECLIC_Registers */
@@ -204,45 +203,45 @@ typedef enum IRQn {
#endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */ #endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */
#ifdef NMSIS_ECLIC_VIRTUAL #ifdef NMSIS_ECLIC_VIRTUAL
#ifndef NMSIS_ECLIC_VIRTUAL_HEADER_FILE #ifndef NMSIS_ECLIC_VIRTUAL_HEADER_FILE
#define NMSIS_ECLIC_VIRTUAL_HEADER_FILE "nmsis_eclic_virtual.h" #define NMSIS_ECLIC_VIRTUAL_HEADER_FILE "nmsis_eclic_virtual.h"
#endif #endif
#include NMSIS_ECLIC_VIRTUAL_HEADER_FILE #include NMSIS_ECLIC_VIRTUAL_HEADER_FILE
#else #else
#define ECLIC_SetCfgNlbits __ECLIC_SetCfgNlbits #define ECLIC_SetCfgNlbits __ECLIC_SetCfgNlbits
#define ECLIC_GetCfgNlbits __ECLIC_GetCfgNlbits #define ECLIC_GetCfgNlbits __ECLIC_GetCfgNlbits
#define ECLIC_GetInfoVer __ECLIC_GetInfoVer #define ECLIC_GetInfoVer __ECLIC_GetInfoVer
#define ECLIC_GetInfoCtlbits __ECLIC_GetInfoCtlbits #define ECLIC_GetInfoCtlbits __ECLIC_GetInfoCtlbits
#define ECLIC_GetInfoNum __ECLIC_GetInfoNum #define ECLIC_GetInfoNum __ECLIC_GetInfoNum
#define ECLIC_SetMth __ECLIC_SetMth #define ECLIC_SetMth __ECLIC_SetMth
#define ECLIC_GetMth __ECLIC_GetMth #define ECLIC_GetMth __ECLIC_GetMth
#define ECLIC_EnableIRQ __ECLIC_EnableIRQ #define ECLIC_EnableIRQ __ECLIC_EnableIRQ
#define ECLIC_GetEnableIRQ __ECLIC_GetEnableIRQ #define ECLIC_GetEnableIRQ __ECLIC_GetEnableIRQ
#define ECLIC_DisableIRQ __ECLIC_DisableIRQ #define ECLIC_DisableIRQ __ECLIC_DisableIRQ
#define ECLIC_SetPendingIRQ __ECLIC_SetPendingIRQ #define ECLIC_SetPendingIRQ __ECLIC_SetPendingIRQ
#define ECLIC_GetPendingIRQ __ECLIC_GetPendingIRQ #define ECLIC_GetPendingIRQ __ECLIC_GetPendingIRQ
#define ECLIC_ClearPendingIRQ __ECLIC_ClearPendingIRQ #define ECLIC_ClearPendingIRQ __ECLIC_ClearPendingIRQ
#define ECLIC_SetTrigIRQ __ECLIC_SetTrigIRQ #define ECLIC_SetTrigIRQ __ECLIC_SetTrigIRQ
#define ECLIC_GetTrigIRQ __ECLIC_GetTrigIRQ #define ECLIC_GetTrigIRQ __ECLIC_GetTrigIRQ
#define ECLIC_SetShvIRQ __ECLIC_SetShvIRQ #define ECLIC_SetShvIRQ __ECLIC_SetShvIRQ
#define ECLIC_GetShvIRQ __ECLIC_GetShvIRQ #define ECLIC_GetShvIRQ __ECLIC_GetShvIRQ
#define ECLIC_SetCtrlIRQ __ECLIC_SetCtrlIRQ #define ECLIC_SetCtrlIRQ __ECLIC_SetCtrlIRQ
#define ECLIC_GetCtrlIRQ __ECLIC_GetCtrlIRQ #define ECLIC_GetCtrlIRQ __ECLIC_GetCtrlIRQ
#define ECLIC_SetLevelIRQ __ECLIC_SetLevelIRQ #define ECLIC_SetLevelIRQ __ECLIC_SetLevelIRQ
#define ECLIC_GetLevelIRQ __ECLIC_GetLevelIRQ #define ECLIC_GetLevelIRQ __ECLIC_GetLevelIRQ
#define ECLIC_SetPriorityIRQ __ECLIC_SetPriorityIRQ #define ECLIC_SetPriorityIRQ __ECLIC_SetPriorityIRQ
#define ECLIC_GetPriorityIRQ __ECLIC_GetPriorityIRQ #define ECLIC_GetPriorityIRQ __ECLIC_GetPriorityIRQ
#endif /* NMSIS_ECLIC_VIRTUAL */ #endif /* NMSIS_ECLIC_VIRTUAL */
#ifdef NMSIS_VECTAB_VIRTUAL #ifdef NMSIS_VECTAB_VIRTUAL
#ifndef NMSIS_VECTAB_VIRTUAL_HEADER_FILE #ifndef NMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define NMSIS_VECTAB_VIRTUAL_HEADER_FILE "nmsis_vectab_virtual.h" #define NMSIS_VECTAB_VIRTUAL_HEADER_FILE "nmsis_vectab_virtual.h"
#endif #endif
#include NMSIS_VECTAB_VIRTUAL_HEADER_FILE #include NMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else #else
#define ECLIC_SetVector __ECLIC_SetVector #define ECLIC_SetVector __ECLIC_SetVector
#define ECLIC_GetVector __ECLIC_GetVector #define ECLIC_GetVector __ECLIC_GetVector
#endif /* (NMSIS_VECTAB_VIRTUAL) */ #endif /* (NMSIS_VECTAB_VIRTUAL) */
/** /**
@@ -255,10 +254,9 @@ typedef enum IRQn {
* \sa * \sa
* - \ref ECLIC_GetCfgNlbits * - \ref ECLIC_GetCfgNlbits
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits) __STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits) {
{
ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk; ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk;
ECLIC->CFG |= (uint8_t)((nlbits <<CLIC_CLICCFG_NLBIT_Pos) & CLIC_CLICCFG_NLBIT_Msk); ECLIC->CFG |= (uint8_t)((nlbits << CLIC_CLICCFG_NLBIT_Pos) & CLIC_CLICCFG_NLBIT_Msk);
} }
/** /**
@@ -271,10 +269,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits)
* \sa * \sa
* - \ref ECLIC_SetCfgNlbits * - \ref ECLIC_SetCfgNlbits
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void) { return ((uint32_t)((ECLIC->CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos)); }
{
return ((uint32_t)((ECLIC->CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos));
}
/** /**
* \brief Get the ECLIC version number * \brief Get the ECLIC version number
@@ -286,11 +281,8 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void)
* - Bit 20:17 for architecture version, bit 16:13 for implementation version. * - Bit 20:17 for architecture version, bit 16:13 for implementation version.
* \sa * \sa
* - \ref ECLIC_GetInfoNum * - \ref ECLIC_GetInfoNum
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos)); }
{
return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos));
}
/** /**
* \brief Get CLICINTCTLBITS * \brief Get CLICINTCTLBITS
@@ -304,10 +296,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void)
* \sa * \sa
* - \ref ECLIC_GetInfoNum * - \ref ECLIC_GetInfoNum
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos)); }
{
return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos));
}
/** /**
* \brief Get number of maximum interrupt inputs supported * \brief Get number of maximum interrupt inputs supported
@@ -320,10 +309,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void)
* \sa * \sa
* - \ref ECLIC_GetInfoCtlbits * - \ref ECLIC_GetInfoCtlbits
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos)); }
{
return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos));
}
/** /**
* \brief Set Machine Mode Interrupt Level Threshold * \brief Set Machine Mode Interrupt Level Threshold
@@ -333,10 +319,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void)
* \sa * \sa
* - \ref ECLIC_GetMth * - \ref ECLIC_GetMth
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth) __STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth) { ECLIC->MTH = mth; }
{
ECLIC->MTH = mth;
}
/** /**
* \brief Get Machine Mode Interrupt Level Threshold * \brief Get Machine Mode Interrupt Level Threshold
@@ -346,11 +329,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth)
* \sa * \sa
* - \ref ECLIC_SetMth * - \ref ECLIC_SetMth
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void) __STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void) { return (ECLIC->MTH); }
{
return (ECLIC->MTH);
}
/** /**
* \brief Enable a specific interrupt * \brief Enable a specific interrupt
@@ -362,10 +341,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void)
* \sa * \sa
* - \ref ECLIC_DisableIRQ * - \ref ECLIC_DisableIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk; }
{
ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk;
}
/** /**
* \brief Get a specific interrupt enable status * \brief Get a specific interrupt enable status
@@ -381,10 +357,7 @@ __STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn)
* - \ref ECLIC_EnableIRQ * - \ref ECLIC_EnableIRQ
* - \ref ECLIC_DisableIRQ * - \ref ECLIC_DisableIRQ
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn) { return ((uint32_t)(ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk); }
{
return((uint32_t) (ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk);
}
/** /**
* \brief Disable a specific interrupt * \brief Disable a specific interrupt
@@ -396,10 +369,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_EnableIRQ * - \ref ECLIC_EnableIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk; }
{
ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk;
}
/** /**
* \brief Get the pending specific interrupt * \brief Get the pending specific interrupt
@@ -415,10 +385,7 @@ __STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn)
* - \ref ECLIC_SetPendingIRQ * - \ref ECLIC_SetPendingIRQ
* - \ref ECLIC_ClearPendingIRQ * - \ref ECLIC_ClearPendingIRQ
*/ */
__STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk); }
{
return((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk);
}
/** /**
* \brief Set a specific interrupt to pending * \brief Set a specific interrupt to pending
@@ -431,10 +398,7 @@ __STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn)
* - \ref ECLIC_GetPendingIRQ * - \ref ECLIC_GetPendingIRQ
* - \ref ECLIC_ClearPendingIRQ * - \ref ECLIC_ClearPendingIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk; }
{
ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk;
}
/** /**
* \brief Clear a specific interrupt from pending * \brief Clear a specific interrupt from pending
@@ -448,10 +412,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn)
* - \ref ECLIC_SetPendingIRQ * - \ref ECLIC_SetPendingIRQ
* - \ref ECLIC_GetPendingIRQ * - \ref ECLIC_GetPendingIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIP &= ~CLIC_INTIP_IP_Msk; }
{
ECLIC->CTRL[IRQn].INTIP &= ~ CLIC_INTIP_IP_Msk;
}
/** /**
* \brief Set trigger mode and polarity for a specific interrupt * \brief Set trigger mode and polarity for a specific interrupt
@@ -469,10 +430,9 @@ __STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetTrigIRQ * - \ref ECLIC_GetTrigIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig) __STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig) {
{
ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk; ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk;
ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig<<CLIC_INTATTR_TRIG_Pos); ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig << CLIC_INTATTR_TRIG_Pos);
} }
/** /**
@@ -490,10 +450,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig)
* \sa * \sa
* - \ref ECLIC_SetTrigIRQ * - \ref ECLIC_SetTrigIRQ
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn) { return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk) >> CLIC_INTATTR_TRIG_Pos)); }
{
return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk)>>CLIC_INTATTR_TRIG_Pos));
}
/** /**
* \brief Set interrupt working mode for a specific interrupt * \brief Set interrupt working mode for a specific interrupt
@@ -508,10 +465,9 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetShvIRQ * - \ref ECLIC_GetShvIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv) __STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv) {
{
ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk; ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk;
ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv<<CLIC_INTATTR_SHV_Pos); ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv << CLIC_INTATTR_SHV_Pos);
} }
/** /**
@@ -527,10 +483,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv)
* \sa * \sa
* - \ref ECLIC_SetShvIRQ * - \ref ECLIC_SetShvIRQ
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn) { return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk) >> CLIC_INTATTR_SHV_Pos)); }
{
return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk)>>CLIC_INTATTR_SHV_Pos));
}
/** /**
* \brief Modify ECLIC Interrupt Input Control Register for a specific interrupt * \brief Modify ECLIC Interrupt Input Control Register for a specific interrupt
@@ -543,10 +496,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetCtrlIRQ * - \ref ECLIC_GetCtrlIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl) __STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl) { ECLIC->CTRL[IRQn].INTCTRL = intctrl; }
{
ECLIC->CTRL[IRQn].INTCTRL = intctrl;
}
/** /**
* \brief Get ECLIC Interrupt Input Control Register value for a specific interrupt * \brief Get ECLIC Interrupt Input Control Register value for a specific interrupt
@@ -559,10 +509,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl)
* \sa * \sa
* - \ref ECLIC_SetCtrlIRQ * - \ref ECLIC_SetCtrlIRQ
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn) { return (ECLIC->CTRL[IRQn].INTCTRL); }
{
return (ECLIC->CTRL[IRQn].INTCTRL);
}
/** /**
* \brief Set ECLIC Interrupt level of a specific interrupt * \brief Set ECLIC Interrupt level of a specific interrupt
@@ -579,8 +526,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetLevelIRQ * - \ref ECLIC_GetLevelIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs) __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs) {
{
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
@@ -613,8 +559,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)
* \sa * \sa
* - \ref ECLIC_SetLevelIRQ * - \ref ECLIC_SetLevelIRQ
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn) {
{
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
@@ -644,8 +589,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetPriorityIRQ * - \ref ECLIC_GetPriorityIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri) __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri) {
{
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
if (nlbits < intctlbits) { if (nlbits < intctlbits) {
@@ -674,8 +618,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)
* \sa * \sa
* - \ref ECLIC_SetPriorityIRQ * - \ref ECLIC_SetPriorityIRQ
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn) {
{
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
if (nlbits < intctlbits) { if (nlbits < intctlbits) {
@@ -705,20 +648,19 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetVector * - \ref ECLIC_GetVector
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) __STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) {
{
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
volatile uint32_t vec_base; volatile uint32_t vec_base;
vec_base = ((uint32_t)__RV_CSR_READ(CSR_MTVT)); vec_base = ((uint32_t)__RV_CSR_READ(CSR_MTVT));
(* (unsigned long *) (vec_base + ((int32_t)IRQn) * 4)) = vector; (*(unsigned long *)(vec_base + ((int32_t)IRQn) * 4)) = vector;
#elif __RISCV_XLEN == 64 #elif __RISCV_XLEN == 64
volatile uint64_t vec_base; volatile uint64_t vec_base;
vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT)); vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT));
(* (unsigned long *) (vec_base + ((int32_t)IRQn) * 8)) = vector; (*(unsigned long *)(vec_base + ((int32_t)IRQn) * 8)) = vector;
#else // TODO Need cover for XLEN=128 case in future #else // TODO Need cover for XLEN=128 case in future
volatile uint64_t vec_base; volatile uint64_t vec_base;
vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT)); vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT));
(* (unsigned long *) (vec_base + ((int32_t)IRQn) * 8)) = vector; (*(unsigned long *)(vec_base + ((int32_t)IRQn) * 8)) = vector;
#endif #endif
} }
@@ -734,14 +676,13 @@ __STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector)
* \sa * \sa
* - \ref ECLIC_SetVector * - \ref ECLIC_SetVector
*/ */
__STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) __STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) {
{
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*4)); return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 4));
#elif __RISCV_XLEN == 64 #elif __RISCV_XLEN == 64
return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*8)); return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 8));
#else // TODO Need cover for XLEN=128 case in future #else // TODO Need cover for XLEN=128 case in future
return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*8)); return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 8));
#endif #endif
} }
@@ -755,8 +696,7 @@ __STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn)
* \sa * \sa
* - \ref __get_exc_entry * - \ref __get_exc_entry
*/ */
__STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) __STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) {
{
addr &= (rv_csr_t)(~0x3F); addr &= (rv_csr_t)(~0x3F);
addr |= ECLIC_MODE_MTVEC_Msk; addr |= ECLIC_MODE_MTVEC_Msk;
__RV_CSR_WRITE(CSR_MTVEC, addr); __RV_CSR_WRITE(CSR_MTVEC, addr);
@@ -772,8 +712,7 @@ __STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr)
* \sa * \sa
* - \ref __set_exc_entry * - \ref __set_exc_entry
*/ */
__STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void) __STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void) {
{
unsigned long addr = __RV_CSR_READ(CSR_MTVEC); unsigned long addr = __RV_CSR_READ(CSR_MTVEC);
return (addr & ~ECLIC_MODE_MTVEC_Msk); return (addr & ~ECLIC_MODE_MTVEC_Msk);
} }
@@ -789,9 +728,8 @@ __STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void)
* \sa * \sa
* - \ref __get_nonvec_entry * - \ref __get_nonvec_entry
*/ */
__STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr) __STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr) {
{ if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
if (__RV_CSR_READ(CSR_MTVT2) & 0x1){
__RV_CSR_WRITE(CSR_MTVT2, addr | 0x01); __RV_CSR_WRITE(CSR_MTVT2, addr | 0x01);
} else { } else {
addr &= (rv_csr_t)(~0x3F); addr &= (rv_csr_t)(~0x3F);
@@ -811,8 +749,7 @@ __STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr)
* \sa * \sa
* - \ref __set_nonvec_entry * - \ref __set_nonvec_entry
*/ */
__STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void) __STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void) {
{
if (__RV_CSR_READ(CSR_MTVT2) & 0x1) { if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1)); return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1));
} else { } else {
@@ -831,10 +768,7 @@ __STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void)
* - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector. * - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector.
* - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored. * - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored.
*/ */
__STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void) __STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void) { return __RV_CSR_READ(CSR_MNVEC); }
{
return __RV_CSR_READ(CSR_MNVEC);
}
/** /**
* \brief Save necessary CSRs into variables for vector interrupt nesting * \brief Save necessary CSRs into variables for vector interrupt nesting

27
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_fpu.h vendored
View File

@@ -29,7 +29,7 @@
* * 2: Double precision FPU present, __RISCV_FLEN == 64 * * 2: Double precision FPU present, __RISCV_FLEN == 64
*/ */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ===== FPU Operations ===== */ /* ===== FPU Operations ===== */
@@ -53,12 +53,12 @@
#if defined(__FPU_PRESENT) && (__FPU_PRESENT > 0) #if defined(__FPU_PRESENT) && (__FPU_PRESENT > 0)
#if __FPU_PRESENT == 1 #if __FPU_PRESENT == 1
/** \brief Refer to the width of the floating point register in bits(either 32 or 64) */ /** \brief Refer to the width of the floating point register in bits(either 32 or 64) */
#define __RISCV_FLEN 32 #define __RISCV_FLEN 32
#elif __FPU_PRESENT == 2 #elif __FPU_PRESENT == 2
#define __RISCV_FLEN 64 #define __RISCV_FLEN 64
#else #else
#define __RISCV_FLEN __riscv_flen #define __RISCV_FLEN __riscv_flen
#endif /* __FPU_PRESENT == 1 */ #endif /* __FPU_PRESENT == 1 */
/** \brief Get FCSR CSR Register */ /** \brief Get FCSR CSR Register */
@@ -85,7 +85,6 @@
* */ * */
#define __disable_FPU() __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS) #define __disable_FPU() __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS)
/** /**
* \brief Load a single-precision value from memory into float point register freg using flw instruction * \brief Load a single-precision value from memory into float point register freg using flw instruction
* \details The FLW instruction loads a single-precision floating point value from memory * \details The FLW instruction loads a single-precision floating point value from memory
@@ -103,9 +102,7 @@
#define __RV_FLW(freg, addr, ofs) \ #define __RV_FLW(freg, addr, ofs) \
({ \ ({ \
register rv_csr_t __addr = (rv_csr_t)(addr); \ register rv_csr_t __addr = (rv_csr_t)(addr); \
__ASM volatile("flw " STRINGIFY(freg) ", %0(%1) " \ __ASM volatile("flw " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \
: : "I"(ofs), "r"(__addr) \
: "memory"); \
}) })
/** /**
@@ -124,9 +121,7 @@
#define __RV_FSW(freg, addr, ofs) \ #define __RV_FSW(freg, addr, ofs) \
({ \ ({ \
register rv_csr_t __addr = (rv_csr_t)(addr); \ register rv_csr_t __addr = (rv_csr_t)(addr); \
__ASM volatile("fsw " STRINGIFY(freg) ", %0(%1) " \ __ASM volatile("fsw " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \
: : "I"(ofs), "r"(__addr) \
: "memory"); \
}) })
/** /**
@@ -147,9 +142,7 @@
#define __RV_FLD(freg, addr, ofs) \ #define __RV_FLD(freg, addr, ofs) \
({ \ ({ \
register rv_csr_t __addr = (rv_csr_t)(addr); \ register rv_csr_t __addr = (rv_csr_t)(addr); \
__ASM volatile("fld " STRINGIFY(freg) ", %0(%1) " \ __ASM volatile("fld " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \
: : "I"(ofs), "r"(__addr) \
: "memory"); \
}) })
/** /**
@@ -170,9 +163,7 @@
#define __RV_FSD(freg, addr, ofs) \ #define __RV_FSD(freg, addr, ofs) \
({ \ ({ \
register rv_csr_t __addr = (rv_csr_t)(addr); \ register rv_csr_t __addr = (rv_csr_t)(addr); \
__ASM volatile("fsd " STRINGIFY(freg) ", %0(%1) " \ __ASM volatile("fsd " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \
: : "I"(ofs), "r"(__addr) \
: "memory"); \
}) })
/** /**

190
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_pmp.h vendored
View File

@@ -29,7 +29,7 @@
* 2. __PMP_ENTRY_NUM: Define the number of PMP entries, only 8 or 16 is configurable. * 2. __PMP_ENTRY_NUM: Define the number of PMP entries, only 8 or 16 is configurable.
*/ */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined(__PMP_PRESENT) && (__PMP_PRESENT == 1) #if defined(__PMP_PRESENT) && (__PMP_PRESENT == 1)
@@ -58,18 +58,18 @@
* \param [in] idx PMP region index(0-15) * \param [in] idx PMP region index(0-15)
* \return PMPxCFG Register value * \return PMPxCFG Register value
*/ */
__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx) __STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx) {
{
rv_csr_t pmpcfg = 0; rv_csr_t pmpcfg = 0;
if (idx >= __PMP_ENTRY_NUM) return 0; if (idx >= __PMP_ENTRY_NUM)
return 0;
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
if (idx < 4) { if (idx < 4) {
pmpcfg = __RV_CSR_READ(CSR_PMPCFG0); pmpcfg = __RV_CSR_READ(CSR_PMPCFG0);
} else if ((idx >=4) && (idx < 8)) { } else if ((idx >= 4) && (idx < 8)) {
idx -= 4; idx -= 4;
pmpcfg = __RV_CSR_READ(CSR_PMPCFG1); pmpcfg = __RV_CSR_READ(CSR_PMPCFG1);
} else if ((idx >=8) && (idx < 12)) { } else if ((idx >= 8) && (idx < 12)) {
idx -= 8; idx -= 8;
pmpcfg = __RV_CSR_READ(CSR_PMPCFG2); pmpcfg = __RV_CSR_READ(CSR_PMPCFG2);
} else { } else {
@@ -78,7 +78,7 @@ __STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
} }
idx = idx << 3; idx = idx << 3;
return (uint8_t)((pmpcfg>>idx) & 0xFF); return (uint8_t)((pmpcfg >> idx) & 0xFF);
#elif __RISCV_XLEN == 64 #elif __RISCV_XLEN == 64
if (idx < 8) { if (idx < 8) {
pmpcfg = __RV_CSR_READ(CSR_PMPCFG0); pmpcfg = __RV_CSR_READ(CSR_PMPCFG0);
@@ -87,7 +87,7 @@ __STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
pmpcfg = __RV_CSR_READ(CSR_PMPCFG2); pmpcfg = __RV_CSR_READ(CSR_PMPCFG2);
} }
idx = idx << 3; idx = idx << 3;
return (uint8_t)((pmpcfg>>idx) & 0xFF); return (uint8_t)((pmpcfg >> idx) & 0xFF);
#else #else
// TODO Add RV128 Handling // TODO Add RV128 Handling
return 0; return 0;
@@ -100,10 +100,10 @@ __STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
* \param [in] idx PMPx region index(0-15) * \param [in] idx PMPx region index(0-15)
* \param [in] pmpxcfg PMPxCFG register value to set * \param [in] pmpxcfg PMPxCFG register value to set
*/ */
__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg) __STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg) {
{
rv_csr_t pmpcfgx = 0; rv_csr_t pmpcfgx = 0;
if (idx >= __PMP_ENTRY_NUM) return; if (idx >= __PMP_ENTRY_NUM)
return;
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
if (idx < 4) { if (idx < 4) {
@@ -111,13 +111,13 @@ __STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg)
idx = idx << 3; idx = idx << 3;
pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx); pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx);
__RV_CSR_WRITE(CSR_PMPCFG0, pmpcfgx); __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfgx);
} else if ((idx >=4) && (idx < 8)) { } else if ((idx >= 4) && (idx < 8)) {
idx -= 4; idx -= 4;
pmpcfgx = __RV_CSR_READ(CSR_PMPCFG1); pmpcfgx = __RV_CSR_READ(CSR_PMPCFG1);
idx = idx << 3; idx = idx << 3;
pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx); pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx);
__RV_CSR_WRITE(CSR_PMPCFG1, pmpcfgx); __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfgx);
} else if ((idx >=8) && (idx < 12)) { } else if ((idx >= 8) && (idx < 12)) {
idx -= 8; idx -= 8;
pmpcfgx = __RV_CSR_READ(CSR_PMPCFG2); pmpcfgx = __RV_CSR_READ(CSR_PMPCFG2);
idx = idx << 3; idx = idx << 3;
@@ -160,14 +160,18 @@ __STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg)
* - For RV32, pmpcfg0–pmpcfg3, hold the configurations * - For RV32, pmpcfg0–pmpcfg3, hold the configurations
* pmp0cfg–pmp15cfg for the 16 PMP entries * pmp0cfg–pmp15cfg for the 16 PMP entries
*/ */
__STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx) __STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx) {
{
switch (idx) { switch (idx) {
case 0: return __RV_CSR_READ(CSR_PMPCFG0); case 0:
case 1: return __RV_CSR_READ(CSR_PMPCFG1); return __RV_CSR_READ(CSR_PMPCFG0);
case 2: return __RV_CSR_READ(CSR_PMPCFG2); case 1:
case 3: return __RV_CSR_READ(CSR_PMPCFG3); return __RV_CSR_READ(CSR_PMPCFG1);
default: return 0; case 2:
return __RV_CSR_READ(CSR_PMPCFG2);
case 3:
return __RV_CSR_READ(CSR_PMPCFG3);
default:
return 0;
} }
} }
@@ -183,14 +187,22 @@ __STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx)
* - For RV32, pmpcfg0–pmpcfg3, hold the configurations * - For RV32, pmpcfg0–pmpcfg3, hold the configurations
* pmp0cfg–pmp15cfg for the 16 PMP entries * pmp0cfg–pmp15cfg for the 16 PMP entries
*/ */
__STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg) __STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg) {
{
switch (idx) { switch (idx) {
case 0: __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg); break; case 0:
case 1: __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg); break; __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg);
case 2: __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg); break; break;
case 3: __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg); break; case 1:
default: return; __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg);
break;
case 2:
__RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg);
break;
case 3:
__RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg);
break;
default:
return;
} }
} }
@@ -200,26 +212,42 @@ __STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg)
* \param [in] idx PMP region index(0-15) * \param [in] idx PMP region index(0-15)
* \return PMPADDRx Register value * \return PMPADDRx Register value
*/ */
__STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx) __STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx) {
{
switch (idx) { switch (idx) {
case 0: return __RV_CSR_READ(CSR_PMPADDR0); case 0:
case 1: return __RV_CSR_READ(CSR_PMPADDR1); return __RV_CSR_READ(CSR_PMPADDR0);
case 2: return __RV_CSR_READ(CSR_PMPADDR2); case 1:
case 3: return __RV_CSR_READ(CSR_PMPADDR3); return __RV_CSR_READ(CSR_PMPADDR1);
case 4: return __RV_CSR_READ(CSR_PMPADDR4); case 2:
case 5: return __RV_CSR_READ(CSR_PMPADDR5); return __RV_CSR_READ(CSR_PMPADDR2);
case 6: return __RV_CSR_READ(CSR_PMPADDR6); case 3:
case 7: return __RV_CSR_READ(CSR_PMPADDR7); return __RV_CSR_READ(CSR_PMPADDR3);
case 8: return __RV_CSR_READ(CSR_PMPADDR8); case 4:
case 9: return __RV_CSR_READ(CSR_PMPADDR9); return __RV_CSR_READ(CSR_PMPADDR4);
case 10: return __RV_CSR_READ(CSR_PMPADDR10); case 5:
case 11: return __RV_CSR_READ(CSR_PMPADDR11); return __RV_CSR_READ(CSR_PMPADDR5);
case 12: return __RV_CSR_READ(CSR_PMPADDR12); case 6:
case 13: return __RV_CSR_READ(CSR_PMPADDR13); return __RV_CSR_READ(CSR_PMPADDR6);
case 14: return __RV_CSR_READ(CSR_PMPADDR14); case 7:
case 15: return __RV_CSR_READ(CSR_PMPADDR15); return __RV_CSR_READ(CSR_PMPADDR7);
default: return 0; case 8:
return __RV_CSR_READ(CSR_PMPADDR8);
case 9:
return __RV_CSR_READ(CSR_PMPADDR9);
case 10:
return __RV_CSR_READ(CSR_PMPADDR10);
case 11:
return __RV_CSR_READ(CSR_PMPADDR11);
case 12:
return __RV_CSR_READ(CSR_PMPADDR12);
case 13:
return __RV_CSR_READ(CSR_PMPADDR13);
case 14:
return __RV_CSR_READ(CSR_PMPADDR14);
case 15:
return __RV_CSR_READ(CSR_PMPADDR15);
default:
return 0;
} }
} }
@@ -229,26 +257,58 @@ __STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx)
* \param [in] idx PMP region index(0-15) * \param [in] idx PMP region index(0-15)
* \param [in] pmpaddr PMPADDRx Register value to set * \param [in] pmpaddr PMPADDRx Register value to set
*/ */
__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, rv_csr_t pmpaddr) __STATIC_INLINE void __set_PMPADDRx(uint32_t idx, rv_csr_t pmpaddr) {
{
switch (idx) { switch (idx) {
case 0: __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr); break; case 0:
case 1: __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr); break; __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr);
case 2: __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr); break; break;
case 3: __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr); break; case 1:
case 4: __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr); break; __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr);
case 5: __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr); break; break;
case 6: __RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr); break; case 2:
case 7: __RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr); break; __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr);
case 8: __RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr); break; break;
case 9: __RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr); break; case 3:
case 10: __RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr); break; __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr);
case 11: __RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr); break; break;
case 12: __RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr); break; case 4:
case 13: __RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr); break; __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr);
case 14: __RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr); break; break;
case 15: __RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr); break; case 5:
default: return; __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr);
break;
case 6:
__RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr);
break;
case 7:
__RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr);
break;
case 8:
__RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr);
break;
case 9:
__RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr);
break;
case 10:
__RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr);
break;
case 11:
__RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr);
break;
case 12:
__RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr);
break;
case 13:
__RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr);
break;
case 14:
__RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr);
break;
case 15:
__RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr);
break;
default:
return;
} }
} }
/** @} */ /* End of Doxygen Group NMSIS_Core_PMP_Functions */ /** @} */ /* End of Doxygen Group NMSIS_Core_PMP_Functions */

79
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_timer.h vendored
View File

@@ -29,7 +29,7 @@
* 2. __SYSTIMER_BASEADDR: Define the base address of the System Timer. * 2. __SYSTIMER_BASEADDR: Define the base address of the System Timer.
*/ */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) #if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1)
@@ -84,7 +84,7 @@ typedef struct {
#endif #endif
/* System Timer Memory mapping of Device */ /* System Timer Memory mapping of Device */
#define SysTimer_BASE __SYSTIMER_BASEADDR /*!< SysTick Base Address */ #define SysTimer_BASE __SYSTIMER_BASEADDR /*!< SysTick Base Address */
#define SysTimer ((SysTimer_Type *) SysTimer_BASE) /*!< SysTick configuration struct */ #define SysTimer ((SysTimer_Type *)SysTimer_BASE) /*!< SysTick configuration struct */
/** @} */ /* end of group NMSIS_Core_SysTimer_Registers */ /** @} */ /* end of group NMSIS_Core_SysTimer_Registers */
/* ################################## SysTimer function ############################################ */ /* ################################## SysTimer function ############################################ */
@@ -102,10 +102,7 @@ typedef struct {
* - Load value is 64bits wide. * - Load value is 64bits wide.
* - \ref SysTimer_GetLoadValue * - \ref SysTimer_GetLoadValue
*/ */
__STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value) __STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value) { SysTimer->MTIMER = value; }
{
SysTimer->MTIMER = value;
}
/** /**
* \brief Get system timer load value * \brief Get system timer load value
@@ -116,10 +113,7 @@ __STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value)
* - Load value is 64bits wide. * - Load value is 64bits wide.
* - \ref SysTimer_SetLoadValue * - \ref SysTimer_SetLoadValue
*/ */
__STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void) __STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void) { return SysTimer->MTIMER; }
{
return SysTimer->MTIMER;
}
/** /**
* \brief Set system timer compare value * \brief Set system timer compare value
@@ -132,10 +126,7 @@ __STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void)
* - Modify the load value or compare value less to clear the interrupt. * - Modify the load value or compare value less to clear the interrupt.
* - \ref SysTimer_GetCompareValue * - \ref SysTimer_GetCompareValue
*/ */
__STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) __STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) { SysTimer->MTIMERCMP = value; }
{
SysTimer->MTIMERCMP = value;
}
/** /**
* \brief Get system timer compare value * \brief Get system timer compare value
@@ -146,10 +137,7 @@ __STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value)
* - Compare value is 64bits wide. * - Compare value is 64bits wide.
* - \ref SysTimer_SetCompareValue * - \ref SysTimer_SetCompareValue
*/ */
__STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void) __STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void) { return SysTimer->MTIMERCMP; }
{
return SysTimer->MTIMERCMP;
}
/** /**
* \brief Enable system timer counter running * \brief Enable system timer counter running
@@ -157,10 +145,7 @@ __STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void)
* Enable system timer counter running by clear * Enable system timer counter running by clear
* TIMESTOP bit in MTIMECTL register. * TIMESTOP bit in MTIMECTL register.
*/ */
__STATIC_FORCEINLINE void SysTimer_Start(void) __STATIC_FORCEINLINE void SysTimer_Start(void) { SysTimer->MTIMECTL &= ~(SysTimer_MTIMECTL_TIMESTOP_Msk); }
{
SysTimer->MTIMECTL &= ~(SysTimer_MTIMECTL_TIMESTOP_Msk);
}
/** /**
* \brief Stop system timer counter running * \brief Stop system timer counter running
@@ -168,10 +153,7 @@ __STATIC_FORCEINLINE void SysTimer_Start(void)
* Stop system timer counter running by set * Stop system timer counter running by set
* TIMESTOP bit in MTIMECTL register. * TIMESTOP bit in MTIMECTL register.
*/ */
__STATIC_FORCEINLINE void SysTimer_Stop(void) __STATIC_FORCEINLINE void SysTimer_Stop(void) { SysTimer->MTIMECTL |= SysTimer_MTIMECTL_TIMESTOP_Msk; }
{
SysTimer->MTIMECTL |= SysTimer_MTIMECTL_TIMESTOP_Msk;
}
/** /**
* \brief Set system timer control value * \brief Set system timer control value
@@ -187,10 +169,7 @@ __STATIC_FORCEINLINE void SysTimer_Stop(void)
* Clear CLKSRC bit to 0 to use *mtime_toggle_a*, otherwise use *core_clk_aon* * Clear CLKSRC bit to 0 to use *mtime_toggle_a*, otherwise use *core_clk_aon*
* - \ref SysTimer_GetControlValue * - \ref SysTimer_GetControlValue
*/ */
__STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl) __STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl) { SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk); }
{
SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk);
}
/** /**
* \brief Get system timer control value * \brief Get system timer control value
@@ -200,10 +179,7 @@ __STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl)
* \remarks * \remarks
* - \ref SysTimer_SetControlValue * - \ref SysTimer_SetControlValue
*/ */
__STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void) __STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void) { return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk); }
{
return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk);
}
/** /**
* \brief Trigger or set software interrupt via system timer * \brief Trigger or set software interrupt via system timer
@@ -214,10 +190,7 @@ __STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void)
* - \ref SysTimer_ClearSWIRQ * - \ref SysTimer_ClearSWIRQ
* - \ref SysTimer_GetMsipValue * - \ref SysTimer_GetMsipValue
*/ */
__STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void) __STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void) { SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk; }
{
SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk;
}
/** /**
* \brief Clear system timer software interrupt pending request * \brief Clear system timer software interrupt pending request
@@ -228,10 +201,7 @@ __STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void)
* - \ref SysTimer_SetSWIRQ * - \ref SysTimer_SetSWIRQ
* - \ref SysTimer_GetMsipValue * - \ref SysTimer_GetMsipValue
*/ */
__STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void) __STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void) { SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk; }
{
SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk;
}
/** /**
* \brief Get system timer MSIP register value * \brief Get system timer MSIP register value
@@ -244,10 +214,7 @@ __STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void)
* - \ref SysTimer_SetSWIRQ * - \ref SysTimer_SetSWIRQ
* - \ref SysTimer_ClearSWIRQ * - \ref SysTimer_ClearSWIRQ
*/ */
__STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void) __STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void) { return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk); }
{
return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk);
}
/** /**
* \brief Set system timer MSIP register value * \brief Set system timer MSIP register value
@@ -255,10 +222,7 @@ __STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void)
* This function set the system timer MSIP register value. * This function set the system timer MSIP register value.
* \param [in] msip value to set MSIP register * \param [in] msip value to set MSIP register
*/ */
__STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip) __STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip) { SysTimer->MSIP = (msip & SysTimer_MSIP_Msk); }
{
SysTimer->MSIP = (msip & SysTimer_MSIP_Msk);
}
/** /**
* \brief Do software reset request * \brief Do software reset request
@@ -270,13 +234,13 @@ __STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip)
* - The software reset is sent to SoC, SoC need to generate reset signal and send back to Core * - The software reset is sent to SoC, SoC need to generate reset signal and send back to Core
* - This function will not return, it will do while(1) to wait the Core reset happened * - This function will not return, it will do while(1) to wait the Core reset happened
*/ */
__STATIC_FORCEINLINE void SysTimer_SoftwareReset(void) __STATIC_FORCEINLINE void SysTimer_SoftwareReset(void) {
{
SysTimer->MSFTRST = SysTimer_MSFRST_KEY; SysTimer->MSFTRST = SysTimer_MSFRST_KEY;
while(1); while (1)
;
} }
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) && defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) #if defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) && defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
/** /**
* \brief System Tick Configuration * \brief System Tick Configuration
* \details Initializes the System Timer and its non-vector interrupt, and starts the System Tick Timer. * \details Initializes the System Timer and its non-vector interrupt, and starts the System Tick Timer.
@@ -301,8 +265,7 @@ __STATIC_FORCEINLINE void SysTimer_SoftwareReset(void)
* \sa * \sa
* - \ref SysTimer_SetCompareValue; SysTimer_SetLoadValue * - \ref SysTimer_SetCompareValue; SysTimer_SetLoadValue
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks) {
{
SysTimer_SetLoadValue(0); SysTimer_SetLoadValue(0);
SysTimer_SetCompareValue(ticks); SysTimer_SetCompareValue(ticks);
ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT); ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
@@ -334,8 +297,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks)
* - \ref SysTimer_SetCompareValue * - \ref SysTimer_SetCompareValue
* - \ref SysTimer_SetLoadValue * - \ref SysTimer_SetLoadValue
*/ */
__STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks) __STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks) {
{
uint64_t cur_ticks = SysTimer->MTIMER; uint64_t cur_ticks = SysTimer->MTIMER;
uint64_t reload_ticks = ticks + cur_ticks; uint64_t reload_ticks = ticks + cur_ticks;
@@ -361,4 +323,3 @@ __STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks)
} }
#endif #endif
#endif /** __CORE_FEATURE_TIMER_H__ */ #endif /** __CORE_FEATURE_TIMER_H__ */

10
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_compiler.h vendored
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@@ -25,13 +25,11 @@
* @file nmsis_compiler.h * @file nmsis_compiler.h
* @brief NMSIS compiler generic header file * @brief NMSIS compiler generic header file
*/ */
#if defined ( __GNUC__ ) #if defined(__GNUC__)
/** GNU GCC Compiler */ /** GNU GCC Compiler */
#include "nmsis_gcc.h" #include "nmsis_gcc.h"
#else #else
#error Unknown compiler. #error Unknown compiler.
#endif #endif
#endif /* __NMSIS_COMPILER_H */ #endif /* __NMSIS_COMPILER_H */

2
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_core.h vendored
View File

@@ -23,7 +23,7 @@
#include <stdint.h> #include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "nmsis_version.h" #include "nmsis_version.h"

123
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_gcc.h vendored
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@@ -22,11 +22,11 @@
* @file nmsis_gcc.h * @file nmsis_gcc.h
* @brief NMSIS compiler GCC header file * @brief NMSIS compiler GCC header file
*/ */
#include <stdint.h>
#include "riscv_encoding.h" #include "riscv_encoding.h"
#include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* ######################### Startup and Lowlevel Init ######################## */ /* ######################### Startup and Lowlevel Init ######################## */
@@ -50,145 +50,137 @@
/* Fallback for __has_builtin */ /* Fallback for __has_builtin */
#ifndef __has_builtin #ifndef __has_builtin
#define __has_builtin(x) (0) #define __has_builtin(x) (0)
#endif #endif
/* NMSIS compiler specific defines */ /* NMSIS compiler specific defines */
/** \brief Pass information from the compiler to the assembler. */ /** \brief Pass information from the compiler to the assembler. */
#ifndef __ASM #ifndef __ASM
#define __ASM __asm #define __ASM __asm
#endif #endif
/** \brief Recommend that function should be inlined by the compiler. */ /** \brief Recommend that function should be inlined by the compiler. */
#ifndef __INLINE #ifndef __INLINE
#define __INLINE inline #define __INLINE inline
#endif #endif
/** \brief Define a static function that may be inlined by the compiler. */ /** \brief Define a static function that may be inlined by the compiler. */
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
/** \brief Define a static function that should be always inlined by the compiler. */ /** \brief Define a static function that should be always inlined by the compiler. */
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif #endif
/** \brief Inform the compiler that a function does not return. */ /** \brief Inform the compiler that a function does not return. */
#ifndef __NO_RETURN #ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__)) #define __NO_RETURN __attribute__((__noreturn__))
#endif #endif
/** \brief Inform that a variable shall be retained in executable image. */ /** \brief Inform that a variable shall be retained in executable image. */
#ifndef __USED #ifndef __USED
#define __USED __attribute__((used)) #define __USED __attribute__((used))
#endif #endif
/** \brief restrict pointer qualifier to enable additional optimizations. */ /** \brief restrict pointer qualifier to enable additional optimizations. */
#ifndef __WEAK #ifndef __WEAK
#define __WEAK __attribute__((weak)) #define __WEAK __attribute__((weak))
#endif #endif
/** \brief specified the vector size of the variable, measured in bytes */ /** \brief specified the vector size of the variable, measured in bytes */
#ifndef __VECTOR_SIZE #ifndef __VECTOR_SIZE
#define __VECTOR_SIZE(x) __attribute__((vector_size(x))) #define __VECTOR_SIZE(x) __attribute__((vector_size(x)))
#endif #endif
/** \brief Request smallest possible alignment. */ /** \brief Request smallest possible alignment. */
#ifndef __PACKED #ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1))) #define __PACKED __attribute__((packed, aligned(1)))
#endif #endif
/** \brief Request smallest possible alignment for a structure. */ /** \brief Request smallest possible alignment for a structure. */
#ifndef __PACKED_STRUCT #ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif #endif
/** \brief Request smallest possible alignment for a union. */ /** \brief Request smallest possible alignment for a union. */
#ifndef __PACKED_UNION #ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1))) #define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
#pragma GCC diagnostic push #pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes" #pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint16_t write access */ /** \brief Packed struct for unaligned uint16_t write access */
__PACKED_STRUCT T_UINT16_WRITE { __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
uint16_t v; #pragma GCC diagnostic pop
}; /** \brief Pointer for unaligned write of a uint16_t variable. */
#pragma GCC diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
/** \brief Pointer for unaligned write of a uint16_t variable. */
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT16_READ #ifndef __UNALIGNED_UINT16_READ
#pragma GCC diagnostic push #pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes" #pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint16_t read access */ /** \brief Packed struct for unaligned uint16_t read access */
__PACKED_STRUCT T_UINT16_READ { __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
uint16_t v; #pragma GCC diagnostic pop
}; /** \brief Pointer for unaligned read of a uint16_t variable. */
#pragma GCC diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
/** \brief Pointer for unaligned read of a uint16_t variable. */
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __UNALIGNED_UINT32_WRITE #ifndef __UNALIGNED_UINT32_WRITE
#pragma GCC diagnostic push #pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes" #pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint32_t write access */ /** \brief Packed struct for unaligned uint32_t write access */
__PACKED_STRUCT T_UINT32_WRITE { __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
uint32_t v; #pragma GCC diagnostic pop
}; /** \brief Pointer for unaligned write of a uint32_t variable. */
#pragma GCC diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
/** \brief Pointer for unaligned write of a uint32_t variable. */
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT32_READ #ifndef __UNALIGNED_UINT32_READ
#pragma GCC diagnostic push #pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes" #pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint32_t read access */ /** \brief Packed struct for unaligned uint32_t read access */
__PACKED_STRUCT T_UINT32_READ { __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
uint32_t v; #pragma GCC diagnostic pop
}; /** \brief Pointer for unaligned read of a uint32_t variable. */
#pragma GCC diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
/** \brief Pointer for unaligned read of a uint32_t variable. */
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif #endif
/** \brief Minimum `x` bytes alignment for a variable. */ /** \brief Minimum `x` bytes alignment for a variable. */
#ifndef __ALIGNED #ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x))) #define __ALIGNED(x) __attribute__((aligned(x)))
#endif #endif
/** \brief restrict pointer qualifier to enable additional optimizations. */ /** \brief restrict pointer qualifier to enable additional optimizations. */
#ifndef __RESTRICT #ifndef __RESTRICT
#define __RESTRICT __restrict #define __RESTRICT __restrict
#endif #endif
/** \brief Barrier to prevent compiler from reordering instructions. */ /** \brief Barrier to prevent compiler from reordering instructions. */
#ifndef __COMPILER_BARRIER #ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory") #define __COMPILER_BARRIER() __ASM volatile("" ::: "memory")
#endif #endif
/** \brief provide the compiler with branch prediction information, the branch is usually true */ /** \brief provide the compiler with branch prediction information, the branch is usually true */
#ifndef __USUALLY #ifndef __USUALLY
#define __USUALLY(exp) __builtin_expect((exp), 1) #define __USUALLY(exp) __builtin_expect((exp), 1)
#endif #endif
/** \brief provide the compiler with branch prediction information, the branch is rarely true */ /** \brief provide the compiler with branch prediction information, the branch is rarely true */
#ifndef __RARELY #ifndef __RARELY
#define __RARELY(exp) __builtin_expect((exp), 0) #define __RARELY(exp) __builtin_expect((exp), 0)
#endif #endif
/** \brief Use this attribute to indicate that the specified function is an interrupt handler. */ /** \brief Use this attribute to indicate that the specified function is an interrupt handler. */
#ifndef __INTERRUPT #ifndef __INTERRUPT
#define __INTERRUPT __attribute__((interrupt)) #define __INTERRUPT __attribute__((interrupt))
#endif #endif
/** @} */ /* End of Doxygen Group NMSIS_Core_CompilerControl */ /** @} */ /* End of Doxygen Group NMSIS_Core_CompilerControl */
@@ -209,9 +201,9 @@
*/ */
/** \brief Defines 'read only' permissions */ /** \brief Defines 'read only' permissions */
#ifdef __cplusplus #ifdef __cplusplus
#define __I volatile #define __I volatile
#else #else
#define __I volatile const #define __I volatile const
#endif #endif
/** \brief Defines 'write only' permissions */ /** \brief Defines 'write only' permissions */
#define __O volatile #define __O volatile
@@ -239,7 +231,7 @@
* \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. * \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
* \return Masked and shifted value. * \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) (((uint32_t)(value) << field##_Pos) & field##_Msk)
/** /**
* \brief Mask and shift a register value to extract a bit filed value. * \brief Mask and shift a register value to extract a bit filed value.
@@ -254,10 +246,9 @@
* \param[in] value Value of register. This parameter is interpreted as an uint32_t type. * \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
* \return Masked and shifted bit field value. * \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) (((uint32_t)(value)&field##_Msk) >> field##_Pos)
/** @} */ /* end of group NMSIS_Core_PeriphAccess */
/** @} */ /* end of group NMSIS_Core_PeriphAccess */
#ifdef __cplusplus #ifdef __cplusplus
} }

50
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/riscv_bits.h vendored
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@@ -19,43 +19,43 @@
#define __RISCV_BITS_H__ #define __RISCV_BITS_H__
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if __riscv_xlen == 64 #if __riscv_xlen == 64
# define SLL32 sllw #define SLL32 sllw
# define STORE sd #define STORE sd
# define LOAD ld #define LOAD ld
# define LWU lwu #define LWU lwu
# define LOG_REGBYTES 3 #define LOG_REGBYTES 3
#else #else
# define SLL32 sll #define SLL32 sll
# define STORE sw #define STORE sw
# define LOAD lw #define LOAD lw
# define LWU lw #define LWU lw
# define LOG_REGBYTES 2 #define LOG_REGBYTES 2
#endif /* __riscv_xlen */ #endif /* __riscv_xlen */
#define REGBYTES (1 << LOG_REGBYTES) #define REGBYTES (1 << LOG_REGBYTES)
#ifdef __riscv_flen #ifdef __riscv_flen
#if __riscv_flen == 64 #if __riscv_flen == 64
# define FPSTORE fsd #define FPSTORE fsd
# define FPLOAD fld #define FPLOAD fld
# define LOG_FPREGBYTES 3 #define LOG_FPREGBYTES 3
#else #else
# define FPSTORE fsw #define FPSTORE fsw
# define FPLOAD flw #define FPLOAD flw
# define LOG_FPREGBYTES 2 #define LOG_FPREGBYTES 2
#endif /* __riscv_flen */ #endif /* __riscv_flen */
#endif #endif
#define FPREGBYTES (1 << LOG_FPREGBYTES) #define FPREGBYTES (1 << LOG_FPREGBYTES)
#define __rv_likely(x) __builtin_expect((x), 1) #define __rv_likely(x) __builtin_expect((x), 1)
#define __rv_unlikely(x) __builtin_expect((x), 0) #define __rv_unlikely(x) __builtin_expect((x), 0)
#define __RV_ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) #define __RV_ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))
#define __RV_ROUNDDOWN(a, b) ((a)/(b)*(b)) #define __RV_ROUNDDOWN(a, b) ((a) / (b) * (b))
#define __RV_MAX(a, b) ((a) > (b) ? (a) : (b)) #define __RV_MAX(a, b) ((a) > (b) ? (a) : (b))
#define __RV_MIN(a, b) ((a) < (b) ? (a) : (b)) #define __RV_MIN(a, b) ((a) < (b) ? (a) : (b))
@@ -65,12 +65,12 @@
#define __RV_INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) #define __RV_INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
#ifdef __ASSEMBLY__ #ifdef __ASSEMBLY__
#define _AC(X,Y) X #define _AC(X, Y) X
#define _AT(T,X) X #define _AT(T, X) X
#else #else
#define __AC(X,Y) (X##Y) #define __AC(X, Y) (X##Y)
#define _AC(X,Y) __AC(X,Y) #define _AC(X, Y) __AC(X, Y)
#define _AT(T,X) ((T)(X)) #define _AT(T, X) ((T)(X))
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#define _UL(x) (_AC(x, UL)) #define _UL(x) (_AC(x, UL))

163
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/riscv_encoding.h vendored
View File

@@ -20,7 +20,7 @@
#include "riscv_bits.h" #include "riscv_bits.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** /**
* \defgroup NMSIS_Core_CSR_Encoding Core CSR Encodings * \defgroup NMSIS_Core_CSR_Encoding Core CSR Encodings
@@ -68,20 +68,20 @@
#define CSR_MCACHE_CTL_IE 0x00000001 #define CSR_MCACHE_CTL_IE 0x00000001
#define CSR_MCACHE_CTL_DE 0x00010000 #define CSR_MCACHE_CTL_DE 0x00010000
#define DCSR_XDEBUGVER (3U<<30) #define DCSR_XDEBUGVER (3U << 30)
#define DCSR_NDRESET (1<<29) #define DCSR_NDRESET (1 << 29)
#define DCSR_FULLRESET (1<<28) #define DCSR_FULLRESET (1 << 28)
#define DCSR_EBREAKM (1<<15) #define DCSR_EBREAKM (1 << 15)
#define DCSR_EBREAKH (1<<14) #define DCSR_EBREAKH (1 << 14)
#define DCSR_EBREAKS (1<<13) #define DCSR_EBREAKS (1 << 13)
#define DCSR_EBREAKU (1<<12) #define DCSR_EBREAKU (1 << 12)
#define DCSR_STOPCYCLE (1<<10) #define DCSR_STOPCYCLE (1 << 10)
#define DCSR_STOPTIME (1<<9) #define DCSR_STOPTIME (1 << 9)
#define DCSR_CAUSE (7<<6) #define DCSR_CAUSE (7 << 6)
#define DCSR_DEBUGINT (1<<5) #define DCSR_DEBUGINT (1 << 5)
#define DCSR_HALT (1<<3) #define DCSR_HALT (1 << 3)
#define DCSR_STEP (1<<2) #define DCSR_STEP (1 << 2)
#define DCSR_PRV (3<<0) #define DCSR_PRV (3 << 0)
#define DCSR_CAUSE_NONE 0 #define DCSR_CAUSE_NONE 0
#define DCSR_CAUSE_SWBP 1 #define DCSR_CAUSE_SWBP 1
@@ -90,22 +90,22 @@
#define DCSR_CAUSE_STEP 4 #define DCSR_CAUSE_STEP 4
#define DCSR_CAUSE_HALT 5 #define DCSR_CAUSE_HALT 5
#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) #define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4))
#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) #define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5))
#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) #define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11))
#define MCONTROL_SELECT (1<<19) #define MCONTROL_SELECT (1 << 19)
#define MCONTROL_TIMING (1<<18) #define MCONTROL_TIMING (1 << 18)
#define MCONTROL_ACTION (0x3f<<12) #define MCONTROL_ACTION (0x3f << 12)
#define MCONTROL_CHAIN (1<<11) #define MCONTROL_CHAIN (1 << 11)
#define MCONTROL_MATCH (0xf<<7) #define MCONTROL_MATCH (0xf << 7)
#define MCONTROL_M (1<<6) #define MCONTROL_M (1 << 6)
#define MCONTROL_H (1<<5) #define MCONTROL_H (1 << 5)
#define MCONTROL_S (1<<4) #define MCONTROL_S (1 << 4)
#define MCONTROL_U (1<<3) #define MCONTROL_U (1 << 3)
#define MCONTROL_EXECUTE (1<<2) #define MCONTROL_EXECUTE (1 << 2)
#define MCONTROL_STORE (1<<1) #define MCONTROL_STORE (1 << 1)
#define MCONTROL_LOAD (1<<0) #define MCONTROL_LOAD (1 << 0)
#define MCONTROL_TYPE_NONE 0 #define MCONTROL_TYPE_NONE 0
#define MCONTROL_TYPE_MATCH 2 #define MCONTROL_TYPE_MATCH 2
@@ -149,59 +149,59 @@
#define TXEVT_TXEVT (0x1) #define TXEVT_TXEVT (0x1)
#define SLEEPVALUE_SLEEPVALUE (0x1) #define SLEEPVALUE_SLEEPVALUE (0x1)
#define MCOUNTINHIBIT_IR (1<<2) #define MCOUNTINHIBIT_IR (1 << 2)
#define MCOUNTINHIBIT_CY (1<<0) #define MCOUNTINHIBIT_CY (1 << 0)
#define MILM_CTL_ILM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) #define MILM_CTL_ILM_BPA (((1ULL << ((__riscv_xlen)-10)) - 1) << 10)
#define MILM_CTL_ILM_EN (1<<0) #define MILM_CTL_ILM_EN (1 << 0)
#define MDLM_CTL_DLM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) #define MDLM_CTL_DLM_BPA (((1ULL << ((__riscv_xlen)-10)) - 1) << 10)
#define MDLM_CTL_DLM_EN (1<<0) #define MDLM_CTL_DLM_EN (1 << 0)
#define MSUBM_PTYP (0x3<<8) #define MSUBM_PTYP (0x3 << 8)
#define MSUBM_TYP (0x3<<6) #define MSUBM_TYP (0x3 << 6)
#define MDCAUSE_MDCAUSE (0x3) #define MDCAUSE_MDCAUSE (0x3)
#define MMISC_CTL_NMI_CAUSE_FFF (1<<9) #define MMISC_CTL_NMI_CAUSE_FFF (1 << 9)
#define MMISC_CTL_MISALIGN (1<<6) #define MMISC_CTL_MISALIGN (1 << 6)
#define MMISC_CTL_BPU (1<<3) #define MMISC_CTL_BPU (1 << 3)
#define MCACHE_CTL_IC_EN (1<<0) #define MCACHE_CTL_IC_EN (1 << 0)
#define MCACHE_CTL_IC_SCPD_MOD (1<<1) #define MCACHE_CTL_IC_SCPD_MOD (1 << 1)
#define MCACHE_CTL_DC_EN (1<<16) #define MCACHE_CTL_DC_EN (1 << 16)
#define MTVT2_MTVT2EN (1<<0) #define MTVT2_MTVT2EN (1 << 0)
#define MTVT2_COMMON_CODE_ENTRY (((1ULL<<((__riscv_xlen)-2))-1)<<2) #define MTVT2_COMMON_CODE_ENTRY (((1ULL << ((__riscv_xlen)-2)) - 1) << 2)
#define MCFG_INFO_TEE (1<<0) #define MCFG_INFO_TEE (1 << 0)
#define MCFG_INFO_ECC (1<<1) #define MCFG_INFO_ECC (1 << 1)
#define MCFG_INFO_CLIC (1<<2) #define MCFG_INFO_CLIC (1 << 2)
#define MCFG_INFO_PLIC (1<<3) #define MCFG_INFO_PLIC (1 << 3)
#define MCFG_INFO_FIO (1<<4) #define MCFG_INFO_FIO (1 << 4)
#define MCFG_INFO_PPI (1<<5) #define MCFG_INFO_PPI (1 << 5)
#define MCFG_INFO_NICE (1<<6) #define MCFG_INFO_NICE (1 << 6)
#define MCFG_INFO_ILM (1<<7) #define MCFG_INFO_ILM (1 << 7)
#define MCFG_INFO_DLM (1<<8) #define MCFG_INFO_DLM (1 << 8)
#define MCFG_INFO_ICACHE (1<<9) #define MCFG_INFO_ICACHE (1 << 9)
#define MCFG_INFO_DCACHE (1<<10) #define MCFG_INFO_DCACHE (1 << 10)
#define MICFG_IC_SET (0xF<<0) #define MICFG_IC_SET (0xF << 0)
#define MICFG_IC_WAY (0x7<<4) #define MICFG_IC_WAY (0x7 << 4)
#define MICFG_IC_LSIZE (0x7<<7) #define MICFG_IC_LSIZE (0x7 << 7)
#define MICFG_ILM_SIZE (0x1F<<16) #define MICFG_ILM_SIZE (0x1F << 16)
#define MICFG_ILM_XONLY (1<<21) #define MICFG_ILM_XONLY (1 << 21)
#define MDCFG_DC_SET (0xF<<0) #define MDCFG_DC_SET (0xF << 0)
#define MDCFG_DC_WAY (0x7<<4) #define MDCFG_DC_WAY (0x7 << 4)
#define MDCFG_DC_LSIZE (0x7<<7) #define MDCFG_DC_LSIZE (0x7 << 7)
#define MDCFG_DLM_SIZE (0x1F<<16) #define MDCFG_DLM_SIZE (0x1F << 16)
#define MPPICFG_INFO_PPI_SIZE (0x1F<<1) #define MPPICFG_INFO_PPI_SIZE (0x1F << 1)
#define MPPICFG_INFO_PPI_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) #define MPPICFG_INFO_PPI_BPA (((1ULL << ((__riscv_xlen)-10)) - 1) << 10)
#define MFIOCFG_INFO_FIO_SIZE (0x1F<<1) #define MFIOCFG_INFO_FIO_SIZE (0x1F << 1)
#define MFIOCFG_INFO_FIO_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) #define MFIOCFG_INFO_FIO_BPA (((1ULL << ((__riscv_xlen)-10)) - 1) << 10)
#define SIP_SSIP MIP_SSIP #define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP #define SIP_STIP MIP_STIP
@@ -255,20 +255,19 @@
/* === FPU FFLAGS Accrued Exceptions === */ /* === FPU FFLAGS Accrued Exceptions === */
/** FPU Inexact */ /** FPU Inexact */
#define FFLAGS_AE_NX (1<<0) #define FFLAGS_AE_NX (1 << 0)
/** FPU Underflow */ /** FPU Underflow */
#define FFLAGS_AE_UF (1<<1) #define FFLAGS_AE_UF (1 << 1)
/** FPU Overflow */ /** FPU Overflow */
#define FFLAGS_AE_OF (1<<2) #define FFLAGS_AE_OF (1 << 2)
/** FPU Divide by Zero */ /** FPU Divide by Zero */
#define FFLAGS_AE_DZ (1<<3) #define FFLAGS_AE_DZ (1 << 3)
/** FPU Invalid Operation */ /** FPU Invalid Operation */
#define FFLAGS_AE_NV (1<<4) #define FFLAGS_AE_NV (1 << 4)
/** Floating Point Register f0-f31, eg. f0 -> FREG(0) */ /** Floating Point Register f0-f31, eg. f0 -> FREG(0) */
#define FREG(idx) f##idx #define FREG(idx) f##idx
/* === PMP CFG Bits === */ /* === PMP CFG Bits === */
#define PMP_R 0x01 #define PMP_R 0x01
#define PMP_W 0x02 #define PMP_W 0x02
@@ -300,13 +299,13 @@
#ifdef __riscv #ifdef __riscv
#ifdef __riscv64 #ifdef __riscv64
# define MSTATUS_SD MSTATUS64_SD #define MSTATUS_SD MSTATUS64_SD
# define SSTATUS_SD SSTATUS64_SD #define SSTATUS_SD SSTATUS64_SD
# define RISCV_PGLEVEL_BITS 9 #define RISCV_PGLEVEL_BITS 9
#else #else
# define MSTATUS_SD MSTATUS32_SD #define MSTATUS_SD MSTATUS32_SD
# define SSTATUS_SD SSTATUS32_SD #define SSTATUS_SD SSTATUS32_SD
# define RISCV_PGLEVEL_BITS 10 #define RISCV_PGLEVEL_BITS 10
#endif /* __riscv64 */ #endif /* __riscv64 */
#define RISCV_PGSHIFT 12 #define RISCV_PGSHIFT 12

57
source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/portmacro.h vendored
View File

@@ -25,7 +25,6 @@
* 1 tab == 4 spaces! * 1 tab == 4 spaces!
*/ */
#ifndef PORTMACRO_H #ifndef PORTMACRO_H
#define PORTMACRO_H #define PORTMACRO_H
@@ -59,39 +58,41 @@ typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t; typedef long BaseType_t;
typedef unsigned long UBaseType_t; typedef unsigned long UBaseType_t;
#if( configUSE_16_BIT_TICKS == 1 ) #if (configUSE_16_BIT_TICKS == 1)
typedef uint16_t TickType_t; typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t )0xffff #define portMAX_DELAY (TickType_t)0xffff
#else #else
/* RISC-V TIMER is 64-bit long */ /* RISC-V TIMER is 64-bit long */
typedef uint64_t TickType_t; typedef uint64_t TickType_t;
#define portMAX_DELAY ( TickType_t )0xFFFFFFFFFFFFFFFFULL #define portMAX_DELAY (TickType_t)0xFFFFFFFFFFFFFFFFULL
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Architecture specifics. */ /* Architecture specifics. */
#define portSTACK_GROWTH ( -1 ) #define portSTACK_GROWTH (-1)
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
#define portBYTE_ALIGNMENT 8 #define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Scheduler utilities. */ /* Scheduler utilities. */
#define portYIELD() \ #define portYIELD() \
{ \ { \
/* Set a software interrupt(SWI) request to request a context switch. */ \ /* Set a software interrupt(SWI) request to request a context switch. */ \
SysTimer_SetSWIRQ(); \ SysTimer_SetSWIRQ(); \
/* Barriers are normally not required but do ensure the code is completely \ /* Barriers are normally not required but do ensure the code is completely \
within the specified behaviour for the architecture. */ \ within the specified behaviour for the architecture. */ \
__RWMB(); \ __RWMB(); \
} }
#define portEND_SWITCHING_ISR( xSwitchRequired ) if ( xSwitchRequired != pdFALSE ) portYIELD() #define portEND_SWITCHING_ISR(xSwitchRequired) \
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) if (xSwitchRequired != pdFALSE) \
portYIELD()
#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Critical section management. */ /* Critical section management. */
extern void vPortEnterCritical( void ); extern void vPortEnterCritical(void);
extern void vPortExitCritical( void ); extern void vPortExitCritical(void);
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x) #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)
@@ -105,22 +106,22 @@ extern void vPortExitCritical( void );
/* Task function macros as described on the FreeRTOS.org WEB site. These are /* Task function macros as described on the FreeRTOS.org WEB site. These are
not necessary for to use this port. They are defined so the common demo files not necessary for to use this port. They are defined so the common demo files
(which build with all the ports) will build. */ (which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */ /* Tickless idle/low power functionality. */
#ifndef portSUPPRESS_TICKS_AND_SLEEP #ifndef portSUPPRESS_TICKS_AND_SLEEP
extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime)
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#ifdef configASSERT #ifdef configASSERT
extern void vPortValidateInterruptPriority( void ); extern void vPortValidateInterruptPriority(void);
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif #endif
/* portNOP() is not required by this port. */ /* portNOP() is not required by this port. */
@@ -129,7 +130,7 @@ not necessary for to use this port. They are defined so the common demo files
#define portINLINE __inline #define portINLINE __inline
#ifndef portFORCE_INLINE #ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__(( always_inline)) #define portFORCE_INLINE inline __attribute__((always_inline))
#endif #endif
/* This variable should not be set in any of the FreeRTOS application /* This variable should not be set in any of the FreeRTOS application
@@ -137,16 +138,14 @@ not necessary for to use this port. They are defined so the common demo files
extern uint8_t uxMaxSysCallMTH; extern uint8_t uxMaxSysCallMTH;
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortRaiseBASEPRI( void ) portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
{
ECLIC_SetMth(uxMaxSysCallMTH); ECLIC_SetMth(uxMaxSysCallMTH);
__RWMB(); __RWMB();
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static uint8_t ulPortRaiseBASEPRI( void ) portFORCE_INLINE static uint8_t ulPortRaiseBASEPRI(void) {
{
uint8_t ulOriginalBASEPRI; uint8_t ulOriginalBASEPRI;
ulOriginalBASEPRI = ECLIC_GetMth(); ulOriginalBASEPRI = ECLIC_GetMth();
@@ -159,18 +158,16 @@ portFORCE_INLINE static uint8_t ulPortRaiseBASEPRI( void )
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint8_t ulNewMaskValue ) portFORCE_INLINE static void vPortSetBASEPRI(uint8_t ulNewMaskValue) {
{
ECLIC_SetMth(ulNewMaskValue); ECLIC_SetMth(ulNewMaskValue);
__RWMB(); __RWMB();
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) #define portMEMORY_BARRIER() __asm volatile("" ::: "memory")
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* PORTMACRO_H */ #endif /* PORTMACRO_H */

2
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/Include/gd32vf103v_eval.h vendored
View File

@@ -36,7 +36,7 @@ OF SUCH DAMAGE.
#define GD32VF103V_EVAL_H #define GD32VF103V_EVAL_H
#ifdef cplusplus #ifdef cplusplus
extern "C" { extern "C" {
#endif #endif
#include "nuclei_sdk_soc.h" #include "nuclei_sdk_soc.h"

3
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/Include/nuclei_sdk_hal.h vendored
View File

@@ -3,12 +3,11 @@
#define _NUCLEI_SDK_HAL_H #define _NUCLEI_SDK_HAL_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "gd32vf103v_eval.h" #include "gd32vf103v_eval.h"
#ifndef NUCLEI_BANNER #ifndef NUCLEI_BANNER
#define NUCLEI_BANNER 0 #define NUCLEI_BANNER 0
#endif #endif

36
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_core.h vendored
View File

@@ -42,7 +42,7 @@ OF SUCH DAMAGE.
#define HC_MAX_PACKET_COUNT 140U /* maximum packet count */ #define HC_MAX_PACKET_COUNT 140U /* maximum packet count */
#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /* endpoint number */ #define EP_ID(x) ((uint8_t)((x)&0x7FU)) /* endpoint number */
#define EP_DIR(x) ((uint8_t)((x) >> 7)) /* endpoint direction */ #define EP_DIR(x) ((uint8_t)((x) >> 7)) /* endpoint direction */
enum _usb_eptype { enum _usb_eptype {
@@ -53,26 +53,22 @@ enum _usb_eptype {
USB_EPTYPE_MASK = 3U, /*!< endpoint type mask */ USB_EPTYPE_MASK = 3U, /*!< endpoint type mask */
}; };
typedef enum typedef enum {
{
USB_OTG_OK = 0, /*!< USB OTG status OK*/ USB_OTG_OK = 0, /*!< USB OTG status OK*/
USB_OTG_FAIL /*!< USB OTG status fail*/ USB_OTG_FAIL /*!< USB OTG status fail*/
} usb_otg_status; } usb_otg_status;
typedef enum typedef enum {
{
USB_OK = 0, /*!< USB status OK*/ USB_OK = 0, /*!< USB status OK*/
USB_FAIL /*!< USB status fail*/ USB_FAIL /*!< USB status fail*/
} usb_status; } usb_status;
typedef enum typedef enum {
{
USB_USE_FIFO, /*!< USB use FIFO transfer mode */ USB_USE_FIFO, /*!< USB use FIFO transfer mode */
USB_USE_DMA /*!< USB use DMA transfer mode */ USB_USE_DMA /*!< USB use DMA transfer mode */
} usb_transfer_mode; } usb_transfer_mode;
typedef struct typedef struct {
{
uint8_t core_enum; /*!< USB core type */ uint8_t core_enum; /*!< USB core type */
uint8_t core_speed; /*!< USB core speed */ uint8_t core_speed; /*!< USB core speed */
uint8_t num_pipe; /*!< USB host channel numbers */ uint8_t num_pipe; /*!< USB host channel numbers */
@@ -86,32 +82,24 @@ typedef struct
/* function declarations */ /* function declarations */
/* config core capabilities */ /* config core capabilities */
usb_status usb_basic_init (usb_core_basic *usb_basic, usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core);
usb_core_regs *usb_regs,
usb_core_enum usb_core);
/*initializes the USB controller registers and prepares the core device mode or host mode operation*/ /*initializes the USB controller registers and prepares the core device mode or host mode operation*/
usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs); usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs);
/* read a packet from the Rx FIFO associated with the endpoint */ /* read a packet from the Rx FIFO associated with the endpoint */
void *usb_rxfifo_read (usb_core_regs *core_regs, uint8_t *dest_buf, uint16_t byte_count); void *usb_rxfifo_read(usb_core_regs *core_regs, uint8_t *dest_buf, uint16_t byte_count);
/* write a packet into the Tx FIFO associated with the endpoint */ /* write a packet into the Tx FIFO associated with the endpoint */
usb_status usb_txfifo_write (usb_core_regs *usb_regs, usb_status usb_txfifo_write(usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count);
uint8_t *src_buf,
uint8_t fifo_num,
uint16_t byte_count);
/* flush a Tx FIFO or all Tx FIFOs */ /* flush a Tx FIFO or all Tx FIFOs */
usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num); usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num);
/* flush the entire Rx FIFO */ /* flush the entire Rx FIFO */
usb_status usb_rxfifo_flush (usb_core_regs *usb_regs); usb_status usb_rxfifo_flush(usb_core_regs *usb_regs);
/* get the global interrupts */ /* get the global interrupts */
static inline uint32_t usb_coreintr_get(usb_core_regs *usb_regs) static inline uint32_t usb_coreintr_get(usb_core_regs *usb_regs) { return usb_regs->gr->GINTEN & usb_regs->gr->GINTF; }
{
return usb_regs->gr->GINTEN & usb_regs->gr->GINTF;
}
#endif /* __DRV_USB_CORE_H */ #endif /* __DRV_USB_CORE_H */

81
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_dev.h vendored
View File

@@ -56,7 +56,7 @@ typedef struct _usb_desc {
uint8_t *config_desc; /*!< config descriptor */ uint8_t *config_desc; /*!< config descriptor */
uint8_t *bos_desc; /*!< BOS descriptor */ uint8_t *bos_desc; /*!< BOS descriptor */
void* const *strings; /*!< string descriptor */ void *const *strings; /*!< string descriptor */
} usb_desc; } usb_desc;
/* USB power management */ /* USB power management */
@@ -75,12 +75,11 @@ typedef struct _usb_control {
uint8_t ctl_zlp; /*!< zero lenth package */ uint8_t ctl_zlp; /*!< zero lenth package */
} usb_control; } usb_control;
typedef struct typedef struct {
{
struct { struct {
uint8_t num: 4; /*!< the endpoint number.it can be from 0 to 6 */ uint8_t num : 4; /*!< the endpoint number.it can be from 0 to 6 */
uint8_t pad: 3; /*!< padding between number and direction */ uint8_t pad : 3; /*!< padding between number and direction */
uint8_t dir: 1; /*!< the endpoint direction */ uint8_t dir : 1; /*!< the endpoint direction */
} ep_addr; } ep_addr;
uint8_t ep_type; /*!< USB endpoint type */ uint8_t ep_type; /*!< USB endpoint type */
@@ -101,27 +100,25 @@ typedef struct
typedef struct _usb_core_driver usb_dev; typedef struct _usb_core_driver usb_dev;
typedef struct _usb_class_core typedef struct _usb_class_core {
{
uint8_t command; /*!< device class request command */ uint8_t command; /*!< device class request command */
uint8_t alter_set; /*!< alternative set */ uint8_t alter_set; /*!< alternative set */
uint8_t (*init) (usb_dev *udev, uint8_t config_index); /*!< initialize handler */ uint8_t (*init)(usb_dev *udev, uint8_t config_index); /*!< initialize handler */
uint8_t (*deinit) (usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */ uint8_t (*deinit)(usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */
uint8_t (*req_proc) (usb_dev *udev, usb_req *req); /*!< device request handler */ uint8_t (*req_proc)(usb_dev *udev, usb_req *req); /*!< device request handler */
uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ uint8_t (*data_in)(usb_dev *udev, uint8_t ep_num); /*!< device data in handler */
uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ uint8_t (*data_out)(usb_dev *udev, uint8_t ep_num); /*!< device data out handler */
uint8_t (*SOF) (usb_dev *udev); /*!< Start of frame handler */ uint8_t (*SOF)(usb_dev *udev); /*!< Start of frame handler */
uint8_t (*incomplete_isoc_in) (usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */ uint8_t (*incomplete_isoc_in)(usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */
uint8_t (*incomplete_isoc_out) (usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */ uint8_t (*incomplete_isoc_out)(usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */
} usb_class_core; } usb_class_core;
typedef struct _usb_perp_dev typedef struct _usb_perp_dev {
{
uint8_t config; /*!< configuration */ uint8_t config; /*!< configuration */
uint8_t dev_addr; /*!< device address */ uint8_t dev_addr; /*!< device address */
@@ -138,8 +135,7 @@ typedef struct _usb_perp_dev
usb_class_core *class_core; /*!< class driver */ usb_class_core *class_core; /*!< class driver */
} usb_perp_dev; } usb_perp_dev;
typedef struct _usb_core_driver typedef struct _usb_core_driver {
{
usb_core_basic bp; /*!< USB basic parameters */ usb_core_basic bp; /*!< USB basic parameters */
usb_core_regs regs; /*!< USB registers */ usb_core_regs regs; /*!< USB registers */
usb_perp_dev dev; /*!< USB peripheral device */ usb_perp_dev dev; /*!< USB peripheral device */
@@ -148,70 +144,69 @@ typedef struct _usb_core_driver
/* function declarations */ /* function declarations */
/* initialize USB core registers for device mode */ /* initialize USB core registers for device mode */
usb_status usb_devcore_init (usb_core_driver *udev); usb_status usb_devcore_init(usb_core_driver *udev);
/* enable the USB device mode interrupts */ /* enable the USB device mode interrupts */
usb_status usb_devint_enable (usb_core_driver *udev); usb_status usb_devint_enable(usb_core_driver *udev);
/* active the usb transaction */ /* active the usb transaction */
usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc); usb_status usb_transc_active(usb_core_driver *udev, usb_transc *transc);
/* deactive the usb transaction */ /* deactive the usb transaction */
usb_status usb_transc_deactivate (usb_core_driver *udev, usb_transc *transc); usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc);
/* configure usb transaction to start IN transfer */ /* configure usb transaction to start IN transfer */
usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc); usb_status usb_transc_inxfer(usb_core_driver *udev, usb_transc *transc);
/* configure usb transaction to start OUT transfer */ /* configure usb transaction to start OUT transfer */
usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc); usb_status usb_transc_outxfer(usb_core_driver *udev, usb_transc *transc);
/* set the usb transaction STALL status */ /* set the usb transaction STALL status */
usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc); usb_status usb_transc_stall(usb_core_driver *udev, usb_transc *transc);
/* clear the usb transaction STALL status */ /* clear the usb transaction STALL status */
usb_status usb_transc_clrstall (usb_core_driver *udev, usb_transc *transc); usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc);
/* read device all OUT endpoint interrupt register */ /* read device all OUT endpoint interrupt register */
uint32_t usb_oepintnum_read (usb_core_driver *udev); uint32_t usb_oepintnum_read(usb_core_driver *udev);
/* read device OUT endpoint interrupt flag register */ /* read device OUT endpoint interrupt flag register */
uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num); uint32_t usb_oepintr_read(usb_core_driver *udev, uint8_t ep_num);
/* read device all IN endpoint interrupt register */ /* read device all IN endpoint interrupt register */
uint32_t usb_iepintnum_read (usb_core_driver *udev); uint32_t usb_iepintnum_read(usb_core_driver *udev);
/* read device IN endpoint interrupt flag register */ /* read device IN endpoint interrupt flag register */
uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num); uint32_t usb_iepintr_read(usb_core_driver *udev, uint8_t ep_num);
/* config the USB device to be disconnected */ /* config the USB device to be disconnected */
void usb_dev_disconnect (usb_core_driver *udev); void usb_dev_disconnect(usb_core_driver *udev);
/* config the USB device to be connected */ /* config the USB device to be connected */
void usb_dev_connect (usb_core_driver *udev); void usb_dev_connect(usb_core_driver *udev);
/* set the USB device address */ /* set the USB device address */
void usb_devaddr_set (usb_core_driver *pudev, uint8_t dev_addr); void usb_devaddr_set(usb_core_driver *pudev, uint8_t dev_addr);
/* configures OUT endpoint 0 to receive SETUP packets */ /* configures OUT endpoint 0 to receive SETUP packets */
void usb_ctlep_startout (usb_core_driver *udev); void usb_ctlep_startout(usb_core_driver *udev);
/* active remote wakeup signalling */ /* active remote wakeup signalling */
void usb_rwkup_active (usb_core_driver *udev); void usb_rwkup_active(usb_core_driver *udev);
/* reset remote wakeup signalling */ /* reset remote wakeup signalling */
void usb_rwkup_reset (usb_core_driver *udev); void usb_rwkup_reset(usb_core_driver *udev);
/* set remote wakeup signalling */ /* set remote wakeup signalling */
void usb_rwkup_set (usb_core_driver *udev); void usb_rwkup_set(usb_core_driver *udev);
/* active USB core clock */ /* active USB core clock */
void usb_clock_active (usb_core_driver *udev); void usb_clock_active(usb_core_driver *udev);
/* usb device suspend */ /* usb device suspend */
void usb_dev_suspend (usb_core_driver *udev); void usb_dev_suspend(usb_core_driver *udev);
/* stop the device and clean up fifos */ /* stop the device and clean up fifos */
void usb_dev_stop (usb_core_driver *udev); void usb_dev_stop(usb_core_driver *udev);
#endif /* __DRV_USB_DEV_H */ #endif /* __DRV_USB_DEV_H */

72
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_host.h vendored
View File

@@ -35,12 +35,11 @@ OF SUCH DAMAGE.
#ifndef __DRV_USB_HOST_H #ifndef __DRV_USB_HOST_H
#define __DRV_USB_HOST_H #define __DRV_USB_HOST_H
#include "drv_usb_core.h"
#include "drv_usb_regs.h" #include "drv_usb_regs.h"
#include "usb_ch9_std.h" #include "usb_ch9_std.h"
#include "drv_usb_core.h"
typedef enum _usb_pipe_status typedef enum _usb_pipe_status {
{
PIPE_IDLE = 0U, PIPE_IDLE = 0U,
PIPE_XF, PIPE_XF,
PIPE_HALTED, PIPE_HALTED,
@@ -53,23 +52,11 @@ typedef enum _usb_pipe_status
PIPE_DTGERR, PIPE_DTGERR,
} usb_pipe_staus; } usb_pipe_staus;
typedef enum _usb_pipe_mode typedef enum _usb_pipe_mode { PIPE_PERIOD = 0U, PIPE_NON_PERIOD = 1U } usb_pipe_mode;
{
PIPE_PERIOD = 0U,
PIPE_NON_PERIOD = 1U
} usb_pipe_mode;
typedef enum _usb_urb_state typedef enum _usb_urb_state { URB_IDLE = 0U, URB_DONE, URB_NOTREADY, URB_ERROR, URB_STALL } usb_urb_state;
{
URB_IDLE = 0U,
URB_DONE,
URB_NOTREADY,
URB_ERROR,
URB_STALL
} usb_urb_state;
typedef struct _usb_pipe typedef struct _usb_pipe {
{
uint8_t in_used; uint8_t in_used;
uint8_t dev_addr; uint8_t dev_addr;
uint32_t dev_speed; uint32_t dev_speed;
@@ -96,9 +83,7 @@ typedef struct _usb_pipe
__IO usb_urb_state urb_state; __IO usb_urb_state urb_state;
} usb_pipe; } usb_pipe;
typedef struct _usb_host_drv {
typedef struct _usb_host_drv
{
uint8_t rx_buf[512U]; uint8_t rx_buf[512U];
__IO uint32_t connect_status; __IO uint32_t connect_status;
__IO uint32_t port_enabled; __IO uint32_t port_enabled;
@@ -107,8 +92,7 @@ typedef struct _usb_host_drv
usb_pipe pipe[USBFS_MAX_TX_FIFOS]; usb_pipe pipe[USBFS_MAX_TX_FIFOS];
} usb_host_drv; } usb_host_drv;
typedef struct _usb_core_driver typedef struct _usb_core_driver {
{
usb_core_basic bp; usb_core_basic bp;
usb_core_regs regs; usb_core_regs regs;
@@ -117,59 +101,59 @@ typedef struct _usb_core_driver
} usb_core_driver; } usb_core_driver;
/* initializes USB core for host mode */ /* initializes USB core for host mode */
usb_status usb_host_init (usb_core_driver *pudev); usb_status usb_host_init(usb_core_driver *pudev);
/* initialize host pipe */ /* initialize host pipe */
usb_status usb_pipe_init (usb_core_driver *pudev, uint8_t pipe_num); usb_status usb_pipe_init(usb_core_driver *pudev, uint8_t pipe_num);
/* prepare host pipe for transferring packets */ /* prepare host pipe for transferring packets */
usb_status usb_pipe_xfer (usb_core_driver *pudev, uint8_t pipe_num); usb_status usb_pipe_xfer(usb_core_driver *pudev, uint8_t pipe_num);
/* halt host pipe */ /* halt host pipe */
usb_status usb_pipe_halt (usb_core_driver *pudev, uint8_t pipe_num); usb_status usb_pipe_halt(usb_core_driver *pudev, uint8_t pipe_num);
/* configure host pipe to do ping operation */ /* configure host pipe to do ping operation */
usb_status usb_pipe_ping (usb_core_driver *pudev, uint8_t pipe_num); usb_status usb_pipe_ping(usb_core_driver *pudev, uint8_t pipe_num);
/* reset host port */ /* reset host port */
uint32_t usb_port_reset (usb_core_driver *pudev); uint32_t usb_port_reset(usb_core_driver *pudev);
/* control the VBUS to power */ /* control the VBUS to power */
void usb_portvbus_switch (usb_core_driver *pudev, uint8_t state); void usb_portvbus_switch(usb_core_driver *pudev, uint8_t state);
/* stop the USB host and clean up FIFO */ /* stop the USB host and clean up FIFO */
void usb_host_stop (usb_core_driver *pudev); void usb_host_stop(usb_core_driver *pudev);
//__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *pudev) //__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *pudev)
uint32_t usb_frame_even (usb_core_driver *pudev); uint32_t usb_frame_even(usb_core_driver *pudev);
//{ //{
// return !(pudev->regs.hr->HFINFR & 0x01U); // return !(pudev->regs.hr->HFINFR & 0x01U);
//} //}
//__STATIC_INLINE void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock) //__STATIC_INLINE void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock)
void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock) ; void usb_phyclock_config(usb_core_driver *pudev, uint8_t clock);
//{ //{
//pudev->regs.hr->HCTL &= ~HCTL_CLKSEL; // pudev->regs.hr->HCTL &= ~HCTL_CLKSEL;
// pudev->regs.hr->HCTL |= clock; // pudev->regs.hr->HCTL |= clock;
//} //}
uint32_t usb_port_read (usb_core_driver *pudev); uint32_t usb_port_read(usb_core_driver *pudev);
//inline uint32_t usb_port_read (usb_core_driver *pudev) // inline uint32_t usb_port_read (usb_core_driver *pudev)
//{ //{
// return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); // return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC);
//} //}
uint32_t usb_curspeed_get (usb_core_driver *pudev); uint32_t usb_curspeed_get(usb_core_driver *pudev);
//inline uint32_t usb_curspeed_get (usb_core_driver *pudev) // inline uint32_t usb_curspeed_get (usb_core_driver *pudev)
//{ //{
// return *pudev->regs.HPCS & HPCS_PS; // return *pudev->regs.HPCS & HPCS_PS;
//} //}
//__STATIC_INLINE uint32_t usb_curframe_get (usb_core_driver *pudev) //__STATIC_INLINE uint32_t usb_curframe_get (usb_core_driver *pudev)
uint32_t usb_curframe_get (usb_core_driver *pudev); uint32_t usb_curframe_get(usb_core_driver *pudev);
//{ //{
// return (pudev->regs.hr->HFINFR & 0xFFFFU); // return (pudev->regs.hr->HFINFR & 0xFFFFU);
//} //}
#endif /* __DRV_USB_HOST_H */ #endif /* __DRV_USB_HOST_H */

14
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_hw.h vendored
View File

@@ -38,24 +38,24 @@ OF SUCH DAMAGE.
#include "usb_conf.h" #include "usb_conf.h"
/* configure USB clock */ /* configure USB clock */
void usb_rcu_config (void); void usb_rcu_config(void);
/* configure USB interrupt */ /* configure USB interrupt */
void usb_intr_config (void); void usb_intr_config(void);
/* initializes delay unit using Timer2 */ /* initializes delay unit using Timer2 */
void usb_timer_init (void); void usb_timer_init(void);
/* delay in micro seconds */ /* delay in micro seconds */
void usb_udelay (const uint32_t usec); void usb_udelay(const uint32_t usec);
/* delay in milli seconds */ /* delay in milli seconds */
void usb_mdelay (const uint32_t msec); void usb_mdelay(const uint32_t msec);
// Functions for USE_HOST_MODE // Functions for USE_HOST_MODE
/* configure USB VBus */ /* configure USB VBus */
void usb_vbus_config (void); void usb_vbus_config(void);
/* drive usb VBus */ /* drive usb VBus */
void usb_vbus_drive (uint8_t State); void usb_vbus_drive(uint8_t State);
#endif /* __DRV_USB_HW_H */ #endif /* __DRV_USB_HW_H */

37
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_regs.h vendored
View File

@@ -55,8 +55,7 @@ OF SUCH DAMAGE.
#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */ #define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */
#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */ #define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */
typedef enum typedef enum {
{
USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */ USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */
USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */ USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */
} usb_core_enum; } usb_core_enum;
@@ -74,8 +73,7 @@ enum usb_reg_offset {
USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */ USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */
}; };
typedef struct typedef struct {
{
__IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */ __IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */
__IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */ __IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */
__IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */ __IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */
@@ -96,9 +94,7 @@ typedef struct
__IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */ __IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */
} usb_gr; } usb_gr;
typedef struct {
typedef struct
{
__IO uint32_t HCTL; /*!< USB host control register 400h */ __IO uint32_t HCTL; /*!< USB host control register 400h */
__IO uint32_t HFT; /*!< USB host frame interval register 404h */ __IO uint32_t HFT; /*!< USB host frame interval register 404h */
__IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */ __IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */
@@ -108,8 +104,7 @@ typedef struct
__IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */ __IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */
} usb_hr; } usb_hr;
typedef struct typedef struct {
{
__IO uint32_t HCHCTL; /*!< USB host channel control register 500h */ __IO uint32_t HCHCTL; /*!< USB host channel control register 500h */
__IO uint32_t HCHSTCTL; /*!< Reserved 504h */ __IO uint32_t HCHSTCTL; /*!< Reserved 504h */
__IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */ __IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */
@@ -119,8 +114,7 @@ typedef struct
uint32_t Reserved[2]; uint32_t Reserved[2];
} usb_pr; } usb_pr;
typedef struct typedef struct {
{
__IO uint32_t DCFG; /*!< USB device configuration register 800h */ __IO uint32_t DCFG; /*!< USB device configuration register 800h */
__IO uint32_t DCTL; /*!< USB device control register 804h */ __IO uint32_t DCTL; /*!< USB device control register 804h */
__IO uint32_t DSTAT; /*!< USB device status register 808h */ __IO uint32_t DSTAT; /*!< USB device status register 808h */
@@ -143,8 +137,7 @@ typedef struct
__IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */ __IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */
} usb_dr; } usb_dr;
typedef struct typedef struct {
{
__IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */ __IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */ uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */
__IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */ __IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */
@@ -154,8 +147,7 @@ typedef struct
__IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */ __IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */
} usb_erin; } usb_erin;
typedef struct typedef struct {
{
__IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */ __IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */ uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */
__IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */ __IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */
@@ -164,14 +156,13 @@ typedef struct
__IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */ __IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */
} usb_erout; } usb_erout;
typedef struct _usb_regs typedef struct _usb_regs {
{ usb_gr * gr; /*!< USBFS global registers */
usb_gr *gr; /*!< USBFS global registers */ usb_dr * dr; /*!< Device control and status registers */
usb_dr *dr; /*!< Device control and status registers */ usb_hr * hr; /*!< Host control and status registers */
usb_hr *hr; /*!< Host control and status registers */ usb_erin * er_in[6]; /*!< USB device IN endpoint register */
usb_erin *er_in[6]; /*!< USB device IN endpoint register */
usb_erout *er_out[6]; /*!< USB device OUT endpoint register */ usb_erout *er_out[6]; /*!< USB device OUT endpoint register */
usb_pr *pr[15]; /*!< USB Host channel-x control register */ usb_pr * pr[15]; /*!< USB Host channel-x control register */
__IO uint32_t *HPCS; /*!< USB host port control and status register */ __IO uint32_t *HPCS; /*!< USB host port control and status register */
__IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS];
@@ -349,7 +340,6 @@ typedef struct _usb_regs
#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ #define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */
#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */
#define TFQSTAT_TXFS BITS(0, 15) #define TFQSTAT_TXFS BITS(0, 15)
#define TFQSTAT_CNUM BITS(27, 30) #define TFQSTAT_CNUM BITS(27, 30)
@@ -425,7 +415,6 @@ typedef struct _usb_regs
/* host channel-x DMA address register bits definitions */ /* host channel-x DMA address register bits definitions */
#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ #define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ #define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */
#define PORT_SPEED_HIGH PORT_SPEED(0) /*!< high speed */ #define PORT_SPEED_HIGH PORT_SPEED(0) /*!< high speed */

7
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbd_int.h vendored
View File

@@ -39,14 +39,13 @@ OF SUCH DAMAGE.
#include "drv_usb_dev.h" #include "drv_usb_dev.h"
/* USB device-mode interrupts global service routine handler */ /* USB device-mode interrupts global service routine handler */
void usbd_isr (usb_core_driver *udev); void usbd_isr(usb_core_driver *udev);
#ifdef USB_HS_DEDICATED_EP1_ENABLED #ifdef USB_HS_DEDICATED_EP1_ENABLED
uint32_t USBD_OTG_EP1IN_ISR_Handler (usb_core_driver *udev); uint32_t USBD_OTG_EP1IN_ISR_Handler(usb_core_driver *udev);
uint32_t USBD_OTG_EP1OUT_ISR_Handler (usb_core_driver *udev); uint32_t USBD_OTG_EP1OUT_ISR_Handler(usb_core_driver *udev);
#endif #endif
#endif /* __DRV_USBD_INT_H */ #endif /* __DRV_USBD_INT_H */

7
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbh_int.h vendored
View File

@@ -37,13 +37,12 @@ OF SUCH DAMAGE.
#include "drv_usb_host.h" #include "drv_usb_host.h"
typedef struct _usbh_int_cb typedef struct _usbh_int_cb {
{ uint8_t (*SOF)(usb_core_driver *pudev);
uint8_t (*SOF) (usb_core_driver *pudev);
} usbh_int_cb; } usbh_int_cb;
extern usbh_int_cb *usbh_int_fop; extern usbh_int_cb *usbh_int_fop;
uint32_t usbh_isr (usb_core_driver *pudev); uint32_t usbh_isr(usb_core_driver *pudev);
#endif /* __DRV_USBH_INT_H */ #endif /* __DRV_USBH_INT_H */

9
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_ch9_std.h vendored
View File

@@ -126,11 +126,10 @@ enum _usbx_type {
#define FEATURE_SELECTOR_EP 0x00 /* USB endpoint feature selector */ #define FEATURE_SELECTOR_EP 0x00 /* USB endpoint feature selector */
#define FEATURE_SELECTOR_DEV 0x01 /* USB device feature selector */ #define FEATURE_SELECTOR_DEV 0x01 /* USB device feature selector */
#define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ #define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
(uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
#define BYTE_LOW(x) ((uint8_t)((x) & 0x00FFU)) #define BYTE_LOW(x) ((uint8_t)((x)&0x00FFU))
#define BYTE_HIGH(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) #define BYTE_HIGH(x) ((uint8_t)(((x)&0xFF00U) >> 8U))
#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) #define USB_MIN(a, b) (((a) < (b)) ? (a) : (b))
@@ -141,7 +140,7 @@ enum _usbx_type {
#define USB_CLASS_MSC 0x08U /*!< USB MSC class */ #define USB_CLASS_MSC 0x08U /*!< USB MSC class */
/* use the following values when USB host need to get descriptor */ /* use the following values when USB host need to get descriptor */
#define USBH_DESC(x) (((x)<< 8U) & 0xFF00U) #define USBH_DESC(x) (((x) << 8U) & 0xFF00U)
/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec /* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec
standard request with no data stage timeout : 50ms */ standard request with no data stage timeout : 50ms */

83
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_conf.h vendored
View File

@@ -1,8 +1,8 @@
#ifndef __USB_CONF_H #ifndef __USB_CONF_H
#define __USB_CONF_H #define __USB_CONF_H
#include <stddef.h>
#include "gd32vf103.h" #include "gd32vf103.h"
#include <stddef.h>
//#ifndef USE_USB_FS //#ifndef USE_USB_FS
//#define USE_USB_HS //#define USE_USB_HS
@@ -11,43 +11,43 @@
#define USE_USB_FS #define USE_USB_FS
#ifdef USE_USB_FS #ifdef USE_USB_FS
#define USB_FS_CORE #define USB_FS_CORE
#endif #endif
#ifdef USE_USB_HS #ifdef USE_USB_HS
#define USB_HS_CORE #define USB_HS_CORE
#endif #endif
#ifdef USB_FS_CORE #ifdef USB_FS_CORE
#define RX_FIFO_FS_SIZE 128 #define RX_FIFO_FS_SIZE 128
#define TX0_FIFO_FS_SIZE 64 #define TX0_FIFO_FS_SIZE 64
#define TX1_FIFO_FS_SIZE 128 #define TX1_FIFO_FS_SIZE 128
#define TX2_FIFO_FS_SIZE 0 #define TX2_FIFO_FS_SIZE 0
#define TX3_FIFO_FS_SIZE 0 #define TX3_FIFO_FS_SIZE 0
#define USB_RX_FIFO_FS_SIZE 128 #define USB_RX_FIFO_FS_SIZE 128
#define USB_HTX_NPFIFO_FS_SIZE 96 #define USB_HTX_NPFIFO_FS_SIZE 96
#define USB_HTX_PFIFO_FS_SIZE 96 #define USB_HTX_PFIFO_FS_SIZE 96
#endif /* USB_FS_CORE */ #endif /* USB_FS_CORE */
#ifdef USB_HS_CORE #ifdef USB_HS_CORE
#define RX_FIFO_HS_SIZE 512 #define RX_FIFO_HS_SIZE 512
#define TX0_FIFO_HS_SIZE 128 #define TX0_FIFO_HS_SIZE 128
#define TX1_FIFO_HS_SIZE 372 #define TX1_FIFO_HS_SIZE 372
#define TX2_FIFO_HS_SIZE 0 #define TX2_FIFO_HS_SIZE 0
#define TX3_FIFO_HS_SIZE 0 #define TX3_FIFO_HS_SIZE 0
#define TX4_FIFO_HS_SIZE 0 #define TX4_FIFO_HS_SIZE 0
#define TX5_FIFO_HS_SIZE 0 #define TX5_FIFO_HS_SIZE 0
#ifdef USE_ULPI_PHY #ifdef USE_ULPI_PHY
#define USB_OTG_ULPI_PHY_ENABLED #define USB_OTG_ULPI_PHY_ENABLED
#endif #endif
#ifdef USE_EMBEDDED_PHY #ifdef USE_EMBEDDED_PHY
#define USB_OTG_EMBEDDED_PHY_ENABLED #define USB_OTG_EMBEDDED_PHY_ENABLED
#endif #endif
#define USB_OTG_HS_INTERNAL_DMA_ENABLED #define USB_OTG_HS_INTERNAL_DMA_ENABLED
#define USB_OTG_HS_DEDICATED_EP1_ENABLED #define USB_OTG_HS_DEDICATED_EP1_ENABLED
#endif /* USB_HS_CORE */ #endif /* USB_HS_CORE */
#ifndef USB_SOF_OUTPUT #ifndef USB_SOF_OUTPUT
@@ -67,35 +67,34 @@
#endif #endif
#ifndef USB_FS_CORE #ifndef USB_FS_CORE
#ifndef USB_HS_CORE #ifndef USB_HS_CORE
#error "USB_HS_CORE or USB_FS_CORE should be defined" #error "USB_HS_CORE or USB_FS_CORE should be defined"
#endif #endif
#endif #endif
#ifndef USE_DEVICE_MODE #ifndef USE_DEVICE_MODE
#ifndef USE_HOST_MODE #ifndef USE_HOST_MODE
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
#endif #endif
#endif #endif
#ifndef USE_USB_HS #ifndef USE_USB_HS
#ifndef USE_USB_FS #ifndef USE_USB_FS
#error "USE_USB_HS or USE_USB_FS should be defined" #error "USE_USB_HS or USE_USB_FS should be defined"
#endif #endif
#endif #endif
/****************** C Compilers dependant keywords ****************************/ /****************** C Compilers dependant keywords ****************************/
/* In HS mode and when the DMA is used, all variables and data structures dealing /* In HS mode and when the DMA is used, all variables and data structures dealing
with the DMA during the transaction process should be 4-bytes aligned */ with the DMA during the transaction process should be 4-bytes aligned */
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
#if defined (__GNUC__) /* GNU Compiler */ #if defined(__GNUC__) /* GNU Compiler */
#define __ALIGN_END __attribute__ ((aligned(4))) #define __ALIGN_END __attribute__((aligned(4)))
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
#endif /* __GNUC__ */ #endif /* __GNUC__ */
#else #else
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
#define __ALIGN_END #define __ALIGN_END
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
#endif /* __USB_CONF_H */ #endif /* __USB_CONF_H */

1
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_conf.h vendored
View File

@@ -7,4 +7,3 @@
#define USBD_ITF_MAX_NUM 1 #define USBD_ITF_MAX_NUM 1
#endif /* __USBD_CONF_H */ #endif /* __USBD_CONF_H */

29
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_core.h vendored
View File

@@ -35,12 +35,10 @@ OF SUCH DAMAGE.
#ifndef __USBD_CORE_H #ifndef __USBD_CORE_H
#define __USBD_CORE_H #define __USBD_CORE_H
#include "drv_usb_core.h" #include "drv_usb_core.h"
#include "drv_usb_dev.h" #include "drv_usb_dev.h"
typedef enum typedef enum {
{
USBD_OK = 0, /*!< status OK */ USBD_OK = 0, /*!< status OK */
USBD_BUSY, /*!< status busy */ USBD_BUSY, /*!< status busy */
USBD_FAIL, /*!< status fail */ USBD_FAIL, /*!< status fail */
@@ -56,40 +54,39 @@ enum _usbd_status {
/* function declarations */ /* function declarations */
/* device connect */ /* device connect */
void usbd_connect (usb_core_driver *udev); void usbd_connect(usb_core_driver *udev);
/* device disconnect */ /* device disconnect */
void usbd_disconnect (usb_core_driver *udev); void usbd_disconnect(usb_core_driver *udev);
/* set USB device address */ /* set USB device address */
void usbd_addr_set (usb_core_driver *udev, uint8_t addr); void usbd_addr_set(usb_core_driver *udev, uint8_t addr);
/* initailizes the USB device-mode stack and load the class driver */ /* initailizes the USB device-mode stack and load the class driver */
void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core); void usbd_init(usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core);
/* endpoint initialization */ /* endpoint initialization */
uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc); uint32_t usbd_ep_setup(usb_core_driver *udev, const usb_desc_ep *ep_desc);
/* configure the endpoint when it is disabled */ /* configure the endpoint when it is disabled */
uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr); uint32_t usbd_ep_clear(usb_core_driver *udev, uint8_t ep_addr);
/* endpoint prepare to receive data */ /* endpoint prepare to receive data */
uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len); uint32_t usbd_ep_recev(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len);
/* endpoint prepare to transmit data */ /* endpoint prepare to transmit data */
uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len); uint32_t usbd_ep_send(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len);
/* set an endpoint to STALL status */ /* set an endpoint to STALL status */
uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr); uint32_t usbd_ep_stall(usb_core_driver *udev, uint8_t ep_addr);
/* clear endpoint STALLed status */ /* clear endpoint STALLed status */
uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr); uint32_t usbd_ep_stall_clear(usb_core_driver *udev, uint8_t ep_addr);
/* flush the endpoint FIFOs */ /* flush the endpoint FIFOs */
uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr); uint32_t usbd_fifo_flush(usb_core_driver *udev, uint8_t ep_addr);
/* get the received data length */ /* get the received data length */
uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num); uint16_t usbd_rxcount_get(usb_core_driver *udev, uint8_t ep_num);
#endif /* __USBD_CORE_H */ #endif /* __USBD_CORE_H */

26
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_enum.h vendored
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@@ -35,12 +35,12 @@ OF SUCH DAMAGE.
#ifndef __USBD_ENUM_H #ifndef __USBD_ENUM_H
#define __USBD_ENUM_H #define __USBD_ENUM_H
#include "usbd_core.h"
#include "usbd_conf.h" #include "usbd_conf.h"
#include "usbd_core.h"
#include <wchar.h> #include <wchar.h>
#ifndef NULL #ifndef NULL
#define NULL 0U #define NULL 0U
#endif #endif
typedef enum _usb_reqsta { typedef enum _usb_reqsta {
@@ -49,8 +49,7 @@ typedef enum _usb_reqsta {
} usb_reqsta; } usb_reqsta;
/* string descriptor index */ /* string descriptor index */
enum _str_index enum _str_index {
{
STR_IDX_LANGID = 0x0U, /* language ID string index */ STR_IDX_LANGID = 0x0U, /* language ID string index */
STR_IDX_MFC = 0x1U, /* manufacturer string index */ STR_IDX_MFC = 0x1U, /* manufacturer string index */
STR_IDX_PRODUCT = 0x2U, /* product string index */ STR_IDX_PRODUCT = 0x2U, /* product string index */
@@ -65,8 +64,7 @@ typedef enum _usb_pwrsta {
USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */ USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */
} usb_pwrsta; } usb_pwrsta;
typedef enum _usb_feature typedef enum _usb_feature {
{
USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */ USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */
USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */ USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */
USB_FEATURE_TEST_MODE = 0x2U /* USB has endpoint test mode feature */ USB_FEATURE_TEST_MODE = 0x2U /* USB has endpoint test mode feature */
@@ -87,28 +85,24 @@ typedef enum _usb_feature
uint8_t _type; \ uint8_t _type; \
wchar_t _data[sizeof(string)]; \ wchar_t _data[sizeof(string)]; \
}) { \ }) { \
sizeof(WIDE_STRING(string)) + 2U - 2U, \ sizeof(WIDE_STRING(string)) + 2U - 2U, USB_DESCTYPE_STR, WIDE_STRING(string) \
USB_DESCTYPE_STR, \
WIDE_STRING(string) \
} }
/* function declarations */ /* function declarations */
/* handle USB standard device request */ /* handle USB standard device request */
usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req); usb_reqsta usbd_standard_request(usb_core_driver *udev, usb_req *req);
/* handle USB device class request */ /* handle USB device class request */
usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req); usb_reqsta usbd_class_request(usb_core_driver *udev, usb_req *req);
/* handle USB vendor request */ /* handle USB vendor request */
usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req); usb_reqsta usbd_vendor_request(usb_core_driver *udev, usb_req *req);
/* handle USB enumeration error */ /* handle USB enumeration error */
void usbd_enum_error (usb_core_driver *udev, usb_req *req); void usbd_enum_error(usb_core_driver *udev, usb_req *req);
/* convert hex 32bits value into unicode char */ /* convert hex 32bits value into unicode char */
void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len); void int_to_unicode(uint32_t value, uint8_t *pbuf, uint8_t len);
#endif /* __USBD_ENUM_H */ #endif /* __USBD_ENUM_H */

15
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_transc.h vendored
View File

@@ -40,25 +40,24 @@ OF SUCH DAMAGE.
/* function declarations */ /* function declarations */
/* USB send data in the control transaction */ /* USB send data in the control transaction */
usbd_status usbd_ctl_send (usb_core_driver *udev); usbd_status usbd_ctl_send(usb_core_driver *udev);
/* USB receive data in control transaction */ /* USB receive data in control transaction */
usbd_status usbd_ctl_recev (usb_core_driver *udev); usbd_status usbd_ctl_recev(usb_core_driver *udev);
/* USB send control transaction status */ /* USB send control transaction status */
usbd_status usbd_ctl_status_send (usb_core_driver *udev); usbd_status usbd_ctl_status_send(usb_core_driver *udev);
/* USB control receive status */ /* USB control receive status */
usbd_status usbd_ctl_status_recev (usb_core_driver *udev); usbd_status usbd_ctl_status_recev(usb_core_driver *udev);
/* USB setup stage processing */ /* USB setup stage processing */
uint8_t usbd_setup_transc (usb_core_driver *udev); uint8_t usbd_setup_transc(usb_core_driver *udev);
/* data out stage processing */ /* data out stage processing */
uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num)__attribute__((optimize("O0"))); uint8_t usbd_out_transc(usb_core_driver *udev, uint8_t ep_num) __attribute__((optimize("O0")));
/* data in stage processing */ /* data in stage processing */
uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num)__attribute__((optimize("O0"))); uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num) __attribute__((optimize("O0")));
#endif /* __USBD_TRANSC_H */ #endif /* __USBD_TRANSC_H */

1
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_conf.h vendored
View File

@@ -6,4 +6,3 @@
#define USBH_MSC_MPS_SIZE 0x200 #define USBH_MSC_MPS_SIZE 0x200
#endif /* __USBH_CONF_H */ #endif /* __USBH_CONF_H */

126
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_core.h vendored
View File

@@ -35,8 +35,8 @@ OF SUCH DAMAGE.
#ifndef __USBH_CORE_H #ifndef __USBH_CORE_H
#define __USBH_CORE_H #define __USBH_CORE_H
#include "usbh_conf.h"
#include "drv_usb_host.h" #include "drv_usb_host.h"
#include "usbh_conf.h"
#define MSC_CLASS 0x08U #define MSC_CLASS 0x08U
#define HID_CLASS 0x03U #define HID_CLASS 0x03U
@@ -48,20 +48,10 @@ OF SUCH DAMAGE.
#define USBH_DEV_ADDR_DEFAULT 0U #define USBH_DEV_ADDR_DEFAULT 0U
#define USBH_DEV_ADDR 1U #define USBH_DEV_ADDR 1U
typedef enum typedef enum { USBH_OK = 0U, USBH_BUSY, USBH_FAIL, USBH_NOT_SUPPORTED, USBH_UNRECOVERED_ERROR, USBH_SPEED_UNKNOWN_ERROR, USBH_APPLY_DEINIT } usbh_status;
{
USBH_OK = 0U,
USBH_BUSY,
USBH_FAIL,
USBH_NOT_SUPPORTED,
USBH_UNRECOVERED_ERROR,
USBH_SPEED_UNKNOWN_ERROR,
USBH_APPLY_DEINIT
} usbh_status;
/* USB host global operation state */ /* USB host global operation state */
typedef enum typedef enum {
{
HOST_DEFAULT = 0U, HOST_DEFAULT = 0U,
HOST_DETECT_DEV_SPEED, HOST_DETECT_DEV_SPEED,
HOST_DEV_ATTACHED, HOST_DEV_ATTACHED,
@@ -75,41 +65,19 @@ typedef enum
} usb_host_state; } usb_host_state;
/* USB host enumeration state */ /* USB host enumeration state */
typedef enum typedef enum { ENUM_DEFAULT = 0U, ENUM_GET_DEV_DESC, ENUM_SET_ADDR, ENUM_GET_CFG_DESC, ENUM_GET_CFG_DESC_SET, ENUM_GET_STR_DESC, ENUM_SET_CONFIGURATION, ENUM_DEV_CONFIGURED } usbh_enum_state;
{
ENUM_DEFAULT = 0U,
ENUM_GET_DEV_DESC,
ENUM_SET_ADDR,
ENUM_GET_CFG_DESC,
ENUM_GET_CFG_DESC_SET,
ENUM_GET_STR_DESC,
ENUM_SET_CONFIGURATION,
ENUM_DEV_CONFIGURED
} usbh_enum_state;
/* USB host control transfer state */ /* USB host control transfer state */
typedef enum typedef enum { CTL_IDLE = 0U, CTL_SETUP, CTL_DATA_IN, CTL_DATA_OUT, CTL_STATUS_IN, CTL_STATUS_OUT, CTL_ERROR, CTL_FINISH } usbh_ctl_state;
{
CTL_IDLE = 0U,
CTL_SETUP,
CTL_DATA_IN,
CTL_DATA_OUT,
CTL_STATUS_IN,
CTL_STATUS_OUT,
CTL_ERROR,
CTL_FINISH
} usbh_ctl_state;
/* user action state */ /* user action state */
typedef enum typedef enum {
{
USBH_USER_NO_RESP = 0U, USBH_USER_NO_RESP = 0U,
USBH_USER_RESP_OK = 1U, USBH_USER_RESP_OK = 1U,
} usbh_user_status; } usbh_user_status;
/* control transfer information */ /* control transfer information */
typedef struct _usbh_control typedef struct _usbh_control {
{
uint8_t pipe_in_num; uint8_t pipe_in_num;
uint8_t pipe_out_num; uint8_t pipe_out_num;
uint8_t max_len; uint8_t max_len;
@@ -124,8 +92,7 @@ typedef struct _usbh_control
} usbh_control; } usbh_control;
/* USB device property */ /* USB device property */
typedef struct typedef struct {
{
uint8_t addr; uint8_t addr;
uint32_t speed; uint32_t speed;
@@ -138,48 +105,43 @@ typedef struct
/** /**
* @brief Device class callbacks * @brief Device class callbacks
*/ */
typedef struct typedef struct {
{ usbh_status (*class_init)(usb_core_driver *pudev, void *phost);
usbh_status (*class_init) (usb_core_driver *pudev, void *phost); void (*class_deinit)(usb_core_driver *pudev, void *phost);
void (*class_deinit) (usb_core_driver *pudev, void *phost); usbh_status (*class_requests)(usb_core_driver *pudev, void *phost);
usbh_status (*class_requests) (usb_core_driver *pudev, void *phost); usbh_status (*class_machine)(usb_core_driver *pudev, void *phost);
usbh_status (*class_machine) (usb_core_driver *pudev, void *phost);
} usbh_class_cb; } usbh_class_cb;
/** /**
* @brief User callbacks * @brief User callbacks
*/ */
typedef struct typedef struct {
{ void (*dev_init)(void);
void (*dev_init) (void); void (*dev_deinit)(void);
void (*dev_deinit) (void); void (*dev_attach)(void);
void (*dev_attach) (void); void (*dev_reset)(void);
void (*dev_reset) (void); void (*dev_detach)(void);
void (*dev_detach) (void); void (*dev_over_currented)(void);
void (*dev_over_currented) (void); void (*dev_speed_detected)(uint32_t dev_speed);
void (*dev_speed_detected) (uint32_t dev_speed); void (*dev_devdesc_assigned)(void *dev_desc);
void (*dev_devdesc_assigned) (void *dev_desc); void (*dev_address_set)(void);
void (*dev_address_set) (void);
void (*dev_cfgdesc_assigned) (usb_desc_config *cfg_desc, void (*dev_cfgdesc_assigned)(usb_desc_config *cfg_desc, usb_desc_itf *itf_desc, usb_desc_ep *ep_desc);
usb_desc_itf *itf_desc,
usb_desc_ep *ep_desc);
void (*dev_mfc_str) (void *mfc_str); void (*dev_mfc_str)(void *mfc_str);
void (*dev_prod_str) (void *prod_str); void (*dev_prod_str)(void *prod_str);
void (*dev_seral_str) (void *serial_str); void (*dev_seral_str)(void *serial_str);
void (*dev_enumerated) (void); void (*dev_enumerated)(void);
usbh_user_status (*dev_user_input) (void); usbh_user_status (*dev_user_input)(void);
int (*dev_user_app) (void); int (*dev_user_app)(void);
void (*dev_not_supported) (void); void (*dev_not_supported)(void);
void (*dev_error) (void); void (*dev_error)(void);
} usbh_user_cb; } usbh_user_cb;
/** /**
* @brief Host information * @brief Host information
*/ */
typedef struct typedef struct {
{
usb_host_state cur_state; /*!< host state machine value */ usb_host_state cur_state; /*!< host state machine value */
usb_host_state backup_state; /*!< backup of previous state machine value */ usb_host_state backup_state; /*!< backup of previous state machine value */
usbh_enum_state enum_state; /*!< enumeration state machine */ usbh_enum_state enum_state; /*!< enumeration state machine */
@@ -187,33 +149,25 @@ typedef struct
usb_dev_prop dev_prop; /*!< USB device properity */ usb_dev_prop dev_prop; /*!< USB device properity */
usbh_class_cb *class_cb; /*!< USB class callback */ usbh_class_cb *class_cb; /*!< USB class callback */
usbh_user_cb *usr_cb; /*!< USB user callback */ usbh_user_cb * usr_cb; /*!< USB user callback */
} usbh_host; } usbh_host;
/* USB host stack initializations */ /* USB host stack initializations */
void usbh_init (usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost); void usbh_init(usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost);
/* de-initialize USB host */ /* de-initialize USB host */
usbh_status usbh_deinit (usb_core_driver *pudev, usbh_host *puhost); usbh_status usbh_deinit(usb_core_driver *pudev, usbh_host *puhost);
/* USB host core main state machine process */ /* USB host core main state machine process */
void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost); void usbh_core_task(usb_core_driver *pudev, usbh_host *puhost);
/* handle the error on USB host side */ /* handle the error on USB host side */
void usbh_error_handler (usbh_host *puhost, usbh_status ErrType); void usbh_error_handler(usbh_host *puhost, usbh_status ErrType);
/* get USB URB state */ /* get USB URB state */
static inline usb_urb_state usbh_urbstate_get (usb_core_driver *pudev, uint8_t pp_num) static inline usb_urb_state usbh_urbstate_get(usb_core_driver *pudev, uint8_t pp_num) { return pudev->host.pipe[pp_num].urb_state; }
{
return pudev->host.pipe[pp_num].urb_state;
}
/* get USB transfer data count */ /* get USB transfer data count */
static inline uint32_t usbh_xfercount_get (usb_core_driver *pudev, uint8_t pp_num) static inline uint32_t usbh_xfercount_get(usb_core_driver *pudev, uint8_t pp_num) { return pudev->host.backup_xfercount[pp_num]; }
{
return pudev->host.backup_xfercount[pp_num];
}
#endif /* __USBH_CORE_H */ #endif /* __USBH_CORE_H */

28
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_enum.h vendored
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@@ -39,40 +39,30 @@ OF SUCH DAMAGE.
#include "usbh_core.h" #include "usbh_core.h"
/* get the next descriptor header */ /* get the next descriptor header */
usb_desc_header *usbh_nextdesc_get (uint8_t *pbuf, uint16_t *ptr); usb_desc_header *usbh_nextdesc_get(uint8_t *pbuf, uint16_t *ptr);
/* configure USB control status parameters */ /* configure USB control status parameters */
void usbh_ctlstate_config (usbh_host *puhost, uint8_t *buf, uint16_t len); void usbh_ctlstate_config(usbh_host *puhost, uint8_t *buf, uint16_t len);
/* get device descriptor from the USB device */ /* get device descriptor from the USB device */
usbh_status usbh_devdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint8_t len); usbh_status usbh_devdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint8_t len);
/* get configuration descriptor from the USB device */ /* get configuration descriptor from the USB device */
usbh_status usbh_cfgdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint16_t len); usbh_status usbh_cfgdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint16_t len);
/* get string descriptor from the USB device */ /* get string descriptor from the USB device */
usbh_status usbh_strdesc_get (usb_core_driver *pudev, usbh_status usbh_strdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint8_t str_index, uint8_t *buf, uint16_t len);
usbh_host *puhost,
uint8_t str_index,
uint8_t *buf,
uint16_t len);
/* set the configuration value to the connected device */ /* set the configuration value to the connected device */
usbh_status usbh_setcfg (usb_core_driver *pudev, usbh_host *puhost, uint16_t config); usbh_status usbh_setcfg(usb_core_driver *pudev, usbh_host *puhost, uint16_t config);
/* set the address to the connected device */ /* set the address to the connected device */
usbh_status usbh_setaddress (usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr); usbh_status usbh_setaddress(usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr);
/* clear or disable a specific feature */ /* clear or disable a specific feature */
usbh_status usbh_clrfeature (usb_core_driver *pudev, usbh_status usbh_clrfeature(usb_core_driver *pudev, usbh_host *puhost, uint8_t ep_num, uint8_t pp_num);
usbh_host *puhost,
uint8_t ep_num,
uint8_t pp_num);
/* set the interface value to the connected device */ /* set the interface value to the connected device */
usbh_status usbh_setinterface (usb_core_driver *pudev, usbh_status usbh_setinterface(usb_core_driver *pudev, usbh_host *puhost, uint8_t ep_num, uint8_t alter_setting);
usbh_host *puhost,
uint8_t ep_num,
uint8_t alter_setting);
#endif /* __USBH_ENUM_H */ #endif /* __USBH_ENUM_H */

18
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_pipe.h vendored
View File

@@ -45,26 +45,18 @@ OF SUCH DAMAGE.
#define HC_USED_MASK 0x7FFFU #define HC_USED_MASK 0x7FFFU
/* allocate a new pipe */ /* allocate a new pipe */
uint8_t usbh_pipe_allocate (usb_core_driver *pudev, uint8_t ep_addr); uint8_t usbh_pipe_allocate(usb_core_driver *pudev, uint8_t ep_addr);
/* delete all USB host pipe */ /* delete all USB host pipe */
uint8_t usbh_pipe_delete (usb_core_driver *pudev); uint8_t usbh_pipe_delete(usb_core_driver *pudev);
/* free a pipe */ /* free a pipe */
uint8_t usbh_pipe_free (usb_core_driver *pudev, uint8_t pp_num); uint8_t usbh_pipe_free(usb_core_driver *pudev, uint8_t pp_num);
/* create a pipe */ /* create a pipe */
uint8_t usbh_pipe_create (usb_core_driver *pudev, uint8_t usbh_pipe_create(usb_core_driver *pudev, usb_dev_prop *udev, uint8_t pp_num, uint8_t ep_type, uint16_t ep_mpl);
usb_dev_prop *udev,
uint8_t pp_num,
uint8_t ep_type,
uint16_t ep_mpl);
/* modify a pipe */ /* modify a pipe */
uint8_t usbh_pipe_update (usb_core_driver *pudev, uint8_t usbh_pipe_update(usb_core_driver *pudev, uint8_t pp_num, uint8_t dev_addr, uint32_t dev_speed, uint16_t ep_mpl);
uint8_t pp_num,
uint8_t dev_addr,
uint32_t dev_speed,
uint16_t ep_mpl);
#endif /* __USBH_PIPE_H */ #endif /* __USBH_PIPE_H */

9
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_transc.h vendored
View File

@@ -39,16 +39,15 @@ OF SUCH DAMAGE.
#include "usbh_core.h" #include "usbh_core.h"
/* send the setup packet to the USB device */ /* send the setup packet to the USB device */
usbh_status usbh_ctlsetup_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num); usbh_status usbh_ctlsetup_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num);
/* send a data packet to the USB device */ /* send a data packet to the USB device */
usbh_status usbh_data_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len); usbh_status usbh_data_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len);
/* receive a data packet from the USB device */ /* receive a data packet from the USB device */
usbh_status usbh_data_recev (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len); usbh_status usbh_data_recev(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len);
/* USB control transfer handler */ /* USB control transfer handler */
usbh_status usbh_ctl_handler (usb_core_driver *pudev, usbh_host *puhost); usbh_status usbh_ctl_handler(usb_core_driver *pudev, usbh_host *puhost);
#endif /* __USBH_TRANSC_H */ #endif /* __USBH_TRANSC_H */

76
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103.h vendored
View File

@@ -36,26 +36,20 @@ extern "C" {
* @{ * @{
*/ */
/** @addtogroup gd32vf103 /** @addtogroup gd32vf103
* @{ * @{
*/ */
/** @addtogroup Configuration_of_NMSIS /** @addtogroup Configuration_of_NMSIS
* @{ * @{
*/ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */ /* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
typedef enum IRQn typedef enum IRQn {
{ /* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */
/* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */
Reserved0_IRQn = 0, /*!< Internal reserved */ Reserved0_IRQn = 0, /*!< Internal reserved */
Reserved1_IRQn = 1, /*!< Internal reserved */ Reserved1_IRQn = 1, /*!< Internal reserved */
@@ -77,8 +71,8 @@ typedef enum IRQn
BusError_IRQn = 17, /*!< Bus Error interrupt */ BusError_IRQn = 17, /*!< Bus Error interrupt */
PerfMon_IRQn = 18, /*!< Performance Monitor */ PerfMon_IRQn = 18, /*!< Performance Monitor */
/* =========================================== GD32VF103 Specific Interrupt Numbers ========================================= */ /* =========================================== GD32VF103 Specific Interrupt Numbers ========================================= */
/* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported /* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported
could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */ eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
/* interruput numbers */ /* interruput numbers */
@@ -155,7 +149,7 @@ typedef enum IRQn
/* =========================================================================================================================== */ /* =========================================================================================================================== */
typedef enum EXCn { typedef enum EXCn {
/* ======================================= Nuclei N/NX Specific Exception Code ======================================== */ /* ======================================= Nuclei N/NX Specific Exception Code ======================================== */
InsUnalign_EXCn = 0, /*!< Instruction address misaligned */ InsUnalign_EXCn = 0, /*!< Instruction address misaligned */
InsAccFault_EXCn = 1, /*!< Instruction access fault */ InsAccFault_EXCn = 1, /*!< Instruction access fault */
IlleIns_EXCn = 2, /*!< Illegal instruction */ IlleIns_EXCn = 2, /*!< Illegal instruction */
@@ -199,22 +193,18 @@ typedef enum EXCn {
/** @} */ /* End of group Configuration_of_CMSIS */ /** @} */ /* End of group Configuration_of_CMSIS */
#include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */ #include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */
/* ToDo: include your system_nuclei_soc.h file /* ToDo: include your system_nuclei_soc.h file
replace 'Device' with your device name */ replace 'Device' with your device name */
#include "system_gd32vf103.h" /*!< gd32vf103 System */ #include "system_gd32vf103.h" /*!< gd32vf103 System */
/* ======================================== Start of section using anonymous unions ======================================== */ /* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__GNUC__) #if defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/* system frequency define */ /* system frequency define */
#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ #define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ #define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
@@ -222,39 +212,23 @@ typedef enum EXCn {
#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) #define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
#define RTC_FREQ LXTAL_VALUE #define RTC_FREQ LXTAL_VALUE
// The TIMER frequency is just the RTC frequency // The TIMER frequency is just the RTC frequency
#define SOC_TIMER_FREQ ((uint32_t)SystemCoreClock/4) //LXTAL_VALUE units HZ #define SOC_TIMER_FREQ ((uint32_t)SystemCoreClock / 4) // LXTAL_VALUE units HZ
/* enum definitions */ /* enum definitions */
typedef enum { typedef enum { DISABLE = 0, ENABLE = !DISABLE } EventStatus, ControlStatus;
DISABLE = 0,
ENABLE = !DISABLE
} EventStatus, ControlStatus;
typedef enum { typedef enum { FALSE = 0, TRUE = !FALSE } BOOL;
FALSE = 0,
TRUE = !FALSE
} BOOL;
typedef enum { typedef enum { RESET = 0, SET = 1, MAX = 0X7FFFFFFF } FlagStatus;
RESET = 0,
SET = 1,
MAX = 0X7FFFFFFF
} FlagStatus;
typedef enum { typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrStatus;
ERROR = 0,
SUCCESS = !ERROR
} ErrStatus;
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */ /* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals /** @addtogroup Device_Peripheral_peripherals
* @{ * @{
*/ */
@@ -263,10 +237,6 @@ typedef enum {
* Platform definitions * Platform definitions
*****************************************************************************/ *****************************************************************************/
/* ToDo: add here your device specific peripheral access structure typedefs /* ToDo: add here your device specific peripheral access structure typedefs
following is an example for Systick Timer*/ following is an example for Systick Timer*/
@@ -276,20 +246,17 @@ typedef enum {
/*@}*/ /* end of group nuclei_soc_Peripherals */ /*@}*/ /* end of group nuclei_soc_Peripherals */
/* ========================================= End of section using anonymous unions ========================================= */ /* ========================================= End of section using anonymous unions ========================================= */
#if defined (__GNUC__) #if defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
#else #else
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */ /* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ToDo: add here your device peripherals base addresses /* ToDo: add here your device peripherals base addresses
following is an example for timer */ following is an example for timer */
/** @addtogroup Device_Peripheral_peripheralAddr /** @addtogroup Device_Peripheral_peripheralAddr
@@ -334,15 +301,12 @@ typedef enum {
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
/** @} */ /* End of group Device_Peripheral_peripheralAddr */ /** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */ /* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ToDo: add here your device peripherals pointer definitions /* ToDo: add here your device peripherals pointer definitions
following is an example for timer */ following is an example for timer */
/** @addtogroup Device_Peripheral_declaration /** @addtogroup Device_Peripheral_declaration
@@ -352,15 +316,14 @@ typedef enum {
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) #define BIT(x) ((uint32_t)((uint32_t)0x01U << (x)))
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) #define GET_BITS(regval, start, end) (((regval)&BITS((start), (end))) >> (start))
// Interrupt Numbers // Interrupt Numbers
#define SOC_ECLIC_NUM_INTERRUPTS 86 #define SOC_ECLIC_NUM_INTERRUPTS 86
#define SOC_ECLIC_INT_GPIO_BASE 19 #define SOC_ECLIC_INT_GPIO_BASE 19
// Interrupt Handler Definitions // Interrupt Handler Definitions
#define SOC_MTIMER_HANDLER eclic_mtip_handler #define SOC_MTIMER_HANDLER eclic_mtip_handler
#define SOC_SOFTINT_HANDLER eclic_msip_handler #define SOC_SOFTINT_HANDLER eclic_msip_handler
@@ -377,7 +340,6 @@ extern uint32_t get_cpu_freq(void);
*/ */
extern void delay_1ms(uint32_t count); extern void delay_1ms(uint32_t count);
/** @} */ /* End of group gd32vf103_soc */ /** @} */ /* End of group gd32vf103_soc */
/** @} */ /* End of group gd32vf103 */ /** @} */ /* End of group gd32vf103 */

67
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_adc.h vendored
View File

@@ -36,14 +36,13 @@ OF SUCH DAMAGE.
#define GD32VF103_ADC_H #define GD32VF103_ADC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* ADC definitions */ /* ADC definitions */
#define ADC0 ADC_BASE #define ADC0 ADC_BASE
#define ADC1 (ADC_BASE + 0x400U) #define ADC1 (ADC_BASE + 0x400U)
/* registers definitions */ /* registers definitions */
#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ #define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ #define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
@@ -76,7 +75,7 @@ OF SUCH DAMAGE.
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
/* ADC_CTL0 */ /* ADC_CTL0 */
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ #define ADC_CTL0_WDCHSEL BITS(0, 4) /*!< analog watchdog channel select bits */
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
@@ -85,8 +84,8 @@ OF SUCH DAMAGE.
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ #define ADC_CTL0_DISNUM BITS(13, 15) /*!< discontinuous mode channel count */
#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ #define ADC_CTL0_SYNCM BITS(16, 19) /*!< sync mode selection */
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
@@ -97,47 +96,47 @@ OF SUCH DAMAGE.
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ #define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ #define ADC_CTL1_DAL BIT(11) /*!< data alignment */
#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ #define ADC_CTL1_ETSIC BITS(12, 14) /*!< external trigger select for inserted channel */
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ #define ADC_CTL1_ETSRC BITS(17, 19) /*!< external trigger select for regular channel */
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ #define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ #define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */
/* ADC_SAMPTx x=0..1 */ /* ADC_SAMPTx x=0..1 */
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ #define ADC_SAMPTX_SPTN BITS(0, 2) /*!< channel n sample time selection */
/* ADC_IOFFx x=0..3 */ /* ADC_IOFFx x=0..3 */
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ #define ADC_IOFFX_IOFF BITS(0, 11) /*!< data offset for inserted channel x */
/* ADC_WDHT */ /* ADC_WDHT */
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ #define ADC_WDHT_WDHT BITS(0, 11) /*!< analog watchdog high threshold */
/* ADC_WDLT */ /* ADC_WDLT */
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ #define ADC_WDLT_WDLT BITS(0, 11) /*!< analog watchdog low threshold */
/* ADC_RSQx x=0..2 */ /* ADC_RSQx x=0..2 */
#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ #define ADC_RSQX_RSQN BITS(0, 4) /*!< nth conversion in regular sequence */
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ #define ADC_RSQ0_RL BITS(20, 23) /*!< regular channel sequence length */
/* ADC_ISQ */ /* ADC_ISQ */
#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ #define ADC_ISQ_ISQN BITS(0, 4) /*!< nth conversion in inserted sequence */
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ #define ADC_ISQ_IL BITS(20, 21) /*!< inserted sequence length */
/* ADC_IDATAx x=0..3*/ /* ADC_IDATAx x=0..3*/
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ #define ADC_IDATAX_IDATAN BITS(0, 15) /*!< inserted data n */
/* ADC_RDATA */ /* ADC_RDATA */
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ #define ADC_RDATA_RDATA BITS(0, 15) /*!< regular data */
#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ #define ADC_RDATA_ADC1RDTR BITS(16, 31) /*!< ADC1 regular channel data */
/* ADC_OVSCR */ /* ADC_OVSCR */
#define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */ #define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */
#define ADC_OVSCR_OVSR BITS(2,4) /*!< oversampling ratio */ #define ADC_OVSCR_OVSR BITS(2, 4) /*!< oversampling ratio */
#define ADC_OVSCR_OVSS BITS(5,8) /*!< oversampling shift */ #define ADC_OVSCR_OVSS BITS(5, 8) /*!< oversampling shift */
#define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */ #define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */
#define ADC_OVSCR_DRES BITS(12,13) /*!< ADC data resolution */ #define ADC_OVSCR_DRES BITS(12, 13) /*!< ADC data resolution */
/* constants definitions */ /* constants definitions */
/* adc_stat register value */ /* adc_stat register value */
@@ -148,7 +147,7 @@ OF SUCH DAMAGE.
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
/* adc_ctl0 register value */ /* adc_ctl0 register value */
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ #define CTL0_DISNUM(regval) (BITS(13, 15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
/* scan mode */ /* scan mode */
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
@@ -157,7 +156,7 @@ OF SUCH DAMAGE.
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
/* ADC sync mode */ /* ADC sync mode */
#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ #define CTL0_SYNCM(regval) (BITS(16, 19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */
#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
@@ -177,7 +176,7 @@ OF SUCH DAMAGE.
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
/* external trigger select for regular channel */ /* external trigger select for regular channel */
#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ #define CTL1_ETSRC(regval) (BITS(17, 19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */
/* for ADC0 and ADC1 regular channel */ /* for ADC0 and ADC1 regular channel */
#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
@@ -189,7 +188,7 @@ OF SUCH DAMAGE.
#define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ #define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
/* external trigger mode for inserted channel */ /* external trigger mode for inserted channel */
#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ #define CTL1_ETSIC(regval) (BITS(12, 14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */
/* for ADC0 and ADC1 inserted channel */ /* for ADC0 and ADC1 inserted channel */
#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
@@ -201,7 +200,7 @@ OF SUCH DAMAGE.
#define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ #define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
/* adc_samptx register value */ /* adc_samptx register value */
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ #define SAMPTX_SPT(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
@@ -212,19 +211,19 @@ OF SUCH DAMAGE.
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
/* adc_ioffx register value */ /* adc_ioffx register value */
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ #define IOFFX_IOFF(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
/* adc_wdht register value */ /* adc_wdht register value */
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ #define WDHT_WDHT(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
/* adc_wdlt register value */ /* adc_wdlt register value */
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ #define WDLT_WDLT(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
/* adc_rsqx register value */ /* adc_rsqx register value */
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ #define RSQ0_RL(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
/* adc_isq register value */ /* adc_isq register value */
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ #define ISQ_IL(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
/* ADC channel group definitions */ /* ADC channel group definitions */
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ #define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
@@ -270,7 +269,7 @@ OF SUCH DAMAGE.
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ #define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
/* ADC resolution definitions */ /* ADC resolution definitions */
#define OVSCR_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) #define OVSCR_DRES(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12))
#define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */ #define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */
#define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */ #define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */
#define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */ #define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */
@@ -281,7 +280,7 @@ OF SUCH DAMAGE.
#define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */ #define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */
/* ADC oversampling shift */ /* ADC oversampling shift */
#define OVSCR_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) #define OVSCR_OVSS(regval) (BITS(5, 8) & ((uint32_t)(regval) << 5))
#define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */
@@ -293,7 +292,7 @@ OF SUCH DAMAGE.
#define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */
/* ADC oversampling ratio */ /* ADC oversampling ratio */
#define OVSCR_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) #define OVSCR_OVSR(regval) (BITS(2, 4) & ((uint32_t)(regval) << 2))
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */ #define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */ #define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */ #define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */

15
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_bkp.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_BKP_H #define GD32VF103_BKP_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* BKP definitions */ /* BKP definitions */
#define BKP BKP_BASE /*!< BKP base address */ #define BKP BKP_BASE /*!< BKP base address */
@@ -91,10 +91,10 @@ OF SUCH DAMAGE.
/* bits definitions */ /* bits definitions */
/* BKP_DATA */ /* BKP_DATA */
#define BKP_DATA BITS(0,15) /*!< backup data */ #define BKP_DATA BITS(0, 15) /*!< backup data */
/* BKP_OCTL */ /* BKP_OCTL */
#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ #define BKP_OCTL_RCCV BITS(0, 6) /*!< RTC clock calibration value */
#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ #define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */
#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ #define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */
#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ #define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */
@@ -112,8 +112,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* BKP data register number */ /* BKP data register number */
typedef enum typedef enum {
{
BKP_DATA_0 = 1, /*!< BKP data register 0 */ BKP_DATA_0 = 1, /*!< BKP data register 0 */
BKP_DATA_1, /*!< BKP data register 1 */ BKP_DATA_1, /*!< BKP data register 1 */
BKP_DATA_2, /*!< BKP data register 2 */ BKP_DATA_2, /*!< BKP data register 2 */
@@ -156,17 +155,17 @@ typedef enum
BKP_DATA_39, /*!< BKP data register 39 */ BKP_DATA_39, /*!< BKP data register 39 */
BKP_DATA_40, /*!< BKP data register 40 */ BKP_DATA_40, /*!< BKP data register 40 */
BKP_DATA_41, /*!< BKP data register 41 */ BKP_DATA_41, /*!< BKP data register 41 */
}bkp_data_register_enum; } bkp_data_register_enum;
/* BKP register */ /* BKP register */
#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) #define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number)*0x04U)
#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) #define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)
/* get data of BKP data register */ /* get data of BKP data register */
#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) #define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15)
/* RTC clock calibration value */ /* RTC clock calibration value */
#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) #define OCTL_RCCV(regval) (BITS(0, 6) & ((uint32_t)(regval) << 0))
/* RTC output selection */ /* RTC output selection */
#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ #define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */

156
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_can.h vendored
View File

@@ -36,14 +36,13 @@ OF SUCH DAMAGE.
#define GD32VF103_CAN_H #define GD32VF103_CAN_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* CAN definitions */ /* CAN definitions */
#define CAN0 CAN_BASE /*!< CAN0 base address */ #define CAN0 CAN_BASE /*!< CAN0 base address */
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ #define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
/* registers definitions */ /* registers definitions */
#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ #define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */
#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ #define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */
@@ -136,20 +135,20 @@ OF SUCH DAMAGE.
#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ #define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */
/* CAN transmit mailbox bank */ /* CAN transmit mailbox bank */
#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ #define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank)*0x10U)) /*!< CAN transmit mailbox identifier register */
#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ #define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank)*0x10U)) /*!< CAN transmit mailbox property register */
#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ #define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank)*0x10U)) /*!< CAN transmit mailbox data0 register */
#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ #define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank)*0x10U)) /*!< CAN transmit mailbox data1 register */
/* CAN filter bank */ /* CAN filter bank */
#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ #define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank)*0x8U) + 0x0U) /*!< CAN filter data 0 register */
#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ #define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank)*0x8U) + 0x4U) /*!< CAN filter data 1 register */
/* CAN receive fifo mailbox bank */ /* CAN receive fifo mailbox bank */
#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ #define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank)*0x10U)) /*!< CAN receive FIFO mailbox identifier register */
#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ #define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank)*0x10U)) /*!< CAN receive FIFO mailbox property register */
#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ #define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank)*0x10U)) /*!< CAN receive FIFO mailbox data0 register */
#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ #define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank)*0x10U)) /*!< CAN receive FIFO mailbox data1 register */
/* bits definitions */ /* bits definitions */
/* CAN_CTL */ /* CAN_CTL */
@@ -191,7 +190,7 @@ OF SUCH DAMAGE.
#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */
#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */
#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */
#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ #define CAN_TSTAT_NUM BITS(24, 25) /*!< mailbox number */
#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */
#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */
#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */
@@ -200,13 +199,13 @@ OF SUCH DAMAGE.
#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */
/* CAN_RFIFO0 */ /* CAN_RFIFO0 */
#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ #define CAN_RFIFO0_RFL0 BITS(0, 1) /*!< receive FIFO0 length */
#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */
#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */
#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */
/* CAN_RFIFO1 */ /* CAN_RFIFO1 */
#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ #define CAN_RFIFO1_RFL1 BITS(0, 1) /*!< receive FIFO1 length */
#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */
#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */
#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */
@@ -231,15 +230,15 @@ OF SUCH DAMAGE.
#define CAN_ERR_WERR BIT(0) /*!< warning error */ #define CAN_ERR_WERR BIT(0) /*!< warning error */
#define CAN_ERR_PERR BIT(1) /*!< passive error */ #define CAN_ERR_PERR BIT(1) /*!< passive error */
#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */
#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ #define CAN_ERR_ERRN BITS(4, 6) /*!< error number */
#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ #define CAN_ERR_TECNT BITS(16, 23) /*!< transmit error count */
#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ #define CAN_ERR_RECNT BITS(24, 31) /*!< receive error count */
/* CAN_BT */ /* CAN_BT */
#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ #define CAN_BT_BAUDPSC BITS(0, 9) /*!< baudrate prescaler */
#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ #define CAN_BT_BS1 BITS(16, 19) /*!< bit segment 1 */
#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ #define CAN_BT_BS2 BITS(20, 22) /*!< bit segment 2 */
#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ #define CAN_BT_SJW BITS(24, 25) /*!< resynchronization jump width */
#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */
#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */
@@ -247,52 +246,52 @@ OF SUCH DAMAGE.
#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ #define CAN_TMI_TEN BIT(0) /*!< transmit enable */
#define CAN_TMI_FT BIT(1) /*!< frame type */ #define CAN_TMI_FT BIT(1) /*!< frame type */
#define CAN_TMI_FF BIT(2) /*!< frame format */ #define CAN_TMI_FF BIT(2) /*!< frame format */
#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ #define CAN_TMI_EFID BITS(3, 31) /*!< the frame identifier */
#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ #define CAN_TMI_SFID BITS(21, 31) /*!< the frame identifier */
/* CAN_TMPx */ /* CAN_TMPx */
#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ #define CAN_TMP_DLENC BITS(0, 3) /*!< data length code */
#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */
#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ #define CAN_TMP_TS BITS(16, 31) /*!< time stamp */
/* CAN_TMDATA0x */ /* CAN_TMDATA0x */
#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ #define CAN_TMDATA0_DB0 BITS(0, 7) /*!< transmit data byte 0 */
#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ #define CAN_TMDATA0_DB1 BITS(8, 15) /*!< transmit data byte 1 */
#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ #define CAN_TMDATA0_DB2 BITS(16, 23) /*!< transmit data byte 2 */
#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ #define CAN_TMDATA0_DB3 BITS(24, 31) /*!< transmit data byte 3 */
/* CAN_TMDATA1x */ /* CAN_TMDATA1x */
#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ #define CAN_TMDATA1_DB4 BITS(0, 7) /*!< transmit data byte 4 */
#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ #define CAN_TMDATA1_DB5 BITS(8, 15) /*!< transmit data byte 5 */
#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ #define CAN_TMDATA1_DB6 BITS(16, 23) /*!< transmit data byte 6 */
#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ #define CAN_TMDATA1_DB7 BITS(24, 31) /*!< transmit data byte 7 */
/* CAN_RFIFOMIx */ /* CAN_RFIFOMIx */
#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */
#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */
#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ #define CAN_RFIFOMI_EFID BITS(3, 31) /*!< the frame identifier */
#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ #define CAN_RFIFOMI_SFID BITS(21, 31) /*!< the frame identifier */
/* CAN_RFIFOMPx */ /* CAN_RFIFOMPx */
#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ #define CAN_RFIFOMP_DLENC BITS(0, 3) /*!< receive data length code */
#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ #define CAN_RFIFOMP_FI BITS(8, 15) /*!< filter index */
#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ #define CAN_RFIFOMP_TS BITS(16, 31) /*!< time stamp */
/* CAN_RFIFOMDATA0x */ /* CAN_RFIFOMDATA0x */
#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ #define CAN_RFIFOMDATA0_DB0 BITS(0, 7) /*!< receive data byte 0 */
#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ #define CAN_RFIFOMDATA0_DB1 BITS(8, 15) /*!< receive data byte 1 */
#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ #define CAN_RFIFOMDATA0_DB2 BITS(16, 23) /*!< receive data byte 2 */
#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ #define CAN_RFIFOMDATA0_DB3 BITS(24, 31) /*!< receive data byte 3 */
/* CAN_RFIFOMDATA1x */ /* CAN_RFIFOMDATA1x */
#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ #define CAN_RFIFOMDATA1_DB4 BITS(0, 7) /*!< receive data byte 4 */
#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ #define CAN_RFIFOMDATA1_DB5 BITS(8, 15) /*!< receive data byte 5 */
#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ #define CAN_RFIFOMDATA1_DB6 BITS(16, 23) /*!< receive data byte 6 */
#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ #define CAN_RFIFOMDATA1_DB7 BITS(24, 31) /*!< receive data byte 7 */
/* CAN_FCTL */ /* CAN_FCTL */
#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */
#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ #define CAN_FCTL_HBC1F BITS(8, 13) /*!< header bank of CAN1 filter */
/* CAN_FMCFG */ /* CAN_FMCFG */
#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/
@@ -313,12 +312,12 @@ OF SUCH DAMAGE.
/* define the CAN bit position and its register index offset */ /* define the CAN bit position and its register index offset */
#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) #define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) #define CAN_BIT_POS(val) ((uint32_t)(val)&0x1FU)
#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) #define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) #define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12)))
#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) #define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) #define CAN_BIT_POS1(val) ((uint32_t)(val)&0x1FU)
/* register offset */ /* register offset */
#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ #define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */
@@ -443,58 +442,58 @@ typedef enum {
} can_struct_type_enum; } can_struct_type_enum;
/* CAN baudrate prescaler*/ /* CAN baudrate prescaler*/
#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) #define BT_BAUDPSC(regval) (BITS(0, 9) & ((uint32_t)(regval) << 0))
/* CAN bit segment 1*/ /* CAN bit segment 1*/
#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) #define BT_BS1(regval) (BITS(16, 19) & ((uint32_t)(regval) << 16))
/* CAN bit segment 2*/ /* CAN bit segment 2*/
#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) #define BT_BS2(regval) (BITS(20, 22) & ((uint32_t)(regval) << 20))
/* CAN resynchronization jump width*/ /* CAN resynchronization jump width*/
#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) #define BT_SJW(regval) (BITS(24, 25) & ((uint32_t)(regval) << 24))
/* CAN communication mode*/ /* CAN communication mode*/
#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) #define BT_MODE(regval) (BITS(30, 31) & ((uint32_t)(regval) << 30))
/* CAN FDATA high 16 bits */ /* CAN FDATA high 16 bits */
#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) #define FDATA_MASK_HIGH(regval) (BITS(16, 31) & ((uint32_t)(regval) << 16))
/* CAN FDATA low 16 bits */ /* CAN FDATA low 16 bits */
#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) #define FDATA_MASK_LOW(regval) (BITS(0, 15) & ((uint32_t)(regval) << 0))
/* CAN1 filter start bank_number*/ /* CAN1 filter start bank_number*/
#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) #define FCTL_HBC1F(regval) (BITS(8, 13) & ((uint32_t)(regval) << 8))
/* CAN transmit mailbox extended identifier*/ /* CAN transmit mailbox extended identifier*/
#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) #define TMI_EFID(regval) (BITS(3, 31) & ((uint32_t)(regval) << 3))
/* CAN transmit mailbox standard identifier*/ /* CAN transmit mailbox standard identifier*/
#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) #define TMI_SFID(regval) (BITS(21, 31) & ((uint32_t)(regval) << 21))
/* transmit data byte 0 */ /* transmit data byte 0 */
#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) #define TMDATA0_DB0(regval) (BITS(0, 7) & ((uint32_t)(regval) << 0))
/* transmit data byte 1 */ /* transmit data byte 1 */
#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) #define TMDATA0_DB1(regval) (BITS(8, 15) & ((uint32_t)(regval) << 8))
/* transmit data byte 2 */ /* transmit data byte 2 */
#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) #define TMDATA0_DB2(regval) (BITS(16, 23) & ((uint32_t)(regval) << 16))
/* transmit data byte 3 */ /* transmit data byte 3 */
#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) #define TMDATA0_DB3(regval) (BITS(24, 31) & ((uint32_t)(regval) << 24))
/* transmit data byte 4 */ /* transmit data byte 4 */
#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) #define TMDATA1_DB4(regval) (BITS(0, 7) & ((uint32_t)(regval) << 0))
/* transmit data byte 5 */ /* transmit data byte 5 */
#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) #define TMDATA1_DB5(regval) (BITS(8, 15) & ((uint32_t)(regval) << 8))
/* transmit data byte 6 */ /* transmit data byte 6 */
#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) #define TMDATA1_DB6(regval) (BITS(16, 23) & ((uint32_t)(regval) << 16))
/* transmit data byte 7 */ /* transmit data byte 7 */
#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) #define TMDATA1_DB7(regval) (BITS(24, 31) & ((uint32_t)(regval) << 24))
/* receive mailbox extended identifier*/ /* receive mailbox extended identifier*/
#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31)
@@ -542,7 +541,7 @@ typedef enum {
#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31)
/* CAN errors */ /* CAN errors */
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) #define ERR_ERRN(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4))
#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ #define CAN_ERRN_0 ERR_ERRN(0) /* no error */
#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ #define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */
#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ #define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */
@@ -657,12 +656,11 @@ typedef enum {
/* deinitialize CAN */ /* deinitialize CAN */
void can_deinit(uint32_t can_periph); void can_deinit(uint32_t can_periph);
/* initialize CAN struct */ /* initialize CAN struct */
void can_struct_para_init(can_struct_type_enum type, void* p_struct); void can_struct_para_init(can_struct_type_enum type, void *p_struct);
/* initialize CAN */ /* initialize CAN */
ErrStatus can_init(uint32_t can_periph, ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init);
can_parameter_struct* can_parameter_init);
/* CAN filter init */ /* CAN filter init */
void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init);
/* set can1 fliter start bank number */ /* set can1 fliter start bank number */
void can1_filter_start_bank(uint8_t start_bank); void can1_filter_start_bank(uint8_t start_bank);
/* enable functions */ /* enable functions */
@@ -677,16 +675,13 @@ void can_time_trigger_mode_disable(uint32_t can_periph);
/* transmit functions */ /* transmit functions */
/* transmit CAN message */ /* transmit CAN message */
uint8_t can_message_transmit(uint32_t can_periph, uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message);
can_trasnmit_message_struct* transmit_message);
/* get CAN transmit state */ /* get CAN transmit state */
can_transmit_state_enum can_transmit_states(uint32_t can_periph, can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
uint8_t mailbox_number);
/* stop CAN transmission */ /* stop CAN transmission */
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
/* CAN receive message */ /* CAN receive message */
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message);
can_receive_message_struct* receive_message);
/* CAN release fifo */ /* CAN release fifo */
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
/* CAN receive message length */ /* CAN receive message length */
@@ -712,8 +707,7 @@ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
/* CAN clear flag state */ /* CAN clear flag state */
void can_flag_clear(uint32_t can_periph, can_flag_enum flag); void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
/* CAN get interrupt flag state */ /* CAN get interrupt flag state */
FlagStatus can_interrupt_flag_get(uint32_t can_periph, FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
can_interrupt_flag_enum flag);
/* CAN clear interrupt flag state */ /* CAN clear interrupt flag state */
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);

2
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_crc.h vendored
View File

@@ -37,8 +37,8 @@ OF SUCH DAMAGE.
#define GD32VF103_CRC_H #define GD32VF103_CRC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* CRC definitions */ /* CRC definitions */
#define CRC CRC_BASE #define CRC CRC_BASE

50
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dac.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_DAC_H #define GD32VF103_DAC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* DACx(x=0,1) definitions */ /* DACx(x=0,1) definitions */
#define DAC DAC_BASE #define DAC DAC_BASE
@@ -64,16 +64,16 @@ OF SUCH DAMAGE.
#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ #define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */
#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ #define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */
#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ #define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */
#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ #define DAC_CTL_DTSEL0 BITS(3, 5) /*!< DAC0 trigger source selection enable/disable bits */
#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ #define DAC_CTL_DWM0 BITS(6, 7) /*!< DAC0 noise wave mode */
#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ #define DAC_CTL_DWBW0 BITS(8, 11) /*!< DAC0 noise wave bit width */
#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */
#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ #define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */
#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */
#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */
#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ #define DAC_CTL_DTSEL1 BITS(19, 21) /*!< DAC1 trigger source selection enable/disable bits */
#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ #define DAC_CTL_DWM1 BITS(22, 23) /*!< DAC1 noise wave mode */
#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ #define DAC_CTL_DWBW1 BITS(24, 27) /*!< DAC1 noise wave bit width */
#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ #define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */
/* DAC_SWT */ /* DAC_SWT */
@@ -81,44 +81,44 @@ OF SUCH DAMAGE.
#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ #define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */
/* DAC0_R12DH */ /* DAC0_R12DH */
#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ #define DAC0_R12DH_DAC0_DH BITS(0, 11) /*!< DAC0 12-bit right-aligned data bits */
/* DAC0_L12DH */ /* DAC0_L12DH */
#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ #define DAC0_L12DH_DAC0_DH BITS(4, 15) /*!< DAC0 12-bit left-aligned data bits */
/* DAC0_R8DH */ /* DAC0_R8DH */
#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ #define DAC0_R8DH_DAC0_DH BITS(0, 7) /*!< DAC0 8-bit right-aligned data bits */
/* DAC1_R12DH */ /* DAC1_R12DH */
#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ #define DAC1_R12DH_DAC1_DH BITS(0, 11) /*!< DAC1 12-bit right-aligned data bits */
/* DAC1_L12DH */ /* DAC1_L12DH */
#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ #define DAC1_L12DH_DAC1_DH BITS(4, 15) /*!< DAC1 12-bit left-aligned data bits */
/* DAC1_R8DH */ /* DAC1_R8DH */
#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ #define DAC1_R8DH_DAC1_DH BITS(0, 7) /*!< DAC1 8-bit right-aligned data bits */
/* DACC_R12DH */ /* DACC_R12DH */
#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ #define DACC_R12DH_DAC0_DH BITS(0, 11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ #define DACC_R12DH_DAC1_DH BITS(16, 27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
/* DACC_L12DH */ /* DACC_L12DH */
#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ #define DACC_L12DH_DAC0_DH BITS(4, 15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ #define DACC_L12DH_DAC1_DH BITS(20, 31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
/* DACC_R8DH */ /* DACC_R8DH */
#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ #define DACC_R8DH_DAC0_DH BITS(0, 7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ #define DACC_R8DH_DAC1_DH BITS(8, 15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
/* DAC0_DO */ /* DAC0_DO */
#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ #define DAC0_DO_DAC0_DO BITS(0, 11) /*!< DAC0 12-bit output data bits */
/* DAC1_DO */ /* DAC1_DO */
#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ #define DAC1_DO_DAC1_DO BITS(0, 11) /*!< DAC1 12-bit output data bits */
/* constants definitions */ /* constants definitions */
/* DAC trigger source */ /* DAC trigger source */
#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) #define CTL_DTSEL(regval) (BITS(3, 5) & ((uint32_t)(regval) << 3))
#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */
#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ #define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */
#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ #define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */
@@ -129,13 +129,13 @@ OF SUCH DAMAGE.
#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */
/* DAC noise wave mode */ /* DAC noise wave mode */
#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) #define CTL_DWM(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6))
#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ #define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */
#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ #define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */
#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */
/* DAC noise wave bit width */ /* DAC noise wave bit width */
#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) #define DWBW(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8))
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ #define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ #define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ #define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
@@ -164,7 +164,7 @@ OF SUCH DAMAGE.
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
/* DAC data alignment */ /* DAC data alignment */
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) #define DATA_ALIGN(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0))
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ #define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ #define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ #define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */

8
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dbg.h vendored
View File

@@ -38,7 +38,6 @@ OF SUCH DAMAGE.
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h" #include "gd32vf103_rcu.h"
/* DBG definitions */ /* DBG definitions */
#define DBG DBG_BASE #define DBG DBG_BASE
@@ -48,7 +47,7 @@ OF SUCH DAMAGE.
/* bits definitions */ /* bits definitions */
/* DBG_ID */ /* DBG_ID */
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ #define DBG_ID_ID_CODE BITS(0, 31) /*!< DBG ID code values */
/* DBG_CTL */ /* DBG_CTL */
#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ #define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
@@ -70,8 +69,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* debug hold when core is halted */ /* debug hold when core is halted */
typedef enum typedef enum {
{
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
@@ -85,7 +83,7 @@ typedef enum
DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */
DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */
DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */
}dbg_periph_enum; } dbg_periph_enum;
/* DBG low power mode configurations */ /* DBG low power mode configurations */
#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ #define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */

34
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dma.h vendored
View File

@@ -36,9 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_DMA_H #define GD32VF103_DMA_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* DMA definitions */ /* DMA definitions */
#define DMA0 (DMA_BASE) /*!< DMA0 base address */ #define DMA0 (DMA_BASE) /*!< DMA0 base address */
@@ -105,24 +104,23 @@ OF SUCH DAMAGE.
#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ #define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ #define DMA_CHXCTL_PWIDTH BITS(8, 9) /*!< transfer data width of peripheral */
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ #define DMA_CHXCTL_MWIDTH BITS(10, 11) /*!< transfer data width of memory */
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ #define DMA_CHXCTL_PRIO BITS(12, 13) /*!< priority level */
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
/* DMA_CHxCNT, x=0..6 */ /* DMA_CHxCNT, x=0..6 */
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ #define DMA_CHXCNT_CNT BITS(0, 15) /*!< transfer counter */
/* DMA_CHxPADDR, x=0..6 */ /* DMA_CHxPADDR, x=0..6 */
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ #define DMA_CHXPADDR_PADDR BITS(0, 31) /*!< peripheral base address */
/* DMA_CHxMADDR, x=0..6 */ /* DMA_CHxMADDR, x=0..6 */
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ #define DMA_CHXMADDR_MADDR BITS(0, 31) /*!< memory base address */
/* constants definitions */ /* constants definitions */
/* DMA channel select */ /* DMA channel select */
typedef enum typedef enum {
{
DMA_CH0 = 0, /*!< DMA Channel0 */ DMA_CH0 = 0, /*!< DMA Channel0 */
DMA_CH1, /*!< DMA Channel1 */ DMA_CH1, /*!< DMA Channel1 */
DMA_CH2, /*!< DMA Channel2 */ DMA_CH2, /*!< DMA Channel2 */
@@ -133,8 +131,7 @@ typedef enum
} dma_channel_enum; } dma_channel_enum;
/* DMA initialize struct */ /* DMA initialize struct */
typedef struct typedef struct {
{
uint32_t periph_addr; /*!< peripheral base address */ uint32_t periph_addr; /*!< peripheral base address */
uint32_t periph_width; /*!< transfer data size of peripheral */ uint32_t periph_width; /*!< transfer data size of peripheral */
uint32_t memory_addr; /*!< memory base address */ uint32_t memory_addr; /*!< memory base address */
@@ -147,7 +144,7 @@ typedef struct
} dma_parameter_struct; } dma_parameter_struct;
#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ #define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift)*4U)) /*!< DMA channel flag shift */
/* DMA_register address */ /* DMA_register address */
#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ #define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
@@ -160,8 +157,7 @@ typedef struct
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ #define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
/* DMA_INTF register */ /* DMA_INTF register */
/* interrupt flag bits */ /* interrupt flag bits */
@@ -195,19 +191,19 @@ typedef struct
#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */ #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */
/* transfer data size of peripheral */ /* transfer data size of peripheral */
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ #define CHCTL_PWIDTH(regval) (BITS(8, 9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
/* transfer data size of memory */ /* transfer data size of memory */
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ #define CHCTL_MWIDTH(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
/* channel priority level */ /* channel priority level */
#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ #define CHCTL_PRIO(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */
#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ #define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ #define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
@@ -226,7 +222,7 @@ typedef struct
/* deinitialize DMA a channel registers */ /* deinitialize DMA a channel registers */
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
/* initialize the parameters of DMA struct with the default values */ /* initialize the parameters of DMA struct with the default values */
void dma_struct_para_init(dma_parameter_struct* init_struct); void dma_struct_para_init(dma_parameter_struct *init_struct);
/* initialize DMA channel */ /* initialize DMA channel */
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct);
/* enable DMA circulation mode */ /* enable DMA circulation mode */

35
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exmc.h vendored
View File

@@ -36,9 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_EXMC_H #define GD32VF103_EXMC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* EXMC definitions */ /* EXMC definitions */
#define EXMC (EXMC_BASE) /*!< EXMC register base address */ #define EXMC (EXMC_BASE) /*!< EXMC register base address */
@@ -54,8 +53,8 @@ OF SUCH DAMAGE.
/* EXMC_SNCTLx, x=0 */ /* EXMC_SNCTLx, x=0 */
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ #define EXMC_SNCTL_NRTP BITS(2, 3) /*!< NOR bank memory type */
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ #define EXMC_SNCTL_NRW BITS(4, 5) /*!< NOR bank memory data bus width */
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ #define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
@@ -63,24 +62,22 @@ OF SUCH DAMAGE.
#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */
/* EXMC_SNTCFGx, x=0 */ /* EXMC_SNTCFGx, x=0 */
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ #define EXMC_SNTCFG_ASET BITS(0, 3) /*!< address setup time */
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ #define EXMC_SNTCFG_AHLD BITS(4, 7) /*!< address hold time */
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ #define EXMC_SNTCFG_DSET BITS(8, 15) /*!< data setup time */
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ #define EXMC_SNTCFG_BUSLAT BITS(16, 19) /*!< bus latency */
/* constants definitions */ /* constants definitions */
/* EXMC NOR/SRAM timing initialize struct */ /* EXMC NOR/SRAM timing initialize struct */
typedef struct typedef struct {
{
uint32_t bus_latency; /*!< configure the bus latency */ uint32_t bus_latency; /*!< configure the bus latency */
uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
}exmc_norsram_timing_parameter_struct; } exmc_norsram_timing_parameter_struct;
/* EXMC NOR/SRAM initialize struct */ /* EXMC NOR/SRAM initialize struct */
typedef struct typedef struct {
{
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */ uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */
@@ -89,20 +86,20 @@ typedef struct
uint32_t databus_width; /*!< specifies the databus width of external memory */ uint32_t databus_width; /*!< specifies the databus width of external memory */
uint32_t memory_type; /*!< specifies the type of external memory */ uint32_t memory_type; /*!< specifies the type of external memory */
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write */ exmc_norsram_timing_parameter_struct *read_write_timing; /*!< timing parameters for read and write */
}exmc_norsram_parameter_struct; } exmc_norsram_parameter_struct;
/* EXMC register address */ /* EXMC register address */
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ #define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */
/* NOR bank memory data bus width */ /* NOR bank memory data bus width */
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) #define SNCTL_NRW(regval) (BITS(4, 5) & ((uint32_t)(regval) << 4))
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */
/* NOR bank memory type */ /* NOR bank memory type */
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) #define SNCTL_NRTP(regval) (BITS(2, 3) & ((uint32_t)(regval) << 2))
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
@@ -118,9 +115,9 @@ typedef struct
/* deinitialize EXMC NOR/SRAM region */ /* deinitialize EXMC NOR/SRAM region */
void exmc_norsram_deinit(uint32_t norsram_region); void exmc_norsram_deinit(uint32_t norsram_region);
/* exmc_norsram_parameter_struct parameter initialize */ /* exmc_norsram_parameter_struct parameter initialize */
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct);
/* initialize EXMC NOR/SRAM region */ /* initialize EXMC NOR/SRAM region */
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct);
/* EXMC NOR/SRAM bank enable */ /* EXMC NOR/SRAM bank enable */
void exmc_norsram_enable(uint32_t norsram_region); void exmc_norsram_enable(uint32_t norsram_region);
/* EXMC NOR/SRAM bank disable */ /* EXMC NOR/SRAM bank disable */

3
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exti.h vendored
View File

@@ -36,9 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_EXTI_H #define GD32VF103_EXTI_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* EXTI definitions */ /* EXTI definitions */
#define EXTI EXTI_BASE #define EXTI EXTI_BASE

45
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fmc.h vendored
View File

@@ -36,9 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_FMC_H #define GD32VF103_FMC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* FMC and option byte definition */ /* FMC and option byte definition */
#define FMC FMC_BASE /*!< FMC register base address */ #define FMC FMC_BASE /*!< FMC register base address */
@@ -64,13 +63,13 @@ OF SUCH DAMAGE.
/* bits definitions */ /* bits definitions */
/* FMC_WS */ /* FMC_WS */
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ #define FMC_WS_WSCNT BITS(0, 2) /*!< wait state counter */
/* FMC_KEY0 */ /* FMC_KEY0 */
#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ #define FMC_KEY0_KEY BITS(0, 31) /*!< FMC_CTL0 unlock key bits */
/* FMC_OBKEY */ /* FMC_OBKEY */
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ #define FMC_OBKEY_OBKEY BITS(0, 31) /*!< option bytes unlock key bits */
/* FMC_STAT0 */ /* FMC_STAT0 */
#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ #define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */
@@ -91,32 +90,32 @@ OF SUCH DAMAGE.
#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ #define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
/* FMC_ADDR0 */ /* FMC_ADDR0 */
#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ #define FMC_ADDR0_ADDR BITS(0, 31) /*!< Flash erase/program command address bits */
/* FMC_OBSTAT */ /* FMC_OBSTAT */
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */
#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */
#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ #define FMC_OBSTAT_USER BITS(2, 9) /*!< store USER of option bytes block after system reset */
#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ #define FMC_OBSTAT_DATA BITS(10, 25) /*!< store DATA of option bytes block after system reset. */
/* FMC_WP */ /* FMC_WP */
#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ #define FMC_WP_WP BITS(0, 31) /*!< store WP of option bytes block after system reset */
/* FMC_WSEN */ /* FMC_WSEN */
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
/* FMC_PID */ /* FMC_PID */
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ #define FMC_PID_PID BITS(0, 31) /*!< product ID bits */
/* constants definitions */ /* constants definitions */
/* define the FMC bit position and its register index offset */ /* define the FMC bit position and its register index offset */
#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) #define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6)))
#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) #define FMC_BIT_POS(val) ((uint32_t)(val)&0x1FU)
#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) #define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) #define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12)))
#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) #define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) #define FMC_BIT_POS1(val) ((uint32_t)(val)&0x1FU)
#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) #define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12)
/* configuration register */ /* configuration register */
@@ -125,46 +124,42 @@ OF SUCH DAMAGE.
#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ #define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
/* fmc state */ /* fmc state */
typedef enum typedef enum {
{
FMC_READY, /*!< the operation has been completed */ FMC_READY, /*!< the operation has been completed */
FMC_BUSY, /*!< the operation is in progress */ FMC_BUSY, /*!< the operation is in progress */
FMC_PGERR, /*!< program error */ FMC_PGERR, /*!< program error */
FMC_WPERR, /*!< erase/program protection error */ FMC_WPERR, /*!< erase/program protection error */
FMC_TOERR, /*!< timeout error */ FMC_TOERR, /*!< timeout error */
}fmc_state_enum; } fmc_state_enum;
/* FMC interrupt enable */ /* FMC interrupt enable */
typedef enum typedef enum {
{
FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
}fmc_int_enum; } fmc_int_enum;
/* FMC flags */ /* FMC flags */
typedef enum typedef enum {
{
FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC busy flag */ FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC busy flag */
FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC operation error flag bit */ FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC operation error flag bit */
FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */ FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */
FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC end of operation flag bit */ FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC end of operation flag bit */
FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */
}fmc_flag_enum; } fmc_flag_enum;
/* FMC interrupt flags */ /* FMC interrupt flags */
typedef enum typedef enum {
{
FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */ FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */
FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */ FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */
FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */ FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */
}fmc_interrupt_flag_enum; } fmc_interrupt_flag_enum;
/* unlock key */ /* unlock key */
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ #define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
/* FMC wait state counter */ /* FMC wait state counter */
#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) #define WS_WSCNT(regval) (BITS(0, 2) & ((uint32_t)(regval)))
#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ #define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */
#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ #define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */
#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ #define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */

11
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fwdgt.h vendored
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@@ -36,9 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_FWDGT_H #define GD32VF103_FWDGT_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* FWDGT definitions */ /* FWDGT definitions */
#define FWDGT FWDGT_BASE /*!< FWDGT base address */ #define FWDGT FWDGT_BASE /*!< FWDGT base address */
@@ -51,13 +50,13 @@ OF SUCH DAMAGE.
/* bits definitions */ /* bits definitions */
/* FWDGT_CTL */ /* FWDGT_CTL */
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ #define FWDGT_CTL_CMD BITS(0, 15) /*!< FWDGT command value */
/* FWDGT_PSC */ /* FWDGT_PSC */
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ #define FWDGT_PSC_PSC BITS(0, 2) /*!< FWDGT prescaler divider value */
/* FWDGT_RLD */ /* FWDGT_RLD */
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ #define FWDGT_RLD_RLD BITS(0, 11) /*!< FWDGT counter reload value */
/* FWDGT_STAT */ /* FWDGT_STAT */
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ #define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
@@ -65,7 +64,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* psc register value */ /* psc register value */
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) #define PSC_PSC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0))
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */

4
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_gpio.h vendored
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@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_GPIO_H #define GD32VF103_GPIO_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* GPIOx(x=A,B,C,D,E) definitions */ /* GPIOx(x=A,B,C,D,E) definitions */
#define GPIOA (GPIO_BASE + 0x00000000U) #define GPIOA (GPIO_BASE + 0x00000000U)
@@ -385,7 +385,7 @@ void gpio_deinit(uint32_t gpio_periph);
/* reset alternate function I/O(AFIO) */ /* reset alternate function I/O(AFIO) */
void gpio_afio_deinit(void); void gpio_afio_deinit(void);
/* GPIO parameter initialization */ /* GPIO parameter initialization */
void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin); void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin);
/* set GPIO pin bit */ /* set GPIO pin bit */
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);

67
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_i2c.h vendored
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@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_I2C_H #define GD32VF103_I2C_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* I2Cx(x=0,1) definitions */ /* I2Cx(x=0,1) definitions */
#define I2C0 I2C_BASE /*!< I2C0 base address */ #define I2C0 I2C_BASE /*!< I2C0 base address */
@@ -72,7 +72,7 @@ OF SUCH DAMAGE.
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ #define I2C_CTL0_SRESET BIT(15) /*!< software reset */
/* I2Cx_CTL1 */ /* I2Cx_CTL1 */
#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ #define I2C_CTL1_I2CCLK BITS(0, 5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
@@ -81,16 +81,16 @@ OF SUCH DAMAGE.
/* I2Cx_SADDR0 */ /* I2Cx_SADDR0 */
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ #define I2C_SADDR0_ADDRESS BITS(1, 7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ #define I2C_SADDR0_ADDRESS_H BITS(8, 9) /*!< highest two bits of a 10-bit address */
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
/* I2Cx_SADDR1 */ /* I2Cx_SADDR1 */
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ #define I2C_SADDR1_ADDRESS2 BITS(1, 7) /*!< second I2C address for the slave in dual-address mode */
/* I2Cx_DATA */ /* I2Cx_DATA */
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ #define I2C_DATA_TRB BITS(0, 7) /*!< 8-bit data register */
/* I2Cx_STAT0 */ /* I2Cx_STAT0 */
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
@@ -116,25 +116,24 @@ OF SUCH DAMAGE.
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ #define I2C_STAT1_PECV BITS(8, 15) /*!< packet error checking value */
/* I2Cx_CKCFG */ /* I2Cx_CKCFG */
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ #define I2C_CKCFG_CLKC BITS(0, 11) /*!< clock control register in fast/standard mode (master mode) */
#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ #define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
/* I2Cx_RT */ /* I2Cx_RT */
#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ #define I2C_RT_RISETIME BITS(0, 5) /*!< maximum rise time in fast/standard mode (Master mode) */
/* constants definitions */ /* constants definitions */
/* define the I2C bit position and its register index offset */ /* define the I2C bit position and its register index offset */
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset)&0xFFFFU) >> 6)))
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) #define I2C_BIT_POS(val) ((uint32_t)(val)&0x1FU)
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ #define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) #define I2C_BIT_POS2(val) (((uint32_t)(val)&0x1F0000U) >> 16)
/* register offset */ /* register offset */
#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ #define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */
@@ -171,20 +170,20 @@ typedef enum {
/* I2C interrupt flags */ /* I2C interrupt flags */
typedef enum { typedef enum {
/* interrupt flags in CTL1 register */ /* interrupt flags in CTL1 register */
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
} i2c_interrupt_flag_enum; } i2c_interrupt_flag_enum;
/* I2C interrupt enable or disable */ /* I2C interrupt enable or disable */
@@ -259,7 +258,7 @@ typedef enum {
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ #define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */
/* transmit I2C data */ /* transmit I2C data */
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) #define DATA_TRANS(regval) (BITS(0, 7) & ((uint32_t)(regval) << 0))
/* receive I2C data */ /* receive I2C data */
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
@@ -278,7 +277,7 @@ void i2c_deinit(uint32_t i2c_periph);
/* configure I2C clock */ /* configure I2C clock */
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
/* configure I2C address */ /* configure I2C address */
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr); void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
/* SMBus type selection */ /* SMBus type selection */
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
/* whether or not to send an ACK */ /* whether or not to send an ACK */
@@ -286,9 +285,9 @@ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
/* configure I2C POAP position */ /* configure I2C POAP position */
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
/* master sends slave address */ /* master sends slave address */
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection); void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
/* configure I2C saddress1 */ /* configure I2C saddress1 */
void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr); void i2c_saddr1_config(uint32_t i2c_periph, uint32_t addr);
/* enable dual-address mode */ /* enable dual-address mode */
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr);
/* disable dual-address mode */ /* disable dual-address mode */
@@ -337,8 +336,8 @@ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
/* disable I2C interrupt */ /* disable I2C interrupt */
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
/* check I2C interrupt flag */ /* check I2C interrupt flag */
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag); FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
/* clear I2C interrupt flag */ /* clear I2C interrupt flag */
void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag); void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
#endif /* GD32VF103_I2C_H */ #endif /* GD32VF103_I2C_H */

6
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_libopt.h vendored
View File

@@ -43,14 +43,15 @@ extern "C" {
#include "gd32vf103_can.h" #include "gd32vf103_can.h"
#include "gd32vf103_crc.h" #include "gd32vf103_crc.h"
#include "gd32vf103_dac.h" #include "gd32vf103_dac.h"
#include "gd32vf103_dbg.h"
#include "gd32vf103_dma.h" #include "gd32vf103_dma.h"
#include "gd32vf103_eclic.h"
#include "gd32vf103_exmc.h" #include "gd32vf103_exmc.h"
#include "gd32vf103_exti.h" #include "gd32vf103_exti.h"
#include "gd32vf103_fmc.h" #include "gd32vf103_fmc.h"
#include "gd32vf103_fwdgt.h"
#include "gd32vf103_gpio.h" #include "gd32vf103_gpio.h"
#include "gd32vf103_i2c.h" #include "gd32vf103_i2c.h"
#include "gd32vf103_fwdgt.h"
#include "gd32vf103_dbg.h"
#include "gd32vf103_pmu.h" #include "gd32vf103_pmu.h"
#include "gd32vf103_rcu.h" #include "gd32vf103_rcu.h"
#include "gd32vf103_rtc.h" #include "gd32vf103_rtc.h"
@@ -58,7 +59,6 @@ extern "C" {
#include "gd32vf103_timer.h" #include "gd32vf103_timer.h"
#include "gd32vf103_usart.h" #include "gd32vf103_usart.h"
#include "gd32vf103_wwdgt.h" #include "gd32vf103_wwdgt.h"
#include "gd32vf103_eclic.h"
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

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