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This commit is contained in:
Ben V. Brown
2021-01-17 10:53:49 +11:00
parent f786901da0
commit bf5055edaa
173 changed files with 42831 additions and 47623 deletions
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4
source/Core/BSP/BSP.h
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@@ -1,10 +1,10 @@
#include <stdint.h>
#include <stdbool.h>
#include "BSP_Flash.h" #include "BSP_Flash.h"
#include "BSP_Power.h" #include "BSP_Power.h"
#include "BSP_QC.h" #include "BSP_QC.h"
#include "Defines.h" #include "Defines.h"
#include "Model_Config.h" #include "Model_Config.h"
#include <stdbool.h>
#include <stdint.h>
/* /*
* BSP.h -- Board Support * BSP.h -- Board Support
* *

1
source/Core/BSP/BSP_Power.h
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@@ -12,7 +12,6 @@
extern "C" { extern "C" {
#endif #endif
// Called periodically in the movement handling thread // Called periodically in the movement handling thread
// Can be used to check any details for the power system // Can be used to check any details for the power system
void power_check(); void power_check();

5
source/Core/BSP/Defines.h
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@@ -8,10 +8,7 @@
#ifndef BSP_DEFINES_H_ #ifndef BSP_DEFINES_H_
#define BSP_DEFINES_H_ #define BSP_DEFINES_H_
enum Orientation { ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3 };
enum Orientation {
ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3
};
// It is assumed that all hardware implements an 8Hz update period at this time // It is assumed that all hardware implements an 8Hz update period at this time
#define PID_TIM_HZ (8) #define PID_TIM_HZ (8)

7
source/Core/BSP/Miniware/FreeRTOSConfig.h
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@@ -154,7 +154,12 @@ extern uint32_t SystemCoreClock;
/* Normal assert() semantics without relying on the provision of an assert.h /* Normal assert() semantics without relying on the provision of an assert.h
header file. */ header file. */
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} #define configASSERT(x) \
if ((x) == 0) { \
taskDISABLE_INTERRUPTS(); \
for (;;) \
; \
}
/* USER CODE END 1 */ /* USER CODE END 1 */
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS

2
source/Core/BSP/Miniware/IRQ.h
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@@ -9,10 +9,10 @@
#define BSP_MINIWARE_IRQ_H_ #define BSP_MINIWARE_IRQ_H_
#include "BSP.h" #include "BSP.h"
#include "stm32f1xx_hal.h"
#include "I2C_Wrapper.hpp" #include "I2C_Wrapper.hpp"
#include "Setup.h" #include "Setup.h"
#include "main.hpp" #include "main.hpp"
#include "stm32f1xx_hal.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

9
source/Core/BSP/Miniware/Software_I2C.h
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@@ -7,8 +7,8 @@
#ifndef BSP_MINIWARE_SOFTWARE_I2C_H_ #ifndef BSP_MINIWARE_SOFTWARE_I2C_H_
#define BSP_MINIWARE_SOFTWARE_I2C_H_ #define BSP_MINIWARE_SOFTWARE_I2C_H_
#include "Model_Config.h"
#include "BSP.h" #include "BSP.h"
#include "Model_Config.h"
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
#ifdef I2C_SOFT #ifdef I2C_SOFT
@@ -18,7 +18,12 @@
#define SOFT_SDA_LOW() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET) #define SOFT_SDA_LOW() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET)
#define SOFT_SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port, SDA2_Pin) == GPIO_PIN_SET ? 1 : 0) #define SOFT_SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port, SDA2_Pin) == GPIO_PIN_SET ? 1 : 0)
#define SOFT_SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port, SCL2_Pin) == GPIO_PIN_SET ? 1 : 0) #define SOFT_SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port, SCL2_Pin) == GPIO_PIN_SET ? 1 : 0)
#define SOFT_I2C_DELAY() {for(int xx=0;xx<40;xx++){asm("nop");}} #define SOFT_I2C_DELAY() \
{ \
for (int xx = 0; xx < 40; xx++) { \
asm("nop"); \
} \
}
#endif #endif

366
source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h vendored
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@@ -43,7 +43,6 @@
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
@@ -84,8 +83,7 @@
*/ */
/*!< Interrupt Number Definition */ /*!< Interrupt Number Definition */
typedef enum typedef enum {
{
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
@@ -159,8 +157,7 @@ typedef enum
* @brief Analog to Digital Converter * @brief Analog to Digital Converter
*/ */
typedef struct typedef struct {
{
__IO uint32_t SR; __IO uint32_t SR;
__IO uint32_t CR1; __IO uint32_t CR1;
__IO uint32_t CR2; __IO uint32_t CR2;
@@ -183,8 +180,7 @@ typedef struct
__IO uint32_t DR; __IO uint32_t DR;
} ADC_TypeDef; } ADC_TypeDef;
typedef struct typedef struct {
{
__IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
__IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
@@ -196,8 +192,7 @@ typedef struct
* @brief Backup Registers * @brief Backup Registers
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0; uint32_t RESERVED0;
__IO uint32_t DR1; __IO uint32_t DR1;
__IO uint32_t DR2; __IO uint32_t DR2;
@@ -218,8 +213,7 @@ typedef struct
* @brief Controller Area Network TxMailBox * @brief Controller Area Network TxMailBox
*/ */
typedef struct typedef struct {
{
__IO uint32_t TIR; __IO uint32_t TIR;
__IO uint32_t TDTR; __IO uint32_t TDTR;
__IO uint32_t TDLR; __IO uint32_t TDLR;
@@ -230,8 +224,7 @@ typedef struct
* @brief Controller Area Network FIFOMailBox * @brief Controller Area Network FIFOMailBox
*/ */
typedef struct typedef struct {
{
__IO uint32_t RIR; __IO uint32_t RIR;
__IO uint32_t RDTR; __IO uint32_t RDTR;
__IO uint32_t RDLR; __IO uint32_t RDLR;
@@ -242,8 +235,7 @@ typedef struct
* @brief Controller Area Network FilterRegister * @brief Controller Area Network FilterRegister
*/ */
typedef struct typedef struct {
{
__IO uint32_t FR1; __IO uint32_t FR1;
__IO uint32_t FR2; __IO uint32_t FR2;
} CAN_FilterRegister_TypeDef; } CAN_FilterRegister_TypeDef;
@@ -252,8 +244,7 @@ typedef struct
* @brief Controller Area Network * @brief Controller Area Network
*/ */
typedef struct typedef struct {
{
__IO uint32_t MCR; __IO uint32_t MCR;
__IO uint32_t MSR; __IO uint32_t MSR;
__IO uint32_t TSR; __IO uint32_t TSR;
@@ -282,8 +273,7 @@ typedef struct
* @brief CRC calculation unit * @brief CRC calculation unit
*/ */
typedef struct typedef struct {
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
@@ -291,13 +281,11 @@ typedef struct
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
} CRC_TypeDef; } CRC_TypeDef;
/** /**
* @brief Debug MCU * @brief Debug MCU
*/ */
typedef struct typedef struct {
{
__IO uint32_t IDCODE; __IO uint32_t IDCODE;
__IO uint32_t CR; __IO uint32_t CR;
} DBGMCU_TypeDef; } DBGMCU_TypeDef;
@@ -306,28 +294,23 @@ typedef struct
* @brief DMA Controller * @brief DMA Controller
*/ */
typedef struct typedef struct {
{
__IO uint32_t CCR; __IO uint32_t CCR;
__IO uint32_t CNDTR; __IO uint32_t CNDTR;
__IO uint32_t CPAR; __IO uint32_t CPAR;
__IO uint32_t CMAR; __IO uint32_t CMAR;
} DMA_Channel_TypeDef; } DMA_Channel_TypeDef;
typedef struct typedef struct {
{
__IO uint32_t ISR; __IO uint32_t ISR;
__IO uint32_t IFCR; __IO uint32_t IFCR;
} DMA_TypeDef; } DMA_TypeDef;
/** /**
* @brief External Interrupt/Event Controller * @brief External Interrupt/Event Controller
*/ */
typedef struct typedef struct {
{
__IO uint32_t IMR; __IO uint32_t IMR;
__IO uint32_t EMR; __IO uint32_t EMR;
__IO uint32_t RTSR; __IO uint32_t RTSR;
@@ -340,8 +323,7 @@ typedef struct
* @brief FLASH Registers * @brief FLASH Registers
*/ */
typedef struct typedef struct {
{
__IO uint32_t ACR; __IO uint32_t ACR;
__IO uint32_t KEYR; __IO uint32_t KEYR;
__IO uint32_t OPTKEYR; __IO uint32_t OPTKEYR;
@@ -357,8 +339,7 @@ typedef struct
* @brief Option Bytes Registers * @brief Option Bytes Registers
*/ */
typedef struct typedef struct {
{
__IO uint16_t RDP; __IO uint16_t RDP;
__IO uint16_t USER; __IO uint16_t USER;
__IO uint16_t Data0; __IO uint16_t Data0;
@@ -373,8 +354,7 @@ typedef struct
* @brief General Purpose I/O * @brief General Purpose I/O
*/ */
typedef struct typedef struct {
{
__IO uint32_t CRL; __IO uint32_t CRL;
__IO uint32_t CRH; __IO uint32_t CRH;
__IO uint32_t IDR; __IO uint32_t IDR;
@@ -388,8 +368,7 @@ typedef struct
* @brief Alternate Function I/O * @brief Alternate Function I/O
*/ */
typedef struct typedef struct {
{
__IO uint32_t EVCR; __IO uint32_t EVCR;
__IO uint32_t MAPR; __IO uint32_t MAPR;
__IO uint32_t EXTICR[4]; __IO uint32_t EXTICR[4];
@@ -400,8 +379,7 @@ typedef struct
* @brief Inter Integrated Circuit Interface * @brief Inter Integrated Circuit Interface
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR1; __IO uint32_t CR1;
__IO uint32_t CR2; __IO uint32_t CR2;
__IO uint32_t OAR1; __IO uint32_t OAR1;
@@ -417,8 +395,7 @@ typedef struct
* @brief Independent WATCHDOG * @brief Independent WATCHDOG
*/ */
typedef struct typedef struct {
{
__IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
@@ -429,8 +406,7 @@ typedef struct
* @brief Power Control * @brief Power Control
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR; __IO uint32_t CR;
__IO uint32_t CSR; __IO uint32_t CSR;
} PWR_TypeDef; } PWR_TypeDef;
@@ -439,8 +415,7 @@ typedef struct
* @brief Reset and Clock Control * @brief Reset and Clock Control
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR; __IO uint32_t CR;
__IO uint32_t CFGR; __IO uint32_t CFGR;
__IO uint32_t CIR; __IO uint32_t CIR;
@@ -452,15 +427,13 @@ typedef struct
__IO uint32_t BDCR; __IO uint32_t BDCR;
__IO uint32_t CSR; __IO uint32_t CSR;
} RCC_TypeDef; } RCC_TypeDef;
/** /**
* @brief Real-Time Clock * @brief Real-Time Clock
*/ */
typedef struct typedef struct {
{
__IO uint32_t CRH; __IO uint32_t CRH;
__IO uint32_t CRL; __IO uint32_t CRL;
__IO uint32_t PRLH; __IO uint32_t PRLH;
@@ -477,8 +450,7 @@ typedef struct
* @brief SD host Interface * @brief SD host Interface
*/ */
typedef struct typedef struct {
{
__IO uint32_t POWER; __IO uint32_t POWER;
__IO uint32_t CLKCR; __IO uint32_t CLKCR;
__IO uint32_t ARG; __IO uint32_t ARG;
@@ -505,8 +477,7 @@ typedef struct
* @brief Serial Peripheral Interface * @brief Serial Peripheral Interface
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR1; __IO uint32_t CR1;
__IO uint32_t CR2; __IO uint32_t CR2;
__IO uint32_t SR; __IO uint32_t SR;
@@ -520,8 +491,7 @@ typedef struct
/** /**
* @brief TIM Timers * @brief TIM Timers
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
@@ -545,13 +515,11 @@ typedef struct
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef; } TIM_TypeDef;
/** /**
* @brief Universal Synchronous Asynchronous Receiver Transmitter * @brief Universal Synchronous Asynchronous Receiver Transmitter
*/ */
typedef struct typedef struct {
{
__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
@@ -565,8 +533,7 @@ typedef struct
* @brief Universal Serial Bus Full Speed Device * @brief Universal Serial Bus Full Speed Device
*/ */
typedef struct typedef struct {
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
@@ -595,13 +562,11 @@ typedef struct
__IO uint16_t RESERVEDC; /*!< Reserved */ __IO uint16_t RESERVEDC; /*!< Reserved */
} USB_TypeDef; } USB_TypeDef;
/** /**
* @brief Window WATCHDOG * @brief Window WATCHDOG
*/ */
typedef struct typedef struct {
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
@@ -615,7 +580,6 @@ typedef struct
* @{ * @{
*/ */
#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ #define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */ #define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ #define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
@@ -624,7 +588,6 @@ typedef struct
#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ #define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */ /*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE #define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
@@ -675,15 +638,12 @@ typedef struct
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ #define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */ #define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ #define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/* USB device FS */ /* USB device FS */
#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
/** /**
* @} * @}
*/ */
@@ -735,7 +695,6 @@ typedef struct
#define OB ((OB_TypeDef *)OB_BASE) #define OB ((OB_TypeDef *)OB_BASE)
#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/** /**
* @} * @}
*/ */
@@ -827,7 +786,6 @@ typedef struct
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
/******************* Bit definition for PWR_CSR register ********************/ /******************* Bit definition for PWR_CSR register ********************/
#define PWR_CSR_WUF_Pos (0U) #define PWR_CSR_WUF_Pos (0U)
#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
@@ -977,7 +935,6 @@ typedef struct
#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
/******************* Bit definition for RCC_CFGR register *******************/ /******************* Bit definition for RCC_CFGR register *******************/
/*!< SW configuration */ /*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U) #define RCC_CFGR_SW_Pos (0U)
@@ -1205,7 +1162,6 @@ typedef struct
#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
/***************** Bit definition for RCC_APB2RSTR register *****************/ /***************** Bit definition for RCC_APB2RSTR register *****************/
#define RCC_APB2RSTR_AFIORST_Pos (0U) #define RCC_APB2RSTR_AFIORST_Pos (0U)
#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
@@ -1240,14 +1196,10 @@ typedef struct
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_IOPERST_Pos (6U) #define RCC_APB2RSTR_IOPERST_Pos (6U)
#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
/***************** Bit definition for RCC_APB1RSTR register *****************/ /***************** Bit definition for RCC_APB1RSTR register *****************/
#define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Pos (0U)
#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
@@ -1293,11 +1245,6 @@ typedef struct
#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
/****************** Bit definition for RCC_AHBENR register ******************/ /****************** Bit definition for RCC_AHBENR register ******************/
#define RCC_AHBENR_DMA1EN_Pos (0U) #define RCC_AHBENR_DMA1EN_Pos (0U)
#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
@@ -1312,9 +1259,6 @@ typedef struct
#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
/****************** Bit definition for RCC_APB2ENR register *****************/ /****************** Bit definition for RCC_APB2ENR register *****************/
#define RCC_APB2ENR_AFIOEN_Pos (0U) #define RCC_APB2ENR_AFIOEN_Pos (0U)
#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
@@ -1349,14 +1293,10 @@ typedef struct
#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
#define RCC_APB2ENR_IOPEEN_Pos (6U) #define RCC_APB2ENR_IOPEEN_Pos (6U)
#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
/***************** Bit definition for RCC_APB1ENR register ******************/ /***************** Bit definition for RCC_APB1ENR register ******************/
#define RCC_APB1ENR_TIM2EN_Pos (0U) #define RCC_APB1ENR_TIM2EN_Pos (0U)
#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
@@ -1402,11 +1342,6 @@ typedef struct
#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
/******************* Bit definition for RCC_BDCR register *******************/ /******************* Bit definition for RCC_BDCR register *******************/
#define RCC_BDCR_LSEON_Pos (0U) #define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
@@ -1466,8 +1401,6 @@ typedef struct
#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* General Purpose and Alternate Function I/O */ /* General Purpose and Alternate Function I/O */
@@ -2190,7 +2123,6 @@ typedef struct
#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
/***************** Bit definition for AFIO_EXTICR1 register *****************/ /***************** Bit definition for AFIO_EXTICR1 register *****************/
#define AFIO_EXTICR1_EXTI0_Pos (0U) #define AFIO_EXTICR1_EXTI0_Pos (0U)
#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
@@ -2585,8 +2517,6 @@ typedef struct
/****************** Bit definition for AFIO_MAPR2 register ******************/ /****************** Bit definition for AFIO_MAPR2 register ******************/
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* External Interrupt/Event Controller */ /* External Interrupt/Event Controller */
@@ -3843,7 +3773,6 @@ typedef struct
#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
/*****************************************************************************/ /*****************************************************************************/
/* */ /* */
/* Timers (TIM) */ /* Timers (TIM) */
@@ -4560,7 +4489,6 @@ typedef struct
#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* SD host Interface */ /* SD host Interface */
@@ -9601,7 +9529,6 @@ typedef struct
#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* Inter-integrated Circuit Interface */ /* Inter-integrated Circuit Interface */
@@ -10271,8 +10198,6 @@ typedef struct
#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ #define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
/** /**
* @} * @}
*/ */
@@ -10286,8 +10211,7 @@ typedef struct
*/ */
/****************************** ADC Instances *********************************/ /****************************** ADC Instances *********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || ((INSTANCE) == ADC2))
((INSTANCE) == ADC2))
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
@@ -10304,20 +10228,12 @@ typedef struct
/****************************** DAC Instances *********************************/ /****************************** DAC Instances *********************************/
/****************************** DMA Instances *********************************/ /****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ #define IS_DMA_ALL_INSTANCE(INSTANCE) \
((INSTANCE) == DMA1_Channel2) || \ (((INSTANCE) == DMA1_Channel1) || ((INSTANCE) == DMA1_Channel2) || ((INSTANCE) == DMA1_Channel3) || ((INSTANCE) == DMA1_Channel4) || ((INSTANCE) == DMA1_Channel5) || ((INSTANCE) == DMA1_Channel6) \
((INSTANCE) == DMA1_Channel3) || \ || ((INSTANCE) == DMA1_Channel7))
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5) || \
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA1_Channel7))
/******************************* GPIO Instances *******************************/ /******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || ((INSTANCE) == GPIOB) || ((INSTANCE) == GPIOC) || ((INSTANCE) == GPIOD) || ((INSTANCE) == GPIOE))
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE))
/**************************** GPIO Alternate Function Instances ***************/ /**************************** GPIO Alternate Function Instances ***************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
@@ -10326,8 +10242,7 @@ typedef struct
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/ /******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2))
((INSTANCE) == I2C2))
/******************************* SMBUS Instances ******************************/ /******************************* SMBUS Instances ******************************/
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
@@ -10336,228 +10251,100 @@ typedef struct
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/******************************** SPI Instances *******************************/ /******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2))
((INSTANCE) == SPI2))
/****************************** START TIM Instances ***************************/ /****************************** START TIM Instances ***************************/
/****************************** TIM Instances *********************************/ /****************************** TIM Instances *********************************/
#define IS_TIM_INSTANCE(INSTANCE)\ #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
#define IS_TIM_CC1_INSTANCE(INSTANCE)\ #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CC2_INSTANCE(INSTANCE)\ #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CC3_INSTANCE(INSTANCE)\ #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CC4_INSTANCE(INSTANCE)\ #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_XOR_INSTANCE(INSTANCE)\ #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_MASTER_INSTANCE(INSTANCE)\ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_BREAK_INSTANCE(INSTANCE)\ #define IS_TIM_BREAK_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
((INSTANCE) == TIM1)
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \ ((((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
(((CHANNEL) == TIM_CHANNEL_1) || \ || (((INSTANCE) == TIM2) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
((CHANNEL) == TIM_CHANNEL_2) || \ || (((INSTANCE) == TIM3) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))) \
((CHANNEL) == TIM_CHANNEL_3) || \ || (((INSTANCE) == TIM4) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4))))
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (((INSTANCE) == TIM1) && (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3)))
(((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3)))
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
((INSTANCE) == TIM1)
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_DMA_INSTANCE(INSTANCE)\ #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
((INSTANCE) == TIM1)
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) || ((INSTANCE) == TIM4))
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/ /****************************** END TIM Instances *****************************/
/******************** USART Instances : Synchronous mode **********************/ /******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Asynchronous mode **********************/ /******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Half-Duplex mode **********************/ /******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : LIN mode **********************/ /******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************** UART Instances : Hardware Flow control ********************/ /****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/********************* UART Instances : Smard card mode ***********************/ /********************* UART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/*********************** UART Instances : IRDA mode ***************************/ /*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/***************** UART Instances : Multi-Processor mode **********************/ /***************** UART Instances : Multi-Processor mode **********************/
#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/***************** UART Instances : DMA mode available **********************/ /***************** UART Instances : DMA mode available **********************/
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || ((INSTANCE) == USART2) || ((INSTANCE) == USART3))
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************************** RTC Instances *********************************/ /****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -10568,8 +10355,6 @@ typedef struct
/****************************** USB Instances ********************************/ /****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
#define RCC_HSE_MIN 4000000U #define RCC_HSE_MIN 4000000U
#define RCC_HSE_MAX 16000000U #define RCC_HSE_MAX 16000000U
@@ -10604,7 +10389,6 @@ typedef struct
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
/* Aliases for __IRQHandler */ /* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler #define ADC1_IRQHandler ADC1_2_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM9_IRQHandler TIM1_BRK_IRQHandler
@@ -10623,7 +10407,6 @@ typedef struct
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
/** /**
* @} * @}
*/ */
@@ -10632,13 +10415,10 @@ typedef struct
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */
#endif /* __STM32F103xB_H */ #endif /* __STM32F103xB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

34
source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h vendored
View File

@@ -75,9 +75,8 @@
application application
*/ */
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ #if !defined(STM32F100xB) && !defined(STM32F100xE) && !defined(STM32F101x6) && !defined(STM32F101xB) && !defined(STM32F101xE) && !defined(STM32F101xG) && !defined(STM32F102x6) \
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ && !defined(STM32F102xB) && !defined(STM32F103x6) && !defined(STM32F103xB) && !defined(STM32F103xE) && !defined(STM32F103xG) && !defined(STM32F105xC) && !defined(STM32F107xC)
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
@@ -114,10 +113,7 @@
#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) | (__STM32F1_CMSIS_VERSION_SUB1 << 16) | (__STM32F1_CMSIS_VERSION_SUB2 << 8) | (__STM32F1_CMSIS_VERSION_RC))
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
/** /**
* @} * @}
@@ -166,30 +162,17 @@
/** @addtogroup Exported_types /** @addtogroup Exported_types
* @{ * @{
*/ */
typedef enum typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState;
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrorStatus;
{
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
/** /**
* @} * @}
*/ */
/** @addtogroup Exported_macros /** @addtogroup Exported_macros
* @{ * @{
*/ */
@@ -209,7 +192,6 @@ typedef enum
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/** /**
* @} * @}
*/ */
@@ -218,7 +200,6 @@ typedef enum
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */
@@ -232,7 +213,4 @@ typedef enum
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1
source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h vendored
View File

@@ -61,7 +61,6 @@
* @} * @}
*/ */
/** @addtogroup STM32F10x_System_Exported_types /** @addtogroup STM32F10x_System_Exported_types
* @{ * @{
*/ */

1
source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_common_tables.h vendored
View File

@@ -85,7 +85,6 @@ extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048]; extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096]; extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */ /* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20) #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48) #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48)

2
source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_const_structs.h vendored
View File

@@ -43,8 +43,8 @@
#ifndef _ARM_CONST_STRUCTS_H #ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H #define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h" #include "arm_common_tables.h"
#include "arm_math.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;

2747
source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_math.h vendored
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File diff suppressed because it is too large Load Diff

147
source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_armcc.h vendored
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@@ -31,11 +31,9 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H #ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!" #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif #endif
@@ -54,133 +52,111 @@
\details Returns the content of the Control Register. \details Returns the content of the Control Register.
\return Control Register value \return Control Register value
*/ */
__STATIC_INLINE uint32_t __get_CONTROL(void) __STATIC_INLINE uint32_t __get_CONTROL(void) {
{
register uint32_t __regControl __ASM("control"); register uint32_t __regControl __ASM("control");
return (__regControl); return (__regControl);
} }
/** /**
\brief Set Control Register \brief Set Control Register
\details Writes the given value to the Control Register. \details Writes the given value to the Control Register.
\param [in] control Control Register value to set \param [in] control Control Register value to set
*/ */
__STATIC_INLINE void __set_CONTROL(uint32_t control) __STATIC_INLINE void __set_CONTROL(uint32_t control) {
{
register uint32_t __regControl __ASM("control"); register uint32_t __regControl __ASM("control");
__regControl = control; __regControl = control;
} }
/** /**
\brief Get IPSR Register \brief Get IPSR Register
\details Returns the content of the IPSR Register. \details Returns the content of the IPSR Register.
\return IPSR Register value \return IPSR Register value
*/ */
__STATIC_INLINE uint32_t __get_IPSR(void) __STATIC_INLINE uint32_t __get_IPSR(void) {
{
register uint32_t __regIPSR __ASM("ipsr"); register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR); return (__regIPSR);
} }
/** /**
\brief Get APSR Register \brief Get APSR Register
\details Returns the content of the APSR Register. \details Returns the content of the APSR Register.
\return APSR Register value \return APSR Register value
*/ */
__STATIC_INLINE uint32_t __get_APSR(void) __STATIC_INLINE uint32_t __get_APSR(void) {
{
register uint32_t __regAPSR __ASM("apsr"); register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR); return (__regAPSR);
} }
/** /**
\brief Get xPSR Register \brief Get xPSR Register
\details Returns the content of the xPSR Register. \details Returns the content of the xPSR Register.
\return xPSR Register value \return xPSR Register value
*/ */
__STATIC_INLINE uint32_t __get_xPSR(void) __STATIC_INLINE uint32_t __get_xPSR(void) {
{
register uint32_t __regXPSR __ASM("xpsr"); register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR); return (__regXPSR);
} }
/** /**
\brief Get Process Stack Pointer \brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP). \details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value \return PSP Register value
*/ */
__STATIC_INLINE uint32_t __get_PSP(void) __STATIC_INLINE uint32_t __get_PSP(void) {
{
register uint32_t __regProcessStackPointer __ASM("psp"); register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer); return (__regProcessStackPointer);
} }
/** /**
\brief Set Process Stack Pointer \brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP). \details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set \param [in] topOfProcStack Process Stack Pointer value to set
*/ */
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) {
{
register uint32_t __regProcessStackPointer __ASM("psp"); register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack; __regProcessStackPointer = topOfProcStack;
} }
/** /**
\brief Get Main Stack Pointer \brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP). \details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value \return MSP Register value
*/ */
__STATIC_INLINE uint32_t __get_MSP(void) __STATIC_INLINE uint32_t __get_MSP(void) {
{
register uint32_t __regMainStackPointer __ASM("msp"); register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer); return (__regMainStackPointer);
} }
/** /**
\brief Set Main Stack Pointer \brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP). \details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set \param [in] topOfMainStack Main Stack Pointer value to set
*/ */
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) {
{
register uint32_t __regMainStackPointer __ASM("msp"); register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack; __regMainStackPointer = topOfMainStack;
} }
/** /**
\brief Get Priority Mask \brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register. \details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value \return Priority Mask value
*/ */
__STATIC_INLINE uint32_t __get_PRIMASK(void) __STATIC_INLINE uint32_t __get_PRIMASK(void) {
{
register uint32_t __regPriMask __ASM("primask"); register uint32_t __regPriMask __ASM("primask");
return (__regPriMask); return (__regPriMask);
} }
/** /**
\brief Set Priority Mask \brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register. \details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask \param [in] priMask Priority Mask
*/ */
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) {
{
register uint32_t __regPriMask __ASM("primask"); register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask); __regPriMask = (priMask);
} }
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/** /**
@@ -190,7 +166,6 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
*/ */
#define __enable_fault_irq __enable_fiq #define __enable_fault_irq __enable_fiq
/** /**
\brief Disable FIQ \brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR. \details Disables FIQ interrupts by setting the F-bit in the CPSR.
@@ -198,70 +173,59 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
*/ */
#define __disable_fault_irq __disable_fiq #define __disable_fault_irq __disable_fiq
/** /**
\brief Get Base Priority \brief Get Base Priority
\details Returns the current value of the Base Priority register. \details Returns the current value of the Base Priority register.
\return Base Priority register value \return Base Priority register value
*/ */
__STATIC_INLINE uint32_t __get_BASEPRI(void) __STATIC_INLINE uint32_t __get_BASEPRI(void) {
{
register uint32_t __regBasePri __ASM("basepri"); register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri); return (__regBasePri);
} }
/** /**
\brief Set Base Priority \brief Set Base Priority
\details Assigns the given value to the Base Priority register. \details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set \param [in] basePri Base Priority value to set
*/ */
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) {
{
register uint32_t __regBasePri __ASM("basepri"); register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU); __regBasePri = (basePri & 0xFFU);
} }
/** /**
\brief Set Base Priority with condition \brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level. or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set \param [in] basePri Base Priority value to set
*/ */
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) {
{
register uint32_t __regBasePriMax __ASM("basepri_max"); register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU); __regBasePriMax = (basePri & 0xFFU);
} }
/** /**
\brief Get Fault Mask \brief Get Fault Mask
\details Returns the current value of the Fault Mask register. \details Returns the current value of the Fault Mask register.
\return Fault Mask register value \return Fault Mask register value
*/ */
__STATIC_INLINE uint32_t __get_FAULTMASK(void) __STATIC_INLINE uint32_t __get_FAULTMASK(void) {
{
register uint32_t __regFaultMask __ASM("faultmask"); register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask); return (__regFaultMask);
} }
/** /**
\brief Set Fault Mask \brief Set Fault Mask
\details Assigns the given value to the Fault Mask register. \details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set \param [in] faultMask Fault Mask value to set
*/ */
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) {
{
register uint32_t __regFaultMask __ASM("faultmask"); register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1); __regFaultMask = (faultMask & (uint32_t)1);
} }
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/** /**
@@ -269,8 +233,7 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
\details Returns the current value of the Floating Point Status/Control register. \details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value \return Floating Point Status/Control register value
*/ */
__STATIC_INLINE uint32_t __get_FPSCR(void) __STATIC_INLINE uint32_t __get_FPSCR(void) {
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr"); register uint32_t __regfpscr __ASM("fpscr");
return (__regfpscr); return (__regfpscr);
@@ -279,14 +242,12 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
#endif #endif
} }
/** /**
\brief Set FPSCR \brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register. \details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set \param [in] fpscr Floating Point Status/Control value to set
*/ */
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) {
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr"); register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr); __regfpscr = (fpscr);
@@ -295,11 +256,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */ /*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */ /* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions Access to dedicated instructions
@@ -312,14 +270,12 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/ */
#define __NOP __nop #define __NOP __nop
/** /**
\brief Wait For Interrupt \brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/ */
#define __WFI __wfi #define __WFI __wfi
/** /**
\brief Wait For Event \brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter \details Wait For Event is a hint instruction that permits the processor to enter
@@ -327,21 +283,20 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/ */
#define __WFE __wfe #define __WFE __wfe
/** /**
\brief Send Event \brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU. \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/ */
#define __SEV __sev #define __SEV __sev
/** /**
\brief Instruction Synchronization Barrier \brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor, \details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory, so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed. after the instruction has been completed.
*/ */
#define __ISB() do {\ #define __ISB() \
do { \
__schedule_barrier(); \ __schedule_barrier(); \
__isb(0xF); \ __isb(0xF); \
__schedule_barrier(); \ __schedule_barrier(); \
@@ -352,7 +307,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\details Acts as a special kind of Data Memory Barrier. \details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete. It completes when all explicit memory accesses before this instruction complete.
*/ */
#define __DSB() do {\ #define __DSB() \
do { \
__schedule_barrier(); \ __schedule_barrier(); \
__dsb(0xF); \ __dsb(0xF); \
__schedule_barrier(); \ __schedule_barrier(); \
@@ -363,7 +319,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\details Ensures the apparent order of the explicit memory operations before \details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion. and after the instruction, without ensuring their completion.
*/ */
#define __DMB() do {\ #define __DMB() \
do { \
__schedule_barrier(); \ __schedule_barrier(); \
__dmb(0xF); \ __dmb(0xF); \
__schedule_barrier(); \ __schedule_barrier(); \
@@ -377,7 +334,6 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/ */
#define __REV __rev #define __REV __rev
/** /**
\brief Reverse byte order (16 bit) \brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values. \details Reverses the byte order in two unsigned short values.
@@ -385,11 +341,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
\return Reversed value \return Reversed value
*/ */
#ifndef __NO_EMBEDDED_ASM #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr }
{
rev16 r0, r0
bx lr
}
#endif #endif
/** /**
@@ -399,14 +351,9 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
\return Reversed value \return Reversed value
*/ */
#ifndef __NO_EMBEDDED_ASM #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr }
{
revsh r0, r0
bx lr
}
#endif #endif
/** /**
\brief Rotate Right in unsigned value (32 bit) \brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@@ -416,7 +363,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
*/ */
#define __ROR __ror #define __ROR __ror
/** /**
\brief Breakpoint \brief Breakpoint
\details Causes the processor to enter Debug state. \details Causes the processor to enter Debug state.
@@ -426,7 +372,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
*/ */
#define __BKPT(value) __breakpoint(value) #define __BKPT(value) __breakpoint(value)
/** /**
\brief Reverse bit order of value \brief Reverse bit order of value
\details Reverses the bit order of the given value. \details Reverses the bit order of the given value.
@@ -436,14 +381,12 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit #define __RBIT __rbit
#else #else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
{
uint32_t result; uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */ result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) for (value >>= 1U; value; value >>= 1U) {
{
result <<= 1U; result <<= 1U;
result |= value & 1U; result |= value & 1U;
s--; s--;
@@ -453,7 +396,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
} }
#endif #endif
/** /**
\brief Count leading zeros \brief Count leading zeros
\details Counts the number of leading zeros of a data value. \details Counts the number of leading zeros of a data value.
@@ -462,7 +404,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
*/ */
#define __CLZ __clz #define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/** /**
@@ -477,7 +418,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop") #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop")
#endif #endif
/** /**
\brief LDR Exclusive (16 bit) \brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values. \details Executes a exclusive LDR instruction for 16 bit values.
@@ -490,7 +430,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop") #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop")
#endif #endif
/** /**
\brief LDR Exclusive (32 bit) \brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values. \details Executes a exclusive LDR instruction for 32 bit values.
@@ -503,7 +442,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop") #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop")
#endif #endif
/** /**
\brief STR Exclusive (8 bit) \brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values. \details Executes a exclusive STR instruction for 8 bit values.
@@ -518,7 +456,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif #endif
/** /**
\brief STR Exclusive (16 bit) \brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values. \details Executes a exclusive STR instruction for 16 bit values.
@@ -533,7 +470,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif #endif
/** /**
\brief STR Exclusive (32 bit) \brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values. \details Executes a exclusive STR instruction for 32 bit values.
@@ -548,14 +484,12 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif #endif
/** /**
\brief Remove the exclusive lock \brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX. \details Removes the exclusive lock which is created by LDREX.
*/ */
#define __CLREX __clrex #define __CLREX __clrex
/** /**
\brief Signed Saturate \brief Signed Saturate
\details Saturates a signed value. \details Saturates a signed value.
@@ -565,7 +499,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
*/ */
#define __SSAT __ssat #define __SSAT __ssat
/** /**
\brief Unsigned Saturate \brief Unsigned Saturate
\details Saturates an unsigned value. \details Saturates an unsigned value.
@@ -575,7 +508,6 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
*/ */
#define __USAT __usat #define __USAT __usat
/** /**
\brief Rotate Right with Extend (32 bit) \brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit. \details Moves each bit of a bitstring right by one bit.
@@ -584,14 +516,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return Rotated value \return Rotated value
*/ */
#ifndef __NO_EMBEDDED_ASM #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr }
{
rrx r0, r0
bx lr
}
#endif #endif
/** /**
\brief LDRT Unprivileged (8 bit) \brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value. \details Executes a Unprivileged LDRT instruction for 8 bit value.
@@ -600,7 +527,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/ */
#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr)) #define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
/** /**
\brief LDRT Unprivileged (16 bit) \brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values. \details Executes a Unprivileged LDRT instruction for 16 bit values.
@@ -609,7 +535,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/ */
#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr)) #define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
/** /**
\brief LDRT Unprivileged (32 bit) \brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values. \details Executes a Unprivileged LDRT instruction for 32 bit values.
@@ -618,7 +543,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/ */
#define __LDRT(ptr) ((uint32_t)__ldrt(ptr)) #define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
/** /**
\brief STRT Unprivileged (8 bit) \brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values. \details Executes a Unprivileged STRT instruction for 8 bit values.
@@ -627,7 +551,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/ */
#define __STRBT(value, ptr) __strt(value, ptr) #define __STRBT(value, ptr) __strt(value, ptr)
/** /**
\brief STRT Unprivileged (16 bit) \brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values. \details Executes a Unprivileged STRT instruction for 16 bit values.
@@ -636,7 +559,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/ */
#define __STRHT(value, ptr) __strt(value, ptr) #define __STRHT(value, ptr) __strt(value, ptr)
/** /**
\brief STRT Unprivileged (32 bit) \brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values. \details Executes a Unprivileged STRT instruction for 32 bit values.
@@ -649,7 +571,6 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */ /* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions Access to dedicated SIMD instructions
@@ -718,17 +639,13 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
#define __QADD __qadd #define __QADD __qadd
#define __QSUB __qsub #define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ #define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ #define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ #define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U)) >> 32U))
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */ #endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */ /*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */ #endif /* __CMSIS_ARMCC_H */

515
source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_armcc_V6.h vendored
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426
source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_gcc.h vendored
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137
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0.h vendored
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@@ -31,7 +31,6 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,12 +71,10 @@
/* CMSIS CM0 definitions */ /* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ #define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined(__CC_ARM) #if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
@@ -160,8 +156,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -219,8 +215,6 @@
/*@} end of group Cortex_M0 */ /*@} end of group Cortex_M0 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -244,10 +238,8 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */ uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
@@ -270,14 +262,11 @@ typedef union
#define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
@@ -288,14 +277,11 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
@@ -327,14 +313,11 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */ uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
@@ -348,7 +331,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -359,8 +341,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U]; uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -375,7 +356,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -386,8 +366,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0; uint32_t RESERVED0;
@@ -482,7 +461,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -493,8 +471,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -534,7 +511,6 @@ typedef struct
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -544,7 +520,6 @@ typedef struct
*/ */
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -570,7 +545,6 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -588,11 +562,8 @@ typedef struct
#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -604,8 +575,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -620,28 +589,19 @@ typedef struct
#define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL)) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL)) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -650,33 +610,21 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -685,21 +633,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0) SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
{ } else {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -709,30 +650,23 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} } else {
else
{
return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */ for (;;) /* wait until reset */
@@ -743,8 +677,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -766,19 +698,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -786,9 +714,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

139
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0plus.h vendored
View File

@@ -31,7 +31,6 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,12 +71,10 @@
/* CMSIS CM0+ definitions */ /* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ #define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined(__CC_ARM) #if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
@@ -160,8 +156,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -229,8 +225,6 @@
/*@} end of group Cortex-M0+ */ /*@} end of group Cortex-M0+ */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -255,10 +249,8 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */ uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
@@ -281,14 +273,11 @@ typedef union
#define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
@@ -299,14 +288,11 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
@@ -338,14 +324,11 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
@@ -362,7 +345,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -373,8 +355,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U]; uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -389,7 +370,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -400,8 +380,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1U) #if (__VTOR_PRESENT == 1U)
@@ -506,7 +485,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -517,8 +495,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -569,8 +546,7 @@ typedef struct
/** /**
\brief Structure type to access the Memory Protection Unit (MPU). \brief Structure type to access the Memory Protection Unit (MPU).
*/ */
typedef struct typedef struct {
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -646,7 +622,6 @@ typedef struct
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -656,7 +631,6 @@ typedef struct
*/ */
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -682,7 +656,6 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -707,8 +680,6 @@ typedef struct
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -720,8 +691,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -736,28 +705,19 @@ typedef struct
#define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL)) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL)) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -766,33 +726,21 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -801,21 +749,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0) SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
{ } else {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -825,30 +766,23 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} } else {
else
{
return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */ for (;;) /* wait until reset */
@@ -859,8 +793,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -882,19 +814,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -902,9 +830,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

214
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm3.h vendored
View File

@@ -31,7 +31,6 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,12 +71,10 @@
/* CMSIS CM3 definitions */ /* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ #define __CORTEX_M (0x03U) /*!< Cortex-M Core */
#if defined(__CC_ARM) #if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
@@ -160,8 +156,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -224,8 +220,6 @@
/*@} end of group Cortex_M3 */ /*@} end of group Cortex_M3 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -251,10 +245,8 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */
uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
@@ -281,14 +273,11 @@ typedef union
#define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
@@ -299,14 +288,11 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
@@ -345,14 +331,11 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
@@ -369,7 +352,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -380,8 +362,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U]; uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -403,7 +384,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -414,8 +394,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -630,7 +609,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -641,8 +619,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control and ID Register not in the SCB. \brief Structure type to access the System Control and ID Register not in the SCB.
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0[1U]; uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) #if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
@@ -669,7 +646,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */ /*@} end of group CMSIS_SCnotSCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -680,8 +656,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -721,7 +696,6 @@ typedef struct
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
@@ -732,10 +706,8 @@ typedef struct
/** /**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/ */
typedef struct typedef struct {
{ __OM union {
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
@@ -824,7 +796,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_ITM */ /*@}*/ /* end of group CMSIS_ITM */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
@@ -835,8 +806,7 @@ typedef struct
/** /**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT). \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
@@ -971,7 +941,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */ /*@}*/ /* end of group CMSIS_DWT */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI) \defgroup CMSIS_TPI Trace Port Interface (TPI)
@@ -982,8 +951,7 @@ typedef struct
/** /**
\brief Structure type to access the Trace Port Interface Register (TPI). \brief Structure type to access the Trace Port Interface Register (TPI).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
@@ -1126,7 +1094,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_TPI */ /*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
@@ -1138,8 +1105,7 @@ typedef struct
/** /**
\brief Structure type to access the Memory Protection Unit (MPU). \brief Structure type to access the Memory Protection Unit (MPU).
*/ */
typedef struct typedef struct {
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -1221,7 +1187,6 @@ typedef struct
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -1232,8 +1197,7 @@ typedef struct
/** /**
\brief Structure type to access the Core Debug Register (CoreDebug). \brief Structure type to access the Core Debug Register (CoreDebug).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
@@ -1326,7 +1290,6 @@ typedef struct
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -1352,7 +1315,6 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -1386,8 +1348,6 @@ typedef struct
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -1400,8 +1360,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1419,52 +1377,36 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field. \param [in] PriorityGroup Priority grouping field.
*/ */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
{
uint32_t reg_value; uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */ reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value | reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value; SCB->AIRCR = reg_value;
} }
/** /**
\brief Get Priority Grouping \brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller. \details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -1473,33 +1415,23 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
{
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Active Interrupt \brief Get Active Interrupt
@@ -1508,11 +1440,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not active. \return 0 Interrupt status is not active.
\return 1 Interrupt status is active. \return 1 Interrupt status is active.
*/ */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -1521,19 +1449,14 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} } else {
else
{
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -1543,20 +1466,15 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{
return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
} } else {
else
{
return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief Encode Priority \brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group, \details Encodes the priority for an interrupt with the given priority group,
@@ -1568,8 +1486,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\param [in] SubPriority Subpriority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/ */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1577,13 +1494,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return ( return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
} }
/** /**
\brief Decode Priority \brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to \details Decodes an interrupt priority value with a given priority group to
@@ -1595,8 +1508,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
\param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0).
*/ */
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1608,18 +1520,14 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */ for (;;) /* wait until reset */
@@ -1630,8 +1538,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1653,19 +1559,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -1673,8 +1575,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */ /* ##################################### Debug In/Output function ########################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1686,7 +1586,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** /**
\brief ITM Send Character \brief ITM Send Character
\details Transmits a character via the ITM channel 0, and \details Transmits a character via the ITM channel 0, and
@@ -1695,13 +1594,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
\param [in] ch Character to transmit. \param [in] ch Character to transmit.
\returns Character to transmit. \returns Character to transmit.
*/ */
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
{ {
while (ITM->PORT[0U].u32 == 0UL) while (ITM->PORT[0U].u32 == 0UL) {
{
__NOP(); __NOP();
} }
ITM->PORT[0U].u8 = (uint8_t)ch; ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -1709,19 +1606,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
return (ch); return (ch);
} }
/** /**
\brief ITM Receive Character \brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer. \details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character. \return Received character.
\return -1 No character pending. \return -1 No character pending.
*/ */
__STATIC_INLINE int32_t ITM_ReceiveChar (void) __STATIC_INLINE int32_t ITM_ReceiveChar(void) {
{
int32_t ch = -1; /* no character available */ int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
{
ch = ITM_RxBuffer; ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
} }
@@ -1729,31 +1623,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
return (ch); return (ch);
} }
/** /**
\brief ITM Check Character \brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available. \return 0 No character available.
\return 1 Character available. \return 1 Character available.
*/ */
__STATIC_INLINE int32_t ITM_CheckChar (void) __STATIC_INLINE int32_t ITM_CheckChar(void) {
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
{
return (0); /* no character available */ return (0); /* no character available */
} } else {
else
{
return (1); /* character available */ return (1); /* character available */
} }
} }
/*@} end of CMSIS_core_DebugFunctions */ /*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

218
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm4.h vendored
View File

@@ -31,7 +31,6 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,12 +71,10 @@
/* CMSIS CM4 definitions */ /* CMSIS CM4 definitions */
#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ #define __CORTEX_M (0x04U) /*!< Cortex-M Core */
#if defined(__CC_ARM) #if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
@@ -207,8 +203,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
#ifdef __cplusplus #ifdef __cplusplus
@@ -277,8 +273,6 @@
/*@} end of group Cortex_M4 */ /*@} end of group Cortex_M4 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -305,10 +299,8 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */
uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */
@@ -340,14 +332,11 @@ typedef union
#define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
@@ -358,14 +347,11 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */
uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */
@@ -409,14 +395,11 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */
@@ -437,7 +420,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -448,8 +430,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U]; uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -471,7 +452,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -482,8 +462,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -690,7 +669,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -701,8 +679,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control and ID Register not in the SCB. \brief Structure type to access the System Control and ID Register not in the SCB.
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0[1U]; uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
@@ -730,7 +707,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */ /*@} end of group CMSIS_SCnotSCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -741,8 +717,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -782,7 +757,6 @@ typedef struct
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
@@ -793,10 +767,8 @@ typedef struct
/** /**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/ */
typedef struct typedef struct {
{ __OM union {
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
@@ -885,7 +857,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_ITM */ /*@}*/ /* end of group CMSIS_ITM */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
@@ -896,8 +867,7 @@ typedef struct
/** /**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT). \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
@@ -1032,7 +1002,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */ /*@}*/ /* end of group CMSIS_DWT */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI) \defgroup CMSIS_TPI Trace Port Interface (TPI)
@@ -1043,8 +1012,7 @@ typedef struct
/** /**
\brief Structure type to access the Trace Port Interface Register (TPI). \brief Structure type to access the Trace Port Interface Register (TPI).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
@@ -1187,7 +1155,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_TPI */ /*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
@@ -1199,8 +1166,7 @@ typedef struct
/** /**
\brief Structure type to access the Memory Protection Unit (MPU). \brief Structure type to access the Memory Protection Unit (MPU).
*/ */
typedef struct typedef struct {
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -1282,7 +1248,6 @@ typedef struct
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif
#if (__FPU_PRESENT == 1U) #if (__FPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
@@ -1294,8 +1259,7 @@ typedef struct
/** /**
\brief Structure type to access the Floating Point Unit (FPU). \brief Structure type to access the Floating Point Unit (FPU).
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0[1U]; uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
@@ -1390,7 +1354,6 @@ typedef struct
/*@} end of group CMSIS_FPU */ /*@} end of group CMSIS_FPU */
#endif #endif
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -1401,8 +1364,7 @@ typedef struct
/** /**
\brief Structure type to access the Core Debug Register (CoreDebug). \brief Structure type to access the Core Debug Register (CoreDebug).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
@@ -1495,7 +1457,6 @@ typedef struct
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -1521,7 +1482,6 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -1560,8 +1520,6 @@ typedef struct
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -1574,8 +1532,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1593,52 +1549,36 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field. \param [in] PriorityGroup Priority grouping field.
*/ */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
{
uint32_t reg_value; uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */ reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value | reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value; SCB->AIRCR = reg_value;
} }
/** /**
\brief Get Priority Grouping \brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller. \details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -1647,33 +1587,23 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
{
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Active Interrupt \brief Get Active Interrupt
@@ -1682,11 +1612,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not active. \return 0 Interrupt status is not active.
\return 1 Interrupt status is active. \return 1 Interrupt status is active.
*/ */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -1695,19 +1621,14 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} } else {
else
{
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -1717,20 +1638,15 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{
return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
} } else {
else
{
return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief Encode Priority \brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group, \details Encodes the priority for an interrupt with the given priority group,
@@ -1742,8 +1658,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\param [in] SubPriority Subpriority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/ */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1751,13 +1666,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return ( return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
} }
/** /**
\brief Decode Priority \brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to \details Decodes an interrupt priority value with a given priority group to
@@ -1769,8 +1680,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
\param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0).
*/ */
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1782,18 +1692,14 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */ for (;;) /* wait until reset */
@@ -1804,8 +1710,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1827,19 +1731,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -1847,8 +1747,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */ /* ##################################### Debug In/Output function ########################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1860,7 +1758,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** /**
\brief ITM Send Character \brief ITM Send Character
\details Transmits a character via the ITM channel 0, and \details Transmits a character via the ITM channel 0, and
@@ -1869,13 +1766,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
\param [in] ch Character to transmit. \param [in] ch Character to transmit.
\returns Character to transmit. \returns Character to transmit.
*/ */
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
{ {
while (ITM->PORT[0U].u32 == 0UL) while (ITM->PORT[0U].u32 == 0UL) {
{
__NOP(); __NOP();
} }
ITM->PORT[0U].u8 = (uint8_t)ch; ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -1883,19 +1778,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
return (ch); return (ch);
} }
/** /**
\brief ITM Receive Character \brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer. \details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character. \return Received character.
\return -1 No character pending. \return -1 No character pending.
*/ */
__STATIC_INLINE int32_t ITM_ReceiveChar (void) __STATIC_INLINE int32_t ITM_ReceiveChar(void) {
{
int32_t ch = -1; /* no character available */ int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
{
ch = ITM_RxBuffer; ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
} }
@@ -1903,31 +1795,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
return (ch); return (ch);
} }
/** /**
\brief ITM Check Character \brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available. \return 0 No character available.
\return 1 Character available. \return 1 Character available.
*/ */
__STATIC_INLINE int32_t ITM_CheckChar (void) __STATIC_INLINE int32_t ITM_CheckChar(void) {
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
{
return (0); /* no character available */ return (0); /* no character available */
} } else {
else
{
return (1); /* character available */ return (1); /* character available */
} }
} }
/*@} end of CMSIS_core_DebugFunctions */ /*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

296
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm7.h vendored
View File

@@ -31,7 +31,6 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,12 +71,10 @@
/* CMSIS CM7 definitions */ /* CMSIS CM7 definitions */
#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | __CM7_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ #define __CORTEX_M (0x07U) /*!< Cortex-M Core */
#if defined(__CC_ARM) #if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
@@ -207,8 +203,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
#ifdef __cplusplus #ifdef __cplusplus
@@ -292,8 +288,6 @@
/*@} end of group Cortex_M7 */ /*@} end of group Cortex_M7 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -320,10 +314,8 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */
uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */
@@ -355,14 +347,11 @@ typedef union
#define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
@@ -373,14 +362,11 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */
uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */
@@ -424,14 +410,11 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */
@@ -452,7 +435,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -463,8 +445,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U]; uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -486,7 +467,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -497,8 +477,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -892,7 +871,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -903,8 +881,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control and ID Register not in the SCB. \brief Structure type to access the System Control and ID Register not in the SCB.
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0[1U]; uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
@@ -932,7 +909,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */ /*@} end of group CMSIS_SCnotSCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -943,8 +919,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -984,7 +959,6 @@ typedef struct
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
@@ -995,10 +969,8 @@ typedef struct
/** /**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/ */
typedef struct typedef struct {
{ __OM union {
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
@@ -1087,7 +1059,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_ITM */ /*@}*/ /* end of group CMSIS_ITM */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
@@ -1098,8 +1069,7 @@ typedef struct
/** /**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT). \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
@@ -1237,7 +1207,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */ /*@}*/ /* end of group CMSIS_DWT */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI) \defgroup CMSIS_TPI Trace Port Interface (TPI)
@@ -1248,8 +1217,7 @@ typedef struct
/** /**
\brief Structure type to access the Trace Port Interface Register (TPI). \brief Structure type to access the Trace Port Interface Register (TPI).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
@@ -1392,7 +1360,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_TPI */ /*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
@@ -1404,8 +1371,7 @@ typedef struct
/** /**
\brief Structure type to access the Memory Protection Unit (MPU). \brief Structure type to access the Memory Protection Unit (MPU).
*/ */
typedef struct typedef struct {
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -1487,7 +1453,6 @@ typedef struct
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif
#if (__FPU_PRESENT == 1U) #if (__FPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
@@ -1499,8 +1464,7 @@ typedef struct
/** /**
\brief Structure type to access the Floating Point Unit (FPU). \brief Structure type to access the Floating Point Unit (FPU).
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0[1U]; uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
@@ -1598,7 +1562,6 @@ typedef struct
/*@} end of group CMSIS_FPU */ /*@} end of group CMSIS_FPU */
#endif #endif
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -1609,8 +1572,7 @@ typedef struct
/** /**
\brief Structure type to access the Core Debug Register (CoreDebug). \brief Structure type to access the Core Debug Register (CoreDebug).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
@@ -1703,7 +1665,6 @@ typedef struct
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -1729,7 +1690,6 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -1768,8 +1728,6 @@ typedef struct
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -1782,8 +1740,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1801,52 +1757,36 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field. \param [in] PriorityGroup Priority grouping field.
*/ */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
{
uint32_t reg_value; uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */ reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value | reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value; SCB->AIRCR = reg_value;
} }
/** /**
\brief Get Priority Grouping \brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller. \details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -1855,33 +1795,23 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
{
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Active Interrupt \brief Get Active Interrupt
@@ -1890,11 +1820,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not active. \return 0 Interrupt status is not active.
\return 1 Interrupt status is active. \return 1 Interrupt status is active.
*/ */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -1903,19 +1829,14 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0)
{
SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} } else {
else
{
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -1925,20 +1846,15 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{
return (((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); return (((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
} } else {
else
{
return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief Encode Priority \brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group, \details Encodes the priority for an interrupt with the given priority group,
@@ -1950,8 +1866,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\param [in] SubPriority Subpriority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/ */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1959,13 +1874,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return ( return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
} }
/** /**
\brief Decode Priority \brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to \details Decodes an interrupt priority value with a given priority group to
@@ -1977,8 +1888,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
\param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0).
*/ */
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1990,18 +1900,14 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */ for (;;) /* wait until reset */
@@ -2012,7 +1918,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */ /* ########################## FPU functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -2029,30 +1934,21 @@ __STATIC_INLINE void NVIC_SystemReset(void)
- \b 1: Single precision FPU - \b 1: Single precision FPU
- \b 2: Double + Single precision FPU - \b 2: Double + Single precision FPU
*/ */
__STATIC_INLINE uint32_t SCB_GetFPUType(void) __STATIC_INLINE uint32_t SCB_GetFPUType(void) {
{
uint32_t mvfr0; uint32_t mvfr0;
mvfr0 = SCB->MVFR0; mvfr0 = SCB->MVFR0;
if ((mvfr0 & 0x00000FF0UL) == 0x220UL) if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
{
return 2UL; /* Double + Single precision FPU */ return 2UL; /* Double + Single precision FPU */
} } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
{
return 1UL; /* Single precision FPU */ return 1UL; /* Single precision FPU */
} } else {
else
{
return 0UL; /* No FPU */ return 0UL; /* No FPU */
} }
} }
/*@} end of CMSIS_Core_FpuFunctions */ /*@} end of CMSIS_Core_FpuFunctions */
/* ########################## Cache functions #################################### */ /* ########################## Cache functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -2065,13 +1961,11 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
#define CCSIDR_WAYS(x) (((x)&SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_WAYS(x) (((x)&SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x)&SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos) #define CCSIDR_SETS(x) (((x)&SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos)
/** /**
\brief Enable I-Cache \brief Enable I-Cache
\details Turns on I-Cache \details Turns on I-Cache
*/ */
__STATIC_INLINE void SCB_EnableICache (void) __STATIC_INLINE void SCB_EnableICache(void) {
{
#if (__ICACHE_PRESENT == 1U) #if (__ICACHE_PRESENT == 1U)
__DSB(); __DSB();
__ISB(); __ISB();
@@ -2082,13 +1976,11 @@ __STATIC_INLINE void SCB_EnableICache (void)
#endif #endif
} }
/** /**
\brief Disable I-Cache \brief Disable I-Cache
\details Turns off I-Cache \details Turns off I-Cache
*/ */
__STATIC_INLINE void SCB_DisableICache (void) __STATIC_INLINE void SCB_DisableICache(void) {
{
#if (__ICACHE_PRESENT == 1U) #if (__ICACHE_PRESENT == 1U)
__DSB(); __DSB();
__ISB(); __ISB();
@@ -2099,13 +1991,11 @@ __STATIC_INLINE void SCB_DisableICache (void)
#endif #endif
} }
/** /**
\brief Invalidate I-Cache \brief Invalidate I-Cache
\details Invalidates I-Cache \details Invalidates I-Cache
*/ */
__STATIC_INLINE void SCB_InvalidateICache (void) __STATIC_INLINE void SCB_InvalidateICache(void) {
{
#if (__ICACHE_PRESENT == 1U) #if (__ICACHE_PRESENT == 1U)
__DSB(); __DSB();
__ISB(); __ISB();
@@ -2115,13 +2005,11 @@ __STATIC_INLINE void SCB_InvalidateICache (void)
#endif #endif
} }
/** /**
\brief Enable D-Cache \brief Enable D-Cache
\details Turns on D-Cache \details Turns on D-Cache
*/ */
__STATIC_INLINE void SCB_EnableDCache (void) __STATIC_INLINE void SCB_EnableDCache(void) {
{
#if (__DCACHE_PRESENT == 1U) #if (__DCACHE_PRESENT == 1U)
uint32_t ccsidr; uint32_t ccsidr;
uint32_t sets; uint32_t sets;
@@ -2137,8 +2025,7 @@ __STATIC_INLINE void SCB_EnableDCache (void)
do { do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do { do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk));
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined(__CC_ARM) #if defined(__CC_ARM)
__schedule_barrier(); __schedule_barrier();
#endif #endif
@@ -2153,13 +2040,11 @@ __STATIC_INLINE void SCB_EnableDCache (void)
#endif #endif
} }
/** /**
\brief Disable D-Cache \brief Disable D-Cache
\details Turns off D-Cache \details Turns off D-Cache
*/ */
__STATIC_INLINE void SCB_DisableDCache (void) __STATIC_INLINE void SCB_DisableDCache(void) {
{
#if (__DCACHE_PRESENT == 1U) #if (__DCACHE_PRESENT == 1U)
uint32_t ccsidr; uint32_t ccsidr;
uint32_t sets; uint32_t sets;
@@ -2177,8 +2062,7 @@ __STATIC_INLINE void SCB_DisableDCache (void)
do { do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do { do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk));
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined(__CC_ARM) #if defined(__CC_ARM)
__schedule_barrier(); __schedule_barrier();
#endif #endif
@@ -2190,13 +2074,11 @@ __STATIC_INLINE void SCB_DisableDCache (void)
#endif #endif
} }
/** /**
\brief Invalidate D-Cache \brief Invalidate D-Cache
\details Invalidates D-Cache \details Invalidates D-Cache
*/ */
__STATIC_INLINE void SCB_InvalidateDCache (void) __STATIC_INLINE void SCB_InvalidateDCache(void) {
{
#if (__DCACHE_PRESENT == 1U) #if (__DCACHE_PRESENT == 1U)
uint32_t ccsidr; uint32_t ccsidr;
uint32_t sets; uint32_t sets;
@@ -2212,8 +2094,7 @@ __STATIC_INLINE void SCB_InvalidateDCache (void)
do { do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do { do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk));
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined(__CC_ARM) #if defined(__CC_ARM)
__schedule_barrier(); __schedule_barrier();
#endif #endif
@@ -2225,13 +2106,11 @@ __STATIC_INLINE void SCB_InvalidateDCache (void)
#endif #endif
} }
/** /**
\brief Clean D-Cache \brief Clean D-Cache
\details Cleans D-Cache \details Cleans D-Cache
*/ */
__STATIC_INLINE void SCB_CleanDCache (void) __STATIC_INLINE void SCB_CleanDCache(void) {
{
#if (__DCACHE_PRESENT == 1U) #if (__DCACHE_PRESENT == 1U)
uint32_t ccsidr; uint32_t ccsidr;
uint32_t sets; uint32_t sets;
@@ -2247,8 +2126,7 @@ __STATIC_INLINE void SCB_CleanDCache (void)
do { do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do { do {
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk));
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
#if defined(__CC_ARM) #if defined(__CC_ARM)
__schedule_barrier(); __schedule_barrier();
#endif #endif
@@ -2260,13 +2138,11 @@ __STATIC_INLINE void SCB_CleanDCache (void)
#endif #endif
} }
/** /**
\brief Clean & Invalidate D-Cache \brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache \details Cleans and Invalidates D-Cache
*/ */
__STATIC_INLINE void SCB_CleanInvalidateDCache (void) __STATIC_INLINE void SCB_CleanInvalidateDCache(void) {
{
#if (__DCACHE_PRESENT == 1U) #if (__DCACHE_PRESENT == 1U)
uint32_t ccsidr; uint32_t ccsidr;
uint32_t sets; uint32_t sets;
@@ -2282,8 +2158,7 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
do { do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do { do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk));
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined(__CC_ARM) #if defined(__CC_ARM)
__schedule_barrier(); __schedule_barrier();
#endif #endif
@@ -2295,15 +2170,13 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
#endif #endif
} }
/** /**
\brief D-Cache Invalidate by address \brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address \details Invalidates D-Cache for the given address
\param[in] addr address (aligned to 32-byte boundary) \param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes) \param[in] dsize size of memory block (in number of bytes)
*/ */
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) __STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize) {
{
#if (__DCACHE_PRESENT == 1U) #if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize; int32_t op_size = dsize;
uint32_t op_addr = (uint32_t)addr; uint32_t op_addr = (uint32_t)addr;
@@ -2322,15 +2195,13 @@ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize
#endif #endif
} }
/** /**
\brief D-Cache Clean by address \brief D-Cache Clean by address
\details Cleans D-Cache for the given address \details Cleans D-Cache for the given address
\param[in] addr address (aligned to 32-byte boundary) \param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes) \param[in] dsize size of memory block (in number of bytes)
*/ */
__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) __STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize) {
{
#if (__DCACHE_PRESENT == 1) #if (__DCACHE_PRESENT == 1)
int32_t op_size = dsize; int32_t op_size = dsize;
uint32_t op_addr = (uint32_t)addr; uint32_t op_addr = (uint32_t)addr;
@@ -2349,15 +2220,13 @@ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
#endif #endif
} }
/** /**
\brief D-Cache Clean and Invalidate by address \brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address \details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 32-byte boundary) \param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes) \param[in] dsize size of memory block (in number of bytes)
*/ */
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize) {
{
#if (__DCACHE_PRESENT == 1U) #if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize; int32_t op_size = dsize;
uint32_t op_addr = (uint32_t)addr; uint32_t op_addr = (uint32_t)addr;
@@ -2376,11 +2245,8 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t
#endif #endif
} }
/*@} end of CMSIS_Core_CacheFunctions */ /*@} end of CMSIS_Core_CacheFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -2402,19 +2268,15 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -2422,8 +2284,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */ /* ##################################### Debug In/Output function ########################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -2435,7 +2295,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** /**
\brief ITM Send Character \brief ITM Send Character
\details Transmits a character via the ITM channel 0, and \details Transmits a character via the ITM channel 0, and
@@ -2444,13 +2303,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
\param [in] ch Character to transmit. \param [in] ch Character to transmit.
\returns Character to transmit. \returns Character to transmit.
*/ */
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
{ {
while (ITM->PORT[0U].u32 == 0UL) while (ITM->PORT[0U].u32 == 0UL) {
{
__NOP(); __NOP();
} }
ITM->PORT[0U].u8 = (uint8_t)ch; ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -2458,19 +2315,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
return (ch); return (ch);
} }
/** /**
\brief ITM Receive Character \brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer. \details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character. \return Received character.
\return -1 No character pending. \return -1 No character pending.
*/ */
__STATIC_INLINE int32_t ITM_ReceiveChar (void) __STATIC_INLINE int32_t ITM_ReceiveChar(void) {
{
int32_t ch = -1; /* no character available */ int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
{
ch = ITM_RxBuffer; ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
} }
@@ -2478,31 +2332,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
return (ch); return (ch);
} }
/** /**
\brief ITM Check Character \brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available. \return 0 No character available.
\return 1 Character available. \return 1 Character available.
*/ */
__STATIC_INLINE int32_t ITM_CheckChar (void) __STATIC_INLINE int32_t ITM_CheckChar(void) {
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
{
return (0); /* no character available */ return (0); /* no character available */
} } else {
else
{
return (1); /* character available */ return (1); /* character available */
} }
} }
/*@} end of CMSIS_core_DebugFunctions */ /*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmFunc.h vendored
View File

@@ -31,7 +31,6 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -41,7 +40,6 @@
#ifndef __CORE_CMFUNC_H #ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H #define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */ /* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface /** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

2
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmInstr.h vendored
View File

@@ -31,7 +31,6 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -41,7 +40,6 @@
#ifndef __CORE_CMINSTR_H #ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H #define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */ /* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions Access to dedicated instructions

3
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmSimd.h vendored
View File

@@ -31,7 +31,6 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -45,7 +44,6 @@
extern "C" { extern "C" {
#endif #endif
/* ################### Compiler specific Intrinsics ########################### */ /* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions Access to dedicated SIMD instructions
@@ -88,7 +86,6 @@
/*@} end of group CMSIS_SIMD_intrinsics */ /*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

143
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_sc000.h vendored
View File

@@ -31,7 +31,6 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,12 +71,10 @@
/* CMSIS SC000 definitions */ /* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | __SC000_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_SC (000U) /*!< Cortex secure core */ #define __CORTEX_SC (000U) /*!< Cortex secure core */
#if defined(__CC_ARM) #if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
@@ -160,8 +156,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -224,8 +220,6 @@
/*@} end of group SC000 */ /*@} end of group SC000 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -250,10 +244,8 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */ uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
@@ -276,14 +268,11 @@ typedef union
#define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
@@ -294,14 +283,11 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
@@ -333,14 +319,11 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */ uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
@@ -354,7 +337,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -365,8 +347,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U]; uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -381,7 +362,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -392,8 +372,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -494,7 +473,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -505,8 +483,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control and ID Register not in the SCB. \brief Structure type to access the System Control and ID Register not in the SCB.
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type; } SCnSCB_Type;
@@ -517,7 +494,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */ /*@} end of group CMSIS_SCnotSCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -528,8 +504,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -580,8 +555,7 @@ typedef struct
/** /**
\brief Structure type to access the Memory Protection Unit (MPU). \brief Structure type to access the Memory Protection Unit (MPU).
*/ */
typedef struct typedef struct {
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -657,7 +631,6 @@ typedef struct
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -667,7 +640,6 @@ typedef struct
*/ */
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -693,7 +665,6 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -719,8 +690,6 @@ typedef struct
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -732,8 +701,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -748,28 +715,19 @@ typedef struct
#define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL)) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL)) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -778,33 +736,21 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -813,21 +759,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0) SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
{ } else {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -837,30 +776,23 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} } else {
else
{
return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */ for (;;) /* wait until reset */
@@ -871,8 +803,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -894,19 +824,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -914,9 +840,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

214
source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_sc300.h vendored
View File

@@ -31,7 +31,6 @@
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/ ---------------------------------------------------------------------------*/
#if defined(__ICCARM__) #if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -61,7 +60,6 @@
Function-like macros are used to allow more efficient code. Function-like macros are used to allow more efficient code.
*/ */
/******************************************************************************* /*******************************************************************************
* CMSIS definitions * CMSIS definitions
******************************************************************************/ ******************************************************************************/
@@ -73,12 +71,10 @@
/* CMSIS SC300 definitions */ /* CMSIS SC300 definitions */
#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | __SC300_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
__SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_SC (300U) /*!< Cortex secure core */ #define __CORTEX_SC (300U) /*!< Cortex secure core */
#if defined(__CC_ARM) #if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
@@ -160,8 +156,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */ #include "core_cmFunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -224,8 +220,6 @@
/*@} end of group SC300 */ /*@} end of group SC300 */
/******************************************************************************* /*******************************************************************************
* Register Abstraction * Register Abstraction
Core Register contain: Core Register contain:
@@ -251,10 +245,8 @@
/** /**
\brief Union type to access the Application Program Status Register (APSR). \brief Union type to access the Application Program Status Register (APSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */
uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
@@ -281,14 +273,11 @@ typedef union
#define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
/** /**
\brief Union type to access the Interrupt Program Status Register (IPSR). \brief Union type to access the Interrupt Program Status Register (IPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */ } b; /*!< Structure used for bit access */
@@ -299,14 +288,11 @@ typedef union
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/** /**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
@@ -345,14 +331,11 @@ typedef union
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/** /**
\brief Union type to access the Control Registers (CONTROL). \brief Union type to access the Control Registers (CONTROL).
*/ */
typedef union typedef union {
{ struct {
struct
{
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
@@ -369,7 +352,6 @@ typedef union
/*@} end of group CMSIS_CORE */ /*@} end of group CMSIS_CORE */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
@@ -380,8 +362,7 @@ typedef union
/** /**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U]; uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -403,7 +384,6 @@ typedef struct
/*@} end of group CMSIS_NVIC */ /*@} end of group CMSIS_NVIC */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB) \defgroup CMSIS_SCB System Control Block (SCB)
@@ -414,8 +394,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control Block (SCB). \brief Structure type to access the System Control Block (SCB).
*/ */
typedef struct typedef struct {
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -627,7 +606,6 @@ typedef struct
/*@} end of group CMSIS_SCB */ /*@} end of group CMSIS_SCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
@@ -638,8 +616,7 @@ typedef struct
/** /**
\brief Structure type to access the System Control and ID Register not in the SCB. \brief Structure type to access the System Control and ID Register not in the SCB.
*/ */
typedef struct typedef struct {
{
uint32_t RESERVED0[1U]; uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
uint32_t RESERVED1[1U]; uint32_t RESERVED1[1U];
@@ -651,7 +628,6 @@ typedef struct
/*@} end of group CMSIS_SCnotSCB */ /*@} end of group CMSIS_SCnotSCB */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick) \defgroup CMSIS_SysTick System Tick Timer (SysTick)
@@ -662,8 +638,7 @@ typedef struct
/** /**
\brief Structure type to access the System Timer (SysTick). \brief Structure type to access the System Timer (SysTick).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -703,7 +678,6 @@ typedef struct
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
@@ -714,10 +688,8 @@ typedef struct
/** /**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/ */
typedef struct typedef struct {
{ __OM union {
__OM union
{
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
@@ -806,7 +778,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_ITM */ /*@}*/ /* end of group CMSIS_ITM */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
@@ -817,8 +788,7 @@ typedef struct
/** /**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT). \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
@@ -953,7 +923,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_DWT */ /*@}*/ /* end of group CMSIS_DWT */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_TPI Trace Port Interface (TPI) \defgroup CMSIS_TPI Trace Port Interface (TPI)
@@ -964,8 +933,7 @@ typedef struct
/** /**
\brief Structure type to access the Trace Port Interface Register (TPI). \brief Structure type to access the Trace Port Interface Register (TPI).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
@@ -1108,7 +1076,6 @@ typedef struct
/*@}*/ /* end of group CMSIS_TPI */ /*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
@@ -1120,8 +1087,7 @@ typedef struct
/** /**
\brief Structure type to access the Memory Protection Unit (MPU). \brief Structure type to access the Memory Protection Unit (MPU).
*/ */
typedef struct typedef struct {
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -1203,7 +1169,6 @@ typedef struct
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
@@ -1214,8 +1179,7 @@ typedef struct
/** /**
\brief Structure type to access the Core Debug Register (CoreDebug). \brief Structure type to access the Core Debug Register (CoreDebug).
*/ */
typedef struct typedef struct {
{
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
@@ -1308,7 +1272,6 @@ typedef struct
/*@} end of group CMSIS_CoreDebug */ /*@} end of group CMSIS_CoreDebug */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros \defgroup CMSIS_core_bitfield Core register bit field macros
@@ -1334,7 +1297,6 @@ typedef struct
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions \defgroup CMSIS_core_base Core Definitions
@@ -1368,8 +1330,6 @@ typedef struct
/*@} */ /*@} */
/******************************************************************************* /*******************************************************************************
* Hardware Abstraction Layer * Hardware Abstraction Layer
Core Function Interface contains: Core Function Interface contains:
@@ -1382,8 +1342,6 @@ typedef struct
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/ */
/* ########################## NVIC functions #################################### */ /* ########################## NVIC functions #################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1401,52 +1359,36 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field. \param [in] PriorityGroup Priority grouping field.
*/ */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
{
uint32_t reg_value; uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */ reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value | reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value; SCB->AIRCR = reg_value;
} }
/** /**
\brief Get Priority Grouping \brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller. \details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
/** /**
\brief Enable External Interrupt \brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Disable External Interrupt \brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
@@ -1455,33 +1397,23 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
{
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn External interrupt number. Value cannot be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }
{
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/** /**
\brief Get Active Interrupt \brief Get Active Interrupt
@@ -1490,11 +1422,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not active. \return 0 Interrupt status is not active.
\return 1 Interrupt status is active. \return 1 Interrupt status is active.
*/ */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
@@ -1503,19 +1431,14 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
{ if ((int32_t)(IRQn) < 0) {
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} } else {
else
{
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of an interrupt.
@@ -1525,20 +1448,15 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
{
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) < 0) {
{
return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
} } else {
else
{
return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
} }
} }
/** /**
\brief Encode Priority \brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group, \details Encodes the priority for an interrupt with the given priority group,
@@ -1550,8 +1468,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\param [in] SubPriority Subpriority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/ */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1559,13 +1476,9 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return ( return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
} }
/** /**
\brief Decode Priority \brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to \details Decodes an interrupt priority value with a given priority group to
@@ -1577,8 +1490,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
\param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0).
*/ */
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits; uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits; uint32_t SubPriorityBits;
@@ -1590,18 +1502,14 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
} }
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __STATIC_INLINE void NVIC_SystemReset(void) {
{
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */ __DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */ for (;;) /* wait until reset */
@@ -1612,8 +1520,6 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1635,19 +1541,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function. must contain a vendor-specific implementation of this function.
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
{ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */ return (1UL); /* Reload value impossible */
} }
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */ return (0UL); /* Function successful */
} }
@@ -1655,8 +1557,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
/*@} end of CMSIS_Core_SysTickFunctions */ /*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */ /* ##################################### Debug In/Output function ########################################### */
/** /**
\ingroup CMSIS_Core_FunctionInterface \ingroup CMSIS_Core_FunctionInterface
@@ -1668,7 +1568,6 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** /**
\brief ITM Send Character \brief ITM Send Character
\details Transmits a character via the ITM channel 0, and \details Transmits a character via the ITM channel 0, and
@@ -1677,13 +1576,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
\param [in] ch Character to transmit. \param [in] ch Character to transmit.
\returns Character to transmit. \returns Character to transmit.
*/ */
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
{ {
while (ITM->PORT[0U].u32 == 0UL) while (ITM->PORT[0U].u32 == 0UL) {
{
__NOP(); __NOP();
} }
ITM->PORT[0U].u8 = (uint8_t)ch; ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -1691,19 +1588,16 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
return (ch); return (ch);
} }
/** /**
\brief ITM Receive Character \brief ITM Receive Character
\details Inputs a character via the external variable \ref ITM_RxBuffer. \details Inputs a character via the external variable \ref ITM_RxBuffer.
\return Received character. \return Received character.
\return -1 No character pending. \return -1 No character pending.
*/ */
__STATIC_INLINE int32_t ITM_ReceiveChar (void) __STATIC_INLINE int32_t ITM_ReceiveChar(void) {
{
int32_t ch = -1; /* no character available */ int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
{
ch = ITM_RxBuffer; ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
} }
@@ -1711,31 +1605,23 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
return (ch); return (ch);
} }
/** /**
\brief ITM Check Character \brief ITM Check Character
\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
\return 0 No character available. \return 0 No character available.
\return 1 Character available. \return 1 Character available.
*/ */
__STATIC_INLINE int32_t ITM_CheckChar (void) __STATIC_INLINE int32_t ITM_CheckChar(void) {
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
{
return (0); /* no character available */ return (0); /* no character available */
} } else {
else
{
return (1); /* character available */ return (1); /* character available */
} }
} }
/*@} end of CMSIS_core_DebugFunctions */ /*@} end of CMSIS_core_DebugFunctions */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

386
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h vendored
View File

@@ -275,8 +275,6 @@
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
/** /**
* @} * @}
*/ */
@@ -378,7 +376,6 @@
* @} * @}
*/ */
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{ * @{
*/ */
@@ -470,12 +467,10 @@
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
#endif /* STM32H7 */ #endif /* STM32H7 */
/** /**
* @} * @}
*/ */
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -720,7 +715,6 @@
* @} * @}
*/ */
/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@@ -741,7 +735,6 @@
* @} * @}
*/ */
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@@ -882,7 +875,6 @@
* @} * @}
*/ */
/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@@ -996,8 +988,7 @@
* @} * @}
*/ */
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@@ -1213,7 +1204,6 @@
* @} * @}
*/ */
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
* @{ * @{
*/ */
@@ -1262,7 +1252,6 @@
* @} * @}
*/ */
/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -1395,7 +1384,6 @@
#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
@@ -1434,158 +1422,176 @@
#define COMP_LOCK __HAL_COMP_LOCK #define COMP_LOCK __HAL_COMP_LOCK
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
__HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
__HAL_COMP_COMP6_EXTI_DISABLE_IT()) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
__HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#endif #endif
#if defined(STM32F302xE) || defined(STM32F302xC) #if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
__HAL_COMP_COMP6_EXTI_ENABLE_IT()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
__HAL_COMP_COMP6_EXTI_DISABLE_IT()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
__HAL_COMP_COMP6_EXTI_GET_FLAG()) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) (((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#endif #endif
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ : __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \
__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ : __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ : __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \
__HAL_COMP_COMP7_EXTI_ENABLE_IT()) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
__HAL_COMP_COMP7_EXTI_DISABLE_IT()) : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ : __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
__HAL_COMP_COMP7_EXTI_GET_FLAG()) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : __HAL_COMP_COMP7_EXTI_ENABLE_IT())
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
(((__EXTILINE__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \
: ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : __HAL_COMP_COMP7_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : __HAL_COMP_COMP7_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == COMP_EXTI_LINE_COMP1) \
? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP2) \
? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP3) \
? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP4) \
? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \
: ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
#endif #endif
#if defined(STM32F373xC) || defined(STM32F378xx) #if defined(STM32F373xC) || defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG())
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#endif #endif
#else #else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG())
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#endif #endif
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
@@ -1616,9 +1622,7 @@
* @{ * @{
*/ */
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
((WAVE) == DAC_WAVE_NOISE)|| \
((WAVE) == DAC_WAVE_TRIANGLE))
/** /**
* @} * @}
@@ -1691,12 +1695,10 @@
#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
/** /**
* @} * @}
*/ */
/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -1706,7 +1708,6 @@
* @} * @}
*/ */
/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -1719,7 +1720,6 @@
* @} * @}
*/ */
/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -1741,7 +1741,6 @@
* @} * @}
*/ */
/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -1761,7 +1760,11 @@
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() \
do { \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while (0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -1770,8 +1773,20 @@
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) #define __HAL_PWR_PVM_DISABLE() \
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) do { \
HAL_PWREx_DisablePVM1(); \
HAL_PWREx_DisablePVM2(); \
HAL_PWREx_DisablePVM3(); \
HAL_PWREx_DisablePVM4(); \
} while (0)
#define __HAL_PWR_PVM_ENABLE() \
do { \
HAL_PWREx_EnablePVM1(); \
HAL_PWREx_EnablePVM2(); \
HAL_PWREx_EnablePVM3(); \
HAL_PWREx_EnablePVM4(); \
} while (0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@@ -1798,7 +1813,6 @@
* @} * @}
*/ */
/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
* @{ * @{
*/ */
@@ -2881,21 +2895,22 @@
#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
#else #else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() \
: (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */ #endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM #define IS_ALARM IS_RTC_ALARM
@@ -3055,7 +3070,6 @@
* @} * @}
*/ */
/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -3200,7 +3214,6 @@
* @} * @}
*/ */
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -3216,4 +3229,3 @@
#endif /* ___STM32_HAL_LEGACY */ #endif /* ___STM32_HAL_LEGACY */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h vendored
View File

@@ -62,13 +62,7 @@ extern "C" {
/** @defgroup HAL_TICK_FREQ Tick Frequency /** @defgroup HAL_TICK_FREQ Tick Frequency
* @{ * @{
*/ */
typedef enum typedef enum { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef;
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/** /**
* @} * @}
*/ */
@@ -248,7 +242,6 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
#endif #endif
#if defined(DBGMCU_CR_DBG_TIM15_STOP) #if defined(DBGMCU_CR_DBG_TIM15_STOP)
/** /**
* @brief TIM15 Peripherals Debug mode * @brief TIM15 Peripherals Debug mode
@@ -280,9 +273,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
/** @defgroup HAL_Private_Macros HAL Private Macros /** @defgroup HAL_Private_Macros HAL Private Macros
* @{ * @{
*/ */
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/** /**
* @} * @}
*/ */

243
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h vendored
View File

@@ -64,11 +64,10 @@
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
* ADC can be either disabled or enabled without conversion on going on regular group. * ADC can be either disabled or enabled without conversion on going on regular group.
*/ */
typedef struct typedef struct {
{
uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset
This parameter can be a value of @ref ADC_Data_align */ application): MSB on register bit 14 and LSB on register bit 3). This parameter can be a value of @ref ADC_Data_align */
uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
@@ -86,7 +85,8 @@ typedef struct
uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). uint32_t
DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */ This parameter can be set to ENABLE or DISABLE. */
@@ -104,18 +104,17 @@ typedef struct
* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
* ADC can be either disabled or enabled without conversion on going on regular group. * ADC can be either disabled or enabled without conversion on going on regular group.
*/ */
typedef struct typedef struct {
{
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection
It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */
Refer to errata sheet of these devices for more details. */
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
This parameter can be a value of @ref ADC_regular_rank This parameter can be a value of @ref ADC_regular_rank
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or
parameter number of conversions can be adjusted) */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
@@ -132,8 +131,7 @@ typedef struct
* @note The setting of these parameters with function is conditioned to ADC state. * @note The setting of these parameters with function is conditioned to ADC state.
* ADC state can be either disabled or enabled without conversion on going on regular and injected groups. * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
*/ */
typedef struct typedef struct {
{
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
This parameter can be a value of @ref ADC_analog_watchdog_mode. */ This parameter can be a value of @ref ADC_analog_watchdog_mode. */
uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
@@ -163,14 +161,16 @@ typedef struct
#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
/* States of ADC group regular */ /* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, #define HAL_ADC_STATE_REG_BUSY \
0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, \
external trigger, low power auto power-on, multimode ADC master control) */ external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ #define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */
/* States of ADC group injected */ /* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, #define HAL_ADC_STATE_INJ_BUSY \
0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, \
external trigger, low power auto power-on, multimode ADC master control) */ external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ #define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
@@ -183,12 +183,10 @@ typedef struct
/* States of ADC multi-mode */ /* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */
/** /**
* @brief ADC handle Structure definition * @brief ADC handle Structure definition
*/ */
typedef struct typedef struct {
{
ADC_TypeDef *Instance; /*!< Register base address */ ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC required parameters */ ADC_InitTypeDef Init; /*!< ADC required parameters */
@@ -205,8 +203,6 @@ typedef struct
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants ADC Exported Constants /** @defgroup ADC_Exported_Constants ADC Exported Constants
@@ -217,7 +213,8 @@ typedef struct
* @{ * @{
*/ */
#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, #define HAL_ADC_ERROR_INTERNAL \
0x01U /*!< ADC IP internal error: if problem of clocking, \
enable/disable, erroneous state */ enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
@@ -226,7 +223,6 @@ typedef struct
* @} * @}
*/ */
/** @defgroup ADC_Data_align ADC data alignment /** @defgroup ADC_Data_align ADC data alignment
* @{ * @{
*/ */
@@ -381,7 +377,6 @@ typedef struct
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@@ -414,28 +409,19 @@ typedef struct
* @{ * @{
*/ */
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
(ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
(ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2)
ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
(ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
(ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1)
ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
(ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
(ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0)
ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
@@ -465,7 +451,6 @@ typedef struct
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Macros ADC Exported Macros /** @defgroup ADC_Exported_Macros ADC Exported Macros
@@ -483,16 +468,14 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval None * @retval None
*/ */
#define __HAL_ADC_ENABLE(__HANDLE__) \ #define __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
(SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
/** /**
* @brief Disable the ADC peripheral * @brief Disable the ADC peripheral
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval None * @retval None
*/ */
#define __HAL_ADC_DISABLE(__HANDLE__) \ #define __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
(CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
/** @brief Enable the ADC end of conversion interrupt. /** @brief Enable the ADC end of conversion interrupt.
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
@@ -503,8 +486,7 @@ typedef struct
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
* @retval None * @retval None
*/ */
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
/** @brief Disable the ADC end of conversion interrupt. /** @brief Disable the ADC end of conversion interrupt.
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
@@ -515,8 +497,7 @@ typedef struct
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
* @retval None * @retval None
*/ */
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
/** @brief Checks if the specified ADC interrupt source is enabled or disabled. /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
@@ -527,8 +508,7 @@ typedef struct
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
* @retval None * @retval None
*/ */
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected ADC's flag status. /** @brief Get the selected ADC's flag status.
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
@@ -541,8 +521,7 @@ typedef struct
* @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
* @retval None * @retval None
*/ */
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the ADC's pending flags /** @brief Clear the ADC's pending flags
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
@@ -555,15 +534,13 @@ typedef struct
* @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
* @retval None * @retval None
*/ */
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
(WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
/** @brief Reset ADC handle state /** @brief Reset ADC handle state
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval None * @retval None
*/ */
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
/** /**
* @} * @}
@@ -582,9 +559,7 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval SET (ADC enabled) or RESET (ADC disabled) * @retval SET (ADC enabled) or RESET (ADC disabled)
*/ */
#define ADC_IS_ENABLE(__HANDLE__) \ #define ADC_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON)) ? SET : RESET)
((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
) ? SET : RESET)
/** /**
* @brief Test if conversion trigger of regular group is software start * @brief Test if conversion trigger of regular group is software start
@@ -592,8 +567,7 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval SET (software start) or RESET (external trigger) * @retval SET (software start) or RESET (external trigger)
*/ */
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
/** /**
* @brief Test if conversion trigger of injected group is software start * @brief Test if conversion trigger of injected group is software start
@@ -601,8 +575,7 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval SET (software start) or RESET (external trigger) * @retval SET (software start) or RESET (external trigger)
*/ */
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
/** /**
* @brief Simultaneously clears and sets specific bits of the handle State * @brief Simultaneously clears and sets specific bits of the handle State
@@ -618,16 +591,14 @@ typedef struct
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval None * @retval None
*/ */
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
/** /**
* @brief Set ADC number of conversions into regular channel sequence length. * @brief Set ADC number of conversions into regular channel sequence length.
* @param _NbrOfConversion_: Regular channel sequence length * @param _NbrOfConversion_: Regular channel sequence length
* @retval None * @retval None
*/ */
#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
(((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
/** /**
* @brief Set the ADC's sample time for channel numbers between 10 and 18. * @brief Set the ADC's sample time for channel numbers between 10 and 18.
@@ -635,8 +606,7 @@ typedef struct
* @param _CHANNELNB_: Channel number. * @param _CHANNELNB_: Channel number.
* @retval None * @retval None
*/ */
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_)-10)))
((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
/** /**
* @brief Set the ADC's sample time for channel numbers between 0 and 9. * @brief Set the ADC's sample time for channel numbers between 0 and 9.
@@ -644,8 +614,7 @@ typedef struct
* @param _CHANNELNB_: Channel number. * @param _CHANNELNB_: Channel number.
* @retval None * @retval None
*/ */
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
/** /**
* @brief Set the selected regular channel rank for rank between 1 and 6. * @brief Set the selected regular channel rank for rank between 1 and 6.
@@ -653,8 +622,7 @@ typedef struct
* @param _RANKNB_: Rank number. * @param _RANKNB_: Rank number.
* @retval None * @retval None
*/ */
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_)-1)))
((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
/** /**
* @brief Set the selected regular channel rank for rank between 7 and 12. * @brief Set the selected regular channel rank for rank between 7 and 12.
@@ -662,8 +630,7 @@ typedef struct
* @param _RANKNB_: Rank number. * @param _RANKNB_: Rank number.
* @retval None * @retval None
*/ */
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_)-7)))
((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
/** /**
* @brief Set the selected regular channel rank for rank between 13 and 16. * @brief Set the selected regular channel rank for rank between 13 and 16.
@@ -671,16 +638,14 @@ typedef struct
* @param _RANKNB_: Rank number. * @param _RANKNB_: Rank number.
* @retval None * @retval None
*/ */
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_)-13)))
((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
/** /**
* @brief Set the injected sequence length. * @brief Set the injected sequence length.
* @param _JSQR_JL_: Sequence length. * @param _JSQR_JL_: Sequence length.
* @retval None * @retval None
*/ */
#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_)-1) << ADC_JSQR_JL_Pos)
(((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
/** /**
* @brief Set the selected injected channel rank * @brief Set the selected injected channel rank
@@ -692,24 +657,21 @@ typedef struct
* @param _JSQR_JL_: Sequence length. * @param _JSQR_JL_: Sequence length.
* @retval None * @retval None
*/ */
#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
/** /**
* @brief Enable ADC continuous conversion mode. * @brief Enable ADC continuous conversion mode.
* @param _CONTINUOUS_MODE_: Continuous mode. * @param _CONTINUOUS_MODE_: Continuous mode.
* @retval None * @retval None
*/ */
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
/** /**
* @brief Configures the number of discontinuous conversions for the regular group channels. * @brief Configures the number of discontinuous conversions for the regular group channels.
* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
* @retval None * @retval None
*/ */
#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_)-1) << ADC_CR1_DISCNUM_Pos)
(((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
/** /**
* @brief Enable ADC scan mode to convert multiple ranks with sequencer. * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
@@ -718,10 +680,7 @@ typedef struct
*/ */
/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
/* is equivalent to ADC_SCAN_ENABLE. */ /* is equivalent to ADC_SCAN_ENABLE. */
#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ #define ADC_CR1_SCAN_SET(_SCAN_MODE_) ((((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)) ? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE))
(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
)
/** /**
* @brief Get the maximum ADC conversion cycles on all channels. * @brief Get the maximum ADC conversion cycles on all channels.
@@ -736,89 +695,47 @@ typedef struct
* @retval ADC conversion cycles on all channels * @retval ADC conversion cycles on all channels
*/ */
#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET)) \
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ ? \
\ \
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 \
ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
: \ : ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \
((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ || ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) \
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 \
((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5))
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT))
((ALIGN) == ADC_DATAALIGN_LEFT) )
#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || ((SCAN_MODE) == ADC_SCAN_ENABLE))
((SCAN_MODE) == ADC_SCAN_ENABLE) )
#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING))
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ #define IS_ADC_CHANNEL(CHANNEL) \
((CHANNEL) == ADC_CHANNEL_1) || \ (((CHANNEL) == ADC_CHANNEL_0) || ((CHANNEL) == ADC_CHANNEL_1) || ((CHANNEL) == ADC_CHANNEL_2) || ((CHANNEL) == ADC_CHANNEL_3) || ((CHANNEL) == ADC_CHANNEL_4) || ((CHANNEL) == ADC_CHANNEL_5) \
((CHANNEL) == ADC_CHANNEL_2) || \ || ((CHANNEL) == ADC_CHANNEL_6) || ((CHANNEL) == ADC_CHANNEL_7) || ((CHANNEL) == ADC_CHANNEL_8) || ((CHANNEL) == ADC_CHANNEL_9) || ((CHANNEL) == ADC_CHANNEL_10) || ((CHANNEL) == ADC_CHANNEL_11) \
((CHANNEL) == ADC_CHANNEL_3) || \ || ((CHANNEL) == ADC_CHANNEL_12) || ((CHANNEL) == ADC_CHANNEL_13) || ((CHANNEL) == ADC_CHANNEL_14) || ((CHANNEL) == ADC_CHANNEL_15) || ((CHANNEL) == ADC_CHANNEL_16) \
((CHANNEL) == ADC_CHANNEL_4) || \ || ((CHANNEL) == ADC_CHANNEL_17))
((CHANNEL) == ADC_CHANNEL_5) || \
((CHANNEL) == ADC_CHANNEL_6) || \
((CHANNEL) == ADC_CHANNEL_7) || \
((CHANNEL) == ADC_CHANNEL_8) || \
((CHANNEL) == ADC_CHANNEL_9) || \
((CHANNEL) == ADC_CHANNEL_10) || \
((CHANNEL) == ADC_CHANNEL_11) || \
((CHANNEL) == ADC_CHANNEL_12) || \
((CHANNEL) == ADC_CHANNEL_13) || \
((CHANNEL) == ADC_CHANNEL_14) || \
((CHANNEL) == ADC_CHANNEL_15) || \
((CHANNEL) == ADC_CHANNEL_16) || \
((CHANNEL) == ADC_CHANNEL_17) )
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ #define IS_ADC_SAMPLE_TIME(TIME) \
((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || ((TIME) == ADC_SAMPLETIME_28CYCLES_5) \
((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ || ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ #define IS_ADC_REGULAR_RANK(CHANNEL) \
((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ (((CHANNEL) == ADC_REGULAR_RANK_1) || ((CHANNEL) == ADC_REGULAR_RANK_2) || ((CHANNEL) == ADC_REGULAR_RANK_3) || ((CHANNEL) == ADC_REGULAR_RANK_4) || ((CHANNEL) == ADC_REGULAR_RANK_5) \
((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ || ((CHANNEL) == ADC_REGULAR_RANK_6) || ((CHANNEL) == ADC_REGULAR_RANK_7) || ((CHANNEL) == ADC_REGULAR_RANK_8) || ((CHANNEL) == ADC_REGULAR_RANK_9) || ((CHANNEL) == ADC_REGULAR_RANK_10) \
((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ || ((CHANNEL) == ADC_REGULAR_RANK_11) || ((CHANNEL) == ADC_REGULAR_RANK_12) || ((CHANNEL) == ADC_REGULAR_RANK_13) || ((CHANNEL) == ADC_REGULAR_RANK_14) || ((CHANNEL) == ADC_REGULAR_RANK_15) \
((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ || ((CHANNEL) == ADC_REGULAR_RANK_16))
((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
((CHANNEL) == ADC_REGULAR_RANK_10) || \
((CHANNEL) == ADC_REGULAR_RANK_11) || \
((CHANNEL) == ADC_REGULAR_RANK_12) || \
((CHANNEL) == ADC_REGULAR_RANK_13) || \
((CHANNEL) == ADC_REGULAR_RANK_14) || \
((CHANNEL) == ADC_REGULAR_RANK_15) || \
((CHANNEL) == ADC_REGULAR_RANK_16) )
#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) \
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC))
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || ((CONVERSION) == ADC_INJECTED_GROUP) || ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP))
((CONVERSION) == ADC_INJECTED_GROUP) || \
((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
/** @defgroup ADC_range_verification ADC range verification /** @defgroup ADC_range_verification ADC range verification
* For a unique ADC resolution: 12 bits * For a unique ADC resolution: 12 bits
* @{ * @{
@@ -860,7 +777,6 @@ typedef struct
* @{ * @{
*/ */
/* Initialization and de-initialization functions **********************************/ /* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
@@ -876,7 +792,6 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
* @{ * @{
*/ */
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
@@ -904,7 +819,6 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
* @} * @}
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
/** @addtogroup ADC_Exported_Functions_Group3 /** @addtogroup ADC_Exported_Functions_Group3
* @{ * @{
@@ -915,7 +829,6 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_Ana
* @} * @}
*/ */
/* Peripheral State functions *************************************************/ /* Peripheral State functions *************************************************/
/** @addtogroup ADC_Exported_Functions_Group4 /** @addtogroup ADC_Exported_Functions_Group4
* @{ * @{
@@ -926,12 +839,10 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Internal HAL driver functions **********************************************/ /* Internal HAL driver functions **********************************************/
/** @addtogroup ADC_Private_Functions /** @addtogroup ADC_Private_Functions
* @{ * @{
@@ -946,7 +857,6 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma);
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@@ -959,7 +869,6 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma);
} }
#endif #endif
#endif /* __STM32F1xx_HAL_ADC_H */ #endif /* __STM32F1xx_HAL_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

285
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h vendored
View File

@@ -68,18 +68,18 @@
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv') * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
* - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group. * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
*/ */
typedef struct typedef struct {
{ uint32_t
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure InjectedChannel; /*!< Selection of ADC channel to configure
This parameter can be a value of @ref ADC_channels This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection
It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */
Refer to errata sheet of these devices for more details. */
uint32_t InjectedRank; /*!< Rank in the injected group sequencer uint32_t InjectedRank; /*!< Rank in the injected group sequencer
This parameter must be a value of @ref ADCEx_injected_rank This parameter must be a value of @ref ADCEx_injected_rank
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel
setting (or parameter number of conversions can be adjusted) */
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
@@ -98,13 +98,12 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 4. This parameter must be a number between Min_Data = 1 and Max_Data = 4.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */ configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). uint32_t
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous
This parameter can be set to ENABLE or DISABLE. mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */
configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
This parameter can be set to ENABLE or DISABLE. This parameter can be set to ENABLE or DISABLE.
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
@@ -118,8 +117,8 @@ typedef struct
If set to external trigger source, triggering is on event rising edge. If set to external trigger source, triggering is on event rising edge.
This parameter can be a value of @ref ADCEx_External_trigger_source_Injected This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to the fly) Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */ configure a channel on injected group can impact the configuration of other channels previously set. */
} ADC_InjectionConfTypeDef; } ADC_InjectionConfTypeDef;
@@ -129,18 +128,18 @@ typedef struct
* @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
* State of ADCs of the common group must be: disabled. * State of ADCs of the common group must be: disabled.
*/ */
typedef struct typedef struct {
{
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
This parameter can be a value of @ref ADCEx_Common_mode This parameter can be a value of @ref ADCEx_Common_mode
Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any
Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2. configuration change. Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1
Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode. and ADC2. Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC
Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters). clock cycles for slow interleaved mode. Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration
The equivalences are: structure can have additional parameters). The equivalences are:
- Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'. - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several
- Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */ ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
- Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32
devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
} ADC_MultiModeTypeDef; } ADC_MultiModeTypeDef;
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
@@ -149,7 +148,6 @@ typedef struct
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
@@ -272,12 +270,20 @@ typedef struct
#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ #define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */ #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */ #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INJECSIMULT_INTERLFAST \
#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ ((uint32_t)(ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling \
phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW \
((uint32_t)(ADC_CR1_DUALMOD_2)) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock \
cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */ #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */ #define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INTERLFAST \
#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles \
(equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INTERLSLOW \
((uint32_t)(ADC_CR1_DUALMOD_3)) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter \
"TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */ #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
/** /**
* @} * @}
@@ -288,7 +294,6 @@ typedef struct
* @} * @}
*/ */
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
@@ -372,7 +377,6 @@ typedef struct
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
@@ -383,7 +387,6 @@ typedef struct
/* Macro reserved for internal HAL driver usage, not intended to be used in */ /* Macro reserved for internal HAL driver usage, not intended to be used in */
/* code of final user. */ /* code of final user. */
/** /**
* @brief For devices with 3 ADCs: Defines the external trigger source * @brief For devices with 3 ADCs: Defines the external trigger source
* for regular group according to ADC into common group ADC1&ADC2 or * for regular group according to ADC into common group ADC1&ADC2 or
@@ -396,20 +399,9 @@ typedef struct
*/ */
#if defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
(( (((__HANDLE__)->Instance) == ADC3) \ (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO) ? (ADC3_EXTERNALTRIG_T8_TRGO) : (__EXT_TRIG_CONV__)) : (__EXT_TRIG_CONV__))
)? \
( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
)? \
(ADC3_EXTERNALTRIG_T8_TRGO) \
: \
(__EXT_TRIG_CONV__) \
) \
: \
(__EXT_TRIG_CONV__) \
)
#else #else
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) (__EXT_TRIG_CONV__)
(__EXT_TRIG_CONV__)
#endif /* STM32F103xE || STM32F103xG */ #endif /* STM32F103xE || STM32F103xG */
/** /**
@@ -424,39 +416,20 @@ typedef struct
*/ */
#if defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
(( (((__HANDLE__)->Instance) == ADC3) \ (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) ? (ADC3_EXTERNALTRIGINJEC_T8_CC4) : (__EXT_TRIG_INJECTCONV__)) : (__EXT_TRIG_INJECTCONV__))
)? \
( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
)? \
(ADC3_EXTERNALTRIGINJEC_T8_CC4) \
: \
(__EXT_TRIG_INJECTCONV__) \
) \
: \
(__EXT_TRIG_INJECTCONV__) \
)
#else #else
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) (__EXT_TRIG_INJECTCONV__)
(__EXT_TRIG_INJECTCONV__)
#endif /* STM32F103xE || STM32F103xG */ #endif /* STM32F103xE || STM32F103xG */
/** /**
* @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs) * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
* @param __HANDLE__: ADC handle * @param __HANDLE__: ADC handle
* @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
*/ */
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_DUALMOD) : (RESET))
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
)? \
(ADC1->CR1 & ADC_CR1_DUALMOD) \
: \
(RESET) \
)
#else #else
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (RESET)
(RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/** /**
@@ -465,16 +438,9 @@ typedef struct
* @retval None * @retval None
*/ */
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (((((__HANDLE__)->Instance) == ADC2)) ? ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) : (!RESET))
(( (((__HANDLE__)->Instance) == ADC2) \
)? \
((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \
: \
(!RESET) \
)
#else #else
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (!RESET)
(!RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/** /**
@@ -483,16 +449,9 @@ typedef struct
* @retval None * @retval None
*/ */
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_JAUTO) : (RESET))
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
)? \
(ADC1->CR1 & ADC_CR1_JAUTO) \
: \
(RESET) \
)
#else #else
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (RESET)
(RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
@@ -502,8 +461,7 @@ typedef struct
* @param __HANDLE_OTHER_ADC__: other ADC handle * @param __HANDLE_OTHER_ADC__: other ADC handle
* @retval None * @retval None
*/ */
#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
((__HANDLE_OTHER_ADC__)->Instance = ADC2)
/** /**
* @brief Set handle of the ADC slave associated to the ADC master * @brief Set handle of the ADC slave associated to the ADC master
@@ -513,18 +471,13 @@ typedef struct
* @param __HANDLE_SLAVE__: ADC slave handle * @param __HANDLE_SLAVE__: ADC slave handle
* @retval None * @retval None
*/ */
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ((__HANDLE_SLAVE__)->Instance = ADC2)
((__HANDLE_SLAVE__)->Instance = ADC2)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || ((CHANNEL) == ADC_INJECTED_RANK_2) || ((CHANNEL) == ADC_INJECTED_RANK_3) || ((CHANNEL) == ADC_INJECTED_RANK_4))
((CHANNEL) == ADC_INJECTED_RANK_2) || \
((CHANNEL) == ADC_INJECTED_RANK_3) || \
((CHANNEL) == ADC_INJECTED_RANK_4))
#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
* @{ * @{
@@ -534,121 +487,69 @@ typedef struct
* @} * @}
*/ */
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ || defined(STM32F105xC) || defined(STM32F107xC)
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ #define IS_ADC_EXTTRIG(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif #endif
#if defined(STM32F101xE) #if defined(STM32F101xE)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ #define IS_ADC_EXTTRIG(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif #endif
#if defined(STM32F101xG) #if defined(STM32F101xG)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ #define IS_ADC_EXTTRIG(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif #endif
#if defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ #define IS_ADC_EXTTRIG(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif #endif
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ || defined(STM32F105xC) || defined(STM32F107xC)
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ #define IS_ADC_EXTTRIGINJEC(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif #endif
#if defined(STM32F101xE) #if defined(STM32F101xE)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ #define IS_ADC_EXTTRIGINJEC(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif #endif
#if defined(STM32F101xG) #if defined(STM32F101xG)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ #define IS_ADC_EXTTRIGINJEC(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif #endif
#if defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F103xE) || defined(STM32F103xG)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ #define IS_ADC_EXTTRIGINJEC(REGTRIG) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif #endif
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ #define IS_ADC_MODE(MODE) \
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ (((MODE) == ADC_MODE_INDEPENDENT) || ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) \
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || ((MODE) == ADC_DUALMODE_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT) || ((MODE) == ADC_DUALMODE_INTERLFAST) \
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \ || ((MODE) == ADC_DUALMODE_INTERLSLOW) || ((MODE) == ADC_DUALMODE_ALTERTRIG))
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
((MODE) == ADC_DUALMODE_INJECSIMULT) || \
((MODE) == ADC_DUALMODE_REGSIMULT) || \
((MODE) == ADC_DUALMODE_INTERLFAST) || \
((MODE) == ADC_DUALMODE_INTERLSLOW) || \
((MODE) == ADC_DUALMODE_ALTERTRIG) )
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/** /**
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup ADCEx_Exported_Functions /** @addtogroup ADCEx_Exported_Functions
* @{ * @{
@@ -689,7 +590,6 @@ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* ha
* @} * @}
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
/** @addtogroup ADCEx_Exported_Functions_Group2 /** @addtogroup ADCEx_Exported_Functions_Group2
* @{ * @{
@@ -702,12 +602,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@@ -722,5 +620,4 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc
#endif /* __STM32F1xx_HAL_ADC_EX_H */ #endif /* __STM32F1xx_HAL_ADC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

104
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h vendored
View File

@@ -61,8 +61,7 @@
* @brief MPU Region initialization structure * @brief MPU Region initialization structure
* @{ * @{
*/ */
typedef struct typedef struct {
{
uint8_t Enable; /*!< Specifies the status of the region. uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect. uint8_t Number; /*!< Specifies the number of the region to protect.
@@ -103,15 +102,20 @@ typedef struct
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{ * @{
*/ */
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority #define NVIC_PRIORITYGROUP_0 \
0x00000007U /*!< 0 bits for pre-emption priority \
4 bits for subpriority */ 4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority #define NVIC_PRIORITYGROUP_1 \
0x00000006U /*!< 1 bits for pre-emption priority \
3 bits for subpriority */ 3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority #define NVIC_PRIORITYGROUP_2 \
0x00000005U /*!< 2 bits for pre-emption priority \
2 bits for subpriority */ 2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority #define NVIC_PRIORITYGROUP_3 \
0x00000004U /*!< 3 bits for pre-emption priority \
1 bits for subpriority */ 1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority #define NVIC_PRIORITYGROUP_4 \
0x00000003U /*!< 4 bits for pre-emption priority \
0 bits for subpriority */ 0 bits for subpriority */
/** /**
* @} * @}
@@ -263,7 +267,6 @@ typedef struct
* @} * @}
*/ */
/* Exported Macros -----------------------------------------------------------*/ /* Exported Macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
@@ -319,11 +322,8 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{ * @{
*/ */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ #define IS_NVIC_PRIORITY_GROUP(GROUP) \
((GROUP) == NVIC_PRIORITYGROUP_1) || \ (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
@@ -331,73 +331,36 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2))
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) \
((TYPE) == MPU_REGION_PRIV_RW) || \ (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \ || ((TYPE) == MPU_REGION_PRIV_RO_URO))
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ #define IS_MPU_REGION_NUMBER(NUMBER) \
((NUMBER) == MPU_REGION_NUMBER1) || \ (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) \
((NUMBER) == MPU_REGION_NUMBER2) || \ || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ #define IS_MPU_REGION_SIZE(SIZE) \
((SIZE) == MPU_REGION_SIZE_64B) || \ (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B) \
((SIZE) == MPU_REGION_SIZE_128B) || \ || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) \
((SIZE) == MPU_REGION_SIZE_256B) || \ || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) \
((SIZE) == MPU_REGION_SIZE_512B) || \ || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) \
((SIZE) == MPU_REGION_SIZE_1KB) || \ || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) \
((SIZE) == MPU_REGION_SIZE_2KB) || \ || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
@@ -422,5 +385,4 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __STM32F1xx_HAL_CORTEX_H */ #endif /* __STM32F1xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

23
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h vendored
View File

@@ -54,22 +54,12 @@ extern "C" {
/** /**
* @brief HAL Status structures definition * @brief HAL Status structures definition
*/ */
typedef enum typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef;
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/** /**
* @brief HAL Lock structures definition * @brief HAL Lock structures definition
*/ */
typedef enum typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef;
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_MAX_DELAY 0xFFFFFFFFU
@@ -108,12 +98,9 @@ typedef enum
#else #else
#define __HAL_LOCK(__HANDLE__) \ #define __HAL_LOCK(__HANDLE__) \
do { \ do { \
if((__HANDLE__)->Lock == HAL_LOCKED) \ if ((__HANDLE__)->Lock == HAL_LOCKED) { \
{ \
return HAL_BUSY; \ return HAL_BUSY; \
} \ } else { \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \ (__HANDLE__)->Lock = HAL_LOCKED; \
} \ } \
} while (0U) } while (0U)
@@ -133,7 +120,6 @@ typedef enum
#endif /* __packed */ #endif /* __packed */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */ #if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END #ifndef __ALIGN_END
@@ -155,7 +141,6 @@ typedef enum
#endif /* __ALIGN_BEGIN */ #endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/** /**
* @brief __RAM_FUNC definition * @brief __RAM_FUNC definition
*/ */

44
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h vendored
View File

@@ -61,8 +61,7 @@
/** /**
* @brief DMA Configuration Structure definition * @brief DMA Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory. from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */ This parameter can be a value of @ref DMA_Data_transfer_direction */
@@ -91,8 +90,7 @@ typedef struct
/** /**
* @brief HAL DMA State structures definition * @brief HAL DMA State structures definition
*/ */
typedef enum typedef enum {
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
@@ -102,8 +100,7 @@ typedef enum
/** /**
* @brief HAL DMA Error Code structure definition * @brief HAL DMA Error Code structure definition
*/ */
typedef enum typedef enum {
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
} HAL_DMA_LevelCompleteTypeDef; } HAL_DMA_LevelCompleteTypeDef;
@@ -111,8 +108,7 @@ typedef enum
/** /**
* @brief HAL DMA Callback ID structure definition * @brief HAL DMA Callback ID structure definition
*/ */
typedef enum typedef enum {
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
@@ -124,8 +120,7 @@ typedef enum
/** /**
* @brief DMA handle Structure definition * @brief DMA handle Structure definition
*/ */
typedef struct __DMA_HandleTypeDef typedef struct __DMA_HandleTypeDef {
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */ DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */ DMA_InitTypeDef Init; /*!< DMA communication parameters */
@@ -242,7 +237,6 @@ typedef struct __DMA_HandleTypeDef
* @} * @}
*/ */
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{ * @{
*/ */
@@ -292,7 +286,6 @@ typedef struct __DMA_HandleTypeDef
* @} * @}
*/ */
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros /** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{ * @{
@@ -318,7 +311,6 @@ typedef struct __DMA_HandleTypeDef
*/ */
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
/* Interrupt & Flag management */ /* Interrupt & Flag management */
/** /**
@@ -422,33 +414,21 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
* @{ * @{
*/ */
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))
((STATE) == DMA_MINC_DISABLE))
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD))
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD))
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR))
((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/** /**
* @} * @}

211
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h vendored
View File

@@ -59,8 +59,7 @@
* @{ * @{
*/ */
/* Interrupt & Flag management */ /* Interrupt & Flag management */
#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
* @{ * @{
*/ */
@@ -71,18 +70,27 @@
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ? DMA_FLAG_TC1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ? DMA_FLAG_TC2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ? DMA_FLAG_TC3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ ? DMA_FLAG_TC4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ ? DMA_FLAG_TC5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_TC5) ? DMA_FLAG_TC6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_TC7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_TC1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_TC2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_TC3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 : DMA_FLAG_TC5)
/** /**
* @brief Returns the current DMA Channel half transfer complete flag. * @brief Returns the current DMA Channel half transfer complete flag.
@@ -90,18 +98,27 @@
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ? DMA_FLAG_HT1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ? DMA_FLAG_HT2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ? DMA_FLAG_HT3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ ? DMA_FLAG_HT4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ ? DMA_FLAG_HT5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_HT5) ? DMA_FLAG_HT6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_HT7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_HT1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_HT2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_HT3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 : DMA_FLAG_HT5)
/** /**
* @brief Returns the current DMA Channel transfer error flag. * @brief Returns the current DMA Channel transfer error flag.
@@ -109,18 +126,27 @@
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ? DMA_FLAG_TE1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ? DMA_FLAG_TE2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ? DMA_FLAG_TE3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ ? DMA_FLAG_TE4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ ? DMA_FLAG_TE5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_TE5) ? DMA_FLAG_TE6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_TE7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_TE1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_TE2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_TE3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 : DMA_FLAG_TE5)
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
@@ -128,18 +154,27 @@
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ ? DMA_FLAG_GL1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ ? DMA_FLAG_GL2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ ? DMA_FLAG_GL3 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ ? DMA_FLAG_GL4 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ ? DMA_FLAG_GL5 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) \
DMA_FLAG_GL5) ? DMA_FLAG_GL6 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) \
? DMA_FLAG_GL7 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) \
? DMA_FLAG_GL1 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) \
? DMA_FLAG_GL2 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) \
? DMA_FLAG_GL3 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 : DMA_FLAG_GL5)
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.
@@ -152,9 +187,7 @@
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET). * @retval The state of FLAG (SET or RESET).
*/ */
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
(DMA1->ISR & (__FLAG__)))
/** /**
* @brief Clears the DMA Channel pending flags. * @brief Clears the DMA Channel pending flags.
@@ -167,9 +200,7 @@
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval None * @retval None
*/ */
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
(DMA1->IFCR = (__FLAG__)))
/** /**
* @} * @}
@@ -186,13 +217,16 @@
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ? DMA_FLAG_TC1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ? DMA_FLAG_TC2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ? DMA_FLAG_TC3 \
DMA_FLAG_TC7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TC4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 : DMA_FLAG_TC7)
/** /**
* @brief Return the current DMA Channel half transfer complete flag. * @brief Return the current DMA Channel half transfer complete flag.
@@ -200,13 +234,16 @@
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ? DMA_FLAG_HT1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ? DMA_FLAG_HT2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ? DMA_FLAG_HT3 \
DMA_FLAG_HT7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_HT4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 : DMA_FLAG_HT7)
/** /**
* @brief Return the current DMA Channel transfer error flag. * @brief Return the current DMA Channel transfer error flag.
@@ -214,13 +251,16 @@
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ? DMA_FLAG_TE1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ? DMA_FLAG_TE2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ? DMA_FLAG_TE3 \
DMA_FLAG_TE7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_TE4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 : DMA_FLAG_TE7)
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
@@ -228,13 +268,16 @@
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ ? DMA_FLAG_GL1 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ ? DMA_FLAG_GL2 \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) \
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ ? DMA_FLAG_GL3 \
DMA_FLAG_GL7) : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) \
? DMA_FLAG_GL4 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
: ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 : DMA_FLAG_GL7)
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.

16
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h vendored
View File

@@ -64,14 +64,10 @@
* @{ * @{
*/ */
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
#if defined(FLASH_ACR_LATENCY) #if defined(FLASH_ACR_LATENCY)
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1) || ((__LATENCY__) == FLASH_LATENCY_2))
((__LATENCY__) == FLASH_LATENCY_1) || \
((__LATENCY__) == FLASH_LATENCY_2))
#else #else
#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
@@ -88,8 +84,7 @@
/** /**
* @brief FLASH Procedure structure definition * @brief FLASH Procedure structure definition
*/ */
typedef enum typedef enum {
{
FLASH_PROC_NONE = 0U, FLASH_PROC_NONE = 0U,
FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_PAGEERASE = 1U,
FLASH_PROC_MASSERASE = 2U, FLASH_PROC_MASSERASE = 2U,
@@ -101,8 +96,7 @@ typedef enum
/** /**
* @brief FLASH handle Structure definition * @brief FLASH handle Structure definition
*/ */
typedef struct typedef struct {
{
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
@@ -223,7 +217,6 @@ typedef struct
*/ */
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__)) #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__))
/** /**
* @brief Get the FLASH Latency. * @brief Get the FLASH Latency.
* @retval FLASH Latency * @retval FLASH Latency
@@ -341,4 +334,3 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
#endif /* __STM32F1xx_HAL_FLASH_H */ #endif /* __STM32F1xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

123
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h vendored
View File

@@ -90,84 +90,88 @@
/* Low Density */ /* Low Density */
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \ #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU)) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
/* Medium Density */ /* Medium Density */
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \ ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU)))) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) \
? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))))
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
/* High Density */ /* High Density */
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \ #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU))) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0807FFFFU) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0805FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU)))
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
/* XL Density */ /* XL Density */
#if defined(FLASH_BANK2_END) #if defined(FLASH_BANK2_END)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \ #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU)) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080FFFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080BFFFFU))
#endif /* FLASH_BANK2_END */ #endif /* FLASH_BANK2_END */
/* Connectivity Line */ /* Connectivity Line */
#if (defined(STM32F105xC) || defined(STM32F107xC)) #if (defined(STM32F105xC) || defined(STM32F107xC))
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \ #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU))) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU)))
#endif /* STM32F105xC || STM32F107xC */ #endif /* STM32F105xC || STM32F107xC */
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#if defined(FLASH_BANK2_END) #if defined(FLASH_BANK2_END)
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || ((BANK) == FLASH_BANK_BOTH))
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
#else #else
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
#endif /* FLASH_BANK2_END */ #endif /* FLASH_BANK2_END */
/* Low Density */ /* Low Density */
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
/* Medium Density */ /* Medium Density */
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \ (((ADDRESS) >= FLASH_BASE) \
((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) \
((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) ? ((ADDRESS) <= FLASH_BANK1_END) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS) <= 0x0800FFFF) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
/* High Density */ /* High Density */
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \ (((ADDRESS) >= FLASH_BASE) \
((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS) <= FLASH_BANK1_END) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
/* XL Density */ /* XL Density */
#if defined(FLASH_BANK2_END) #if defined(FLASH_BANK2_END)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
#endif /* FLASH_BANK2_END */ #endif /* FLASH_BANK2_END */
/* Connectivity Line */ /* Connectivity Line */
#if (defined(STM32F105xC) || defined(STM32F107xC)) #if (defined(STM32F105xC) || defined(STM32F107xC))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ (((ADDRESS) >= FLASH_BASE) \
((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS) <= FLASH_BANK1_END) \
: (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
#endif /* STM32F105xC || STM32F107xC */ #endif /* STM32F105xC || STM32F107xC */
@@ -183,8 +187,7 @@
/** /**
* @brief FLASH Erase structure definition * @brief FLASH Erase structure definition
*/ */
typedef struct typedef struct {
{
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
This parameter can be a value of @ref FLASHEx_Type_Erase */ This parameter can be a value of @ref FLASHEx_Type_Erase */
@@ -203,8 +206,7 @@ typedef struct
/** /**
* @brief FLASH Options bytes program structure definition * @brief FLASH Options bytes program structure definition
*/ */
typedef struct typedef struct {
{
uint32_t OptionType; /*!< OptionType: Option byte to be configured. uint32_t OptionType; /*!< OptionType: Option byte to be configured.
This parameter can be a value of @ref FLASHEx_OB_Type */ This parameter can be a value of @ref FLASHEx_OB_Type */
@@ -329,9 +331,7 @@ typedef struct
* @{ * @{
*/ */
/* STM32 Low and Medium density devices */ /* STM32 Low and Medium density devices */
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \ #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
|| defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
|| defined(STM32F103xB)
#define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */ #define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */
#define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */ #define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */
#define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */ #define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */
@@ -371,11 +371,8 @@ typedef struct
#define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */ #define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
/* STM32 High-density, XL-density and Connectivity line devices */ /* STM32 High-density, XL-density and Connectivity line devices */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|| defined(STM32F101xG) || defined(STM32F103xG) \
|| defined(STM32F105xC) || defined(STM32F107xC)
#define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */ #define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */
#define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */ #define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */
#define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */ #define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */
@@ -582,7 +579,6 @@ typedef struct
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@@ -608,7 +604,8 @@ typedef struct
* @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
* @retval none * @retval none
*/ */
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) \
do { \
/* Enable Bank1 IT */ \ /* Enable Bank1 IT */ \
SET_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \ SET_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
/* Enable Bank2 IT */ \ /* Enable Bank2 IT */ \
@@ -625,7 +622,8 @@ typedef struct
* @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
* @retval none * @retval none
*/ */
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) \
do { \
/* Disable Bank1 IT */ \ /* Disable Bank1 IT */ \
CLEAR_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \ CLEAR_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
/* Disable Bank2 IT */ \ /* Disable Bank2 IT */ \
@@ -647,11 +645,8 @@ typedef struct
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
* @retval The new state of __FLAG__ (SET or RESET). * @retval The new state of __FLAG__ (SET or RESET).
*/ */
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ #define __HAL_FLASH_GET_FLAG(__FLAG__) \
(FLASH->OBR & FLASH_OBR_OPTERR) : \ (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : ((((__FLAG__)&SR_FLAG_MASK) != RESET) ? (FLASH->SR & ((__FLAG__)&SR_FLAG_MASK)) : (FLASH->SR2 & ((__FLAG__) >> 16U))))
((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
(FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
(FLASH->SR2 & ((__FLAG__) >> 16U))))
/** /**
* @brief Clear the specified FLASH flag. * @brief Clear the specified FLASH flag.
@@ -668,21 +663,18 @@ typedef struct
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
* @retval none * @retval none
*/ */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) \
do { \
/* Clear FLASH_FLAG_OPTVERR flag */ \ /* Clear FLASH_FLAG_OPTVERR flag */ \
if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ if ((__FLAG__) == FLASH_FLAG_OPTVERR) { \
{ \
CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
} \ } else { \
else { \
/* Clear Flag in Bank1 */ \ /* Clear Flag in Bank1 */ \
if (((__FLAG__) & SR_FLAG_MASK) != RESET) \ if (((__FLAG__)&SR_FLAG_MASK) != RESET) { \
{ \
FLASH->SR = ((__FLAG__)&SR_FLAG_MASK); \ FLASH->SR = ((__FLAG__)&SR_FLAG_MASK); \
} \ } \
/* Clear Flag in Bank2 */ \ /* Clear Flag in Bank2 */ \
if (((__FLAG__) >> 16U) != RESET) \ if (((__FLAG__) >> 16U) != RESET) { \
{ \
FLASH->SR2 = ((__FLAG__) >> 16U); \ FLASH->SR2 = ((__FLAG__) >> 16U); \
} \ } \
} \ } \
@@ -719,9 +711,7 @@ typedef struct
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
* @retval The new state of __FLAG__ (SET or RESET). * @retval The new state of __FLAG__ (SET or RESET).
*/ */
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : (FLASH->SR & (__FLAG__)))
(FLASH->OBR & FLASH_OBR_OPTERR) : \
(FLASH->SR & (__FLAG__)))
/** /**
* @brief Clear the specified FLASH flag. * @brief Clear the specified FLASH flag.
* @param __FLAG__ specifies the FLASH flags to clear. * @param __FLAG__ specifies the FLASH flags to clear.
@@ -732,13 +722,12 @@ typedef struct
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
* @retval none * @retval none
*/ */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) \
do { \
/* Clear FLASH_FLAG_OPTVERR flag */ \ /* Clear FLASH_FLAG_OPTVERR flag */ \
if ((__FLAG__) == FLASH_FLAG_OPTVERR) \ if ((__FLAG__) == FLASH_FLAG_OPTVERR) { \
{ \
CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
} \ } else { \
else { \
/* Clear Flag in Bank1 */ \ /* Clear Flag in Bank1 */ \
FLASH->SR = (__FLAG__); \ FLASH->SR = (__FLAG__); \
} \ } \

31
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h vendored
View File

@@ -60,8 +60,7 @@ extern "C" {
/** /**
* @brief GPIO Init structure definition * @brief GPIO Init structure definition
*/ */
typedef struct typedef struct {
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured. uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */ This parameter can be any value of @ref GPIO_pins_define */
@@ -78,11 +77,7 @@ typedef struct
/** /**
* @brief GPIO Bit SET and Bit RESET enumeration * @brief GPIO Bit SET and Bit RESET enumeration
*/ */
typedef enum typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState;
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
} GPIO_PinState;
/** /**
* @} * @}
*/ */
@@ -278,22 +273,12 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
*/ */
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(PIN) ((((PIN)&GPIO_PIN_MASK) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_PIN(PIN) ((((PIN)&GPIO_PIN_MASK) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ #define IS_GPIO_MODE(MODE) \
((MODE) == GPIO_MODE_OUTPUT_PP) ||\ (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) \
((MODE) == GPIO_MODE_OUTPUT_OD) ||\ || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) \
((MODE) == GPIO_MODE_AF_PP) ||\ || ((MODE) == GPIO_MODE_ANALOG))
((MODE) == GPIO_MODE_AF_OD) ||\ #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
((MODE) == GPIO_MODE_IT_RISING) ||\ #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN))
((MODE) == GPIO_MODE_IT_FALLING) ||\
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING) ||\
((MODE) == GPIO_MODE_EVT_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
((PULL) == GPIO_PULLDOWN))
/** /**
* @} * @}
*/ */

61
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h vendored
View File

@@ -84,22 +84,11 @@ extern "C" {
#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ #define IS_AFIO_EVENTOUT_PIN(__PIN__) \
((__PIN__) == AFIO_EVENTOUT_PIN_1) || \ (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4) \
((__PIN__) == AFIO_EVENTOUT_PIN_2) || \ || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9) \
((__PIN__) == AFIO_EVENTOUT_PIN_3) || \ || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) \
((__PIN__) == AFIO_EVENTOUT_PIN_4) || \ || ((__PIN__) == AFIO_EVENTOUT_PIN_15))
((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
((__PIN__) == AFIO_EVENTOUT_PIN_15))
/** /**
* @} * @}
*/ */
@@ -114,11 +103,8 @@ extern "C" {
#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ #define IS_AFIO_EVENTOUT_PORT(__PORT__) \
((__PORT__) == AFIO_EVENTOUT_PORT_B) || \ (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))
((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
((__PORT__) == AFIO_EVENTOUT_PORT_E))
/** /**
* @} * @}
*/ */
@@ -825,43 +811,42 @@ extern "C" {
* @{ * @{
*/ */
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : 3U)
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :3U)
#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : 4U)
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :4U)
#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ #define GPIO_GET_INDEX(__GPIOx__) \
((__GPIOx__) == (GPIOB))? 1U :\ (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : ((__GPIOx__) == (GPIOE)) ? 4U : ((__GPIOx__) == (GPIOF)) ? 5U : 6U)
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :\
((__GPIOx__) == (GPIOE))? 4U :\
((__GPIOx__) == (GPIOF))? 5U :6U)
#endif #endif
#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ #define AFIO_REMAP_ENABLE(REMAP_PIN) \
do { \
uint32_t tmpreg = AFIO->MAPR; \
tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \
tmpreg |= REMAP_PIN; \ tmpreg |= REMAP_PIN; \
AFIO->MAPR = tmpreg; \ AFIO->MAPR = tmpreg; \
} while (0U) } while (0U)
#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ #define AFIO_REMAP_DISABLE(REMAP_PIN) \
do { \
uint32_t tmpreg = AFIO->MAPR; \
tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \
tmpreg &= ~REMAP_PIN; \ tmpreg &= ~REMAP_PIN; \
AFIO->MAPR = tmpreg; \ AFIO->MAPR = tmpreg; \
} while (0U) } while (0U)
#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \ #define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) \
do { \
uint32_t tmpreg = AFIO->MAPR; \
tmpreg &= ~REMAP_PIN_MASK; \ tmpreg &= ~REMAP_PIN_MASK; \
tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \
tmpreg |= REMAP_PIN; \ tmpreg |= REMAP_PIN; \
AFIO->MAPR = tmpreg; \ AFIO->MAPR = tmpreg; \
} while (0U) } while (0U)
#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \ #define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) \
do { \
uint32_t tmpreg = AFIO->MAPR; \
tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \ tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
tmpreg |= DBGAFR_SWJCFG; \ tmpreg |= DBGAFR_SWJCFG; \
AFIO->MAPR = tmpreg; \ AFIO->MAPR = tmpreg; \

50
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h vendored
View File

@@ -60,8 +60,7 @@
/** /**
* @brief I2C Configuration Structure definition * @brief I2C Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t ClockSpeed; /*!< Specifies the clock frequency. uint32_t ClockSpeed; /*!< Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */ This parameter must be set to a value lower than 400kHz */
@@ -114,8 +113,7 @@ typedef struct
* 0 : Ready (no Tx operation ongoing) * 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing) * 1 : Busy (Tx operation ongoing)
*/ */
typedef enum typedef enum {
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
@@ -149,8 +147,7 @@ typedef enum
* b3-b2-b1-b0 (not used) * b3-b2-b1-b0 (not used)
* xxxx : Should be set to 0000 * xxxx : Should be set to 0000
*/ */
typedef enum typedef enum {
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
@@ -161,8 +158,7 @@ typedef enum
/** /**
* @brief I2C handle Structure definition * @brief I2C handle Structure definition
*/ */
typedef struct typedef struct {
{
I2C_TypeDef *Instance; /*!< I2C registers base address */ I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */ I2C_InitTypeDef Init; /*!< I2C communication parameters */
@@ -406,8 +402,9 @@ typedef struct
* @arg I2C_FLAG_MSL: Master/Slave flag * @arg I2C_FLAG_MSL: Master/Slave flag
* @retval The new state of __FLAG__ (TRUE or FALSE). * @retval The new state of __FLAG__ (TRUE or FALSE).
*/ */
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) \
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? ((((__HANDLE__)->Instance->SR1) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)) \
: ((((__HANDLE__)->Instance->SR2) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)))
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. /** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
* @param __HANDLE__: specifies the I2C Handle. * @param __HANDLE__: specifies the I2C Handle.
@@ -578,10 +575,11 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__) / 1000000U) #define I2C_FREQRANGE(__PCLK__) ((__PCLK__) / 1000000U)
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__)*300U) / 1000U) + 1U)) #define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__)*300U) / 1000U) + 1U))
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U) ? 4U : I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U)) #define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U) ? 4U : I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9)) #define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) \
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2) ? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ #define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) (((__SPEED__) <= 100000U) ? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) \
: ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U) ? 1U : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) #define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) #define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
@@ -596,25 +594,16 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters /** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
* @{ * @{
*/ */
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || ((CYCLE) == I2C_DUTYCYCLE_16_9))
((CYCLE) == I2C_DUTYCYCLE_16_9)) #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || ((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || ((STRETCH) == I2C_NOSTRETCH_ENABLE))
((ADDRESS) == I2C_DUALADDRESS_ENABLE)) #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || ((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U)) #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U) #define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || ((REQUEST) == I2C_NEXT_FRAME) || ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME))
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))
/** /**
* @} * @}
*/ */
@@ -644,7 +633,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
} }
#endif #endif
#endif /* __STM32F1xx_HAL_I2C_H */ #endif /* __STM32F1xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

18
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h vendored
View File

@@ -60,8 +60,7 @@ extern "C" {
/** /**
* @brief IWDG Init structure definition * @brief IWDG Init structure definition
*/ */
typedef struct typedef struct {
{
uint32_t Prescaler; /*!< Select the prescaler of the IWDG. uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
This parameter can be a value of @ref IWDG_Prescaler */ This parameter can be a value of @ref IWDG_Prescaler */
@@ -73,8 +72,7 @@ typedef struct
/** /**
* @brief IWDG Handle Structure definition * @brief IWDG Handle Structure definition
*/ */
typedef struct typedef struct {
{
IWDG_TypeDef *Instance; /*!< Register base address */ IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
@@ -108,7 +106,6 @@ typedef struct
* @} * @}
*/ */
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{ * @{
@@ -201,13 +198,9 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
* @param __PRESCALER__ IWDG prescaler value * @param __PRESCALER__ IWDG prescaler value
* @retval None * @retval None
*/ */
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ #define IS_IWDG_PRESCALER(__PRESCALER__) \
((__PRESCALER__) == IWDG_PRESCALER_8) || \ (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) \
((__PRESCALER__) == IWDG_PRESCALER_16) || \ || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128) || ((__PRESCALER__) == IWDG_PRESCALER_256))
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
/** /**
* @brief Check IWDG reload value. * @brief Check IWDG reload value.
@@ -228,7 +221,6 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

44
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h vendored
View File

@@ -61,8 +61,7 @@
/** /**
* @brief PWR PVD configuration structure definition * @brief PWR PVD configuration structure definition
*/ */
typedef struct typedef struct {
{
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level */ This parameter can be a value of @ref PWR_PVD_detection_level */
@@ -70,12 +69,10 @@ typedef struct
This parameter can be a value of @ref PWR_PVD_Mode */ This parameter can be a value of @ref PWR_PVD_Mode */
} PWR_PVDTypeDef; } PWR_PVDTypeDef;
/** /**
* @} * @}
*/ */
/* Internal constants --------------------------------------------------------*/ /* Internal constants --------------------------------------------------------*/
/** @addtogroup PWR_Private_Constants /** @addtogroup PWR_Private_Constants
@@ -88,7 +85,6 @@ typedef struct
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants /** @defgroup PWR_Exported_Constants PWR Exported Constants
@@ -126,7 +122,6 @@ typedef struct
* @} * @}
*/ */
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{ * @{
*/ */
@@ -174,7 +169,6 @@ typedef struct
#define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO #define PWR_FLAG_PVDO PWR_CSR_PVDO
/** /**
* @} * @}
*/ */
@@ -237,21 +231,18 @@ typedef struct
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
/** /**
* @brief PVD EXTI line configuration: set falling edge trigger. * @brief PVD EXTI line configuration: set falling edge trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Disable the PVD Extended Interrupt Falling Trigger. * @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief PVD EXTI line configuration: set rising edge trigger. * @brief PVD EXTI line configuration: set rising edge trigger.
* @retval None. * @retval None.
@@ -269,16 +260,18 @@ typedef struct
* @brief PVD EXTI line configuration: set rising & falling edge trigger. * @brief PVD EXTI line configuration: set rising & falling edge trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
/** /**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* This parameter can be: * This parameter can be:
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/** /**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not. * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
@@ -305,21 +298,17 @@ typedef struct
/** @defgroup PWR_Private_Macros PWR Private Macros /** @defgroup PWR_Private_Macros PWR Private Macros
* @{ * @{
*/ */
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ #define IS_PWR_PVD_LEVEL(LEVEL) \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) \
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) \
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_PVD_MODE_NORMAL))
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
@@ -329,8 +318,6 @@ typedef struct
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions /** @addtogroup PWR_Exported_Functions PWR Exported Functions
@@ -374,8 +361,6 @@ void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void); void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void); void HAL_PWR_DisableSEVOnPend(void);
void HAL_PWR_PVD_IRQHandler(void); void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void); void HAL_PWR_PVDCallback(void);
/** /**
@@ -398,7 +383,6 @@ void HAL_PWR_PVDCallback(void);
} }
#endif #endif
#endif /* __STM32F1xx_HAL_PWR_H */ #endif /* __STM32F1xx_HAL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

168
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h vendored
View File

@@ -61,8 +61,7 @@
/** /**
* @brief RCC PLL configuration structure definition * @brief RCC PLL configuration structure definition
*/ */
typedef struct typedef struct {
{
uint32_t PLLState; /*!< PLLState: The new state of the PLL. uint32_t PLLState; /*!< PLLState: The new state of the PLL.
This parameter can be a value of @ref RCC_PLL_Config */ This parameter can be a value of @ref RCC_PLL_Config */
@@ -76,8 +75,7 @@ typedef struct
/** /**
* @brief RCC System, AHB and APB busses clock configuration structure definition * @brief RCC System, AHB and APB busses clock configuration structure definition
*/ */
typedef struct typedef struct {
{
uint32_t ClockType; /*!< The clock to be configured. uint32_t ClockType; /*!< The clock to be configured.
This parameter can be a value of @ref RCC_System_Clock_Type */ This parameter can be a value of @ref RCC_System_Clock_Type */
@@ -255,7 +253,6 @@ typedef struct
* @} * @}
*/ */
/** @defgroup RCC_MCO_Index MCO Index /** @defgroup RCC_MCO_Index MCO Index
* @{ * @{
*/ */
@@ -335,7 +332,8 @@ typedef struct
* using it. * using it.
* @{ * @{
*/ */
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ #define __HAL_RCC_DMA1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -343,7 +341,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ #define __HAL_RCC_SRAM_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -351,7 +350,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ #define __HAL_RCC_FLITF_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN); \ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -359,7 +359,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_CRC_CLK_ENABLE() do { \ #define __HAL_RCC_CRC_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -404,7 +405,8 @@ typedef struct
* using it. * using it.
* @{ * @{
*/ */
#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ #define __HAL_RCC_TIM2_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -412,7 +414,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ #define __HAL_RCC_TIM3_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -420,7 +423,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ #define __HAL_RCC_WWDG_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -428,7 +432,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_USART2_CLK_ENABLE() do { \ #define __HAL_RCC_USART2_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -436,7 +441,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ #define __HAL_RCC_I2C1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -444,7 +450,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_BKP_CLK_ENABLE() do { \ #define __HAL_RCC_BKP_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN); \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -452,7 +459,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \ #define __HAL_RCC_PWR_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -507,7 +515,8 @@ typedef struct
* using it. * using it.
* @{ * @{
*/ */
#define __HAL_RCC_AFIO_CLK_ENABLE() do { \ #define __HAL_RCC_AFIO_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN); \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -515,7 +524,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ #define __HAL_RCC_GPIOA_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN); \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -523,7 +533,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ #define __HAL_RCC_GPIOB_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN); \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -531,7 +542,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ #define __HAL_RCC_GPIOC_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN); \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -539,7 +551,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ #define __HAL_RCC_GPIOD_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -547,7 +560,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ #define __HAL_RCC_ADC1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -555,7 +569,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ #define __HAL_RCC_TIM1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -563,7 +578,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ #define __HAL_RCC_SPI1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -571,7 +587,8 @@ typedef struct
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while (0U) } while (0U)
#define __HAL_RCC_USART1_CLK_ENABLE() do { \ #define __HAL_RCC_USART1_CLK_ENABLE() \
do { \
__IO uint32_t tmpreg; \ __IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
/* Delay after an RCC peripheral clock enabling */ \ /* Delay after an RCC peripheral clock enabling */ \
@@ -709,8 +726,7 @@ typedef struct
* (default is RCC_HSICALIBRATION_DEFAULT). * (default is RCC_HSICALIBRATION_DEFAULT).
* This parameter must be a number between 0 and 0x1F. * This parameter must be a number between 0 and 0x1F.
*/ */
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
/** /**
* @} * @}
@@ -766,22 +782,15 @@ typedef struct
*/ */
#define __HAL_RCC_HSE_CONFIG(__STATE__) \ #define __HAL_RCC_HSE_CONFIG(__STATE__) \
do { \ do { \
if ((__STATE__) == RCC_HSE_ON) \ if ((__STATE__) == RCC_HSE_ON) { \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEON); \ SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \ } else if ((__STATE__) == RCC_HSE_OFF) { \
else if ((__STATE__) == RCC_HSE_OFF) \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \ } else if ((__STATE__) == RCC_HSE_BYPASS) { \
else if ((__STATE__) == RCC_HSE_BYPASS) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
SET_BIT(RCC->CR, RCC_CR_HSEON); \ SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \ } else { \
else \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \ } \
@@ -814,22 +823,15 @@ typedef struct
*/ */
#define __HAL_RCC_LSE_CONFIG(__STATE__) \ #define __HAL_RCC_LSE_CONFIG(__STATE__) \
do { \ do { \
if ((__STATE__) == RCC_LSE_ON) \ if ((__STATE__) == RCC_LSE_ON) { \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \ } else if ((__STATE__) == RCC_LSE_OFF) { \
else if ((__STATE__) == RCC_LSE_OFF) \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \ } else if ((__STATE__) == RCC_LSE_BYPASS) { \
else if ((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \ } else { \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \ } \
@@ -886,8 +888,7 @@ typedef struct
* @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
* *
*/ */
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL), ((__RCC_PLLSOURCE__) | (__PLLMUL__)))
MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
/** @brief Get oscillator clock selected as PLL input clock /** @brief Get oscillator clock selected as PLL input clock
* @retval The clock source used for PLL entry. The returned value can be one * @retval The clock source used for PLL entry. The returned value can be one
@@ -913,8 +914,7 @@ typedef struct
* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
*/ */
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
/** @brief Macro to get the clock source used as system clock. /** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one * @retval The clock source used as system clock. The returned value can be one
@@ -965,9 +965,7 @@ typedef struct
*/ */
#endif #endif
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
/** /**
* @} * @}
@@ -1143,9 +1141,7 @@ typedef struct
* @arg @ref RCC_FLAG_LPWRRST Low Power reset. * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
* @retval The new state of __FLAG__ (TRUE or FALSE). * @retval The new state of __FLAG__ (TRUE or FALSE).
*/ */
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) & (1U << ((__FLAG__)&RCC_FLAG_MASK)))
((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
/** /**
* @} * @}
@@ -1329,47 +1325,30 @@ void HAL_RCC_CSSCallback(void);
* @} * @}
*/ */
#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))
((__SOURCE__) == RCC_PLLSOURCE_HSE)) #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS))
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
((__HSE__) == RCC_HSE_BYPASS))
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
((__LSE__) == RCC_LSE_BYPASS))
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
((__PLL__) == RCC_PLL_ON))
#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ #define IS_RCC_CLOCKTYPE(CLK) \
(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ ((((CLK)&RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK)&RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK)&RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \
(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ || (((CLK)&RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ #define IS_RCC_HCLK(__HCLK__) \
((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) \
#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))
((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))
((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
((__HCLK__) == RCC_SYSCLK_DIV512))
#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
((__PCLK__) == RCC_HCLK_DIV16))
#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ #define IS_RCC_RTCCLKSOURCE(__SOURCE__) \
((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
/** /**
* @} * @}
@@ -1390,4 +1369,3 @@ void HAL_RCC_CSSCallback(void);
#endif /* __STM32F1xx_HAL_RCC_H */ #endif /* __STM32F1xx_HAL_RCC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

440
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h vendored
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File diff suppressed because it is too large Load Diff

357
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h vendored
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@@ -59,8 +59,7 @@
/** /**
* @brief TIM Time base Configuration Structure definition * @brief TIM Time base Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
@@ -90,8 +89,7 @@ typedef struct
/** /**
* @brief TIM Output Compare Configuration Structure definition * @brief TIM Output Compare Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t OCMode; /*!< Specifies the TIM mode. uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
@@ -109,7 +107,6 @@ typedef struct
This parameter can be a value of @ref TIM_Output_Fast_State This parameter can be a value of @ref TIM_Output_Fast_State
@note This parameter is valid only in PWM1 and PWM2 mode. */ @note This parameter is valid only in PWM1 and PWM2 mode. */
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */ @note This parameter is valid only for TIM1 and TIM8. */
@@ -122,8 +119,7 @@ typedef struct
/** /**
* @brief TIM One Pulse Mode Configuration Structure definition * @brief TIM One Pulse Mode Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t OCMode; /*!< Specifies the TIM mode. uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
@@ -155,12 +151,10 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_OnePulse_InitTypeDef; } TIM_OnePulse_InitTypeDef;
/** /**
* @brief TIM Input Capture Configuration Structure definition * @brief TIM Input Capture Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -177,8 +171,7 @@ typedef struct
/** /**
* @brief TIM Encoder Configuration Structure definition * @brief TIM Encoder Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Encoder_Mode */ This parameter can be a value of @ref TIM_Encoder_Mode */
@@ -207,12 +200,10 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_Encoder_InitTypeDef; } TIM_Encoder_InitTypeDef;
/** /**
* @brief TIM Clock Configuration Handle Structure definition * @brief TIM Clock Configuration Handle Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t ClockSource; /*!< TIM clock sources uint32_t ClockSource; /*!< TIM clock sources
This parameter can be a value of @ref TIM_Clock_Source */ This parameter can be a value of @ref TIM_Clock_Source */
uint32_t ClockPolarity; /*!< TIM clock polarity uint32_t ClockPolarity; /*!< TIM clock polarity
@@ -226,8 +217,7 @@ typedef struct
/** /**
* @brief TIM Clear Input Configuration Handle Structure definition * @brief TIM Clear Input Configuration Handle Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t ClearInputState; /*!< TIM clear Input state uint32_t ClearInputState; /*!< TIM clear Input state
This parameter can be ENABLE or DISABLE */ This parameter can be ENABLE or DISABLE */
uint32_t ClearInputSource; /*!< TIM clear Input sources uint32_t ClearInputSource; /*!< TIM clear Input sources
@@ -260,8 +250,7 @@ typedef struct {
/** /**
* @brief HAL State structures definition * @brief HAL State structures definition
*/ */
typedef enum typedef enum {
{
HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
@@ -272,8 +261,7 @@ typedef enum
/** /**
* @brief HAL Active channel structures definition * @brief HAL Active channel structures definition
*/ */
typedef enum typedef enum {
{
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
@@ -284,8 +272,7 @@ typedef enum
/** /**
* @brief TIM Time Base Handle Structure definition * @brief TIM Time Base Handle Structure definition
*/ */
typedef struct typedef struct {
{
TIM_TypeDef * Instance; /*!< Register base address */ TIM_TypeDef * Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
@@ -468,9 +455,11 @@ typedef struct
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{ * @{
*/ */
#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be #define TIM_ICSELECTION_DIRECTTI \
(TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
connected to IC1, IC2, IC3 or IC4, respectively */ connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be #define TIM_ICSELECTION_INDIRECTTI \
(TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
connected to IC2, IC1, IC4 or IC3, respectively */ connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/** /**
@@ -887,225 +876,123 @@ typedef struct
* @{ * @{
*/ */
#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ #define IS_TIM_COUNTER_MODE(MODE) \
((MODE) == TIM_COUNTERMODE_DOWN) || \ (((MODE) == TIM_COUNTERMODE_UP) || ((MODE) == TIM_COUNTERMODE_DOWN) || ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \
((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ || ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || ((DIV) == TIM_CLOCKDIVISION_DIV2) || ((DIV) == TIM_CLOCKDIVISION_DIV4))
((DIV) == TIM_CLOCKDIVISION_DIV2) || \
((DIV) == TIM_CLOCKDIVISION_DIV4))
#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2))
((MODE) == TIM_OCMODE_PWM2))
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ #define IS_TIM_OC_MODE(MODE) \
((MODE) == TIM_OCMODE_ACTIVE) || \ (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE) || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_FORCED_ACTIVE) \
((MODE) == TIM_OCMODE_INACTIVE) || \ || ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
((MODE) == TIM_OCMODE_TOGGLE) || \
((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
((MODE) == TIM_OCMODE_FORCED_INACTIVE))
#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || ((STATE) == TIM_OCFAST_ENABLE))
((STATE) == TIM_OCFAST_ENABLE))
#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || ((POLARITY) == TIM_OCPOLARITY_LOW))
((POLARITY) == TIM_OCPOLARITY_LOW))
#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || ((POLARITY) == TIM_OCNPOLARITY_LOW))
((POLARITY) == TIM_OCNPOLARITY_LOW))
#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || ((STATE) == TIM_OCIDLESTATE_RESET))
((STATE) == TIM_OCIDLESTATE_RESET))
#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || ((STATE) == TIM_OCNIDLESTATE_RESET))
((STATE) == TIM_OCNIDLESTATE_RESET))
#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3) || ((CHANNEL) == TIM_CHANNEL_4) || ((CHANNEL) == TIM_CHANNEL_ALL))
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_ALL))
#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2))
((CHANNEL) == TIM_CHANNEL_2))
#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || ((CHANNEL) == TIM_CHANNEL_2) || ((CHANNEL) == TIM_CHANNEL_3))
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || ((SELECTION) == TIM_ICSELECTION_TRC))
((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
((SELECTION) == TIM_ICSELECTION_TRC))
#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || ((PRESCALER) == TIM_ICPSC_DIV2) || ((PRESCALER) == TIM_ICPSC_DIV4) || ((PRESCALER) == TIM_ICPSC_DIV8))
((PRESCALER) == TIM_ICPSC_DIV2) || \
((PRESCALER) == TIM_ICPSC_DIV4) || \
((PRESCALER) == TIM_ICPSC_DIV8))
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPETITIVE))
((MODE) == TIM_OPMODE_REPETITIVE))
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || ((MODE) == TIM_ENCODERMODE_TI2) || ((MODE) == TIM_ENCODERMODE_TI12))
((MODE) == TIM_ENCODERMODE_TI2) || \
((MODE) == TIM_ENCODERMODE_TI12))
#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE)&0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE)&0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE)&0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE)&0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ #define IS_TIM_CLOCKSOURCE(CLOCK) \
((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || ((CLOCK) == TIM_CLOCKSOURCE_ITR2) \
((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ || ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || ((CLOCK) == TIM_CLOCKSOURCE_TI1) || ((CLOCK) == TIM_CLOCKSOURCE_TI2) || ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ #define IS_TIM_CLOCKPOLARITY(POLARITY) \
((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \
((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ || ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ #define IS_TIM_CLOCKPRESCALER(PRESCALER) \
((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) \
((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || ((STATE) == TIM_OSSR_DISABLE))
((STATE) == TIM_OSSR_DISABLE))
#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || ((STATE) == TIM_OSSI_DISABLE))
((STATE) == TIM_OSSI_DISABLE))
#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || ((LEVEL) == TIM_LOCKLEVEL_1) || ((LEVEL) == TIM_LOCKLEVEL_2) || ((LEVEL) == TIM_LOCKLEVEL_3))
((LEVEL) == TIM_LOCKLEVEL_1) || \
((LEVEL) == TIM_LOCKLEVEL_2) || \
((LEVEL) == TIM_LOCKLEVEL_3))
#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || ((STATE) == TIM_BREAK_DISABLE))
((STATE) == TIM_BREAK_DISABLE))
#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
((POLARITY) == TIM_BREAKPOLARITY_HIGH))
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ #define IS_TIM_TRGO_SOURCE(SOURCE) \
((SOURCE) == TIM_TRGO_ENABLE) || \ (((SOURCE) == TIM_TRGO_RESET) || ((SOURCE) == TIM_TRGO_ENABLE) || ((SOURCE) == TIM_TRGO_UPDATE) || ((SOURCE) == TIM_TRGO_OC1) || ((SOURCE) == TIM_TRGO_OC1REF) || ((SOURCE) == TIM_TRGO_OC2REF) \
((SOURCE) == TIM_TRGO_UPDATE) || \ || ((SOURCE) == TIM_TRGO_OC3REF) || ((SOURCE) == TIM_TRGO_OC4REF))
((SOURCE) == TIM_TRGO_OC1) || \
((SOURCE) == TIM_TRGO_OC1REF) || \
((SOURCE) == TIM_TRGO_OC2REF) || \
((SOURCE) == TIM_TRGO_OC3REF) || \
((SOURCE) == TIM_TRGO_OC4REF))
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ #define IS_TIM_SLAVE_MODE(MODE) \
((MODE) == TIM_SLAVEMODE_GATED) || \ (((MODE) == TIM_SLAVEMODE_DISABLE) || ((MODE) == TIM_SLAVEMODE_GATED) || ((MODE) == TIM_SLAVEMODE_RESET) || ((MODE) == TIM_SLAVEMODE_TRIGGER) || ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
((MODE) == TIM_SLAVEMODE_RESET) || \
((MODE) == TIM_SLAVEMODE_TRIGGER) || \
((MODE) == TIM_SLAVEMODE_EXTERNAL1))
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ #define IS_TIM_TRIGGER_SELECTION(SELECTION) \
((SELECTION) == TIM_TS_ITR1) || \ (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3) || ((SELECTION) == TIM_TS_TI1F_ED) || ((SELECTION) == TIM_TS_TI1FP1) \
((SELECTION) == TIM_TS_ITR2) || \ || ((SELECTION) == TIM_TS_TI2FP2) || ((SELECTION) == TIM_TS_ETRF))
((SELECTION) == TIM_TS_ITR3) || \
((SELECTION) == TIM_TS_TI1F_ED) || \
((SELECTION) == TIM_TS_TI1FP1) || \
((SELECTION) == TIM_TS_TI2FP2) || \
((SELECTION) == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) \
((SELECTION) == TIM_TS_ITR1) || \ (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3) || ((SELECTION) == TIM_TS_NONE))
((SELECTION) == TIM_TS_ITR2) || \
((SELECTION) == TIM_TS_ITR3) || \
((SELECTION) == TIM_TS_NONE))
#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ #define IS_TIM_TRIGGERPOLARITY(POLARITY) \
((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED) || ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || ((POLARITY) == TIM_TRIGGERPOLARITY_RISING) || ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING) \
((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ || ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE))
((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ #define IS_TIM_TRIGGERPRESCALER(PRESCALER) \
((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ #define IS_TIM_DMA_BASE(BASE) \
((BASE) == TIM_DMABASE_CR2) || \ (((BASE) == TIM_DMABASE_CR1) || ((BASE) == TIM_DMABASE_CR2) || ((BASE) == TIM_DMABASE_SMCR) || ((BASE) == TIM_DMABASE_DIER) || ((BASE) == TIM_DMABASE_SR) || ((BASE) == TIM_DMABASE_EGR) \
((BASE) == TIM_DMABASE_SMCR) || \ || ((BASE) == TIM_DMABASE_CCMR1) || ((BASE) == TIM_DMABASE_CCMR2) || ((BASE) == TIM_DMABASE_CCER) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC) || ((BASE) == TIM_DMABASE_ARR) \
((BASE) == TIM_DMABASE_DIER) || \ || ((BASE) == TIM_DMABASE_RCR) || ((BASE) == TIM_DMABASE_CCR1) || ((BASE) == TIM_DMABASE_CCR2) || ((BASE) == TIM_DMABASE_CCR3) || ((BASE) == TIM_DMABASE_CCR4) || ((BASE) == TIM_DMABASE_BDTR) \
((BASE) == TIM_DMABASE_SR) || \ || ((BASE) == TIM_DMABASE_DCR))
((BASE) == TIM_DMABASE_EGR) || \
((BASE) == TIM_DMABASE_CCMR1) || \
((BASE) == TIM_DMABASE_CCMR2) || \
((BASE) == TIM_DMABASE_CCER) || \
((BASE) == TIM_DMABASE_CNT) || \
((BASE) == TIM_DMABASE_PSC) || \
((BASE) == TIM_DMABASE_ARR) || \
((BASE) == TIM_DMABASE_RCR) || \
((BASE) == TIM_DMABASE_CCR1) || \
((BASE) == TIM_DMABASE_CCR2) || \
((BASE) == TIM_DMABASE_CCR3) || \
((BASE) == TIM_DMABASE_CCR4) || \
((BASE) == TIM_DMABASE_BDTR) || \
((BASE) == TIM_DMABASE_DCR))
#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ #define IS_TIM_DMA_LENGTH(LENGTH) \
((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \
((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ || ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \
((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ || ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \
((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ || ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \
((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ || ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
@@ -1116,10 +1003,10 @@ typedef struct
* @retval None * @retval None
*/ */
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
/** @brief Reset TIM IC prescaler /** @brief Reset TIM IC prescaler
* @param __HANDLE__: TIM handle * @param __HANDLE__: TIM handle
@@ -1127,11 +1014,10 @@ typedef struct
* @retval None * @retval None
*/ */
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ (((__CHANNEL__) == TIM_CHANNEL_1) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
/** @brief Set TIM IC polarity /** @brief Set TIM IC polarity
* @param __HANDLE__: TIM handle * @param __HANDLE__: TIM handle
@@ -1140,10 +1026,10 @@ typedef struct
* @retval None * @retval None
*/ */
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) \
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P))) : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
/** @brief Reset TIM IC polarity /** @brief Reset TIM IC polarity
* @param __HANDLE__: TIM handle * @param __HANDLE__: TIM handle
@@ -1151,10 +1037,10 @@ typedef struct
* @retval None * @retval None
*/ */
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t) ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t) ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t) ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) \
((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) : ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
/** /**
* @} * @}
@@ -1207,10 +1093,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat
*/ */
#define __HAL_TIM_DISABLE(__HANDLE__) \ #define __HAL_TIM_DISABLE(__HANDLE__) \
do { \ do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) { \
{ \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) { \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \ } \
} \ } \
@@ -1225,10 +1109,8 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat
*/ */
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \ do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) { \
{ \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) { \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \ } \
} \ } \
@@ -1396,8 +1278,7 @@ mode.
* @param __COMPARE__: specifies the Capture Compare register new value. * @param __COMPARE__: specifies the Capture Compare register new value.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
/** /**
* @brief Gets the TIM Capture Compare Register value on runtime * @brief Gets the TIM Capture Compare Register value on runtime
@@ -1410,8 +1291,7 @@ mode.
* @arg TIM_CHANNEL_4: get capture/compare 4 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/ */
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
/** /**
* @brief Sets the TIM Counter Register value on runtime. * @brief Sets the TIM Counter Register value on runtime.
@@ -1426,8 +1306,7 @@ mode.
* @param __HANDLE__: TIM handle. * @param __HANDLE__: TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/ */
#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
((__HANDLE__)->Instance->CNT)
/** /**
* @brief Sets the TIM Autoreload Register value on runtime without calling * @brief Sets the TIM Autoreload Register value on runtime without calling
@@ -1447,8 +1326,7 @@ mode.
* @param __HANDLE__: TIM handle. * @param __HANDLE__: TIM handle.
* @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/ */
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
((__HANDLE__)->Instance->ARR)
/** /**
* @brief Sets the TIM Clock Division value on runtime without calling * @brief Sets the TIM Clock Division value on runtime without calling
@@ -1476,8 +1354,7 @@ mode.
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/ */
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/** /**
* @brief Sets the TIM Input Capture prescaler on runtime without calling * @brief Sets the TIM Input Capture prescaler on runtime without calling
@@ -1519,10 +1396,10 @@ mode.
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
*/ */
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ (((__CHANNEL__) == TIM_CHANNEL_1) \
((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \
(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
/** /**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
@@ -1532,8 +1409,7 @@ mode.
* enabled) * enabled)
* @retval None * @retval None
*/ */
#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= (TIM_CR1_URS))
((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
/** /**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
@@ -1546,8 +1422,7 @@ mode.
* (+) Update generation through the slave mode controller * (+) Update generation through the slave mode controller
* @retval None * @retval None
*/ */
#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_URS))
((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
/** /**
* @brief Sets the TIM Capture x input polarity on runtime. * @brief Sets the TIM Capture x input polarity on runtime.
@@ -1730,11 +1605,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);

45
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h vendored
View File

@@ -57,13 +57,11 @@
* @{ * @{
*/ */
/** /**
* @brief TIM Hall sensor Configuration Structure definition * @brief TIM Hall sensor Configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -77,16 +75,12 @@ typedef struct
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef; } TIM_HallSensor_InitTypeDef;
#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#if defined (STM32F100xB) || defined (STM32F100xE) || \
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** /**
* @brief TIM Break and Dead time configuration Structure definition * @brief TIM Break and Dead time configuration Structure definition
*/ */
typedef struct typedef struct {
{
uint32_t OffStateRunMode; /*!< TIM off state in run mode uint32_t OffStateRunMode; /*!< TIM off state in run mode
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
@@ -122,9 +116,7 @@ typedef struct {
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
* @{ * @{
*/ */
@@ -157,10 +149,10 @@ typedef struct {
* @retval None * @retval None
*/ */
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ (((__CHANNEL__) == TIM_CHANNEL_1) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
/** /**
* @brief Resets the TIM Output compare preload. * @brief Resets the TIM Output compare preload.
@@ -174,10 +166,10 @@ typedef struct {
* @retval None * @retval None
*/ */
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) \
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) \
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) \
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) : ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions /** @addtogroup TIMEx_Exported_Functions
@@ -207,9 +199,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
* @} * @}
*/ */
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @addtogroup TIMEx_Exported_Functions_Group2 /** @addtogroup TIMEx_Exported_Functions_Group2
* @{ * @{
@@ -270,9 +260,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* @{ * @{
*/ */
/* Extended Control functions ************************************************/ /* Extended Control functions ************************************************/
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
@@ -295,9 +283,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
* @} * @}
*/ */
#if defined (STM32F100xB) || defined (STM32F100xE) || \ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
defined (STM32F105xC) || defined (STM32F107xC)
/** @addtogroup TIMEx_Exported_Functions_Group7 /** @addtogroup TIMEx_Exported_Functions_Group7
* @{ * @{
*/ */
@@ -337,7 +323,6 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
} }
#endif #endif
#endif /* __STM32F1xx_HAL_TIM_EX_H */ #endif /* __STM32F1xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

33
source/Core/BSP/Miniware/portmacro.h
View File

@@ -88,7 +88,9 @@ typedef uint32_t TickType_t;
#define portNVIC_INT_CTRL_REG (*((volatile uint32_t *)0xe000ed04)) #define portNVIC_INT_CTRL_REG (*((volatile uint32_t *)0xe000ed04))
#define portNVIC_PENDSVSET_BIT (1UL << 28UL) #define portNVIC_PENDSVSET_BIT (1UL << 28UL)
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD() #define portEND_SWITCHING_ISR(xSwitchRequired) \
if (xSwitchRequired != pdFALSE) \
portYIELD()
#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x) #define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@@ -126,8 +128,7 @@ extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Generic helper function. */ /* Generic helper function. */
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( __attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros(uint32_t ulBitmap) {
uint32_t ulBitmap) {
uint8_t ucReturn; uint8_t ucReturn;
__asm volatile("clz %0, %1" : "=r"(ucReturn) : "r"(ulBitmap) : "memory"); __asm volatile("clz %0, %1" : "=r"(ucReturn) : "r"(ulBitmap) : "memory");
@@ -188,14 +189,13 @@ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) {
portFORCE_INLINE static void vPortRaiseBASEPRI(void) { portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
uint32_t ulNewBASEPRI; uint32_t ulNewBASEPRI;
__asm volatile __asm volatile(" mov %0, %1 \n"
(
" mov %0, %1 \n"
" msr basepri, %0 \n" " msr basepri, %0 \n"
" isb \n" " isb \n"
" dsb \n" " dsb \n"
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" : "=r"(ulNewBASEPRI)
); : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
: "memory");
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@@ -203,15 +203,14 @@ portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) { portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) {
uint32_t ulOriginalBASEPRI, ulNewBASEPRI; uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile __asm volatile(" mrs %0, basepri \n"
(
" mrs %0, basepri \n"
" mov %1, %2 \n" " mov %1, %2 \n"
" msr basepri, %1 \n" " msr basepri, %1 \n"
" isb \n" " isb \n"
" dsb \n" " dsb \n"
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" : "=r"(ulOriginalBASEPRI), "=r"(ulNewBASEPRI)
); : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
: "memory");
/* This return will not be reached but is necessary to prevent compiler /* This return will not be reached but is necessary to prevent compiler
warnings. */ warnings. */
@@ -219,12 +218,7 @@ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) {
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { __asm volatile(" msr basepri, %0 " ::"r"(ulNewMaskValue) : "memory"); }
__asm volatile
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
);
}
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#define portMEMORY_BARRIER() __asm volatile("" ::: "memory") #define portMEMORY_BARRIER() __asm volatile("" ::: "memory")
@@ -234,4 +228,3 @@ portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) {
#endif #endif
#endif /* PORTMACRO_H */ #endif /* PORTMACRO_H */

5
source/Core/BSP/Pine64/FreeRTOSConfig.h
View File

@@ -1,7 +1,7 @@
#ifndef FREERTOS_CONFIG_H #ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H
#include <stdint.h>
#include "nuclei_sdk_soc.h" #include "nuclei_sdk_soc.h"
#include <stdint.h>
// RISC-V configuration // RISC-V configuration
#define USER_MODE_TASKS 0 #define USER_MODE_TASKS 0
@@ -67,8 +67,7 @@
/* Define to trap errors during development. */ /* Define to trap errors during development. */
#define configASSERT(x) \ #define configASSERT(x) \
if ((x) == 0) \ if ((x) == 0) { \
{ \
taskDISABLE_INTERRUPTS(); \ taskDISABLE_INTERRUPTS(); \
for (;;) \ for (;;) \
; \ ; \

1
source/Core/BSP/Pine64/Pins.h
View File

@@ -35,7 +35,6 @@
#define SDA_Pin BIT(7) #define SDA_Pin BIT(7)
#define SDA_GPIO_Port GPIOB #define SDA_GPIO_Port GPIOB
#define USB_DM_Pin BIT(11) #define USB_DM_Pin BIT(11)
#define USB_DM_LOW_GPIO_Port GPIOA #define USB_DM_LOW_GPIO_Port GPIOA

34
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_compatiable.h vendored
View File

@@ -70,8 +70,7 @@
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __SSAT(val, sat) __RV_SCLIP32((val), (sat - 1)) #define __SSAT(val, sat) __RV_SCLIP32((val), (sat - 1))
#else #else
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) {
{
if ((sat >= 1U) && (sat <= 32U)) { if ((sat >= 1U) && (sat <= 32U)) {
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max; const int32_t min = -1 - max;
@@ -95,8 +94,7 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __USAT(val, sat) __RV_UCLIP32((val), (sat - 1)) #define __USAT(val, sat) __RV_UCLIP32((val), (sat - 1))
#else #else
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) {
{
if (sat <= 31U) { if (sat <= 31U) {
const uint32_t max = ((1U << sat) - 1U); const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max) { if (val > (int32_t)max) {
@@ -117,14 +115,10 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
* \param [in] value Value to reverse * \param [in] value Value to reverse
* \return Reversed value * \return Reversed value
*/ */
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) {
{
uint32_t result; uint32_t result;
result = ((value & 0xff000000) >> 24) result = ((value & 0xff000000) >> 24) | ((value & 0x00ff0000) >> 8) | ((value & 0x0000ff00) << 8) | ((value & 0x000000ff) << 24);
| ((value & 0x00ff0000) >> 8 )
| ((value & 0x0000ff00) << 8 )
| ((value & 0x000000ff) << 24);
return result; return result;
} }
@@ -135,13 +129,9 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
* \param [in] value Value to reverse * \param [in] value Value to reverse
* \return Reversed value * \return Reversed value
*/ */
__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) {
{
uint32_t result; uint32_t result;
result = ((value & 0xff000000) >> 8) result = ((value & 0xff000000) >> 8) | ((value & 0x00ff00000) << 8) | ((value & 0x0000ff00) >> 8) | ((value & 0x000000ff) << 8);
| ((value & 0x00ff00000) << 8 )
| ((value & 0x0000ff00) >> 8 )
| ((value & 0x000000ff) << 8) ;
return result; return result;
} }
@@ -154,8 +144,7 @@ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
* \param [in] value Value to reverse * \param [in] value Value to reverse
* \return Reversed value * \return Reversed value
*/ */
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) {
{
int16_t result; int16_t result;
result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8); result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8);
return result; return result;
@@ -169,8 +158,7 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
* \param [in] op2 Number of Bits to rotate(0-31) * \param [in] op2 Number of Bits to rotate(0-31)
* \return Rotated value * \return Rotated value
*/ */
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) {
{
op2 = op2 & 0x1F; op2 = op2 & 0x1F;
if (op2 == 0U) { if (op2 == 0U) {
return op1; return op1;
@@ -187,8 +175,7 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __RBIT(value) __RV_BITREVI((value), 31) #define __RBIT(value) __RV_BITREVI((value), 31)
#else #else
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) {
{
uint32_t result; uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
@@ -212,8 +199,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __CLZ(data) __RV_CLZ32(data) #define __CLZ(data) __RV_CLZ32(data)
#else #else
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) {
{
uint8_t ret = 0; uint8_t ret = 0;
uint32_t temp = ~data; uint32_t temp = ~data;
while (temp & 0x80000000) { while (temp & 0x80000000) {

301
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_base.h vendored
View File

@@ -22,8 +22,8 @@
* @file core_feature_base.h * @file core_feature_base.h
* @brief Base core feature API for Nuclei N/NX Core * @brief Base core feature API for Nuclei N/NX Core
*/ */
#include <stdint.h>
#include "riscv_encoding.h" #include "riscv_encoding.h"
#include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -232,7 +232,6 @@ typedef union {
rv_csr_t d; /*!< Type used for csr data access */ rv_csr_t d; /*!< Type used for csr data access */
} CSR_MMISCCTRL_Type; } CSR_MMISCCTRL_Type;
/** /**
* \brief Union type to access MSAVESTATUS configure register. * \brief Union type to access MSAVESTATUS configure register.
*/ */
@@ -269,7 +268,6 @@ typedef union {
* @{ * @{
*/ */
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/** /**
@@ -285,10 +283,7 @@ typedef union {
#define __RV_CSR_SWAP(csr, val) \ #define __RV_CSR_SWAP(csr, val) \
({ \ ({ \
register rv_csr_t __v = (unsigned long)(val); \ register rv_csr_t __v = (unsigned long)(val); \
__ASM volatile("csrrw %0, " STRINGIFY(csr) ", %1" \ __ASM volatile("csrrw %0, " STRINGIFY(csr) ", %1" : "=r"(__v) : "rK"(__v) : "memory"); \
: "=r"(__v) \
: "rK"(__v) \
: "memory"); \
__v; \ __v; \
}) })
@@ -303,10 +298,7 @@ typedef union {
#define __RV_CSR_READ(csr) \ #define __RV_CSR_READ(csr) \
({ \ ({ \
register rv_csr_t __v; \ register rv_csr_t __v; \
__ASM volatile("csrr %0, " STRINGIFY(csr) \ __ASM volatile("csrr %0, " STRINGIFY(csr) : "=r"(__v) : : "memory"); \
: "=r"(__v) \
: \
: "memory"); \
__v; \ __v; \
}) })
@@ -321,10 +313,7 @@ typedef union {
#define __RV_CSR_WRITE(csr, val) \ #define __RV_CSR_WRITE(csr, val) \
({ \ ({ \
register rv_csr_t __v = (rv_csr_t)(val); \ register rv_csr_t __v = (rv_csr_t)(val); \
__ASM volatile("csrw " STRINGIFY(csr) ", %0" \ __ASM volatile("csrw " STRINGIFY(csr) ", %0" : : "rK"(__v) : "memory"); \
: \
: "rK"(__v) \
: "memory"); \
}) })
/** /**
@@ -340,10 +329,7 @@ typedef union {
#define __RV_CSR_READ_SET(csr, val) \ #define __RV_CSR_READ_SET(csr, val) \
({ \ ({ \
register rv_csr_t __v = (rv_csr_t)(val); \ register rv_csr_t __v = (rv_csr_t)(val); \
__ASM volatile("csrrs %0, " STRINGIFY(csr) ", %1" \ __ASM volatile("csrrs %0, " STRINGIFY(csr) ", %1" : "=r"(__v) : "rK"(__v) : "memory"); \
: "=r"(__v) \
: "rK"(__v) \
: "memory"); \
__v; \ __v; \
}) })
@@ -358,10 +344,7 @@ typedef union {
#define __RV_CSR_SET(csr, val) \ #define __RV_CSR_SET(csr, val) \
({ \ ({ \
register rv_csr_t __v = (rv_csr_t)(val); \ register rv_csr_t __v = (rv_csr_t)(val); \
__ASM volatile("csrs " STRINGIFY(csr) ", %0" \ __ASM volatile("csrs " STRINGIFY(csr) ", %0" : : "rK"(__v) : "memory"); \
: \
: "rK"(__v) \
: "memory"); \
}) })
/** /**
@@ -377,10 +360,7 @@ typedef union {
#define __RV_CSR_READ_CLEAR(csr, val) \ #define __RV_CSR_READ_CLEAR(csr, val) \
({ \ ({ \
register rv_csr_t __v = (rv_csr_t)(val); \ register rv_csr_t __v = (rv_csr_t)(val); \
__ASM volatile("csrrc %0, " STRINGIFY(csr) ", %1" \ __ASM volatile("csrrc %0, " STRINGIFY(csr) ", %1" : "=r"(__v) : "rK"(__v) : "memory"); \
: "=r"(__v) \
: "rK"(__v) \
: "memory"); \
__v; \ __v; \
}) })
@@ -395,10 +375,7 @@ typedef union {
#define __RV_CSR_CLEAR(csr, val) \ #define __RV_CSR_CLEAR(csr, val) \
({ \ ({ \
register rv_csr_t __v = (rv_csr_t)(val); \ register rv_csr_t __v = (rv_csr_t)(val); \
__ASM volatile("csrc " STRINGIFY(csr) ", %0" \ __ASM volatile("csrc " STRINGIFY(csr) ", %0" : : "rK"(__v) : "memory"); \
: \
: "rK"(__v) \
: "memory"); \
}) })
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
@@ -408,10 +385,7 @@ typedef union {
* \remarks * \remarks
* Can only be executed in Privileged modes. * Can only be executed in Privileged modes.
*/ */
__STATIC_FORCEINLINE void __enable_irq(void) __STATIC_FORCEINLINE void __enable_irq(void) { __RV_CSR_SET(CSR_MSTATUS, MSTATUS_MIE); }
{
__RV_CSR_SET(CSR_MSTATUS, MSTATUS_MIE);
}
/** /**
* \brief Disable IRQ Interrupts * \brief Disable IRQ Interrupts
@@ -419,10 +393,7 @@ __STATIC_FORCEINLINE void __enable_irq(void)
* \remarks * \remarks
* Can only be executed in Privileged modes. * Can only be executed in Privileged modes.
*/ */
__STATIC_FORCEINLINE void __disable_irq(void) __STATIC_FORCEINLINE void __disable_irq(void) { __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_MIE); }
{
__RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
}
/** /**
* \brief Read whole 64 bits value of mcycle counter * \brief Read whole 64 bits value of mcycle counter
@@ -430,8 +401,7 @@ __STATIC_FORCEINLINE void __disable_irq(void)
* \return The whole 64 bits value of MCYCLE * \return The whole 64 bits value of MCYCLE
* \remarks It will work for both RV32 and RV64 to get full 64bits value of MCYCLE * \remarks It will work for both RV32 and RV64 to get full 64bits value of MCYCLE
*/ */
__STATIC_FORCEINLINE uint64_t __get_rv_cycle(void) __STATIC_FORCEINLINE uint64_t __get_rv_cycle(void) {
{
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
volatile uint32_t high0, low, high; volatile uint32_t high0, low, high;
uint64_t full; uint64_t full;
@@ -457,8 +427,7 @@ __STATIC_FORCEINLINE uint64_t __get_rv_cycle(void)
* \return The whole 64 bits value of MINSTRET * \return The whole 64 bits value of MINSTRET
* \remarks It will work for both RV32 and RV64 to get full 64bits value of MINSTRET * \remarks It will work for both RV32 and RV64 to get full 64bits value of MINSTRET
*/ */
__STATIC_FORCEINLINE uint64_t __get_rv_instret(void) __STATIC_FORCEINLINE uint64_t __get_rv_instret(void) {
{
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
volatile uint32_t high0, low, high; volatile uint32_t high0, low, high;
uint64_t full; uint64_t full;
@@ -485,8 +454,7 @@ __STATIC_FORCEINLINE uint64_t __get_rv_instret(void)
* \remarks It will work for both RV32 and RV64 to get full 64bits value of TIME * \remarks It will work for both RV32 and RV64 to get full 64bits value of TIME
* \attention only available when user mode available * \attention only available when user mode available
*/ */
__STATIC_FORCEINLINE uint64_t __get_rv_time(void) __STATIC_FORCEINLINE uint64_t __get_rv_time(void) {
{
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
volatile uint32_t high0, low, high; volatile uint32_t high0, low, high;
uint64_t full; uint64_t full;
@@ -525,10 +493,7 @@ __STATIC_FORCEINLINE uint64_t __get_rv_time(void)
* No Operation does nothing. * No Operation does nothing.
* This instruction can be used for code alignment purposes. * This instruction can be used for code alignment purposes.
*/ */
__STATIC_FORCEINLINE void __NOP(void) __STATIC_FORCEINLINE void __NOP(void) { __ASM volatile("nop"); }
{
__ASM volatile("nop");
}
/** /**
* \brief Wait For Interrupt * \brief Wait For Interrupt
@@ -539,8 +504,7 @@ __STATIC_FORCEINLINE void __NOP(void)
* 1. mstatus.MIE == 1(interrupt enabled), Core will enter ISR code * 1. mstatus.MIE == 1(interrupt enabled), Core will enter ISR code
* 2. mstatus.MIE == 0(interrupt disabled), Core will resume previous execution * 2. mstatus.MIE == 0(interrupt disabled), Core will resume previous execution
*/ */
__STATIC_FORCEINLINE void __WFI(void) __STATIC_FORCEINLINE void __WFI(void) {
{
__RV_CSR_CLEAR(CSR_WFE, WFE_WFE); __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
__ASM volatile("wfi"); __ASM volatile("wfi");
} }
@@ -552,8 +516,7 @@ __STATIC_FORCEINLINE void __WFI(void)
* It will suspends execution until event, NMI or Debug happened. * It will suspends execution until event, NMI or Debug happened.
* When Core is waked up, Core will resume previous execution * When Core is waked up, Core will resume previous execution
*/ */
__STATIC_FORCEINLINE void __WFE(void) __STATIC_FORCEINLINE void __WFE(void) {
{
__RV_CSR_SET(CSR_WFE, WFE_WFE); __RV_CSR_SET(CSR_WFE, WFE_WFE);
__ASM volatile("wfi"); __ASM volatile("wfi");
__RV_CSR_CLEAR(CSR_WFE, WFE_WFE); __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
@@ -566,10 +529,7 @@ __STATIC_FORCEINLINE void __WFE(void)
* Debug tools can use this to investigate system state * Debug tools can use this to investigate system state
* when the instruction at a particular address is reached. * when the instruction at a particular address is reached.
*/ */
__STATIC_FORCEINLINE void __EBREAK(void) __STATIC_FORCEINLINE void __EBREAK(void) { __ASM volatile("ebreak"); }
{
__ASM volatile("ebreak");
}
/** /**
* \brief Environment Call Instruction * \brief Environment Call Instruction
@@ -577,10 +537,7 @@ __STATIC_FORCEINLINE void __EBREAK(void)
* The ECALL instruction is used to make a service request to * The ECALL instruction is used to make a service request to
* the execution environment. * the execution environment.
*/ */
__STATIC_FORCEINLINE void __ECALL(void) __STATIC_FORCEINLINE void __ECALL(void) { __ASM volatile("ecall"); }
{
__ASM volatile("ecall");
}
/** /**
* \brief WFI Sleep Mode enumeration * \brief WFI Sleep Mode enumeration
@@ -597,10 +554,7 @@ typedef enum WFI_SleepMode {
* WFI Sleep mode. * WFI Sleep mode.
* \param[in] mode The sleep mode to be set * \param[in] mode The sleep mode to be set
*/ */
__STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode) __STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode) { __RV_CSR_WRITE(CSR_SLEEPVALUE, mode); }
{
__RV_CSR_WRITE(CSR_SLEEPVALUE, mode);
}
/** /**
* \brief Send TX Event * \brief Send TX Event
@@ -608,70 +562,49 @@ __STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode)
* Set the CSR TXEVT to control send a TX Event. * Set the CSR TXEVT to control send a TX Event.
* The Core will output signal tx_evt as output event signal. * The Core will output signal tx_evt as output event signal.
*/ */
__STATIC_FORCEINLINE void __TXEVT(void) __STATIC_FORCEINLINE void __TXEVT(void) { __RV_CSR_SET(CSR_TXEVT, 0x1); }
{
__RV_CSR_SET(CSR_TXEVT, 0x1);
}
/** /**
* \brief Enable MCYCLE counter * \brief Enable MCYCLE counter
* \details * \details
* Clear the CY bit of MCOUNTINHIBIT to 0 to enable MCYCLE Counter * Clear the CY bit of MCOUNTINHIBIT to 0 to enable MCYCLE Counter
*/ */
__STATIC_FORCEINLINE void __enable_mcycle_counter(void) __STATIC_FORCEINLINE void __enable_mcycle_counter(void) { __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY); }
{
__RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
}
/** /**
* \brief Disable MCYCLE counter * \brief Disable MCYCLE counter
* \details * \details
* Set the CY bit of MCOUNTINHIBIT to 1 to disable MCYCLE Counter * Set the CY bit of MCOUNTINHIBIT to 1 to disable MCYCLE Counter
*/ */
__STATIC_FORCEINLINE void __disable_mcycle_counter(void) __STATIC_FORCEINLINE void __disable_mcycle_counter(void) { __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY); }
{
__RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
}
/** /**
* \brief Enable MINSTRET counter * \brief Enable MINSTRET counter
* \details * \details
* Clear the IR bit of MCOUNTINHIBIT to 0 to enable MINSTRET Counter * Clear the IR bit of MCOUNTINHIBIT to 0 to enable MINSTRET Counter
*/ */
__STATIC_FORCEINLINE void __enable_minstret_counter(void) __STATIC_FORCEINLINE void __enable_minstret_counter(void) { __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR); }
{
__RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
}
/** /**
* \brief Disable MINSTRET counter * \brief Disable MINSTRET counter
* \details * \details
* Set the IR bit of MCOUNTINHIBIT to 1 to disable MINSTRET Counter * Set the IR bit of MCOUNTINHIBIT to 1 to disable MINSTRET Counter
*/ */
__STATIC_FORCEINLINE void __disable_minstret_counter(void) __STATIC_FORCEINLINE void __disable_minstret_counter(void) { __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR); }
{
__RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
}
/** /**
* \brief Enable MCYCLE & MINSTRET counter * \brief Enable MCYCLE & MINSTRET counter
* \details * \details
* Clear the IR and CY bit of MCOUNTINHIBIT to 1 to enable MINSTRET & MCYCLE Counter * Clear the IR and CY bit of MCOUNTINHIBIT to 1 to enable MINSTRET & MCYCLE Counter
*/ */
__STATIC_FORCEINLINE void __enable_all_counter(void) __STATIC_FORCEINLINE void __enable_all_counter(void) { __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY); }
{
__RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR|MCOUNTINHIBIT_CY);
}
/** /**
* \brief Disable MCYCLE & MINSTRET counter * \brief Disable MCYCLE & MINSTRET counter
* \details * \details
* Set the IR and CY bit of MCOUNTINHIBIT to 1 to disable MINSTRET & MCYCLE Counter * Set the IR and CY bit of MCOUNTINHIBIT to 1 to disable MINSTRET & MCYCLE Counter
*/ */
__STATIC_FORCEINLINE void __disable_all_counter(void) __STATIC_FORCEINLINE void __disable_all_counter(void) { __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY); }
{
__RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR|MCOUNTINHIBIT_CY);
}
/** /**
* \brief Execute fence instruction, p -> pred, s -> succ * \brief Execute fence instruction, p -> pred, s -> succ
@@ -691,10 +624,7 @@ __STATIC_FORCEINLINE void __disable_all_counter(void)
* The FENCE.I instruction is used to synchronize the instruction * The FENCE.I instruction is used to synchronize the instruction
* and data streams. * and data streams.
*/ */
__STATIC_FORCEINLINE void __FENCE_I(void) __STATIC_FORCEINLINE void __FENCE_I(void) { __ASM volatile("fence.i"); }
{
__ASM volatile("fence.i");
}
/** \brief Read & Write Memory barrier */ /** \brief Read & Write Memory barrier */
#define __RWMB() __FENCE(iorw, iorw) #define __RWMB() __FENCE(iorw, iorw)
@@ -717,7 +647,6 @@ __STATIC_FORCEINLINE void __FENCE_I(void)
/** \brief CPU relax for busy loop */ /** \brief CPU relax for busy loop */
#define __CPU_RELAX() __ASM volatile("" : : : "memory") #define __CPU_RELAX() __ASM volatile("" : : : "memory")
/* ===== Load/Store Operations ===== */ /* ===== Load/Store Operations ===== */
/** /**
* \brief Load 8bit value from address (8 bit) * \brief Load 8bit value from address (8 bit)
@@ -725,8 +654,7 @@ __STATIC_FORCEINLINE void __FENCE_I(void)
* \param [in] addr Address pointer to data * \param [in] addr Address pointer to data
* \return value of type uint8_t at (*addr) * \return value of type uint8_t at (*addr)
*/ */
__STATIC_FORCEINLINE uint8_t __LB(volatile void *addr) __STATIC_FORCEINLINE uint8_t __LB(volatile void *addr) {
{
uint8_t result; uint8_t result;
__ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr)); __ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr));
@@ -739,8 +667,7 @@ __STATIC_FORCEINLINE uint8_t __LB(volatile void *addr)
* \param [in] addr Address pointer to data * \param [in] addr Address pointer to data
* \return value of type uint16_t at (*addr) * \return value of type uint16_t at (*addr)
*/ */
__STATIC_FORCEINLINE uint16_t __LH(volatile void *addr) __STATIC_FORCEINLINE uint16_t __LH(volatile void *addr) {
{
uint16_t result; uint16_t result;
__ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr)); __ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr));
@@ -753,8 +680,7 @@ __STATIC_FORCEINLINE uint16_t __LH(volatile void *addr)
* \param [in] addr Address pointer to data * \param [in] addr Address pointer to data
* \return value of type uint32_t at (*addr) * \return value of type uint32_t at (*addr)
*/ */
__STATIC_FORCEINLINE uint32_t __LW(volatile void *addr) __STATIC_FORCEINLINE uint32_t __LW(volatile void *addr) {
{
uint32_t result; uint32_t result;
__ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr)); __ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr));
@@ -769,8 +695,7 @@ __STATIC_FORCEINLINE uint32_t __LW(volatile void *addr)
* \return value of type uint64_t at (*addr) * \return value of type uint64_t at (*addr)
* \remarks RV64 only macro * \remarks RV64 only macro
*/ */
__STATIC_FORCEINLINE uint64_t __LD(volatile void *addr) __STATIC_FORCEINLINE uint64_t __LD(volatile void *addr) {
{
uint64_t result; uint64_t result;
__ASM volatile("ld %0, 0(%1)" : "=r"(result) : "r"(addr)); __ASM volatile("ld %0, 0(%1)" : "=r"(result) : "r"(addr));
return result; return result;
@@ -783,10 +708,7 @@ __STATIC_FORCEINLINE uint64_t __LD(volatile void *addr)
* \param [in] addr Address pointer to data * \param [in] addr Address pointer to data
* \param [in] val Value to set * \param [in] val Value to set
*/ */
__STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val) __STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val) { __ASM volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr)); }
{
__ASM volatile ("sb %0, 0(%1)" : : "r" (val), "r" (addr));
}
/** /**
* \brief Write 16bit value to address (16 bit) * \brief Write 16bit value to address (16 bit)
@@ -794,10 +716,7 @@ __STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val)
* \param [in] addr Address pointer to data * \param [in] addr Address pointer to data
* \param [in] val Value to set * \param [in] val Value to set
*/ */
__STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val) __STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val) { __ASM volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr)); }
{
__ASM volatile ("sh %0, 0(%1)" : : "r" (val), "r" (addr));
}
/** /**
* \brief Write 32bit value to address (32 bit) * \brief Write 32bit value to address (32 bit)
@@ -805,10 +724,7 @@ __STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val)
* \param [in] addr Address pointer to data * \param [in] addr Address pointer to data
* \param [in] val Value to set * \param [in] val Value to set
*/ */
__STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val) __STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val) { __ASM volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr)); }
{
__ASM volatile ("sw %0, 0(%1)" : : "r" (val), "r" (addr));
}
#if __RISCV_XLEN != 32 #if __RISCV_XLEN != 32
/** /**
@@ -817,10 +733,7 @@ __STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val)
* \param [in] addr Address pointer to data * \param [in] addr Address pointer to data
* \param [in] val Value to set * \param [in] val Value to set
*/ */
__STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val) __STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val) { __ASM volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr)); }
{
__ASM volatile ("sd %0, 0(%1)" : : "r" (val), "r" (addr));
}
#endif #endif
/** /**
@@ -834,19 +747,17 @@ __STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val)
* \param [in] newval New value to be stored into the address * \param [in] newval New value to be stored into the address
* \return return the initial value in memory * \return return the initial value in memory
*/ */
__STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval, uint32_t newval) __STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval, uint32_t newval) {
{
register uint32_t result; register uint32_t result;
register uint32_t rc; register uint32_t rc;
__ASM volatile ( \ __ASM volatile("0: lr.w %0, %2 \n"
"0: lr.w %0, %2 \n" \ " bne %0, %z3, 1f \n"
" bne %0, %z3, 1f \n" \ " sc.w %1, %z4, %2 \n"
" sc.w %1, %z4, %2 \n" \ " bnez %1, 0b \n"
" bnez %1, 0b \n" \ "1:\n"
"1:\n" \ : "=&r"(result), "=&r"(rc), "+A"(*addr)
: "=&r"(result), "=&r"(rc), "+A"(*addr) \ : "r"(oldval), "r"(newval)
: "r"(oldval), "r"(newval) \
: "memory"); : "memory");
return result; return result;
} }
@@ -858,12 +769,10 @@ __STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval,
* \param [in] newval New value to be stored into the address * \param [in] newval New value to be stored into the address
* \return return the original value in memory * \return return the original value in memory
*/ */
__STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) __STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) {
{
register uint32_t result; register uint32_t result;
__ASM volatile ("amoswap.w %0, %2, %1" : \ __ASM volatile("amoswap.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
return result; return result;
} }
@@ -874,12 +783,10 @@ __STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newv
* \param [in] value value to be ADDed * \param [in] value value to be ADDed
* \return return memory value + add value * \return return memory value + add value
*/ */
__STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) __STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) {
{
register int32_t result; register int32_t result;
__ASM volatile ("amoadd.w %0, %2, %1" : \ __ASM volatile("amoadd.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -890,12 +797,10 @@ __STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
* \param [in] value value to be ANDed * \param [in] value value to be ANDed
* \return return memory value & and value * \return return memory value & and value
*/ */
__STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) __STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) {
{
register int32_t result; register int32_t result;
__ASM volatile ("amoand.w %0, %2, %1" : \ __ASM volatile("amoand.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -906,12 +811,10 @@ __STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
* \param [in] value value to be ORed * \param [in] value value to be ORed
* \return return memory value | and value * \return return memory value | and value
*/ */
__STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) __STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) {
{
register int32_t result; register int32_t result;
__ASM volatile ("amoor.w %0, %2, %1" : \ __ASM volatile("amoor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -922,12 +825,10 @@ __STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
* \param [in] value value to be XORed * \param [in] value value to be XORed
* \return return memory value ^ and value * \return return memory value ^ and value
*/ */
__STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) __STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) {
{
register int32_t result; register int32_t result;
__ASM volatile ("amoxor.w %0, %2, %1" : \ __ASM volatile("amoxor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -938,12 +839,10 @@ __STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
* \param [in] value value to be compared * \param [in] value value to be compared
* \return return the bigger value * \return return the bigger value
*/ */
__STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) __STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) {
{
register uint32_t result; register uint32_t result;
__ASM volatile ("amomaxu.w %0, %2, %1" : \ __ASM volatile("amomaxu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -954,12 +853,10 @@ __STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t valu
* \param [in] value value to be compared * \param [in] value value to be compared
* \return the bigger value * \return the bigger value
*/ */
__STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) __STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) {
{
register int32_t result; register int32_t result;
__ASM volatile ("amomax.w %0, %2, %1" : \ __ASM volatile("amomax.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -970,12 +867,10 @@ __STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
* \param [in] value value to be compared * \param [in] value value to be compared
* \return the smaller value * \return the smaller value
*/ */
__STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) __STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) {
{
register uint32_t result; register uint32_t result;
__ASM volatile ("amominu.w %0, %2, %1" : \ __ASM volatile("amominu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -986,12 +881,10 @@ __STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t valu
* \param [in] value value to be compared * \param [in] value value to be compared
* \return the smaller value * \return the smaller value
*/ */
__STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) __STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) {
{
register int32_t result; register int32_t result;
__ASM volatile ("amomin.w %0, %2, %1" : \ __ASM volatile("amomin.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -1007,19 +900,17 @@ __STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
* \param [in] newval New value to be stored into the address * \param [in] newval New value to be stored into the address
* \return return the initial value in memory * \return return the initial value in memory
*/ */
__STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval, uint64_t newval) __STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval, uint64_t newval) {
{
register uint64_t result; register uint64_t result;
register uint64_t rc; register uint64_t rc;
__ASM volatile ( \ __ASM volatile("0: lr.d %0, %2 \n"
"0: lr.d %0, %2 \n" \ " bne %0, %z3, 1f \n"
" bne %0, %z3, 1f \n" \ " sc.d %1, %z4, %2 \n"
" sc.d %1, %z4, %2 \n" \ " bnez %1, 0b \n"
" bnez %1, 0b \n" \ "1:\n"
"1:\n" \ : "=&r"(result), "=&r"(rc), "+A"(*addr)
: "=&r"(result), "=&r"(rc), "+A"(*addr) \ : "r"(oldval), "r"(newval)
: "r"(oldval), "r"(newval) \
: "memory"); : "memory");
return result; return result;
} }
@@ -1031,12 +922,10 @@ __STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval,
* \param [in] newval New value to be stored into the address * \param [in] newval New value to be stored into the address
* \return return the original value in memory * \return return the original value in memory
*/ */
__STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newval) __STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newval) {
{
register uint64_t result; register uint64_t result;
__ASM volatile ("amoswap.d %0, %2, %1" : \ __ASM volatile("amoswap.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
return result; return result;
} }
@@ -1047,12 +936,10 @@ __STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newv
* \param [in] value value to be ADDed * \param [in] value value to be ADDed
* \return return memory value + add value * \return return memory value + add value
*/ */
__STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value) __STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value) {
{
register int64_t result; register int64_t result;
__ASM volatile ("amoadd.d %0, %2, %1" : \ __ASM volatile("amoadd.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -1063,12 +950,10 @@ __STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value)
* \param [in] value value to be ANDed * \param [in] value value to be ANDed
* \return return memory value & and value * \return return memory value & and value
*/ */
__STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value) __STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value) {
{
register int64_t result; register int64_t result;
__ASM volatile ("amoand.d %0, %2, %1" : \ __ASM volatile("amoand.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -1079,12 +964,10 @@ __STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value)
* \param [in] value value to be ORed * \param [in] value value to be ORed
* \return return memory value | and value * \return return memory value | and value
*/ */
__STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value) __STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value) {
{
register int64_t result; register int64_t result;
__ASM volatile ("amoor.d %0, %2, %1" : \ __ASM volatile("amoor.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -1095,12 +978,10 @@ __STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value)
* \param [in] value value to be XORed * \param [in] value value to be XORed
* \return return memory value ^ and value * \return return memory value ^ and value
*/ */
__STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value) __STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value) {
{
register int64_t result; register int64_t result;
__ASM volatile ("amoxor.d %0, %2, %1" : \ __ASM volatile("amoxor.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -1111,12 +992,10 @@ __STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value)
* \param [in] value value to be compared * \param [in] value value to be compared
* \return return the bigger value * \return return the bigger value
*/ */
__STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t value) __STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t value) {
{
register uint64_t result; register uint64_t result;
__ASM volatile ("amomaxu.d %0, %2, %1" : \ __ASM volatile("amomaxu.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -1127,12 +1006,10 @@ __STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t valu
* \param [in] value value to be compared * \param [in] value value to be compared
* \return the bigger value * \return the bigger value
*/ */
__STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value) __STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value) {
{
register int64_t result; register int64_t result;
__ASM volatile ("amomax.d %0, %2, %1" : \ __ASM volatile("amomax.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -1143,12 +1020,10 @@ __STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value)
* \param [in] value value to be compared * \param [in] value value to be compared
* \return the smaller value * \return the smaller value
*/ */
__STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t value) __STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t value) {
{
register uint64_t result; register uint64_t result;
__ASM volatile ("amominu.d %0, %2, %1" : \ __ASM volatile("amominu.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
@@ -1159,12 +1034,10 @@ __STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t valu
* \param [in] value value to be compared * \param [in] value value to be compared
* \return the smaller value * \return the smaller value
*/ */
__STATIC_FORCEINLINE int64_t __AMOMIN_D(volatile int64_t *addr, int64_t value) __STATIC_FORCEINLINE int64_t __AMOMIN_D(volatile int64_t *addr, int64_t value) {
{
register int64_t result; register int64_t result;
__ASM volatile ("amomin.d %0, %2, %1" : \ __ASM volatile("amomin.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr; return *addr;
} }
#endif /* __RISCV_XLEN == 64 */ #endif /* __RISCV_XLEN == 64 */

20
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_cache.h vendored
View File

@@ -60,10 +60,7 @@
* \sa * \sa
* - \ref DisableICache * - \ref DisableICache
*/ */
__STATIC_FORCEINLINE void EnableICache (void) __STATIC_FORCEINLINE void EnableICache(void) { __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); }
{
__RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
}
/** /**
* \brief Disable ICache * \brief Disable ICache
@@ -74,10 +71,7 @@ __STATIC_FORCEINLINE void EnableICache (void)
* \sa * \sa
* - \ref EnableICache * - \ref EnableICache
*/ */
__STATIC_FORCEINLINE void DisableICache (void) __STATIC_FORCEINLINE void DisableICache(void) { __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); }
{
__RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
}
/** @} */ /* End of Doxygen Group NMSIS_Core_ICache */ /** @} */ /* End of Doxygen Group NMSIS_Core_ICache */
#endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */ #endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */
@@ -97,10 +91,7 @@ __STATIC_FORCEINLINE void DisableICache (void)
* \sa * \sa
* - \ref DisableDCache * - \ref DisableDCache
*/ */
__STATIC_FORCEINLINE void EnableDCache (void) __STATIC_FORCEINLINE void EnableDCache(void) { __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); }
{
__RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
}
/** /**
* \brief Disable DCache * \brief Disable DCache
@@ -111,10 +102,7 @@ __STATIC_FORCEINLINE void EnableDCache (void)
* \sa * \sa
* - \ref EnableDCache * - \ref EnableDCache
*/ */
__STATIC_FORCEINLINE void DisableDCache (void) __STATIC_FORCEINLINE void DisableDCache(void) { __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); }
{
__RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
}
/** @} */ /* End of Doxygen Group NMSIS_Core_DCache */ /** @} */ /* End of Doxygen Group NMSIS_Core_DCache */
#endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */ #endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */

1024
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_dsp.h vendored
View File

File diff suppressed because it is too large Load Diff

128
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_eclic.h vendored
View File

@@ -48,8 +48,7 @@
/** /**
* \brief Union type to access CLICFG configure register. * \brief Union type to access CLICFG configure register.
*/ */
typedef union typedef union {
{
struct { struct {
uint8_t _reserved0 : 1; /*!< bit: 0 Overflow condition code flag */ uint8_t _reserved0 : 1; /*!< bit: 0 Overflow condition code flag */
uint8_t nlbits : 4; /*!< bit: 29 Carry condition code flag */ uint8_t nlbits : 4; /*!< bit: 29 Carry condition code flag */
@@ -255,8 +254,7 @@ typedef enum IRQn {
* \sa * \sa
* - \ref ECLIC_GetCfgNlbits * - \ref ECLIC_GetCfgNlbits
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits) __STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits) {
{
ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk; ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk;
ECLIC->CFG |= (uint8_t)((nlbits << CLIC_CLICCFG_NLBIT_Pos) & CLIC_CLICCFG_NLBIT_Msk); ECLIC->CFG |= (uint8_t)((nlbits << CLIC_CLICCFG_NLBIT_Pos) & CLIC_CLICCFG_NLBIT_Msk);
} }
@@ -271,10 +269,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits)
* \sa * \sa
* - \ref ECLIC_SetCfgNlbits * - \ref ECLIC_SetCfgNlbits
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void) { return ((uint32_t)((ECLIC->CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos)); }
{
return ((uint32_t)((ECLIC->CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos));
}
/** /**
* \brief Get the ECLIC version number * \brief Get the ECLIC version number
@@ -287,10 +282,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void)
* \sa * \sa
* - \ref ECLIC_GetInfoNum * - \ref ECLIC_GetInfoNum
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos)); }
{
return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos));
}
/** /**
* \brief Get CLICINTCTLBITS * \brief Get CLICINTCTLBITS
@@ -304,10 +296,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void)
* \sa * \sa
* - \ref ECLIC_GetInfoNum * - \ref ECLIC_GetInfoNum
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos)); }
{
return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos));
}
/** /**
* \brief Get number of maximum interrupt inputs supported * \brief Get number of maximum interrupt inputs supported
@@ -320,10 +309,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void)
* \sa * \sa
* - \ref ECLIC_GetInfoCtlbits * - \ref ECLIC_GetInfoCtlbits
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void) __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos)); }
{
return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos));
}
/** /**
* \brief Set Machine Mode Interrupt Level Threshold * \brief Set Machine Mode Interrupt Level Threshold
@@ -333,10 +319,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void)
* \sa * \sa
* - \ref ECLIC_GetMth * - \ref ECLIC_GetMth
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth) __STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth) { ECLIC->MTH = mth; }
{
ECLIC->MTH = mth;
}
/** /**
* \brief Get Machine Mode Interrupt Level Threshold * \brief Get Machine Mode Interrupt Level Threshold
@@ -346,11 +329,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth)
* \sa * \sa
* - \ref ECLIC_SetMth * - \ref ECLIC_SetMth
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void) __STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void) { return (ECLIC->MTH); }
{
return (ECLIC->MTH);
}
/** /**
* \brief Enable a specific interrupt * \brief Enable a specific interrupt
@@ -362,10 +341,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void)
* \sa * \sa
* - \ref ECLIC_DisableIRQ * - \ref ECLIC_DisableIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk; }
{
ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk;
}
/** /**
* \brief Get a specific interrupt enable status * \brief Get a specific interrupt enable status
@@ -381,10 +357,7 @@ __STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn)
* - \ref ECLIC_EnableIRQ * - \ref ECLIC_EnableIRQ
* - \ref ECLIC_DisableIRQ * - \ref ECLIC_DisableIRQ
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn) { return ((uint32_t)(ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk); }
{
return((uint32_t) (ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk);
}
/** /**
* \brief Disable a specific interrupt * \brief Disable a specific interrupt
@@ -396,10 +369,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_EnableIRQ * - \ref ECLIC_EnableIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk; }
{
ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk;
}
/** /**
* \brief Get the pending specific interrupt * \brief Get the pending specific interrupt
@@ -415,10 +385,7 @@ __STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn)
* - \ref ECLIC_SetPendingIRQ * - \ref ECLIC_SetPendingIRQ
* - \ref ECLIC_ClearPendingIRQ * - \ref ECLIC_ClearPendingIRQ
*/ */
__STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk); }
{
return((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk);
}
/** /**
* \brief Set a specific interrupt to pending * \brief Set a specific interrupt to pending
@@ -431,10 +398,7 @@ __STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn)
* - \ref ECLIC_GetPendingIRQ * - \ref ECLIC_GetPendingIRQ
* - \ref ECLIC_ClearPendingIRQ * - \ref ECLIC_ClearPendingIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk; }
{
ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk;
}
/** /**
* \brief Clear a specific interrupt from pending * \brief Clear a specific interrupt from pending
@@ -448,10 +412,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn)
* - \ref ECLIC_SetPendingIRQ * - \ref ECLIC_SetPendingIRQ
* - \ref ECLIC_GetPendingIRQ * - \ref ECLIC_GetPendingIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIP &= ~CLIC_INTIP_IP_Msk; }
{
ECLIC->CTRL[IRQn].INTIP &= ~ CLIC_INTIP_IP_Msk;
}
/** /**
* \brief Set trigger mode and polarity for a specific interrupt * \brief Set trigger mode and polarity for a specific interrupt
@@ -469,8 +430,7 @@ __STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetTrigIRQ * - \ref ECLIC_GetTrigIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig) __STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig) {
{
ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk; ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk;
ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig << CLIC_INTATTR_TRIG_Pos); ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig << CLIC_INTATTR_TRIG_Pos);
} }
@@ -490,10 +450,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig)
* \sa * \sa
* - \ref ECLIC_SetTrigIRQ * - \ref ECLIC_SetTrigIRQ
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn) { return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk) >> CLIC_INTATTR_TRIG_Pos)); }
{
return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk)>>CLIC_INTATTR_TRIG_Pos));
}
/** /**
* \brief Set interrupt working mode for a specific interrupt * \brief Set interrupt working mode for a specific interrupt
@@ -508,8 +465,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetShvIRQ * - \ref ECLIC_GetShvIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv) __STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv) {
{
ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk; ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk;
ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv << CLIC_INTATTR_SHV_Pos); ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv << CLIC_INTATTR_SHV_Pos);
} }
@@ -527,10 +483,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv)
* \sa * \sa
* - \ref ECLIC_SetShvIRQ * - \ref ECLIC_SetShvIRQ
*/ */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn) { return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk) >> CLIC_INTATTR_SHV_Pos)); }
{
return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk)>>CLIC_INTATTR_SHV_Pos));
}
/** /**
* \brief Modify ECLIC Interrupt Input Control Register for a specific interrupt * \brief Modify ECLIC Interrupt Input Control Register for a specific interrupt
@@ -543,10 +496,7 @@ __STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetCtrlIRQ * - \ref ECLIC_GetCtrlIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl) __STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl) { ECLIC->CTRL[IRQn].INTCTRL = intctrl; }
{
ECLIC->CTRL[IRQn].INTCTRL = intctrl;
}
/** /**
* \brief Get ECLIC Interrupt Input Control Register value for a specific interrupt * \brief Get ECLIC Interrupt Input Control Register value for a specific interrupt
@@ -559,10 +509,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl)
* \sa * \sa
* - \ref ECLIC_SetCtrlIRQ * - \ref ECLIC_SetCtrlIRQ
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn) { return (ECLIC->CTRL[IRQn].INTCTRL); }
{
return (ECLIC->CTRL[IRQn].INTCTRL);
}
/** /**
* \brief Set ECLIC Interrupt level of a specific interrupt * \brief Set ECLIC Interrupt level of a specific interrupt
@@ -579,8 +526,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetLevelIRQ * - \ref ECLIC_GetLevelIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs) __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs) {
{
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
@@ -613,8 +559,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)
* \sa * \sa
* - \ref ECLIC_SetLevelIRQ * - \ref ECLIC_SetLevelIRQ
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn) {
{
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
@@ -644,8 +589,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetPriorityIRQ * - \ref ECLIC_GetPriorityIRQ
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri) __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri) {
{
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
if (nlbits < intctlbits) { if (nlbits < intctlbits) {
@@ -674,8 +618,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)
* \sa * \sa
* - \ref ECLIC_SetPriorityIRQ * - \ref ECLIC_SetPriorityIRQ
*/ */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn) __STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn) {
{
uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
if (nlbits < intctlbits) { if (nlbits < intctlbits) {
@@ -705,8 +648,7 @@ __STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn)
* \sa * \sa
* - \ref ECLIC_GetVector * - \ref ECLIC_GetVector
*/ */
__STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) __STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) {
{
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
volatile uint32_t vec_base; volatile uint32_t vec_base;
vec_base = ((uint32_t)__RV_CSR_READ(CSR_MTVT)); vec_base = ((uint32_t)__RV_CSR_READ(CSR_MTVT));
@@ -734,8 +676,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector)
* \sa * \sa
* - \ref ECLIC_SetVector * - \ref ECLIC_SetVector
*/ */
__STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) __STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) {
{
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 4)); return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 4));
#elif __RISCV_XLEN == 64 #elif __RISCV_XLEN == 64
@@ -755,8 +696,7 @@ __STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn)
* \sa * \sa
* - \ref __get_exc_entry * - \ref __get_exc_entry
*/ */
__STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) __STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) {
{
addr &= (rv_csr_t)(~0x3F); addr &= (rv_csr_t)(~0x3F);
addr |= ECLIC_MODE_MTVEC_Msk; addr |= ECLIC_MODE_MTVEC_Msk;
__RV_CSR_WRITE(CSR_MTVEC, addr); __RV_CSR_WRITE(CSR_MTVEC, addr);
@@ -772,8 +712,7 @@ __STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr)
* \sa * \sa
* - \ref __set_exc_entry * - \ref __set_exc_entry
*/ */
__STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void) __STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void) {
{
unsigned long addr = __RV_CSR_READ(CSR_MTVEC); unsigned long addr = __RV_CSR_READ(CSR_MTVEC);
return (addr & ~ECLIC_MODE_MTVEC_Msk); return (addr & ~ECLIC_MODE_MTVEC_Msk);
} }
@@ -789,8 +728,7 @@ __STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void)
* \sa * \sa
* - \ref __get_nonvec_entry * - \ref __get_nonvec_entry
*/ */
__STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr) __STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr) {
{
if (__RV_CSR_READ(CSR_MTVT2) & 0x1) { if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
__RV_CSR_WRITE(CSR_MTVT2, addr | 0x01); __RV_CSR_WRITE(CSR_MTVT2, addr | 0x01);
} else { } else {
@@ -811,8 +749,7 @@ __STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr)
* \sa * \sa
* - \ref __set_nonvec_entry * - \ref __set_nonvec_entry
*/ */
__STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void) __STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void) {
{
if (__RV_CSR_READ(CSR_MTVT2) & 0x1) { if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1)); return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1));
} else { } else {
@@ -831,10 +768,7 @@ __STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void)
* - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector. * - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector.
* - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored. * - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored.
*/ */
__STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void) __STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void) { return __RV_CSR_READ(CSR_MNVEC); }
{
return __RV_CSR_READ(CSR_MNVEC);
}
/** /**
* \brief Save necessary CSRs into variables for vector interrupt nesting * \brief Save necessary CSRs into variables for vector interrupt nesting

17
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_fpu.h vendored
View File

@@ -85,7 +85,6 @@
* */ * */
#define __disable_FPU() __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS) #define __disable_FPU() __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS)
/** /**
* \brief Load a single-precision value from memory into float point register freg using flw instruction * \brief Load a single-precision value from memory into float point register freg using flw instruction
* \details The FLW instruction loads a single-precision floating point value from memory * \details The FLW instruction loads a single-precision floating point value from memory
@@ -103,9 +102,7 @@
#define __RV_FLW(freg, addr, ofs) \ #define __RV_FLW(freg, addr, ofs) \
({ \ ({ \
register rv_csr_t __addr = (rv_csr_t)(addr); \ register rv_csr_t __addr = (rv_csr_t)(addr); \
__ASM volatile("flw " STRINGIFY(freg) ", %0(%1) " \ __ASM volatile("flw " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \
: : "I"(ofs), "r"(__addr) \
: "memory"); \
}) })
/** /**
@@ -124,9 +121,7 @@
#define __RV_FSW(freg, addr, ofs) \ #define __RV_FSW(freg, addr, ofs) \
({ \ ({ \
register rv_csr_t __addr = (rv_csr_t)(addr); \ register rv_csr_t __addr = (rv_csr_t)(addr); \
__ASM volatile("fsw " STRINGIFY(freg) ", %0(%1) " \ __ASM volatile("fsw " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \
: : "I"(ofs), "r"(__addr) \
: "memory"); \
}) })
/** /**
@@ -147,9 +142,7 @@
#define __RV_FLD(freg, addr, ofs) \ #define __RV_FLD(freg, addr, ofs) \
({ \ ({ \
register rv_csr_t __addr = (rv_csr_t)(addr); \ register rv_csr_t __addr = (rv_csr_t)(addr); \
__ASM volatile("fld " STRINGIFY(freg) ", %0(%1) " \ __ASM volatile("fld " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \
: : "I"(ofs), "r"(__addr) \
: "memory"); \
}) })
/** /**
@@ -170,9 +163,7 @@
#define __RV_FSD(freg, addr, ofs) \ #define __RV_FSD(freg, addr, ofs) \
({ \ ({ \
register rv_csr_t __addr = (rv_csr_t)(addr); \ register rv_csr_t __addr = (rv_csr_t)(addr); \
__ASM volatile("fsd " STRINGIFY(freg) ", %0(%1) " \ __ASM volatile("fsd " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \
: : "I"(ofs), "r"(__addr) \
: "memory"); \
}) })
/** /**

176
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_pmp.h vendored
View File

@@ -58,11 +58,11 @@
* \param [in] idx PMP region index(0-15) * \param [in] idx PMP region index(0-15)
* \return PMPxCFG Register value * \return PMPxCFG Register value
*/ */
__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx) __STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx) {
{
rv_csr_t pmpcfg = 0; rv_csr_t pmpcfg = 0;
if (idx >= __PMP_ENTRY_NUM) return 0; if (idx >= __PMP_ENTRY_NUM)
return 0;
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
if (idx < 4) { if (idx < 4) {
pmpcfg = __RV_CSR_READ(CSR_PMPCFG0); pmpcfg = __RV_CSR_READ(CSR_PMPCFG0);
@@ -100,10 +100,10 @@ __STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
* \param [in] idx PMPx region index(0-15) * \param [in] idx PMPx region index(0-15)
* \param [in] pmpxcfg PMPxCFG register value to set * \param [in] pmpxcfg PMPxCFG register value to set
*/ */
__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg) __STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg) {
{
rv_csr_t pmpcfgx = 0; rv_csr_t pmpcfgx = 0;
if (idx >= __PMP_ENTRY_NUM) return; if (idx >= __PMP_ENTRY_NUM)
return;
#if __RISCV_XLEN == 32 #if __RISCV_XLEN == 32
if (idx < 4) { if (idx < 4) {
@@ -160,14 +160,18 @@ __STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg)
* - For RV32, pmpcfg0–pmpcfg3, hold the configurations * - For RV32, pmpcfg0–pmpcfg3, hold the configurations
* pmp0cfg–pmp15cfg for the 16 PMP entries * pmp0cfg–pmp15cfg for the 16 PMP entries
*/ */
__STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx) __STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx) {
{
switch (idx) { switch (idx) {
case 0: return __RV_CSR_READ(CSR_PMPCFG0); case 0:
case 1: return __RV_CSR_READ(CSR_PMPCFG1); return __RV_CSR_READ(CSR_PMPCFG0);
case 2: return __RV_CSR_READ(CSR_PMPCFG2); case 1:
case 3: return __RV_CSR_READ(CSR_PMPCFG3); return __RV_CSR_READ(CSR_PMPCFG1);
default: return 0; case 2:
return __RV_CSR_READ(CSR_PMPCFG2);
case 3:
return __RV_CSR_READ(CSR_PMPCFG3);
default:
return 0;
} }
} }
@@ -183,14 +187,22 @@ __STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx)
* - For RV32, pmpcfg0–pmpcfg3, hold the configurations * - For RV32, pmpcfg0–pmpcfg3, hold the configurations
* pmp0cfg–pmp15cfg for the 16 PMP entries * pmp0cfg–pmp15cfg for the 16 PMP entries
*/ */
__STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg) __STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg) {
{
switch (idx) { switch (idx) {
case 0: __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg); break; case 0:
case 1: __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg); break; __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg);
case 2: __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg); break; break;
case 3: __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg); break; case 1:
default: return; __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg);
break;
case 2:
__RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg);
break;
case 3:
__RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg);
break;
default:
return;
} }
} }
@@ -200,26 +212,42 @@ __STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg)
* \param [in] idx PMP region index(0-15) * \param [in] idx PMP region index(0-15)
* \return PMPADDRx Register value * \return PMPADDRx Register value
*/ */
__STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx) __STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx) {
{
switch (idx) { switch (idx) {
case 0: return __RV_CSR_READ(CSR_PMPADDR0); case 0:
case 1: return __RV_CSR_READ(CSR_PMPADDR1); return __RV_CSR_READ(CSR_PMPADDR0);
case 2: return __RV_CSR_READ(CSR_PMPADDR2); case 1:
case 3: return __RV_CSR_READ(CSR_PMPADDR3); return __RV_CSR_READ(CSR_PMPADDR1);
case 4: return __RV_CSR_READ(CSR_PMPADDR4); case 2:
case 5: return __RV_CSR_READ(CSR_PMPADDR5); return __RV_CSR_READ(CSR_PMPADDR2);
case 6: return __RV_CSR_READ(CSR_PMPADDR6); case 3:
case 7: return __RV_CSR_READ(CSR_PMPADDR7); return __RV_CSR_READ(CSR_PMPADDR3);
case 8: return __RV_CSR_READ(CSR_PMPADDR8); case 4:
case 9: return __RV_CSR_READ(CSR_PMPADDR9); return __RV_CSR_READ(CSR_PMPADDR4);
case 10: return __RV_CSR_READ(CSR_PMPADDR10); case 5:
case 11: return __RV_CSR_READ(CSR_PMPADDR11); return __RV_CSR_READ(CSR_PMPADDR5);
case 12: return __RV_CSR_READ(CSR_PMPADDR12); case 6:
case 13: return __RV_CSR_READ(CSR_PMPADDR13); return __RV_CSR_READ(CSR_PMPADDR6);
case 14: return __RV_CSR_READ(CSR_PMPADDR14); case 7:
case 15: return __RV_CSR_READ(CSR_PMPADDR15); return __RV_CSR_READ(CSR_PMPADDR7);
default: return 0; case 8:
return __RV_CSR_READ(CSR_PMPADDR8);
case 9:
return __RV_CSR_READ(CSR_PMPADDR9);
case 10:
return __RV_CSR_READ(CSR_PMPADDR10);
case 11:
return __RV_CSR_READ(CSR_PMPADDR11);
case 12:
return __RV_CSR_READ(CSR_PMPADDR12);
case 13:
return __RV_CSR_READ(CSR_PMPADDR13);
case 14:
return __RV_CSR_READ(CSR_PMPADDR14);
case 15:
return __RV_CSR_READ(CSR_PMPADDR15);
default:
return 0;
} }
} }
@@ -229,26 +257,58 @@ __STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx)
* \param [in] idx PMP region index(0-15) * \param [in] idx PMP region index(0-15)
* \param [in] pmpaddr PMPADDRx Register value to set * \param [in] pmpaddr PMPADDRx Register value to set
*/ */
__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, rv_csr_t pmpaddr) __STATIC_INLINE void __set_PMPADDRx(uint32_t idx, rv_csr_t pmpaddr) {
{
switch (idx) { switch (idx) {
case 0: __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr); break; case 0:
case 1: __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr); break; __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr);
case 2: __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr); break; break;
case 3: __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr); break; case 1:
case 4: __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr); break; __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr);
case 5: __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr); break; break;
case 6: __RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr); break; case 2:
case 7: __RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr); break; __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr);
case 8: __RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr); break; break;
case 9: __RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr); break; case 3:
case 10: __RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr); break; __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr);
case 11: __RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr); break; break;
case 12: __RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr); break; case 4:
case 13: __RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr); break; __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr);
case 14: __RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr); break; break;
case 15: __RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr); break; case 5:
default: return; __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr);
break;
case 6:
__RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr);
break;
case 7:
__RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr);
break;
case 8:
__RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr);
break;
case 9:
__RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr);
break;
case 10:
__RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr);
break;
case 11:
__RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr);
break;
case 12:
__RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr);
break;
case 13:
__RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr);
break;
case 14:
__RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr);
break;
case 15:
__RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr);
break;
default:
return;
} }
} }
/** @} */ /* End of Doxygen Group NMSIS_Core_PMP_Functions */ /** @} */ /* End of Doxygen Group NMSIS_Core_PMP_Functions */

73
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/core_feature_timer.h vendored
View File

@@ -102,10 +102,7 @@ typedef struct {
* - Load value is 64bits wide. * - Load value is 64bits wide.
* - \ref SysTimer_GetLoadValue * - \ref SysTimer_GetLoadValue
*/ */
__STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value) __STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value) { SysTimer->MTIMER = value; }
{
SysTimer->MTIMER = value;
}
/** /**
* \brief Get system timer load value * \brief Get system timer load value
@@ -116,10 +113,7 @@ __STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value)
* - Load value is 64bits wide. * - Load value is 64bits wide.
* - \ref SysTimer_SetLoadValue * - \ref SysTimer_SetLoadValue
*/ */
__STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void) __STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void) { return SysTimer->MTIMER; }
{
return SysTimer->MTIMER;
}
/** /**
* \brief Set system timer compare value * \brief Set system timer compare value
@@ -132,10 +126,7 @@ __STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void)
* - Modify the load value or compare value less to clear the interrupt. * - Modify the load value or compare value less to clear the interrupt.
* - \ref SysTimer_GetCompareValue * - \ref SysTimer_GetCompareValue
*/ */
__STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) __STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) { SysTimer->MTIMERCMP = value; }
{
SysTimer->MTIMERCMP = value;
}
/** /**
* \brief Get system timer compare value * \brief Get system timer compare value
@@ -146,10 +137,7 @@ __STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value)
* - Compare value is 64bits wide. * - Compare value is 64bits wide.
* - \ref SysTimer_SetCompareValue * - \ref SysTimer_SetCompareValue
*/ */
__STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void) __STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void) { return SysTimer->MTIMERCMP; }
{
return SysTimer->MTIMERCMP;
}
/** /**
* \brief Enable system timer counter running * \brief Enable system timer counter running
@@ -157,10 +145,7 @@ __STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void)
* Enable system timer counter running by clear * Enable system timer counter running by clear
* TIMESTOP bit in MTIMECTL register. * TIMESTOP bit in MTIMECTL register.
*/ */
__STATIC_FORCEINLINE void SysTimer_Start(void) __STATIC_FORCEINLINE void SysTimer_Start(void) { SysTimer->MTIMECTL &= ~(SysTimer_MTIMECTL_TIMESTOP_Msk); }
{
SysTimer->MTIMECTL &= ~(SysTimer_MTIMECTL_TIMESTOP_Msk);
}
/** /**
* \brief Stop system timer counter running * \brief Stop system timer counter running
@@ -168,10 +153,7 @@ __STATIC_FORCEINLINE void SysTimer_Start(void)
* Stop system timer counter running by set * Stop system timer counter running by set
* TIMESTOP bit in MTIMECTL register. * TIMESTOP bit in MTIMECTL register.
*/ */
__STATIC_FORCEINLINE void SysTimer_Stop(void) __STATIC_FORCEINLINE void SysTimer_Stop(void) { SysTimer->MTIMECTL |= SysTimer_MTIMECTL_TIMESTOP_Msk; }
{
SysTimer->MTIMECTL |= SysTimer_MTIMECTL_TIMESTOP_Msk;
}
/** /**
* \brief Set system timer control value * \brief Set system timer control value
@@ -187,10 +169,7 @@ __STATIC_FORCEINLINE void SysTimer_Stop(void)
* Clear CLKSRC bit to 0 to use *mtime_toggle_a*, otherwise use *core_clk_aon* * Clear CLKSRC bit to 0 to use *mtime_toggle_a*, otherwise use *core_clk_aon*
* - \ref SysTimer_GetControlValue * - \ref SysTimer_GetControlValue
*/ */
__STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl) __STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl) { SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk); }
{
SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk);
}
/** /**
* \brief Get system timer control value * \brief Get system timer control value
@@ -200,10 +179,7 @@ __STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl)
* \remarks * \remarks
* - \ref SysTimer_SetControlValue * - \ref SysTimer_SetControlValue
*/ */
__STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void) __STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void) { return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk); }
{
return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk);
}
/** /**
* \brief Trigger or set software interrupt via system timer * \brief Trigger or set software interrupt via system timer
@@ -214,10 +190,7 @@ __STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void)
* - \ref SysTimer_ClearSWIRQ * - \ref SysTimer_ClearSWIRQ
* - \ref SysTimer_GetMsipValue * - \ref SysTimer_GetMsipValue
*/ */
__STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void) __STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void) { SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk; }
{
SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk;
}
/** /**
* \brief Clear system timer software interrupt pending request * \brief Clear system timer software interrupt pending request
@@ -228,10 +201,7 @@ __STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void)
* - \ref SysTimer_SetSWIRQ * - \ref SysTimer_SetSWIRQ
* - \ref SysTimer_GetMsipValue * - \ref SysTimer_GetMsipValue
*/ */
__STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void) __STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void) { SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk; }
{
SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk;
}
/** /**
* \brief Get system timer MSIP register value * \brief Get system timer MSIP register value
@@ -244,10 +214,7 @@ __STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void)
* - \ref SysTimer_SetSWIRQ * - \ref SysTimer_SetSWIRQ
* - \ref SysTimer_ClearSWIRQ * - \ref SysTimer_ClearSWIRQ
*/ */
__STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void) __STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void) { return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk); }
{
return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk);
}
/** /**
* \brief Set system timer MSIP register value * \brief Set system timer MSIP register value
@@ -255,10 +222,7 @@ __STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void)
* This function set the system timer MSIP register value. * This function set the system timer MSIP register value.
* \param [in] msip value to set MSIP register * \param [in] msip value to set MSIP register
*/ */
__STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip) __STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip) { SysTimer->MSIP = (msip & SysTimer_MSIP_Msk); }
{
SysTimer->MSIP = (msip & SysTimer_MSIP_Msk);
}
/** /**
* \brief Do software reset request * \brief Do software reset request
@@ -270,10 +234,10 @@ __STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip)
* - The software reset is sent to SoC, SoC need to generate reset signal and send back to Core * - The software reset is sent to SoC, SoC need to generate reset signal and send back to Core
* - This function will not return, it will do while(1) to wait the Core reset happened * - This function will not return, it will do while(1) to wait the Core reset happened
*/ */
__STATIC_FORCEINLINE void SysTimer_SoftwareReset(void) __STATIC_FORCEINLINE void SysTimer_SoftwareReset(void) {
{
SysTimer->MSFTRST = SysTimer_MSFRST_KEY; SysTimer->MSFTRST = SysTimer_MSFRST_KEY;
while(1); while (1)
;
} }
#if defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) && defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) #if defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) && defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
@@ -301,8 +265,7 @@ __STATIC_FORCEINLINE void SysTimer_SoftwareReset(void)
* \sa * \sa
* - \ref SysTimer_SetCompareValue; SysTimer_SetLoadValue * - \ref SysTimer_SetCompareValue; SysTimer_SetLoadValue
*/ */
__STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks) __STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks) {
{
SysTimer_SetLoadValue(0); SysTimer_SetLoadValue(0);
SysTimer_SetCompareValue(ticks); SysTimer_SetCompareValue(ticks);
ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT); ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
@@ -334,8 +297,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks)
* - \ref SysTimer_SetCompareValue * - \ref SysTimer_SetCompareValue
* - \ref SysTimer_SetLoadValue * - \ref SysTimer_SetLoadValue
*/ */
__STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks) __STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks) {
{
uint64_t cur_ticks = SysTimer->MTIMER; uint64_t cur_ticks = SysTimer->MTIMER;
uint64_t reload_ticks = ticks + cur_ticks; uint64_t reload_ticks = ticks + cur_ticks;
@@ -361,4 +323,3 @@ __STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks)
} }
#endif #endif
#endif /** __CORE_FEATURE_TIMER_H__ */ #endif /** __CORE_FEATURE_TIMER_H__ */

2
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_compiler.h vendored
View File

@@ -32,6 +32,4 @@
#error Unknown compiler. #error Unknown compiler.
#endif #endif
#endif /* __NMSIS_COMPILER_H */ #endif /* __NMSIS_COMPILER_H */

19
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/nmsis_gcc.h vendored
View File

@@ -22,8 +22,8 @@
* @file nmsis_gcc.h * @file nmsis_gcc.h
* @brief NMSIS compiler GCC header file * @brief NMSIS compiler GCC header file
*/ */
#include <stdint.h>
#include "riscv_encoding.h" #include "riscv_encoding.h"
#include <stdint.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -114,9 +114,7 @@
#pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes" #pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint16_t write access */ /** \brief Packed struct for unaligned uint16_t write access */
__PACKED_STRUCT T_UINT16_WRITE { __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
uint16_t v;
};
#pragma GCC diagnostic pop #pragma GCC diagnostic pop
/** \brief Pointer for unaligned write of a uint16_t variable. */ /** \brief Pointer for unaligned write of a uint16_t variable. */
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
@@ -127,9 +125,7 @@
#pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes" #pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint16_t read access */ /** \brief Packed struct for unaligned uint16_t read access */
__PACKED_STRUCT T_UINT16_READ { __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
uint16_t v;
};
#pragma GCC diagnostic pop #pragma GCC diagnostic pop
/** \brief Pointer for unaligned read of a uint16_t variable. */ /** \brief Pointer for unaligned read of a uint16_t variable. */
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
@@ -140,9 +136,7 @@
#pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes" #pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint32_t write access */ /** \brief Packed struct for unaligned uint32_t write access */
__PACKED_STRUCT T_UINT32_WRITE { __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
uint32_t v;
};
#pragma GCC diagnostic pop #pragma GCC diagnostic pop
/** \brief Pointer for unaligned write of a uint32_t variable. */ /** \brief Pointer for unaligned write of a uint32_t variable. */
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
@@ -153,9 +147,7 @@
#pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes" #pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint32_t read access */ /** \brief Packed struct for unaligned uint32_t read access */
__PACKED_STRUCT T_UINT32_READ { __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
uint32_t v;
};
#pragma GCC diagnostic pop #pragma GCC diagnostic pop
/** \brief Pointer for unaligned read of a uint32_t variable. */ /** \brief Pointer for unaligned read of a uint32_t variable. */
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
@@ -258,7 +250,6 @@
/** @} */ /* end of group NMSIS_Core_PeriphAccess */ /** @} */ /* end of group NMSIS_Core_PeriphAccess */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

1
source/Core/BSP/Pine64/Vendor/NMSIS/Core/Include/riscv_encoding.h vendored
View File

@@ -268,7 +268,6 @@
/** Floating Point Register f0-f31, eg. f0 -> FREG(0) */ /** Floating Point Register f0-f31, eg. f0 -> FREG(0) */
#define FREG(idx) f##idx #define FREG(idx) f##idx
/* === PMP CFG Bits === */ /* === PMP CFG Bits === */
#define PMP_R 0x01 #define PMP_R 0x01
#define PMP_W 0x02 #define PMP_W 0x02

15
source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/portmacro.h vendored
View File

@@ -25,7 +25,6 @@
* 1 tab == 4 spaces! * 1 tab == 4 spaces!
*/ */
#ifndef PORTMACRO_H #ifndef PORTMACRO_H
#define PORTMACRO_H #define PORTMACRO_H
@@ -85,7 +84,9 @@ typedef unsigned long UBaseType_t;
__RWMB(); \ __RWMB(); \
} }
#define portEND_SWITCHING_ISR( xSwitchRequired ) if ( xSwitchRequired != pdFALSE ) portYIELD() #define portEND_SWITCHING_ISR(xSwitchRequired) \
if (xSwitchRequired != pdFALSE) \
portYIELD()
#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x) #define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@@ -137,16 +138,14 @@ not necessary for to use this port. They are defined so the common demo files
extern uint8_t uxMaxSysCallMTH; extern uint8_t uxMaxSysCallMTH;
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortRaiseBASEPRI( void ) portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
{
ECLIC_SetMth(uxMaxSysCallMTH); ECLIC_SetMth(uxMaxSysCallMTH);
__RWMB(); __RWMB();
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static uint8_t ulPortRaiseBASEPRI( void ) portFORCE_INLINE static uint8_t ulPortRaiseBASEPRI(void) {
{
uint8_t ulOriginalBASEPRI; uint8_t ulOriginalBASEPRI;
ulOriginalBASEPRI = ECLIC_GetMth(); ulOriginalBASEPRI = ECLIC_GetMth();
@@ -159,8 +158,7 @@ portFORCE_INLINE static uint8_t ulPortRaiseBASEPRI( void )
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint8_t ulNewMaskValue ) portFORCE_INLINE static void vPortSetBASEPRI(uint8_t ulNewMaskValue) {
{
ECLIC_SetMth(ulNewMaskValue); ECLIC_SetMth(ulNewMaskValue);
__RWMB(); __RWMB();
} }
@@ -173,4 +171,3 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint8_t ulNewMaskValue )
#endif #endif
#endif /* PORTMACRO_H */ #endif /* PORTMACRO_H */

1
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/Include/nuclei_sdk_hal.h vendored
View File

@@ -8,7 +8,6 @@
#include "gd32vf103v_eval.h" #include "gd32vf103v_eval.h"
#ifndef NUCLEI_BANNER #ifndef NUCLEI_BANNER
#define NUCLEI_BANNER 0 #define NUCLEI_BANNER 0
#endif #endif

26
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_core.h vendored
View File

@@ -53,26 +53,22 @@ enum _usb_eptype {
USB_EPTYPE_MASK = 3U, /*!< endpoint type mask */ USB_EPTYPE_MASK = 3U, /*!< endpoint type mask */
}; };
typedef enum typedef enum {
{
USB_OTG_OK = 0, /*!< USB OTG status OK*/ USB_OTG_OK = 0, /*!< USB OTG status OK*/
USB_OTG_FAIL /*!< USB OTG status fail*/ USB_OTG_FAIL /*!< USB OTG status fail*/
} usb_otg_status; } usb_otg_status;
typedef enum typedef enum {
{
USB_OK = 0, /*!< USB status OK*/ USB_OK = 0, /*!< USB status OK*/
USB_FAIL /*!< USB status fail*/ USB_FAIL /*!< USB status fail*/
} usb_status; } usb_status;
typedef enum typedef enum {
{
USB_USE_FIFO, /*!< USB use FIFO transfer mode */ USB_USE_FIFO, /*!< USB use FIFO transfer mode */
USB_USE_DMA /*!< USB use DMA transfer mode */ USB_USE_DMA /*!< USB use DMA transfer mode */
} usb_transfer_mode; } usb_transfer_mode;
typedef struct typedef struct {
{
uint8_t core_enum; /*!< USB core type */ uint8_t core_enum; /*!< USB core type */
uint8_t core_speed; /*!< USB core speed */ uint8_t core_speed; /*!< USB core speed */
uint8_t num_pipe; /*!< USB host channel numbers */ uint8_t num_pipe; /*!< USB host channel numbers */
@@ -86,9 +82,7 @@ typedef struct
/* function declarations */ /* function declarations */
/* config core capabilities */ /* config core capabilities */
usb_status usb_basic_init (usb_core_basic *usb_basic, usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core);
usb_core_regs *usb_regs,
usb_core_enum usb_core);
/*initializes the USB controller registers and prepares the core device mode or host mode operation*/ /*initializes the USB controller registers and prepares the core device mode or host mode operation*/
usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs); usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs);
@@ -97,10 +91,7 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs);
void *usb_rxfifo_read(usb_core_regs *core_regs, uint8_t *dest_buf, uint16_t byte_count); void *usb_rxfifo_read(usb_core_regs *core_regs, uint8_t *dest_buf, uint16_t byte_count);
/* write a packet into the Tx FIFO associated with the endpoint */ /* write a packet into the Tx FIFO associated with the endpoint */
usb_status usb_txfifo_write (usb_core_regs *usb_regs, usb_status usb_txfifo_write(usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count);
uint8_t *src_buf,
uint8_t fifo_num,
uint16_t byte_count);
/* flush a Tx FIFO or all Tx FIFOs */ /* flush a Tx FIFO or all Tx FIFOs */
usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num); usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num);
@@ -109,9 +100,6 @@ usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num);
usb_status usb_rxfifo_flush(usb_core_regs *usb_regs); usb_status usb_rxfifo_flush(usb_core_regs *usb_regs);
/* get the global interrupts */ /* get the global interrupts */
static inline uint32_t usb_coreintr_get(usb_core_regs *usb_regs) static inline uint32_t usb_coreintr_get(usb_core_regs *usb_regs) { return usb_regs->gr->GINTEN & usb_regs->gr->GINTF; }
{
return usb_regs->gr->GINTEN & usb_regs->gr->GINTF;
}
#endif /* __DRV_USB_CORE_H */ #endif /* __DRV_USB_CORE_H */

13
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_dev.h vendored
View File

@@ -75,8 +75,7 @@ typedef struct _usb_control {
uint8_t ctl_zlp; /*!< zero lenth package */ uint8_t ctl_zlp; /*!< zero lenth package */
} usb_control; } usb_control;
typedef struct typedef struct {
{
struct { struct {
uint8_t num : 4; /*!< the endpoint number.it can be from 0 to 6 */ uint8_t num : 4; /*!< the endpoint number.it can be from 0 to 6 */
uint8_t pad : 3; /*!< padding between number and direction */ uint8_t pad : 3; /*!< padding between number and direction */
@@ -101,8 +100,7 @@ typedef struct
typedef struct _usb_core_driver usb_dev; typedef struct _usb_core_driver usb_dev;
typedef struct _usb_class_core typedef struct _usb_class_core {
{
uint8_t command; /*!< device class request command */ uint8_t command; /*!< device class request command */
uint8_t alter_set; /*!< alternative set */ uint8_t alter_set; /*!< alternative set */
@@ -120,8 +118,7 @@ typedef struct _usb_class_core
uint8_t (*incomplete_isoc_out)(usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */ uint8_t (*incomplete_isoc_out)(usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */
} usb_class_core; } usb_class_core;
typedef struct _usb_perp_dev typedef struct _usb_perp_dev {
{
uint8_t config; /*!< configuration */ uint8_t config; /*!< configuration */
uint8_t dev_addr; /*!< device address */ uint8_t dev_addr; /*!< device address */
@@ -138,8 +135,7 @@ typedef struct _usb_perp_dev
usb_class_core *class_core; /*!< class driver */ usb_class_core *class_core; /*!< class driver */
} usb_perp_dev; } usb_perp_dev;
typedef struct _usb_core_driver typedef struct _usb_core_driver {
{
usb_core_basic bp; /*!< USB basic parameters */ usb_core_basic bp; /*!< USB basic parameters */
usb_core_regs regs; /*!< USB registers */ usb_core_regs regs; /*!< USB registers */
usb_perp_dev dev; /*!< USB peripheral device */ usb_perp_dev dev; /*!< USB peripheral device */
@@ -214,4 +210,3 @@ void usb_dev_suspend (usb_core_driver *udev);
void usb_dev_stop(usb_core_driver *udev); void usb_dev_stop(usb_core_driver *udev);
#endif /* __DRV_USB_DEV_H */ #endif /* __DRV_USB_DEV_H */

30
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_host.h vendored
View File

@@ -35,12 +35,11 @@ OF SUCH DAMAGE.
#ifndef __DRV_USB_HOST_H #ifndef __DRV_USB_HOST_H
#define __DRV_USB_HOST_H #define __DRV_USB_HOST_H
#include "drv_usb_core.h"
#include "drv_usb_regs.h" #include "drv_usb_regs.h"
#include "usb_ch9_std.h" #include "usb_ch9_std.h"
#include "drv_usb_core.h"
typedef enum _usb_pipe_status typedef enum _usb_pipe_status {
{
PIPE_IDLE = 0U, PIPE_IDLE = 0U,
PIPE_XF, PIPE_XF,
PIPE_HALTED, PIPE_HALTED,
@@ -53,23 +52,11 @@ typedef enum _usb_pipe_status
PIPE_DTGERR, PIPE_DTGERR,
} usb_pipe_staus; } usb_pipe_staus;
typedef enum _usb_pipe_mode typedef enum _usb_pipe_mode { PIPE_PERIOD = 0U, PIPE_NON_PERIOD = 1U } usb_pipe_mode;
{
PIPE_PERIOD = 0U,
PIPE_NON_PERIOD = 1U
} usb_pipe_mode;
typedef enum _usb_urb_state typedef enum _usb_urb_state { URB_IDLE = 0U, URB_DONE, URB_NOTREADY, URB_ERROR, URB_STALL } usb_urb_state;
{
URB_IDLE = 0U,
URB_DONE,
URB_NOTREADY,
URB_ERROR,
URB_STALL
} usb_urb_state;
typedef struct _usb_pipe typedef struct _usb_pipe {
{
uint8_t in_used; uint8_t in_used;
uint8_t dev_addr; uint8_t dev_addr;
uint32_t dev_speed; uint32_t dev_speed;
@@ -96,9 +83,7 @@ typedef struct _usb_pipe
__IO usb_urb_state urb_state; __IO usb_urb_state urb_state;
} usb_pipe; } usb_pipe;
typedef struct _usb_host_drv {
typedef struct _usb_host_drv
{
uint8_t rx_buf[512U]; uint8_t rx_buf[512U];
__IO uint32_t connect_status; __IO uint32_t connect_status;
__IO uint32_t port_enabled; __IO uint32_t port_enabled;
@@ -107,8 +92,7 @@ typedef struct _usb_host_drv
usb_pipe pipe[USBFS_MAX_TX_FIFOS]; usb_pipe pipe[USBFS_MAX_TX_FIFOS];
} usb_host_drv; } usb_host_drv;
typedef struct _usb_core_driver typedef struct _usb_core_driver {
{
usb_core_basic bp; usb_core_basic bp;
usb_core_regs regs; usb_core_regs regs;

27
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_regs.h vendored
View File

@@ -55,8 +55,7 @@ OF SUCH DAMAGE.
#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */ #define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */
#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */ #define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */
typedef enum typedef enum {
{
USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */ USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */
USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */ USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */
} usb_core_enum; } usb_core_enum;
@@ -74,8 +73,7 @@ enum usb_reg_offset {
USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */ USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */
}; };
typedef struct typedef struct {
{
__IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */ __IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */
__IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */ __IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */
__IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */ __IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */
@@ -96,9 +94,7 @@ typedef struct
__IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */ __IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */
} usb_gr; } usb_gr;
typedef struct {
typedef struct
{
__IO uint32_t HCTL; /*!< USB host control register 400h */ __IO uint32_t HCTL; /*!< USB host control register 400h */
__IO uint32_t HFT; /*!< USB host frame interval register 404h */ __IO uint32_t HFT; /*!< USB host frame interval register 404h */
__IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */ __IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */
@@ -108,8 +104,7 @@ typedef struct
__IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */ __IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */
} usb_hr; } usb_hr;
typedef struct typedef struct {
{
__IO uint32_t HCHCTL; /*!< USB host channel control register 500h */ __IO uint32_t HCHCTL; /*!< USB host channel control register 500h */
__IO uint32_t HCHSTCTL; /*!< Reserved 504h */ __IO uint32_t HCHSTCTL; /*!< Reserved 504h */
__IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */ __IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */
@@ -119,8 +114,7 @@ typedef struct
uint32_t Reserved[2]; uint32_t Reserved[2];
} usb_pr; } usb_pr;
typedef struct typedef struct {
{
__IO uint32_t DCFG; /*!< USB device configuration register 800h */ __IO uint32_t DCFG; /*!< USB device configuration register 800h */
__IO uint32_t DCTL; /*!< USB device control register 804h */ __IO uint32_t DCTL; /*!< USB device control register 804h */
__IO uint32_t DSTAT; /*!< USB device status register 808h */ __IO uint32_t DSTAT; /*!< USB device status register 808h */
@@ -143,8 +137,7 @@ typedef struct
__IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */ __IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */
} usb_dr; } usb_dr;
typedef struct typedef struct {
{
__IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */ __IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */ uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */
__IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */ __IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */
@@ -154,8 +147,7 @@ typedef struct
__IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */ __IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */
} usb_erin; } usb_erin;
typedef struct typedef struct {
{
__IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */ __IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */ uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */
__IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */ __IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */
@@ -164,8 +156,7 @@ typedef struct
__IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */ __IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */
} usb_erout; } usb_erout;
typedef struct _usb_regs typedef struct _usb_regs {
{
usb_gr * gr; /*!< USBFS global registers */ usb_gr * gr; /*!< USBFS global registers */
usb_dr * dr; /*!< Device control and status registers */ usb_dr * dr; /*!< Device control and status registers */
usb_hr * hr; /*!< Host control and status registers */ usb_hr * hr; /*!< Host control and status registers */
@@ -349,7 +340,6 @@ typedef struct _usb_regs
#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ #define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */
#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */
#define TFQSTAT_TXFS BITS(0, 15) #define TFQSTAT_TXFS BITS(0, 15)
#define TFQSTAT_CNUM BITS(27, 30) #define TFQSTAT_CNUM BITS(27, 30)
@@ -425,7 +415,6 @@ typedef struct _usb_regs
/* host channel-x DMA address register bits definitions */ /* host channel-x DMA address register bits definitions */
#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ #define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */
#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ #define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */
#define PORT_SPEED_HIGH PORT_SPEED(0) /*!< high speed */ #define PORT_SPEED_HIGH PORT_SPEED(0) /*!< high speed */

1
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbd_int.h vendored
View File

@@ -49,4 +49,3 @@ uint32_t USBD_OTG_EP1OUT_ISR_Handler (usb_core_driver *udev);
#endif #endif
#endif /* __DRV_USBD_INT_H */ #endif /* __DRV_USBD_INT_H */

3
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbh_int.h vendored
View File

@@ -37,8 +37,7 @@ OF SUCH DAMAGE.
#include "drv_usb_host.h" #include "drv_usb_host.h"
typedef struct _usbh_int_cb typedef struct _usbh_int_cb {
{
uint8_t (*SOF)(usb_core_driver *pudev); uint8_t (*SOF)(usb_core_driver *pudev);
} usbh_int_cb; } usbh_int_cb;

3
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_ch9_std.h vendored
View File

@@ -126,8 +126,7 @@ enum _usbx_type {
#define FEATURE_SELECTOR_EP 0x00 /* USB endpoint feature selector */ #define FEATURE_SELECTOR_EP 0x00 /* USB endpoint feature selector */
#define FEATURE_SELECTOR_DEV 0x01 /* USB device feature selector */ #define FEATURE_SELECTOR_DEV 0x01 /* USB device feature selector */
#define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ #define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
(uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
#define BYTE_LOW(x) ((uint8_t)((x)&0x00FFU)) #define BYTE_LOW(x) ((uint8_t)((x)&0x00FFU))
#define BYTE_HIGH(x) ((uint8_t)(((x)&0xFF00U) >> 8U)) #define BYTE_HIGH(x) ((uint8_t)(((x)&0xFF00U) >> 8U))

3
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_conf.h vendored
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@@ -1,8 +1,8 @@
#ifndef __USB_CONF_H #ifndef __USB_CONF_H
#define __USB_CONF_H #define __USB_CONF_H
#include <stddef.h>
#include "gd32vf103.h" #include "gd32vf103.h"
#include <stddef.h>
//#ifndef USE_USB_FS //#ifndef USE_USB_FS
//#define USE_USB_HS //#define USE_USB_HS
@@ -98,4 +98,3 @@
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
#endif /* __USB_CONF_H */ #endif /* __USB_CONF_H */

1
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_conf.h vendored
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@@ -7,4 +7,3 @@
#define USBD_ITF_MAX_NUM 1 #define USBD_ITF_MAX_NUM 1
#endif /* __USBD_CONF_H */ #endif /* __USBD_CONF_H */

5
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_core.h vendored
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@@ -35,12 +35,10 @@ OF SUCH DAMAGE.
#ifndef __USBD_CORE_H #ifndef __USBD_CORE_H
#define __USBD_CORE_H #define __USBD_CORE_H
#include "drv_usb_core.h" #include "drv_usb_core.h"
#include "drv_usb_dev.h" #include "drv_usb_dev.h"
typedef enum typedef enum {
{
USBD_OK = 0, /*!< status OK */ USBD_OK = 0, /*!< status OK */
USBD_BUSY, /*!< status busy */ USBD_BUSY, /*!< status busy */
USBD_FAIL, /*!< status fail */ USBD_FAIL, /*!< status fail */
@@ -92,4 +90,3 @@ uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr);
uint16_t usbd_rxcount_get(usb_core_driver *udev, uint8_t ep_num); uint16_t usbd_rxcount_get(usb_core_driver *udev, uint8_t ep_num);
#endif /* __USBD_CORE_H */ #endif /* __USBD_CORE_H */

14
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_enum.h vendored
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@@ -35,8 +35,8 @@ OF SUCH DAMAGE.
#ifndef __USBD_ENUM_H #ifndef __USBD_ENUM_H
#define __USBD_ENUM_H #define __USBD_ENUM_H
#include "usbd_core.h"
#include "usbd_conf.h" #include "usbd_conf.h"
#include "usbd_core.h"
#include <wchar.h> #include <wchar.h>
#ifndef NULL #ifndef NULL
@@ -49,8 +49,7 @@ typedef enum _usb_reqsta {
} usb_reqsta; } usb_reqsta;
/* string descriptor index */ /* string descriptor index */
enum _str_index enum _str_index {
{
STR_IDX_LANGID = 0x0U, /* language ID string index */ STR_IDX_LANGID = 0x0U, /* language ID string index */
STR_IDX_MFC = 0x1U, /* manufacturer string index */ STR_IDX_MFC = 0x1U, /* manufacturer string index */
STR_IDX_PRODUCT = 0x2U, /* product string index */ STR_IDX_PRODUCT = 0x2U, /* product string index */
@@ -65,8 +64,7 @@ typedef enum _usb_pwrsta {
USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */ USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */
} usb_pwrsta; } usb_pwrsta;
typedef enum _usb_feature typedef enum _usb_feature {
{
USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */ USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */
USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */ USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */
USB_FEATURE_TEST_MODE = 0x2U /* USB has endpoint test mode feature */ USB_FEATURE_TEST_MODE = 0x2U /* USB has endpoint test mode feature */
@@ -87,9 +85,7 @@ typedef enum _usb_feature
uint8_t _type; \ uint8_t _type; \
wchar_t _data[sizeof(string)]; \ wchar_t _data[sizeof(string)]; \
}) { \ }) { \
sizeof(WIDE_STRING(string)) + 2U - 2U, \ sizeof(WIDE_STRING(string)) + 2U - 2U, USB_DESCTYPE_STR, WIDE_STRING(string) \
USB_DESCTYPE_STR, \
WIDE_STRING(string) \
} }
/* function declarations */ /* function declarations */
@@ -110,5 +106,3 @@ void usbd_enum_error (usb_core_driver *udev, usb_req *req);
void int_to_unicode(uint32_t value, uint8_t *pbuf, uint8_t len); void int_to_unicode(uint32_t value, uint8_t *pbuf, uint8_t len);
#endif /* __USBD_ENUM_H */ #endif /* __USBD_ENUM_H */

1
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_transc.h vendored
View File

@@ -61,4 +61,3 @@ uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num)__attribute__((op
uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num) __attribute__((optimize("O0"))); uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num) __attribute__((optimize("O0")));
#endif /* __USBD_TRANSC_H */ #endif /* __USBD_TRANSC_H */

1
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_conf.h vendored
View File

@@ -6,4 +6,3 @@
#define USBH_MSC_MPS_SIZE 0x200 #define USBH_MSC_MPS_SIZE 0x200
#endif /* __USBH_CONF_H */ #endif /* __USBH_CONF_H */

74
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_core.h vendored
View File

@@ -35,8 +35,8 @@ OF SUCH DAMAGE.
#ifndef __USBH_CORE_H #ifndef __USBH_CORE_H
#define __USBH_CORE_H #define __USBH_CORE_H
#include "usbh_conf.h"
#include "drv_usb_host.h" #include "drv_usb_host.h"
#include "usbh_conf.h"
#define MSC_CLASS 0x08U #define MSC_CLASS 0x08U
#define HID_CLASS 0x03U #define HID_CLASS 0x03U
@@ -48,20 +48,10 @@ OF SUCH DAMAGE.
#define USBH_DEV_ADDR_DEFAULT 0U #define USBH_DEV_ADDR_DEFAULT 0U
#define USBH_DEV_ADDR 1U #define USBH_DEV_ADDR 1U
typedef enum typedef enum { USBH_OK = 0U, USBH_BUSY, USBH_FAIL, USBH_NOT_SUPPORTED, USBH_UNRECOVERED_ERROR, USBH_SPEED_UNKNOWN_ERROR, USBH_APPLY_DEINIT } usbh_status;
{
USBH_OK = 0U,
USBH_BUSY,
USBH_FAIL,
USBH_NOT_SUPPORTED,
USBH_UNRECOVERED_ERROR,
USBH_SPEED_UNKNOWN_ERROR,
USBH_APPLY_DEINIT
} usbh_status;
/* USB host global operation state */ /* USB host global operation state */
typedef enum typedef enum {
{
HOST_DEFAULT = 0U, HOST_DEFAULT = 0U,
HOST_DETECT_DEV_SPEED, HOST_DETECT_DEV_SPEED,
HOST_DEV_ATTACHED, HOST_DEV_ATTACHED,
@@ -75,41 +65,19 @@ typedef enum
} usb_host_state; } usb_host_state;
/* USB host enumeration state */ /* USB host enumeration state */
typedef enum typedef enum { ENUM_DEFAULT = 0U, ENUM_GET_DEV_DESC, ENUM_SET_ADDR, ENUM_GET_CFG_DESC, ENUM_GET_CFG_DESC_SET, ENUM_GET_STR_DESC, ENUM_SET_CONFIGURATION, ENUM_DEV_CONFIGURED } usbh_enum_state;
{
ENUM_DEFAULT = 0U,
ENUM_GET_DEV_DESC,
ENUM_SET_ADDR,
ENUM_GET_CFG_DESC,
ENUM_GET_CFG_DESC_SET,
ENUM_GET_STR_DESC,
ENUM_SET_CONFIGURATION,
ENUM_DEV_CONFIGURED
} usbh_enum_state;
/* USB host control transfer state */ /* USB host control transfer state */
typedef enum typedef enum { CTL_IDLE = 0U, CTL_SETUP, CTL_DATA_IN, CTL_DATA_OUT, CTL_STATUS_IN, CTL_STATUS_OUT, CTL_ERROR, CTL_FINISH } usbh_ctl_state;
{
CTL_IDLE = 0U,
CTL_SETUP,
CTL_DATA_IN,
CTL_DATA_OUT,
CTL_STATUS_IN,
CTL_STATUS_OUT,
CTL_ERROR,
CTL_FINISH
} usbh_ctl_state;
/* user action state */ /* user action state */
typedef enum typedef enum {
{
USBH_USER_NO_RESP = 0U, USBH_USER_NO_RESP = 0U,
USBH_USER_RESP_OK = 1U, USBH_USER_RESP_OK = 1U,
} usbh_user_status; } usbh_user_status;
/* control transfer information */ /* control transfer information */
typedef struct _usbh_control typedef struct _usbh_control {
{
uint8_t pipe_in_num; uint8_t pipe_in_num;
uint8_t pipe_out_num; uint8_t pipe_out_num;
uint8_t max_len; uint8_t max_len;
@@ -124,8 +92,7 @@ typedef struct _usbh_control
} usbh_control; } usbh_control;
/* USB device property */ /* USB device property */
typedef struct typedef struct {
{
uint8_t addr; uint8_t addr;
uint32_t speed; uint32_t speed;
@@ -138,8 +105,7 @@ typedef struct
/** /**
* @brief Device class callbacks * @brief Device class callbacks
*/ */
typedef struct typedef struct {
{
usbh_status (*class_init)(usb_core_driver *pudev, void *phost); usbh_status (*class_init)(usb_core_driver *pudev, void *phost);
void (*class_deinit)(usb_core_driver *pudev, void *phost); void (*class_deinit)(usb_core_driver *pudev, void *phost);
usbh_status (*class_requests)(usb_core_driver *pudev, void *phost); usbh_status (*class_requests)(usb_core_driver *pudev, void *phost);
@@ -149,8 +115,7 @@ typedef struct
/** /**
* @brief User callbacks * @brief User callbacks
*/ */
typedef struct typedef struct {
{
void (*dev_init)(void); void (*dev_init)(void);
void (*dev_deinit)(void); void (*dev_deinit)(void);
void (*dev_attach)(void); void (*dev_attach)(void);
@@ -161,9 +126,7 @@ typedef struct
void (*dev_devdesc_assigned)(void *dev_desc); void (*dev_devdesc_assigned)(void *dev_desc);
void (*dev_address_set)(void); void (*dev_address_set)(void);
void (*dev_cfgdesc_assigned) (usb_desc_config *cfg_desc, void (*dev_cfgdesc_assigned)(usb_desc_config *cfg_desc, usb_desc_itf *itf_desc, usb_desc_ep *ep_desc);
usb_desc_itf *itf_desc,
usb_desc_ep *ep_desc);
void (*dev_mfc_str)(void *mfc_str); void (*dev_mfc_str)(void *mfc_str);
void (*dev_prod_str)(void *prod_str); void (*dev_prod_str)(void *prod_str);
@@ -178,8 +141,7 @@ typedef struct
/** /**
* @brief Host information * @brief Host information
*/ */
typedef struct typedef struct {
{
usb_host_state cur_state; /*!< host state machine value */ usb_host_state cur_state; /*!< host state machine value */
usb_host_state backup_state; /*!< backup of previous state machine value */ usb_host_state backup_state; /*!< backup of previous state machine value */
usbh_enum_state enum_state; /*!< enumeration state machine */ usbh_enum_state enum_state; /*!< enumeration state machine */
@@ -190,7 +152,6 @@ typedef struct
usbh_user_cb * usr_cb; /*!< USB user callback */ usbh_user_cb * usr_cb; /*!< USB user callback */
} usbh_host; } usbh_host;
/* USB host stack initializations */ /* USB host stack initializations */
void usbh_init(usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost); void usbh_init(usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost);
@@ -204,16 +165,9 @@ void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost);
void usbh_error_handler(usbh_host *puhost, usbh_status ErrType); void usbh_error_handler(usbh_host *puhost, usbh_status ErrType);
/* get USB URB state */ /* get USB URB state */
static inline usb_urb_state usbh_urbstate_get (usb_core_driver *pudev, uint8_t pp_num) static inline usb_urb_state usbh_urbstate_get(usb_core_driver *pudev, uint8_t pp_num) { return pudev->host.pipe[pp_num].urb_state; }
{
return pudev->host.pipe[pp_num].urb_state;
}
/* get USB transfer data count */ /* get USB transfer data count */
static inline uint32_t usbh_xfercount_get (usb_core_driver *pudev, uint8_t pp_num) static inline uint32_t usbh_xfercount_get(usb_core_driver *pudev, uint8_t pp_num) { return pudev->host.backup_xfercount[pp_num]; }
{
return pudev->host.backup_xfercount[pp_num];
}
#endif /* __USBH_CORE_H */ #endif /* __USBH_CORE_H */

16
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_enum.h vendored
View File

@@ -51,11 +51,7 @@ usbh_status usbh_devdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint8_t
usbh_status usbh_cfgdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint16_t len); usbh_status usbh_cfgdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint16_t len);
/* get string descriptor from the USB device */ /* get string descriptor from the USB device */
usbh_status usbh_strdesc_get (usb_core_driver *pudev, usbh_status usbh_strdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint8_t str_index, uint8_t *buf, uint16_t len);
usbh_host *puhost,
uint8_t str_index,
uint8_t *buf,
uint16_t len);
/* set the configuration value to the connected device */ /* set the configuration value to the connected device */
usbh_status usbh_setcfg(usb_core_driver *pudev, usbh_host *puhost, uint16_t config); usbh_status usbh_setcfg(usb_core_driver *pudev, usbh_host *puhost, uint16_t config);
@@ -64,15 +60,9 @@ usbh_status usbh_setcfg (usb_core_driver *pudev, usbh_host *puhost, uint16_t con
usbh_status usbh_setaddress(usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr); usbh_status usbh_setaddress(usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr);
/* clear or disable a specific feature */ /* clear or disable a specific feature */
usbh_status usbh_clrfeature (usb_core_driver *pudev, usbh_status usbh_clrfeature(usb_core_driver *pudev, usbh_host *puhost, uint8_t ep_num, uint8_t pp_num);
usbh_host *puhost,
uint8_t ep_num,
uint8_t pp_num);
/* set the interface value to the connected device */ /* set the interface value to the connected device */
usbh_status usbh_setinterface (usb_core_driver *pudev, usbh_status usbh_setinterface(usb_core_driver *pudev, usbh_host *puhost, uint8_t ep_num, uint8_t alter_setting);
usbh_host *puhost,
uint8_t ep_num,
uint8_t alter_setting);
#endif /* __USBH_ENUM_H */ #endif /* __USBH_ENUM_H */

12
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_pipe.h vendored
View File

@@ -54,17 +54,9 @@ uint8_t usbh_pipe_delete (usb_core_driver *pudev);
uint8_t usbh_pipe_free(usb_core_driver *pudev, uint8_t pp_num); uint8_t usbh_pipe_free(usb_core_driver *pudev, uint8_t pp_num);
/* create a pipe */ /* create a pipe */
uint8_t usbh_pipe_create (usb_core_driver *pudev, uint8_t usbh_pipe_create(usb_core_driver *pudev, usb_dev_prop *udev, uint8_t pp_num, uint8_t ep_type, uint16_t ep_mpl);
usb_dev_prop *udev,
uint8_t pp_num,
uint8_t ep_type,
uint16_t ep_mpl);
/* modify a pipe */ /* modify a pipe */
uint8_t usbh_pipe_update (usb_core_driver *pudev, uint8_t usbh_pipe_update(usb_core_driver *pudev, uint8_t pp_num, uint8_t dev_addr, uint32_t dev_speed, uint16_t ep_mpl);
uint8_t pp_num,
uint8_t dev_addr,
uint32_t dev_speed,
uint16_t ep_mpl);
#endif /* __USBH_PIPE_H */ #endif /* __USBH_PIPE_H */

1
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_transc.h vendored
View File

@@ -51,4 +51,3 @@ usbh_status usbh_data_recev (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_nu
usbh_status usbh_ctl_handler(usb_core_driver *pudev, usbh_host *puhost); usbh_status usbh_ctl_handler(usb_core_driver *pudev, usbh_host *puhost);
#endif /* __USBH_TRANSC_H */ #endif /* __USBH_TRANSC_H */

48
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103.h vendored
View File

@@ -36,25 +36,19 @@ extern "C" {
* @{ * @{
*/ */
/** @addtogroup gd32vf103 /** @addtogroup gd32vf103
* @{ * @{
*/ */
/** @addtogroup Configuration_of_NMSIS /** @addtogroup Configuration_of_NMSIS
* @{ * @{
*/ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */ /* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
typedef enum IRQn typedef enum IRQn {
{
/* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */ /* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */
Reserved0_IRQn = 0, /*!< Internal reserved */ Reserved0_IRQn = 0, /*!< Internal reserved */
@@ -199,14 +193,11 @@ typedef enum EXCn {
/** @} */ /* End of group Configuration_of_CMSIS */ /** @} */ /* End of group Configuration_of_CMSIS */
#include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */ #include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */
/* ToDo: include your system_nuclei_soc.h file /* ToDo: include your system_nuclei_soc.h file
replace 'Device' with your device name */ replace 'Device' with your device name */
#include "system_gd32vf103.h" /*!< gd32vf103 System */ #include "system_gd32vf103.h" /*!< gd32vf103 System */
/* ======================================== Start of section using anonymous unions ======================================== */ /* ======================================== Start of section using anonymous unions ======================================== */
#if defined(__GNUC__) #if defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
@@ -214,7 +205,6 @@ typedef enum EXCn {
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/* system frequency define */ /* system frequency define */
#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ #define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ #define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
@@ -222,39 +212,23 @@ typedef enum EXCn {
#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) #define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
#define RTC_FREQ LXTAL_VALUE #define RTC_FREQ LXTAL_VALUE
// The TIMER frequency is just the RTC frequency // The TIMER frequency is just the RTC frequency
#define SOC_TIMER_FREQ ((uint32_t)SystemCoreClock / 4) // LXTAL_VALUE units HZ #define SOC_TIMER_FREQ ((uint32_t)SystemCoreClock / 4) // LXTAL_VALUE units HZ
/* enum definitions */ /* enum definitions */
typedef enum { typedef enum { DISABLE = 0, ENABLE = !DISABLE } EventStatus, ControlStatus;
DISABLE = 0,
ENABLE = !DISABLE
} EventStatus, ControlStatus;
typedef enum { typedef enum { FALSE = 0, TRUE = !FALSE } BOOL;
FALSE = 0,
TRUE = !FALSE
} BOOL;
typedef enum { typedef enum { RESET = 0, SET = 1, MAX = 0X7FFFFFFF } FlagStatus;
RESET = 0,
SET = 1,
MAX = 0X7FFFFFFF
} FlagStatus;
typedef enum { typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrStatus;
ERROR = 0,
SUCCESS = !ERROR
} ErrStatus;
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */ /* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals /** @addtogroup Device_Peripheral_peripherals
* @{ * @{
*/ */
@@ -263,10 +237,6 @@ typedef enum {
* Platform definitions * Platform definitions
*****************************************************************************/ *****************************************************************************/
/* ToDo: add here your device specific peripheral access structure typedefs /* ToDo: add here your device specific peripheral access structure typedefs
following is an example for Systick Timer*/ following is an example for Systick Timer*/
@@ -276,7 +246,6 @@ typedef enum {
/*@}*/ /* end of group nuclei_soc_Peripherals */ /*@}*/ /* end of group nuclei_soc_Peripherals */
/* ========================================= End of section using anonymous unions ========================================= */ /* ========================================= End of section using anonymous unions ========================================= */
#if defined(__GNUC__) #if defined(__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */
@@ -284,12 +253,10 @@ typedef enum {
#warning Not supported compiler type #warning Not supported compiler type
#endif #endif
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */ /* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ToDo: add here your device peripherals base addresses /* ToDo: add here your device peripherals base addresses
following is an example for timer */ following is an example for timer */
/** @addtogroup Device_Peripheral_peripheralAddr /** @addtogroup Device_Peripheral_peripheralAddr
@@ -334,15 +301,12 @@ typedef enum {
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
/** @} */ /* End of group Device_Peripheral_peripheralAddr */ /** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */ /* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ToDo: add here your device peripherals pointer definitions /* ToDo: add here your device peripherals pointer definitions
following is an example for timer */ following is an example for timer */
/** @addtogroup Device_Peripheral_declaration /** @addtogroup Device_Peripheral_declaration
@@ -360,7 +324,6 @@ typedef enum {
#define SOC_ECLIC_NUM_INTERRUPTS 86 #define SOC_ECLIC_NUM_INTERRUPTS 86
#define SOC_ECLIC_INT_GPIO_BASE 19 #define SOC_ECLIC_INT_GPIO_BASE 19
// Interrupt Handler Definitions // Interrupt Handler Definitions
#define SOC_MTIMER_HANDLER eclic_mtip_handler #define SOC_MTIMER_HANDLER eclic_mtip_handler
#define SOC_SOFTINT_HANDLER eclic_msip_handler #define SOC_SOFTINT_HANDLER eclic_msip_handler
@@ -377,7 +340,6 @@ extern uint32_t get_cpu_freq(void);
*/ */
extern void delay_1ms(uint32_t count); extern void delay_1ms(uint32_t count);
/** @} */ /* End of group gd32vf103_soc */ /** @} */ /* End of group gd32vf103_soc */
/** @} */ /* End of group gd32vf103 */ /** @} */ /* End of group gd32vf103 */

3
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_adc.h vendored
View File

@@ -36,14 +36,13 @@ OF SUCH DAMAGE.
#define GD32VF103_ADC_H #define GD32VF103_ADC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* ADC definitions */ /* ADC definitions */
#define ADC0 ADC_BASE #define ADC0 ADC_BASE
#define ADC1 (ADC_BASE + 0x400U) #define ADC1 (ADC_BASE + 0x400U)
/* registers definitions */ /* registers definitions */
#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ #define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ #define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */

5
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_bkp.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_BKP_H #define GD32VF103_BKP_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* BKP definitions */ /* BKP definitions */
#define BKP BKP_BASE /*!< BKP base address */ #define BKP BKP_BASE /*!< BKP base address */
@@ -112,8 +112,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* BKP data register number */ /* BKP data register number */
typedef enum typedef enum {
{
BKP_DATA_0 = 1, /*!< BKP data register 0 */ BKP_DATA_0 = 1, /*!< BKP data register 0 */
BKP_DATA_1, /*!< BKP data register 1 */ BKP_DATA_1, /*!< BKP data register 1 */
BKP_DATA_2, /*!< BKP data register 2 */ BKP_DATA_2, /*!< BKP data register 2 */

18
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_can.h vendored
View File

@@ -36,14 +36,13 @@ OF SUCH DAMAGE.
#define GD32VF103_CAN_H #define GD32VF103_CAN_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* CAN definitions */ /* CAN definitions */
#define CAN0 CAN_BASE /*!< CAN0 base address */ #define CAN0 CAN_BASE /*!< CAN0 base address */
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ #define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
/* registers definitions */ /* registers definitions */
#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ #define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */
#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ #define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */
@@ -659,8 +658,7 @@ void can_deinit(uint32_t can_periph);
/* initialize CAN struct */ /* initialize CAN struct */
void can_struct_para_init(can_struct_type_enum type, void *p_struct); void can_struct_para_init(can_struct_type_enum type, void *p_struct);
/* initialize CAN */ /* initialize CAN */
ErrStatus can_init(uint32_t can_periph, ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init);
can_parameter_struct* can_parameter_init);
/* CAN filter init */ /* CAN filter init */
void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init); void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init);
/* set can1 fliter start bank number */ /* set can1 fliter start bank number */
@@ -677,16 +675,13 @@ void can_time_trigger_mode_disable(uint32_t can_periph);
/* transmit functions */ /* transmit functions */
/* transmit CAN message */ /* transmit CAN message */
uint8_t can_message_transmit(uint32_t can_periph, uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message);
can_trasnmit_message_struct* transmit_message);
/* get CAN transmit state */ /* get CAN transmit state */
can_transmit_state_enum can_transmit_states(uint32_t can_periph, can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
uint8_t mailbox_number);
/* stop CAN transmission */ /* stop CAN transmission */
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
/* CAN receive message */ /* CAN receive message */
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message);
can_receive_message_struct* receive_message);
/* CAN release fifo */ /* CAN release fifo */
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
/* CAN receive message length */ /* CAN receive message length */
@@ -712,8 +707,7 @@ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
/* CAN clear flag state */ /* CAN clear flag state */
void can_flag_clear(uint32_t can_periph, can_flag_enum flag); void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
/* CAN get interrupt flag state */ /* CAN get interrupt flag state */
FlagStatus can_interrupt_flag_get(uint32_t can_periph, FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
can_interrupt_flag_enum flag);
/* CAN clear interrupt flag state */ /* CAN clear interrupt flag state */
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);

2
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_crc.h vendored
View File

@@ -37,8 +37,8 @@ OF SUCH DAMAGE.
#define GD32VF103_CRC_H #define GD32VF103_CRC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* CRC definitions */ /* CRC definitions */
#define CRC CRC_BASE #define CRC CRC_BASE

2
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dac.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_DAC_H #define GD32VF103_DAC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* DACx(x=0,1) definitions */ /* DACx(x=0,1) definitions */
#define DAC DAC_BASE #define DAC DAC_BASE

4
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dbg.h vendored
View File

@@ -38,7 +38,6 @@ OF SUCH DAMAGE.
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h" #include "gd32vf103_rcu.h"
/* DBG definitions */ /* DBG definitions */
#define DBG DBG_BASE #define DBG DBG_BASE
@@ -70,8 +69,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* debug hold when core is halted */ /* debug hold when core is halted */
typedef enum typedef enum {
{
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */

12
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dma.h vendored
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@@ -36,9 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_DMA_H #define GD32VF103_DMA_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* DMA definitions */ /* DMA definitions */
#define DMA0 (DMA_BASE) /*!< DMA0 base address */ #define DMA0 (DMA_BASE) /*!< DMA0 base address */
@@ -121,8 +120,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* DMA channel select */ /* DMA channel select */
typedef enum typedef enum {
{
DMA_CH0 = 0, /*!< DMA Channel0 */ DMA_CH0 = 0, /*!< DMA Channel0 */
DMA_CH1, /*!< DMA Channel1 */ DMA_CH1, /*!< DMA Channel1 */
DMA_CH2, /*!< DMA Channel2 */ DMA_CH2, /*!< DMA Channel2 */
@@ -133,8 +131,7 @@ typedef enum
} dma_channel_enum; } dma_channel_enum;
/* DMA initialize struct */ /* DMA initialize struct */
typedef struct typedef struct {
{
uint32_t periph_addr; /*!< peripheral base address */ uint32_t periph_addr; /*!< peripheral base address */
uint32_t periph_width; /*!< transfer data size of peripheral */ uint32_t periph_width; /*!< transfer data size of peripheral */
uint32_t memory_addr; /*!< memory base address */ uint32_t memory_addr; /*!< memory base address */
@@ -160,8 +157,7 @@ typedef struct
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ #define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
/* DMA_INTF register */ /* DMA_INTF register */
/* interrupt flag bits */ /* interrupt flag bits */

9
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exmc.h vendored
View File

@@ -36,9 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_EXMC_H #define GD32VF103_EXMC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* EXMC definitions */ /* EXMC definitions */
#define EXMC (EXMC_BASE) /*!< EXMC register base address */ #define EXMC (EXMC_BASE) /*!< EXMC register base address */
@@ -70,8 +69,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* EXMC NOR/SRAM timing initialize struct */ /* EXMC NOR/SRAM timing initialize struct */
typedef struct typedef struct {
{
uint32_t bus_latency; /*!< configure the bus latency */ uint32_t bus_latency; /*!< configure the bus latency */
uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
@@ -79,8 +77,7 @@ typedef struct
} exmc_norsram_timing_parameter_struct; } exmc_norsram_timing_parameter_struct;
/* EXMC NOR/SRAM initialize struct */ /* EXMC NOR/SRAM initialize struct */
typedef struct typedef struct {
{
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */ uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */

3
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exti.h vendored
View File

@@ -36,9 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_EXTI_H #define GD32VF103_EXTI_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* EXTI definitions */ /* EXTI definitions */
#define EXTI EXTI_BASE #define EXTI EXTI_BASE

15
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fmc.h vendored
View File

@@ -36,9 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_FMC_H #define GD32VF103_FMC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* FMC and option byte definition */ /* FMC and option byte definition */
#define FMC FMC_BASE /*!< FMC register base address */ #define FMC FMC_BASE /*!< FMC register base address */
@@ -125,8 +124,7 @@ OF SUCH DAMAGE.
#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ #define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
/* fmc state */ /* fmc state */
typedef enum typedef enum {
{
FMC_READY, /*!< the operation has been completed */ FMC_READY, /*!< the operation has been completed */
FMC_BUSY, /*!< the operation is in progress */ FMC_BUSY, /*!< the operation is in progress */
FMC_PGERR, /*!< program error */ FMC_PGERR, /*!< program error */
@@ -135,15 +133,13 @@ typedef enum
} fmc_state_enum; } fmc_state_enum;
/* FMC interrupt enable */ /* FMC interrupt enable */
typedef enum typedef enum {
{
FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
} fmc_int_enum; } fmc_int_enum;
/* FMC flags */ /* FMC flags */
typedef enum typedef enum {
{
FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC busy flag */ FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC busy flag */
FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC operation error flag bit */ FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC operation error flag bit */
FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */ FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */
@@ -152,8 +148,7 @@ typedef enum
} fmc_flag_enum; } fmc_flag_enum;
/* FMC interrupt flags */ /* FMC interrupt flags */
typedef enum typedef enum {
{
FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */ FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */
FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */ FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */
FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */ FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */

3
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fwdgt.h vendored
View File

@@ -36,9 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_FWDGT_H #define GD32VF103_FWDGT_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* FWDGT definitions */ /* FWDGT definitions */
#define FWDGT FWDGT_BASE /*!< FWDGT base address */ #define FWDGT FWDGT_BASE /*!< FWDGT base address */

2
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_gpio.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_GPIO_H #define GD32VF103_GPIO_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* GPIOx(x=A,B,C,D,E) definitions */ /* GPIOx(x=A,B,C,D,E) definitions */
#define GPIOA (GPIO_BASE + 0x00000000U) #define GPIOA (GPIO_BASE + 0x00000000U)

5
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_i2c.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_I2C_H #define GD32VF103_I2C_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* I2Cx(x=0,1) definitions */ /* I2Cx(x=0,1) definitions */
#define I2C0 I2C_BASE /*!< I2C0 base address */ #define I2C0 I2C_BASE /*!< I2C0 base address */
@@ -131,8 +131,7 @@ OF SUCH DAMAGE.
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset)&0xFFFFU) >> 6))) #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset)&0xFFFFU) >> 6)))
#define I2C_BIT_POS(val) ((uint32_t)(val)&0x1FU) #define I2C_BIT_POS(val) ((uint32_t)(val)&0x1FU)
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ #define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
#define I2C_BIT_POS2(val) (((uint32_t)(val)&0x1F0000U) >> 16) #define I2C_BIT_POS2(val) (((uint32_t)(val)&0x1F0000U) >> 16)

6
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_libopt.h vendored
View File

@@ -43,14 +43,15 @@ extern "C" {
#include "gd32vf103_can.h" #include "gd32vf103_can.h"
#include "gd32vf103_crc.h" #include "gd32vf103_crc.h"
#include "gd32vf103_dac.h" #include "gd32vf103_dac.h"
#include "gd32vf103_dbg.h"
#include "gd32vf103_dma.h" #include "gd32vf103_dma.h"
#include "gd32vf103_eclic.h"
#include "gd32vf103_exmc.h" #include "gd32vf103_exmc.h"
#include "gd32vf103_exti.h" #include "gd32vf103_exti.h"
#include "gd32vf103_fmc.h" #include "gd32vf103_fmc.h"
#include "gd32vf103_fwdgt.h"
#include "gd32vf103_gpio.h" #include "gd32vf103_gpio.h"
#include "gd32vf103_i2c.h" #include "gd32vf103_i2c.h"
#include "gd32vf103_fwdgt.h"
#include "gd32vf103_dbg.h"
#include "gd32vf103_pmu.h" #include "gd32vf103_pmu.h"
#include "gd32vf103_rcu.h" #include "gd32vf103_rcu.h"
#include "gd32vf103_rtc.h" #include "gd32vf103_rtc.h"
@@ -58,7 +59,6 @@ extern "C" {
#include "gd32vf103_timer.h" #include "gd32vf103_timer.h"
#include "gd32vf103_usart.h" #include "gd32vf103_usart.h"
#include "gd32vf103_wwdgt.h" #include "gd32vf103_wwdgt.h"
#include "gd32vf103_eclic.h"
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_pmu.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_PMU_H #define GD32VF103_PMU_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* PMU definitions */ /* PMU definitions */
#define PMU PMU_BASE /*!< PMU base address */ #define PMU PMU_BASE /*!< PMU base address */

4
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rcu.h vendored
View File

@@ -56,7 +56,6 @@ OF SUCH DAMAGE.
#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ #define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */
#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ #define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */
/* bits definitions */ /* bits definitions */
/* RCU_CTL */ /* RCU_CTL */
#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */
@@ -74,7 +73,6 @@ OF SUCH DAMAGE.
#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ #define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */
#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */
#define RCU_CFG0_SCS BITS(0, 1) /*!< system clock switch */ #define RCU_CFG0_SCS BITS(0, 1) /*!< system clock switch */
#define RCU_CFG0_SCSS BITS(2, 3) /*!< system clock switch status */ #define RCU_CFG0_SCSS BITS(2, 3) /*!< system clock switch status */
#define RCU_CFG0_AHBPSC BITS(4, 7) /*!< AHB prescaler selection */ #define RCU_CFG0_AHBPSC BITS(4, 7) /*!< AHB prescaler selection */
@@ -639,7 +637,6 @@ typedef enum {
#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ #define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */
#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ #define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */
/* PREDV0 input clock source selection */ /* PREDV0 input clock source selection */
#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */ #define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */
#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ #define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */
@@ -652,7 +649,6 @@ typedef enum {
#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ #define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */
#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ #define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */
/* deep-sleep mode voltage */ /* deep-sleep mode voltage */
#define DSV_DSLPVS(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0)) #define DSV_DSLPVS(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0))
#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ #define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */

2
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rtc.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_RTC_H #define GD32VF103_RTC_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* RTC definitions */ /* RTC definitions */
#define RTC RTC_BASE #define RTC RTC_BASE

5
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_spi.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_SPI_H #define GD32VF103_SPI_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* SPIx(x=0,1,2) definitions */ /* SPIx(x=0,1,2) definitions */
#define SPI0 (SPI_BASE + 0x0000F800U) #define SPI0 (SPI_BASE + 0x0000F800U)
@@ -122,8 +122,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* SPI and I2S parameter struct definitions */ /* SPI and I2S parameter struct definitions */
typedef struct typedef struct {
{
uint32_t device_mode; /*!< SPI master or slave */ uint32_t device_mode; /*!< SPI master or slave */
uint32_t trans_mode; /*!< SPI transtype */ uint32_t trans_mode; /*!< SPI transtype */
uint32_t frame_size; /*!< SPI frame size */ uint32_t frame_size; /*!< SPI frame size */

15
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_timer.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_TIMER_H #define GD32VF103_TIMER_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* TIMERx(x=0..13) definitions */ /* TIMERx(x=0..13) definitions */
#define TIMER0 (TIMER_BASE + 0x00012C00U) #define TIMER0 (TIMER_BASE + 0x00012C00U)
@@ -240,8 +240,7 @@ OF SUCH DAMAGE.
/* constants definitions */ /* constants definitions */
/* TIMER init parameter struct definitions */ /* TIMER init parameter struct definitions */
typedef struct typedef struct {
{
uint16_t prescaler; /*!< prescaler value */ uint16_t prescaler; /*!< prescaler value */
uint16_t alignedmode; /*!< aligned mode */ uint16_t alignedmode; /*!< aligned mode */
uint16_t counterdirection; /*!< counter direction */ uint16_t counterdirection; /*!< counter direction */
@@ -251,8 +250,7 @@ typedef struct
} timer_parameter_struct; } timer_parameter_struct;
/* break parameter struct definitions */ /* break parameter struct definitions */
typedef struct typedef struct {
{
uint16_t runoffstate; /*!< run mode off-state */ uint16_t runoffstate; /*!< run mode off-state */
uint16_t ideloffstate; /*!< idle mode off-state */ uint16_t ideloffstate; /*!< idle mode off-state */
uint16_t deadtime; /*!< dead time */ uint16_t deadtime; /*!< dead time */
@@ -263,8 +261,7 @@ typedef struct
} timer_break_parameter_struct; } timer_break_parameter_struct;
/* channel output parameter struct definitions */ /* channel output parameter struct definitions */
typedef struct typedef struct {
{
uint16_t outputstate; /*!< channel output state */ uint16_t outputstate; /*!< channel output state */
uint16_t outputnstate; /*!< channel complementary output state */ uint16_t outputnstate; /*!< channel complementary output state */
uint16_t ocpolarity; /*!< channel output polarity */ uint16_t ocpolarity; /*!< channel output polarity */
@@ -274,8 +271,7 @@ typedef struct
} timer_oc_parameter_struct; } timer_oc_parameter_struct;
/* channel input parameter struct definitions */ /* channel input parameter struct definitions */
typedef struct typedef struct {
{
uint16_t icpolarity; /*!< channel input polarity */ uint16_t icpolarity; /*!< channel input polarity */
uint16_t icselection; /*!< channel input mode selection */ uint16_t icselection; /*!< channel input mode selection */
uint16_t icprescaler; /*!< channel input capture prescaler */ uint16_t icprescaler; /*!< channel input capture prescaler */
@@ -415,7 +411,6 @@ typedef struct
#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ #define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */
/* idle mode off-state configure */ /* idle mode off-state configure */
#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ #define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */

14
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_usart.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_USART_H #define GD32VF103_USART_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ /* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */
#define USART1 USART_BASE /*!< USART1 base address */ #define USART1 USART_BASE /*!< USART1 base address */
@@ -124,8 +124,7 @@ OF SUCH DAMAGE.
#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6))) #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6)))
#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU)) #define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU))
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16) #define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16)
@@ -136,8 +135,7 @@ OF SUCH DAMAGE.
#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */ #define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */
/* USART flags */ /* USART flags */
typedef enum typedef enum {
{
/* flags in STAT register */ /* flags in STAT register */
USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
@@ -152,8 +150,7 @@ typedef enum
} usart_flag_enum; } usart_flag_enum;
/* USART interrupt flags */ /* USART interrupt flags */
typedef enum typedef enum {
{
/* interrupt flags in CTL0 register */ /* interrupt flags in CTL0 register */
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
@@ -171,8 +168,7 @@ typedef enum
} usart_interrupt_flag_enum; } usart_interrupt_flag_enum;
/* USART interrupt enable or disable */ /* USART interrupt enable or disable */
typedef enum typedef enum {
{
/* interrupt in CTL0 register */ /* interrupt in CTL0 register */
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */

2
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_wwdgt.h vendored
View File

@@ -36,8 +36,8 @@ OF SUCH DAMAGE.
#define GD32VF103_WWDGT_H #define GD32VF103_WWDGT_H
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_dbg.h" #include "gd32vf103_dbg.h"
#include "gd32vf103_rcu.h"
/* WWDGT definitions */ /* WWDGT definitions */
#define WWDGT WWDGT_BASE /*!< WWDGT base address */ #define WWDGT WWDGT_BASE /*!< WWDGT base address */

1
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Include/nuclei_sdk_soc.h vendored
View File

@@ -9,7 +9,6 @@
#include "gd32vf103.h" #include "gd32vf103.h"
#include "gd32vf103_libopt.h" #include "gd32vf103_libopt.h"
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

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