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Trying to chase down why __libc_init_array isnt working yet

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This commit is contained in:
Ben V. Brown
2022-04-18 22:27:25 +10:00
parent ecf36b9b0a
commit bb28bb45b5
8 changed files with 202 additions and 131 deletions
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64
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld
View File

@@ -80,6 +80,70 @@ SECTIONS
__text_code_end__ = .;
} > xip_memory
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >xip_memory AT>xip_memory
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >xip_memory AT>xip_memory
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >xip_memory AT>xip_memory
.ctors :
{
/* gcc uses crtbegin.o to find the start of
* the constructors, so we make sure it is
* first. Because this is a wildcard, it
* doesn't matter if the user does not
* actually link against crtbegin.o; the
* linker won't look for a file to match a
* wildcard. The wildcard also means that it
* doesn't matter which directory crtbegin.o
* is in.
*/
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
* the crtend.o file until after the sorted ctors.
* The .ctor section from the crtend file contains the
* end of ctors marker and it must be last
*/
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >xip_memory AT>xip_memory
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >xip_memory AT>xip_memory
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >xip_memory AT>xip_memory
. = ALIGN(4);
__itcm_load_addr = .;

9
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/entry.S
View File

@@ -78,11 +78,20 @@ _enter:
/* start load code to itcm like. */
call start_load
// Register at exit cleanup (not required for embedded)
// la a0, __libc_fini_array
// call atexit
/* Call C/C++ constructor start up code */
call __libc_init_array
jal System_Post_Init
/* At this point we can enter the C runtime's startup file. The arguments
* to this function are designed to match those provided to the SEE, just
* so we don't have to write another ABI. */
//Sets argv,argc to 0/null
csrr a0, mhartid
li a1, 0
li a2, 0

93
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/start_load.c
View File

@@ -21,8 +21,8 @@
*
*/
#include <stdint.h>
#include "bl702.h"
#include <stdint.h>
#define __STARTUP_CLEAR_BSS 1
@@ -54,62 +54,61 @@ extern uint32_t __StackLimit;
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;
//extern uint32_t __copy_table_start__;
//extern uint32_t __copy_table_end__;
//extern uint32_t __zero_table_start__;
//extern uint32_t __zero_table_end__;
// extern uint32_t __copy_table_start__;
// extern uint32_t __copy_table_end__;
// extern uint32_t __zero_table_start__;
// extern uint32_t __zero_table_end__;
void start_load(void)
{
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
void start_load(void) {
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
/* Copy ITCM code */
pSrc = &__itcm_load_addr;
pDest = &__tcm_code_start__;
/* Copy ITCM code */
pSrc = &__itcm_load_addr;
pDest = &__tcm_code_start__;
for (; pDest < &__tcm_code_end__;) {
*pDest++ = *pSrc++;
}
for (; pDest < &__tcm_code_end__;) {
*pDest++ = *pSrc++;
}
/* Copy DTCM code */
pSrc = &__dtcm_load_addr;
pDest = &__tcm_data_start__;
/* Copy DTCM code */
pSrc = &__dtcm_load_addr;
pDest = &__tcm_data_start__;
for (; pDest < &__tcm_data_end__;) {
*pDest++ = *pSrc++;
}
for (; pDest < &__tcm_data_end__;) {
*pDest++ = *pSrc++;
}
/* BF Add system RAM data copy */
pSrc = &__system_ram_load_addr;
pDest = &__system_ram_data_start__;
/* BF Add system RAM data copy */
pSrc = &__system_ram_load_addr;
pDest = &__system_ram_data_start__;
for (; pDest < &__system_ram_data_end__;) {
*pDest++ = *pSrc++;
}
for (; pDest < &__system_ram_data_end__;) {
*pDest++ = *pSrc++;
}
/* BF Add OCARAM data copy */
pSrc = &__ram_load_addr;
pDest = &__ram_data_start__;
/* BF Add OCARAM data copy */
pSrc = &__ram_load_addr;
pDest = &__ram_data_start__;
for (; pDest < &__ram_data_end__;) {
*pDest++ = *pSrc++;
}
for (; pDest < &__ram_data_end__;) {
*pDest++ = *pSrc++;
}
#ifdef __STARTUP_CLEAR_BSS
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
// #ifdef __STARTUP_CLEAR_BSS
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
for (; pDest < &__bss_end__;) {
*pDest++ = 0ul;
}
for (; pDest < &__bss_end__;) {
*pDest++ = 0ul;
}
#endif
// #endif
}

155
source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c
View File

@@ -27,10 +27,9 @@
#ifdef BFLB_EFLASH_LOADER
#include "bl702_usb.h"
void USB_DoNothing_IRQHandler(void)
{
/* clear all USB int sts */
USB_Clr_IntStatus(32);
void USB_DoNothing_IRQHandler(void) {
/* clear all USB int sts */
USB_Clr_IntStatus(32);
}
#endif
@@ -42,101 +41,99 @@ void USB_DoNothing_IRQHandler(void)
/*----------------------------------------------------------------------------
Vector Table
*----------------------------------------------------------------------------*/
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET \
0x00 /*!< Vector Table base offset field. \
This value must be a multiple of 0x200. */
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void system_bor_init(void)
{
HBN_BOR_CFG_Type borCfg = { 0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */ };
HBN_Set_BOR_Cfg(&borCfg);
void system_bor_init(void) {
HBN_BOR_CFG_Type borCfg = {0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */};
HBN_Set_BOR_Cfg(&borCfg);
}
void SystemInit(void)
{
uint32_t *p;
uint32_t i = 0;
uint32_t tmpVal = 0;
uint8_t flashCfg = 0;
uint8_t psramCfg = 0;
uint8_t isInternalFlash = 0;
uint8_t isInternalPsram = 0;
void SystemInit(void) {
uint32_t *p;
uint32_t i = 0;
uint32_t tmpVal = 0;
uint8_t flashCfg = 0;
uint8_t psramCfg = 0;
uint8_t isInternalFlash = 0;
uint8_t isInternalPsram = 0;
/* global IRQ disable */
__disable_irq();
/* global IRQ disable */
__disable_irq();
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
tmpVal |= (1 << 8); /*mask pds wakeup*/
tmpVal |= (1 << 10); /*mask rf done*/
tmpVal |= (1 << 11); /*mask pll done*/
tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
tmpVal |= (1 << 8); /*mask pds wakeup*/
tmpVal |= (1 << 10); /*mask rf done*/
tmpVal |= (1 << 11); /*mask pll done*/
tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
/* GLB_Set_EM_Sel(GLB_EM_0KB); */
tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, GLB_EM_0KB);
BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
/* GLB_Set_EM_Sel(GLB_EM_0KB); */
tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, GLB_EM_0KB);
BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
/* Restore default setting*/
/* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE);
BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
/* Restore default setting*/
/* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE);
BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
/* fix 57.6M */
if (SystemCoreClockGet() == 57 * 6000 * 1000) {
SystemCoreClockSet(57.6 * 1000 * 1000)
}
/* fix 57.6M */
if (SystemCoreClockGet() == 57 * 6000 * 1000) {
SystemCoreClockSet(57.6 * 1000 * 1000)
}
/* CLear all interrupt */
p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE);
/* CLear all interrupt */
p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE);
for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
p[i] = 0;
}
for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
p[i] = 0;
}
p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIP);
p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIP);
for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
p[i] = 0;
}
for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
p[i] = 0;
}
/* SF io select from efuse value */
tmpVal = BL_RD_WORD(0x40007074);
flashCfg = ((tmpVal >> 26) & 7);
psramCfg = ((tmpVal >> 24) & 3);
if (flashCfg == 1 || flashCfg == 2) {
isInternalFlash = 1;
} else {
isInternalFlash = 0;
}
if (psramCfg == 1) {
isInternalPsram = 1;
} else {
isInternalPsram = 0;
}
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
if (isInternalFlash == 1 && isInternalPsram == 0) {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
} else {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
}
BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
/* SF io select from efuse value */
tmpVal = BL_RD_WORD(0x40007074);
flashCfg = ((tmpVal >> 26) & 7);
psramCfg = ((tmpVal >> 24) & 3);
if (flashCfg == 1 || flashCfg == 2) {
isInternalFlash = 1;
} else {
isInternalFlash = 0;
}
if (psramCfg == 1) {
isInternalPsram = 1;
} else {
isInternalPsram = 0;
}
tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
if (isInternalFlash == 1 && isInternalPsram == 0) {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
} else {
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
}
BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
#ifdef BFLB_EFLASH_LOADER
Interrupt_Handler_Register(USB_IRQn, USB_DoNothing_IRQHandler);
Interrupt_Handler_Register(USB_IRQn, USB_DoNothing_IRQHandler);
#endif
/* init bor for all platform */
system_bor_init();
/* global IRQ enable */
__enable_irq();
/* init for for all platform */
system_bor_init();
/* global IRQ enable */
__enable_irq();
}
void System_Post_Init(void)
{
PDS_Trim_RC32M();
HBN_Trim_RC32K();
void System_Post_Init(void) {
PDS_Trim_RC32M();
HBN_Trim_RC32K();
}

2
source/Core/BSP/Magic/configuration.h
View File

@@ -133,7 +133,7 @@
#define MIN_BOOST_TEMP_C 250 // The min settable temp for boost mode °C
#define MIN_BOOST_TEMP_F 480 // The min settable temp for boost mode °F
#define POW_PD 0
#define POW_PD 1
#define POW_QC 0
#define POW_DC 1
#define POW_QC_20V 1