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Merge pull request #707 from Ralim/pinecil

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Pinecil Support.
This is still not perfect, some compiler issues, but want to get the damn thing in and then iterate on compiler quirkyness later.
(Compiler under docker+WSL+Windows works great, under plain ubuntu+docker it doesnt 🤔 )
This commit is contained in:
Ben V. Brown
2020-11-10 13:24:52 +11:00
committed by GitHub
parent bafc793e16 65267d0cc7
commit a6edc9bfcc
201 changed files with 27099 additions and 2938 deletions
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30
.github/workflows/ccpp.yml → .github/workflows/pr.yml vendored
View File

@@ -1,6 +1,6 @@
name: C/C++ CI
name: CI PR
on: [pull_request, push]
on: [pull_request]
jobs:
build_TS80:
@@ -75,3 +75,29 @@ jobs:
workspace/TS100/Hexfile/TS100_*.hex
workspace/TS100/Hexfile/TS100_*.bin
if-no-files-found: error
build_Pinecil:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: chmod
run: chmod +x setup.sh && chmod +x workspace/TS100/build.sh
- name: setup
run: ./setup.sh
- name: build Pinecil
run: cd workspace/TS100 && ./build.sh -m Pinecil
- name: Archive Pinecil artifacts
uses: actions/upload-artifact@v2
with:
name: Pinecil
path: |
workspace/TS100/Hexfile/Pinecil_*.hex
workspace/TS100/Hexfile/Pinecil_*.bin
if-no-files-found: error

98
.github/workflows/push.yml vendored Normal file
View File

@@ -0,0 +1,98 @@
name: CI PR
on: [push]
jobs:
build_TS80:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: chmod
run: chmod +x setup.sh && chmod +x workspace/TS100/build.sh
- name: setup
run: ./setup.sh
- name: build TS80
run: cd workspace/TS100 && ./build.sh -m TS80
- name: Archive TS80 artifacts
uses: actions/upload-artifact@v2
with:
name: TS80
path: |
workspace/TS100/Hexfile/TS80_*.hex
workspace/TS100/Hexfile/TS80_*.bin
if-no-files-found: error
build_TS80P:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: chmod
run: chmod +x setup.sh && chmod +x workspace/TS100/build.sh
- name: setup
run: ./setup.sh
- name: build TS80P
run: cd workspace/TS100 && ./build.sh -m TS80P
- name: Archive TS80P artifacts
uses: actions/upload-artifact@v2
with:
name: TS80P
path: |
workspace/TS100/Hexfile/TS80P_*.hex
workspace/TS100/Hexfile/TS80P_*.bin
if-no-files-found: error
build_TS100:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: chmod
run: chmod +x setup.sh && chmod +x workspace/TS100/build.sh
- name: setup
run: ./setup.sh
- name: build TS100
run: cd workspace/TS100 && ./build.sh -m TS100
- name: Archive TS100 artifacts
uses: actions/upload-artifact@v2
with:
name: TS100
path: |
workspace/TS100/Hexfile/TS100_*.hex
workspace/TS100/Hexfile/TS100_*.bin
if-no-files-found: error
build_Pinecil:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: chmod
run: chmod +x setup.sh && chmod +x workspace/TS100/build.sh
- name: setup
run: ./setup.sh
- name: build Pinecil
run: cd workspace/TS100 && ./build.sh -m Pinecil
- name: Archive Pinecil artifacts
uses: actions/upload-artifact@v2
with:
name: Pinecil
path: |
workspace/TS100/Hexfile/Pinecil_*.hex
workspace/TS100/Hexfile/Pinecil_*.bin
if-no-files-found: error

2
Dockerfile
View File

@@ -14,8 +14,10 @@ RUN apt-get update && \
wget && \
apt-get clean
RUN wget -qO- https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 | tar -xj
RUN wget -qO- https://github.com/Ralim/nuclei-compiler/releases/download/2020.08/nuclei_riscv_newlibc_prebuilt_linux64_2020.08.tar.bz2 | tar -xj
# Add compiler to the path
ENV PATH "/build/gcc-arm-none-eabi-9-2020-q2-update/bin:$PATH"
ENV PATH "/build/gcc/bin/:$PATH"
COPY . /build/source
COPY ./ci /build/ci

15
Translation Editor/translation_bg.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Източник",
"захранване"
@@ -206,7 +210,7 @@
],
"desc": "Прецизна калибрация с използване на термо-двойка на върха на поялника"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Мощност на",
"захранване"
@@ -255,6 +259,13 @@
],
"desc": "Усилване на върха на поялника"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_cs.json Executable file → Normal file
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Zdroj",
"napájení"
@@ -206,7 +210,7 @@
],
"desc": "Pokročilá kalibrace pomocí termočlánku na hrotu."
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Výkon",
"ve wattech"
@@ -255,6 +259,13 @@
],
"desc": "Zisk hrotu (měření)"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_da.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "D",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "S",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Power",
"source"
@@ -206,7 +210,7 @@
],
"desc": "Advanced calibration using thermocouple on the tip"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Power",
"Wattage"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_de.json
View File

@@ -39,6 +39,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -74,7 +78,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Spannungs-",
"quelle"
@@ -207,7 +211,7 @@
],
"desc": "Erweiterte Kalibrierung mittels eines Thermoelements an der Lötspitze"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Leistungs-",
"Aufnahme"
@@ -256,6 +260,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

21
Translation Editor/translation_en.json
View File

@@ -39,6 +39,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -74,7 +78,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Power",
"source"
@@ -207,12 +211,12 @@
],
"desc": "Advanced calibration using thermocouple on the tip"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Power",
"wattage"
"QC",
"Voltage"
],
"desc": "Power wattage of the power adapter used"
"desc": "Desired max QC Voltage negotiated for"
},
"PowerLimit": {
"text2": [
@@ -256,6 +260,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_es.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "R",
"SettingStartSleepOffChar": "F",
"SettingStartNoneChar": "N",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Fuente",
"de energía"
@@ -206,7 +210,7 @@
],
"desc": "Calibrar con un termopar en la punta; más difícil."
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Potencia de",
"entrada"
@@ -255,6 +259,13 @@
],
"desc": "Modificar el valor de ganancia de la punta."
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_fi.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Virtalähde",
"DC"
@@ -206,7 +210,7 @@
],
"desc": "Advanced calibration using thermocouple on the tip"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Power",
"Wattage"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_fr.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "V",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "D",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "V"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Source",
"d'alim"
@@ -206,7 +210,7 @@
],
"desc": "Calibration avancées à l'aide d'un thermocouple sur la panne"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Puissance de",
"l'alimentation"
@@ -261,6 +265,13 @@
"verrouillage"
],
"desc": "Permet de verrouiller les touches pendant la soudure sur un appuis long des 2 bouttons <D=Désactiver, B=Boost seulement, V=Verr. total>"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
}
}
}

15
Translation Editor/translation_hr.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Izvor",
"napajanja"
@@ -206,7 +210,7 @@
],
"desc": "Kalibracija korištenjem termo-elementa"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Snaga",
"napajanja"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_hu.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Áram",
"forrás"
@@ -206,7 +210,7 @@
],
"desc": "Haladó kalibrálás hegyre helyezett hőelem segítségével"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Bemeneti",
"teljesítmény"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_it.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "D",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Sorgente",
"alimentaz"
@@ -206,7 +210,7 @@
],
"desc": "Calibra le rilevazioni di temperatura attraverso la termocoppia presente nella punta"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Potenza",
"alimentaz"
@@ -255,6 +259,13 @@
],
"desc": "Varia il guadagno della punta"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_lt.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Maitinimo",
"šaltinis"
@@ -206,7 +210,7 @@
],
"desc": "Išplėstinė kalibracija naudojant termoelementą"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Galia",
"vatais"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

17
Translation Editor/translation_nl.json
View File

@@ -40,7 +40,11 @@
"SettingStartNoneChar": "F",
"SettingLockDisableChar": "U",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "V"
"SettingLockFullChar": "V",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H"
},
"menuGroups": {
"SolderingMenu": {
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Spannings-",
"bron"
@@ -206,7 +210,7 @@
],
"desc": "Geavanceerde calibratie met een thermokoppel op de punt"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Power",
"Wattage"
@@ -255,6 +259,13 @@
],
"desc": "Punt gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Blokkeer",

15
Translation Editor/translation_nl_be.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Spannings-",
"bron"
@@ -206,7 +210,7 @@
],
"desc": "Calibrering met thermokoppel"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Vermogen",
"Watt"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_no.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "D",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "I",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Kilde",
""
@@ -206,7 +210,7 @@
],
"desc": "Advanced calibration using thermocouple on the tip"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Power",
"Wattage"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_pl.json
View File

@@ -39,6 +39,10 @@
"SettingStartSleepChar": "Z",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "B",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -74,7 +78,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Źródło",
"zasilania"
@@ -207,7 +211,7 @@
],
"desc": "Zaawansowana kalibracja za pomocą termoelementu na grocie"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Moc",
"w W"
@@ -256,6 +260,13 @@
],
"desc": "Zysk grotu"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_pt.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Fonte",
"alimentação"
@@ -206,7 +210,7 @@
],
"desc": "Calibração avançada com um termopar na ponta"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Potência",
"Fonte"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_ru.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "О",
"SettingStartSleepOffChar": "К",
"SettingStartNoneChar": "В",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Источник",
"питания"
@@ -206,7 +210,7 @@
],
"desc": "Улучшенная калибровка с импользованием термопары жала"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Мощность",
"питания"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_sk.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "K",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "N",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Zdroj",
"napätia"
@@ -206,7 +210,7 @@
],
"desc": "Pokročilá kalibrácia meraním teploty hrotu"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Obmedzenie",
"výkonu"
@@ -255,6 +259,13 @@
],
"desc": "Úprava zisku hrotu"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_sl.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Vir",
"napajanja"
@@ -206,7 +210,7 @@
],
"desc": "Napredna kalibracija s termočlenom na konici"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Moč napajalnega",
"vira"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_sr_cyrl.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Врста",
"напајања"
@@ -206,7 +210,7 @@
],
"desc": "Напредна калибрација помоћу термопара."
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Улазна",
"снага"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_sr_latn.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Vrsta",
"napajanja"
@@ -206,7 +210,7 @@
],
"desc": "Napredna kalibracija pomoću termopara."
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Ulazna",
"snaga"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_sv.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Ström-",
"källa"
@@ -206,7 +210,7 @@
],
"desc": "Advanced calibration using thermocouple on the tip"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Power",
"Wattage"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_tr.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "S",
"SettingStartSleepOffChar": "O",
"SettingStartNoneChar": "F",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"PWRSC",
""
@@ -206,7 +210,7 @@
],
"desc": "Uçtaki ısı sensörünü kullanarak gelişmiş kalibrasyon"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Güç",
"Miktarı(W)"
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

15
Translation Editor/translation_uk.json
View File

@@ -38,6 +38,10 @@
"SettingStartSleepChar": "О",
"SettingStartSleepOffChar": "К",
"SettingStartNoneChar": "В",
"SettingSensitivityOff": "O",
"SettingSensitivityLow": "L",
"SettingSensitivityMedium": "M",
"SettingSensitivityHigh": "H",
"SettingLockDisableChar": "D",
"SettingLockBoostChar": "B",
"SettingLockFullChar": "F"
@@ -73,7 +77,7 @@
}
},
"menuOptions": {
"PowerSource": {
"DCInCutoff": {
"text2": [
"Джерело",
"живлення"
@@ -206,7 +210,7 @@
],
"desc": "Калібрування за допомогою термопари"
},
"PowerInput": {
"QCMaxVoltage": {
"text2": [
"Потужність",
"дж. живл."
@@ -255,6 +259,13 @@
],
"desc": "Tip gain"
},
"HallEffSensitivity": {
"text2": [
"Hall Eff",
"Sensitivity"
],
"desc": "Sensitivity of the Hall effect sensor in detecting sleep <O=Off,L=Low,M=Medium,H=High>"
},
"LockingMode": {
"text2": [
"Allow buttons",

23
Translation Editor/translations_def.js
View File

@@ -149,6 +149,21 @@ var def =
"len": 1
},
{
"id": "SettingSensitivityOff",
"len": 1
},
{
"id": "SettingSensitivityLow",
"len": 1
},
{
"id": "SettingSensitivityMedium",
"len": 1
},
{
"id": "SettingSensitivityHigh",
"len": 1
}, {
"id": "SettingLockDisableChar",
"len": 1,
"default": "D"
@@ -184,7 +199,7 @@ var def =
],
"menuOptions": [
{
"id": "PowerSource",
"id": "DCInCutoff",
"maxLen": 5,
"maxLen2": 11
},
@@ -279,7 +294,7 @@ var def =
"maxLen2": 16
},
{
"id": "PowerInput",
"id": "QCMaxVoltage",
"maxLen": 8,
"maxLen2": 16
},
@@ -314,6 +329,10 @@ var def =
"maxLen2": 8
},
{
"id": "HallEffSensitivity",
"maxLen": 6,
"maxLen2": 8
}, {
"id": "LockingMode",
"maxLen": 6,
"maxLen2": 13

2
setup.sh
View File

@@ -7,7 +7,9 @@ sudo mkdir /build
cd /build
sudo wget -qO- https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 | sudo tar -xj
sudo wget -qO- https://github.com/Ralim/nuclei-compiler/releases/download/2020.08/nuclei_riscv_newlibc_prebuilt_linux64_2020.08.tar.bz2 | sudo tar -xj
# Add compiler to the path
sudo ln -s /build/gcc-arm-none-eabi-9-2020-q2-update/bin/* /usr/local/bin
sudo ln -s /build/gcc/bin/* /usr/local/bin

7
workspace/TS100/Core/BSP/BSP.h
View File

@@ -63,6 +63,13 @@ uint8_t showBootLogoIfavailable();
void delay_ms(uint16_t count) ;
//Used to allow knowledge of if usb_pd is being used
uint8_t usb_pd_detect();
bool getHallSensorFitted();
// If the iron has a hall effect sensor in the handle, return an signed count of the reading
// If the sensor is single polarity (or polarity insensitive) just return 0..32768
int16_t getRawHallEffect();
//Returns true if power is from dumb "DC" input rather than "smart" QC or PD
bool getIsPoweredByDCIN();
#ifdef __cplusplus
}

1
workspace/TS100/Core/BSP/BSP_Common.c Normal file
View File

@@ -0,0 +1 @@
#include "BSP.h"

4
workspace/TS100/Core/BSP/Defines.h
View File

@@ -15,5 +15,7 @@ enum Orientation {
//It is assumed that all hardware implements an 8Hz update period at this time
#define PID_TIM_HZ (8)
#define TICKS_SECOND configTICK_RATE_HZ
#define TICKS_MIN (60*TICKS_SECOND)
#define TICKS_100MS (TICKS_SECOND/10)
#endif /* BSP_DEFINES_H_ */

2
workspace/TS100/Core/BSP/Miniware/BSP.cpp
View File

@@ -93,6 +93,7 @@ static const uint16_t NTCHandleLookup[] = {
// 11292, 60, //
};
#endif
uint16_t getHandleTemperature() {
#ifdef TEMP_NTC
//TS80P uses 100k NTC resistors instead
@@ -347,7 +348,6 @@ void BSPInit(void) {
}
void reboot() {
NVIC_SystemReset();
}

0
workspace/TS100/Core/Inc/FreeRTOSConfig.h → workspace/TS100/Core/BSP/Miniware/FreeRTOSConfig.h
View File

26
workspace/TS100/Core/BSP/Miniware/I2C_Wrapper.cpp
View File

@@ -4,9 +4,9 @@
* Created on: 14Apr.,2018
* Author: Ralim
*/
#include <I2C_Wrapper.hpp>
#include "BSP.h"
#include "Setup.h"
#include <I2C_Wrapper.hpp>
SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr;
StaticSemaphore_t FRToSI2C::xSemaphoreBuffer;
@@ -22,8 +22,8 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t MemAddress,
if (!lock())
return false;
if (HAL_I2C_Mem_Read(&hi2c1, DevAddress, MemAddress,
I2C_MEMADD_SIZE_8BIT, pData, Size, 500) != HAL_OK) {
if (HAL_I2C_Mem_Read(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT,
pData, Size, 500) != HAL_OK) {
I2C_Unstick();
unlock();
@@ -32,7 +32,6 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t MemAddress,
unlock();
return true;
}
bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) {
return Mem_Write(address, reg, &data, 1);
@@ -48,8 +47,8 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
if (!lock())
return false;
if (HAL_I2C_Mem_Write(&hi2c1, DevAddress, MemAddress,
I2C_MEMADD_SIZE_8BIT, pData, Size, 500) != HAL_OK) {
if (HAL_I2C_Mem_Write(&hi2c1, DevAddress, MemAddress, I2C_MEMADD_SIZE_8BIT,
pData, Size, 500) != HAL_OK) {
I2C_Unstick();
unlock();
@@ -87,11 +86,22 @@ void FRToSI2C::I2C_Unstick() {
}
void FRToSI2C::unlock() {
xSemaphoreGive(I2CSemaphore);
}
bool FRToSI2C::lock() {
return xSemaphoreTake(I2CSemaphore, (TickType_t)50) == pdTRUE;
}
bool FRToSI2C::writeRegistersBulk(const uint8_t address,
const I2C_REG *registers, const uint8_t registersLength) {
for (int index = 0; index < registersLength; index++) {
if (!I2C_RegisterWrite(address, registers[index].reg,
registers[index].val)) {
return false;
}
if (registers[index].pause_ms)
delay_ms(registers[index].pause_ms);
}
return true;
}

8
workspace/TS100/Core/BSP/Miniware/Model_Config.h
View File

@@ -18,17 +18,20 @@
#endif
#ifdef MODEL_TS100
#define POW_DC
#define ACCEL_MMA
#define ACCEL_LIS
#define TEMP_TMP36
#define BATTFILTERDEPTH 32
#endif
#ifdef MODEL_TS80
#define ACCEL_LIS
#define POW_QC
#define TEMP_TMP36
#define LIS_ORI_FLIP
#define ACCEL_ORI_FLIP
#define OLED_FLIP
#define BATTFILTERDEPTH 8
#endif
#ifdef MODEL_TS80P
@@ -37,8 +40,9 @@
#define POW_QC
#define TEMP_NTC
#define I2C_SOFT
#define LIS_ORI_FLIP
#define ACCEL_ORI_FLIP
#define OLED_FLIP
#define BATTFILTERDEPTH 8
#endif
#endif /* BSP_MINIWARE_MODEL_CONFIG_H_ */

14
workspace/TS100/Core/BSP/Miniware/Power.cpp
View File

@@ -34,3 +34,17 @@ uint8_t usb_pd_detect() {
return false;
}
bool getIsPoweredByDCIN() {
#ifdef MODEL_TS80
return false;
#endif
#ifdef MODEL_TS80P
return false;
#endif
#ifdef MODEL_TS100
return true;
#endif
}

6
workspace/TS100/Core/BSP/Miniware/QC_GPIO.cpp
View File

@@ -66,11 +66,13 @@ void QC_Post_Probe_En() {
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
}
uint8_t QC_DM_PulledDown() { return HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11) == GPIO_PIN_RESET ? 1 : 0; }
uint8_t QC_DM_PulledDown() {
return HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11) == GPIO_PIN_RESET ? 1 : 0;
}
#endif
void QC_resync() {
#ifdef POW_QC
seekQC((systemSettings.cutoutSetting) ? 120 : 90,
seekQC((systemSettings.QCIdealVoltage) ? 120 : 90,
systemSettings.voltageDiv); // Run the QC seek again if we have drifted too much
#endif
}

2
workspace/TS100/Core/BSP/Miniware/Software_I2C.h
View File

@@ -22,6 +22,4 @@
#endif
#endif /* BSP_MINIWARE_SOFTWARE_I2C_H_ */

4
workspace/TS100/Core/BSP/Miniware/flash.c
View File

@@ -33,8 +33,8 @@ uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
HAL_FLASH_Unlock();
for (uint8_t i = 0; i < (length / 2); i++) {
resetWatchdog();
HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, (uint32_t)&settings_page[i],
data[i]);
HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,
(uint32_t) &settings_page[i], data[i]);
}
HAL_FLASH_Lock();
return 1;

7
workspace/TS100/Core/BSP/Miniware/fusb302b.cpp
View File

@@ -142,16 +142,16 @@ void fusb_send_hardrst() {
I2CBB::unlock2();
}
void fusb_setup() {
bool fusb_setup() {
if (!I2CBB::lock2()) {
return;
return false;
}
/* Fully reset the FUSB302B */
// fusb_write_byte( FUSB_RESET, FUSB_RESET_SW_RES);
// osDelay(2);
if (!fusb_read_id()) {
return;
return false;
}
/* Turn on all power */
@@ -200,6 +200,7 @@ void fusb_setup() {
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 10, 0);
HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
return true;
}
void fusb_get_status(union fusb_status *status) {

3
workspace/TS100/Core/BSP/Miniware/logo.cpp
View File

@@ -15,8 +15,7 @@ static uint8_t logo_page[1024] __attribute__ ((section (".logo_page")));
uint8_t showBootLogoIfavailable() {
// Do not show logo data if signature is not found.
if (LOGO_HEADER_VALUE
!= *(reinterpret_cast<const uint32_t*>(logo_page))) {
if (LOGO_HEADER_VALUE != *(reinterpret_cast<const uint32_t*>(logo_page))) {
return 0;
}

94
workspace/TS100/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c → workspace/TS100/Core/BSP/Miniware/port.c
View File

@@ -163,7 +163,8 @@ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
#if( configASSERT_DEFINED == 1 )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
static const volatile uint8_t *const pcInterruptPriorityRegisters =
(const volatile uint8_t* const ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */
/*-----------------------------------------------------------*/
@@ -171,8 +172,8 @@ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
StackType_t* pxPortInitialiseStack(StackType_t *pxTopOfStack,
TaskFunction_t pxCode, void *pvParameters) {
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
@@ -189,8 +190,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
static void prvTaskExitError(void) {
volatile uint32_t ulDummy = 0UL;
/* A function that implements a task must not exit or attempt to return to
@@ -201,8 +201,7 @@ volatile uint32_t ulDummy = 0UL;
defined, then stop here so application writers can catch the error. */
configASSERT(uxCriticalNesting == ~0UL);
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
{
while (ulDummy == 0) {
/* This file calls prvTaskExitError() after the scheduler has been
started to remove a compiler warning about the function being defined
but never called. ulDummy is used purely to quieten other warnings
@@ -214,8 +213,7 @@ volatile uint32_t ulDummy = 0UL;
}
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
void vPortSVCHandler(void) {
__asm volatile (
" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
@@ -234,8 +232,7 @@ void vPortSVCHandler( void )
}
/*-----------------------------------------------------------*/
static void prvPortStartFirstTask( void )
{
static void prvPortStartFirstTask(void) {
__asm volatile(
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n"
@@ -254,8 +251,7 @@ static void prvPortStartFirstTask( void )
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
BaseType_t xPortStartScheduler(void) {
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
configASSERT(configMAX_SYSCALL_INTERRUPT_PRIORITY);
@@ -263,7 +259,9 @@ BaseType_t xPortStartScheduler( void )
#if( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
volatile uint8_t *const pucFirstUserPriorityRegister =
(volatile uint8_t* const ) ( portNVIC_IP_REGISTERS_OFFSET_16
+ portFIRST_USER_INTERRUPT_NUMBER);
volatile uint8_t ucMaxPriorityValue;
/* Determine the maximum priority from which ISR safe FreeRTOS API
@@ -282,13 +280,13 @@ BaseType_t xPortStartScheduler( void )
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY
& ucMaxPriorityValue;
/* Calculate the maximum acceptable priority group value for the number
of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
{
while ((ucMaxPriorityValue & portTOP_BIT_OF_BYTE) == portTOP_BIT_OF_BYTE) {
ulMaxPRIGROUPValue--;
ucMaxPriorityValue <<= (uint8_t) 0x01;
}
@@ -350,16 +348,14 @@ BaseType_t xPortStartScheduler( void )
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
void vPortEndScheduler(void) {
/* Not implemented in ports where there is nothing to return to.
Artificially force an assert. */
configASSERT(uxCriticalNesting == 1000UL);
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
void vPortEnterCritical(void) {
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
@@ -368,26 +364,22 @@ void vPortEnterCritical( void )
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
{
if (uxCriticalNesting == 1) {
configASSERT(( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK) == 0);
}
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
void vPortExitCritical(void) {
configASSERT(uxCriticalNesting);
uxCriticalNesting--;
if( uxCriticalNesting == 0 )
{
if (uxCriticalNesting == 0) {
portENABLE_INTERRUPTS();
}
}
/*-----------------------------------------------------------*/
void xPortPendSVHandler( void )
{
void xPortPendSVHandler(void) {
/* This is a naked function. */
__asm volatile
@@ -423,8 +415,7 @@ void xPortPendSVHandler( void )
}
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
void xPortSysTickHandler(void) {
/* The SysTick runs at the lowest interrupt priority, so when this interrupt
executes all interrupts must be unmasked. There is therefore no need to
save and then restore the interrupt mask value as its value is already
@@ -432,8 +423,7 @@ void xPortSysTickHandler( void )
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
if (xTaskIncrementTick() != pdFALSE) {
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
@@ -614,8 +604,7 @@ void xPortSysTickHandler( void )
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
__attribute__(( weak )) void vPortSetupTimerInterrupt(void) {
/* Calculate the constants required to configure the tick interrupt. */
#if( configUSE_TICKLESS_IDLE == 1 )
{
@@ -630,15 +619,16 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ)
- 1UL;
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT
| portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT);
}
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
void vPortValidateInterruptPriority(void) {
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
@@ -646,8 +636,7 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
{
if (ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER) {
/* Look up the interrupt's priority. */
ucCurrentPriority = pcInterruptPriorityRegisters[ulCurrentInterrupt];
@@ -690,28 +679,9 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
scheduler. Note however that some vendor specific peripheral libraries
assume a non-zero priority group setting, in which cases using a value
of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
configASSERT(
( portAIRCR_REG & portPRIORITY_GROUP_MASK) <= ulMaxPRIGROUPValue);
}
#endif /* configASSERT_DEFINED */

42
workspace/TS100/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h → workspace/TS100/Core/BSP/Miniware/portmacro.h
View File

@@ -25,7 +25,6 @@
* 1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
@@ -127,8 +126,8 @@ not necessary for to use this port. They are defined so the common demo files
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
/* Generic helper function. */
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
{
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros(
uint32_t ulBitmap) {
uint8_t ucReturn;
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
@@ -168,20 +167,16 @@ not necessary for to use this port. They are defined so the common demo files
/*-----------------------------------------------------------*/
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
{
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) {
uint32_t ulCurrentInterrupt;
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
if( ulCurrentInterrupt == 0 )
{
if (ulCurrentInterrupt == 0) {
xReturn = pdFALSE;
}
else
{
} else {
xReturn = pdTRUE;
}
@@ -190,33 +185,31 @@ BaseType_t xReturn;
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
uint32_t ulNewBASEPRI;
__asm volatile
(
" mov %0, %1 \n" \
" msr basepri, %0 \n" \
" isb \n" \
" dsb \n" \
" mov %0, %1 \n"
" msr basepri, %0 \n"
" isb \n"
" dsb \n"
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) {
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile
(
" mrs %0, basepri \n" \
" mov %1, %2 \n" \
" msr basepri, %1 \n" \
" isb \n" \
" dsb \n" \
" mrs %0, basepri \n"
" mov %1, %2 \n"
" msr basepri, %1 \n"
" isb \n"
" dsb \n"
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
@@ -226,8 +219,7 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) {
__asm volatile
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"

1
workspace/TS100/Core/BSP/Miniware/stm32f1xx_hal_msp.c
View File

@@ -26,7 +26,6 @@ void HAL_MspInit(void) {
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
}
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {

12
workspace/TS100/Core/BSP/Miniware/stm32f1xx_hal_timebase_TIM.c
View File

@@ -75,8 +75,7 @@ uint32_t uwIncrementState = 0;
* @param TickPriority: Tick interrupt priorty.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0;
uint32_t uwPrescalerValue = 0;
@@ -113,8 +112,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
htim1.Init.Prescaler = uwPrescalerValue;
htim1.Init.ClockDivision = 0;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
if(HAL_TIM_Base_Init(&htim1) == HAL_OK)
{
if (HAL_TIM_Base_Init(&htim1) == HAL_OK) {
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim1);
}
@@ -129,8 +127,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
* @param None
* @retval None
*/
void HAL_SuspendTick(void)
{
void HAL_SuspendTick(void) {
/* Disable TIM1 update Interrupt */
__HAL_TIM_DISABLE_IT(&htim1, TIM_IT_UPDATE);
}
@@ -141,8 +138,7 @@ void HAL_SuspendTick(void)
* @param None
* @retval None
*/
void HAL_ResumeTick(void)
{
void HAL_ResumeTick(void) {
/* Enable TIM1 Update interrupt */
__HAL_TIM_ENABLE_IT(&htim1, TIM_IT_UPDATE);
}

27
workspace/TS100/Core/BSP/Miniware/system_stm32f1xx.c
View File

@@ -27,10 +27,10 @@
uint32_t SystemCoreClock = 64000000U; /*!< System Clock Frequency (Core Clock) */
#endif
const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t AHBPrescTable[16U] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7,
8, 9 };
const uint8_t APBPrescTable[8U] = { 0, 0, 0, 0, 1, 2, 3, 4 };
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
@@ -39,8 +39,7 @@ const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
* @param None
* @retval None
*/
void SystemInit (void)
{
void SystemInit(void) {
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= 0x00000001U;
@@ -129,8 +128,7 @@ void SystemInit (void)
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
void SystemCoreClockUpdate(void) {
uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
#if defined(STM32F105xC) || defined(STM32F107xC)
@@ -144,8 +142,7 @@ void SystemCoreClockUpdate (void)
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
switch (tmp) {
case 0x00U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
@@ -161,25 +158,19 @@ void SystemCoreClockUpdate (void)
#if !defined(STM32F105xC) && !defined(STM32F107xC)
pllmull = (pllmull >> 18U) + 2U;
if (pllsource == 0x00U)
{
if (pllsource == 0x00U) {
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
}
else
{
} else {
#if defined(STM32F100xB) || defined(STM32F100xE)
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else
/* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t) RESET) {/* HSE oscillator clock divided by 2 */
SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
}
else
{
} else {
SystemCoreClock = HSE_VALUE * pllmull;
}
#endif

130
workspace/TS100/Core/BSP/Pine64/BSP.cpp Normal file
View File

@@ -0,0 +1,130 @@
// BSP mapping functions
#include "BSP.h"
#include "I2C_Wrapper.hpp"
#include "Pins.h"
#include "Setup.h"
#include "gd32vf103_timer.h"
#include "history.hpp"
#include "main.hpp"
#include "systick.h"
#include <IRQ.h>
const uint16_t powerPWM = 255;
const uint8_t holdoffTicks = 25; // delay of 7 ms
const uint8_t tempMeasureTicks = 25;
uint16_t totalPWM; // htim2.Init.Period, the full PWM cycle
// 2 second filter (ADC is PID_TIM_HZ Hz)
history<uint16_t, PID_TIM_HZ> rawTempFilter = { { 0 }, 0, 0 };
void resetWatchdog() {
fwdgt_counter_reload();
}
uint16_t getTipInstantTemperature() {
volatile uint16_t sum = 0; // 12 bit readings * 8*2 -> 16 bits
for (int i = 0; i < 4; i++) {
sum += adc_inserted_data_read(ADC0, i);
sum += adc_inserted_data_read(ADC1, i);
}
return sum; // 8x over sample
}
uint16_t getTipRawTemp(uint8_t refresh) {
if (refresh) {
uint16_t lastSample = getTipInstantTemperature();
rawTempFilter.update(lastSample);
return lastSample;
} else {
return rawTempFilter.average();
}
}
uint16_t getHandleTemperature() {
#ifdef TEMP_TMP36
// We return the current handle temperature in X10 C
// TMP36 in handle, 0.5V offset and then 10mV per deg C (0.75V @ 25C for
// example) STM32 = 4096 count @ 3.3V input -> But We oversample by 32/(2^2) =
// 8 times oversampling Therefore 32768 is the 3.3V input, so 0.1007080078125
// mV per count So we need to subtract an offset of 0.5V to center on 0C
// (4964.8 counts)
//
int32_t result = getADC(0);
result -= 4965; // remove 0.5V offset
// 10mV per C
// 99.29 counts per Deg C above 0C
result *= 100;
result /= 993;
return result;
#else
#error
#endif
}
uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) {
static uint8_t preFillneeded = 10;
static uint32_t samples[BATTFILTERDEPTH];
static uint8_t index = 0;
if (preFillneeded) {
for (uint8_t i = 0; i < BATTFILTERDEPTH; i++)
samples[i] = getADC(1);
preFillneeded--;
}
if (sample) {
samples[index] = getADC(1);
index = (index + 1) % BATTFILTERDEPTH;
}
uint32_t sum = 0;
for (uint8_t i = 0; i < BATTFILTERDEPTH; i++)
sum += samples[i];
sum /= BATTFILTERDEPTH;
if (divisor == 0) {
divisor = 1;
}
return sum * 4 / divisor;
}
void unstick_I2C() {
/* configure SDA/SCL for GPIO */
GPIO_BC(GPIOB) |= SDA_Pin | SCL_Pin;
gpio_init(SDA_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ,
SDA_Pin | SCL_Pin);
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
GPIO_BOP(GPIOB) |= SCL_Pin;
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
GPIO_BOP(GPIOB) |= SDA_Pin;
/* connect PB6 to I2C0_SCL */
/* connect PB7 to I2C0_SDA */
gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ,
SDA_Pin | SCL_Pin);
}
uint8_t getButtonA() {
return (gpio_input_bit_get(KEY_A_GPIO_Port, KEY_A_Pin) == SET) ? 1 : 0;
}
uint8_t getButtonB() {
return (gpio_input_bit_get(KEY_B_GPIO_Port, KEY_B_Pin) == SET) ? 1 : 0;
}
void reboot() {
//Spin for watchdog
for (;;) {
}
}
void delay_ms(uint16_t count) {
delay_1ms(count);
}

25
workspace/TS100/Core/BSP/Pine64/BSP_PD.c Normal file
View File

@@ -0,0 +1,25 @@
/*
* BSP_PD.c
*
* Created on: 21 Jul 2020
* Author: Ralim
*/
#include "BSP_PD.h"
#include "Model_Config.h"
#ifdef POW_PD
/*
* An array of all of the desired voltages & minimum currents in preferred order
*/
const uint16_t USB_PD_Desired_Levels[] = {
//mV desired input, mA minimum required current
//Tip is ~ 7.5 ohms
20000, 2666, // 20V, 2.6A
15000, 2000, // 15V 2A
12000, 1600, //12V @ 1.6A
9000, 1200, //9V @ 1.2A
5000, 100, //5V @ whatever
};
const uint8_t USB_PD_Desired_Levels_Len = 5;
#endif

98
workspace/TS100/Core/BSP/Pine64/FreeRTOSConfig.h Normal file
View File

@@ -0,0 +1,98 @@
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/* Ensure stdint is only used by the compiler, and not the assembler. */
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif
//RISC-V configuration
#include "n200_timer.h"
#define USER_MODE_TASKS 0
#define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configUSE_TICKLESS_IDLE 0
#define configCPU_CLOCK_HZ ((uint32_t)SystemCoreClock)
#define configRTC_CLOCK_HZ ((uint32_t)TIMER_FREQ)
#define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES (4) //0 - 3 å…±6等级，idle独å<C2AC> 0，Tmr_svc独å<C2AC> 3
#define configMINIMAL_STACK_SIZE ((unsigned short)128)
#define configMAX_TASK_NAME_LEN 24
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_TASK_NOTIFICATIONS 1
#define configUSE_MUTEXES 1
#define configUSE_RECURSIVE_MUTEXES 0
#define configUSE_COUNTING_SEMAPHORES 0
#define configQUEUE_REGISTRY_SIZE 10
#define configUSE_QUEUE_SETS 0
#define configUSE_TIME_SLICING 1
#define configUSE_NEWLIB_REENTRANT 0
#define configENABLE_BACKWARD_COMPATIBILITY 0
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_vTaskDelay 1
/* Memory allocation related definitions. */
#define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 1
#define configTOTAL_HEAP_SIZE 1024
#define configAPPLICATION_ALLOCATED_HEAP 0
/* Hook function related definitions. */
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_MALLOC_FAILED_HOOK 0
#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
/* Run time and task stats gathering related definitions. */
#define configGENERATE_RUN_TIME_STATS 0
#define configUSE_TRACE_FACILITY 1
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
/* Co-routine related definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES 1
/* Software timer related definitions. */
#define configUSE_TIMERS 0
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) //Tmr_svc 独å<C2AC> æœ€é«˜ä¼˜å…ˆçº§
#define configTIMER_QUEUE_LENGTH 5
#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
/* Interrupt nesting behaviour configuration. */
#define configPRIO_BITS (4UL)
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x1
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 0xe
#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* Define to trap errors during development. */
#define configASSERT(x) \
if ((x) == 0) { \
taskDISABLE_INTERRUPTS(); \
for (;;) \
; \
}
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_xResumeFromISR 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_xTaskGetIdleTaskHandle 1
#define INCLUDE_eTaskGetState 0
#define INCLUDE_xEventGroupSetBitFromISR 1
#define INCLUDE_xTimerPendFunctionCall 0
#define INCLUDE_xTaskAbortDelay 0
#define INCLUDE_xTaskGetHandle 1
#define INCLUDE_xTaskResumeFromISR 1
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#endif /* FREERTOS_CONFIG_H */

532
workspace/TS100/Core/BSP/Pine64/I2C_Wrapper.cpp Normal file
View File

@@ -0,0 +1,532 @@
/*
* FRToSI2C.cpp
*
* Created on: 14Apr.,2018
* Author: Ralim
*/
#include "BSP.h"
#include "IRQ.h"
#include "Setup.h"
#include <I2C_Wrapper.hpp>
SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr;
StaticSemaphore_t FRToSI2C::xSemaphoreBuffer;
#define I2C_TIME_OUT (uint16_t)(5000)
void FRToSI2C::CpltCallback() {
// TODO
}
bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) {
return Mem_Write(address, reg, &data, 1);
}
uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) {
uint8_t temp = 0;
Mem_Read(add, reg, &temp, 1);
return temp;
}
bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address,
uint8_t *p_buffer, uint16_t number_of_byte) {
if (!lock())
return false;
i2c_interrupt_disable(I2C0, I2C_INT_ERR);
i2c_interrupt_disable(I2C0, I2C_INT_BUF);
i2c_interrupt_disable(I2C0, I2C_INT_EV);
dma_parameter_struct dma_init_struct;
uint8_t state = I2C_START;
uint8_t in_rx_cycle = 0;
uint16_t timeout = 0;
uint8_t tries = 0;
uint8_t i2c_timeout_flag = 0;
while (!(i2c_timeout_flag)) {
switch (state) {
case I2C_START:
tries++;
if (tries > 64) {
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
unlock();
return false;
}
if (0 == in_rx_cycle) {
/* disable I2C0 */
i2c_disable(I2C0);
/* enable I2C0 */
i2c_enable(I2C0);
/* enable acknowledge */
i2c_ack_config(I2C0, I2C_ACK_ENABLE);
/* i2c master sends start signal only when the bus is idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) &&
(timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
/* send the start signal */
i2c_start_on_bus(I2C0);
timeout = 0;
state = I2C_SEND_ADDRESS;
} else {
I2C_Unstick();
timeout = 0;
state = I2C_START;
}
} else {
i2c_start_on_bus(I2C0);
timeout = 0;
state = I2C_SEND_ADDRESS;
}
break;
case I2C_SEND_ADDRESS:
/* i2c master sends START signal successfully */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) &&
(timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
if (RESET == in_rx_cycle) {
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
state = I2C_CLEAR_ADDRESS_FLAG;
} else {
i2c_master_addressing(I2C0, DevAddress, I2C_RECEIVER);
state = I2C_CLEAR_ADDRESS_FLAG;
}
timeout = 0;
} else {
timeout = 0;
state = I2C_START;
in_rx_cycle = 0;
}
break;
case I2C_CLEAR_ADDRESS_FLAG:
/* address flag set means i2c slave sends ACK */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) &&
(timeout < I2C_TIME_OUT)) {
timeout++;
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
// Address NACK'd
unlock();
return false;
}
}
if (timeout < I2C_TIME_OUT) {
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
timeout = 0;
state = I2C_TRANSMIT_DATA;
} else {
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
// Address NACK'd
unlock();
return false;
}
break;
case I2C_TRANSMIT_DATA:
if (0 == in_rx_cycle) {
/* wait until the transmit data buffer is empty */
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) &&
(timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
// Write out the 8 byte address
i2c_data_transmit(I2C0, read_address);
timeout = 0;
} else {
timeout = 0;
state = I2C_START;
in_rx_cycle = 0;
}
/* wait until BTC bit is set */
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) &&
(timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
timeout = 0;
state = I2C_START;
in_rx_cycle = 1;
} else {
timeout = 0;
state = I2C_START;
in_rx_cycle = 0;
}
} else {
/* one byte master reception procedure (polling) */
if (number_of_byte < 2) {
/* disable acknowledge */
i2c_ack_config(I2C0, I2C_ACK_DISABLE);
/* clear ADDSEND register by reading I2C_STAT0 then I2C_STAT1 register
* (I2C_STAT0 has already been read) */
i2c_flag_get(I2C0, I2C_FLAG_ADDSEND);
/* send a stop condition to I2C bus*/
i2c_stop_on_bus(I2C0);
/* wait for the byte to be received */
while (!i2c_flag_get(I2C0, I2C_FLAG_RBNE))
;
/* read the byte received from the EEPROM */
*p_buffer = i2c_data_receive(I2C0);
/* decrement the read bytes counter */
number_of_byte--;
timeout = 0;
} else { /* more than one byte master reception procedure (DMA) */
dma_deinit(DMA0, DMA_CH6);
dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_addr = (uint32_t)p_buffer;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
dma_init_struct.number = number_of_byte;
dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0);
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
dma_init(DMA0, DMA_CH6, &dma_init_struct);
i2c_dma_last_transfer_config(I2C0, I2C_DMALST_ON);
/* enable I2C0 DMA */
i2c_dma_enable(I2C0, I2C_DMA_ON);
/* enable DMA0 channel5 */
dma_channel_enable(DMA0, DMA_CH6);
/* wait until BTC bit is set */
while (!dma_flag_get(DMA0, DMA_CH6, DMA_FLAG_FTF)) {
osDelay(1);
}
/* send a stop condition to I2C bus*/
i2c_stop_on_bus(I2C0);
}
timeout = 0;
state = I2C_STOP;
}
break;
case I2C_STOP:
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
timeout = 0;
state = I2C_END;
i2c_timeout_flag = I2C_OK;
} else {
timeout = 0;
state = I2C_START;
in_rx_cycle = 0;
}
break;
default:
state = I2C_START;
in_rx_cycle = 0;
i2c_timeout_flag = I2C_OK;
timeout = 0;
break;
}
}
unlock();
return true;
}
bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress,
uint8_t *p_buffer, uint16_t number_of_byte) {
if (!lock())
return false;
i2c_interrupt_disable(I2C0, I2C_INT_ERR);
i2c_interrupt_disable(I2C0, I2C_INT_EV);
i2c_interrupt_disable(I2C0, I2C_INT_BUF);
dma_parameter_struct dma_init_struct;
uint8_t state = I2C_START;
uint16_t timeout = 0;
bool done = false;
bool timedout = false;
while (!(done || timedout)) {
switch (state) {
case I2C_START:
/* i2c master sends start signal only when the bus is idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
i2c_start_on_bus(I2C0);
timeout = 0;
state = I2C_SEND_ADDRESS;
} else {
I2C_Unstick();
timeout = 0;
state = I2C_START;
}
break;
case I2C_SEND_ADDRESS:
/* i2c master sends START signal successfully */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) &&
(timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
timeout = 0;
state = I2C_CLEAR_ADDRESS_FLAG;
} else {
timedout = true;
done = true;
timeout = 0;
state = I2C_START;
}
break;
case I2C_CLEAR_ADDRESS_FLAG:
/* address flag set means i2c slave sends ACK */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) &&
(timeout < I2C_TIME_OUT)) {
timeout++;
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
// Address NACK'd
unlock();
return false;
}
}
timeout = 0;
if (timeout < I2C_TIME_OUT) {
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
state = I2C_TRANSMIT_DATA;
} else {
// Dont retry as this means a NAK
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
unlock();
return false;
}
break;
case I2C_TRANSMIT_DATA:
/* wait until the transmit data buffer is empty */
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
/* send the EEPROM's internal address to write to : only one byte
* address */
i2c_data_transmit(I2C0, MemAddress);
timeout = 0;
} else {
timedout = true;
timeout = 0;
state = I2C_START;
}
/* wait until BTC bit is set */
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC))
;
dma_deinit(DMA0, DMA_CH5);
dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_addr = (uint32_t)p_buffer;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
dma_init_struct.number = number_of_byte;
dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0);
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
dma_init(DMA0, DMA_CH5, &dma_init_struct);
/* enable I2C0 DMA */
i2c_dma_enable(I2C0, I2C_DMA_ON);
/* enable DMA0 channel5 */
dma_channel_enable(DMA0, DMA_CH5);
/* wait until BTC bit is set */
while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {
osDelay(1);
}
/* wait until BTC bit is set */
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC))
;
state = I2C_STOP;
break;
case I2C_STOP:
/* send a stop condition to I2C bus */
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
timeout = 0;
state = I2C_END;
done = true;
} else {
timedout = true;
done = true;
timeout = 0;
state = I2C_START;
}
break;
default:
state = I2C_START;
timeout = 0;
break;
}
}
unlock();
return timedout == false;
}
bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1);
}
bool FRToSI2C::probe(uint16_t DevAddress) {
uint8_t temp[1];
return Mem_Read(DevAddress, 0x00, temp, sizeof(temp));
}
void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
bool FRToSI2C::lock() {
if (I2CSemaphore == nullptr) {
return false;
}
return xSemaphoreTake(I2CSemaphore, 1000) == pdTRUE;
}
void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); }
bool FRToSI2C::writeRegistersBulk(const uint8_t address,
const I2C_REG *registers,
const uint8_t registersLength) {
for (int index = 0; index < registersLength; index++) {
if (!I2C_RegisterWrite(address, registers[index].reg,
registers[index].val)) {
return false;
}
if (registers[index].pause_ms) {
delay_ms(registers[index].pause_ms);
}
}
return true;
}
bool FRToSI2C::wakePart(uint16_t DevAddress) {
// wakepart is a special case where only the device address is sent
if (!lock())
return false;
i2c_interrupt_disable(I2C0, I2C_INT_ERR);
i2c_interrupt_disable(I2C0, I2C_INT_EV);
i2c_interrupt_disable(I2C0, I2C_INT_BUF);
uint8_t state = I2C_START;
uint16_t timeout = 0;
bool done = false;
bool timedout = false;
while (!(done || timedout)) {
switch (state) {
case I2C_START:
/* i2c master sends start signal only when the bus is idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
i2c_start_on_bus(I2C0);
timeout = 0;
state = I2C_SEND_ADDRESS;
} else {
I2C_Unstick();
timeout = 0;
state = I2C_START;
}
break;
case I2C_SEND_ADDRESS:
/* i2c master sends START signal successfully */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) &&
(timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
i2c_master_addressing(I2C0, DevAddress, I2C_TRANSMITTER);
timeout = 0;
state = I2C_CLEAR_ADDRESS_FLAG;
} else {
timedout = true;
done = true;
timeout = 0;
state = I2C_START;
}
break;
case I2C_CLEAR_ADDRESS_FLAG:
/* address flag set means i2c slave sends ACK */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) &&
(timeout < I2C_TIME_OUT)) {
timeout++;
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
// Address NACK'd
unlock();
return false;
}
}
if (timeout < I2C_TIME_OUT) {
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
timeout = 0;
state = I2C_STOP;
} else {
// Dont retry as this means a NAK
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
unlock();
return false;
}
break;
case I2C_STOP:
/* send a stop condition to I2C bus */
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
timeout = 0;
state = I2C_END;
done = true;
} else {
timedout = true;
done = true;
timeout = 0;
state = I2C_START;
}
break;
default:
state = I2C_START;
timeout = 0;
break;
}
}
unlock();
return timedout == false;
}

121
workspace/TS100/Core/BSP/Pine64/IRQ.cpp Normal file
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/*
* IRQ.c
*
* Created on: 30 May 2020
* Author: Ralim
*/
#include "IRQ.h"
#include "Pins.h"
#include "int_n.h"
volatile uint8_t i2c_read_process = 0;
volatile uint8_t i2c_write_process = 0;
volatile uint8_t i2c_slave_address = 0;
volatile uint8_t i2c_error_code = 0;
volatile uint8_t *i2c_write;
volatile uint8_t *i2c_read;
volatile uint16_t i2c_nbytes;
volatile uint16_t i2c_write_dress;
volatile uint16_t i2c_read_dress;
volatile uint8_t i2c_process_flag = 0;
void ADC0_1_IRQHandler(void) {
adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC);
// unblock the PID controller thread
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
if (pidTaskNotification) {
vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
}
}
volatile uint16_t PWMSafetyTimer = 0;
volatile uint8_t pendingPWM = 0;
void TIMER1_IRQHandler(void) {
if (timer_interrupt_flag_get(TIMER1, TIMER_INT_UP) == SET) {
timer_interrupt_flag_clear(TIMER1, TIMER_INT_UP);
// rollover turn on output if required
if (PWMSafetyTimer && pendingPWM) {
timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 50);
}
if (PWMSafetyTimer) {
PWMSafetyTimer--;
}
}
if (timer_interrupt_flag_get(TIMER1, TIMER_INT_CH1) == SET) {
timer_interrupt_flag_clear(TIMER1, TIMER_INT_CH1);
// This is triggered on pwm setpoint trigger; we want to copy the pending
// PWM value into the output control reg
timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0);
if (pendingPWM) {
timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, pendingPWM);
}
}
}
void setTipPWM(uint8_t pulse) {
PWMSafetyTimer =
10; // This is decremented in the handler for PWM so that the tip pwm is
// disabled if the PID task is not scheduled often enough.
pendingPWM = pulse;
}
static bool fastPWM;
static void switchToFastPWM(void) {
fastPWM = true;
totalPWM = powerPWM + tempMeasureTicks * 2;
TIMER_CAR(TIMER1) = (uint32_t)totalPWM;
// ~3.5 Hz rate
TIMER_CH0CV(TIMER1) = powerPWM + holdoffTicks * 2;
// 1 kHz tick rate
TIMER_PSC(TIMER1) = 12000;
/* generate an update event */
TIMER_SWEVG(TIMER1) |= (uint32_t)TIMER_SWEVG_UPG;
}
static void switchToSlowPWM(void) {
fastPWM = false;
totalPWM = powerPWM + tempMeasureTicks;
TIMER_CAR(TIMER1) = (uint32_t)totalPWM;
// ~1.84 Hz rate
TIMER_CH0CV(TIMER1) = powerPWM + holdoffTicks;
// 500 Hz tick rate
TIMER_PSC(TIMER1) = 24000;
/* generate an update event */
TIMER_SWEVG(TIMER1) |= (uint32_t)TIMER_SWEVG_UPG;
}
bool tryBetterPWM(uint8_t pwm) {
if (fastPWM && pwm == powerPWM) {
// maximum power for fast PWM reached, need to go slower to get more
switchToSlowPWM();
return true;
} else if (!fastPWM && pwm < 230) {
// 254 in fast PWM mode gives the same power as 239 in slow
// allow for some reasonable hysteresis by switching only when it goes
// below 230 (equivalent to 245 in fast mode)
switchToFastPWM();
return true;
}
return false;
}
void EXTI5_9_IRQHandler(void) {
#ifdef POW_PD
if (RESET != exti_interrupt_flag_get(EXTI_5)) {
exti_interrupt_flag_clear(EXTI_5);
if (RESET == gpio_input_bit_get(FUSB302_IRQ_GPIO_Port, FUSB302_IRQ_Pin)) {
InterruptHandler::irqCallback();
}
}
#endif
}
// These are unused for now
void I2C0_EV_IRQHandler(void) {}
void I2C0_ER_IRQHandler(void) {}

56
workspace/TS100/Core/BSP/Pine64/IRQ.h Normal file
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/*
* Irqs.h
*
* Created on: 30 May 2020
* Author: Ralim
*/
#ifndef BSP_MINIWARE_IRQ_H_
#define BSP_MINIWARE_IRQ_H_
#include "BSP.h"
#include "I2C_Wrapper.hpp"
#include "Setup.h"
#include "gd32vf103.h"
#include "main.hpp"
#ifdef __cplusplus
extern "C" {
#endif
void ADC0_1_IRQHandler(void);
void TIMER1_IRQHandler(void);
void EXTI5_9_IRQHandler(void);
/* handle I2C0 event interrupt request */
void I2C0_EV_IRQHandler(void);
/* handle I2C0 error interrupt request */
void I2C0_ER_IRQHandler(void);
typedef enum {
I2C_SEND_ADDRESS_FIRST = 0, //Sending slave address
I2C_CLEAR_ADDRESS_FLAG_FIRST, // Clear address send
I2C_TRANSMIT_WRITE_READ_ADD, //Transmit the memory address to read/write from
I2C_SEND_ADDRESS_SECOND, //Send address again for read
I2C_CLEAR_ADDRESS_FLAG_SECOND, //Clear address again
I2C_TRANSMIT_DATA, //Transmit recieve data
I2C_STOP, //Send stop
I2C_ABORTED, //
I2C_DONE,// I2C transfer is complete
I2C_START ,
I2C_END,
I2C_OK,
I2C_SEND_ADDRESS,
I2C_CLEAR_ADDRESS_FLAG,
} i2c_process_enum;
extern volatile uint8_t i2c_slave_address;
extern volatile uint8_t i2c_read_process;
extern volatile uint8_t i2c_write_process;
extern volatile uint8_t i2c_error_code;
extern volatile uint8_t* i2c_write;
extern volatile uint8_t* i2c_read;
extern volatile uint16_t i2c_nbytes;
extern volatile uint16_t i2c_write_dress;
extern volatile uint16_t i2c_read_dress;
extern volatile uint8_t i2c_process_flag;
#ifdef __cplusplus
}
#endif
#endif /* BSP_MINIWARE_IRQ_H_ */

31
workspace/TS100/Core/BSP/Pine64/Model_Config.h Normal file
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/*
* Model_Config.h
*
* Created on: 25 Jul 2020
* Author: Ralim
*/
#ifndef BSP_MINIWARE_MODEL_CONFIG_H_
#define BSP_MINIWARE_MODEL_CONFIG_H_
/*
* Lookup for mapping features <-> Models
*/
#if defined(MODEL_Pinecil) == 0
#error "No model defined!"
#endif
#ifdef MODEL_Pinecil
#define POW_PD
#define POW_QC
#define POW_DC
#define POW_QC_20V
#define ENABLE_QC2
#define TEMP_TMP36
#define ACCEL_BMA
#define HALL_SENSOR
#define HALL_SI7210
#define BATTFILTERDEPTH 32
#endif
#endif /* BSP_MINIWARE_MODEL_CONFIG_H_ */

318
workspace/TS100/Core/BSP/Pine64/N200/port.c Normal file
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#include "FreeRTOSConfig.h"
//
#include "FreeRTOS.h"
#include "gd32vf103.h"
#include "n200_eclic.h"
#include "n200_func.h"
#include "n200_timer.h"
#include "portmacro.h"
#include "riscv_encoding.h"
#include "task.h"
/* Standard Includes */
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
/* Each task maintains its own interrupt status in the critical nesting variable. */
UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
#if USER_MODE_TASKS
#ifdef __riscv_flen
unsigned long MSTATUS_INIT = (MSTATUS_MPIE | (0x1 << 13));
#else
unsigned long MSTATUS_INIT = (MSTATUS_MPIE);
#endif
#else
#ifdef __riscv_flen
unsigned long MSTATUS_INIT = (MSTATUS_MPP | MSTATUS_MPIE | (0x1 << 13));
#else
unsigned long MSTATUS_INIT = (MSTATUS_MPP | MSTATUS_MPIE);
#endif
#endif
/*
* Used to catch tasks that attempt to return from their implementing function.
*/
static void prvTaskExitError(void);
/**
* @brief System Call Trap
*
* @param mcause csr
* @param sp 触发系统调用时的栈地址
* @param arg1 ECALL macro stores argument in a2
* @return unsigned long 传入的sp
*/
unsigned long ulSynchTrap(unsigned long mcause, unsigned long sp, unsigned long arg1) {
switch (mcause & 0X00000fff) {
//on User and Machine ECALL, handler the request
case 8:
case 11: {
if (arg1 == IRQ_DISABLE) {
//zero out mstatus.mpie
clear_csr(mstatus, MSTATUS_MPIE);
} else if (arg1 == IRQ_ENABLE) {
//set mstatus.mpie
set_csr(mstatus, MSTATUS_MPIE);
} else if (arg1 == PORT_YIELD) {
//always yield from machine mode
//fix up mepc on sync trap
unsigned long epc = read_csr(mepc);
vPortYield_from_ulSynchTrap(sp, epc + 4);
} else if (arg1 == PORT_YIELD_TO_RA) {
vPortYield_from_ulSynchTrap(sp, (*(unsigned long *)(sp + 1 * sizeof(sp))));
}
break;
}
default: {
/* 异常处理 */
extern uintptr_t handle_trap(uintptr_t mcause, uintptr_t sp);
handle_trap(mcause, sp);
}
}
//fix mepc and return
unsigned long epc = read_csr(mepc);
write_csr(mepc, epc + 4);
return sp;
}
/*-----------------------------------------------------------*/
/**
* @brief 设置触发软中断
* @note 目的是在软中断内进行任务上下文切换
*
*/
void vPortSetMSIPInt(void) {
*(volatile uint8_t *)(TIMER_CTRL_ADDR + TIMER_MSIP) |= 0x01;
__asm volatile("fence");
__asm volatile("fence.i");
}
/*-----------------------------------------------------------*/
/**
* @brief 清除软中断
*
*/
void vPortClearMSIPInt(void) {
*(volatile uint8_t *)(TIMER_CTRL_ADDR + TIMER_MSIP) &= ~0x01;
}
/*-----------------------------------------------------------*/
/**
* @brief 执行任务上下文切换,在portasm.S中被调用
*
* @param sp 触发任务切换时的栈地址
* @param arg1
* @return unsigned long sp地址
*/
unsigned long taskswitch(unsigned long sp, unsigned long arg1) {
//always yield from machine mode
//fix up mepc on
unsigned long epc = read_csr(mepc);
vPortYield(sp, epc); //never returns
return sp;
}
/*-----------------------------------------------------------*/
/**
* @brief 调研freertos内建函数vTaskSwitchContext,在portasm.S中被调用
*
*/
void vDoTaskSwitchContext(void) {
portDISABLE_INTERRUPTS();
vTaskSwitchContext();
portENABLE_INTERRUPTS();
}
/*-----------------------------------------------------------*/
/**
* @brief 进入临界段
*
*/
void vPortEnterCritical(void) {
#if USER_MODE_TASKS
ECALL(IRQ_DISABLE);
#else
portDISABLE_INTERRUPTS();
#endif
uxCriticalNesting++;
}
/*-----------------------------------------------------------*/
/**
* @brief 退出临界段
*
*/
void vPortExitCritical(void) {
configASSERT(uxCriticalNesting);
uxCriticalNesting--;
if (uxCriticalNesting == 0) {
#if USER_MODE_TASKS
ECALL(IRQ_ENABLE);
#else
portENABLE_INTERRUPTS();
#endif
}
return;
}
/*-----------------------------------------------------------*/
/**
* @brief Clear current interrupt mask and set given mask
*
* @param int_mask mth值
*/
void vPortClearInterruptMask(int int_mask) {
eclic_set_mth(int_mask);
}
/*-----------------------------------------------------------*/
/**
* @brief Set interrupt mask and return current interrupt enable register
*
* @return int
*/
int xPortSetInterruptMask(void) {
int int_mask = 0;
int_mask = eclic_get_mth();
portDISABLE_INTERRUPTS();
return int_mask;
}
/*-----------------------------------------------------------*/
/**
* @brief 初始化任务栈帧
*
* @param pxTopOfStack 栈顶
* @param pxCode 任务入口
* @param pvParameters 任务参数
* @return StackType_t* 完成初始化后的栈顶
*/
StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) {
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
#ifdef __riscv_flen
pxTopOfStack -= 32; /* 浮点寄存器 */
#endif
pxTopOfStack--;
*pxTopOfStack = 0xb8000000; /* CSR_MCAUSE */
pxTopOfStack--;
*pxTopOfStack = 0x40; /* CSR_SUBM */
pxTopOfStack--;
*pxTopOfStack = (portSTACK_TYPE)pxCode; /* Start address */
pxTopOfStack--;
*pxTopOfStack = MSTATUS_INIT; /* CSR_MSTATUS */
pxTopOfStack -= 22;
*pxTopOfStack = (portSTACK_TYPE)pvParameters; /* Register a0 */
pxTopOfStack -= 9;
*pxTopOfStack = (portSTACK_TYPE)prvTaskExitError; /* Register ra */
pxTopOfStack--;
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
/**
* @brief 任务退出函数
*
*/
void prvTaskExitError(void) {
/* A function that implements a task must not exit or attempt to return to
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT(uxCriticalNesting == ~0UL);
portDISABLE_INTERRUPTS();
for (;;)
;
}
/*-----------------------------------------------------------*/
/**
* @brief tick中断
* @note 由于该中断配置为向量模式，则中断到来会调用portasm.S的MTIME_HANDLER,进行栈帧保存之后该函数会调用vPortSysTickHandler
*
*/
void vPortSysTickHandler(void) {
volatile uint64_t *mtime = (uint64_t *)(TIMER_CTRL_ADDR + TIMER_MTIME);
volatile uint64_t *mtimecmp = (uint64_t *)(TIMER_CTRL_ADDR + TIMER_MTIMECMP);
UBaseType_t uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
#if CONFIG_SYSTEMVIEW_EN
traceISR_ENTER();
#endif
uint64_t now = *mtime;
now += (configRTC_CLOCK_HZ / configTICK_RATE_HZ);
*mtimecmp = now;
/* 调用freertos的tick增加接口 */
if (xTaskIncrementTick() != pdFALSE) {
#if CONFIG_SYSTEMVIEW_EN
traceISR_EXIT_TO_SCHEDULER();
#endif
portYIELD();
}
#if CONFIG_SYSTEMVIEW_EN
else {
traceISR_EXIT();
}
#endif
portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedInterruptStatus);
}
/*-----------------------------------------------------------*/
/**
* @brief 初始化tick
*
*/
void vPortSetupTimer(void) {
/* 内核timer定时器使用64位的计数器来实现 */
volatile uint64_t *mtime = (uint64_t *)(TIMER_CTRL_ADDR + TIMER_MTIME);
volatile uint64_t *mtimecmp = (uint64_t *)(TIMER_CTRL_ADDR + TIMER_MTIMECMP);
portENTER_CRITICAL();
uint64_t now = *mtime;
now += (configRTC_CLOCK_HZ / configTICK_RATE_HZ);
*mtimecmp = now;
portEXIT_CRITICAL();
eclic_set_vmode(CLIC_INT_TMR);
eclic_irq_enable(CLIC_INT_TMR, configKERNEL_INTERRUPT_PRIORITY >> configPRIO_BITS, 0);
}
/*-----------------------------------------------------------*/
/**
* @brief 初始化软中断
*
*/
void vPortSetupMSIP(void) {
eclic_set_vmode(CLIC_INT_SFT);
eclic_irq_enable(CLIC_INT_SFT, configKERNEL_INTERRUPT_PRIORITY >> configPRIO_BITS, 0);
}
/*-----------------------------------------------------------*/
/**
* @brief 调度启动前的初始化准备
*
*/
void vPortSetup(void) {
vPortSetupTimer();
vPortSetupMSIP();
uxCriticalNesting = 0;
}
/*-----------------------------------------------------------*/

730
workspace/TS100/Core/BSP/Pine64/N200/portasm.S Normal file
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@@ -0,0 +1,730 @@
#include "riscv_encoding.h"
#include "riscv_bits.h"
#include "n200_timer.h"
#include "n200_eclic.h"
#define USE_MSP 1 //启用中断栈
.section .text.entry
.align 4
.global vPortYield
.global vPortYield_from_ulSynchTrap
.global xPortStartScheduler
.global vPortEndScheduler
.global vPortAsmAssertSP
.section .init
.weak eclic_msip_handler //弱定义函数，这些在编译为bin后可以看到将全部为0
.weak eclic_mtip_handler
.weak eclic_bwei_handler
.weak eclic_pmovi_handler
.weak WWDGT_IRQHandler
.weak LVD_IRQHandler
.weak TAMPER_IRQHandler
.weak RTC_IRQHandler
.weak FMC_IRQHandler
.weak RCU_IRQHandler
.weak EXTI0_IRQHandler
.weak EXTI1_IRQHandler
.weak EXTI2_IRQHandler
.weak EXTI3_IRQHandler
.weak EXTI4_IRQHandler
.weak DMA0_Channel0_IRQHandler
.weak DMA0_Channel1_IRQHandler
.weak DMA0_Channel2_IRQHandler
.weak DMA0_Channel3_IRQHandler
.weak DMA0_Channel4_IRQHandler
.weak DMA0_Channel5_IRQHandler
.weak DMA0_Channel6_IRQHandler
.weak ADC0_1_IRQHandler
.weak CAN0_TX_IRQHandler
.weak CAN0_RX0_IRQHandler
.weak CAN0_RX1_IRQHandler
.weak CAN0_EWMC_IRQHandler
.weak EXTI5_9_IRQHandler
.weak TIMER0_BRK_IRQHandler
.weak TIMER0_UP_IRQHandler
.weak TIMER0_TRG_CMT_IRQHandler
.weak TIMER0_Channel_IRQHandler
.weak TIMER1_IRQHandler
.weak TIMER2_IRQHandler
.weak TIMER3_IRQHandler
.weak I2C0_EV_IRQHandler
.weak I2C0_ER_IRQHandler
.weak I2C1_EV_IRQHandler
.weak I2C1_ER_IRQHandler
.weak SPI0_IRQHandler
.weak SPI1_IRQHandler
.weak USART0_IRQHandler
.weak USART1_IRQHandler
.weak USART2_IRQHandler
.weak EXTI10_15_IRQHandler
.weak RTC_Alarm_IRQHandler
.weak USBFS_WKUP_IRQHandler
.weak EXMC_IRQHandler
.weak TIMER4_IRQHandler
.weak SPI2_IRQHandler
.weak UART3_IRQHandler
.weak UART4_IRQHandler
.weak TIMER5_IRQHandler
.weak TIMER6_IRQHandler
.weak DMA1_Channel0_IRQHandler
.weak DMA1_Channel1_IRQHandler
.weak DMA1_Channel2_IRQHandler
.weak DMA1_Channel3_IRQHandler
.weak DMA1_Channel4_IRQHandler
.weak CAN1_TX_IRQHandler
.weak CAN1_RX0_IRQHandler
.weak CAN1_RX1_IRQHandler
.weak CAN1_EWMC_IRQHandler
.weak USBFS_IRQHandler
vector_base: //中断向量表
j _start //第一条指令即跳转到_start处开始执行
.align 2
.word 0
.word 0
.word eclic_msip_handler
.word 0
.word 0
.word 0
.word eclic_mtip_handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word eclic_bwei_handler
.word eclic_pmovi_handler
.word WWDGT_IRQHandler
.word LVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FMC_IRQHandler
.word RCU_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA0_Channel0_IRQHandler
.word DMA0_Channel1_IRQHandler
.word DMA0_Channel2_IRQHandler
.word DMA0_Channel3_IRQHandler
.word DMA0_Channel4_IRQHandler
.word DMA0_Channel5_IRQHandler
.word DMA0_Channel6_IRQHandler
.word ADC0_1_IRQHandler
.word CAN0_TX_IRQHandler
.word CAN0_RX0_IRQHandler
.word CAN0_RX1_IRQHandler
.word CAN0_EWMC_IRQHandler
.word EXTI5_9_IRQHandler
.word TIMER0_BRK_IRQHandler
.word TIMER0_UP_IRQHandler
.word TIMER0_TRG_CMT_IRQHandler
.word TIMER0_Channel_IRQHandler
.word TIMER1_IRQHandler
.word TIMER2_IRQHandler
.word TIMER3_IRQHandler
.word I2C0_EV_IRQHandler
.word I2C0_ER_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word SPI0_IRQHandler
.word SPI1_IRQHandler
.word USART0_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word EXTI10_15_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBFS_WKUP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word EXMC_IRQHandler
.word 0
.word TIMER4_IRQHandler
.word SPI2_IRQHandler
.word UART3_IRQHandler
.word UART4_IRQHandler
.word TIMER5_IRQHandler
.word TIMER6_IRQHandler
.word DMA1_Channel0_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word 0
.word 0
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_EWMC_IRQHandler
.word USBFS_IRQHandler
.globl _start
.type _start,@function
_start:
csrc CSR_MSTATUS, MSTATUS_MIE //CSR_MSTATUS &= ~0x8 mstatus[3]:0屏蔽全部中断 1不屏蔽全部中断 （当然这里全部中断是除过不可屏蔽中断）
/* Jump to logical address first to ensure correct operation of RAM region */
la a0, _start //a0 = _start
li a1, 1 //a1 = 1
slli a1, a1, 29 //a1 = 0x20000000 raw起始地址
bleu a1, a0, _start0800 //if( a1 <= a0 ) JUMP _start0800
srli a1, a1, 2 //a1 = 0x08000000 flash起始地址
bleu a1, a0, _start0800 //if( a1 <= a0 ) JUMP _start0800
la a0, _start0800 //a0 = _start0800
add a0, a0, a1 //a0 = a0+a1
jr a0 //JUMP a0
_start0800:
/* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
li t0, 0x200 //t0 = 0x200
csrs CSR_MMISC_CTL, t0 //mmisc_ctl |= 0x200 CSR_MMISC_CTL[9]：设置NMI的地址与mtvec相同且，mcause.EXCCODE = 0xfff
//cs开头的指令是特有的用来操作内核寄存器的的指令，内核寄存器是一组特有的12位地址
/* Intial the mtvt*/
la t0, vector_base //t0 = vector_base 向量表地址
csrw CSR_MTVT, t0 //mtvt = vector_base 中断向量表基地址
/* Intial the mtvt2 and enable it*/
la t0, irq_entry //t0 = irq_entry irq_entry定义在entry.S,有freertos操作系统情况下定义在portasm.S
csrw CSR_MTVT2, t0 //mtvt2 = irq_entry mtvt2[31:2]: 中断入口函数地址
csrs CSR_MTVT2, 0x1 //mtvt2 |= 0x1 mtvt2[0]: 1配置mtvt2的配置有效，配0则为mtvec内地址
/* Intial the CSR MTVEC for the Trap ane NMI base addr*/
la t0, trap_entry //t0 = trap_entry trap_entry定义在entry.S,有freertos操作系统情况下定义在portasm.S
csrw CSR_MTVEC, t0 //mtvec = trap_entry mtvec[31:6]：异常入口地址
// mtvec[5:0]：0B00011 -- ECLIC中断模式 其他：默认模式
// 这里配置为默认模式
// trap_entry基本上可以理解为arm里的hard/mem/use/svc等fault了，
// 这里在移植freertos时就使用了 ecall 进入trap_entry里 相当于arm里的PendSVC
/* OS启动前配置中断栈为FHEAP的end地址 */
la t0, ucHeap
csrw CSR_MSCRATCH, t0
#ifdef __riscv_flen //浮点宏
/* Enable FPU */
li t0, MSTATUS_FS //t0 = 0x6000
csrs mstatus, t0 //mstatus |= 0x6000 mstatus[14:13]:非零值启用浮点单元，配置为1或2会在第一次使用浮点单元时变为3，这里直接配置为3
csrw fcsr, x0 //fcsr = x0 = 0 ??这里x0是否指的是zero通用寄存器值? 这个寄存器0-4位是浮点异常状态标志，5-7位是浮点舍入模式配置
#endif
.option push
.option norelax
la gp, __global_pointer$ //__global_pointer$定义在link连接脚本内，指向所有.data段后偏移0x800的地址,0x800为2K，其值源于下文解释
//gp 意为global pointer （全局指针）寄存器是一个解决方案，
//为了以进一步优化存储器访问单个4KB区域内。
//链接器使用__global_pointer$符号定义来比较内存地址，如果在范围内，
//则它将绝对/相对pc寻址替换为gp相对寻址，从而使代码更有效。这个过程通过-Wl,--no-relax选项使用。
//这里.option norelax起到-Wl,--no-relax作用，就不需要在编译选项添加了
//上文参考自：https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register
//要让 relaxing 优化起作用，编译时要加入 -msmall-data-limit=n 参数，有了这个参数，
//编译器会把内存空间小于 n 字节的静态变量放入 .sdata 或者 .sdata.* 节，
//然后链接器将这部分静态变量集中在 __global_pointer$ +/- 2K 的范围内。
//上文参考自：https://blog.csdn.net/zoomdy/article/details/100703451
.option pop
la sp, _sp //sp = 主栈栈顶地址 _sp定义在link连接脚本内
/* Load data section */
la a0, _data_lma //a0 = data的Load Memory Address _data_lma定义在link连接脚本内
la a1, _data //a1 = data的Run Memory Address _data定义在link连接脚本内
la a2, _edata //a2 = data的Run Memory Address结束地址 _edata定义在link连接脚本内
bgeu a1, a2, 2f //if( a1 >= a2 ) JUMP 2f 原则上不会出现_data地址大于_edata地址
//如果出现了则直接跳转到 2f 即下一个2标签
1:
lw t0, (a0) //t0 = _data_lma
sw t0, (a1) //*_data = t0 即 *_data_lma，按word写入
addi a0, a0, 4 //a0 = a0 + 4 下一个ward
addi a1, a1, 4 //a1 = a1 + 4
bltu a1, a2, 1b //if( a1 < a2 ) JUMP 1b 如果未到达_edata则跳转到 1b 即上一个1标签，这里会完成一个循环
2:
/* Clear bss section */
la a0, __bss_start //a0 = __bss_start 初值为0的全局变量段起始地址 __bss_start定义在link连接脚本内
la a1, _end //a1 = _end 初值为0的全局变量段结束地址 _end定义在link连接脚本内
bgeu a0, a1, 2f //if( a0 >= a1 ) JUMP 2f 原则上不会出现__bss_start地址大于_end地址
//如果出现了则直接跳转到 2f 即下一个2标签
1:
sw zero, (a0) //*__bss_start = zero = 0 bss段清除为0
addi a0, a0, 4 //a0 = a0 + 4 下一个ward
bltu a0, a1, 1b //if( a0 < a1 ) JUMP 1b 如果未到达_end则跳转到 1b 即上一个1标签，这里会完成一个循环
//程序执行到这里全局变量就以及处理完毕了
2:
/*enable mcycle_minstret*/
csrci CSR_MCOUNTINHIBIT, 0x5 //CSR_MCOUNTINHIBIT &= ~0x5 这里清零了第0bit和第1bit，使能了mcycle计数和minstret计数
//csrci这条指令处理立即数5bit，列如0x5只是0B00101，高位不处理
/*
* Call vendor defined SystemInit to
* initialize the micro-controller system
*/
call SystemInit
/* Call global constructors */
la a0, __libc_fini_array //a0 = __libc_fini_array newlib中atexit函数的参数
call atexit //调用newlib中的 void atexit(void (*func)(void)) 函数
//功能为注册main函数结束后调用的函数，这里是__libc_fini_array
call __libc_init_array //调用newlib中的 void __libc_init_array (void) 函数
//这里要注意__libc_init_array函数会调用_init的钩子函数，用来做c环境初始化前的一些硬件初始化
//列如时钟的配置等，这里_init定义在init.c
//程序执行到这里C/C++环境就初始化完成了，可以进入main函数入口了
/* argc = argv = 0 */
li a0, 0 //a0 = 0 main函数参数argc = 0
li a1, 0 //a1 = 0 main函数参数argv = 0
call main //调用 int main(int argc,char **argv) 函数
tail exit //main返回后调用newlib的exit函数, tail指令应该是不会返回的调用函数了
1:
j 1b //1b 即上一次1标签，即跳转到自己，程序到这里就死循环了，原则不会运行到这里
.global disable_mcycle_minstret
disable_mcycle_minstret:
csrsi CSR_MCOUNTINHIBIT, 0x5 //关闭了mcycle计数和minstret计数
ret
.global enable_mcycle_minstret
enable_mcycle_minstret:
csrci CSR_MCOUNTINHIBIT, 0x5 //使能了mcycle计数和minstret计数
ret
/**
* @brief 压栈通用寄存器
* @param x 目标sp寄存器
*/
.macro pushREGFILE x
#ifdef __riscv_flen
addi \x, \x, -REGBYTES * 68 //36+32
#else
addi \x, \x, -REGBYTES * 36
#endif
STORE x1, 1 * REGBYTES(\x)
STORE x2, 2 * REGBYTES(\x)
#STORE x3, 3 * REGBYTES(\x)
#STORE x4, 4 * REGBYTES(\x)
STORE x5, 5 * REGBYTES(\x)
STORE x6, 6 * REGBYTES(\x)
STORE x7, 7 * REGBYTES(\x)
STORE x8, 8 * REGBYTES(\x)
STORE x9, 9 * REGBYTES(\x)
STORE x10, 10 * REGBYTES(\x)
STORE x11, 11 * REGBYTES(\x)
STORE x12, 12 * REGBYTES(\x)
STORE x13, 13 * REGBYTES(\x)
STORE x14, 14 * REGBYTES(\x)
STORE x15, 15 * REGBYTES(\x)
#ifndef __riscv_32e
STORE x16, 16 * REGBYTES(\x)
STORE x17, 17 * REGBYTES(\x)
STORE x18, 18 * REGBYTES(\x)
STORE x19, 19 * REGBYTES(\x)
STORE x20, 20 * REGBYTES(\x)
STORE x21, 21 * REGBYTES(\x)
STORE x22, 22 * REGBYTES(\x)
STORE x23, 23 * REGBYTES(\x)
STORE x24, 24 * REGBYTES(\x)
STORE x25, 25 * REGBYTES(\x)
STORE x26, 26 * REGBYTES(\x)
STORE x27, 27 * REGBYTES(\x)
STORE x28, 28 * REGBYTES(\x)
STORE x29, 29 * REGBYTES(\x)
STORE x30, 30 * REGBYTES(\x)
STORE x31, 31 * REGBYTES(\x)
#endif
.endm
/**
* @brief 压栈csr寄存器（CSR_MSTATUS、CSR_MEPC、CSR_MSUBM、CSR_MCAUSE）
* @param x 目标sp寄存器
*/
.macro portSAVE_CONTEXT_EXCP x
csrr t0, CSR_MSTATUS
STORE t0, 32 * REGBYTES(\x)
csrr t0, CSR_MEPC
STORE t0, 33 * REGBYTES(\x)
csrr t0, CSR_MSUBM
STORE t0, 34 * REGBYTES(\x)
csrr t0, CSR_MCAUSE
STORE t0, 35 * REGBYTES(\x)
.endm
/**
* @brief 压栈浮点寄存器
* @param x 目标sp寄存器
*/
.macro popVFPREGFILE x
flw f0, 36 * REGBYTES(\x)
flw f1, 37 * REGBYTES(\x)
flw f2, 38 * REGBYTES(\x)
flw f3, 39 * REGBYTES(\x)
flw f4, 40 * REGBYTES(\x)
flw f5, 41 * REGBYTES(\x)
flw f6, 42 * REGBYTES(\x)
flw f7, 43 * REGBYTES(\x)
flw f8, 44 * REGBYTES(\x)
flw f9, 45 * REGBYTES(\x)
flw f10,46 * REGBYTES(\x)
flw f11, 47 * REGBYTES(\x)
flw f12, 48 * REGBYTES(\x)
flw f13, 49 * REGBYTES(\x)
flw f14, 50 * REGBYTES(\x)
flw f15, 51 * REGBYTES(\x)
flw f16, 52 * REGBYTES(\x)
flw f17, 53 * REGBYTES(\x)
flw f18, 54 * REGBYTES(\x)
flw f19, 55 * REGBYTES(\x)
flw f20, 56 * REGBYTES(\x)
flw f21, 57 * REGBYTES(\x)
flw f22, 58 * REGBYTES(\x)
flw f23, 59 * REGBYTES(\x)
flw f24, 60 * REGBYTES(\x)
flw f25, 61 * REGBYTES(\x)
flw f26, 62 * REGBYTES(\x)
flw f27, 63 * REGBYTES(\x)
flw f28, 64 * REGBYTES(\x)
flw f29, 65 * REGBYTES(\x)
flw f30, 66 * REGBYTES(\x)
flw f31, 67 * REGBYTES(\x)
.endm
/**
* @brief 出栈通用寄存器
* @param x 目标sp寄存器
*/
.macro popREGFILE x
LOAD x1, 1 * REGBYTES(\x)
#LOAD x2, 2 * REGBYTES(\x)
#LOAD x3, 3 * REGBYTES(\x)
#LOAD x4, 4 * REGBYTES(\x)
LOAD x5, 5 * REGBYTES(\x)
LOAD x6, 6 * REGBYTES(\x)
LOAD x7, 7 * REGBYTES(\x)
LOAD x8, 8 * REGBYTES(\x)
LOAD x9, 9 * REGBYTES(\x)
LOAD x10, 10 * REGBYTES(\x)
LOAD x11, 11 * REGBYTES(\x)
LOAD x12, 12 * REGBYTES(\x)
LOAD x13, 13 * REGBYTES(\x)
LOAD x14, 14 * REGBYTES(\x)
LOAD x15, 15 * REGBYTES(\x)
#ifndef __riscv_32e
LOAD x16, 16 * REGBYTES(\x)
LOAD x17, 17 * REGBYTES(\x)
LOAD x18, 18 * REGBYTES(\x)
LOAD x19, 19 * REGBYTES(\x)
LOAD x20, 20 * REGBYTES(\x)
LOAD x21, 21 * REGBYTES(\x)
LOAD x22, 22 * REGBYTES(\x)
LOAD x23, 23 * REGBYTES(\x)
LOAD x24, 24 * REGBYTES(\x)
LOAD x25, 25 * REGBYTES(\x)
LOAD x26, 26 * REGBYTES(\x)
LOAD x27, 27 * REGBYTES(\x)
LOAD x28, 28 * REGBYTES(\x)
LOAD x29, 29 * REGBYTES(\x)
LOAD x30, 30 * REGBYTES(\x)
LOAD x31, 31 * REGBYTES(\x)
#endif
#ifdef __riscv_flen
addi \x, \x, REGBYTES * 68 //36+32
#else
addi \x, \x, REGBYTES * 36
#endif
.endm
/**
* @brief 出栈csr寄存器（CSR_MSTATUS、CSR_MEPC、CSR_MSUBM、CSR_MCAUSE）
* @param x 目标sp寄存器
*/
.macro portRESTORE_CONTEXT_EXCP x
LOAD t0, 35*REGBYTES(\x)
csrw CSR_MCAUSE, t0
LOAD t0, 34*REGBYTES(\x)
csrw CSR_MSUBM, t0
LOAD t0, 33*REGBYTES(\x)
csrw CSR_MEPC, t0
LOAD t0, 32*REGBYTES(\x)
csrw CSR_MSTATUS, t0
.endm
/**
* @brief 出栈浮点寄存器
* @param x 目标sp寄存器
*/
.macro pushVFPREGFILE x
fsw f0, 36 * REGBYTES(\x)
fsw f1, 37 * REGBYTES(\x)
fsw f2, 38 * REGBYTES(\x)
fsw f3, 39 * REGBYTES(\x)
fsw f4, 40 * REGBYTES(\x)
fsw f5, 41 * REGBYTES(\x)
fsw f6, 42 * REGBYTES(\x)
fsw f7, 43 * REGBYTES(\x)
fsw f8, 44 * REGBYTES(\x)
fsw f9, 45 * REGBYTES(\x)
fsw f10, 46 * REGBYTES(\x)
fsw f11, 47 * REGBYTES(\x)
fsw f12, 48 * REGBYTES(\x)
fsw f13, 49 * REGBYTES(\x)
fsw f14, 50 * REGBYTES(\x)
fsw f15, 51 * REGBYTES(\x)
fsw f16, 52 * REGBYTES(\x)
fsw f17, 53 * REGBYTES(\x)
fsw f18, 54 * REGBYTES(\x)
fsw f19, 55 * REGBYTES(\x)
fsw f20, 56 * REGBYTES(\x)
fsw f21, 57 * REGBYTES(\x)
fsw f22, 58 * REGBYTES(\x)
fsw f23, 59 * REGBYTES(\x)
fsw f24, 60 * REGBYTES(\x)
fsw f25, 61 * REGBYTES(\x)
fsw f26, 62 * REGBYTES(\x)
fsw f27, 63 * REGBYTES(\x)
fsw f28, 64 * REGBYTES(\x)
fsw f29, 65 * REGBYTES(\x)
fsw f30, 66 * REGBYTES(\x)
fsw f31, 67 * REGBYTES(\x)
.endm
/**
* @brief 清理fpu状态寄存器
*/
.macro CONFIG_FS_CLEAN
li t0, (0x1 << 13) //配置FS为clean状态
csrc mstatus, t0
li t0, (0x1 << 14)
csrs mstatus, t0
.endm
/* -------------------------------------------------------------------------------------------------------- */
/**
* @brief trap入口函数
*/
.section .text.trap
.align 6// In CLIC mode, the trap entry must be 64bytes aligned
.global trap_entry
.weak trap_entry
trap_entry:
pushREGFILE sp //trap这里就直接使用当前栈，方便对当前位置进行异常分析，
//同时不担心(任务栈/中断栈/主栈)溢出，因为程序进入这里便不会返回了
portSAVE_CONTEXT_EXCP sp
csrr a0, mcause
mv a1, sp
jal ulSynchTrap
mv sp, a0
portRESTORE_CONTEXT_EXCP sp
popREGFILE sp
mret
/* -------------------------------------------------------------------------------------------------------- */
/**
* @brife trq入口函数
*/
.align 2
.global irq_entry
irq_entry:
#if USE_MSP
csrrw sp, CSR_MSCRATCHCSWL, sp
#endif
pushREGFILE sp
portSAVE_CONTEXT_EXCP sp
#ifdef __riscv_flen
csrr t2, mstatus
li t0, (0x3 << 13)
and t1,t2,t0
bne t1,t0,1f
pushVFPREGFILE sp
1:
CONFIG_FS_CLEAN
#endif
int_loop:
csrrw ra, CSR_JALMNXTI, ra
csrrsi a0, CSR_MNXTI, MSTATUS_MIE
bnez a0, int_loop
csrc CSR_MSTATUS, MSTATUS_MIE
#ifdef __riscv_flen
csrr t2, mstatus
li t0, (0x3 << 13)
and t1,t2, t0
bne t1,t0, 2f
popVFPREGFILE sp
2:
#endif
portRESTORE_CONTEXT_EXCP sp
#ifdef __riscv_flen
CONFIG_FS_CLEAN
#endif
popREGFILE sp
#if USE_MSP
csrrw sp, CSR_MSCRATCHCSWL, sp
#endif
mret
/* -------------------------------------------------------------------------------------------------------- */
/**
* @brife MTIME入口函数
*/
.align 2
.globl MTIME_HANDLER
MTIME_HANDLER:
#if USE_MSP
csrrw sp, CSR_MSCRATCHCSWL, sp
#endif
pushREGFILE sp
portSAVE_CONTEXT_EXCP sp
csrs CSR_MSTATUS, MSTATUS_MIE
jal vPortSysTickHandler
csrc CSR_MSTATUS, MSTATUS_MIE
portRESTORE_CONTEXT_EXCP sp
popREGFILE sp
#if USE_MSP
csrrw sp, CSR_MSCRATCHCSWL, sp
#endif
mret
/* -------------------------------------------------------------------------------------------------------- */
/**
* @brife MSIP入口函数
*/
.align 2
.globl MSIP_HANDLER
MSIP_HANDLER:
pushREGFILE sp
portSAVE_CONTEXT_EXCP sp
mv a0,sp
call vPortClearMSIPInt
jal taskswitch
portRESTORE_CONTEXT_EXCP sp
popREGFILE sp
mret
/* -------------------------------------------------------------------------------------------------------- */
/**
* @brife Trap模式请求切换任务函数
*/
.align 6
vPortYield_from_ulSynchTrap:
mv sp, a0
portSAVE_CONTEXT_EXCP sp
j _vPortYield
/* -------------------------------------------------------------------------------------------------------- */
/**
* @brife MSIP模式请求切换任务函数
*/
.align 6
vPortYield:
mv sp, a0
_vPortYield:
LOAD t0, pxCurrentTCB
STORE sp, 0x0(t0)
#ifdef __riscv_flen
csrr t2, mstatus
li t0, (0x3 << 13)
and t1,t2,t0
bne t1,t0,1f
pushVFPREGFILE sp
1:
CONFIG_FS_CLEAN
#endif
STORE a1, 33 * REGBYTES(sp)
#if USE_MSP
csrr sp, CSR_MSCRATCH
#endif
csrs CSR_MSTATUS, MSTATUS_MIE
jal vDoTaskSwitchContext
csrc CSR_MSTATUS, MSTATUS_MIE
LOAD sp, pxCurrentTCB
LOAD sp, 0x0(sp)
portRESTORE_CONTEXT_EXCP sp
#ifdef __riscv_flen
csrr t2, mstatus
li t0, (0x3 << 13)
and t1, t2, t0
bne t1, t0, 2f
popVFPREGFILE sp
2:
CONFIG_FS_CLEAN
#endif
popREGFILE sp
mret
/* -------------------------------------------------------------------------------------------------------- */
/**
* @brife freertos启动调度函数
*/
xPortStartScheduler:
jal vPortSetup
csrc CSR_MSTATUS, MSTATUS_MIE
#if USE_MSP
la t0, _sp
csrw CSR_MSCRATCH, t0
#endif
LOAD sp, pxCurrentTCB
LOAD sp, 0x0(sp)
portRESTORE_CONTEXT_EXCP sp
popREGFILE sp
mret
/* -------------------------------------------------------------------------------------------------------- */
/**
* @brife MSIP模式请求切换任务函数
*/
vPortEndScheduler:
j vPortEndScheduler
/* Default Handler for Exceptions / Interrupts */
.global default_intexc_handler
.weak default_intexc_handler
Undef_Handler:
default_intexc_handler:
1:
j 1b

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workspace/TS100/Core/BSP/Pine64/N200/portmacro.h Normal file
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#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "n200_func.h"
#include "riscv_encoding.h"
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t;
typedef unsigned long UBaseType_t;
#if (configUSE_16_BIT_TICKS == 1)
typedef uint16_t TickType_t;
#define portMAX_DELAY (TickType_t)0xffff
#else
typedef uint32_t TickType_t;
#define portMAX_DELAY (TickType_t)0xffffffffUL
#endif
/*-----------------------------------------------------------*/
/* Architecture specifics. */
#define portSTACK_GROWTH (-1)
#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
/* Architecture specifics. */
extern void vPortYield(unsigned long, unsigned long);
extern void vPortYield_from_ulSynchTrap(unsigned long, unsigned long);
extern int xPortSetInterruptMask(void);
extern void vPortClearInterruptMask(int uxSavedStatusValue);
/*-----------------------------------------------------------*/
/*System Calls */
/*-----------------------------------------------------------*/
//ecall macro used to store argument in a3
#define ECALL(arg) ({ \
register uintptr_t a2 asm("a2") = (uintptr_t)(arg); \
asm volatile("ecall" \
: "+r"(a2) \
: \
: "memory"); \
a2; \
})
extern void vPortSetMSIPInt(void);
#define port_MSIPSET_BIT vPortSetMSIPInt()
#define IRQ_DISABLE 20
#define IRQ_ENABLE 30
#define PORT_YIELD 40
#define PORT_YIELD_TO_RA 50
/*-----------------------------------------------------------*/
/* Scheduler utilities. */
/* the return after the ECALL is VERY important */
//#define portYIELD() ECALL(PORT_YIELD);
#define portYIELD() port_MSIPSET_BIT;
#ifdef CONFIG_SYSTEMVIEW_EN
#define portEND_SWITCHING_ISR(xSwitchRequired) \
{ \
if (xSwitchRequired != pdFALSE) { \
traceISR_EXIT_TO_SCHEDULER(); \
portYIELD(); \
} else { \
traceISR_EXIT(); \
} \
}
#else
#define portEND_SWITCHING_ISR(xSwitchRequired) \
if (xSwitchRequired != pdFALSE) \
portYIELD()
#endif
#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
/* Critical section management. */
extern void vPortEnterCritical(void);
extern void vPortExitCritical(void);
extern void eclic_set_mth(uint8_t mth);
#define portDISABLE_INTERRUPTS() \
{ \
eclic_set_mth((configMAX_SYSCALL_INTERRUPT_PRIORITY) | 0x1f); \
__asm volatile("fence"); \
__asm volatile("fence.i"); \
}
#define portENABLE_INTERRUPTS() eclic_set_mth(0)
#define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedStatusValue) vPortClearInterruptMask(uxSavedStatusValue)
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
not necessary for to use this port. They are defined so the common demo files
(which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
#ifndef portSUPPRESS_TICKS_AND_SLEEP
extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
#define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime)
#endif
/*-----------------------------------------------------------*/
#define portINLINE __inline
#ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__((always_inline))
#endif
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */

38
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# Notes on RISC-V
## Pinmap
| Pin Number | Name | Function | Notes |
| ---------- | ---- | ---------------- | ----------- |
| 17 | PB2 | BOOT2 | Pulldown |
| 32 | | IMU INT 1 | N/A |
| 30 | | IMU INT 2 | N/A |
| | PA4 | Handle Temp | ADC Input ? |
| | PA1 | Tip Temp | ADC Input ? |
| | PB1 | B Button | Active High |
| | PB0 | A Button | Active High |
| | PA11 | USB D- | - |
| | PA12 | USB D+ | - |
| | PA6 | Tip PWM Out | - |
| | PA0 | Input DC V Sense | ADC Input ? |
| | PA9 | OLED Reset | |
| | PB7 | SDA | I2C0_SDA |
| | PB6 | SCL | I2C0_SCL |
## ADC Configuration
For now running in matching mode for TS100
- X channels DMA in background
- Sample tip using "Intereted" channels using TIMER 0,1,3 TRGO or timer0,1,2 channels
- Using just 12 bit mode for now and move to hardware oversampling later
- use DMA for normal samples and 4x16 bit regs for tip temp
- It has dual ADC's so run them in pair mode
## Timers
### Timer 2
Timer 2 CH0 is tip drive PWM out.
This is fixed at 50% duty cycle and used via the cap to turn on the heater tip.
This should toggle relatively quickly.

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/*
* Pins.h
*
* Created on: 29 May 2020
* Author: Ralim
*/
#ifndef BSP_MINIWARE_PINS_H_
#define BSP_MINIWARE_PINS_H_
#include "Vendor/Lib/gd32vf103_gpio.h"
//TODO
#define KEY_B_Pin BIT(1)
#define KEY_B_GPIO_Port GPIOB
#define TMP36_INPUT_Pin BIT(4)
#define TMP36_INPUT_GPIO_Port GPIOA
#define TMP36_ADC0_CHANNEL ADC_CHANNEL_4
#define TMP36_ADC1_CHANNEL ADC_CHANNEL_4
#define TIP_TEMP_Pin BIT(1)
#define TIP_TEMP_GPIO_Port GPIOA
#define TIP_TEMP_ADC0_CHANNEL ADC_CHANNEL_1
#define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_1
#define VIN_Pin BIT(0)
#define VIN_GPIO_Port GPIOA
#define VIN_ADC0_CHANNEL ADC_CHANNEL_0
#define VIN_ADC1_CHANNEL ADC_CHANNEL_0
#define OLED_RESET_Pin BIT(9)
#define OLED_RESET_GPIO_Port GPIOA
#define KEY_A_Pin BIT(0)
#define KEY_A_GPIO_Port GPIOB
#define PWM_Out_Pin BIT(6)
#define PWM_Out_GPIO_Port GPIOA
#define SCL_Pin BIT(6)
#define SCL_GPIO_Port GPIOB
#define SDA_Pin BIT(7)
#define SDA_GPIO_Port GPIOB
#define USB_DM_Pin BIT(11)
#define USB_DM_LOW_GPIO_Port GPIOA
#define QC_DP_LOW_Pin BIT(7)
#define QC_DP_LOW_GPIO_Port GPIOA
// LOW = low resistance, HIGH = high resistance
#define QC_DM_LOW_Pin BIT(8)
#define QC_DM_LOW_GPIO_Port GPIOA
#define QC_DM_HIGH_Pin BIT(10)
#define QC_DM_HIGH_GPIO_Port GPIOA
#define FUSB302_IRQ_Pin BIT(5)
#define FUSB302_IRQ_GPIO_Port GPIOB
#endif /* BSP_MINIWARE_PINS_H_ */

49
workspace/TS100/Core/BSP/Pine64/Power.cpp Normal file
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#include "BSP.h"
#include "BSP_Power.h"
#include "QC3.h"
#include "Settings.h"
#include "Pins.h"
#include "fusbpd.h"
#include "Model_Config.h"
#include "policy_engine.h"
#include "int_n.h"
bool FUSB302_present = false;
void power_check() {
#ifdef POW_PD
if (FUSB302_present) {
//Cant start QC until either PD works or fails
if (PolicyEngine::setupCompleteOrTimedOut() == false) {
return;
}
if (PolicyEngine::pdHasNegotiated()) {
return;
}
}
#endif
#ifdef POW_QC
QC_resync();
#endif
}
uint8_t usb_pd_detect() {
#ifdef POW_PD
FUSB302_present = fusb302_detect();
return FUSB302_present;
#endif
return false;
}
bool getIsPoweredByDCIN() {
//We return false until we are sure we are not using PD
if (PolicyEngine::setupCompleteOrTimedOut() == false) {
return false;
}
if (PolicyEngine::pdHasNegotiated()) {
return false; // We are using PD
}
if (hasQCNegotiated()) {
return false; // We are using QC
}
return true;
}

65
workspace/TS100/Core/BSP/Pine64/QC_GPIO.cpp Normal file
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/*
* QC.c
*
* Created on: 29 May 2020
* Author: Ralim
*/
#include "BSP.h"
#include "Pins.h"
#include "QC3.h"
#include "Settings.h"
#include "gd32vf103.h"
#ifdef POW_QC
void QC_DPlusZero_Six() {
// pull down D+
gpio_bit_reset(QC_DP_LOW_GPIO_Port, QC_DP_LOW_Pin);
}
void QC_DNegZero_Six() {
gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin);
gpio_bit_reset(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin);
}
void QC_DPlusThree_Three() {
// pull up D+
gpio_bit_set(QC_DP_LOW_GPIO_Port, QC_DP_LOW_Pin);
}
void QC_DNegThree_Three() {
gpio_bit_set(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin);
gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin);
}
void QC_DM_PullDown() {
gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, USB_DM_Pin);
}
void QC_DM_No_PullDown() {
gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_2MHZ, USB_DM_Pin);
}
void QC_Init_GPIO() {
// Setup any GPIO into the right states for QC
//D+ pulldown as output
gpio_init(QC_DP_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DP_LOW_Pin);
//Make two D- pins floating
QC_DM_PullDown();
}
void QC_Post_Probe_En() {
//Make two D- pins outputs
gpio_init(QC_DM_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_LOW_Pin);
gpio_init(QC_DM_HIGH_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_HIGH_Pin);
}
uint8_t QC_DM_PulledDown() {
return gpio_input_bit_get(USB_DM_LOW_GPIO_Port, USB_DM_Pin) == RESET ? 1 : 0;
}
#endif
void QC_resync() {
#ifdef POW_QC
uint8_t targetvoltage = 90;
if (systemSettings.QCIdealVoltage == 1) {
targetvoltage = 120;
} else if (systemSettings.QCIdealVoltage == 2) {
targetvoltage = 200;
}
seekQC(targetvoltage, systemSettings.voltageDiv); // Run the QC seek again if we have drifted too much
#endif
}

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workspace/TS100/Core/BSP/Pine64/README.md Normal file
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# BSP section for STM32F103 based Miniware products
This folder contains the hardware abstractions required for the TS100, TS80 and probably TS80P soldering irons.
## Main abstractions
* Hardware Init
* -> Should contain all bootstrap to bring the hardware up to an operating point
* -> Two functions are required, a pre and post FreeRToS call
* I2C read/write
* Set PWM for the tip
* Links between IRQ's on the system and the calls in the rest of the firmware

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/*
* Setup.c
*
* Created on: 29Aug.,2017
* Author: Ben V. Brown
*/
#include "Setup.h"
#include "BSP.h"
#include "Pins.h"
#include "gd32vf103.h"
#include "systick.h"
#include <string.h>
#define ADC_NORM_CHANNELS 2
#define ADC_NORM_SAMPLES 32
uint16_t ADCReadings[ADC_NORM_SAMPLES *
ADC_NORM_CHANNELS]; // room for 32 lots of the pair of readings
// Functions
void setup_gpio();
void setup_dma();
void setup_i2c();
void setup_adc();
void setup_timers();
void setup_iwdg();
void hardware_init() {
// GPIO
setup_gpio();
// DMA
setup_dma();
// I2C
setup_i2c();
// ADC's
setup_adc();
// Timers
setup_timers();
// Watchdog
setup_iwdg();
/* enable TIMER1 - PWM control timing*/
timer_enable(TIMER1);
timer_enable(TIMER2);
eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL4_PRIO0);
eclic_global_interrupt_enable();
}
// channel 0 -> temperature sensor, 1-> VIN
uint16_t getADC(uint8_t channel) {
uint32_t sum = 0;
for (uint8_t i = 0; i < ADC_NORM_SAMPLES; i++)
sum += ADCReadings[channel + (i * ADC_NORM_CHANNELS)];
return sum >> 2;
}
void setup_gpio() {
/* enable GPIOB clock */
rcu_periph_clock_enable(RCU_GPIOA);
/* enable GPIOB clock */
rcu_periph_clock_enable(RCU_GPIOB);
// Alternate function clock enable
rcu_periph_clock_enable(RCU_AF);
// Buttons as input
gpio_init(KEY_A_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_A_Pin);
gpio_init(KEY_B_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_B_Pin);
// OLED reset as output
gpio_init(OLED_RESET_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ,
OLED_RESET_Pin);
// I2C as AF Open Drain
gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ,
SDA_Pin | SCL_Pin);
// PWM output as AF Push Pull
gpio_init(PWM_Out_GPIO_Port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, PWM_Out_Pin);
// Analog Inputs ... as analog inputs
gpio_init(TMP36_INPUT_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ,
TMP36_INPUT_Pin);
gpio_init(TIP_TEMP_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, TIP_TEMP_Pin);
gpio_init(VIN_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, VIN_Pin);
// Remap PB4 away from JTAG NJRST
gpio_pin_remap_config(GPIO_SWJ_NONJTRST_REMAP, ENABLE);
// TODO - rest of pins as floating
}
void setup_dma() {
// Setup DMA for ADC0
{
/* enable DMA0 clock */
rcu_periph_clock_enable(RCU_DMA0);
rcu_periph_clock_enable(RCU_DMA1);
/* ADC_DMA_channel configuration */
dma_parameter_struct dma_data_parameter;
/* ADC DMA_channel configuration */
dma_deinit(DMA0, DMA_CH0);
/* initialize DMA data mode */
dma_data_parameter.periph_addr = (uint32_t) (&ADC_RDATA(ADC0));
dma_data_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_data_parameter.memory_addr = (uint32_t) (ADCReadings);
dma_data_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_data_parameter.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
dma_data_parameter.memory_width = DMA_MEMORY_WIDTH_16BIT;
dma_data_parameter.direction = DMA_PERIPHERAL_TO_MEMORY;
dma_data_parameter.number = ADC_NORM_SAMPLES * ADC_NORM_CHANNELS;
dma_data_parameter.priority = DMA_PRIORITY_HIGH;
dma_init(DMA0, DMA_CH0, &dma_data_parameter);
dma_circulation_enable(DMA0, DMA_CH0);
/* enable DMA channel */
dma_channel_enable(DMA0, DMA_CH0);
}
}
void setup_i2c() {
/* enable I2C0 clock */
rcu_periph_clock_enable(RCU_I2C0);
// Setup I20 at 400kHz
i2c_clock_config(I2C0, 400 * 1000, I2C_DTCY_16_9);
i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, 0x00);
i2c_enable(I2C0);
/* enable acknowledge */
i2c_ack_config(I2C0, I2C_ACK_ENABLE);
eclic_irq_enable(I2C0_EV_IRQn, 1, 0);
eclic_irq_enable(I2C0_ER_IRQn, 2, 0);
}
void setup_adc() {
// Setup ADC in normal + injected mode
// Want it to sample handle temp and input voltage normally via dma
// Then injected trigger to sample tip temp
memset(ADCReadings, 0, sizeof(ADCReadings));
rcu_periph_clock_enable(RCU_ADC0);
rcu_periph_clock_enable(RCU_ADC1);
adc_deinit(ADC0);
adc_deinit(ADC1);
/* config ADC clock */
rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV16);
// Run in normal parallel + inserted parallel
adc_mode_config(ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL);
adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE);
adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE);
adc_special_function_config(ADC1, ADC_CONTINUOUS_MODE, ENABLE);
adc_special_function_config(ADC1, ADC_SCAN_MODE, ENABLE);
// Align right
adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT);
adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT);
// Setup reading 2 channels on regular mode (Handle Temp + dc in)
adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, ADC_NORM_CHANNELS);
adc_channel_length_config(ADC1, ADC_REGULAR_CHANNEL, ADC_NORM_CHANNELS);
// Setup the two channels
adc_regular_channel_config(ADC0, 0, TMP36_ADC0_CHANNEL,
ADC_SAMPLETIME_71POINT5); // temp sensor
adc_regular_channel_config(ADC1, 0, TMP36_ADC1_CHANNEL,
ADC_SAMPLETIME_71POINT5); // temp sensor
adc_regular_channel_config(ADC0, 1, VIN_ADC0_CHANNEL,
ADC_SAMPLETIME_71POINT5); // DC Input voltage
adc_regular_channel_config(ADC1, 1, VIN_ADC1_CHANNEL,
ADC_SAMPLETIME_71POINT5); // DC Input voltage
// Setup that we want all 4 inserted readings to be the tip temp
adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 4);
adc_channel_length_config(ADC1, ADC_INSERTED_CHANNEL, 4);
for (int rank = 0; rank < 4; rank++) {
adc_inserted_channel_config(ADC0, rank, TIP_TEMP_ADC0_CHANNEL,
ADC_SAMPLETIME_1POINT5);
adc_inserted_channel_config(ADC1, rank, TIP_TEMP_ADC1_CHANNEL,
ADC_SAMPLETIME_1POINT5);
}
// Setup timer 1 channel 0 to trigger injected measurements
adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL,
ADC0_1_EXTTRIG_INSERTED_T1_CH0);
adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL,
ADC0_1_EXTTRIG_INSERTED_T1_CH0);
adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL,
ADC0_1_EXTTRIG_REGULAR_NONE);
adc_external_trigger_source_config(ADC1, ADC_REGULAR_CHANNEL,
ADC0_1_EXTTRIG_REGULAR_NONE);
// Enable triggers for the ADC
adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE);
adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ENABLE);
adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE);
adc_external_trigger_config(ADC1, ADC_REGULAR_CHANNEL, ENABLE);
adc_watchdog_disable(ADC0);
adc_watchdog_disable(ADC1);
adc_resolution_config(ADC0, ADC_RESOLUTION_12B);
adc_resolution_config(ADC1, ADC_RESOLUTION_12B);
/* clear the ADC flag */
adc_oversample_mode_disable(ADC0);
adc_oversample_mode_disable(ADC1);
adc_enable(ADC0);
adc_calibration_enable(ADC0);
adc_enable(ADC1);
adc_calibration_enable(ADC1);
adc_dma_mode_enable(ADC0);
// Enable interrupt on end of injected readings
adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOC);
adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC);
adc_interrupt_enable(ADC0, ADC_INT_EOIC);
eclic_irq_enable(ADC0_1_IRQn, 2, 0);
adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL);
adc_software_trigger_enable(ADC1, ADC_REGULAR_CHANNEL);
adc_tempsensor_vrefint_disable();
}
void setup_timers() {
// Setup timer 1 to run the actual PWM level
/* enable timer1 clock */
rcu_periph_clock_enable(RCU_TIMER1);
rcu_periph_clock_enable(RCU_TIMER2);
timer_oc_parameter_struct timer_ocintpara;
timer_parameter_struct timer_initpara;
{
// deinit to reset the timer
timer_deinit(TIMER1);
/* initialize TIMER init parameter struct */
timer_struct_para_init(&timer_initpara);
/* TIMER1 configuration */
timer_initpara.prescaler = 24000;
timer_initpara.alignedmode = TIMER_COUNTER_EDGE;
timer_initpara.counterdirection = TIMER_COUNTER_UP;
timer_initpara.period = powerPWM + tempMeasureTicks;
timer_initpara.clockdivision = TIMER_CKDIV_DIV4;
timer_initpara.repetitioncounter = 0;
timer_init(TIMER1, &timer_initpara);
/* CH0 configured to implement the PWM irq's for the output control*/
timer_channel_output_struct_para_init(&timer_ocintpara);
timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocintpara);
timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, powerPWM + holdoffTicks);
timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_PWM1);
timer_channel_output_shadow_config(TIMER1, TIMER_CH_0,
TIMER_OC_SHADOW_DISABLE);
/* CH1 used for irq */
timer_channel_output_struct_para_init(&timer_ocintpara);
timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocintpara);
timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 0);
timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_PWM0);
timer_channel_output_shadow_config(TIMER1, TIMER_CH_1,
TIMER_OC_SHADOW_DISABLE);
// IRQ
timer_interrupt_enable(TIMER1, TIMER_INT_UP);
timer_interrupt_enable(TIMER1, TIMER_INT_CH1);
}
eclic_irq_enable(TIMER1_IRQn, 2, 5);
// Setup timer 2 to control the output signal
{
timer_deinit(TIMER2);
/* initialize TIMER init parameter struct */
timer_struct_para_init(&timer_initpara);
/* TIMER1 configuration */
timer_initpara.prescaler = 200;
timer_initpara.alignedmode = TIMER_COUNTER_EDGE;
timer_initpara.counterdirection = TIMER_COUNTER_UP;
timer_initpara.period = 100;
timer_initpara.clockdivision = TIMER_CKDIV_DIV4;
timer_initpara.repetitioncounter = 0;
timer_init(TIMER2, &timer_initpara);
/* CH0 configuration in PWM mode0 */
timer_channel_output_struct_para_init(&timer_ocintpara);
timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE;
timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH;
timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW;
timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
timer_channel_output_config(TIMER2, TIMER_CH_0, &timer_ocintpara);
timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0);
timer_channel_output_mode_config(TIMER2, TIMER_CH_0, TIMER_OC_MODE_PWM0);
timer_channel_output_shadow_config(TIMER2, TIMER_CH_0,
TIMER_OC_SHADOW_DISABLE);
timer_auto_reload_shadow_enable(TIMER2);
timer_enable(TIMER2);
}
}
void setup_iwdg() {
fwdgt_config(0x0FFF, FWDGT_PSC_DIV256);
fwdgt_enable();
}
void setupFUSBIRQ() {
// Setup IRQ for USB-PD
gpio_init(FUSB302_IRQ_GPIO_Port, GPIO_MODE_IPU, GPIO_OSPEED_2MHZ,
FUSB302_IRQ_Pin);
eclic_irq_enable(EXTI5_9_IRQn, 1, 1);
/* connect key EXTI line to key GPIO pin */
gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOB, GPIO_PIN_SOURCE_5);
/* configure key EXTI line */
exti_init(EXTI_5, EXTI_INTERRUPT, EXTI_TRIG_FALLING);
exti_interrupt_flag_clear(EXTI_5);
}

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/*
* Setup.h
*
* Created on: 29Aug.,2017
* Author: Ben V. Brown
*/
#ifndef SETUP_H_
#define SETUP_H_
#include "Vendor/Lib/gd32vf103_libopt.h"
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
uint16_t getADC(uint8_t channel);
void hardware_init();
void setupFUSBIRQ();
#ifdef __cplusplus
}
#endif
extern const uint8_t holdoffTicks;
extern const uint8_t tempMeasureTicks;
#endif /* SETUP_H_ */

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/*
* UnitSettings.h
*
* Created on: 29 May 2020
* Author: Ralim
*/
#ifndef BSP_MINIWARE_UNITSETTINGS_H_
#define BSP_MINIWARE_UNITSETTINGS_H_
#endif /* BSP_MINIWARE_UNITSETTINGS_H_ */

13
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/* See LICENSE of license details. */
#include <errno.h>
#include <time.h>
#include <stdint.h>
#include "system_gd32vf103.h"
/* Get resolution of clock. */
int clock_getres(clockid_t clock_id, struct timespec *res)
{
res->tv_sec = 0;
res->tv_nsec = 1000000000 / SystemCoreClock;
return 0;
}

20
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/clock_gettime.c vendored Normal file
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/* See LICENSE of license details. */
#include <errno.h>
#include <time.h>
#include <sys/time.h>
extern int _gettimeofday(struct timeval *tp, void *tzp);
/* Get current value of CLOCK and store it in tp. */
int clock_gettime(clockid_t clock_id, struct timespec *tp)
{
struct timeval tv;
int retval = -1;
retval = _gettimeofday(&tv, NULL);
if (retval == 0) {
TIMEVAL_TO_TIMESPEC(&tv, tp);
}
return retval;
}

9
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/clock_settime.c vendored Normal file
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@@ -0,0 +1,9 @@
/* See LICENSE of license details. */
#include <errno.h>
#include <time.h>
/* Set CLOCK to value TP. */
int clock_settime(clockid_t clock_id, const struct timespec *tp)
{
return -1;
}

11
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/close.c vendored Normal file
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@@ -0,0 +1,11 @@
/* See LICENSE of license details. */
#include <errno.h>
#undef errno
extern int errno;
int _close(int fd)
{
errno = EBADF;
return -1;
}

11
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/execve.c vendored Normal file
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@@ -0,0 +1,11 @@
/* See LICENSE of license details. */
#include <errno.h>
#undef errno
extern int errno;
int _execve(char *name, char **argv, char **env)
{
errno = ENOMEM;
return -1;
}

9
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/exit.c vendored Normal file
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@@ -0,0 +1,9 @@
/* See LICENSE of license details. */
#include "n200_func.h"
void _exit(int fd)
{
while(1) {
__WFI();
}
}

11
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@@ -0,0 +1,11 @@
/* See LICENSE of license details. */
#include <errno.h>
#undef errno
extern int errno;
int fork(void)
{
errno = EAGAIN;
return -1;
}

18
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/fstat.c vendored Normal file
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@@ -0,0 +1,18 @@
/* See LICENSE of license details. */
#include <errno.h>
#include <sys/stat.h>
#include <unistd.h>
#undef errno
extern int errno;
int _fstat(int file, struct stat *st)
{
if ((STDOUT_FILENO == file) || (STDERR_FILENO == file)) {
st->st_mode = S_IFCHR;
return 0;
} else {
errno = EBADF;
return -1;
}
}

7
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/getpid.c vendored Normal file
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/* See LICENSE of license details. */
#include <errno.h>
int getpid(void)
{
return 1;
}

14
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/* See LICENSE of license details. */
#include <errno.h>
#include <sys/time.h>
#include "system_gd32vf103.h"
int _gettimeofday(struct timeval *tp, void *tzp)
{
uint64_t cycles;
cycles = __get_rv_cycle();
tp->tv_sec = cycles / SystemCoreClock;
tp->tv_usec = (cycles % SystemCoreClock) * 1000000 / SystemCoreClock;
return 0;
}

7
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/* See LICENSE of license details. */
#include <unistd.h>
int _isatty(int fd)
{
return 1;
}

10
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/* See LICENSE of license details. */
#include <errno.h>
#undef errno
extern int errno;
int _kill(int pid, int sig)
{
errno = EINVAL;
return -1;
}

11
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/link.c vendored Normal file
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/* See LICENSE of license details. */
#include <errno.h>
#undef errno
extern int errno;
int _link(char *old, char *new)
{
errno = EMLINK;
return -1;
}

10
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/lseek.c vendored Normal file
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@@ -0,0 +1,10 @@
/* See LICENSE of license details. */
#include <errno.h>
#undef errno
extern int errno;
int _lseek(int file, int offset, int whence)
{
return 0;
}

11
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/open.c vendored Normal file
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@@ -0,0 +1,11 @@
/* See LICENSE of license details. */
#include <errno.h>
#undef errno
extern int errno;
int _open(const char *name, int flags, int mode)
{
errno = ENOSYS;
return -1;
}

10
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/read.c vendored Normal file
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@@ -0,0 +1,10 @@
/* See LICENSE of license details. */
#include <stdint.h>
#include <errno.h>
#include <unistd.h>
#include <sys/types.h>
ssize_t _read(int fd, void* ptr, size_t len) {
return -1;
}

9
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/sbrk.c vendored Normal file
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@@ -0,0 +1,9 @@
/* See LICENSE of license details. */
#include <stdint.h>
#include <stddef.h>
#include <unistd.h>
void *_sbrk(ptrdiff_t incr)
{
return (void *)0;
}

8
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/stat.c vendored Normal file
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@@ -0,0 +1,8 @@
/* See LICENSE of license details. */
#include <sys/stat.h>
int _stat(char *file, struct stat *st)
{
st->st_mode = S_IFCHR;
return 0;
}

26
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/times.c vendored Normal file
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/* See LICENSE of license details. */
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
extern int _gettimeofday(struct timeval *, void *);
clock_t _times(struct tms *buf)
{
static struct timeval t0;
struct timeval t;
long long utime;
/* When called for the first time, initialize t0. */
if (t0.tv_sec == 0 && t0.tv_usec == 0) {
_gettimeofday(&t0, 0);
}
_gettimeofday(&t, 0);
utime = (t.tv_sec - t0.tv_sec) * 1000000 + (t.tv_usec - t0.tv_usec);
buf->tms_utime = utime * CLOCKS_PER_SEC / 1000000;
buf->tms_stime = buf->tms_cstime = buf->tms_cutime = 0;
return buf->tms_utime;
}

11
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/unlink.c vendored Normal file
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@@ -0,0 +1,11 @@
/* See LICENSE of license details. */
#include <errno.h>
#undef errno
extern int errno;
int _unlink(const char *name)
{
return -1;
}

12
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/* See LICENSE of license details. */
#include <sys/stat.h>
#include <errno.h>
#undef errno
extern int errno;
int _wait(int *status)
{
errno = ECHILD;
return -1;
}

11
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/Stubs/write.c vendored Normal file
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@@ -0,0 +1,11 @@
/* See LICENSE of license details. */
#include <stdint.h>
#include <errno.h>
#include <unistd.h>
#include <sys/types.h>
ssize_t _write(int fd, const void* ptr, size_t len)
{
return -1;
}

246
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/gd32vf103.h vendored Normal file
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/*!
\file gd32vf103.h
\brief general definitions for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103_H
#define GD32VF103_H
#ifdef cplusplus
extern "C" {
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
#define GD32VF103V_EVAL
/* define value of high speed crystal oscillator (HXTAL) in Hz */
#if !defined HXTAL_VALUE
#ifdef GD32VF103R_START
#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
#define HXTAL_VALUE_8M HXTAL_VALUE
#elif defined(GD32VF103V_EVAL) || defined(GD32VF103C_START) || defined(GD32VF103T_START)
#define HXTAL_VALUE ((uint32_t)8000000) /*!< value of the external oscillator in Hz */
#define HXTAL_VALUE_25M HXTAL_VALUE
#else
#error "Please select the target board type used in your application (in gd32vf103.h file)"
#endif
#endif /* high speed crystal oscillator value */
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
#if !defined(HXTAL_STARTUP_TIMEOUT)
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
#endif /* high speed crystal oscillator startup timeout */
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
#if !defined(IRC8M_VALUE)
#define IRC8M_VALUE ((uint32_t)8000000)
#endif /* internal 8MHz RC oscillator value */
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
#if !defined(IRC8M_STARTUP_TIMEOUT)
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 8MHz RC oscillator startup timeout */
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
#if !defined(IRC40K_VALUE)
#define IRC40K_VALUE ((uint32_t)40000)
#endif /* internal 40KHz RC oscillator value */
/* define value of low speed crystal oscillator (LXTAL)in Hz */
#if !defined(LXTAL_VALUE)
#define LXTAL_VALUE ((uint32_t)32768)
#endif /* low speed crystal oscillator value */
/* define interrupt number */
typedef enum IRQn {
CLIC_INT_RESERVED = 0, /*!< RISC-V reserved */
CLIC_INT_SFT = 3, /*!< Software interrupt */
CLIC_INT_TMR = 7, /*!< CPU Timer interrupt */
CLIC_INT_BWEI = 17, /*!< Bus Error interrupt */
CLIC_INT_PMOVI = 18, /*!< Performance Monitor */
/* interrupt numbers */
WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */
LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */
TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */
RTC_IRQn = 22, /*!< RTC alarm interrupt */
FMC_IRQn = 23, /*!< FMC interrupt */
RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */
EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */
EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */
EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */
EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */
EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */
DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */
DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */
DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */
DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */
DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */
DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */
DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */
ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */
CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */
CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */
CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */
CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */
EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */
TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */
TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */
TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */
TIMER1_IRQn = 47, /*!< TIMER1 interrupt */
TIMER2_IRQn = 48, /*!< TIMER2 interrupt */
TIMER3_IRQn = 49, /*!< TIMER3 interrupts */
I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */
SPI0_IRQn = 54, /*!< SPI0 interrupt */
SPI1_IRQn = 55, /*!< SPI1 interrupt */
USART0_IRQn = 56, /*!< USART0 interrupt */
USART1_IRQn = 57, /*!< USART1 interrupt */
USART2_IRQn = 58, /*!< USART2 interrupt */
EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */
RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */
USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */
EXMC_IRQn = 67, /*!< EXMC global interrupt */
TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */
SPI2_IRQn = 70, /*!< SPI2 global interrupt */
UART3_IRQn = 71, /*!< UART3 global interrupt */
UART4_IRQn = 72, /*!< UART4 global interrupt */
TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */
TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */
DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */
CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */
CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */
CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */
CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */
USBFS_IRQn = 86, /*!< USBFS global interrupt */
ECLIC_NUM_INTERRUPTS
} IRQn_Type;
/* includes */
#include "system_gd32vf103.h"
#include <stdint.h>
/* enum definitions */
typedef enum { DISABLE = 0,
ENABLE = !DISABLE } EventStatus,
ControlStatus;
// typedef enum { FALSE = 0,
// TRUE = !FALSE } bool;
typedef enum { RESET = 0,
SET = 1,
MAX = 0X7FFFFFFF } FlagStatus;
typedef enum { ERROR = 0,
SUCCESS = !ERROR } ErrStatus;
/* bit operations */
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
#define BIT(x) ((uint32_t)((uint32_t)0x01U << (x)))
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval)&BITS((start), (end))) >> (start))
/* main flash and SRAM memory map */
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
/* peripheral memory map */
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
/* advanced peripheral bus 1 memory map */
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
/* advanced peripheral bus 2 memory map */
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
/* advanced high performance bus 1 memory map */
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
/* define marco USE_STDPERIPH_DRIVER */
#if !defined USE_STDPERIPH_DRIVER
#define USE_STDPERIPH_DRIVER
#endif
#ifdef USE_STDPERIPH_DRIVER
#include "gd32vf103_libopt.h"
#endif /* USE_STDPERIPH_DRIVER */
#ifdef cplusplus
}
#endif
#endif

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/*!
\file gd32vf103_adc.c
\brief ADC driver
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32vf103_adc.h"
/* discontinuous mode macro*/
#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U)
/* ADC regular channel macro */
#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U)
#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U)
#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U)
#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U)
/* ADC sampling time macro */
#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U)
#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U)
#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U)
/* ADC inserted channel macro */
#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U)
#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U)
/* ADC inserted channel offset macro */
#define ADC_OFFSET_LENGTH ((uint8_t)3U)
#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U)
/*!
\brief reset ADC
\param[in] adc_periph: ADCx, x=0,1
\param[out] none
\retval none
*/
void adc_deinit(uint32_t adc_periph)
{
switch(adc_periph){
case ADC0:
/* reset ADC0 */
rcu_periph_reset_enable(RCU_ADC0RST);
rcu_periph_reset_disable(RCU_ADC0RST);
break;
case ADC1:
/* reset ADC1 */
rcu_periph_reset_enable(RCU_ADC1RST);
rcu_periph_reset_disable(RCU_ADC1RST);
break;
default:
break;
}
}
/*!
\brief configure the ADC sync mode
\param[in] mode: ADC mode
only one parameter can be selected which is shown as below:
\arg ADC_MODE_FREE: all the ADCs work independently
\arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
\arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
\arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
\arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
\arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
\arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
\arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only
\arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only
\arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only
\param[out] none
\retval none
*/
void adc_mode_config(uint32_t mode)
{
ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM);
ADC_CTL0(ADC0) |= mode;
}
/*!
\brief enable or disable ADC special function
\param[in] adc_periph: ADCx, x=0,1
\param[in] function: the function to config
only one parameter can be selected which is shown as below:
\arg ADC_SCAN_MODE: scan mode select
\arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
\arg ADC_CONTINUOUS_MODE: continuous mode select
\param[in] newvalue: ENABLE or DISABLE
\param[out] none
\retval none
*/
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
{
if(newvalue){
if(0U != (function & ADC_SCAN_MODE)){
/* enable scan mode */
ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
}
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
/* enable inserted channel group convert automatically */
ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
}
if(0U != (function & ADC_CONTINUOUS_MODE)){
/* enable continuous mode */
ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
}
}else{
if(0U != (function & ADC_SCAN_MODE)){
/* disable scan mode */
ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
}
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
/* disable inserted channel group convert automatically */
ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
}
if(0U != (function & ADC_CONTINUOUS_MODE)){
/* disable continuous mode */
ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
}
}
}
/*!
\brief configure ADC data alignment
\param[in] adc_periph: ADCx, x=0,1
\param[in] data_alignment: data alignment select
only one parameter can be selected which is shown as below:
\arg ADC_DATAALIGN_RIGHT: LSB alignment
\arg ADC_DATAALIGN_LEFT: MSB alignment
\param[out] none
\retval none
*/
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
{
if(ADC_DATAALIGN_RIGHT != data_alignment){
/* MSB alignment */
ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
}else{
/* LSB alignment */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
}
}
/*!
\brief enable ADC interface
\param[in] adc_periph: ADCx, x=0,1
\param[out] none
\retval none
*/
void adc_enable(uint32_t adc_periph)
{
if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
/* enable ADC */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
}
}
/*!
\brief disable ADC interface
\param[in] adc_periph: ADCx, x=0,1
\param[out] none
\retval none
*/
void adc_disable(uint32_t adc_periph)
{
/* disable ADC */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
}
/*!
\brief ADC calibration and reset calibration
\param[in] adc_periph: ADCx, x=0,1
\param[out] none
\retval none
*/
void adc_calibration_enable(uint32_t adc_periph)
{
/* reset the selected ADC1 calibration registers */
ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
/* check the RSTCLB bit state */
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
}
/* enable ADC calibration process */
ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
/* check the CLB bit state */
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
}
}
/*!
\brief enable the temperature sensor and Vrefint channel
\param[in] none
\param[out] none
\retval none
*/
void adc_tempsensor_vrefint_enable(void)
{
/* enable the temperature sensor and Vrefint channel */
ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
}
/*!
\brief disable the temperature sensor and Vrefint channel
\param[in] none
\param[out] none
\retval none
*/
void adc_tempsensor_vrefint_disable(void)
{
/* disable the temperature sensor and Vrefint channel */
ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
}
/*!
\brief enable DMA request
\param[in] adc_periph: ADCx, x=0,1
\param[out] none
\retval none
*/
void adc_dma_mode_enable(uint32_t adc_periph)
{
/* enable DMA request */
ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
}
/*!
\brief disable DMA request
\param[in] adc_periph: ADCx, x=0,1
\param[out] none
\retval none
*/
void adc_dma_mode_disable(uint32_t adc_periph)
{
/* disable DMA request */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
}
/*!
\brief configure ADC discontinuous mode
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_channel_group: select the channel group
only one parameter can be selected which is shown as below:
\arg ADC_REGULAR_CHANNEL: regular channel group
\arg ADC_INSERTED_CHANNEL: inserted channel group
\arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel
\param[in] length: number of conversions in discontinuous mode,the number can be 1..8
for regular channel, the number has no effect for inserted channel
\param[out] none
\retval none
*/
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
{
/* disable discontinuous mode of regular & inserted channel */
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
switch(adc_channel_group){
case ADC_REGULAR_CHANNEL:
/* config the number of conversions in discontinuous mode */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
/* enable regular channel group discontinuous mode */
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
break;
case ADC_INSERTED_CHANNEL:
/* enable inserted channel group discontinuous mode */
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
break;
case ADC_CHANNEL_DISCON_DISABLE:
/* disable discontinuous mode of regular & inserted channel */
default:
break;
}
}
/*!
\brief configure the length of regular channel group or inserted channel group
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_channel_group: select the channel group
only one parameter can be selected which is shown as below:
\arg ADC_REGULAR_CHANNEL: regular channel group
\arg ADC_INSERTED_CHANNEL: inserted channel group
\param[in] length: the length of the channel
regular channel 1-16
inserted channel 1-4
\param[out] none
\retval none
*/
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
{
switch(adc_channel_group){
case ADC_REGULAR_CHANNEL:
/* configure the length of regular channel group */
ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
break;
case ADC_INSERTED_CHANNEL:
/* configure the length of inserted channel group */
ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
break;
default:
break;
}
}
/*!
\brief configure ADC regular channel
\param[in] adc_periph: ADCx, x=0,1
\param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15
\param[in] adc_channel: the selected ADC channel
only one parameter can be selected which is shown as below:
\arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
\param[in] sample_time: the sample time value
only one parameter can be selected which is shown as below:
\arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
\arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
\arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
\arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
\arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
\arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
\arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
\arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
\param[out] none
\retval none
*/
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
{
uint32_t rsq,sampt;
/* ADC regular sequence config */
if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){
/* the regular group sequence rank is smaller than six */
rsq = ADC_RSQ2(adc_periph);
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)));
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank));
ADC_RSQ2(adc_periph) = rsq;
}else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){
/* the regular group sequence rank is smaller than twelve */
rsq = ADC_RSQ1(adc_periph);
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))));
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)));
ADC_RSQ1(adc_periph) = rsq;
}else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){
/* the regular group sequence rank is smaller than sixteen */
rsq = ADC_RSQ0(adc_periph);
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))));
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)));
ADC_RSQ0(adc_periph) = rsq;
}else{
}
/* ADC sampling time config */
if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
/* the regular group sequence rank is smaller than ten */
sampt = ADC_SAMPT1(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
/* channel sample time set*/
sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel));
ADC_SAMPT1(adc_periph) = sampt;
}else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
/* the regular group sequence rank is smaller than eighteen */
sampt = ADC_SAMPT0(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
/* channel sample time set*/
sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
ADC_SAMPT0(adc_periph) = sampt;
}else{
}
}
/*!
\brief configure ADC inserted channel
\param[in] adc_periph: ADCx, x=0,1
\param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
\param[in] adc_channel: the selected ADC channel
only one parameter can be selected which is shown as below:
\arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
\param[in] sample_time: The sample time value
only one parameter can be selected which is shown as below:
\arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
\arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
\arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
\arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
\arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
\arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
\arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
\arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
\param[out] none
\retval none
*/
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
{
uint8_t inserted_length;
uint32_t isq,sampt;
/* get inserted channel group length */
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
/* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */
isq = ADC_ISQ(adc_periph);
isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)));
isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH));
ADC_ISQ(adc_periph) = isq;
/* ADC sampling time config */
if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
/* the inserted group sequence rank is smaller than ten */
sampt = ADC_SAMPT1(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
/* channel sample time set*/
sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel);
ADC_SAMPT1(adc_periph) = sampt;
}else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
/* the inserted group sequence rank is smaller than eighteen */
sampt = ADC_SAMPT0(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
/* channel sample time set*/
sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
ADC_SAMPT0(adc_periph) = sampt;
}else{
}
}
/*!
\brief configure ADC inserted channel offset
\param[in] adc_periph: ADCx, x=0,1
\param[in] inserted_channel: insert channel select
only one parameter can be selected
\arg ADC_INSERTED_CHANNEL_0: inserted channel0
\arg ADC_INSERTED_CHANNEL_1: inserted channel1
\arg ADC_INSERTED_CHANNEL_2: inserted channel2
\arg ADC_INSERTED_CHANNEL_3: inserted channel3
\param[in] offset: the offset data
\param[out] none
\retval none
*/
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
{
uint8_t inserted_length;
uint32_t num = 0U;
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
if(num <= ADC_OFFSET_LENGTH){
/* calculate the offset of the register */
num = num * ADC_OFFSET_SHIFT_LENGTH;
/* config the offset of the selected channels */
REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
}
}
/*!
\brief configure ADC external trigger source
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_channel_group: select the channel group
only one parameter can be selected which is shown as below:
\arg ADC_REGULAR_CHANNEL: regular channel group
\arg ADC_INSERTED_CHANNEL: inserted channel group
\param[in] external_trigger_source: regular or inserted group trigger source
only one parameter can be selected
for regular channel:
\arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select
\arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select
\arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select
\arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select
\arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select
\arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select
\arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11
\arg ADC0_1_EXTTRIG_REGULAR_NONE: software trigger
for inserted channel:
\arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select
\arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select
\arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select
\arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select
\arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select
\arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select
\arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15
\arg ADC0_1_EXTTRIG_INSERTED_NONE: software trigger
\param[out] none
\retval none
*/
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
{
switch(adc_channel_group){
case ADC_REGULAR_CHANNEL:
/* configure ADC regular group external trigger source */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
break;
case ADC_INSERTED_CHANNEL:
/* configure ADC inserted group external trigger source */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
break;
default:
break;
}
}
/*!
\brief configure ADC external trigger
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_channel_group: select the channel group
one or more parameters can be selected which are shown as below:
\arg ADC_REGULAR_CHANNEL: regular channel group
\arg ADC_INSERTED_CHANNEL: inserted channel group
\param[in] newvalue: ENABLE or DISABLE
\param[out] none
\retval none
*/
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
{
if(newvalue){
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
/* enable ADC regular channel group external trigger */
ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
}
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
/* enable ADC inserted channel group external trigger */
ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
}
}else{
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
/* disable ADC regular channel group external trigger */
ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
}
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
/* disable ADC regular channel group external trigger */
ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
}
}
}
/*!
\brief enable ADC software trigger
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_channel_group: select the channel group
one or more parameters can be selected which are shown as below:
\arg ADC_REGULAR_CHANNEL: regular channel group
\arg ADC_INSERTED_CHANNEL: inserted channel group
\param[out] none
\retval none
*/
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
{
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
/* enable ADC regular channel group software trigger */
ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
}
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
/* enable ADC inserted channel group software trigger */
ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
}
}
/*!
\brief read ADC regular group data register
\param[in] adc_periph: ADCx, x=0,1
\param[in] none
\param[out] none
\retval the conversion value
*/
uint16_t adc_regular_data_read(uint32_t adc_periph)
{
return (uint16_t)(ADC_RDATA(adc_periph));
}
/*!
\brief read ADC inserted group data register
\param[in] adc_periph: ADCx, x=0,1
\param[in] inserted_channel: insert channel select
only one parameter can be selected
\arg ADC_INSERTED_CHANNEL_0: inserted Channel0
\arg ADC_INSERTED_CHANNEL_1: inserted channel1
\arg ADC_INSERTED_CHANNEL_2: inserted Channel2
\arg ADC_INSERTED_CHANNEL_3: inserted Channel3
\param[out] none
\retval the conversion value
*/
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
{
uint32_t idata;
/* read the data of the selected channel */
switch(inserted_channel){
case ADC_INSERTED_CHANNEL_0:
/* read the data of channel 0 */
idata = ADC_IDATA0(adc_periph);
break;
case ADC_INSERTED_CHANNEL_1:
/* read the data of channel 1 */
idata = ADC_IDATA1(adc_periph);
break;
case ADC_INSERTED_CHANNEL_2:
/* read the data of channel 2 */
idata = ADC_IDATA2(adc_periph);
break;
case ADC_INSERTED_CHANNEL_3:
/* read the data of channel 3 */
idata = ADC_IDATA3(adc_periph);
break;
default:
idata = 0U;
break;
}
return (uint16_t)idata& 0xFFFF;
}
/*!
\brief read the last ADC0 and ADC1 conversion result data in sync mode
\param[in] none
\param[out] none
\retval the conversion value
*/
uint32_t adc_sync_mode_convert_value_read(void)
{
/* return conversion value */
return ADC_RDATA(ADC0);
}
/*!
\brief configure ADC analog watchdog single channel
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_channel: the selected ADC channel
only one parameter can be selected which is shown as below:
\arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0)
\param[out] none
\retval none
*/
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
{
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
/* analog watchdog channel select */
ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
}
/*!
\brief configure ADC analog watchdog group channel
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_channel_group: the channel group use analog watchdog
only one parameter can be selected which is shown as below:
\arg ADC_REGULAR_CHANNEL: regular channel group
\arg ADC_INSERTED_CHANNEL: inserted channel group
\arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
\param[out] none
\retval none
*/
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
{
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
/* select the group */
switch(adc_channel_group){
case ADC_REGULAR_CHANNEL:
/* regular channel analog watchdog enable */
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
break;
case ADC_INSERTED_CHANNEL:
/* inserted channel analog watchdog enable */
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
break;
case ADC_REGULAR_INSERTED_CHANNEL:
/* regular and inserted channel analog watchdog enable */
ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
break;
default:
break;
}
}
/*!
\brief disable ADC analog watchdog
\param[in] adc_periph: ADCx, x=0,1
\param[out] none
\retval none
*/
void adc_watchdog_disable(uint32_t adc_periph)
{
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
}
/*!
\brief configure ADC analog watchdog threshold
\param[in] adc_periph: ADCx, x=0,1
\param[in] low_threshold: analog watchdog low threshold, 0..4095
\param[in] high_threshold: analog watchdog high threshold, 0..4095
\param[out] none
\retval none
*/
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
{
ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
}
/*!
\brief get the ADC flag bits
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_flag: the adc flag bits
only one parameter can be selected which is shown as below:
\arg ADC_FLAG_WDE: analog watchdog event flag
\arg ADC_FLAG_EOC: end of group conversion flag
\arg ADC_FLAG_EOIC: end of inserted group conversion flag
\arg ADC_FLAG_STIC: start flag of inserted channel group
\arg ADC_FLAG_STRC: start flag of regular channel group
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag)
{
FlagStatus reval = RESET;
if(ADC_STAT(adc_periph) & adc_flag){
reval = SET;
}
return reval;
}
/*!
\brief clear the ADC flag bits
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_flag: the adc flag bits
one or more parameters can be selected which are shown as below:
\arg ADC_FLAG_WDE: analog watchdog event flag
\arg ADC_FLAG_EOC: end of group conversion flag
\arg ADC_FLAG_EOIC: end of inserted group conversion flag
\arg ADC_FLAG_STIC: start flag of inserted channel group
\arg ADC_FLAG_STRC: start flag of regular channel group
\param[out] none
\retval none
*/
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag)
{
ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
}
/*!
\brief get the bit state of ADCx software start conversion
\param[in] adc_periph: ADCx, x=0,1
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
{
FlagStatus reval = RESET;
if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){
reval = SET;
}
return reval;
}
/*!
\brief get the bit state of ADCx software inserted channel start conversion
\param[in] adc_periph: ADCx, x=0,1
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
{
FlagStatus reval = RESET;
if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){
reval = SET;
}
return reval;
}
/*!
\brief get the ADC interrupt bits
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_interrupt: the adc interrupt bits
only one parameter can be selected which is shown as below:
\arg ADC_INT_FLAG_WDE: analog watchdog interrupt
\arg ADC_INT_FLAG_EOC: end of group conversion interrupt
\arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt)
{
FlagStatus interrupt_flag = RESET;
uint32_t state;
/* check the interrupt bits */
switch(adc_interrupt){
case ADC_INT_FLAG_WDE:
/* get the ADC analog watchdog interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
interrupt_flag = SET;
}
break;
case ADC_INT_FLAG_EOC:
/* get the ADC end of group conversion interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
interrupt_flag = SET;
}
break;
case ADC_INT_FLAG_EOIC:
/* get the ADC end of inserted group conversion interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
interrupt_flag = SET;
}
break;
default:
break;
}
return interrupt_flag;
}
/*!
\brief clear the ADC flag
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_interrupt: the adc status flag
one or more parameters can be selected which are shown as below:
\arg ADC_INT_FLAG_WDE: analog watchdog interrupt
\arg ADC_INT_FLAG_EOC: end of group conversion interrupt
\arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
\param[out] none
\retval none
*/
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt)
{
ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
}
/*!
\brief enable ADC interrupt
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_interrupt: the adc interrupt
one or more parameters can be selected which are shown as below:
\arg ADC_INT_WDE: analog watchdog interrupt flag
\arg ADC_INT_EOC: end of group conversion interrupt flag
\arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
\param[out] none
\retval none
*/
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt)
{
/* enable ADC analog watchdog interrupt */
if(0U != (adc_interrupt & ADC_INT_WDE)){
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
}
/* enable ADC end of group conversion interrupt */
if(0U != (adc_interrupt & ADC_INT_EOC)){
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
}
/* enable ADC end of inserted group conversion interrupt */
if(0U != (adc_interrupt & ADC_INT_EOIC)){
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
}
}
/*!
\brief disable ADC interrupt
\param[in] adc_periph: ADCx, x=0,1
\param[in] adc_interrupt: the adc interrupt flag
one or more parameters can be selected which are shown as below:
\arg ADC_INT_WDE: analog watchdog interrupt flag
\arg ADC_INT_EOC: end of group conversion interrupt flag
\arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
\param[out] none
\retval none
*/
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
{
/* disable ADC analog watchdog interrupt */
if(0U != (adc_interrupt & ADC_INT_WDE)){
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
}
/* disable ADC end of group conversion interrupt */
if(0U != (adc_interrupt & ADC_INT_EOC)){
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
}
/* disable ADC end of inserted group conversion interrupt */
if(0U != (adc_interrupt & ADC_INT_EOIC)){
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
}
}
/*!
\brief adc resolution config
\param[in] adc_periph: ADCx, x=0,1
\param[in] resolution: ADC resolution
only one parameter can be selected which is shown as below:
\arg ADC_RESOLUTION_12B: 12-bit ADC resolution
\arg ADC_RESOLUTION_10B: 10-bit ADC resolution
\arg ADC_RESOLUTION_8B: 8-bit ADC resolution
\arg ADC_RESOLUTION_6B: 6-bit ADC resolution
\param[out] none
\retval none
*/
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
{
ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_DRES);
ADC_OVSCR(adc_periph) |= (uint32_t)resolution;
}
/*!
\brief adc oversample mode config
\param[in] adc_periph: ADCx, x=0,1
\param[in] mode: ADC oversampling mode
only one parameter can be selected which is shown as below:
\arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel
are done consecutively after a trigger
\arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel
needs a trigger
\param[in] shift: ADC oversampling shift
only one parameter can be selected which is shown as below:
\arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
\arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
\arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
\arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
\arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
\arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
\arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
\arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
\arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
\param[in] ratio: ADC oversampling ratio
only one parameter can be selected which is shown as below:
\arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio X2
\arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio X4
\arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio X8
\arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio X16
\arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio X32
\arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio X64
\arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio X128
\arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio X256
\param[out] none
\retval none
*/
void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift,uint8_t ratio)
{
if(mode){
ADC_OVSCR(adc_periph) |= (uint32_t)ADC_OVSCR_TOVS;
}else{
ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_TOVS);
}
/* config the shift and ratio */
ADC_OVSCR(adc_periph) &= ~((uint32_t)(ADC_OVSCR_OVSR | ADC_OVSCR_OVSS));
ADC_OVSCR(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio);
}
/*!
\brief enable ADC oversample mode
\param[in] adc_periph: ADCx, x=0,1
\param[out] none
\retval none
*/
void adc_oversample_mode_enable(uint32_t adc_periph)
{
ADC_OVSCR(adc_periph) |= ADC_OVSCR_OVSEN;
}
/*!
\brief disable ADC oversample mode
\param[in] adc_periph: ADCx, x=0,1
\param[out] none
\retval none
*/
void adc_oversample_mode_disable(uint32_t adc_periph)
{
ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_OVSEN);
}

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/*!
\file gd32vf103_adc.h
\brief definitions for the ADC
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef GD32VF103_ADC_H
#define GD32VF103_ADC_H
#include "gd32vf103.h"
/* ADC definitions */
#define ADC0 ADC_BASE
#define ADC1 (ADC_BASE + 0x400U)
/* registers definitions */
#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */
#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */
#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */
#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */
#define ADC_OVSCR(adcx) REG32((adcx) + 0x80U) /*!< ADC oversample control register */
/* bits definitions */
/* ADC_STAT */
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
/* ADC_CTL0 */
#define ADC_CTL0_WDCHSEL BITS(0, 4) /*!< analog watchdog channel select bits */
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
#define ADC_CTL0_DISNUM BITS(13, 15) /*!< discontinuous mode channel count */
#define ADC_CTL0_SYNCM BITS(16, 19) /*!< sync mode selection */
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
/* ADC_CTL1 */
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
#define ADC_CTL1_ETSIC BITS(12, 14) /*!< external trigger select for inserted channel */
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
#define ADC_CTL1_ETSRC BITS(17, 19) /*!< external trigger select for regular channel */
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */
/* ADC_SAMPTx x=0..1 */
#define ADC_SAMPTX_SPTN BITS(0, 2) /*!< channel n sample time selection */
/* ADC_IOFFx x=0..3 */
#define ADC_IOFFX_IOFF BITS(0, 11) /*!< data offset for inserted channel x */
/* ADC_WDHT */
#define ADC_WDHT_WDHT BITS(0, 11) /*!< analog watchdog high threshold */
/* ADC_WDLT */
#define ADC_WDLT_WDLT BITS(0, 11) /*!< analog watchdog low threshold */
/* ADC_RSQx x=0..2 */
#define ADC_RSQX_RSQN BITS(0, 4) /*!< nth conversion in regular sequence */
#define ADC_RSQ0_RL BITS(20, 23) /*!< regular channel sequence length */
/* ADC_ISQ */
#define ADC_ISQ_ISQN BITS(0, 4) /*!< nth conversion in inserted sequence */
#define ADC_ISQ_IL BITS(20, 21) /*!< inserted sequence length */
/* ADC_IDATAx x=0..3*/
#define ADC_IDATAX_IDATAN BITS(0, 15) /*!< inserted data n */
/* ADC_RDATA */
#define ADC_RDATA_RDATA BITS(0, 15) /*!< regular data */
#define ADC_RDATA_ADC1RDTR BITS(16, 31) /*!< ADC1 regular channel data */
/* ADC_OVSCR */
#define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */
#define ADC_OVSCR_OVSR BITS(2, 4) /*!< oversampling ratio */
#define ADC_OVSCR_OVSS BITS(5, 8) /*!< oversampling shift */
#define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */
#define ADC_OVSCR_DRES BITS(12, 13) /*!< ADC data resolution */
/* constants definitions */
/* adc_stat register value */
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
/* adc_ctl0 register value */
#define CTL0_DISNUM(regval) (BITS(13, 15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
/* scan mode */
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
/* inserted channel group convert automatically */
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
/* ADC sync mode */
#define CTL0_SYNCM(regval) (BITS(16, 19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */
#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */
#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */
#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */
#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */
#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */
#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */
/* adc_ctl1 register value */
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
/* continuous mode */
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
/* external trigger select for regular channel */
#define CTL1_ETSRC(regval) (BITS(17, 19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */
/* for ADC0 and ADC1 regular channel */
#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */
#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */
#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
#define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
/* external trigger mode for inserted channel */
#define CTL1_ETSIC(regval) (BITS(12, 14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */
/* for ADC0 and ADC1 inserted channel */
#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */
#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */
#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */
#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
#define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
/* adc_samptx register value */
#define SAMPTX_SPT(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
/* adc_ioffx register value */
#define IOFFX_IOFF(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
/* adc_wdht register value */
#define WDHT_WDHT(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
/* adc_wdlt register value */
#define WDLT_WDLT(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
/* adc_rsqx register value */
#define RSQ0_RL(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
/* adc_isq register value */
#define ISQ_IL(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
/* ADC channel group definitions */
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
/* ADC inserted channel definitions */
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
/* ADC channel definitions */
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
/* ADC interrupt */
#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
/* ADC interrupt flag */
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
/* ADC resolution definitions */
#define OVSCR_DRES(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12))
#define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */
#define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */
#define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */
#define ADC_RESOLUTION_6B OVSCR_DRES(3) /*!< 6-bit ADC resolution */
/* ADC oversampling mode */
#define ADC_OVERSAMPLING_ALL_CONVERT 0 /*!< all oversampled conversions for a channel are done consecutively after a trigger */
#define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */
/* ADC oversampling shift */
#define OVSCR_OVSS(regval) (BITS(5, 8) & ((uint32_t)(regval) << 5))
#define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_3B OVSCR_OVSS(3) /*!< 3-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_4B OVSCR_OVSS(4) /*!< 4-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_5B OVSCR_OVSS(5) /*!< 5-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_6B OVSCR_OVSS(6) /*!< 6-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_7B OVSCR_OVSS(7) /*!< 7-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */
/* ADC oversampling ratio */
#define OVSCR_OVSR(regval) (BITS(2, 4) & ((uint32_t)(regval) << 2))
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSCR_OVSR(3) /*!< oversampling ratio X16 */
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSCR_OVSR(4) /*!< oversampling ratio X32 */
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSCR_OVSR(5) /*!< oversampling ratio X64 */
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSCR_OVSR(6) /*!< oversampling ratio X128 */
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSCR_OVSR(7) /*!< oversampling ratio X256 */
/* function declarations */
/* initialization config */
/* reset ADC */
void adc_deinit(uint32_t adc_periph);
/* configure the ADC sync mode */
void adc_mode_config(uint32_t mode);
/* enable or disable ADC special function */
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue);
/* configure ADC data alignment */
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment);
/* enable ADC interface */
void adc_enable(uint32_t adc_periph);
/* disable ADC interface */
void adc_disable(uint32_t adc_periph);
/* ADC calibration and reset calibration */
void adc_calibration_enable(uint32_t adc_periph);
/* enable the temperature sensor and Vrefint channel */
void adc_tempsensor_vrefint_enable(void);
/* disable the temperature sensor and Vrefint channel */
void adc_tempsensor_vrefint_disable(void);
/* DMA config */
/* enable DMA request */
void adc_dma_mode_enable(uint32_t adc_periph);
/* disable DMA request */
void adc_dma_mode_disable(uint32_t adc_periph);
/* regular group and inserted group config */
/* configure ADC discontinuous mode */
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length);
/* configure the length of regular channel group or inserted channel group */
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length);
/* configure ADC regular channel */
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
/* configure ADC inserted channel */
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
/* configure ADC inserted channel offset */
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset);
/* configure ADC external trigger source */
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
/* configure ADC external trigger */
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
/* enable ADC software trigger */
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group);
/* get channel data */
/* read ADC regular group data register */
uint16_t adc_regular_data_read(uint32_t adc_periph);
/* read ADC inserted group data register */
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel);
/* read the last ADC0 and ADC1 conversion result data in sync mode */
uint32_t adc_sync_mode_convert_value_read(void);
/* watchdog config */
/* configure ADC analog watchdog single channel */
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
/* configure ADC analog watchdog group channel */
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
/* disable ADC analog watchdog */
void adc_watchdog_disable(uint32_t adc_periph);
/* configure ADC analog watchdog threshold */
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold);
/* interrupt & flag functions */
/* get the ADC flag bits */
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag);
/* clear the ADC flag bits */
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag);
/* get the bit state of ADCx software start conversion */
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph);
/* get the bit state of ADCx software inserted channel start conversion */
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
/* get the ADC interrupt bits */
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt);
/* clear the ADC flag */
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt);
/* enable ADC interrupt */
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt);
/* disable ADC interrupt */
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt);
/* ADC resolution & oversample */
/* ADC resolution config */
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution);
/* ADC oversample mode config */
void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio);
/* enable ADC oversample mode */
void adc_oversample_mode_enable(uint32_t adc_periph);
/* disable ADC oversample mode */
void adc_oversample_mode_disable(uint32_t adc_periph);
#endif /* GD32VF103_ADC_H */
#ifdef __cplusplus
}
#endif

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/*!
\file gd32vf103_bkp.c
\brief BKP driver
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32vf103_bkp.h"
/* BKP register bits offset */
#define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U)
/*!
\brief reset BKP registers
\param[in] none
\param[out] none
\retval none
*/
void bkp_deinit(void)
{
/* reset BKP domain register*/
rcu_bkp_reset_enable();
rcu_bkp_reset_disable();
}
/*!
\brief write BKP data register
\param[in] register_number: refer to bkp_data_register_enum
only one parameter can be selected which is shown as below:
\arg BKP_DATA_x(x = 0..41): bkp data register number x
\param[in] data: the data to be write in BKP data register
\param[out] none
\retval none
*/
void bkp_data_write(bkp_data_register_enum register_number, uint16_t data)
{
if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
BKP_DATA10_41(register_number - 1U) = data;
}else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
BKP_DATA0_9(register_number - 1U) = data;
}else{
/* illegal parameters */
}
}
/*!
\brief read BKP data register
\param[in] register_number: refer to bkp_data_register_enum
only one parameter can be selected which is shown as below:
\arg BKP_DATA_x(x = 0..41): bkp data register number x
\param[out] none
\retval data of BKP data register
*/
uint16_t bkp_data_read(bkp_data_register_enum register_number)
{
uint16_t data = 0U;
/* get the data from the BKP data register */
if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
data = BKP_DATA10_41(register_number - 1U);
}else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
data = BKP_DATA0_9(register_number - 1U);
}else{
/* illegal parameters */
}
return data;
}
/*!
\brief enable RTC clock calibration output
\param[in] none
\param[out] none
\retval none
*/
void bkp_rtc_calibration_output_enable(void)
{
BKP_OCTL |= (uint16_t)BKP_OCTL_COEN;
}
/*!
\brief disable RTC clock calibration output
\param[in] none
\param[out] none
\retval none
*/
void bkp_rtc_calibration_output_disable(void)
{
BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN;
}
/*!
\brief enable RTC alarm or second signal output
\param[in] none
\param[out] none
\retval none
*/
void bkp_rtc_signal_output_enable(void)
{
BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN;
}
/*!
\brief disable RTC alarm or second signal output
\param[in] none
\param[out] none
\retval none
*/
void bkp_rtc_signal_output_disable(void)
{
BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN;
}
/*!
\brief select RTC output
\param[in] outputsel: RTC output selection
only one parameter can be selected which is shown as below:
\arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output
\arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output
\param[out] none
\retval none
*/
void bkp_rtc_output_select(uint16_t outputsel)
{
uint16_t ctl = 0U;
/* configure BKP_OCTL_ROSEL with outputsel */
ctl = BKP_OCTL;
ctl &= (uint16_t)~BKP_OCTL_ROSEL;
ctl |= outputsel;
BKP_OCTL = ctl;
}
/*!
\brief set RTC clock calibration value
\param[in] value: RTC clock calibration value
\arg 0x00 - 0x7F
\param[out] none
\retval none
*/
void bkp_rtc_calibration_value_set(uint8_t value)
{
uint16_t ctl;
/* configure BKP_OCTL_RCCV with value */
ctl = BKP_OCTL;
ctl &= (uint16_t)~BKP_OCTL_RCCV;
ctl |= (uint16_t)OCTL_RCCV(value);
BKP_OCTL = ctl;
}
/*!
\brief enable tamper detection
\param[in] none
\param[out] none
\retval none
*/
void bkp_tamper_detection_enable(void)
{
BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN;
}
/*!
\brief disable tamper detection
\param[in] none
\param[out] none
\retval none
*/
void bkp_tamper_detection_disable(void)
{
BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN;
}
/*!
\brief set tamper pin active level
\param[in] level: tamper active level
only one parameter can be selected which is shown as below:
\arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high
\arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low
\param[out] none
\retval none
*/
void bkp_tamper_active_level_set(uint16_t level)
{
uint16_t ctl = 0U;
/* configure BKP_TPCTL_TPAL with level */
ctl = BKP_TPCTL;
ctl &= (uint16_t)~BKP_TPCTL_TPAL;
ctl |= level;
BKP_TPCTL = ctl;
}
/*!
\brief enable tamper interrupt
\param[in] none
\param[out] none
\retval none
*/
void bkp_interrupt_enable(void)
{
BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE;
}
/*!
\brief disable tamper interrupt
\param[in] none
\param[out] none
\retval none
*/
void bkp_interrupt_disable(void)
{
BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE;
}
/*!
\brief get tamper flag state
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus bkp_flag_get(void)
{
if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear tamper flag state
\param[in] none
\param[out] none
\retval none
*/
void bkp_flag_clear(void)
{
BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET);
}
/*!
\brief get tamper interrupt flag state
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus bkp_interrupt_flag_get(void)
{
if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear tamper interrupt flag state
\param[in] none
\param[out] none
\retval none
*/
void bkp_interrupt_flag_clear(void)
{
BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET);
}

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/*!
\file gd32vf103_bkp.h
\brief definitions for the BKP
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef GD32VF103_BKP_H
#define GD32VF103_BKP_H
#include "gd32vf103.h"
/* BKP definitions */
#define BKP BKP_BASE /*!< BKP base address */
/* registers definitions */
#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */
#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */
#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */
#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */
#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */
#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */
#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */
#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */
#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */
#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */
#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */
#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */
#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */
#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */
#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */
#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */
#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */
#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */
#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */
#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */
#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */
#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */
#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */
#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */
#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */
#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */
#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */
#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */
#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */
#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */
#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */
#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */
#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */
#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */
#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */
#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */
#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */
#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */
#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */
#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */
#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */
#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */
#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */
#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */
#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */
/* bits definitions */
/* BKP_DATA */
#define BKP_DATA BITS(0, 15) /*!< backup data */
/* BKP_OCTL */
#define BKP_OCTL_RCCV BITS(0, 6) /*!< RTC clock calibration value */
#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */
#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */
#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */
/* BKP_TPCTL */
#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */
#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */
/* BKP_TPCS */
#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */
#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */
#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */
#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */
#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */
/* constants definitions */
/* BKP data register number */
typedef enum {
BKP_DATA_0 = 1, /*!< BKP data register 0 */
BKP_DATA_1, /*!< BKP data register 1 */
BKP_DATA_2, /*!< BKP data register 2 */
BKP_DATA_3, /*!< BKP data register 3 */
BKP_DATA_4, /*!< BKP data register 4 */
BKP_DATA_5, /*!< BKP data register 5 */
BKP_DATA_6, /*!< BKP data register 6 */
BKP_DATA_7, /*!< BKP data register 7 */
BKP_DATA_8, /*!< BKP data register 8 */
BKP_DATA_9, /*!< BKP data register 9 */
BKP_DATA_10, /*!< BKP data register 10 */
BKP_DATA_11, /*!< BKP data register 11 */
BKP_DATA_12, /*!< BKP data register 12 */
BKP_DATA_13, /*!< BKP data register 13 */
BKP_DATA_14, /*!< BKP data register 14 */
BKP_DATA_15, /*!< BKP data register 15 */
BKP_DATA_16, /*!< BKP data register 16 */
BKP_DATA_17, /*!< BKP data register 17 */
BKP_DATA_18, /*!< BKP data register 18 */
BKP_DATA_19, /*!< BKP data register 19 */
BKP_DATA_20, /*!< BKP data register 20 */
BKP_DATA_21, /*!< BKP data register 21 */
BKP_DATA_22, /*!< BKP data register 22 */
BKP_DATA_23, /*!< BKP data register 23 */
BKP_DATA_24, /*!< BKP data register 24 */
BKP_DATA_25, /*!< BKP data register 25 */
BKP_DATA_26, /*!< BKP data register 26 */
BKP_DATA_27, /*!< BKP data register 27 */
BKP_DATA_28, /*!< BKP data register 28 */
BKP_DATA_29, /*!< BKP data register 29 */
BKP_DATA_30, /*!< BKP data register 30 */
BKP_DATA_31, /*!< BKP data register 31 */
BKP_DATA_32, /*!< BKP data register 32 */
BKP_DATA_33, /*!< BKP data register 33 */
BKP_DATA_34, /*!< BKP data register 34 */
BKP_DATA_35, /*!< BKP data register 35 */
BKP_DATA_36, /*!< BKP data register 36 */
BKP_DATA_37, /*!< BKP data register 37 */
BKP_DATA_38, /*!< BKP data register 38 */
BKP_DATA_39, /*!< BKP data register 39 */
BKP_DATA_40, /*!< BKP data register 40 */
BKP_DATA_41, /*!< BKP data register 41 */
} bkp_data_register_enum;
/* BKP register */
#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number)*0x04U)
#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)
/* get data of BKP data register */
#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15)
/* RTC clock calibration value */
#define OCTL_RCCV(regval) (BITS(0, 6) & ((uint32_t)(regval) << 0))
/* RTC output selection */
#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */
#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */
/* tamper pin active level */
#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */
#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */
/* tamper flag */
#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */
/* tamper interrupt flag */
#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */
/* function declarations */
/* reset BKP registers */
void bkp_deinit(void);
/* write BKP data register */
void bkp_data_write(bkp_data_register_enum register_number, uint16_t data);
/* read BKP data register */
uint16_t bkp_data_read(bkp_data_register_enum register_number);
/* RTC related functions */
/* enable RTC clock calibration output */
void bkp_rtc_calibration_output_enable(void);
/* disable RTC clock calibration output */
void bkp_rtc_calibration_output_disable(void);
/* enable RTC alarm or second signal output */
void bkp_rtc_signal_output_enable(void);
/* disable RTC alarm or second signal output */
void bkp_rtc_signal_output_disable(void);
/* select RTC output */
void bkp_rtc_output_select(uint16_t outputsel);
/* set RTC clock calibration value */
void bkp_rtc_calibration_value_set(uint8_t value);
/* tamper pin related functions */
/* enable tamper pin detection */
void bkp_tamper_detection_enable(void);
/* disable tamper pin detection */
void bkp_tamper_detection_disable(void);
/* set tamper pin active level */
void bkp_tamper_active_level_set(uint16_t level);
/* interrupt & flag functions */
/* enable tamper interrupt */
void bkp_interrupt_enable(void);
/* disable tamper interrupt */
void bkp_interrupt_disable(void);
/* get tamper flag state */
FlagStatus bkp_flag_get(void);
/* clear tamper flag state */
void bkp_flag_clear(void);
/* get tamper interrupt flag state */
FlagStatus bkp_interrupt_flag_get(void);
/* clear tamper interrupt flag state */
void bkp_interrupt_flag_clear(void);
#endif /* GD32VF103_BKP_H */
#ifdef __cplusplus
}
#endif

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/*!
\file gd32vf103_crc.c
\brief CRC driver
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32vf103_crc.h"
#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU)
#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U)
/*!
\brief deinit CRC calculation unit
\param[in] none
\param[out] none
\retval none
*/
void crc_deinit(void)
{
CRC_DATA = CRC_DATA_RESET_VALUE;
CRC_FDATA = CRC_FDATA_RESET_VALUE;
CRC_CTL = (uint32_t)CRC_CTL_RST;
}
/*!
\brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF
\param[in] none
\param[out] none
\retval none
*/
void crc_data_register_reset(void)
{
CRC_CTL |= (uint32_t)CRC_CTL_RST;
}
/*!
\brief read the value of the data register
\param[in] none
\param[out] none
\retval 32-bit value of the data register
*/
uint32_t crc_data_register_read(void)
{
uint32_t data;
data = CRC_DATA;
return (data);
}
/*!
\brief read the value of the free data register
\param[in] none
\param[out] none
\retval 8-bit value of the free data register
*/
uint8_t crc_free_data_register_read(void)
{
uint8_t fdata;
fdata = (uint8_t)CRC_FDATA;
return (fdata);
}
/*!
\brief write data to the free data register
\param[in] free_data: specified 8-bit data
\param[out] none
\retval none
*/
void crc_free_data_register_write(uint8_t free_data)
{
CRC_FDATA = (uint32_t)free_data;
}
/*!
\brief calculate the CRC value of a 32-bit data
\param[in] sdata: specified 32-bit data
\param[out] none
\retval 32-bit value calculated by CRC
*/
uint32_t crc_single_data_calculate(uint32_t sdata)
{
CRC_DATA = sdata;
return (CRC_DATA);
}
/*!
\brief calculate the CRC value of an array of 32-bit values
\param[in] array: pointer to an array of 32-bit values
\param[in] size: size of the array
\param[out] none
\retval 32-bit value calculated by CRC
*/
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
{
uint32_t index;
for(index = 0U; index < size; index++){
CRC_DATA = array[index];
}
return (CRC_DATA);
}

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/*!
\file gd32vf103_crc.h
\brief definitions for the CRC
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef GD32VF103_CRC_H
#define GD32VF103_CRC_H
#include "gd32vf103.h"
/* CRC definitions */
#define CRC CRC_BASE
/* registers definitions */
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
/* bits definitions */
/* CRC_DATA */
#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */
/* CRC_FDATA */
#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */
/* CRC_CTL */
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
/* function declarations */
/* deinit CRC calculation unit */
void crc_deinit(void);
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
void crc_data_register_reset(void);
/* read the value of the data register */
uint32_t crc_data_register_read(void);
/* read the value of the free data register */
uint8_t crc_free_data_register_read(void);
/* write data to the free data register */
void crc_free_data_register_write(uint8_t free_data);
/* calculate the CRC value of a 32-bit data */
uint32_t crc_single_data_calculate(uint32_t sdata);
/* calculate the CRC value of an array of 32-bit values */
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
#endif /* GD32VF103_CRC_H */
#ifdef __cplusplus
}
#endif

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/*!
\file gd32vf103_dbg.c
\brief DBG driver
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32vf103_dbg.h"
/*!
\brief read DBG_ID code register
\param[in] none
\param[out] none
\retval DBG_ID code
*/
uint32_t dbg_id_get(void)
{
return DBG_ID;
}
/*!
\brief enable low power behavior when the mcu is in debug mode
\param[in] dbg_low_power:
one or more parameters can be selected which are shown as below:
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
\param[out] none
\retval none
*/
void dbg_low_power_enable(uint32_t dbg_low_power)
{
DBG_CTL |= dbg_low_power;
}
/*!
\brief disable low power behavior when the mcu is in debug mode
\param[in] dbg_low_power:
one or more parameters can be selected which are shown as below:
\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
\param[out] none
\retval none
*/
void dbg_low_power_disable(uint32_t dbg_low_power)
{
DBG_CTL &= ~dbg_low_power;
}
/*!
\brief enable peripheral behavior when the mcu is in debug mode
\param[in] dbg_periph: refer to dbg_periph_enum
one or more parameters can be selected which are shown as below:
\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
\arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted
\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted
\param[out] none
\retval none
*/
void dbg_periph_enable(dbg_periph_enum dbg_periph)
{
DBG_CTL |= (uint32_t)dbg_periph;
}
/*!
\brief disable peripheral behavior when the mcu is in debug mode
\param[in] dbg_periph: refer to dbg_periph_enum
one or more parameters can be selected which are shown as below:
\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
\arg DBG_CANx_HOLD (x=0,1): hold CAN0 counter when core is halted
\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted
\param[out] none
\retval none
*/
void dbg_periph_disable(dbg_periph_enum dbg_periph)
{
DBG_CTL &= ~(uint32_t)dbg_periph;
}

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/*!
\file gd32vf103_dbg.h
\brief definitions for the DBG
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef GD32VF103_DBG_H
#define GD32VF103_DBG_H
#include "gd32vf103.h"
/* DBG definitions */
#define DBG DBG_BASE
/* registers definitions */
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */
/* bits definitions */
/* DBG_ID */
#define DBG_ID_ID_CODE BITS(0, 31) /*!< DBG ID code values */
/* DBG_CTL */
#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */
#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */
#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */
#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */
/* constants definitions */
/* debug hold when core is halted */
typedef enum {
DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */
DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */
DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */
DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */
DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */
DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */
DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */
DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */
DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */
DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */
} dbg_periph_enum;
/* DBG low power mode configurations */
#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */
/* function declarations */
/* read DBG_ID code register */
uint32_t dbg_id_get(void);
/* low power behavior configuration */
/* enable low power behavior when the MCU is in debug mode */
void dbg_low_power_enable(uint32_t dbg_low_power);
/* disable low power behavior when the MCU is in debug mode */
void dbg_low_power_disable(uint32_t dbg_low_power);
/* peripheral behavior configuration */
/* enable peripheral behavior when the MCU is in debug mode */
void dbg_periph_enable(dbg_periph_enum dbg_periph);
/* disable peripheral behavior when the MCU is in debug mode */
void dbg_periph_disable(dbg_periph_enum dbg_periph);
#endif /* GD32VF103_DBG_H */
#ifdef __cplusplus
}
#endif

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/*!
\file gd32vf103_dma.c
\brief DMA driver
\version 2019-06-05, V1.0.0, firmware for GD32VF103
\version 2019-10-30, V1.0.1, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32vf103_dma.h"
#define DMA_WRONG_HANDLE while(1){}
/* check whether peripheral matches channels or not */
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx);
/*!
\brief deinitialize DMA a channel registers
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel is deinitialized
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* disable DMA a channel */
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
/* reset DMA channel registers */
DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
}
/*!
\brief initialize the parameters of DMA struct with the default values
\param[in] init_struct: the initialization data needed to initialize DMA channel
\param[out] none
\retval none
*/
void dma_struct_para_init(dma_parameter_struct* init_struct)
{
/* set the DMA struct with the default values */
init_struct->periph_addr = 0U;
init_struct->periph_width = 0U;
init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE;
init_struct->memory_addr = 0U;
init_struct->memory_width = 0U;
init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE;
init_struct->number = 0U;
init_struct->direction = DMA_PERIPHERAL_TO_MEMORY;
init_struct->priority = DMA_PRIORITY_LOW;
}
/*!
\brief initialize DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel is initialized
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] init_struct: the data needed to initialize DMA channel
periph_addr: peripheral base address
periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE
memory_addr: memory base address
memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
number: the number of remaining data to be transferred by the DMA
priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
\param[out] none
\retval none
*/
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* configure peripheral base address */
DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr;
/* configure memory base address */
DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr;
/* configure the number of remaining data to be transferred */
DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK);
/* configure peripheral transfer width,memory transfer width and priority */
ctl = DMA_CHCTL(dma_periph, channelx);
ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority);
DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
}else{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
}
/* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
}else{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/* configure the direction of data transfer */
if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
}else{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
}
}
/*!
\brief enable DMA circulation mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
}
/*!
\brief disable DMA circulation mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
}
/*!
\brief enable memory to memory mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M;
}
/*!
\brief disable memory to memory mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
}
/*!
\brief enable DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
}
/*!
\brief disable DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
}
/*!
\brief set DMA peripheral base address
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set peripheral base address
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] address: peripheral base address
\param[out] none
\retval none
*/
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHPADDR(dma_periph, channelx) = address;
}
/*!
\brief set DMA memory base address
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set memory base address
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] address: memory base address
\param[out] none
\retval none
*/
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHMADDR(dma_periph, channelx) = address;
}
/*!
\brief set the number of remaining data to be transferred by the DMA
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set number
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] number: the number of remaining data to be transferred by the DMA
\param[out] none
\retval none
*/
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK);
}
/*!
\brief get the number of remaining data to be transferred by the DMA
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set number
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval uint32_t: the number of remaining data to be transferred by the DMA
*/
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
return (uint32_t)DMA_CHCNT(dma_periph, channelx);
}
/*!
\brief configure priority level of DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] priority: priority Level of this channel
only one parameter can be selected which is shown as below:
\arg DMA_PRIORITY_LOW: low priority
\arg DMA_PRIORITY_MEDIUM: medium priority
\arg DMA_PRIORITY_HIGH: high priority
\arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
\param[out] none
\retval none
*/
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph, channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PRIO;
ctl |= priority;
DMA_CHCTL(dma_periph, channelx) = ctl;
}
/*!
\brief configure transfer data size of memory
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] mwidth: transfer data width of memory
only one parameter can be selected which is shown as below:
\arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
\arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
\arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
\param[out] none
\retval none
*/
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph, channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_MWIDTH;
ctl |= mwidth;
DMA_CHCTL(dma_periph, channelx) = ctl;
}
/*!
\brief configure transfer data size of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] pwidth: transfer data width of peripheral
only one parameter can be selected which is shown as below:
\arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
\arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
\arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
\param[out] none
\retval none
*/
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph, channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PWIDTH;
ctl |= pwidth;
DMA_CHCTL(dma_periph, channelx) = ctl;
}
/*!
\brief enable next address increasement algorithm of memory
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
}
/*!
\brief disable next address increasement algorithm of memory
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/*!
\brief enable next address increasement algorithm of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
}
/*!
\brief disable next address increasement algorithm of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
}
/*!
\brief configure the direction of data transfer on the channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] direction: specify the direction of data transfer
only one parameter can be selected which is shown as below:
\arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
\arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
\param[out] none
\retval none
*/
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
if(DMA_PERIPHERAL_TO_MEMORY == direction){
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
}
}
/*!
\brief check DMA flag is set or not
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to get flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_FLAG_G: global interrupt flag of channel
\arg DMA_FLAG_FTF: full transfer finish flag of channel
\arg DMA_FLAG_HTF: half transfer finish flag of channel
\arg DMA_FLAG_ERR: error flag of channel
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
FlagStatus reval;
if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){
reval = SET;
}else{
reval = RESET;
}
return reval;
}
/*!
\brief clear DMA a channel flag
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to clear flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_FLAG_G: global interrupt flag of channel
\arg DMA_FLAG_FTF: full transfer finish flag of channel
\arg DMA_FLAG_HTF: half transfer finish flag of channel
\arg DMA_FLAG_ERR: error flag of channel
\param[out] none
\retval none
*/
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
}
/*!
\brief check DMA flag and interrupt enable bit is set or not
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to get flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
switch(flag){
case DMA_INT_FLAG_FTF:
/* check whether the full transfer finish interrupt flag is set and enabled */
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
break;
case DMA_INT_FLAG_HTF:
/* check whether the half transfer finish interrupt flag is set and enabled */
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
break;
case DMA_INT_FLAG_ERR:
/* check whether the error interrupt flag is set and enabled */
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
break;
default:
DMA_WRONG_HANDLE
}
/* when the interrupt flag is set and enabled, return SET */
if(interrupt_flag && interrupt_enable){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear DMA a channel flag
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to clear flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_INT_FLAG_G: global interrupt flag of channel
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
\param[out] none
\retval none
*/
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
}
/*!
\brief enable DMA interrupt
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] source: specify which interrupt to enbale
one or more parameters can be selected which are shown as below
\arg DMA_INT_FTF: channel full transfer finish interrupt
\arg DMA_INT_HTF: channel half transfer finish interrupt
\arg DMA_INT_ERR: channel error interrupt
\param[out] none
\retval none
*/
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= source;
}
/*!
\brief disable DMA interrupt
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] source: specify which interrupt to disbale
one or more parameters can be selected which are shown as below
\arg DMA_INT_FTF: channel full transfer finish interrupt
\arg DMA_INT_HTF: channel half transfer finish interrupt
\arg DMA_INT_ERR: channel error interrupt
\param[out] none
\retval none
*/
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~source;
}
/*!
\brief check whether peripheral and channels match
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA_CHx(x=0..6)
\param[out] none
\retval none
*/
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx)
{
ErrStatus val = SUCCESS;
if(DMA1 == dma_periph){
/* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */
if(channelx > DMA_CH4){
val = ERROR;
}
}
return val;
}

287
workspace/TS100/Core/BSP/Pine64/Vendor/Lib/gd32vf103_dma.h vendored Normal file
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@@ -0,0 +1,287 @@
/*!
\file gd32vf103_dma.h
\brief definitions for the DMA
\version 2019-06-05, V1.0.0, firmware for GD32VF103
\version 2019-10-30, V1.0.1, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef GD32VF103_DMA_H
#define GD32VF103_DMA_H
#include "gd32vf103.h"
/* DMA definitions */
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */
/* registers definitions */
#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */
#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */
#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */
#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */
#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */
#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */
#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */
#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */
#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */
#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */
#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */
/* bits definitions */
/* DMA_INTF */
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
/* DMA_INTC */
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
/* DMA_CHxCTL, x=0..6 */
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */
#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */
#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
#define DMA_CHXCTL_PWIDTH BITS(8, 9) /*!< transfer data width of peripheral */
#define DMA_CHXCTL_MWIDTH BITS(10, 11) /*!< transfer data width of memory */
#define DMA_CHXCTL_PRIO BITS(12, 13) /*!< priority level */
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
/* DMA_CHxCNT, x=0..6 */
#define DMA_CHXCNT_CNT BITS(0, 15) /*!< transfer counter */
/* DMA_CHxPADDR, x=0..6 */
#define DMA_CHXPADDR_PADDR BITS(0, 31) /*!< peripheral base address */
/* DMA_CHxMADDR, x=0..6 */
#define DMA_CHXMADDR_MADDR BITS(0, 31) /*!< memory base address */
/* constants definitions */
/* DMA channel select */
typedef enum {
DMA_CH0 = 0, /*!< DMA Channel0 */
DMA_CH1, /*!< DMA Channel1 */
DMA_CH2, /*!< DMA Channel2 */
DMA_CH3, /*!< DMA Channel3 */
DMA_CH4, /*!< DMA Channel4 */
DMA_CH5, /*!< DMA Channel5 */
DMA_CH6 /*!< DMA Channel6 */
} dma_channel_enum;
/* DMA initialize struct */
typedef struct
{
uint32_t periph_addr; /*!< peripheral base address */
uint32_t periph_width; /*!< transfer data size of peripheral */
uint32_t memory_addr; /*!< memory base address */
uint32_t memory_width; /*!< transfer data size of memory */
uint32_t number; /*!< channel transfer number */
uint32_t priority; /*!< channel priority level */
uint8_t periph_inc; /*!< peripheral increasing mode */
uint8_t memory_inc; /*!< memory increasing mode */
uint8_t direction; /*!< channel data transfer direction */
} dma_parameter_struct;
#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift)*4U)) /*!< DMA channel flag shift */
/* DMA_register address */
#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
/* DMA reset value */
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
/* DMA_INTF register */
/* interrupt flag bits */
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
/* flag bits */
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
/* DMA_CHxCTL register */
/* interrupt enable bits */
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
/* transfer direction */
#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */
#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */
/* peripheral increasing mode */
#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */
#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */
/* memory increasing mode */
#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */
#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */
/* transfer data size of peripheral */
#define CHCTL_PWIDTH(regval) (BITS(8, 9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
/* transfer data size of memory */
#define CHCTL_MWIDTH(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
/* channel priority level */
#define CHCTL_PRIO(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */
#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */
/* memory to memory mode */
#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */
#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */
/* DMA_CHxCNT register */
/* transfer counter */
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */
/* function declarations */
/* DMA deinitialization and initialization functions */
/* deinitialize DMA a channel registers */
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
/* initialize the parameters of DMA struct with the default values */
void dma_struct_para_init(dma_parameter_struct *init_struct);
/* initialize DMA channel */
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct);
/* enable DMA circulation mode */
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable DMA circulation mode */
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* enable memory to memory mode */
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable memory to memory mode */
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* enable DMA channel */
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable DMA channel */
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* DMA configuration functions */
/* set DMA peripheral base address */
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
/* set DMA memory base address */
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
/* set the number of remaining data to be transferred by the DMA */
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
/* get the number of remaining data to be transferred by the DMA */
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
/* configure priority level of DMA channel */
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
/* configure transfer data size of memory */
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
/* configure transfer data size of peripheral */
void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
/* enable next address increasement algorithm of memory */
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable next address increasement algorithm of memory */
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* enable next address increasement algorithm of peripheral */
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable next address increasement algorithm of peripheral */
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* configure the direction of data transfer on the channel */
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction);
/* flag and interrupt functions */
/* check DMA flag is set or not */
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
/* clear the flag of a DMA channel */
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
/* check DMA flag and interrupt enable bit is set or not */
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
/* clear the interrupt flag of a DMA channel */
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
/* enable DMA interrupt */
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
/* disable DMA interrupt */
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
#endif /* GD32VF103_DMA_H */
#ifdef __cplusplus
}
#endif

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/*!
\file gd32vf103_eclic.c
\brief ECLIC(Enhancement Core-Local Interrupt Controller) driver
\version 2019-06-05, V1.0.1, firmware for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32vf103_eclic.h"
#include "riscv_encoding.h"
extern uint32_t mstatus;
#define REG_DBGMCU2 ((uint32_t)0xE0042008)
#define REG_DBGMCU2EN ((uint32_t)0xE004200C)
/*!
\brief enable the global interrupt
\param[in] none
\param[out] none
\retval none
*/
void eclic_global_interrupt_enable(void) {
/* set machine interrupt enable bit */
set_csr(mstatus, MSTATUS_MIE);
}
/*!
\brief disable the global interrupt
\param[in] none
\param[out] none
\retval none
*/
void eclic_global_interrupt_disable(void) {
/* clear machine interrupt enable bit */
clear_csr(mstatus, MSTATUS_MIE);
}
/*!
\brief set the priority group
\param[in] prigroup: specify the priority group
\arg ECLIC_PRIGROUP_LEVEL0_PRIO4
\arg ECLIC_PRIGROUP_LEVEL1_PRIO3
\arg ECLIC_PRIGROUP_LEVEL2_PRIO2
\arg ECLIC_PRIGROUP_LEVEL3_PRIO1
\arg ECLIC_PRIGROUP_LEVEL4_PRIO0
\param[out] none
\retval none
*/
void eclic_priority_group_set(uint32_t prigroup) {
eclic_set_nlbits(prigroup);
}
/*!
\brief enable the interrupt request
\param[in] source: interrupt request, detailed in IRQn_Type
\param[in] level: the level needed to set (maximum is 15, refer to the priority group)
\param[in] priority: the priority needed to set (maximum is 15, refer to the priority group)
\param[out] none
\retval none
*/
void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority) {
eclic_enable_interrupt(source);
eclic_set_irq_lvl_abs(source, level);
eclic_set_irq_priority(source, priority);
}
/*!
\brief disable the interrupt request
\param[in] source: interrupt request, detailed in IRQn_Type
\param[out] none
\retval none
*/
void eclic_irq_disable(uint32_t source) {
eclic_disable_interrupt(source);
}
/*!
\brief reset system
\param[in] none
\param[out] none
\retval none
*/
void eclic_system_reset(void) {
REG32(REG_DBGMCU2EN) = 0x4b5a6978;
REG32(REG_DBGMCU2) = 0x1;
}
/*!
\brief send event(SEV)
\param[in] none
\param[out] none
\retval none
*/
void eclic_send_event(void) {
set_csr(0x812, 0x1);
}

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