From 8ea1edf7a778b1c35bb303d68833ba8a6c158cdb Mon Sep 17 00:00:00 2001 From: "Ben V. Brown" Date: Thu, 21 Apr 2022 18:25:14 +1000 Subject: [PATCH] Tuning in ADC --- source/Core/BSP/Magic/BSP.cpp | 4 ++-- source/Core/BSP/Magic/IRQ.cpp | 4 ++-- source/Core/BSP/Magic/Setup.cpp | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/source/Core/BSP/Magic/BSP.cpp b/source/Core/BSP/Magic/BSP.cpp index 7c857124..8a67734e 100644 --- a/source/Core/BSP/Magic/BSP.cpp +++ b/source/Core/BSP/Magic/BSP.cpp @@ -12,8 +12,8 @@ // These control the period's of time used for the PWM const uint16_t powerPWM = 255; -const uint8_t holdoffTicks = 14; -const uint8_t tempMeasureTicks = 10; +const uint8_t holdoffTicks = 3; // This is the tick delay +const uint8_t tempMeasureTicks = 4; uint16_t totalPWM = 255; // Total length of the cycle's ticks diff --git a/source/Core/BSP/Magic/IRQ.cpp b/source/Core/BSP/Magic/IRQ.cpp index c1350c79..44655d58 100644 --- a/source/Core/BSP/Magic/IRQ.cpp +++ b/source/Core/BSP/Magic/IRQ.cpp @@ -108,7 +108,7 @@ void switchToFastPWM(void) { uint32_t tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, 20); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, 11); BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal); } @@ -126,7 +126,7 @@ void switchToSlowPWM(void) { uint32_t tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, 40); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, 22); BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal); } diff --git a/source/Core/BSP/Magic/Setup.cpp b/source/Core/BSP/Magic/Setup.cpp index bf6a31c5..6ae30fe9 100644 --- a/source/Core/BSP/Magic/Setup.cpp +++ b/source/Core/BSP/Magic/Setup.cpp @@ -86,7 +86,7 @@ void setup_adc(void) { ADC_Reset(); ADC_Init(&adc_cfg); adc_fifo_cfg.dmaEn = DISABLE; - adc_fifo_cfg.fifoThreshold = ADC_FIFO_THRESHOLD_8; + adc_fifo_cfg.fifoThreshold = ADC_FIFO_THRESHOLD_4; ADC_FIFO_Cfg(&adc_fifo_cfg); ADC_MIC_Bias_Disable();