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Move to latest HAL release trying to get I2C DMA to be more reliable, and known good point.

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Cleans up some redundant calls as well to make some flash room.
This commit is contained in:
Ben V. Brown
2018-12-16 18:13:59 +11:00
parent b744f51e2d
commit 873eb2a1e9
135 changed files with 9319 additions and 6521 deletions
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74
workspace/TS100/HAL_Driver/Src/stm32f1xx_ll_rcc.c
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@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_ll_rcc.c
* @author MCD Application Team
* @version V1.1.1
* @date 12-May-2017
* @brief RCC LL module driver.
******************************************************************************
* @attention
@@ -106,7 +104,7 @@ uint32_t RCC_PLL2_GetFreqClockFreq(void);
* @brief Reset the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
* - HSE PLL, PLL2, PLL3 OFF
* - HSE PLL, PLL2 & PLL3 are OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO OFF
* - All interrupts disabled
@@ -114,78 +112,62 @@ uint32_t RCC_PLL2_GetFreqClockFreq(void);
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RCC registers are de-initialized
* - ERROR: not applicable
* - SUCCESS: RCC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_RCC_DeInit(void)
{
uint32_t vl_mask = 0U;
/* Set HSION bit */
LL_RCC_HSI_Enable();
/* Reset SW, HPRE, PPRE, MCOSEL, PLLXTPRE, PLLSRC and ADCPRE bits */
vl_mask = 0xFFFFFFFFU;
CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL |\
RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_ADCPRE));
/* Wait for HSI READY bit */
while(LL_RCC_HSI_IsReady() != 1U)
{}
#if defined(USB)
/* Reset USBPRE bit */
CLEAR_BIT(vl_mask, RCC_CFGR_USBPRE);
#elif defined(USB_OTG_FS)
/* Reset OTGFSPRE bit */
CLEAR_BIT(vl_mask, RCC_CFGR_OTGFSPRE);
#endif /* USB */
/* Configure HSI as system clock source */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
#if defined(RCC_CFGR_PLLMULL2)
/* Set PLL multiplication factor to 2 */
vl_mask |= RCC_CFGR_PLLMULL2;
#else
/* Set PLL multiplication factor to 4 */
vl_mask |= RCC_CFGR_PLLMULL4;
#endif /* RCC_CFGR_PLLMULL2 */
/* Wait till clock switch is ready */
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
{}
LL_RCC_WriteReg(CFGR, vl_mask);
/* Reset PLLON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
/* Reset HSEON, HSEBYP, CSSON, PLLON bits */
vl_mask = 0xFFFFFFFFU;
CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
/* Wait for PLL READY bit to be reset */
while(LL_RCC_PLL_IsReady() != 0U)
{}
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
/* Reset HSEON, HSEBYP & CSSON bits */
CLEAR_BIT(RCC->CR, (RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
#if defined(RCC_CR_PLL2ON)
/* Reset PLL2ON bit */
CLEAR_BIT(vl_mask, RCC_CR_PLL2ON);
CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
#endif /* RCC_CR_PLL2ON */
#if defined(RCC_CR_PLL3ON)
/* Reset PLL3ON bit */
CLEAR_BIT(vl_mask, RCC_CR_PLL3ON);
CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
#endif /* RCC_CR_PLL3ON */
LL_RCC_WriteReg(CR, vl_mask);
/* Set HSITRIM bits to the reset value */
LL_RCC_HSI_SetCalibTrimming(0x10U);
#if defined(RCC_CFGR2_PREDIV1)
/* Reset CFGR2 register */
vl_mask = 0x00000000U;
#if defined(RCC_PLL2_SUPPORT)
/* Set PLL2 multiplication factor to 8 */
vl_mask |= RCC_CFGR2_PLL2MUL8;
#endif /* RCC_PLL2_SUPPORT */
#if defined(RCC_PLLI2S_SUPPORT)
/* Set PLL3 multiplication factor to 8 */
vl_mask |= RCC_CFGR2_PLL3MUL8;
#endif /* RCC_PLLI2S_SUPPORT */
LL_RCC_WriteReg(CFGR2, vl_mask);
LL_RCC_WriteReg(CFGR2, 0x00000000U);
#endif /* RCC_CFGR2_PREDIV1 */
/* Disable all interrupts */
LL_RCC_WriteReg(CIR, 0x00000000U);
/* Clear reset flags */
LL_RCC_ClearResetFlags();
return SUCCESS;
}