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Move to latest HAL release trying to get I2C DMA to be more reliable, and known good point.
Cleans up some redundant calls as well to make some flash room.
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@@ -2,8 +2,6 @@
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******************************************************************************
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* @file stm32f1xx_hal_iwdg.c
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief IWDG HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Independent Watchdog (IWDG) peripheral:
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@@ -21,9 +19,9 @@
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(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
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if the main clock fails.
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(+) Once the IWDG is started, the LSI is forced ON and both can not be
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(+) Once the IWDG is started, the LSI is forced ON and both can not be
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disabled. The counter starts counting down from the reset value (0xFFF).
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When it reaches the end of count value (0x000) a reset signal is
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When it reaches the end of count value (0x000) a reset signal is
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generated (IWDG reset).
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(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
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@@ -119,7 +117,7 @@
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/** @defgroup IWDG_Private_Defines IWDG Private Defines
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* @{
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*/
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/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
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/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
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higher prescaler (256), and according to HSI variation, we need to wait at
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least 6 cycles so 48 ms. */
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#define HAL_IWDG_DEFAULT_TIMEOUT 48U
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@@ -166,7 +164,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
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uint32_t tickstart;
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/* Check the IWDG handle allocation */
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if(hiwdg == NULL)
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if (hiwdg == NULL)
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{
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return HAL_ERROR;
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}
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@@ -190,9 +188,9 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
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tickstart = HAL_GetTick();
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/* Wait for register to be updated */
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while(hiwdg->Instance->SR != RESET)
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while (hiwdg->Instance->SR != RESET)
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{
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if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
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if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
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{
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return HAL_TIMEOUT;
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}
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