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Format Pine code

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This commit is contained in:
Ben V. Brown
2021-01-17 10:55:15 +11:00
parent bf5055edaa
commit 7ecc7e4d12
60 changed files with 9387 additions and 10756 deletions
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3
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h vendored
View File

@@ -105,7 +105,8 @@ typedef struct {
* ADC can be either disabled or enabled without conversion on going on regular group.
*/
typedef struct {
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
uint32_t
Channel; /*!< Specifies the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)

8
source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h vendored
View File

@@ -69,13 +69,13 @@ extern "C" {
* - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
*/
typedef struct {
uint32_t
InjectedChannel; /*!< Selection of ADC channel to configure
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection
trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with
injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata
sheet of these devices for more details. */
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
This parameter must be a value of @ref ADCEx_injected_rank
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel

29
source/Core/BSP/Pine64/BSP.cpp
View File

@@ -16,10 +16,8 @@ const uint8_t tempMeasureTicks = 25;
uint16_t totalPWM; // htim2.Init.Period, the full PWM cycle
// 2 second filter (ADC is PID_TIM_HZ Hz)
history<uint16_t, PID_TIM_HZ> rawTempFilter = { { 0 }, 0, 0 };
void resetWatchdog() {
fwdgt_counter_reload();
}
history<uint16_t, PID_TIM_HZ> rawTempFilter = {{0}, 0, 0};
void resetWatchdog() { fwdgt_counter_reload(); }
uint16_t getTipInstantTemperature() {
volatile uint16_t sum = 0; // 12 bit readings * 8*2 -> 16 bits
@@ -90,8 +88,7 @@ uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) {
void unstick_I2C() {
/* configure SDA/SCL for GPIO */
GPIO_BC(GPIOB) |= SDA_Pin | SCL_Pin;
gpio_init(SDA_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ,
SDA_Pin | SCL_Pin);
gpio_init(SDA_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin);
asm("nop");
asm("nop");
asm("nop");
@@ -106,26 +103,18 @@ void unstick_I2C() {
GPIO_BOP(GPIOB) |= SDA_Pin;
/* connect PB6 to I2C0_SCL */
/* connect PB7 to I2C0_SDA */
gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ,
SDA_Pin | SCL_Pin);
gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin);
}
uint8_t getButtonA() {
return (gpio_input_bit_get(KEY_A_GPIO_Port, KEY_A_Pin) == SET) ? 1 : 0;
}
uint8_t getButtonB() {
return (gpio_input_bit_get(KEY_B_GPIO_Port, KEY_B_Pin) == SET) ? 1 : 0;
}
uint8_t getButtonA() { return (gpio_input_bit_get(KEY_A_GPIO_Port, KEY_A_Pin) == SET) ? 1 : 0; }
uint8_t getButtonB() { return (gpio_input_bit_get(KEY_B_GPIO_Port, KEY_B_Pin) == SET) ? 1 : 0; }
void reboot() {
//Spin for watchdog
for (;;) {
}
// Spin for watchdog
for (;;) {}
}
void delay_ms(uint16_t count) {
delay_1ms(count);
}
void delay_ms(uint16_t count) { delay_1ms(count); }
uint32_t __get_IPSR(void) {
return 0; // To shut-up CMSIS
}

12
source/Core/BSP/Pine64/BSP_PD.c
View File

@@ -12,14 +12,14 @@
* An array of all of the desired voltages & minimum currents in preferred order
*/
const uint16_t USB_PD_Desired_Levels[] = {
//mV desired input, mA minimum required current
//Tip is ~ 7.5 ohms
// mV desired input, mA minimum required current
// Tip is ~ 7.5 ohms
20000, 2666, // 20V, 2.6A
15000, 2000, // 15V 2A
12000, 1600, //12V @ 1.6A
9000, 1200, //9V @ 1.2A
5000, 100, //5V @ whatever
12000, 1600, // 12V @ 1.6A
9000, 1200, // 9V @ 1.2A
5000, 100, // 5V @ whatever
};
};
const uint8_t USB_PD_Desired_Levels_Len = 5;
#endif

75
source/Core/BSP/Pine64/I2C_Wrapper.cpp
View File

@@ -15,9 +15,7 @@ void FRToSI2C::CpltCallback() {
// TODO
}
bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) {
return Mem_Write(address, reg, &data, 1);
}
bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }
uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) {
uint8_t temp = 0;
@@ -45,7 +43,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
if (tries > 64) {
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
unlock();
@@ -60,7 +58,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
/* enable acknowledge */
i2c_ack_config(I2C0, I2C_ACK_ENABLE);
/* i2c master sends start signal only when the bus is idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT )) {
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -81,7 +79,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
break;
case I2C_SEND_ADDRESS:
/* i2c master sends START signal successfully */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT )) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -101,13 +99,13 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
break;
case I2C_CLEAR_ADDRESS_FLAG:
/* address flag set means i2c slave sends ACK */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT )) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++;
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
// Address NACK'd
@@ -122,7 +120,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
} else {
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
// Address NACK'd
@@ -133,7 +131,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
case I2C_TRANSMIT_DATA:
if (0 == in_rx_cycle) {
/* wait until the transmit data buffer is empty */
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT )) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -146,7 +144,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
in_rx_cycle = 0;
}
/* wait until BTC bit is set */
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT )) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -179,11 +177,11 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
} else { /* more than one byte master reception procedure (DMA) */
dma_deinit(DMA0, DMA_CH6);
dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_addr = (uint32_t) p_buffer;
dma_init_struct.memory_addr = (uint32_t)p_buffer;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
dma_init_struct.number = number_of_byte;
dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0);
dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0);
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
@@ -195,9 +193,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
/* enable DMA0 channel5 */
dma_channel_enable(DMA0, DMA_CH6);
/* wait until BTC bit is set */
while (!dma_flag_get(DMA0, DMA_CH6, DMA_FLAG_FTF)) {
}
while (!dma_flag_get(DMA0, DMA_CH6, DMA_FLAG_FTF)) {}
/* send a stop condition to I2C bus*/
i2c_stop_on_bus(I2C0);
}
@@ -207,7 +203,7 @@ bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_b
break;
case I2C_STOP:
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -249,7 +245,7 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
switch (state) {
case I2C_START:
/* i2c master sends start signal only when the bus is idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT )) {
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -264,7 +260,7 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
break;
case I2C_SEND_ADDRESS:
/* i2c master sends START signal successfully */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT )) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -280,13 +276,13 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
break;
case I2C_CLEAR_ADDRESS_FLAG:
/* address flag set means i2c slave sends ACK */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT )) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++;
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
// Address NACK'd
@@ -302,7 +298,7 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
// Dont retry as this means a NAK
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
unlock();
@@ -311,7 +307,7 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
break;
case I2C_TRANSMIT_DATA:
/* wait until the transmit data buffer is empty */
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT )) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -329,11 +325,11 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
;
dma_deinit(DMA0, DMA_CH5);
dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_addr = (uint32_t) p_buffer;
dma_init_struct.memory_addr = (uint32_t)p_buffer;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
dma_init_struct.number = number_of_byte;
dma_init_struct.periph_addr = (uint32_t) &I2C_DATA(I2C0);
dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0);
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
@@ -343,19 +339,16 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
/* enable DMA0 channel5 */
dma_channel_enable(DMA0, DMA_CH5);
/* wait until BTC bit is set */
while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {
}
while (!dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) {}
/* wait until BTC bit is set */
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) {
}
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) {}
state = I2C_STOP;
break;
case I2C_STOP:
/* send a stop condition to I2C bus */
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -379,18 +372,14 @@ bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_bu
return timedout == false;
}
bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1);
}
bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) { return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1); }
bool FRToSI2C::probe(uint16_t DevAddress) {
uint8_t temp[1];
return Mem_Read(DevAddress, 0x00, temp, sizeof(temp));
}
void FRToSI2C::I2C_Unstick() {
unstick_I2C();
}
void FRToSI2C::I2C_Unstick() { unstick_I2C(); }
bool FRToSI2C::lock() {
if (I2CSemaphore == nullptr) {
@@ -438,7 +427,7 @@ bool FRToSI2C::wakePart(uint16_t DevAddress) {
switch (state) {
case I2C_START:
/* i2c master sends start signal only when the bus is idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT )) {
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -453,7 +442,7 @@ bool FRToSI2C::wakePart(uint16_t DevAddress) {
break;
case I2C_SEND_ADDRESS:
/* i2c master sends START signal successfully */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT )) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
@@ -469,13 +458,13 @@ bool FRToSI2C::wakePart(uint16_t DevAddress) {
break;
case I2C_CLEAR_ADDRESS_FLAG:
/* address flag set means i2c slave sends ACK */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT )) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++;
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
// Address NACK'd
@@ -491,7 +480,7 @@ bool FRToSI2C::wakePart(uint16_t DevAddress) {
// Dont retry as this means a NAK
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
unlock();
@@ -503,7 +492,7 @@ bool FRToSI2C::wakePart(uint16_t DevAddress) {
/* send a stop condition to I2C bus */
i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT )) {
while ((I2C_CTL0(I2C0) & 0x0200) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {

14
source/Core/BSP/Pine64/IRQ.cpp
View File

@@ -67,26 +67,26 @@ static bool fastPWM;
static void switchToFastPWM(void) {
fastPWM = true;
totalPWM = powerPWM + tempMeasureTicks * 2;
TIMER_CAR(TIMER1) = (uint32_t) totalPWM;
TIMER_CAR(TIMER1) = (uint32_t)totalPWM;
// ~3.5 Hz rate
TIMER_CH0CV(TIMER1) = powerPWM + holdoffTicks * 2;
// 1 kHz tick rate
TIMER_PSC(TIMER1) = 12000;
/* generate an update event */
TIMER_SWEVG(TIMER1) |= (uint32_t) TIMER_SWEVG_UPG;
TIMER_SWEVG(TIMER1) |= (uint32_t)TIMER_SWEVG_UPG;
}
static void switchToSlowPWM(void) {
fastPWM = false;
totalPWM = powerPWM + tempMeasureTicks;
TIMER_CAR(TIMER1) = (uint32_t) totalPWM;
TIMER_CAR(TIMER1) = (uint32_t)totalPWM;
// ~1.84 Hz rate
TIMER_CH0CV(TIMER1) = powerPWM + holdoffTicks;
// 500 Hz tick rate
TIMER_PSC(TIMER1) = 24000;
/* generate an update event */
TIMER_SWEVG(TIMER1) |= (uint32_t) TIMER_SWEVG_UPG;
TIMER_SWEVG(TIMER1) |= (uint32_t)TIMER_SWEVG_UPG;
}
bool tryBetterPWM(uint8_t pwm) {
@@ -119,8 +119,6 @@ void EXTI5_9_IRQHandler(void) {
}
// These are unused for now
void I2C0_EV_IRQHandler(void) {
}
void I2C0_EV_IRQHandler(void) {}
void I2C0_ER_IRQHandler(void) {
}
void I2C0_ER_IRQHandler(void) {}

10
source/Core/BSP/Pine64/Power.cpp
View File

@@ -1,18 +1,18 @@
#include "BSP.h"
#include "BSP_Power.h"
#include "Model_Config.h"
#include "Pins.h"
#include "QC3.h"
#include "Settings.h"
#include "Pins.h"
#include "fusbpd.h"
#include "Model_Config.h"
#include "policy_engine.h"
#include "int_n.h"
#include "policy_engine.h"
bool FUSB302_present = false;
void power_check() {
#ifdef POW_PD
if (FUSB302_present) {
//Cant start QC until either PD works or fails
// Cant start QC until either PD works or fails
if (PolicyEngine::setupCompleteOrTimedOut() == false) {
return;
}
@@ -35,7 +35,7 @@ uint8_t usb_pd_detect() {
}
bool getIsPoweredByDCIN() {
//We return false until we are sure we are not using PD
// We return false until we are sure we are not using PD
if (PolicyEngine::setupCompleteOrTimedOut() == false) {
return false;
}

22
source/Core/BSP/Pine64/QC_GPIO.cpp
View File

@@ -4,11 +4,11 @@
* Created on: 29 May 2020
* Author: Ralim
*/
#include "gd32vf103_libopt.h"
#include "BSP.h"
#include "Pins.h"
#include "QC3.h"
#include "Settings.h"
#include "gd32vf103_libopt.h"
#ifdef POW_QC
void QC_DPlusZero_Six() {
@@ -18,7 +18,6 @@ void QC_DPlusZero_Six() {
void QC_DNegZero_Six() {
gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin);
gpio_bit_reset(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin);
}
void QC_DPlusThree_Three() {
// pull up D+
@@ -28,29 +27,22 @@ void QC_DNegThree_Three() {
gpio_bit_set(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin);
gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin);
}
void QC_DM_PullDown() {
gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, USB_DM_Pin);
}
void QC_DM_No_PullDown() {
gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_2MHZ, USB_DM_Pin);
}
void QC_DM_PullDown() { gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, USB_DM_Pin); }
void QC_DM_No_PullDown() { gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_2MHZ, USB_DM_Pin); }
void QC_Init_GPIO() {
// Setup any GPIO into the right states for QC
//D+ pulldown as output
// D+ pulldown as output
gpio_init(QC_DP_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DP_LOW_Pin);
//Make two D- pins floating
// Make two D- pins floating
QC_DM_PullDown();
}
void QC_Post_Probe_En() {
//Make two D- pins outputs
// Make two D- pins outputs
gpio_init(QC_DM_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_LOW_Pin);
gpio_init(QC_DM_HIGH_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_HIGH_Pin);
}
uint8_t QC_DM_PulledDown() {
return gpio_input_bit_get(USB_DM_LOW_GPIO_Port, USB_DM_Pin) == RESET ? 1 : 0;
}
uint8_t QC_DM_PulledDown() { return gpio_input_bit_get(USB_DM_LOW_GPIO_Port, USB_DM_Pin) == RESET ? 1 : 0; }
#endif
void QC_resync() {
#ifdef POW_QC

64
source/Core/BSP/Pine64/Setup.cpp
View File

@@ -11,8 +11,7 @@
#include <string.h>
#define ADC_NORM_CHANNELS 2
#define ADC_NORM_SAMPLES 32
uint16_t ADCReadings[ADC_NORM_SAMPLES *
ADC_NORM_CHANNELS]; // room for 32 lots of the pair of readings
uint16_t ADCReadings[ADC_NORM_SAMPLES * ADC_NORM_CHANNELS]; // room for 32 lots of the pair of readings
// Functions
void setup_gpio();
@@ -59,21 +58,16 @@ void setup_gpio() {
gpio_init(KEY_A_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_A_Pin);
gpio_init(KEY_B_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_B_Pin);
// OLED reset as output
gpio_init(OLED_RESET_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ,
OLED_RESET_Pin);
gpio_init(OLED_RESET_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, OLED_RESET_Pin);
gpio_bit_set(SDA_GPIO_Port, SDA_Pin);
gpio_bit_set(SDA_GPIO_Port, SCL_Pin);
// I2C as AF Open Drain
gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_2MHZ,
SDA_Pin | SCL_Pin);
gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_2MHZ, SDA_Pin | SCL_Pin);
// PWM output as AF Push Pull
gpio_init(PWM_Out_GPIO_Port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ,
PWM_Out_Pin);
gpio_init(PWM_Out_GPIO_Port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, PWM_Out_Pin);
// Analog Inputs ... as analog inputs
gpio_init(TMP36_INPUT_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ,
TMP36_INPUT_Pin);
gpio_init(TIP_TEMP_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ,
TIP_TEMP_Pin);
gpio_init(TMP36_INPUT_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, TMP36_INPUT_Pin);
gpio_init(TIP_TEMP_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, TIP_TEMP_Pin);
gpio_init(VIN_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, VIN_Pin);
// Remap PB4 away from JTAG NJRST
@@ -94,9 +88,9 @@ void setup_dma() {
dma_deinit(DMA0, DMA_CH0);
/* initialize DMA data mode */
dma_data_parameter.periph_addr = (uint32_t) (&ADC_RDATA(ADC0));
dma_data_parameter.periph_addr = (uint32_t)(&ADC_RDATA(ADC0));
dma_data_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
dma_data_parameter.memory_addr = (uint32_t) (ADCReadings);
dma_data_parameter.memory_addr = (uint32_t)(ADCReadings);
dma_data_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_data_parameter.periph_width = DMA_PERIPHERAL_WIDTH_16BIT;
dma_data_parameter.memory_width = DMA_MEMORY_WIDTH_16BIT;
@@ -160,21 +154,15 @@ void setup_adc() {
adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 4);
adc_channel_length_config(ADC1, ADC_INSERTED_CHANNEL, 4);
for (int rank = 0; rank < 4; rank++) {
adc_inserted_channel_config(ADC0, rank, TIP_TEMP_ADC0_CHANNEL,
ADC_SAMPLETIME_1POINT5);
adc_inserted_channel_config(ADC1, rank, TIP_TEMP_ADC1_CHANNEL,
ADC_SAMPLETIME_1POINT5);
adc_inserted_channel_config(ADC0, rank, TIP_TEMP_ADC0_CHANNEL, ADC_SAMPLETIME_1POINT5);
adc_inserted_channel_config(ADC1, rank, TIP_TEMP_ADC1_CHANNEL, ADC_SAMPLETIME_1POINT5);
}
// Setup timer 1 channel 0 to trigger injected measurements
adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL,
ADC0_1_EXTTRIG_INSERTED_T1_CH0);
adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL,
ADC0_1_EXTTRIG_INSERTED_T1_CH0);
adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_T1_CH0);
adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_T1_CH0);
adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL,
ADC0_1_EXTTRIG_REGULAR_NONE);
adc_external_trigger_source_config(ADC1, ADC_REGULAR_CHANNEL,
ADC0_1_EXTTRIG_REGULAR_NONE);
adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE);
adc_external_trigger_source_config(ADC1, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE);
// Enable triggers for the ADC
adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE);
adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ENABLE);
@@ -229,12 +217,9 @@ void setup_timers() {
timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocintpara);
timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0,
powerPWM + holdoffTicks);
timer_channel_output_mode_config(TIMER1, TIMER_CH_0,
TIMER_OC_MODE_PWM1);
timer_channel_output_shadow_config(TIMER1, TIMER_CH_0,
TIMER_OC_SHADOW_DISABLE);
timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, powerPWM + holdoffTicks);
timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_PWM1);
timer_channel_output_shadow_config(TIMER1, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE);
/* CH1 used for irq */
timer_channel_output_struct_para_init(&timer_ocintpara);
timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH;
@@ -242,10 +227,8 @@ void setup_timers() {
timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocintpara);
timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 0);
timer_channel_output_mode_config(TIMER1, TIMER_CH_1,
TIMER_OC_MODE_PWM0);
timer_channel_output_shadow_config(TIMER1, TIMER_CH_1,
TIMER_OC_SHADOW_DISABLE);
timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_PWM0);
timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE);
// IRQ
timer_interrupt_enable(TIMER1, TIMER_INT_UP);
timer_interrupt_enable(TIMER1, TIMER_INT_CH1);
@@ -276,10 +259,8 @@ void setup_timers() {
timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
timer_channel_output_config(TIMER2, TIMER_CH_0, &timer_ocintpara);
timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0);
timer_channel_output_mode_config(TIMER2, TIMER_CH_0,
TIMER_OC_MODE_PWM0);
timer_channel_output_shadow_config(TIMER2, TIMER_CH_0,
TIMER_OC_SHADOW_DISABLE);
timer_channel_output_mode_config(TIMER2, TIMER_CH_0, TIMER_OC_MODE_PWM0);
timer_channel_output_shadow_config(TIMER2, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE);
timer_auto_reload_shadow_enable(TIMER2);
timer_enable(TIMER2);
}
@@ -292,8 +273,7 @@ void setup_iwdg() {
void setupFUSBIRQ() {
// Setup IRQ for USB-PD
gpio_init(FUSB302_IRQ_GPIO_Port, GPIO_MODE_IPU, GPIO_OSPEED_2MHZ,
FUSB302_IRQ_Pin);
gpio_init(FUSB302_IRQ_GPIO_Port, GPIO_MODE_IPU, GPIO_OSPEED_2MHZ, FUSB302_IRQ_Pin);
eclic_irq_enable(EXTI5_9_IRQn, 1, 1);
/* connect key EXTI line to key GPIO pin */
gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOB, GPIO_PIN_SOURCE_5);

198
source/Core/BSP/Pine64/Vendor/OS/FreeRTOS/Source/portable/GCC/port.c vendored
View File

@@ -30,58 +30,58 @@
*----------------------------------------------------------*/
/* Scheduler includes. */
#include <stdio.h>
#include "FreeRTOS.h"
#include "task.h"
#include <stdio.h>
//#define ENABLE_KERNEL_DEBUG
#ifdef ENABLE_KERNEL_DEBUG
#define FREERTOS_PORT_DEBUG(...) printf(__VA_ARGS__)
#define FREERTOS_PORT_DEBUG(...) printf(__VA_ARGS__)
#else
#define FREERTOS_PORT_DEBUG(...)
#define FREERTOS_PORT_DEBUG(...)
#endif
#ifndef configSYSTICK_CLOCK_HZ
#define configSYSTICK_CLOCK_HZ SOC_TIMER_FREQ
#define configSYSTICK_CLOCK_HZ SOC_TIMER_FREQ
#endif
#ifndef configKERNEL_INTERRUPT_PRIORITY
#define configKERNEL_INTERRUPT_PRIORITY 0
#define configKERNEL_INTERRUPT_PRIORITY 0
#endif
#ifndef configMAX_SYSCALL_INTERRUPT_PRIORITY
// See function prvCheckMaxSysCallPrio and prvCalcMaxSysCallMTH
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 255
// See function prvCheckMaxSysCallPrio and prvCalcMaxSysCallMTH
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 255
#endif
/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER ( 18 )
#define portFIRST_USER_INTERRUPT_NUMBER (18)
#define SYSTICK_TICK_CONST (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ)
/* Masks off all bits but the ECLIC MTH bits in the MTH register. */
#define portMTH_MASK ( 0xFFUL )
#define portMTH_MASK (0xFFUL)
/* Constants required to set up the initial stack. */
#define portINITIAL_MSTATUS ( MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL)
#define portINITIAL_EXC_RETURN ( 0xfffffffd )
#define portINITIAL_MSTATUS (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL)
#define portINITIAL_EXC_RETURN (0xfffffffd)
/* The systick is a 64-bit counter. */
#define portMAX_BIT_NUMBER ( SysTimer_MTIMER_Msk )
#define portMAX_BIT_NUMBER (SysTimer_MTIMER_Msk)
/* A fiddle factor to estimate the number of SysTick counts that would have
occurred while the SysTick counter is stopped during tickless idle
calculations. */
#define portMISSED_COUNTS_FACTOR ( 45UL )
#define portMISSED_COUNTS_FACTOR (45UL)
/* Let the user override the pre-loading of the initial LR with the address of
prvTaskExitError() in case it messes up unwinding of the stack in the
debugger. */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
#define portTASK_RETURN_ADDRESS prvTaskExitError
#define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/*
@@ -89,22 +89,22 @@ debugger. */
* file is weak to allow application writers to change the timer used to
* generate the tick interrupt.
*/
void vPortSetupTimerInterrupt( void );
void vPortSetupTimerInterrupt(void);
/*
* Exception handlers.
*/
void xPortSysTickHandler( void );
void xPortSysTickHandler(void);
/*
* Start first task is a separate function so it can be tested in isolation.
*/
extern void prvPortStartFirstTask( void ) __attribute__ (( naked ));
extern void prvPortStartFirstTask(void) __attribute__((naked));
/*
* Used to catch tasks that attempt to return from their implementing function.
*/
static void prvTaskExitError( void );
static void prvTaskExitError(void);
#define xPortSysTickHandler eclic_mtip_handler
@@ -133,24 +133,24 @@ uint8_t uxMaxSysCallMTH = 255;
/*
* The number of SysTick increments that make up one tick period.
*/
#if( configUSE_TICKLESS_IDLE == 1 )
static TickType_t ulTimerCountsForOneTick = 0;
#if (configUSE_TICKLESS_IDLE == 1)
static TickType_t ulTimerCountsForOneTick = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
* The maximum number of tick periods that can be suppressed is limited by the
* 24 bit resolution of the SysTick timer.
*/
#if( configUSE_TICKLESS_IDLE == 1 )
static TickType_t xMaximumPossibleSuppressedTicks = 0;
#if (configUSE_TICKLESS_IDLE == 1)
static TickType_t xMaximumPossibleSuppressedTicks = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
* Compensate for the CPU cycles that pass while the SysTick is stopped (low
* power functionality only.
*/
#if( configUSE_TICKLESS_IDLE == 1 )
static TickType_t ulStoppedTimerCompensation = 0;
#if (configUSE_TICKLESS_IDLE == 1)
static TickType_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
/*
@@ -158,8 +158,8 @@ uint8_t uxMaxSysCallMTH = 255;
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
#if( configASSERT_DEFINED == 1 )
static uint8_t ucMaxSysCallPriority = 0;
#if (configASSERT_DEFINED == 1)
static uint8_t ucMaxSysCallPriority = 0;
#endif /* configASSERT_DEFINED */
/*-----------------------------------------------------------*/
@@ -223,8 +223,7 @@ uint8_t uxMaxSysCallMTH = 255;
* portTASK_RETURN_ADDRESS
* pxCode
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) {
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
@@ -239,19 +238,18 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
#else
pxTopOfStack -= 6; /* X11 - X15. */
#endif
*pxTopOfStack = ( StackType_t ) pvParameters; /* X10/A0 */
*pxTopOfStack = (StackType_t)pvParameters; /* X10/A0 */
pxTopOfStack -= 6; /* X5 - X9 */
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* RA, X1 */
*pxTopOfStack = (StackType_t)portTASK_RETURN_ADDRESS; /* RA, X1 */
pxTopOfStack --;
*pxTopOfStack = ( ( StackType_t ) pxCode ) ; /* PC */
pxTopOfStack--;
*pxTopOfStack = ((StackType_t)pxCode); /* PC */
return pxTopOfStack;
}
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
static void prvTaskExitError(void) {
volatile uint32_t ulDummy = 0;
/* A function that implements a task must not exit or attempt to return to
@@ -260,10 +258,9 @@ static void prvTaskExitError( void )
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
configASSERT(uxCriticalNesting == ~0UL);
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
{
while (ulDummy == 0) {
/* This file calls prvTaskExitError() after the scheduler has been
started to remove a compiler warning about the function being defined
but never called. ulDummy is used purely to quieten other warnings
@@ -277,8 +274,7 @@ static void prvTaskExitError( void )
}
/*-----------------------------------------------------------*/
static uint8_t prvCheckMaxSysCallPrio( uint8_t max_syscall_prio )
{
static uint8_t prvCheckMaxSysCallPrio(uint8_t max_syscall_prio) {
uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t intctlbits = __ECLIC_INTCTLBITS;
uint8_t lvlbits, temp;
@@ -289,15 +285,14 @@ static uint8_t prvCheckMaxSysCallPrio( uint8_t max_syscall_prio )
lvlbits = intctlbits;
}
temp = ((1<<lvlbits) - 1);
temp = ((1 << lvlbits) - 1);
if (max_syscall_prio > temp) {
max_syscall_prio = temp;
}
return max_syscall_prio;
}
static uint8_t prvCalcMaxSysCallMTH( uint8_t max_syscall_prio )
{
static uint8_t prvCalcMaxSysCallMTH(uint8_t max_syscall_prio) {
uint8_t nlbits = __ECLIC_GetCfgNlbits();
uint8_t intctlbits = __ECLIC_INTCTLBITS;
uint8_t lvlbits, lfabits;
@@ -312,12 +307,12 @@ static uint8_t prvCalcMaxSysCallMTH( uint8_t max_syscall_prio )
lfabits = 8 - lvlbits;
temp = ((1<<lvlbits) - 1);
temp = ((1 << lvlbits) - 1);
if (max_syscall_prio > temp) {
max_syscall_prio = temp;
}
maxsyscallmth = (max_syscall_prio << lfabits) | ((1<<lfabits) - 1);
maxsyscallmth = (max_syscall_prio << lfabits) | ((1 << lfabits) - 1);
return maxsyscallmth;
}
@@ -325,22 +320,21 @@ static uint8_t prvCalcMaxSysCallMTH( uint8_t max_syscall_prio )
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
BaseType_t xPortStartScheduler(void) {
/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. */
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
configASSERT(configMAX_SYSCALL_INTERRUPT_PRIORITY);
/* Get the real MTH should be set to ECLIC MTH register */
uxMaxSysCallMTH = prvCalcMaxSysCallMTH(configMAX_SYSCALL_INTERRUPT_PRIORITY);
FREERTOS_PORT_DEBUG("Max SysCall MTH is set to 0x%x\n", uxMaxSysCallMTH);
#if( configASSERT_DEFINED == 1 )
#if (configASSERT_DEFINED == 1)
{
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = prvCheckMaxSysCallPrio(configMAX_SYSCALL_INTERRUPT_PRIORITY);
FREERTOS_PORT_DEBUG("Max SysCall Priority is set to %d\n", ucMaxSysCallPriority);
}
#endif /* conifgASSERT_DEFINED */
#endif /* conifgASSERT_DEFINED */
__disable_irq();
/* Start the timer that generates the tick ISR. Interrupts are disabled
@@ -367,16 +361,14 @@ BaseType_t xPortStartScheduler( void )
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
void vPortEndScheduler(void) {
/* Not implemented in ports where there is nothing to return to.
Artificially force an assert. */
configASSERT( uxCriticalNesting == 1000UL );
configASSERT(uxCriticalNesting == 1000UL);
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
void vPortEnterCritical(void) {
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
@@ -385,26 +377,22 @@ void vPortEnterCritical( void )
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
{
configASSERT( ( __ECLIC_GetMth() & portMTH_MASK ) == uxMaxSysCallMTH );
if (uxCriticalNesting == 1) {
configASSERT((__ECLIC_GetMth() & portMTH_MASK) == uxMaxSysCallMTH);
}
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
configASSERT( uxCriticalNesting );
void vPortExitCritical(void) {
configASSERT(uxCriticalNesting);
uxCriticalNesting--;
if( uxCriticalNesting == 0 )
{
if (uxCriticalNesting == 0) {
portENABLE_INTERRUPTS();
}
}
/*-----------------------------------------------------------*/
void vPortAssert( int32_t x )
{
void vPortAssert(int32_t x) {
TaskHandle_t th;
if ((x) == 0) {
taskDISABLE_INTERRUPTS();
@@ -414,7 +402,7 @@ void vPortAssert( int32_t x )
printf("Assert in task %s\n", pcTaskGetName(th));
}
#endif
while(1) {
while (1) {
/* Sleep and wait for interrupt */
__WFI();
};
@@ -422,9 +410,7 @@ void vPortAssert( int32_t x )
}
/*-----------------------------------------------------------*/
void xPortTaskSwitch( void )
{
void xPortTaskSwitch(void) {
portDISABLE_INTERRUPTS();
/* Clear Software IRQ, A MUST */
SysTimer_ClearSWIRQ();
@@ -433,8 +419,7 @@ void xPortTaskSwitch( void )
}
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
void xPortSysTickHandler(void) {
/* The SysTick runs at the lowest interrupt priority, so when this interrupt
executes all interrupts must be unmasked. There is therefore no need to
save and then restore the interrupt mask value as its value is already
@@ -443,8 +428,7 @@ void xPortSysTickHandler( void )
{
SysTick_Reload(SYSTICK_TICK_CONST);
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
{
if (xTaskIncrementTick() != pdFALSE) {
/* A context switch is required. Context switching is performed in
the SWI interrupt. Pend the SWI interrupt. */
portYIELD();
@@ -454,18 +438,16 @@ void xPortSysTickHandler( void )
}
/*-----------------------------------------------------------*/
#if( configUSE_TICKLESS_IDLE == 1 )
#if (configUSE_TICKLESS_IDLE == 1)
__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
__attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) {
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
volatile TickType_t xModifiableIdleTime, xTickCountBeforeSleep, XLastLoadValue;
FREERTOS_PORT_DEBUG("Enter TickLess %d\n", (uint32_t)xExpectedIdleTime);
/* Make sure the SysTick reload value does not overflow the counter. */
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
{
if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks) {
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
@@ -478,9 +460,8 @@ void xPortSysTickHandler( void )
/* Calculate the reload value required to wait xExpectedIdleTime
tick periods. -1 is used because this code will execute part way
through one of the tick periods. */
ulReloadValue = ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
ulReloadValue = (ulTimerCountsForOneTick * (xExpectedIdleTime - 1UL));
if (ulReloadValue > ulStoppedTimerCompensation) {
ulReloadValue -= ulStoppedTimerCompensation;
}
@@ -490,8 +471,7 @@ void xPortSysTickHandler( void )
/* If a context switch is pending or a task is waiting for the scheduler
to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
if (eTaskConfirmSleepModeStatus() == eAbortSleep) {
/* Restart from whatever is left in the count register to complete
this tick period. */
/* Restart SysTick. */
@@ -504,9 +484,7 @@ void xPortSysTickHandler( void )
/* Re-enable interrupts - see comments above the cpsid instruction()
above. */
__enable_irq();
}
else
{
} else {
xTickCountBeforeSleep = xTaskGetTickCount();
/* Set the new reload value. */
@@ -526,12 +504,11 @@ void xPortSysTickHandler( void )
should not be executed again. However, the original expected idle
time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
{
configPRE_SLEEP_PROCESSING(xModifiableIdleTime);
if (xModifiableIdleTime > 0) {
__WFI();
}
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
configPOST_SLEEP_PROCESSING(xExpectedIdleTime);
/* Re-enable interrupts to allow the interrupt that brought the MCU
out of sleep mode to execute immediately. */
@@ -558,22 +535,19 @@ void xPortSysTickHandler( void )
/* Determine if SysTimer Interrupt is not yet happened,
(in which case an interrupt other than the SysTick
must have brought the system out of sleep mode). */
if (SysTimer_GetLoadValue() >= (XLastLoadValue + ulReloadValue))
{
if (SysTimer_GetLoadValue() >= (XLastLoadValue + ulReloadValue)) {
/* As the pending tick will be processed as soon as this
function exits, the tick value maintained by the tick is stepped
forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
FREERTOS_PORT_DEBUG("TickLess - SysTimer Interrupt Entered!\n");
}
else
{
} else {
/* Something other than the tick interrupt ended the sleep.
Work out how long the sleep lasted rounded to complete tick
periods (not the ulReload value which accounted for part
ticks). */
xModifiableIdleTime = SysTimer_GetLoadValue();
if ( xModifiableIdleTime > XLastLoadValue ) {
if (xModifiableIdleTime > XLastLoadValue) {
ulCompletedSysTickDecrements = (xModifiableIdleTime - XLastLoadValue);
} else {
ulCompletedSysTickDecrements = (xModifiableIdleTime + portMAX_BIT_NUMBER - XLastLoadValue);
@@ -592,13 +566,13 @@ void xPortSysTickHandler( void )
FREERTOS_PORT_DEBUG("End TickLess %d\n", (uint32_t)ulCompleteTickPeriods);
/* Restart SysTick */
vTaskStepTick( ulCompleteTickPeriods );
vTaskStepTick(ulCompleteTickPeriods);
/* Exit with interrupts enabled. */
ECLIC_EnableIRQ(SysTimer_IRQn);
__enable_irq();
}
}
}
#endif /* #if configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/
@@ -607,18 +581,17 @@ void xPortSysTickHandler( void )
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
/* Calculate the constants required to configure the tick interrupt. */
#if( configUSE_TICKLESS_IDLE == 1 )
__attribute__((weak)) void vPortSetupTimerInterrupt(void) {
/* Calculate the constants required to configure the tick interrupt. */
#if (configUSE_TICKLESS_IDLE == 1)
{
ulTimerCountsForOneTick = ( SYSTICK_TICK_CONST );
ulTimerCountsForOneTick = (SYSTICK_TICK_CONST);
xMaximumPossibleSuppressedTicks = portMAX_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
FREERTOS_PORT_DEBUG("CountsForOneTick, SuppressedTicks and TimerCompensation: %u, %u, %u\n", \
(uint32_t)ulTimerCountsForOneTick, (uint32_t)xMaximumPossibleSuppressedTicks, (uint32_t)ulStoppedTimerCompensation);
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / (configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ);
FREERTOS_PORT_DEBUG("CountsForOneTick, SuppressedTicks and TimerCompensation: %u, %u, %u\n", (uint32_t)ulTimerCountsForOneTick, (uint32_t)xMaximumPossibleSuppressedTicks,
(uint32_t)ulStoppedTimerCompensation);
}
#endif /* configUSE_TICKLESS_IDLE */
#endif /* configUSE_TICKLESS_IDLE */
TickType_t ticks = SYSTICK_TICK_CONST;
/* Make SWI and SysTick the lowest priority interrupts. */
@@ -638,10 +611,9 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
#if (configASSERT_DEFINED == 1)
void vPortValidateInterruptPriority( void )
{
void vPortValidateInterruptPriority(void) {
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
@@ -652,7 +624,7 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
if (mcause.b.interrupt) {
ulCurrentInterrupt = mcause.b.exccode;
/* Is the interrupt number a user defined interrupt? */
if ( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) {
if (ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER) {
/* Look up the interrupt's priority. */
ucCurrentPriority = __ECLIC_GetLevelIRQ(ulCurrentInterrupt);
/* The following assertion will fail if a service routine (ISR) for
@@ -677,9 +649,9 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
The following links provide detailed information:
http://www.freertos.org/FAQHelp.html */
configASSERT( ucCurrentPriority <= ucMaxSysCallPriority );
}
configASSERT(ucCurrentPriority <= ucMaxSysCallPriority);
}
}
}
#endif /* configASSERT_DEFINED */

7
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Board/pinecil/Source/gd32vf103v_eval.c vendored
View File

@@ -32,8 +32,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
OF SUCH DAMAGE.
*/
#include "nuclei_sdk_hal.h"
#include "gd32vf103_usart.h"
#include "gd32vf103_gpio.h"
#include "gd32vf103_exti.h"
#include "gd32vf103_gpio.h"
#include "gd32vf103_usart.h"
#include "nuclei_sdk_hal.h"

70
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_core.c vendored
View File

@@ -41,13 +41,13 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
static void usb_core_reset (usb_core_regs *usb_regs)
{
static void usb_core_reset(usb_core_regs *usb_regs) {
/* enable core soft reset */
usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST;
/* wait for the core to be soft reset */
while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST);
while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST)
;
/* wait for addtional 3 PHY clocks */
usb_udelay(3);
@@ -61,10 +61,7 @@ static void usb_core_reset (usb_core_regs *usb_regs)
\param[out] none
\retval operation status
*/
usb_status usb_basic_init (usb_core_basic *usb_basic,
usb_core_regs *usb_regs,
usb_core_enum usb_core)
{
usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core) {
uint32_t i = 0, reg_base = 0;
/* config USB default transfer mode as FIFO mode */
@@ -117,31 +114,25 @@ usb_status usb_basic_init (usb_core_basic *usb_basic,
usb_basic->low_power = USB_LOW_POWER;
/* assign main registers address */
*usb_regs = (usb_core_regs) {
.gr = (usb_gr*) (reg_base + USB_REG_OFFSET_CORE),
.hr = (usb_hr*) (reg_base + USB_REG_OFFSET_HOST),
.dr = (usb_dr*) (reg_base + USB_REG_OFFSET_DEV),
*usb_regs = (usb_core_regs){.gr = (usb_gr *)(reg_base + USB_REG_OFFSET_CORE),
.hr = (usb_hr *)(reg_base + USB_REG_OFFSET_HOST),
.dr = (usb_dr *)(reg_base + USB_REG_OFFSET_DEV),
.HPCS = (uint32_t*) (reg_base + USB_REG_OFFSET_PORT),
.PWRCLKCTL = (uint32_t*) (reg_base + USB_REG_OFFSET_PWRCLKCTL)
};
.HPCS = (uint32_t *)(reg_base + USB_REG_OFFSET_PORT),
.PWRCLKCTL = (uint32_t *)(reg_base + USB_REG_OFFSET_PWRCLKCTL)};
/* assign device endpoint registers address */
for (i = 0; i < usb_basic->num_ep; i++) {
usb_regs->er_in[i] = (usb_erin *) \
(reg_base + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP));
usb_regs->er_in[i] = (usb_erin *)(reg_base + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP));
usb_regs->er_out[i] = (usb_erout *)\
(reg_base + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP));
usb_regs->er_out[i] = (usb_erout *)(reg_base + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP));
}
/* assign host pipe registers address */
for (i = 0; i < usb_basic->num_pipe; i++) {
usb_regs->pr[i] = (usb_pr *) \
(reg_base + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH));
usb_regs->pr[i] = (usb_pr *)(reg_base + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH));
usb_regs->DFIFO[i] = (uint32_t *) \
(reg_base + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE));
usb_regs->DFIFO[i] = (uint32_t *)(reg_base + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE));
}
return USB_OK;
@@ -155,8 +146,7 @@ usb_status usb_basic_init (usb_core_basic *usb_basic,
\param[out] none
\retval operation status
*/
usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
{
usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs) {
uint32_t reg_value = usb_regs->gr->GCCFG;
/* disable USB global interrupt */
@@ -183,12 +173,12 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
#endif
/* soft reset the core */
usb_core_reset (usb_regs);
usb_core_reset(usb_regs);
} else {
usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY;
/* soft reset the core */
usb_core_reset (usb_regs);
usb_core_reset(usb_regs);
/* active the transceiver and enable vbus sensing */
reg_value = GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN;
@@ -221,8 +211,7 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
/* enable the USB wakeup and suspend interrupts */
usb_regs->gr->GINTF = 0xBFFFFFFFU;
usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \
GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE;
usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE;
#endif /* USE_OTG_MODE */
@@ -238,17 +227,13 @@ usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs)
\param[out] none
\retval operation status
*/
usb_status usb_txfifo_write (usb_core_regs *usb_regs,
uint8_t *src_buf,
uint8_t fifo_num,
uint16_t byte_count)
{
usb_status usb_txfifo_write(usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count) {
uint32_t word_count = (byte_count + 3U) / 4U;
__IO uint32_t *fifo = usb_regs->DFIFO[fifo_num];
while (word_count-- > 0) {
*fifo = *(( uint32_t *)src_buf);
*fifo = *((uint32_t *)src_buf);
src_buf += 4U;
}
@@ -264,14 +249,13 @@ usb_status usb_txfifo_write (usb_core_regs *usb_regs,
\param[out] none
\retval void type pointer
*/
void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count)
{
void *usb_rxfifo_read(usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count) {
uint32_t word_count = (byte_count + 3U) / 4U;
__IO uint32_t *fifo = usb_regs->DFIFO[0];
while (word_count-- > 0) {
*( uint32_t *)dest_buf = *fifo;
*(uint32_t *)dest_buf = *fifo;
dest_buf += 4U;
}
@@ -286,12 +270,12 @@ void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte
\param[out] none
\retval operation status
*/
usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num)
{
usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num) {
usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF;
/* wait for Tx FIFO flush bit is set */
while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF);
while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF)
;
/* wait for 3 PHY clocks*/
usb_udelay(3);
@@ -305,12 +289,12 @@ usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num)
\param[out] none
\retval operation status
*/
usb_status usb_rxfifo_flush (usb_core_regs *usb_regs)
{
usb_status usb_rxfifo_flush(usb_core_regs *usb_regs) {
usb_regs->gr->GRSTCTL = GRSTCTL_RXFF;
/* wait for Rx FIFO flush bit is set */
while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF);
while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF)
;
/* wait for 3 PHY clocks */
usb_udelay(3);

138
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_dev.c vendored
View File

@@ -31,41 +31,23 @@ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWIS
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32vf103_libopt.h"
#include "drv_usb_hw.h"
#include "drv_usb_core.h"
#include "drv_usb_dev.h"
#include "drv_usb_core.h"
#include "drv_usb_hw.h"
#include "gd32vf103_libopt.h"
/* endpoint 0 max packet length */
static const uint8_t EP0_MAXLEN[4] = {
[DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64,
[DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64,
[DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64,
[DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8
};
static const uint8_t EP0_MAXLEN[4] = {[DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64, [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64, [DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64, [DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8};
#ifdef USB_FS_CORE
/* USB endpoint Tx FIFO size */
static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] =
{
(uint16_t)TX0_FIFO_FS_SIZE,
(uint16_t)TX1_FIFO_FS_SIZE,
(uint16_t)TX2_FIFO_FS_SIZE,
(uint16_t)TX3_FIFO_FS_SIZE
};
static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = {(uint16_t)TX0_FIFO_FS_SIZE, (uint16_t)TX1_FIFO_FS_SIZE, (uint16_t)TX2_FIFO_FS_SIZE, (uint16_t)TX3_FIFO_FS_SIZE};
#elif defined(USB_HS_CORE)
uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] =
{
(uint16_t)TX0_FIFO_HS_SIZE,
(uint16_t)TX1_FIFO_HS_SIZE,
(uint16_t)TX2_FIFO_HS_SIZE,
(uint16_t)TX3_FIFO_HS_SIZE,
(uint16_t)TX4_FIFO_HS_SIZE,
(uint16_t)TX5_FIFO_HS_SIZE
};
uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT]
= {(uint16_t)TX0_FIFO_HS_SIZE, (uint16_t)TX1_FIFO_HS_SIZE, (uint16_t)TX2_FIFO_HS_SIZE, (uint16_t)TX3_FIFO_HS_SIZE, (uint16_t)TX4_FIFO_HS_SIZE, (uint16_t)TX5_FIFO_HS_SIZE};
#endif /* USBFS_CORE */
@@ -75,8 +57,7 @@ uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] =
\param[out] none
\retval operation status
*/
usb_status usb_devcore_init (usb_core_driver *udev)
{
usb_status usb_devcore_init(usb_core_driver *udev) {
uint32_t i, ram_addr = 0;
/* force to peripheral mode */
@@ -102,8 +83,7 @@ usb_status usb_devcore_init (usb_core_driver *udev)
udev->regs.gr->GRFLEN = RX_FIFO_FS_SIZE;
/* set endpoint 0 Tx FIFO length and RAM address */
udev->regs.gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)TX0_FIFO_FS_SIZE << 16) | \
((uint32_t)RX_FIFO_FS_SIZE);
udev->regs.gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)TX0_FIFO_FS_SIZE << 16) | ((uint32_t)RX_FIFO_FS_SIZE);
ram_addr = RX_FIFO_FS_SIZE;
@@ -111,8 +91,7 @@ usb_status usb_devcore_init (usb_core_driver *udev)
for (i = 1; i < USBFS_MAX_EP_COUNT; i++) {
ram_addr += USBFS_TX_FIFO_SIZE[i - 1];
udev->regs.gr->DIEPTFLEN[i - 1] = ((uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U) | \
ram_addr;
udev->regs.gr->DIEPTFLEN[i - 1] = ((uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U) | ram_addr;
}
}
#endif
@@ -121,7 +100,7 @@ usb_status usb_devcore_init (usb_core_driver *udev)
if (udev->bp.core == USB_CORE_HS) {
if (udev->bp.core_phy == USB_ULPI_PHY) {
udev->regs.dr->DCFG |= USB_SPEED_EXP_HIGH;
} else {/* set High speed phy in Full speed mode */
} else { /* set High speed phy in Full speed mode */
udev->regs.dr->DCFG |= USB_SPEED_EXP_FULL;
}
@@ -130,8 +109,7 @@ usb_status usb_devcore_init (usb_core_driver *udev)
udev->regs.gr->GRFLEN |= RX_FIFO_HS_SIZE;
/* Set endpoint 0 Tx FIFO length and RAM address */
udev->regs.gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)TX0_FIFO_HS_SIZE << 16) | \
RX_FIFO_HS_SIZE;
udev->regs.gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)TX0_FIFO_HS_SIZE << 16) | RX_FIFO_HS_SIZE;
ram_addr = RX_FIFO_HS_SIZE;
@@ -139,8 +117,7 @@ usb_status usb_devcore_init (usb_core_driver *udev)
for (i = 1; i < USBHS_MAX_EP_COUNT; i++) {
ram_addr += USBHS_TX_FIFO_SIZE[i - 1];
udev->regs.gr->DIEPTFLEN[i - 1] = ((uint32_t)USBHS_TX_FIFO_SIZE[i] << 16) | \
ram_addr;
udev->regs.gr->DIEPTFLEN[i - 1] = ((uint32_t)USBHS_TX_FIFO_SIZE[i] << 16) | ram_addr;
}
}
#endif
@@ -148,10 +125,10 @@ usb_status usb_devcore_init (usb_core_driver *udev)
/* make sure all FIFOs are flushed */
/* flush all Tx FIFOs */
usb_txfifo_flush (&udev->regs, 0x10);
usb_txfifo_flush(&udev->regs, 0x10);
/* flush entire Rx FIFO */
usb_rxfifo_flush (&udev->regs);
usb_rxfifo_flush(&udev->regs);
/* clear all pending device interrupts */
udev->regs.dr->DIEPINTEN = 0U;
@@ -186,7 +163,7 @@ usb_status usb_devcore_init (usb_core_driver *udev)
udev->regs.er_out[i]->DOEPINTF = 0xFFU;
}
usb_devint_enable (udev);
usb_devint_enable(udev);
return USB_OK;
}
@@ -197,8 +174,7 @@ usb_status usb_devcore_init (usb_core_driver *udev)
\param[out] none
\retval operation status
*/
usb_status usb_devint_enable (usb_core_driver *udev)
{
usb_status usb_devint_enable(usb_core_driver *udev) {
/* clear any pending USB OTG interrupts */
udev->regs.gr->GOTGINTF = 0xFFFFFFFFU;
@@ -212,8 +188,7 @@ usb_status usb_devint_enable (usb_core_driver *udev)
if (USB_USE_FIFO == udev->bp.transfer_mode) {
udev->regs.gr->GINTEN |= GINTEN_RXFNEIE;
}
udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE |\
GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_MFIE;
udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_MFIE;
#ifdef VBUS_SENSING_ENABLED
udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE;
@@ -231,10 +206,7 @@ usb_status usb_devint_enable (usb_core_driver *udev)
\param[out] none
\retval operation status
*/
void usb_dev_disconnect (usb_core_driver *udev)
{
udev->regs.dr->DCTL |= DCTL_SD;
}
void usb_dev_disconnect(usb_core_driver *udev) { udev->regs.dr->DCTL |= DCTL_SD; }
/*!
\brief config the USB device to be connected
@@ -242,10 +214,7 @@ void usb_dev_disconnect (usb_core_driver *udev)
\param[out] none
\retval operation status
*/
void usb_dev_connect (usb_core_driver *udev)
{
udev->regs.dr->DCTL &= ~DCTL_SD;
}
void usb_dev_connect(usb_core_driver *udev) { udev->regs.dr->DCTL &= ~DCTL_SD; }
/*!
\brief set the USB device address
@@ -254,8 +223,7 @@ void usb_dev_connect (usb_core_driver *udev)
\param[out] none
\retval operation status
*/
void usb_devaddr_set (usb_core_driver *udev, uint8_t dev_addr)
{
void usb_devaddr_set(usb_core_driver *udev, uint8_t dev_addr) {
udev->regs.dr->DCFG &= ~DCFG_DAR;
udev->regs.dr->DCFG |= dev_addr << 4;
}
@@ -267,8 +235,7 @@ void usb_devaddr_set (usb_core_driver *udev, uint8_t dev_addr)
\param[out] none
\retval status
*/
usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc)
{
usb_status usb_transc_active(usb_core_driver *udev, usb_transc *transc) {
__IO uint32_t *reg_addr = NULL;
__IO uint32_t epinten = 0U;
@@ -305,8 +272,7 @@ usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc)
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
if ((ep_num == 1) && (udev->bp.core == USB_HS_CORE_ID)) {
udev->regs.dr->DEP1INTEN |= epinten;
}
else
} else
#endif
{
/* enable the interrupts for this endpoint */
@@ -323,8 +289,7 @@ usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc)
\param[out] none
\retval status
*/
usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc)
{
usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc) {
uint32_t epinten = 0U;
uint8_t ep_num = transc->ep_addr.num;
@@ -343,8 +308,7 @@ usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc)
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
if ((ep_num == 1) && (udev->bp.core == USB_CORE_HS)) {
udev->regs.dr->DEP1INTEN &= ~epinten;
}
else
} else
#endif
{
/* disable the interrupts for this endpoint */
@@ -361,8 +325,7 @@ usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc)
\param[out] none
\retval status
*/
usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc)
{
usb_status usb_transc_inxfer(usb_core_driver *udev, usb_transc *transc) {
usb_status status = USB_OK;
uint8_t ep_num = transc->ep_addr.num;
@@ -419,7 +382,7 @@ usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc)
udev->regs.dr->DIEPFEINTEN |= 1 << ep_num;
}
} else {
usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, transc->xfer_len);
usb_txfifo_write(&udev->regs, transc->xfer_buf, ep_num, transc->xfer_len);
}
return status;
@@ -432,8 +395,7 @@ usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc)
\param[out] none
\retval status
*/
usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc)
{
usb_status usb_transc_outxfer(usb_core_driver *udev, usb_transc *transc) {
usb_status status = USB_OK;
uint8_t ep_num = transc->ep_addr.num;
@@ -490,8 +452,7 @@ usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc)
\param[out] none
\retval status
*/
usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc)
{
usb_status usb_transc_stall(usb_core_driver *udev, usb_transc *transc) {
__IO uint32_t *reg_addr = NULL;
uint8_t ep_num = transc->ep_addr.num;
@@ -521,8 +482,7 @@ usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc)
\param[out] none
\retval status
*/
usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc)
{
usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc) {
__IO uint32_t *reg_addr = NULL;
uint8_t ep_num = transc->ep_addr.num;
@@ -550,8 +510,7 @@ usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc)
\param[out] none
\retval none
*/
uint32_t usb_oepintnum_read (usb_core_driver *udev)
{
uint32_t usb_oepintnum_read(usb_core_driver *udev) {
uint32_t value = udev->regs.dr->DAEPINT;
value &= udev->regs.dr->DAEPINTEN;
@@ -566,8 +525,7 @@ uint32_t usb_oepintnum_read (usb_core_driver *udev)
\param[out] none
\retval none
*/
uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num)
{
uint32_t usb_oepintr_read(usb_core_driver *udev, uint8_t ep_num) {
uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF;
value &= udev->regs.dr->DOEPINTEN;
@@ -581,8 +539,7 @@ uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num)
\param[out] none
\retval none
*/
uint32_t usb_iepintnum_read (usb_core_driver *udev)
{
uint32_t usb_iepintnum_read(usb_core_driver *udev) {
uint32_t value = udev->regs.dr->DAEPINT;
value &= udev->regs.dr->DAEPINTEN;
@@ -590,7 +547,6 @@ uint32_t usb_iepintnum_read (usb_core_driver *udev)
return value & DAEPINT_IEPITB;
}
/*!
\brief read device IN endpoint interrupt flag register
\param[in] udev: pointer to usb device
@@ -598,8 +554,7 @@ uint32_t usb_iepintnum_read (usb_core_driver *udev)
\param[out] none
\retval none
*/
uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num)
{
uint32_t usb_iepintr_read(usb_core_driver *udev, uint8_t ep_num) {
uint32_t value = 0U, fifoemptymask = 0U, commonintmask = 0U;
commonintmask = udev->regs.dr->DIEPINTEN;
@@ -619,8 +574,7 @@ uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num)
\param[out] none
\retval none
*/
void usb_ctlep_startout (usb_core_driver *udev)
{
void usb_ctlep_startout(usb_core_driver *udev) {
/* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */
udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U);
@@ -638,8 +592,7 @@ void usb_ctlep_startout (usb_core_driver *udev)
\param[out] none
\retval none
*/
void usb_rwkup_set (usb_core_driver *udev)
{
void usb_rwkup_set(usb_core_driver *udev) {
if (udev->dev.pm.dev_remote_wakeup) {
/* enable remote wakeup signaling */
udev->regs.dr->DCTL |= DCTL_RWKUP;
@@ -652,8 +605,7 @@ void usb_rwkup_set (usb_core_driver *udev)
\param[out] none
\retval none
*/
void usb_rwkup_reset (usb_core_driver *udev)
{
void usb_rwkup_reset(usb_core_driver *udev) {
if (udev->dev.pm.dev_remote_wakeup) {
/* disable remote wakeup signaling */
udev->regs.dr->DCTL &= ~DCTL_RWKUP;
@@ -666,8 +618,7 @@ void usb_rwkup_reset (usb_core_driver *udev)
\param[out] none
\retval none
*/
void usb_rwkup_active (usb_core_driver *udev)
{
void usb_rwkup_active(usb_core_driver *udev) {
if (udev->dev.pm.dev_remote_wakeup) {
if (udev->regs.dr->DSTAT & DSTAT_SPST) {
if (udev->bp.low_power) {
@@ -691,8 +642,7 @@ void usb_rwkup_active (usb_core_driver *udev)
\param[out] none
\retval none
*/
void usb_clock_active (usb_core_driver *udev)
{
void usb_clock_active(usb_core_driver *udev) {
if (udev->bp.low_power) {
if (udev->regs.dr->DSTAT & DSTAT_SPST) {
/* un-gate USB Core clock */
@@ -707,8 +657,7 @@ void usb_clock_active (usb_core_driver *udev)
\param[out] none
\retval none
*/
void usb_dev_suspend (usb_core_driver *udev)
{
void usb_dev_suspend(usb_core_driver *udev) {
__IO uint32_t devstat = udev->regs.dr->DSTAT;
if ((udev->bp.low_power) && (devstat & DSTAT_SPST)) {
@@ -726,8 +675,7 @@ void usb_dev_suspend (usb_core_driver *udev)
\param[out] none
\retval none
*/
void usb_dev_stop (usb_core_driver *udev)
{
void usb_dev_stop(usb_core_driver *udev) {
uint32_t i;
udev->dev.cur_status = 1;
@@ -744,6 +692,6 @@ void usb_dev_stop (usb_core_driver *udev)
udev->regs.dr->DAEPINT = 0xFFFFFFFFU;
/* flush the FIFO */
usb_rxfifo_flush (&udev->regs);
usb_txfifo_flush (&udev->regs, 0x10);
usb_rxfifo_flush(&udev->regs);
usb_txfifo_flush(&udev->regs, 0x10);
}

92
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_host.c vendored
View File

@@ -32,45 +32,29 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
OF SUCH DAMAGE.
*/
#include "drv_usb_hw.h"
#include "drv_usb_core.h"
#include "drv_usb_host.h"
#include "drv_usb_core.h"
#include "drv_usb_hw.h"
const uint32_t PIPE_DPID[] = {
PIPE_DPID_DATA0,
PIPE_DPID_DATA1
};
const uint32_t PIPE_DPID[] = {PIPE_DPID_DATA0, PIPE_DPID_DATA1};
//__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *pudev)
uint32_t usb_frame_even (usb_core_driver *pudev)
{
return !(pudev->regs.hr->HFINFR & 0x01U);
}
uint32_t usb_frame_even(usb_core_driver *pudev) { return !(pudev->regs.hr->HFINFR & 0x01U); }
//__STATIC_INLINE void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock)
void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock)
{
void usb_phyclock_config(usb_core_driver *pudev, uint8_t clock) {
pudev->regs.hr->HCTL &= ~HCTL_CLKSEL;
pudev->regs.hr->HCTL |= clock;
}
//__STATIC_INLINE uint32_t usb_port_read (usb_core_driver *pudev)
uint32_t usb_port_read (usb_core_driver *pudev)
{
return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC);
}
uint32_t usb_port_read(usb_core_driver *pudev) { return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); }
//__STATIC_INLINE uint32_t usb_curspeed_get (usb_core_driver *pudev)
uint32_t usb_curspeed_get (usb_core_driver *pudev)
{
return *pudev->regs.HPCS & HPCS_PS;
}
uint32_t usb_curspeed_get(usb_core_driver *pudev) { return *pudev->regs.HPCS & HPCS_PS; }
uint32_t usb_curframe_get (usb_core_driver *pudev)
{
return (pudev->regs.hr->HFINFR & 0xFFFFU);
}
uint32_t usb_curframe_get(usb_core_driver *pudev) { return (pudev->regs.hr->HFINFR & 0xFFFFU); }
/*!
\brief initializes USB core for host mode
@@ -78,8 +62,7 @@ uint32_t usb_curframe_get (usb_core_driver *pudev)
\param[out] none
\retval operation status
*/
usb_status usb_host_init (usb_core_driver *pudev)
{
usb_status usb_host_init(usb_core_driver *pudev) {
uint32_t i = 0, inten = 0U;
uint32_t nptxfifolen = 0U;
@@ -93,12 +76,12 @@ usb_status usb_host_init (usb_core_driver *pudev)
/* initialize host configuration register */
if (USB_ULPI_PHY == pudev->bp.phy_itf) {
usb_phyclock_config (pudev, HCTL_30_60MHZ);
usb_phyclock_config(pudev, HCTL_30_60MHZ);
} else {
usb_phyclock_config (pudev, HCTL_48MHZ);
usb_phyclock_config(pudev, HCTL_48MHZ);
}
usb_port_reset (pudev);
usb_port_reset(pudev);
/* support FS/LS only */
pudev->regs.hr->HCTL &= ~HCTL_SPDFSLS;
@@ -157,10 +140,10 @@ usb_status usb_host_init (usb_core_driver *pudev)
/* make sure the FIFOs are flushed */
/* flush all Tx FIFOs in device or host mode */
usb_txfifo_flush (&pudev->regs, 0x10U);
usb_txfifo_flush(&pudev->regs, 0x10U);
/* flush the entire Rx FIFO */
usb_rxfifo_flush (&pudev->regs);
usb_rxfifo_flush(&pudev->regs);
/* clear all pending host channel interrupts */
for (i = 0U; i < pudev->bp.num_pipe; i++) {
@@ -169,7 +152,7 @@ usb_status usb_host_init (usb_core_driver *pudev)
}
#ifndef USE_OTG_MODE
usb_portvbus_switch (pudev, 1U);
usb_portvbus_switch(pudev, 1U);
#endif /* USE_OTG_MODE */
pudev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE;
@@ -199,15 +182,14 @@ usb_status usb_host_init (usb_core_driver *pudev)
\param[out] none
\retval none
*/
void usb_portvbus_switch (usb_core_driver *pudev, uint8_t state)
{
void usb_portvbus_switch(usb_core_driver *pudev, uint8_t state) {
uint32_t port = 0U;
/* enable or disable the external charge pump */
usb_vbus_drive (state);
usb_vbus_drive(state);
/* turn on the host port power. */
port = usb_port_read (pudev);
port = usb_port_read(pudev);
if (!(port & HPCS_PP) && (1U == state)) {
port |= HPCS_PP;
@@ -219,7 +201,7 @@ void usb_portvbus_switch (usb_core_driver *pudev, uint8_t state)
*pudev->regs.HPCS = port;
usb_mdelay (200U);
usb_mdelay(200U);
}
/*!
@@ -228,17 +210,16 @@ void usb_portvbus_switch (usb_core_driver *pudev, uint8_t state)
\param[out] none
\retval operation status
*/
uint32_t usb_port_reset (usb_core_driver *pudev)
{
__IO uint32_t port = usb_port_read (pudev);
uint32_t usb_port_reset(usb_core_driver *pudev) {
__IO uint32_t port = usb_port_read(pudev);
*pudev->regs.HPCS = port | HPCS_PRST;
usb_mdelay (100U); /* see note */
usb_mdelay(100U); /* see note */
*pudev->regs.HPCS = port & ~HPCS_PRST;
usb_mdelay (20U);
usb_mdelay(20U);
return 1;
}
@@ -250,8 +231,7 @@ uint32_t usb_port_reset (usb_core_driver *pudev)
\param[out] none
\retval operation status
*/
usb_status usb_pipe_init (usb_core_driver *pudev, uint8_t pipe_num)
{
usb_status usb_pipe_init(usb_core_driver *pudev, uint8_t pipe_num) {
usb_status status = USB_OK;
__IO uint32_t pp_ctl = 0U;
@@ -274,8 +254,7 @@ usb_status usb_pipe_init (usb_core_driver *pudev, uint8_t pipe_num)
switch (pp->ep.type) {
case USB_EPTYPE_CTRL:
case USB_EPTYPE_BULK:
pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE \
| HCHINTEN_DTERIE | HCHINTEN_NAKIE;
pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE | HCHINTEN_NAKIE;
if (!pp->ep.dir) {
pp_inten |= HCHINTEN_NYETIE;
@@ -287,8 +266,7 @@ usb_status usb_pipe_init (usb_core_driver *pudev, uint8_t pipe_num)
break;
case USB_EPTYPE_INTR:
pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \
| HCHINTEN_NAKIE | HCHINTEN_REQOVRIE;
pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE;
break;
case USB_EPTYPE_ISOC:
@@ -333,8 +311,7 @@ usb_status usb_pipe_init (usb_core_driver *pudev, uint8_t pipe_num)
\param[out] none
\retval operation status
*/
usb_status usb_pipe_xfer (usb_core_driver *pudev, uint8_t pipe_num)
{
usb_status usb_pipe_xfer(usb_core_driver *pudev, uint8_t pipe_num) {
usb_status status = USB_OK;
uint16_t dword_len = 0U;
@@ -415,7 +392,7 @@ usb_status usb_pipe_xfer (usb_core_driver *pudev, uint8_t pipe_num)
}
/* write packet into the tx fifo. */
usb_txfifo_write (&pudev->regs, pp->xfer_buf, pipe_num, pp->xfer_len);
usb_txfifo_write(&pudev->regs, pp->xfer_buf, pipe_num, pp->xfer_len);
}
}
@@ -429,8 +406,7 @@ usb_status usb_pipe_xfer (usb_core_driver *pudev, uint8_t pipe_num)
\param[out] none
\retval operation status
*/
usb_status usb_pipe_halt (usb_core_driver *pudev, uint8_t pipe_num)
{
usb_status usb_pipe_halt(usb_core_driver *pudev, uint8_t pipe_num) {
__IO uint32_t pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL;
uint8_t ep_type = (pp_ctl & HCHCTL_EPTYPE) >> 18U;
@@ -468,8 +444,7 @@ usb_status usb_pipe_halt (usb_core_driver *pudev, uint8_t pipe_num)
\param[out] none
\retval operation status
*/
usb_status usb_pipe_ping (usb_core_driver *pudev, uint8_t pipe_num)
{
usb_status usb_pipe_ping(usb_core_driver *pudev, uint8_t pipe_num) {
uint32_t pp_ctl = 0U;
pudev->regs.pr[pipe_num]->HCHLEN = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U));
@@ -490,8 +465,7 @@ usb_status usb_pipe_ping (usb_core_driver *pudev, uint8_t pipe_num)
\param[out] none
\retval none
*/
void usb_host_stop (usb_core_driver *pudev)
{
void usb_host_stop(usb_core_driver *pudev) {
uint32_t i;
__IO uint32_t pp_ctl = 0U;
@@ -509,6 +483,6 @@ void usb_host_stop (usb_core_driver *pudev)
}
/* flush the FIFO */
usb_rxfifo_flush (&pudev->regs);
usb_txfifo_flush (&pudev->regs, 0x10U);
usb_rxfifo_flush(&pudev->regs);
usb_txfifo_flush(&pudev->regs, 0x10U);
}

145
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbd_int.c vendored
View File

@@ -36,21 +36,17 @@ OF SUCH DAMAGE.
#include "drv_usbd_int.h"
#include "usbd_transc.h"
static uint32_t usbd_int_epout (usb_core_driver *udev);
static uint32_t usbd_int_epin (usb_core_driver *udev);
static uint32_t usbd_int_rxfifo (usb_core_driver *udev);
static uint32_t usbd_int_reset (usb_core_driver *udev);
static uint32_t usbd_int_enumfinish (usb_core_driver *udev);
static uint32_t usbd_int_suspend (usb_core_driver *udev);
static uint32_t usbd_int_epout(usb_core_driver *udev);
static uint32_t usbd_int_epin(usb_core_driver *udev);
static uint32_t usbd_int_rxfifo(usb_core_driver *udev);
static uint32_t usbd_int_reset(usb_core_driver *udev);
static uint32_t usbd_int_enumfinish(usb_core_driver *udev);
static uint32_t usbd_int_suspend(usb_core_driver *udev);
static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num);
static uint32_t usbd_emptytxfifo_write(usb_core_driver *udev, uint32_t ep_num);
static const uint8_t USB_SPEED[4] = {
[DSTAT_EM_HS_PHY_30MHZ_60MHZ] = USB_SPEED_HIGH,
[DSTAT_EM_FS_PHY_30MHZ_60MHZ] = USB_SPEED_FULL,
[DSTAT_EM_FS_PHY_48MHZ] = USB_SPEED_FULL,
[DSTAT_EM_LS_PHY_6MHZ] = USB_SPEED_LOW
};
static const uint8_t USB_SPEED[4]
= {[DSTAT_EM_HS_PHY_30MHZ_60MHZ] = USB_SPEED_HIGH, [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = USB_SPEED_FULL, [DSTAT_EM_FS_PHY_48MHZ] = USB_SPEED_FULL, [DSTAT_EM_LS_PHY_6MHZ] = USB_SPEED_LOW};
__IO uint8_t setupc_flag = 0U;
@@ -62,8 +58,7 @@ __IO uint8_t setupc_flag = 0U;
\param[out] none
\retval operation status
*/
uint32_t USBD_OTG_EP1OUT_ISR_Handler (usb_core_driver *udev)
{
uint32_t USBD_OTG_EP1OUT_ISR_Handler(usb_core_driver *udev) {
uint32_t oepintr = 0U;
uint32_t oeplen = 0U;
@@ -71,18 +66,15 @@ uint32_t USBD_OTG_EP1OUT_ISR_Handler (usb_core_driver *udev)
oepintr &= udev->regs.dr->DOEP1INTEN;
/* Transfer complete */
if (oepintr & DOEPINTF_TF)
{
if (oepintr & DOEPINTF_TF) {
/* Clear the bit in DOEPINTn for this interrupt */
udev->regs.er_out[1]->DOEPINTF = DOEPINTF_TF;
if (USB_USE_DMA == udev->bp.transfer_mode)
{
if (USB_USE_DMA == udev->bp.transfer_mode) {
oeplen = udev->regs.er_out[1]->DOEPLEN;
/* ToDo : handle more than one single MPS size packet */
udev->dev.transc_out[1].xfer_count = udev->dev.transc_out[1].usb_transc - \
oeplen & DEPLEN_TLEN;
udev->dev.transc_out[1].xfer_count = udev->dev.transc_out[1].usb_transc - oeplen & DEPLEN_TLEN;
}
/* RX COMPLETE */
@@ -98,19 +90,17 @@ uint32_t USBD_OTG_EP1OUT_ISR_Handler (usb_core_driver *udev)
\param[out] none
\retval operation status
*/
uint32_t USBD_OTG_EP1IN_ISR_Handler (usb_core_driver *udev)
{
uint32_t USBD_OTG_EP1IN_ISR_Handler(usb_core_driver *udev) {
uint32_t inten, intr, emptyen;
inten = udev->regs.dr->DIEP1INTEN;
emptyen = udev->regs.dr->DIEPFEINTEN;
inten |= ((emptyen >> 1 ) & 0x1) << 7;
inten |= ((emptyen >> 1) & 0x1) << 7;
intr = udev->regs.er_in[1]->DIEPINTF & inten;
if (intr & DIEPINTF_TF)
{
if (intr & DIEPINTF_TF) {
udev->regs.dr->DIEPFEINTEN &= ~(0x1 << 1);
udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TF;
@@ -119,8 +109,7 @@ uint32_t USBD_OTG_EP1IN_ISR_Handler (usb_core_driver *udev)
USBD_DCD_INT_fops->DataInStage(udev, 1);
}
if (intr & DIEPINTF_TXFE)
{
if (intr & DIEPINTF_TXFE) {
DCD_WriteEmptyTxFifo(udev, 1);
udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TXFE;
@@ -131,15 +120,13 @@ uint32_t USBD_OTG_EP1IN_ISR_Handler (usb_core_driver *udev)
#endif
/*!
\brief USB device-mode interrupts global service routine handler
\param[in] udev: pointer to usb device instance
\param[out] none
\retval none
*/
void usbd_isr (usb_core_driver *udev)
{
void usbd_isr(usb_core_driver *udev) {
if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) {
uint32_t intr = udev->regs.gr->GINTF & udev->regs.gr->GINTEN;
@@ -150,17 +137,17 @@ void usbd_isr (usb_core_driver *udev)
/* OUT endpoints interrupts */
if (intr & GINTF_OEPIF) {
usbd_int_epout (udev);
usbd_int_epout(udev);
}
/* IN endpoints interrupts */
if (intr & GINTF_IEPIF) {
usbd_int_epin (udev);
usbd_int_epin(udev);
}
/* suspend interrupt */
if (intr & GINTF_SP) {
usbd_int_suspend (udev);
usbd_int_suspend(udev);
}
/* wakeup interrupt */
@@ -186,10 +173,10 @@ void usbd_isr (usb_core_driver *udev)
}
if (0U != setupc_flag) {
setupc_flag ++;
setupc_flag++;
if (setupc_flag >= 3U) {
usbd_setup_transc (udev);
usbd_setup_transc(udev);
setupc_flag = 0U;
}
@@ -201,17 +188,17 @@ void usbd_isr (usb_core_driver *udev)
/* receive FIFO not empty interrupt */
if (intr & GINTF_RXFNEIF) {
usbd_int_rxfifo (udev);
usbd_int_rxfifo(udev);
}
/* USB reset interrupt */
if (intr & GINTF_RST) {
usbd_int_reset (udev);
usbd_int_reset(udev);
}
/* enumeration has been done interrupt */
if (intr & GINTF_ENUMFIF) {
usbd_int_enumfinish (udev);
usbd_int_enumfinish(udev);
}
/* incomplete synchronization IN transfer interrupt*/
@@ -243,9 +230,7 @@ void usbd_isr (usb_core_driver *udev)
/* OTG mode interrupt */
if (intr & GINTF_OTGIF) {
if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) {
}
if (udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) {}
/* Clear OTG interrupt */
udev->regs.gr->GINTF = GINTF_OTGIF;
@@ -260,14 +245,13 @@ void usbd_isr (usb_core_driver *udev)
\param[out] none
\retval operation status
*/
static uint32_t usbd_int_epout (usb_core_driver *udev)
{
static uint32_t usbd_int_epout(usb_core_driver *udev) {
uint32_t epintnum = 0U;
uint32_t ep_num = 0U;
for (epintnum = usb_oepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) {
for (epintnum = usb_oepintnum_read(udev); epintnum; epintnum >>= 1, ep_num++) {
if (epintnum & 0x1) {
__IO uint32_t oepintr = usb_oepintr_read (udev, ep_num);
__IO uint32_t oepintr = usb_oepintr_read(udev, ep_num);
/* transfer complete interrupt */
if (oepintr & DOEPINTF_TF) {
@@ -277,16 +261,15 @@ static uint32_t usbd_int_epout (usb_core_driver *udev)
if (USB_USE_DMA == udev->bp.transfer_mode) {
__IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN;
udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - \
eplen & DEPLEN_TLEN;
udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - eplen & DEPLEN_TLEN;
}
/* inform upper layer: data ready */
usbd_out_transc (udev, ep_num);
usbd_out_transc(udev, ep_num);
if (USB_USE_DMA == udev->bp.transfer_mode) {
if ((0U == ep_num) && (USB_CTL_STATUS_OUT == udev->dev.control.ctl_state)) {
usb_ctlep_startout (udev);
usb_ctlep_startout(udev);
}
}
}
@@ -295,7 +278,7 @@ static uint32_t usbd_int_epout (usb_core_driver *udev)
if (oepintr & DOEPINTF_STPF) {
/* inform the upper layer that a setup packet is available */
if ((0U == ep_num) && (0U != setupc_flag)) {
usbd_setup_transc (udev);
usbd_setup_transc(udev);
setupc_flag = 0U;
@@ -314,30 +297,29 @@ static uint32_t usbd_int_epout (usb_core_driver *udev)
\param[out] none
\retval operation status
*/
static uint32_t usbd_int_epin (usb_core_driver *udev)
{
static uint32_t usbd_int_epin(usb_core_driver *udev) {
uint32_t epintnum = 0U;
uint32_t ep_num = 0U;
for (epintnum = usb_iepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) {
for (epintnum = usb_iepintnum_read(udev); epintnum; epintnum >>= 1, ep_num++) {
if (epintnum & 0x1U) {
__IO uint32_t iepintr = usb_iepintr_read (udev, ep_num);
__IO uint32_t iepintr = usb_iepintr_read(udev, ep_num);
if (iepintr & DIEPINTF_TF) {
udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF;
/* data transmittion is completed */
usbd_in_transc (udev, ep_num);
usbd_in_transc(udev, ep_num);
if (USB_USE_DMA == udev->bp.transfer_mode) {
if ((0U == ep_num) && (USB_CTL_STATUS_IN == udev->dev.control.ctl_state)) {
usb_ctlep_startout (udev);
usb_ctlep_startout(udev);
}
}
}
if (iepintr & DIEPINTF_TXFE) {
usbd_emptytxfifo_write (udev, ep_num);
usbd_emptytxfifo_write(udev, ep_num);
udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE;
}
@@ -353,8 +335,7 @@ static uint32_t usbd_int_epin (usb_core_driver *udev)
\param[out] none
\retval operation status
*/
static uint32_t usbd_int_rxfifo (usb_core_driver *udev)
{
static uint32_t usbd_int_rxfifo(usb_core_driver *udev) {
usb_transc *transc = NULL;
uint8_t data_PID = 0;
@@ -379,7 +360,7 @@ static uint32_t usbd_int_rxfifo (usb_core_driver *udev)
case RSTAT_DATA_UPDT:
if (bcount > 0) {
usb_rxfifo_read (&udev->regs, transc->xfer_buf, bcount);
usb_rxfifo_read(&udev->regs, transc->xfer_buf, bcount);
transc->xfer_buf += bcount;
transc->xfer_count += bcount;
@@ -397,7 +378,7 @@ static uint32_t usbd_int_rxfifo (usb_core_driver *udev)
case RSTAT_SETUP_UPDT:
if ((transc->ep_addr.num == 0) && (bcount == 8) && (data_PID == DPID_DATA0)) {
/* copy the setup packet received in FIFO into the setup buffer in RAM */
usb_rxfifo_read (&udev->regs, (uint8_t *)&udev->dev.control.req, bcount);
usb_rxfifo_read(&udev->regs, (uint8_t *)&udev->dev.control.req, bcount);
transc->xfer_count += bcount;
@@ -421,15 +402,14 @@ static uint32_t usbd_int_rxfifo (usb_core_driver *udev)
\param[out] none
\retval status
*/
static uint32_t usbd_int_reset (usb_core_driver *udev)
{
static uint32_t usbd_int_reset(usb_core_driver *udev) {
uint32_t i;
/* clear the remote wakeup signaling */
udev->regs.dr->DCTL &= ~DCTL_RWKUP;
/* flush the Tx FIFO */
usb_txfifo_flush (&udev->regs, 0);
usb_txfifo_flush(&udev->regs, 0);
for (i = 0; i < udev->bp.num_ep; i++) {
udev->regs.er_in[i]->DIEPINTF = 0xFFU;
@@ -453,28 +433,21 @@ static uint32_t usbd_int_reset (usb_core_driver *udev)
udev->dev.dev_addr = 0U;
/* configure endpoint 0 to receive SETUP packets */
usb_ctlep_startout (udev);
usb_ctlep_startout(udev);
/* clear USB reset interrupt */
udev->regs.gr->GINTF = GINTF_RST;
udev->dev.transc_out[0] = (usb_transc) {
.ep_type = USB_EPTYPE_CTRL,
.max_len = USB_FS_EP0_MAX_LEN
};
udev->dev.transc_out[0] = (usb_transc){.ep_type = USB_EPTYPE_CTRL, .max_len = USB_FS_EP0_MAX_LEN};
usb_transc_active (udev, &udev->dev.transc_out[0]);
usb_transc_active(udev, &udev->dev.transc_out[0]);
udev->dev.transc_in[0] = (usb_transc) {
.ep_addr = {
.dir = 1
},
udev->dev.transc_in[0] = (usb_transc){.ep_addr = {.dir = 1},
.ep_type = USB_EPTYPE_CTRL,
.max_len = USB_FS_EP0_MAX_LEN
};
.max_len = USB_FS_EP0_MAX_LEN};
usb_transc_active (udev, &udev->dev.transc_in[0]);
usb_transc_active(udev, &udev->dev.transc_in[0]);
/* upon reset call usr call back */
udev->dev.cur_status = USBD_DEFAULT;
@@ -488,8 +461,7 @@ static uint32_t usbd_int_reset (usb_core_driver *udev)
\param[out] none
\retval status
*/
static uint32_t usbd_int_enumfinish (usb_core_driver *udev)
{
static uint32_t usbd_int_enumfinish(usb_core_driver *udev) {
uint8_t enum_speed = (uint8_t)((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U);
udev->regs.dr->DCTL &= ~DCTL_CGINAK;
@@ -520,11 +492,10 @@ static uint32_t usbd_int_enumfinish (usb_core_driver *udev)
\param[out] none
\retval operation status
*/
static uint32_t usbd_int_suspend (usb_core_driver *udev)
{
static uint32_t usbd_int_suspend(usb_core_driver *udev) {
__IO uint8_t low_power = udev->bp.low_power;
__IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST);
__IO uint8_t is_configured = (udev->dev.cur_status == USBD_CONFIGURED)? 1U : 0U;
__IO uint8_t is_configured = (udev->dev.cur_status == USBD_CONFIGURED) ? 1U : 0U;
udev->dev.backup_status = udev->dev.cur_status;
udev->dev.cur_status = USBD_SUSPENDED;
@@ -550,8 +521,7 @@ static uint32_t usbd_int_suspend (usb_core_driver *udev)
\param[out] none
\retval status
*/
static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num)
{
static uint32_t usbd_emptytxfifo_write(usb_core_driver *udev, uint32_t ep_num) {
usb_transc *transc = NULL;
uint32_t len = 0;
@@ -568,8 +538,7 @@ static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num)
word_count = (len + 3) / 4;
while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) > word_count) && \
(transc->xfer_count < transc->xfer_len)) {
while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) > word_count) && (transc->xfer_count < transc->xfer_len)) {
len = transc->xfer_len - transc->xfer_count;
if (len > transc->max_len) {
@@ -580,7 +549,7 @@ static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num)
word_count = (len + 3) / 4;
/* write the FIFO */
usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, len);
usb_txfifo_write(&udev->regs, transc->xfer_buf, ep_num, len);
transc->xfer_buf += len;
transc->xfer_count += len;

95
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbh_int.c vendored
View File

@@ -32,26 +32,22 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
OF SUCH DAMAGE.
*/
#include "drv_usbh_int.h"
#include "drv_usb_core.h"
#include "drv_usb_host.h"
#include "drv_usbh_int.h"
#if defined (__GNUC__) /*!< GNU compiler */
#pragma GCC optimize ("O0")
#if defined(__GNUC__) /*!< GNU compiler */
#pragma GCC optimize("O0")
#endif /* __GNUC__ */
static uint32_t usbh_int_port (usb_core_driver *pudev);
static uint32_t usbh_int_pipe (usb_core_driver *pudev);
static uint32_t usbh_int_pipe_in (usb_core_driver *pudev, uint32_t pp_num);
static uint32_t usbh_int_pipe_out (usb_core_driver *pudev, uint32_t pp_num);
static uint32_t usbh_int_rxfifonoempty (usb_core_driver *pudev);
static uint32_t usbh_int_txfifoempty (usb_core_driver *pudev, usb_pipe_mode pp_mode);
static uint32_t usbh_int_port(usb_core_driver *pudev);
static uint32_t usbh_int_pipe(usb_core_driver *pudev);
static uint32_t usbh_int_pipe_in(usb_core_driver *pudev, uint32_t pp_num);
static uint32_t usbh_int_pipe_out(usb_core_driver *pudev, uint32_t pp_num);
static uint32_t usbh_int_rxfifonoempty(usb_core_driver *pudev);
static uint32_t usbh_int_txfifoempty(usb_core_driver *pudev, usb_pipe_mode pp_mode);
static inline void usb_pp_halt (usb_core_driver *pudev,
uint8_t pp_num,
uint32_t pp_int,
usb_pipe_staus pp_status)
{
static inline void usb_pp_halt(usb_core_driver *pudev, uint8_t pp_num, uint32_t pp_int, usb_pipe_staus pp_status) {
pudev->regs.pr[pp_num]->HCHINTEN |= HCHINTEN_CHIE;
usb_pipe_halt(pudev, pp_num);
@@ -67,8 +63,7 @@ static inline void usb_pp_halt (usb_core_driver *pudev,
\param[out] none
\retval operation status
*/
uint32_t usbh_isr (usb_core_driver *pudev)
{
uint32_t usbh_isr(usb_core_driver *pudev) {
uint32_t Retval = 0U;
__IO uint32_t intr = 0U;
@@ -89,23 +84,23 @@ uint32_t usbh_isr (usb_core_driver *pudev)
}
if (intr & GINTF_RXFNEIF) {
Retval |= usbh_int_rxfifonoempty (pudev);
Retval |= usbh_int_rxfifonoempty(pudev);
}
if (intr & GINTF_NPTXFEIF) {
Retval |= usbh_int_txfifoempty (pudev, PIPE_NON_PERIOD);
Retval |= usbh_int_txfifoempty(pudev, PIPE_NON_PERIOD);
}
if (intr & GINTF_PTXFEIF) {
Retval |= usbh_int_txfifoempty (pudev, PIPE_PERIOD);
Retval |= usbh_int_txfifoempty(pudev, PIPE_PERIOD);
}
if (intr & GINTF_HCIF) {
Retval |= usbh_int_pipe (pudev);
Retval |= usbh_int_pipe(pudev);
}
if (intr & GINTF_HPIF) {
Retval |= usbh_int_port (pudev);
Retval |= usbh_int_port(pudev);
}
if (intr & GINTF_DISCIF) {
@@ -132,17 +127,16 @@ uint32_t usbh_isr (usb_core_driver *pudev)
\param[out] none
\retval operation status
*/
static uint32_t usbh_int_pipe (usb_core_driver *pudev)
{
static uint32_t usbh_int_pipe(usb_core_driver *pudev) {
uint32_t pp_num = 0U;
uint32_t retval = 0U;
for (pp_num = 0U; pp_num < pudev->bp.num_pipe; pp_num++) {
if ((pudev->regs.hr->HACHINT & HACHINT_HACHINT) & (1U << pp_num)) {
if (pudev->regs.pr[pp_num]->HCHCTL & HCHCTL_EPDIR) {
retval |= usbh_int_pipe_in (pudev, pp_num);
retval |= usbh_int_pipe_in(pudev, pp_num);
} else {
retval |= usbh_int_pipe_out (pudev, pp_num);
retval |= usbh_int_pipe_out(pudev, pp_num);
}
}
}
@@ -156,8 +150,7 @@ static uint32_t usbh_int_pipe (usb_core_driver *pudev)
\param[out] none
\retval operation status
*/
static uint32_t usbh_int_txfifoempty (usb_core_driver *pudev, usb_pipe_mode pp_mode)
{
static uint32_t usbh_int_txfifoempty(usb_core_driver *pudev, usb_pipe_mode pp_mode) {
uint8_t pp_num = 0U;
uint16_t word_count = 0U, len = 0U;
__IO uint32_t *txfiforeg = 0U, txfifostate = 0U;
@@ -191,7 +184,7 @@ static uint32_t usbh_int_txfifoempty (usb_core_driver *pudev, usb_pipe_mode pp_m
}
word_count = (pudev->host.pipe[pp_num].xfer_len + 3U) / 4U;
usb_txfifo_write (&pudev->regs, pudev->host.pipe[pp_num].xfer_buf, pp_num, len);
usb_txfifo_write(&pudev->regs, pudev->host.pipe[pp_num].xfer_buf, pp_num, len);
pudev->host.pipe[pp_num].xfer_buf += len;
pudev->host.pipe[pp_num].xfer_len -= len;
@@ -209,8 +202,7 @@ static uint32_t usbh_int_txfifoempty (usb_core_driver *pudev, usb_pipe_mode pp_m
\param[out] none
\retval operation status
*/
static uint32_t usbh_int_port (usb_core_driver *pudev)
{
static uint32_t usbh_int_port(usb_core_driver *pudev) {
uint32_t retval = 0U;
__IO uint32_t port_state = *pudev->regs.HPCS;
@@ -242,14 +234,14 @@ static uint32_t usbh_int_port (usb_core_driver *pudev)
if (HCTL_6MHZ != clock_type) {
if (USB_EMBEDDED_PHY == pudev->bp.phy_itf) {
usb_phyclock_config (pudev, HCTL_6MHZ);
usb_phyclock_config(pudev, HCTL_6MHZ);
}
}
} else if (PORT_SPEED_FULL == port_speed) {
pudev->regs.hr->HFT = 48000U;
if (HCTL_48MHZ != clock_type) {
usb_phyclock_config (pudev, HCTL_48MHZ);
usb_phyclock_config(pudev, HCTL_48MHZ);
}
} else {
/* for high speed device and others */
@@ -276,8 +268,7 @@ static uint32_t usbh_int_port (usb_core_driver *pudev)
\param[out] none
\retval operation status
*/
uint32_t usbh_int_pipe_out (usb_core_driver *pudev, uint32_t pp_num)
{
uint32_t usbh_int_pipe_out(usb_core_driver *pudev, uint32_t pp_num) {
usb_pr *pp_reg = pudev->regs.pr[pp_num];
usb_pipe *pp = &pudev->host.pipe[pp_num];
@@ -287,24 +278,24 @@ uint32_t usbh_int_pipe_out (usb_core_driver *pudev, uint32_t pp_num)
if (intr_pp & HCHINTF_ACK) {
pp_reg->HCHINTF = HCHINTF_ACK;
} else if (intr_pp & HCHINTF_STALL) {
usb_pp_halt (pudev, pp_num, HCHINTF_STALL, PIPE_STALL);
usb_pp_halt(pudev, pp_num, HCHINTF_STALL, PIPE_STALL);
} else if (intr_pp & HCHINTF_DTER) {
usb_pp_halt (pudev, pp_num, HCHINTF_DTER, PIPE_DTGERR);
usb_pp_halt(pudev, pp_num, HCHINTF_DTER, PIPE_DTGERR);
pp_reg->HCHINTF = HCHINTF_NAK;
} else if (intr_pp & HCHINTF_REQOVR) {
usb_pp_halt (pudev, pp_num, HCHINTF_REQOVR, PIPE_REQOVR);
usb_pp_halt(pudev, pp_num, HCHINTF_REQOVR, PIPE_REQOVR);
} else if (intr_pp & HCHINTF_TF) {
pp->err_count = 0U;
usb_pp_halt (pudev, pp_num, HCHINTF_TF, PIPE_XF);
usb_pp_halt(pudev, pp_num, HCHINTF_TF, PIPE_XF);
} else if (intr_pp & HCHINTF_NAK) {
pp->err_count = 0U;
usb_pp_halt (pudev, pp_num, HCHINTF_NAK, PIPE_NAK);
usb_pp_halt(pudev, pp_num, HCHINTF_NAK, PIPE_NAK);
} else if (intr_pp & HCHINTF_USBER) {
pp->err_count++;
usb_pp_halt (pudev, pp_num, HCHINTF_USBER, PIPE_TRACERR);
usb_pp_halt(pudev, pp_num, HCHINTF_USBER, PIPE_TRACERR);
} else if (intr_pp & HCHINTF_NYET) {
pp->err_count = 0U;
usb_pp_halt (pudev, pp_num, HCHINTF_NYET, PIPE_NYET);
usb_pp_halt(pudev, pp_num, HCHINTF_NYET, PIPE_NYET);
} else if (intr_pp & HCHINTF_CH) {
pudev->regs.pr[pp_num]->HCHINTEN &= ~HCHINTEN_CHIE;
@@ -323,7 +314,7 @@ uint32_t usbh_int_pipe_out (usb_core_driver *pudev, uint32_t pp_num)
case PIPE_NYET:
if (1U == pudev->host.pipe[pp_num].ping) {
usb_pipe_ping (pudev, pp_num);
usb_pipe_ping(pudev, pp_num);
}
pp->urb_state = URB_NOTREADY;
@@ -357,8 +348,7 @@ uint32_t usbh_int_pipe_out (usb_core_driver *pudev, uint32_t pp_num)
\param[out] none
\retval operation status
*/
uint32_t usbh_int_pipe_in (usb_core_driver *pudev, uint32_t pp_num)
{
uint32_t usbh_int_pipe_in(usb_core_driver *pudev, uint32_t pp_num) {
usb_pr *pp_reg = pudev->regs.pr[pp_num];
usb_pipe *pp = &pudev->host.pipe[pp_num];
@@ -370,7 +360,7 @@ uint32_t usbh_int_pipe_in (usb_core_driver *pudev, uint32_t pp_num)
if (intr_pp & HCHINTF_ACK) {
pp_reg->HCHINTF = HCHINTF_ACK;
} else if (intr_pp & HCHINTF_STALL) {
usb_pp_halt (pudev, pp_num, HCHINTF_STALL, PIPE_STALL);
usb_pp_halt(pudev, pp_num, HCHINTF_STALL, PIPE_STALL);
pp_reg->HCHINTF = HCHINTF_NAK;
/* note: When there is a 'STALL', reset also nak,
@@ -378,12 +368,12 @@ uint32_t usbh_int_pipe_in (usb_core_driver *pudev, uint32_t pp_num)
will be overwritten by 'NAK' in code below */
intr_pp &= ~HCHINTF_NAK;
} else if (intr_pp & HCHINTF_DTER) {
usb_pp_halt (pudev, pp_num, HCHINTF_DTER, PIPE_DTGERR);
usb_pp_halt(pudev, pp_num, HCHINTF_DTER, PIPE_DTGERR);
pp_reg->HCHINTF = HCHINTF_NAK;
}
if (intr_pp & HCHINTF_REQOVR) {
usb_pp_halt (pudev, pp_num, HCHINTF_REQOVR, PIPE_REQOVR);
usb_pp_halt(pudev, pp_num, HCHINTF_REQOVR, PIPE_REQOVR);
} else if (intr_pp & HCHINTF_TF) {
if (USB_USE_DMA == pudev->bp.transfer_mode) {
pudev->host.backup_xfercount[pp_num] = pp->xfer_len - pp_reg->HCHLEN & HCHLEN_TLEN;
@@ -397,7 +387,7 @@ uint32_t usbh_int_pipe_in (usb_core_driver *pudev, uint32_t pp_num)
switch (ep_type) {
case USB_EPTYPE_CTRL:
case USB_EPTYPE_BULK:
usb_pp_halt (pudev, pp_num, HCHINTF_NAK, PIPE_XF);
usb_pp_halt(pudev, pp_num, HCHINTF_NAK, PIPE_XF);
pp->data_toggle_in ^= 1U;
break;
@@ -429,7 +419,7 @@ uint32_t usbh_int_pipe_in (usb_core_driver *pudev, uint32_t pp_num)
break;
default:
if(USB_EPTYPE_INTR == ep_type) {
if (USB_EPTYPE_INTR == ep_type) {
pp->data_toggle_in ^= 1U;
}
break;
@@ -438,7 +428,7 @@ uint32_t usbh_int_pipe_in (usb_core_driver *pudev, uint32_t pp_num)
pp_reg->HCHINTF = HCHINTF_CH;
} else if (intr_pp & HCHINTF_BBER) {
pp->err_count++;
usb_pp_halt (pudev, pp_num, HCHINTF_BBER, PIPE_TRACERR);
usb_pp_halt(pudev, pp_num, HCHINTF_BBER, PIPE_TRACERR);
} else if (intr_pp & HCHINTF_NAK) {
switch (ep_type) {
case USB_EPTYPE_CTRL:
@@ -471,8 +461,7 @@ uint32_t usbh_int_pipe_in (usb_core_driver *pudev, uint32_t pp_num)
\param[out] none
\retval operation status
*/
static uint32_t usbh_int_rxfifonoempty (usb_core_driver *pudev)
{
static uint32_t usbh_int_rxfifonoempty(usb_core_driver *pudev) {
uint32_t count = 0U;
__IO uint8_t pp_num = 0U;
@@ -490,7 +479,7 @@ static uint32_t usbh_int_rxfifonoempty (usb_core_driver *pudev)
/* read the data into the host buffer. */
if ((count > 0U) && (NULL != pudev->host.pipe[pp_num].xfer_buf)) {
usb_rxfifo_read (&pudev->regs, pudev->host.pipe[pp_num].xfer_buf, count);
usb_rxfifo_read(&pudev->regs, pudev->host.pipe[pp_num].xfer_buf, count);
/* manage multiple transfer packet */
pudev->host.pipe[pp_num].xfer_buf += count;

72
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/gd32vf103_usb_hw.c vendored
View File

@@ -31,13 +31,12 @@ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWIS
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32vf103_libopt.h"
#include "drv_usb_hw.h"
#include "gd32vf103_libopt.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define TIM_MSEC_DELAY 0x01
#define TIM_USEC_DELAY 0x02
@@ -49,8 +48,8 @@ __IO uint32_t delay_time = 0;
__IO uint32_t usbfs_prescaler = 0;
__IO uint32_t timer_prescaler = 5;
static void hwp_time_set (uint8_t unit);
static void hwp_delay (uint32_t ntime, uint8_t unit);
static void hwp_time_set(uint8_t unit);
static void hwp_delay(uint32_t ntime, uint8_t unit);
/*!
\brief configure USB clock
@@ -58,8 +57,7 @@ static void hwp_delay (uint32_t ntime, uint8_t unit);
\param[out] none
\retval none
*/
void usb_rcu_config (void)
{
void usb_rcu_config(void) {
uint32_t system_clock = rcu_clock_freq_get(CK_SYS);
if (system_clock == 48000000) {
@@ -85,10 +83,9 @@ void usb_rcu_config (void)
\param[out] none
\retval none
*/
void usb_intr_config (void)
{
ECLIC_SetLevelIRQ(USBFS_IRQn,1);
ECLIC_SetPriorityIRQ(USBFS_IRQn,0);
void usb_intr_config(void) {
ECLIC_SetLevelIRQ(USBFS_IRQn, 1);
ECLIC_SetPriorityIRQ(USBFS_IRQn, 0);
ECLIC_EnableIRQ(USBFS_IRQn);
#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
@@ -100,8 +97,8 @@ void usb_intr_config (void)
exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING);
exti_interrupt_enable(EXTI_18);
ECLIC_SetLevelIRQ(USBFS_WKUP_IRQn,3);
ECLIC_SetPriorityIRQ(USBFS_WKUP_IRQn,0);
ECLIC_SetLevelIRQ(USBFS_WKUP_IRQn, 3);
ECLIC_SetPriorityIRQ(USBFS_WKUP_IRQn, 0);
ECLIC_EnableIRQ(USBFS_WKUP_IRQn);
#endif /* USBHS_LOW_PWR_MGMT_SUPPORT */
@@ -113,15 +110,11 @@ void usb_intr_config (void)
\param[out] none
\retval none
*/
void usb_vbus_drive (uint8_t state)
{
if (0 == state)
{
void usb_vbus_drive(uint8_t state) {
if (0 == state) {
/* DISABLE is needed on output of the Power Switch */
gpio_bit_reset(HOST_POWERSW_PORT, HOST_POWERSW_VBUS);
}
else
{
} else {
/*ENABLE the Power Switch by driving the Enable LOW */
gpio_bit_set(HOST_POWERSW_PORT, HOST_POWERSW_VBUS);
}
@@ -133,8 +126,7 @@ void usb_vbus_drive (uint8_t state)
\param[out] none
\retval none
*/
void usb_vbus_config (void)
{
void usb_vbus_config(void) {
rcu_periph_clock_enable(HOST_POWERSW_PORT_RCC);
gpio_init(HOST_POWERSW_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, HOST_POWERSW_VBUS);
@@ -145,8 +137,8 @@ void usb_vbus_config (void)
/* Delay is need for stabilising the Vbus Low in Reset Condition,
* when Vbus=1 and Reset-button is pressed by user
*/
//usb_mdelay (1);
usb_mdelay (2);
// usb_mdelay (1);
usb_mdelay(2);
}
/*!
@@ -155,11 +147,10 @@ void usb_vbus_config (void)
\param[out] none
\retval none
*/
void usb_timer_init (void)
{
void usb_timer_init(void) {
rcu_periph_clock_enable(RCU_TIMER2);
//eclic_irq_enable(TIMER2_IRQn, 2, 0);
// eclic_irq_enable(TIMER2_IRQn, 2, 0);
/*ECLIC_Register_IRQn(TIMER2_IRQn, ECLIC_VECTOR_INTERRUPT,
ECLIC_LEVEL_TRIGGER, 2, 0,
TIMER2_IRQHandler);*/
@@ -171,10 +162,7 @@ void usb_timer_init (void)
\param[out] none
\retval none
*/
void usb_udelay (const uint32_t usec)
{
hwp_delay(usec, TIM_USEC_DELAY);
}
void usb_udelay(const uint32_t usec) { hwp_delay(usec, TIM_USEC_DELAY); }
/*!
\brief delay in milli seconds
@@ -182,10 +170,7 @@ void usb_udelay (const uint32_t usec)
\param[out] none
\retval none
*/
void usb_mdelay (const uint32_t msec)
{
hwp_delay(msec, TIM_MSEC_DELAY);
}
void usb_mdelay(const uint32_t msec) { hwp_delay(msec, TIM_MSEC_DELAY); }
/*!
\brief timer base IRQ
@@ -193,12 +178,11 @@ void usb_mdelay (const uint32_t msec)
\param[out] none
\retval none
*/
void usb_timer_irq (void)
{
if (timer_interrupt_flag_get(TIMER2, TIMER_INT_UP) != RESET){
void usb_timer_irq(void) {
if (timer_interrupt_flag_get(TIMER2, TIMER_INT_UP) != RESET) {
timer_interrupt_flag_clear(TIMER2, TIMER_INT_UP);
if (delay_time > 0x00U){
if (delay_time > 0x00U) {
delay_time--;
} else {
timer_disable(TIMER2);
@@ -213,12 +197,12 @@ void usb_timer_irq (void)
\param[out] none
\retval none
*/
static void hwp_delay(uint32_t ntime, uint8_t unit)
{
static void hwp_delay(uint32_t ntime, uint8_t unit) {
delay_time = ntime;
hwp_time_set(unit);
while(delay_time != 0);
while (delay_time != 0)
;
timer_disable(TIMER2);
}
@@ -229,8 +213,7 @@ static void hwp_delay(uint32_t ntime, uint8_t unit)
\param[out] none
\retval none
*/
static void hwp_time_set(uint8_t unit)
{
static void hwp_time_set(uint8_t unit) {
timer_parameter_struct timer_basestructure;
timer_disable(TIMER2);
@@ -238,7 +221,7 @@ static void hwp_time_set(uint8_t unit)
if (unit == TIM_USEC_DELAY) {
timer_basestructure.period = 11;
} else if(unit == TIM_MSEC_DELAY) {
} else if (unit == TIM_MSEC_DELAY) {
timer_basestructure.period = 11999;
} else {
/* no operation */
@@ -262,4 +245,3 @@ static void hwp_time_set(uint8_t unit)
/* timer2 enable counter */
timer_enable(TIMER2);
}

78
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_core.c vendored
View File

@@ -36,12 +36,7 @@ OF SUCH DAMAGE.
#include "drv_usb_hw.h"
/* endpoint type */
const uint32_t ep_type[] = {
[USB_EP_ATTR_CTL] = USB_EPTYPE_CTRL,
[USB_EP_ATTR_BULK] = USB_EPTYPE_BULK,
[USB_EP_ATTR_INT] = USB_EPTYPE_INTR,
[USB_EP_ATTR_ISO] = USB_EPTYPE_ISOC
};
const uint32_t ep_type[] = {[USB_EP_ATTR_CTL] = USB_EPTYPE_CTRL, [USB_EP_ATTR_BULK] = USB_EPTYPE_BULK, [USB_EP_ATTR_INT] = USB_EPTYPE_INTR, [USB_EP_ATTR_ISO] = USB_EPTYPE_ISOC};
/*!
\brief initailizes the USB device-mode stack and load the class driver
@@ -51,25 +46,24 @@ const uint32_t ep_type[] = {
\param[out] none
\retval none
*/
void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core)
{
void usbd_init(usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core) {
/* device descriptor, class and user callbacks */
udev->dev.class_core = class_core;
/* configure USB capabilites */
usb_basic_init (&udev->bp, &udev->regs, core);
usb_basic_init(&udev->bp, &udev->regs, core);
/* initailizes the USB core*/
usb_core_init (udev->bp, &udev->regs);
usb_core_init(udev->bp, &udev->regs);
/* set device disconnect */
usbd_disconnect (udev);
usbd_disconnect(udev);
/* initailizes device mode */
usb_devcore_init (udev);
usb_devcore_init(udev);
/* set device connect */
usbd_connect (udev);
usbd_connect(udev);
udev->dev.cur_status = USBD_DEFAULT;
}
@@ -81,8 +75,7 @@ void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_class_core *class
\param[out] none
\retval none
*/
uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc)
{
uint32_t usbd_ep_setup(usb_core_driver *udev, const usb_desc_ep *ep_desc) {
usb_transc *transc;
uint8_t ep_addr = ep_desc->bEndpointAddress;
@@ -104,7 +97,7 @@ uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc)
transc->ep_type = ep_type[ep_desc->bmAttributes & USB_EPTYPE_MASK];
/* active USB endpoint function */
usb_transc_active (udev, transc);
usb_transc_active(udev, transc);
return 0;
}
@@ -119,8 +112,7 @@ uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc)
\param[out] none
\retval none
*/
uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr)
{
uint32_t usbd_ep_clear(usb_core_driver *udev, uint8_t ep_addr) {
usb_transc *transc;
if (EP_DIR(ep_addr)) {
@@ -130,12 +122,11 @@ uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr)
}
/* deactive USB endpoint function */
usb_transc_deactivate (udev, transc);
usb_transc_deactivate(udev, transc);
return 0;
}
/*!
\brief endpoint prepare to receive data
\param[in] udev: pointer to usb core instance
@@ -148,8 +139,7 @@ uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr)
\param[out] none
\retval none
*/
uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len)
{
uint32_t usbd_ep_recev(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len) {
usb_transc *transc = &udev->dev.transc_out[EP_ID(ep_addr)];
/* setup the transfer */
@@ -162,7 +152,7 @@ uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, u
}
/* start the transfer */
usb_transc_outxfer (udev, transc);
usb_transc_outxfer(udev, transc);
return 0;
}
@@ -179,8 +169,7 @@ uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, u
\param[out] none
\retval none
*/
uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len)
{
uint32_t usbd_ep_send(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len) {
usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_addr)];
/* setup the transfer */
@@ -193,7 +182,7 @@ uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, u
}
/* start the transfer */
usb_transc_inxfer (udev, transc);
usb_transc_inxfer(udev, transc);
return 0;
}
@@ -208,8 +197,7 @@ uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, u
\param[out] none
\retval none
*/
uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr)
{
uint32_t usbd_ep_stall(usb_core_driver *udev, uint8_t ep_addr) {
usb_transc *transc = NULL;
if (EP_DIR(ep_addr)) {
@@ -220,7 +208,7 @@ uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr)
transc->ep_stall = 1;
usb_transc_stall (udev, transc);
usb_transc_stall(udev, transc);
return (0);
}
@@ -235,8 +223,7 @@ uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr)
\param[out] none
\retval none
*/
uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr)
{
uint32_t usbd_ep_stall_clear(usb_core_driver *udev, uint8_t ep_addr) {
usb_transc *transc = NULL;
if (EP_DIR(ep_addr)) {
@@ -247,7 +234,7 @@ uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr)
transc->ep_stall = 0;
usb_transc_clrstall (udev, transc);
usb_transc_clrstall(udev, transc);
return (0);
}
@@ -262,12 +249,11 @@ uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr)
\param[out] none
\retval none
*/
uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr)
{
uint32_t usbd_fifo_flush(usb_core_driver *udev, uint8_t ep_addr) {
if (EP_DIR(ep_addr)) {
usb_txfifo_flush (&udev->regs, EP_ID(ep_addr));
usb_txfifo_flush(&udev->regs, EP_ID(ep_addr));
} else {
usb_rxfifo_flush (&udev->regs);
usb_rxfifo_flush(&udev->regs);
}
return (0);
@@ -280,10 +266,7 @@ uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr)
\param[out] none
\retval none
*/
void usbd_addr_set (usb_core_driver *udev, uint8_t addr)
{
usb_devaddr_set(udev, addr);
}
void usbd_addr_set(usb_core_driver *udev, uint8_t addr) { usb_devaddr_set(udev, addr); }
/*!
\brief get the received data length
@@ -292,10 +275,7 @@ void usbd_addr_set (usb_core_driver *udev, uint8_t addr)
\param[out] none
\retval USB device operation cur_status
*/
uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num)
{
return udev->dev.transc_out[ep_num].xfer_count;
}
uint16_t usbd_rxcount_get(usb_core_driver *udev, uint8_t ep_num) { return udev->dev.transc_out[ep_num].xfer_count; }
/*!
\brief device connect
@@ -303,11 +283,10 @@ uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num)
\param[out] none
\retval none
*/
void usbd_connect (usb_core_driver *udev)
{
void usbd_connect(usb_core_driver *udev) {
#ifndef USE_OTG_MODE
/* connect device */
usb_dev_connect (udev);
usb_dev_connect(udev);
usb_mdelay(3);
#endif /* USE_OTG_MODE */
@@ -319,11 +298,10 @@ void usbd_connect (usb_core_driver *udev)
\param[out] none
\retval none
*/
void usbd_disconnect (usb_core_driver *udev)
{
void usbd_disconnect(usb_core_driver *udev) {
#ifndef USE_OTG_MODE
/* disconnect device for 3ms */
usb_dev_disconnect (udev);
usb_dev_disconnect(udev);
usb_mdelay(3);
#endif /* USE_OTG_MODE */
}

138
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_enum.c vendored
View File

@@ -35,26 +35,25 @@ OF SUCH DAMAGE.
#include "usbd_enum.h"
#include "usb_ch9_std.h"
static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_setaddress(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_setconfiguration(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_getconfiguration(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_getdescriptor(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_setfeature(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_clearfeature(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_reserved(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_setdescriptor(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_getinterface(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_setinterface(usb_core_driver *udev, usb_req *req);
static usb_reqsta _usb_std_synchframe(usb_core_driver *udev, usb_req *req);
static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len);
static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len);
static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len);
static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len);
static uint8_t *_usb_dev_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len);
static uint8_t *_usb_config_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len);
static uint8_t *_usb_str_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len);
static uint8_t *_usb_bos_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len);
static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) =
{
static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = {
[USB_GET_STATUS] = _usb_std_getstatus,
[USB_CLEAR_FEATURE] = _usb_std_clearfeature,
[USB_RESERVED2] = _usb_std_reserved,
@@ -71,11 +70,8 @@ static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) =
};
/* get standard descriptor handler */
static uint8_t* (*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len) = {
[USB_DESCTYPE_DEV - 1] = _usb_dev_desc_get,
[USB_DESCTYPE_CONFIG - 1] = _usb_config_desc_get,
[USB_DESCTYPE_STR - 1] = _usb_str_desc_get
};
static uint8_t *(*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len)
= {[USB_DESCTYPE_DEV - 1] = _usb_dev_desc_get, [USB_DESCTYPE_CONFIG - 1] = _usb_config_desc_get, [USB_DESCTYPE_STR - 1] = _usb_str_desc_get};
/*!
\brief handle USB standard device request
@@ -84,10 +80,7 @@ static uint8_t* (*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t
\param[out] none
\retval USB device request status
*/
usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req)
{
return (*_std_dev_req[req->bRequest])(udev, req);
}
usb_reqsta usbd_standard_request(usb_core_driver *udev, usb_req *req) { return (*_std_dev_req[req->bRequest])(udev, req); }
/*!
\brief handle USB device class request
@@ -96,8 +89,7 @@ usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req)
{
usb_reqsta usbd_class_request(usb_core_driver *udev, usb_req *req) {
if (USBD_CONFIGURED == udev->dev.cur_status) {
if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) {
/* call device class handle function */
@@ -115,8 +107,7 @@ usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req)
{
usb_reqsta usbd_vendor_request(usb_core_driver *udev, usb_req *req) {
/* added by user... */
return REQ_SUPP;
@@ -129,8 +120,7 @@ usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_reserved(usb_core_driver *udev, usb_req *req) {
/* no operation... */
return REQ_NOTSUPP;
@@ -143,8 +133,7 @@ static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req)
\param[out] len: data length pointer
\retval descriptor buffer pointer
*/
static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len)
{
static uint8_t *_usb_dev_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) {
*len = udev->dev.desc.dev_desc[0];
return udev->dev.desc.dev_desc;
@@ -157,8 +146,7 @@ static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_
\param[out] len: data length pointer
\retval descriptor buffer pointer
*/
static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len)
{
static uint8_t *_usb_config_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) {
*len = udev->dev.desc.config_desc[2];
return udev->dev.desc.config_desc;
@@ -171,8 +159,7 @@ static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint
\param[out] len: data length pointer
\retval descriptor buffer pointer
*/
static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len)
{
static uint8_t *_usb_bos_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) {
*len = udev->dev.desc.bos_desc[2];
return udev->dev.desc.bos_desc;
@@ -185,8 +172,7 @@ static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_
\param[out] len: pointer to string length
\retval descriptor buffer pointer
*/
static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len)
{
static uint8_t *_usb_str_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) {
uint8_t *desc = udev->dev.desc.strings[index];
*len = desc[0];
@@ -201,18 +187,16 @@ static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req) {
uint8_t recp = BYTE_LOW(req->wIndex);
usb_transc *transc = &udev->dev.transc_in[0];
static uint8_t status[2] = {0};
switch(req->bmRequestType & USB_RECPTYPE_MASK) {
switch (req->bmRequestType & USB_RECPTYPE_MASK) {
case USB_RECPTYPE_DEV:
if ((USBD_ADDRESSED == udev->dev.cur_status) || \
(USBD_CONFIGURED == udev->dev.cur_status)) {
if ((USBD_ADDRESSED == udev->dev.cur_status) || (USBD_CONFIGURED == udev->dev.cur_status)) {
if (udev->dev.pm.power_mode) {
status[0] = USB_STATUS_SELF_POWERED;
@@ -271,15 +255,12 @@ static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_clearfeature(usb_core_driver *udev, usb_req *req) {
uint8_t ep = 0;
switch(req->bmRequestType & USB_RECPTYPE_MASK)
{
switch (req->bmRequestType & USB_RECPTYPE_MASK) {
case USB_RECPTYPE_DEV:
if ((USBD_ADDRESSED == udev->dev.cur_status) || \
(USBD_CONFIGURED == udev->dev.cur_status)) {
if ((USBD_ADDRESSED == udev->dev.cur_status) || (USBD_CONFIGURED == udev->dev.cur_status)) {
/* clear device remote wakeup feature */
if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) {
@@ -300,9 +281,9 @@ static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req)
if (USBD_CONFIGURED == udev->dev.cur_status) {
/* clear endpoint halt feature */
if ((USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) {
usbd_ep_stall_clear (udev, ep);
usbd_ep_stall_clear(udev, ep);
udev->dev.class_core->req_proc (udev, req);
udev->dev.class_core->req_proc(udev, req);
}
return REQ_SUPP;
@@ -323,15 +304,12 @@ static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_setfeature(usb_core_driver *udev, usb_req *req) {
uint8_t ep = 0;
switch(req->bmRequestType & USB_RECPTYPE_MASK)
{
switch (req->bmRequestType & USB_RECPTYPE_MASK) {
case USB_RECPTYPE_DEV:
if ((USBD_ADDRESSED == udev->dev.cur_status) || \
(USBD_CONFIGURED == udev->dev.cur_status)) {
if ((USBD_ADDRESSED == udev->dev.cur_status) || (USBD_CONFIGURED == udev->dev.cur_status)) {
/* set device remote wakeup feature */
if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) {
udev->dev.pm.dev_remote_wakeup = 1U;
@@ -351,7 +329,7 @@ static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req)
if (USBD_CONFIGURED == udev->dev.cur_status) {
/* set endpoint halt feature */
if ((USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) {
usbd_ep_stall (udev, ep);
usbd_ep_stall(udev, ep);
}
return REQ_SUPP;
@@ -372,13 +350,12 @@ static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_setaddress(usb_core_driver *udev, usb_req *req) {
if ((0U == req->wIndex) && (0U == req->wLength)) {
udev->dev.dev_addr = (uint8_t)(req->wValue) & 0x7FU;
if (udev->dev.cur_status != USBD_CONFIGURED) {
usbd_addr_set (udev, udev->dev.dev_addr);
usbd_addr_set(udev, udev->dev.dev_addr);
if (udev->dev.dev_addr) {
udev->dev.cur_status = USBD_ADDRESSED;
@@ -400,8 +377,7 @@ static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_getdescriptor(usb_core_driver *udev, usb_req *req) {
uint8_t desc_type = 0;
uint8_t desc_index = 0;
@@ -481,8 +457,7 @@ static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_setdescriptor(usb_core_driver *udev, usb_req *req) {
/* no handle... */
return REQ_SUPP;
}
@@ -494,8 +469,7 @@ static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_getconfiguration(usb_core_driver *udev, usb_req *req) {
usb_transc *transc = &udev->dev.transc_in[0];
switch (udev->dev.cur_status) {
@@ -531,8 +505,7 @@ static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_setconfiguration(usb_core_driver *udev, usb_req *req) {
static uint8_t config;
config = (uint8_t)(req->wValue);
@@ -540,7 +513,7 @@ static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req
if (config <= USBD_CFG_MAX_NUM) {
switch (udev->dev.cur_status) {
case USBD_ADDRESSED:
if (config){
if (config) {
udev->dev.class_core->init(udev, config);
udev->dev.config = config;
@@ -584,8 +557,7 @@ static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_getinterface(usb_core_driver *udev, usb_req *req) {
switch (udev->dev.cur_status) {
case USBD_DEFAULT:
break;
@@ -618,8 +590,7 @@ static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_setinterface(usb_core_driver *udev, usb_req *req) {
switch (udev->dev.cur_status) {
case USBD_DEFAULT:
break;
@@ -649,8 +620,7 @@ static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval USB device request status
*/
static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req)
{
static usb_reqsta _usb_std_synchframe(usb_core_driver *udev, usb_req *req) {
/* no handle... */
return REQ_SUPP;
}
@@ -662,10 +632,9 @@ static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval none
*/
void usbd_enum_error (usb_core_driver *udev, usb_req *req)
{
usbd_ep_stall (udev, 0x80);
usbd_ep_stall (udev, 0x00);
void usbd_enum_error(usb_core_driver *udev, usb_req *req) {
usbd_ep_stall(udev, 0x80);
usbd_ep_stall(udev, 0x00);
usb_ctlep_startout(udev);
}
@@ -678,8 +647,7 @@ void usbd_enum_error (usb_core_driver *udev, usb_req *req)
\param[out] none
\retval none
*/
void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len)
{
void int_to_unicode(uint32_t value, uint8_t *pbuf, uint8_t len) {
uint8_t index = 0;
for (index = 0; index < len; index++) {

61
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_transc.c vendored
View File

@@ -32,8 +32,8 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
OF SUCH DAMAGE.
*/
#include "usbd_enum.h"
#include "usbd_transc.h"
#include "usbd_enum.h"
/*!
\brief USB send data in the control transaction
@@ -41,8 +41,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval USB device operation cur_status
*/
usbd_status usbd_ctl_send (usb_core_driver *udev)
{
usbd_status usbd_ctl_send(usb_core_driver *udev) {
usb_transc *transc = &udev->dev.transc_in[0];
usbd_ep_send(udev, 0U, transc->xfer_buf, transc->remain_len);
@@ -62,11 +61,10 @@ usbd_status usbd_ctl_send (usb_core_driver *udev)
\param[out] none
\retval USB device operation cur_status
*/
usbd_status usbd_ctl_recev (usb_core_driver *udev)
{
usbd_status usbd_ctl_recev(usb_core_driver *udev) {
usb_transc *transc = &udev->dev.transc_out[0];
usbd_ep_recev (udev, 0U, transc->xfer_buf, transc->remain_len);
usbd_ep_recev(udev, 0U, transc->xfer_buf, transc->remain_len);
if (transc->remain_len > transc->max_len) {
udev->dev.control.ctl_state = USB_CTL_DATA_OUT;
@@ -83,11 +81,10 @@ usbd_status usbd_ctl_recev (usb_core_driver *udev)
\param[out] none
\retval USB device operation cur_status
*/
usbd_status usbd_ctl_status_send (usb_core_driver *udev)
{
usbd_status usbd_ctl_status_send(usb_core_driver *udev) {
udev->dev.control.ctl_state = USB_CTL_STATUS_IN;
usbd_ep_send (udev, 0U, NULL, 0U);
usbd_ep_send(udev, 0U, NULL, 0U);
usb_ctlep_startout(udev);
@@ -100,11 +97,10 @@ usbd_status usbd_ctl_status_send (usb_core_driver *udev)
\param[out] none
\retval USB device operation cur_status
*/
usbd_status usbd_ctl_status_recev (usb_core_driver *udev)
{
usbd_status usbd_ctl_status_recev(usb_core_driver *udev) {
udev->dev.control.ctl_state = USB_CTL_STATUS_OUT;
usbd_ep_recev (udev, 0, NULL, 0);
usbd_ep_recev(udev, 0, NULL, 0);
usb_ctlep_startout(udev);
@@ -117,8 +113,7 @@ usbd_status usbd_ctl_status_recev (usb_core_driver *udev)
\param[out] none
\retval USB device operation cur_status
*/
uint8_t usbd_setup_transc (usb_core_driver *udev)
{
uint8_t usbd_setup_transc(usb_core_driver *udev) {
usb_reqsta reqstat = REQ_NOTSUPP;
usb_req req = udev->dev.control.req;
@@ -126,17 +121,17 @@ uint8_t usbd_setup_transc (usb_core_driver *udev)
switch (req.bmRequestType & USB_REQTYPE_MASK) {
/* standard device request */
case USB_REQTYPE_STRD:
reqstat = usbd_standard_request (udev, &req);
reqstat = usbd_standard_request(udev, &req);
break;
/* device class request */
case USB_REQTYPE_CLASS:
reqstat = usbd_class_request (udev, &req);
reqstat = usbd_class_request(udev, &req);
break;
/* vendor defined request */
case USB_REQTYPE_VENDOR:
reqstat = usbd_vendor_request (udev, &req);
reqstat = usbd_vendor_request(udev, &req);
break;
default:
@@ -145,16 +140,16 @@ uint8_t usbd_setup_transc (usb_core_driver *udev)
if (REQ_SUPP == reqstat) {
if (req.wLength == 0) {
usbd_ctl_status_send (udev);
usbd_ctl_status_send(udev);
} else {
if (req.bmRequestType & 0x80) {
usbd_ctl_send (udev);
usbd_ctl_send(udev);
} else {
usbd_ctl_recev (udev);
usbd_ctl_recev(udev);
}
}
} else {
usbd_enum_error (udev, &req);
usbd_enum_error(udev, &req);
}
return USBD_OK;
@@ -167,8 +162,7 @@ uint8_t usbd_setup_transc (usb_core_driver *udev)
\param[out] none
\retval USB device operation cur_status
*/
uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num)
{
uint8_t usbd_out_transc(usb_core_driver *udev, uint8_t ep_num) {
if (ep_num == 0) {
usb_transc *transc = &udev->dev.transc_out[0];
@@ -177,26 +171,26 @@ uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num)
/* update transfer length */
transc->remain_len -= transc->max_len;
usbd_ctl_recev (udev);
usbd_ctl_recev(udev);
break;
case USB_CTL_LAST_DATA_OUT:
if (udev->dev.cur_status == USBD_CONFIGURED) {
if (udev->dev.class_core->data_out != NULL) {
udev->dev.class_core->data_out (udev, 0U);
udev->dev.class_core->data_out(udev, 0U);
}
}
transc->remain_len = 0U;
usbd_ctl_status_send (udev);
usbd_ctl_status_send(udev);
break;
default:
break;
}
} else if ((udev->dev.class_core->data_out != NULL) && (udev->dev.cur_status == USBD_CONFIGURED)) {
udev->dev.class_core->data_out (udev, ep_num);
udev->dev.class_core->data_out(udev, ep_num);
}
return USBD_OK;
@@ -209,8 +203,7 @@ uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num)
\param[out] none
\retval USB device operation cur_status
*/
uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num)
{
uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num) {
if (0U == ep_num) {
usb_transc *transc = &udev->dev.transc_in[0];
@@ -219,25 +212,25 @@ uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num)
/* update transfer length */
transc->remain_len -= transc->max_len;
usbd_ctl_send (udev);
usbd_ctl_send(udev);
break;
case USB_CTL_LAST_DATA_IN:
/* last packet is MPS multiple, so send ZLP packet */
if (udev->dev.control.ctl_zlp) {
usbd_ep_send (udev, 0U, NULL, 0U);
usbd_ep_send(udev, 0U, NULL, 0U);
udev->dev.control.ctl_zlp = 0U;
} else {
if (udev->dev.cur_status == USBD_CONFIGURED) {
if (udev->dev.class_core->data_in != NULL) {
udev->dev.class_core->data_in (udev, 0U);
udev->dev.class_core->data_in(udev, 0U);
}
}
transc->remain_len = 0U;
usbd_ctl_status_recev (udev);
usbd_ctl_status_recev(udev);
}
break;
@@ -246,7 +239,7 @@ uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num)
}
} else {
if ((udev->dev.cur_status == USBD_CONFIGURED) && (udev->dev.class_core->data_in != NULL)) {
udev->dev.class_core->data_in (udev, ep_num);
udev->dev.class_core->data_in(udev, ep_num);
}
}

130
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_core.c vendored
View File

@@ -32,22 +32,19 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
OF SUCH DAMAGE.
*/
#include "drv_usb_hw.h"
#include "usbh_pipe.h"
#include "usbh_enum.h"
#include "usbh_core.h"
#include "drv_usb_hw.h"
#include "drv_usbh_int.h"
#include "usbh_enum.h"
#include "usbh_pipe.h"
uint8_t usbh_sof (usb_core_driver *pudev);
uint8_t usbh_sof(usb_core_driver *pudev);
usbh_int_cb usbh_int_op =
{
usbh_sof
};
usbh_int_cb usbh_int_op = {usbh_sof};
usbh_int_cb *usbh_int_fop = &usbh_int_op;
static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost);
static usbh_status usbh_enum_task(usb_core_driver *pudev, usbh_host *puhost);
/*!
\brief USB SOF callback function from the interrupt
@@ -55,8 +52,7 @@ static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost);
\param[out] none
\retval operation status
*/
uint8_t usbh_sof (usb_core_driver *pudev)
{
uint8_t usbh_sof(usb_core_driver *pudev) {
/* this callback could be used to implement a scheduler process */
return 0U;
}
@@ -69,8 +65,7 @@ uint8_t usbh_sof (usb_core_driver *pudev)
\param[out] none
\retval operation status
*/
void usbh_init (usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost)
{
void usbh_init(usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost) {
uint8_t i = 0U;
/* host de-initializations */
@@ -86,13 +81,13 @@ void usbh_init (usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost)
pudev->host.pipe[0].ep.mps = 8U;
usb_basic_init (&pudev->bp, &pudev->regs, core);
usb_basic_init(&pudev->bp, &pudev->regs, core);
#ifndef DUAL_ROLE_MODE_ENABLED
usb_core_init (pudev->bp, &pudev->regs);
usb_core_init(pudev->bp, &pudev->regs);
usb_host_init (pudev);
usb_host_init(pudev);
#endif /* DUAL_ROLE_MODE_ENABLED */
@@ -107,8 +102,7 @@ void usbh_init (usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost)
\param[out] none
\retval operation status
*/
usbh_status usbh_deinit(usb_core_driver *pudev, usbh_host *puhost)
{
usbh_status usbh_deinit(usb_core_driver *pudev, usbh_host *puhost) {
/* software init */
puhost->cur_state = HOST_DEFAULT;
puhost->backup_state = HOST_DEFAULT;
@@ -133,8 +127,7 @@ usbh_status usbh_deinit(usb_core_driver *pudev, usbh_host *puhost)
\param[out] none
\retval none
*/
void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost)
{
void usbh_core_task(usb_core_driver *pudev, usbh_host *puhost) {
volatile usbh_status status = USBH_FAIL;
/* check for host port events */
@@ -149,9 +142,9 @@ void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost)
if (pudev->host.connect_status) {
puhost->cur_state = HOST_DETECT_DEV_SPEED;
usb_mdelay (100U);
usb_mdelay(100U);
// usb_mdelay (2U);
usb_port_reset (pudev);
usb_port_reset(pudev);
puhost->usr_cb->dev_reset();
}
@@ -160,10 +153,10 @@ void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost)
case HOST_DETECT_DEV_SPEED:
if (pudev->host.port_enabled) {
puhost->cur_state = HOST_DEV_ATTACHED;
puhost->dev_prop.speed = usb_curspeed_get (pudev);
puhost->dev_prop.speed = usb_curspeed_get(pudev);
puhost->usr_cb->dev_speed_detected(puhost->dev_prop.speed);
usb_mdelay (50U);
usb_mdelay(50U);
}
break;
@@ -173,21 +166,13 @@ void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost)
puhost->control.pipe_in_num = usbh_pipe_allocate(pudev, 0x80U);
/* reset USB device */
usb_port_reset (pudev);
usb_port_reset(pudev);
/* open IN control pipe */
usbh_pipe_create (pudev,
&puhost->dev_prop,
puhost->control.pipe_in_num,
USB_EPTYPE_CTRL,
puhost->control.max_len);
usbh_pipe_create(pudev, &puhost->dev_prop, puhost->control.pipe_in_num, USB_EPTYPE_CTRL, puhost->control.max_len);
/* open OUT control pipe */
usbh_pipe_create (pudev,
&puhost->dev_prop,
puhost->control.pipe_out_num,
USB_EPTYPE_CTRL,
puhost->control.max_len);
usbh_pipe_create(pudev, &puhost->dev_prop, puhost->control.pipe_out_num, USB_EPTYPE_CTRL, puhost->control.max_len);
puhost->cur_state = HOST_ENUM;
break;
@@ -195,7 +180,7 @@ void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost)
case HOST_ENUM:
/* check for enumeration status */
if (USBH_OK == usbh_enum_task (pudev, puhost)) {
if (USBH_OK == usbh_enum_task(pudev, puhost)) {
/* the function shall return USBH_OK when full enumeration is complete */
/* user callback for end of device basic enumeration */
@@ -220,7 +205,7 @@ void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost)
if (USBH_OK == status) {
puhost->cur_state = HOST_CLASS_HANDLER;
} else {
usbh_error_handler (puhost, status);
usbh_error_handler(puhost, status);
}
break;
@@ -228,7 +213,7 @@ void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost)
/* process class state machine */
status = puhost->class_cb->class_machine(pudev, puhost);
usbh_error_handler (puhost, status);
usbh_error_handler(puhost, status);
break;
case HOST_SUSPENDED:
@@ -236,7 +221,7 @@ void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost)
case HOST_ERROR:
/* re-initilaize host for new enumeration */
usbh_deinit (pudev, puhost);
usbh_deinit(pudev, puhost);
puhost->usr_cb->dev_deinit();
puhost->class_cb->class_deinit(pudev, puhost);
break;
@@ -265,8 +250,7 @@ void usbh_core_task (usb_core_driver *pudev, usbh_host *puhost)
\param[out] none
\retval none
*/
void usbh_error_handler (usbh_host *puhost, usbh_status err_type)
{
void usbh_error_handler(usbh_host *puhost, usbh_status err_type) {
/* error unrecovered or not supported device speed */
if ((USBH_SPEED_UNKNOWN_ERROR == err_type) || (USBH_UNRECOVERED_ERROR == err_type)) {
puhost->usr_cb->dev_error();
@@ -287,8 +271,7 @@ void usbh_error_handler (usbh_host *puhost, usbh_status err_type)
\param[out] none
\retval none
*/
static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost)
{
static usbh_status usbh_enum_task(usb_core_driver *pudev, usbh_host *puhost) {
uint8_t str_buf[64];
usbh_status status = USBH_BUSY;
@@ -298,32 +281,25 @@ static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost)
switch (puhost->enum_state) {
case ENUM_DEFAULT:
/* get device descriptor for only 1st 8 bytes : to get ep0 maxpacketsize */
if (USBH_OK == usbh_devdesc_get (pudev, puhost, 8U)) {
if (USBH_OK == usbh_devdesc_get(pudev, puhost, 8U)) {
puhost->control.max_len = puhost->dev_prop.dev_desc.bMaxPacketSize0;
/* issue reset */
usb_port_reset (pudev);
usb_port_reset(pudev);
/* modify control channels configuration for maximum packet size */
usbh_pipe_update (pudev,
puhost->control.pipe_out_num,
0U, 0U,
puhost->control.max_len);
usbh_pipe_update(pudev, puhost->control.pipe_out_num, 0U, 0U, puhost->control.max_len);
usbh_pipe_update (pudev,
puhost->control.pipe_in_num,
0U, 0U,
puhost->control.max_len);
usbh_pipe_update(pudev, puhost->control.pipe_in_num, 0U, 0U, puhost->control.max_len);
puhost->enum_state = ENUM_GET_DEV_DESC;
}
break;
case ENUM_GET_DEV_DESC:
/* get full device descriptor */
if (USBH_OK == usbh_devdesc_get (pudev, puhost, USB_DEV_DESC_LEN)) {
if (USBH_OK == usbh_devdesc_get(pudev, puhost, USB_DEV_DESC_LEN)) {
puhost->usr_cb->dev_devdesc_assigned(&puhost->dev_prop.dev_desc);
index_mfc_str = puhost->dev_prop.dev_desc.iManufacturer;
@@ -336,8 +312,8 @@ static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost)
case ENUM_SET_ADDR:
/* set address */
if (USBH_OK == usbh_setaddress (pudev, puhost, USBH_DEV_ADDR)) {
usb_mdelay (2);
if (USBH_OK == usbh_setaddress(pudev, puhost, USBH_DEV_ADDR)) {
usb_mdelay(2);
puhost->dev_prop.addr = USBH_DEV_ADDR;
@@ -345,15 +321,9 @@ static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost)
puhost->usr_cb->dev_address_set();
/* modify control channels to update device address */
usbh_pipe_update (pudev,
puhost->control.pipe_in_num,
puhost->dev_prop.addr,
0U, 0U);
usbh_pipe_update(pudev, puhost->control.pipe_in_num, puhost->dev_prop.addr, 0U, 0U);
usbh_pipe_update (pudev,
puhost->control.pipe_out_num,
puhost->dev_prop.addr,
0U, 0U);
usbh_pipe_update(pudev, puhost->control.pipe_out_num, puhost->dev_prop.addr, 0U, 0U);
puhost->enum_state = ENUM_GET_CFG_DESC;
}
@@ -361,18 +331,16 @@ static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost)
case ENUM_GET_CFG_DESC:
/* get standard configuration descriptor */
if (USBH_OK == usbh_cfgdesc_get (pudev, puhost, USB_CFG_DESC_LEN)) {
if (USBH_OK == usbh_cfgdesc_get(pudev, puhost, USB_CFG_DESC_LEN)) {
puhost->enum_state = ENUM_GET_CFG_DESC_SET;
}
break;
case ENUM_GET_CFG_DESC_SET:
/* get full config descriptor (config, interface, endpoints) */
if (USBH_OK == usbh_cfgdesc_get (pudev, puhost, puhost->dev_prop.cfg_desc.wTotalLength)) {
if (USBH_OK == usbh_cfgdesc_get(pudev, puhost, puhost->dev_prop.cfg_desc.wTotalLength)) {
/* user callback for configuration descriptors available */
puhost->usr_cb->dev_cfgdesc_assigned (&puhost->dev_prop.cfg_desc,
puhost->dev_prop.itf_desc,
puhost->dev_prop.ep_desc[0]);
puhost->usr_cb->dev_cfgdesc_assigned(&puhost->dev_prop.cfg_desc, puhost->dev_prop.itf_desc, puhost->dev_prop.ep_desc[0]);
puhost->enum_state = ENUM_GET_STR_DESC;
}
@@ -380,11 +348,7 @@ static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost)
case ENUM_GET_STR_DESC:
if (index_mfc_str) {
if (USBH_OK == usbh_strdesc_get (pudev,
puhost,
puhost->dev_prop.dev_desc.iManufacturer,
str_buf,
0xFFU)) {
if (USBH_OK == usbh_strdesc_get(pudev, puhost, puhost->dev_prop.dev_desc.iManufacturer, str_buf, 0xFFU)) {
/* user callback for manufacturing string */
puhost->usr_cb->dev_mfc_str(str_buf);
@@ -393,22 +357,14 @@ static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost)
} else {
if (index_prod_str) {
/* check that product string is available */
if (USBH_OK == usbh_strdesc_get (pudev,
puhost,
puhost->dev_prop.dev_desc.iProduct,
str_buf,
0xFFU)) {
if (USBH_OK == usbh_strdesc_get(pudev, puhost, puhost->dev_prop.dev_desc.iProduct, str_buf, 0xFFU)) {
puhost->usr_cb->dev_prod_str(str_buf);
index_prod_str = 0U;
}
} else {
if (index_serial_str) {
if (USBH_OK == usbh_strdesc_get (pudev,
puhost,
puhost->dev_prop.dev_desc.iSerialNumber,
str_buf,
0xFFU)) {
if (USBH_OK == usbh_strdesc_get(pudev, puhost, puhost->dev_prop.dev_desc.iSerialNumber, str_buf, 0xFFU)) {
puhost->usr_cb->dev_seral_str(str_buf);
puhost->enum_state = ENUM_SET_CONFIGURATION;
@@ -422,9 +378,7 @@ static usbh_status usbh_enum_task (usb_core_driver *pudev, usbh_host *puhost)
break;
case ENUM_SET_CONFIGURATION:
if (USBH_OK == usbh_setcfg (pudev,
puhost,
puhost->dev_prop.cfg_desc.bConfigurationValue)) {
if (USBH_OK == usbh_setcfg(pudev, puhost, puhost->dev_prop.cfg_desc.bConfigurationValue)) {
puhost->enum_state = ENUM_DEV_CONFIGURED;
}
break;

202
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_enum.c vendored
View File

@@ -32,16 +32,15 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
OF SUCH DAMAGE.
*/
#include "usbh_transc.h"
#include "usbh_enum.h"
#include "usbh_transc.h"
static void usbh_devdesc_parse (usb_desc_dev *cfg_desc, uint8_t *buf, uint16_t len);
static void usbh_cfgset_parse (usb_dev_prop *udev, uint8_t *buf);
static void usbh_cfgdesc_parse (usb_desc_config *cfg_desc, uint8_t *buf);
static void usbh_itfdesc_parse (usb_desc_itf *itf_desc, uint8_t *buf);
static void usbh_epdesc_parse (usb_desc_ep *ep_desc, uint8_t *buf);
static void usbh_strdesc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len);
static void usbh_devdesc_parse(usb_desc_dev *cfg_desc, uint8_t *buf, uint16_t len);
static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf);
static void usbh_cfgdesc_parse(usb_desc_config *cfg_desc, uint8_t *buf);
static void usbh_itfdesc_parse(usb_desc_itf *itf_desc, uint8_t *buf);
static void usbh_epdesc_parse(usb_desc_ep *ep_desc, uint8_t *buf);
static void usbh_strdesc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len);
/*!
\brief configure USB control status parameters
@@ -51,8 +50,7 @@ static void usbh_strdesc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len);
\param[out] none
\retval none
*/
void usbh_ctlstate_config (usbh_host *puhost, uint8_t *buf, uint16_t len)
{
void usbh_ctlstate_config(usbh_host *puhost, uint8_t *buf, uint16_t len) {
/* prepare the transactions */
puhost->control.buf = buf;
puhost->control.ctl_len = len;
@@ -68,29 +66,23 @@ void usbh_ctlstate_config (usbh_host *puhost, uint8_t *buf, uint16_t len)
\param[out] none
\retval operation status
*/
usbh_status usbh_devdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint8_t len)
{
usbh_status usbh_devdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint8_t len) {
usbh_status status = USBH_BUSY;
usbh_control *usb_ctl = &puhost->control;
if (CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_GET_DESCRIPTOR,
.wValue = USBH_DESC(USB_DESCTYPE_DEV),
.wIndex = 0U,
.wLength = len
};
usb_ctl->setup.req
= (usb_req){.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_GET_DESCRIPTOR, .wValue = USBH_DESC(USB_DESCTYPE_DEV), .wIndex = 0U, .wLength = len};
usbh_ctlstate_config (puhost, pudev->host.rx_buf, len);
usbh_ctlstate_config(puhost, pudev->host.rx_buf, len);
}
status = usbh_ctl_handler (pudev, puhost);
status = usbh_ctl_handler(pudev, puhost);
if (USBH_OK == status) {
/* commands successfully sent and response received */
usbh_devdesc_parse (&puhost->dev_prop.dev_desc, pudev->host.rx_buf, len);
usbh_devdesc_parse(&puhost->dev_prop.dev_desc, pudev->host.rx_buf, len);
}
return status;
@@ -104,31 +96,25 @@ usbh_status usbh_devdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint8_t
\param[out] none
\retval operation status
*/
usbh_status usbh_cfgdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint16_t len)
{
usbh_status usbh_cfgdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint16_t len) {
usbh_status status = USBH_BUSY;
usbh_control *usb_ctl = &puhost->control;
if (CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_GET_DESCRIPTOR,
.wValue = USBH_DESC(USB_DESCTYPE_CONFIG),
.wIndex = 0U,
.wLength = len
};
usb_ctl->setup.req
= (usb_req){.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_GET_DESCRIPTOR, .wValue = USBH_DESC(USB_DESCTYPE_CONFIG), .wIndex = 0U, .wLength = len};
usbh_ctlstate_config (puhost, pudev->host.rx_buf, len);
usbh_ctlstate_config(puhost, pudev->host.rx_buf, len);
}
status = usbh_ctl_handler (pudev, puhost);
status = usbh_ctl_handler(pudev, puhost);
if (USBH_OK == status) {
if (len <= USB_CFG_DESC_LEN) {
usbh_cfgdesc_parse (&puhost->dev_prop.cfg_desc, pudev->host.rx_buf);
usbh_cfgdesc_parse(&puhost->dev_prop.cfg_desc, pudev->host.rx_buf);
} else {
usbh_cfgset_parse (&puhost->dev_prop, pudev->host.rx_buf);
usbh_cfgset_parse(&puhost->dev_prop, pudev->host.rx_buf);
}
}
@@ -145,33 +131,23 @@ usbh_status usbh_cfgdesc_get (usb_core_driver *pudev, usbh_host *puhost, uint16_
\param[out] none
\retval operation status
*/
usbh_status usbh_strdesc_get (usb_core_driver *pudev,
usbh_host *puhost,
uint8_t str_index,
uint8_t *buf,
uint16_t len)
{
usbh_status usbh_strdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint8_t str_index, uint8_t *buf, uint16_t len) {
usbh_status status = USBH_BUSY;
usbh_control *usb_ctl = &puhost->control;
if (CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_GET_DESCRIPTOR,
.wValue = USBH_DESC(USB_DESCTYPE_STR) | str_index,
.wIndex = 0x0409U,
.wLength = len
};
usb_ctl->setup.req = (usb_req){
.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_GET_DESCRIPTOR, .wValue = USBH_DESC(USB_DESCTYPE_STR) | str_index, .wIndex = 0x0409U, .wLength = len};
usbh_ctlstate_config (puhost, pudev->host.rx_buf, len);
usbh_ctlstate_config(puhost, pudev->host.rx_buf, len);
}
status = usbh_ctl_handler (pudev, puhost);
status = usbh_ctl_handler(pudev, puhost);
if (USBH_OK == status) {
/* commands successfully sent and response received */
usbh_strdesc_parse (pudev->host.rx_buf, buf, len);
usbh_strdesc_parse(pudev->host.rx_buf, buf, len);
}
return status;
@@ -185,25 +161,18 @@ usbh_status usbh_strdesc_get (usb_core_driver *pudev,
\param[out] none
\retval operation status
*/
usbh_status usbh_setaddress (usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr)
{
usbh_status usbh_setaddress(usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr) {
usbh_status status = USBH_BUSY;
usbh_control *usb_ctl = &puhost->control;
if (CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_SET_ADDRESS,
.wValue = (uint16_t)dev_addr,
.wIndex = 0U,
.wLength = 0U
};
usb_ctl->setup.req = (usb_req){.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_SET_ADDRESS, .wValue = (uint16_t)dev_addr, .wIndex = 0U, .wLength = 0U};
usbh_ctlstate_config (puhost, NULL, 0U);
usbh_ctlstate_config(puhost, NULL, 0U);
}
status = usbh_ctl_handler (pudev, puhost);
status = usbh_ctl_handler(pudev, puhost);
return status;
}
@@ -216,25 +185,18 @@ usbh_status usbh_setaddress (usb_core_driver *pudev, usbh_host *puhost, uint8_t
\param[out] none
\retval operation status
*/
usbh_status usbh_setcfg (usb_core_driver *pudev, usbh_host *puhost, uint16_t config_index)
{
usbh_status usbh_setcfg(usb_core_driver *pudev, usbh_host *puhost, uint16_t config_index) {
usbh_status status = USBH_BUSY;
usbh_control *usb_ctl = &puhost->control;
if (CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD,
.bRequest = USB_SET_CONFIGURATION,
.wValue = config_index,
.wIndex = 0U,
.wLength = 0U
};
usb_ctl->setup.req = (usb_req){.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_SET_CONFIGURATION, .wValue = config_index, .wIndex = 0U, .wLength = 0U};
usbh_ctlstate_config (puhost, NULL, 0U);
usbh_ctlstate_config(puhost, NULL, 0U);
}
status = usbh_ctl_handler (pudev, puhost);
status = usbh_ctl_handler(pudev, puhost);
return status;
}
@@ -248,28 +210,18 @@ usbh_status usbh_setcfg (usb_core_driver *pudev, usbh_host *puhost, uint16_t con
\param[out] none
\retval operation status
*/
usbh_status usbh_setinterface (usb_core_driver *pudev,
usbh_host *puhost,
uint8_t ep_num,
uint8_t set)
{
usbh_status usbh_setinterface(usb_core_driver *pudev, usbh_host *puhost, uint8_t ep_num, uint8_t set) {
usbh_status status = USBH_BUSY;
usbh_control *usb_ctl = &puhost->control;
if (CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_STRD,
.bRequest = USB_SET_INTERFACE,
.wValue = set,
.wIndex = ep_num,
.wLength = 0U
};
usb_ctl->setup.req = (usb_req){.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, .bRequest = USB_SET_INTERFACE, .wValue = set, .wIndex = ep_num, .wLength = 0U};
usbh_ctlstate_config (puhost, NULL, 0U);
usbh_ctlstate_config(puhost, NULL, 0U);
}
status = usbh_ctl_handler (pudev, puhost);
status = usbh_ctl_handler(pudev, puhost);
return status;
}
@@ -283,23 +235,13 @@ usbh_status usbh_setinterface (usb_core_driver *pudev,
\param[out] none
\retval operation status
*/
usbh_status usbh_clrfeature (usb_core_driver *pudev,
usbh_host *puhost,
uint8_t ep_addr,
uint8_t pp_num)
{
usbh_status usbh_clrfeature(usb_core_driver *pudev, usbh_host *puhost, uint8_t ep_addr, uint8_t pp_num) {
usbh_status status = USBH_BUSY;
usbh_control *usb_ctl = &puhost->control;
if (CTL_IDLE == usb_ctl->ctl_state) {
usb_ctl->setup.req = (usb_req) {
.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_EP | USB_REQTYPE_STRD,
.bRequest = USB_CLEAR_FEATURE,
.wValue = FEATURE_SELECTOR_EP,
.wIndex = ep_addr,
.wLength = 0
};
usb_ctl->setup.req = (usb_req){.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_EP | USB_REQTYPE_STRD, .bRequest = USB_CLEAR_FEATURE, .wValue = FEATURE_SELECTOR_EP, .wIndex = ep_addr, .wLength = 0};
if (EP_DIR(ep_addr)) {
pudev->host.pipe[pp_num].data_toggle_in = 0U;
@@ -307,10 +249,10 @@ usbh_status usbh_clrfeature (usb_core_driver *pudev,
pudev->host.pipe[pp_num].data_toggle_out = 0U;
}
usbh_ctlstate_config (puhost, NULL, 0U);
usbh_ctlstate_config(puhost, NULL, 0U);
}
status = usbh_ctl_handler (pudev, puhost);
status = usbh_ctl_handler(pudev, puhost);
return status;
}
@@ -323,20 +265,14 @@ usbh_status usbh_clrfeature (usb_core_driver *pudev,
\param[out] none
\retval operation status
*/
static void usbh_devdesc_parse (usb_desc_dev *dev_desc, uint8_t *buf, uint16_t len)
{
*dev_desc = (usb_desc_dev) {
.header = {
.bLength = *(uint8_t *)(buf + 0U),
.bDescriptorType = *(uint8_t *)(buf + 1U)
},
static void usbh_devdesc_parse(usb_desc_dev *dev_desc, uint8_t *buf, uint16_t len) {
*dev_desc = (usb_desc_dev){.header = {.bLength = *(uint8_t *)(buf + 0U), .bDescriptorType = *(uint8_t *)(buf + 1U)},
.bcdUSB = BYTE_SWAP(buf + 2U),
.bDeviceClass = *(uint8_t *)(buf + 4U),
.bDeviceSubClass = *(uint8_t *)(buf + 5U),
.bDeviceProtocol = *(uint8_t *)(buf + 6U),
.bMaxPacketSize0 = *(uint8_t *)(buf + 7U)
};
.bMaxPacketSize0 = *(uint8_t *)(buf + 7U)};
if (len > 8U) {
/* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */
@@ -357,8 +293,7 @@ static void usbh_devdesc_parse (usb_desc_dev *dev_desc, uint8_t *buf, uint16_t
\param[out] none
\retval operation status
*/
static void usbh_cfgdesc_parse (usb_desc_config *cfg_desc, uint8_t *buf)
{
static void usbh_cfgdesc_parse(usb_desc_config *cfg_desc, uint8_t *buf) {
/* parse configuration descriptor */
*cfg_desc = (usb_desc_config) {
.header = {
@@ -382,9 +317,8 @@ static void usbh_cfgdesc_parse (usb_desc_config *cfg_desc, uint8_t *buf)
\param[out] none
\retval operation status
*/
static void usbh_cfgset_parse (usb_dev_prop *udev, uint8_t *buf)
{
usb_desc_ep *ep = NULL;
static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf) {
usb_desc_ep * ep = NULL;
usb_desc_itf *itf = NULL, itf_value;
usb_desc_header *pdesc = (usb_desc_header *)buf;
@@ -396,7 +330,7 @@ static void usbh_cfgset_parse (usb_dev_prop *udev, uint8_t *buf)
uint16_t prev_ep_len = 0U;
/* parse configuration descriptor */
usbh_cfgdesc_parse (&udev->cfg_desc, buf);
usbh_cfgdesc_parse(&udev->cfg_desc, buf);
ptr = USB_CFG_DESC_LEN;
@@ -405,38 +339,38 @@ static void usbh_cfgset_parse (usb_dev_prop *udev, uint8_t *buf)
}
while (ptr < udev->cfg_desc.wTotalLength) {
pdesc = usbh_nextdesc_get ((uint8_t *)pdesc, &ptr);
pdesc = usbh_nextdesc_get((uint8_t *)pdesc, &ptr);
if (pdesc->bDescriptorType == USB_DESCTYPE_ITF) {
itf_index = *(((uint8_t *)pdesc) + 2U);
itf = &udev->itf_desc[itf_index];
if ((*((uint8_t *)pdesc + 3U)) < 3U) {
usbh_itfdesc_parse (&itf_value, (uint8_t *)pdesc);
usbh_itfdesc_parse(&itf_value, (uint8_t *)pdesc);
/* parse endpoint descriptors relative to the current interface */
if (itf_value.bNumEndpoints > USBH_MAX_EP_NUM) {
return;
}
for (ep_index = 0; ep_index < itf_value.bNumEndpoints; ) {
pdesc = usbh_nextdesc_get ((void*)pdesc, &ptr);
for (ep_index = 0; ep_index < itf_value.bNumEndpoints;) {
pdesc = usbh_nextdesc_get((void *)pdesc, &ptr);
if (pdesc->bDescriptorType == USB_DESCTYPE_EP) {
ep = &udev->ep_desc[itf_index][ep_index];
if (prev_itf != itf_index) {
prev_itf = itf_index;
usbh_itfdesc_parse (itf, (uint8_t *)&itf_value);
usbh_itfdesc_parse(itf, (uint8_t *)&itf_value);
} else {
if (prev_ep_len > BYTE_SWAP((uint8_t *)pdesc + 4U)) {
break;
} else {
usbh_itfdesc_parse (itf, (uint8_t *)&itf_value);
usbh_itfdesc_parse(itf, (uint8_t *)&itf_value);
}
}
usbh_epdesc_parse (ep, (uint8_t *)pdesc);
usbh_epdesc_parse(ep, (uint8_t *)pdesc);
prev_ep_len = BYTE_SWAP((uint8_t *)pdesc + 4U);
ep_index++;
}
@@ -453,8 +387,7 @@ static void usbh_cfgset_parse (usb_dev_prop *udev, uint8_t *buf)
\param[out] none
\retval operation status
*/
static void usbh_itfdesc_parse (usb_desc_itf *itf_desc, uint8_t *buf)
{
static void usbh_itfdesc_parse(usb_desc_itf *itf_desc, uint8_t *buf) {
*itf_desc = (usb_desc_itf) {
.header = {
.bLength = *(uint8_t *)(buf + 0U),
@@ -478,19 +411,13 @@ static void usbh_itfdesc_parse (usb_desc_itf *itf_desc, uint8_t *buf)
\param[out] none
\retval operation status
*/
static void usbh_epdesc_parse (usb_desc_ep *ep_desc, uint8_t *buf)
{
*ep_desc = (usb_desc_ep) {
.header = {
.bLength = *(uint8_t *)(buf + 0U),
.bDescriptorType = *(uint8_t *)(buf + 1U)
},
static void usbh_epdesc_parse(usb_desc_ep *ep_desc, uint8_t *buf) {
*ep_desc = (usb_desc_ep){.header = {.bLength = *(uint8_t *)(buf + 0U), .bDescriptorType = *(uint8_t *)(buf + 1U)},
.bEndpointAddress = *(uint8_t *)(buf + 2U),
.bmAttributes = *(uint8_t *)(buf + 3U),
.wMaxPacketSize = BYTE_SWAP(buf + 4U),
.bInterval = *(uint8_t *)(buf + 6U)
};
.bInterval = *(uint8_t *)(buf + 6U)};
}
/*!
@@ -501,8 +428,7 @@ static void usbh_epdesc_parse (usb_desc_ep *ep_desc, uint8_t *buf)
\param[out] none
\retval operation status
*/
static void usbh_strdesc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len)
{
static void usbh_strdesc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len) {
uint16_t str_len = 0U, index = 0U;
/* the unicode string descriptor is not NULL-terminated. The string length is
@@ -536,8 +462,7 @@ static void usbh_strdesc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len)
\param[out] none
\retval operation status
*/
usb_desc_header *usbh_nextdesc_get (uint8_t *pbuf, uint16_t *ptr)
{
usb_desc_header *usbh_nextdesc_get(uint8_t *pbuf, uint16_t *ptr) {
usb_desc_header *pnext;
*ptr += ((usb_desc_header *)pbuf)->bLength;
@@ -546,4 +471,3 @@ usb_desc_header *usbh_nextdesc_get (uint8_t *pbuf, uint16_t *ptr)
return (pnext);
}

36
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_pipe.c vendored
View File

@@ -34,7 +34,7 @@ OF SUCH DAMAGE.
#include "usbh_pipe.h"
static uint16_t usbh_freepipe_get (usb_core_driver *pudev);
static uint16_t usbh_freepipe_get(usb_core_driver *pudev);
/*!
\brief create a pipe
@@ -46,12 +46,7 @@ static uint16_t usbh_freepipe_get (usb_core_driver *pudev);
\param[out] none
\retval operation status
*/
uint8_t usbh_pipe_create (usb_core_driver *pudev,
usb_dev_prop *udev,
uint8_t pp_num,
uint8_t ep_type,
uint16_t ep_mpl)
{
uint8_t usbh_pipe_create(usb_core_driver *pudev, usb_dev_prop *udev, uint8_t pp_num, uint8_t ep_type, uint16_t ep_mpl) {
usb_pipe *pp = &pudev->host.pipe[pp_num];
pp->dev_addr = udev->addr;
@@ -60,7 +55,7 @@ uint8_t usbh_pipe_create (usb_core_driver *pudev,
pp->ep.mps = ep_mpl;
pp->ping = udev->speed == PORT_SPEED_HIGH;
usb_pipe_init (pudev, pp_num);
usb_pipe_init(pudev, pp_num);
return HC_OK;
}
@@ -76,12 +71,7 @@ uint8_t usbh_pipe_create (usb_core_driver *pudev,
\param[out] none
\retval operation status
*/
uint8_t usbh_pipe_update (usb_core_driver *pudev,
uint8_t pp_num,
uint8_t dev_addr,
uint32_t dev_speed,
uint16_t ep_mpl)
{
uint8_t usbh_pipe_update(usb_core_driver *pudev, uint8_t pp_num, uint8_t dev_addr, uint32_t dev_speed, uint16_t ep_mpl) {
usb_pipe *pp = &pudev->host.pipe[pp_num];
if ((pp->dev_addr != dev_addr) && (dev_addr)) {
@@ -96,7 +86,7 @@ uint8_t usbh_pipe_update (usb_core_driver *pudev,
pp->ep.mps = ep_mpl;
}
usb_pipe_init (pudev, pp_num);
usb_pipe_init(pudev, pp_num);
return HC_OK;
}
@@ -108,9 +98,8 @@ uint8_t usbh_pipe_update (usb_core_driver *pudev,
\param[out] none
\retval operation status
*/
uint8_t usbh_pipe_allocate (usb_core_driver *pudev, uint8_t ep_addr)
{
uint16_t pp_num = usbh_freepipe_get (pudev);
uint8_t usbh_pipe_allocate(usb_core_driver *pudev, uint8_t ep_addr) {
uint16_t pp_num = usbh_freepipe_get(pudev);
if (HC_ERROR != pp_num) {
pudev->host.pipe[pp_num].in_used = 1U;
@@ -128,8 +117,7 @@ uint8_t usbh_pipe_allocate (usb_core_driver *pudev, uint8_t ep_addr)
\param[out] none
\retval operation status
*/
uint8_t usbh_pipe_free (usb_core_driver *pudev, uint8_t pp_num)
{
uint8_t usbh_pipe_free(usb_core_driver *pudev, uint8_t pp_num) {
if (pp_num < HC_MAX) {
pudev->host.pipe[pp_num].in_used = 0U;
}
@@ -143,12 +131,11 @@ uint8_t usbh_pipe_free (usb_core_driver *pudev, uint8_t pp_num)
\param[out] none
\retval operation status
*/
uint8_t usbh_pipe_delete (usb_core_driver *pudev)
{
uint8_t usbh_pipe_delete(usb_core_driver *pudev) {
uint8_t pp_num = 0U;
for (pp_num = 2U; pp_num < HC_MAX; pp_num++) {
pudev->host.pipe[pp_num] = (usb_pipe) {0};
pudev->host.pipe[pp_num] = (usb_pipe){0};
}
return USBH_OK;
@@ -160,8 +147,7 @@ uint8_t usbh_pipe_delete (usb_core_driver *pudev)
\param[out] none
\retval operation status
*/
static uint16_t usbh_freepipe_get (usb_core_driver *pudev)
{
static uint16_t usbh_freepipe_get(usb_core_driver *pudev) {
uint8_t pp_num = 0U;
for (pp_num = 0U; pp_num < HC_MAX; pp_num++) {

85
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_transc.c vendored
View File

@@ -32,8 +32,8 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
OF SUCH DAMAGE.
*/
#include "drv_usb_hw.h"
#include "usbh_transc.h"
#include "drv_usb_hw.h"
/*!
\brief prepare a pipe and start a transfer
@@ -42,12 +42,11 @@ OF SUCH DAMAGE.
\param[out] none
\retval operation status
*/
static uint32_t usbh_request_submit (usb_core_driver *pudev, uint8_t pp_num)
{
static uint32_t usbh_request_submit(usb_core_driver *pudev, uint8_t pp_num) {
pudev->host.pipe[pp_num].urb_state = URB_IDLE;
pudev->host.pipe[pp_num].xfer_count = 0U;
return usb_pipe_xfer (pudev, pp_num);
return usb_pipe_xfer(pudev, pp_num);
}
/*!
@@ -58,15 +57,14 @@ static uint32_t usbh_request_submit (usb_core_driver *pudev, uint8_t pp_num)
\param[out] none
\retval operation status
*/
usbh_status usbh_ctlsetup_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num)
{
usbh_status usbh_ctlsetup_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num) {
usb_pipe *pp = &pudev->host.pipe[pp_num];
pp->DPID = PIPE_DPID_SETUP;
pp->xfer_buf = buf;
pp->xfer_len = USB_SETUP_PACKET_LEN;
return (usbh_status)usbh_request_submit (pudev, pp_num);
return (usbh_status)usbh_request_submit(pudev, pp_num);
}
/*!
@@ -78,8 +76,7 @@ usbh_status usbh_ctlsetup_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp
\param[out] none
\retval operation status
*/
usbh_status usbh_data_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len)
{
usbh_status usbh_data_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len) {
usb_pipe *pp = &pudev->host.pipe[pp_num];
pp->xfer_buf = buf;
@@ -112,7 +109,7 @@ usbh_status usbh_data_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num
break;
}
usbh_request_submit (pudev, pp_num);
usbh_request_submit(pudev, pp_num);
return USBH_OK;
}
@@ -126,8 +123,7 @@ usbh_status usbh_data_send (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num
\param[out] none
\retval operation status
*/
usbh_status usbh_data_recev (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len)
{
usbh_status usbh_data_recev(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len) {
usb_pipe *pp = &pudev->host.pipe[pp_num];
pp->xfer_buf = buf;
@@ -157,7 +153,7 @@ usbh_status usbh_data_recev (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_nu
break;
}
usbh_request_submit (pudev, pp_num);
usbh_request_submit(pudev, pp_num);
return USBH_OK;
}
@@ -171,8 +167,7 @@ usbh_status usbh_data_recev (usb_core_driver *pudev, uint8_t *buf, uint8_t pp_nu
\param[out] none
\retval USB URB state
*/
static usb_urb_state usbh_urb_wait (usb_core_driver *pudev, usbh_host *puhost, uint8_t pp_num, uint32_t wait_time)
{
static usb_urb_state usbh_urb_wait(usb_core_driver *pudev, usbh_host *puhost, uint8_t pp_num, uint32_t wait_time) {
usb_urb_state urb_status = URB_IDLE;
while (URB_DONE != (urb_status = usbh_urbstate_get(pudev, pp_num))) {
@@ -184,8 +179,7 @@ static usb_urb_state usbh_urb_wait (usb_core_driver *pudev, usbh_host *puhost, u
} else if (URB_ERROR == urb_status) {
puhost->control.ctl_state = CTL_ERROR;
break;
} else if ((wait_time > 0U) && \
((usb_curframe_get(pudev)- puhost->control.timer) > wait_time)) {
} else if ((wait_time > 0U) && ((usb_curframe_get(pudev) - puhost->control.timer) > wait_time)) {
/* timeout for in transfer */
puhost->control.ctl_state = CTL_ERROR;
break;
@@ -204,16 +198,13 @@ static usb_urb_state usbh_urb_wait (usb_core_driver *pudev, usbh_host *puhost, u
\param[out] none
\retval none
*/
static void usbh_setup_transc (usb_core_driver *pudev, usbh_host *puhost)
{
static void usbh_setup_transc(usb_core_driver *pudev, usbh_host *puhost) {
usb_urb_state urb_status = URB_IDLE;
/* send a SETUP packet */
usbh_ctlsetup_send (pudev,
puhost->control.setup.data,
puhost->control.pipe_out_num);
usbh_ctlsetup_send(pudev, puhost->control.setup.data, puhost->control.pipe_out_num);
urb_status = usbh_urb_wait (pudev, puhost, puhost->control.pipe_out_num, 0U);
urb_status = usbh_urb_wait(pudev, puhost, puhost->control.pipe_out_num, 0U);
if (URB_DONE == urb_status) {
uint8_t dir = (puhost->control.setup.req.bmRequestType & USB_TRX_MASK);
@@ -244,16 +235,12 @@ static void usbh_setup_transc (usb_core_driver *pudev, usbh_host *puhost)
\param[out] none
\retval none
*/
static void usbh_data_in_transc (usb_core_driver *pudev, usbh_host *puhost)
{
static void usbh_data_in_transc(usb_core_driver *pudev, usbh_host *puhost) {
usb_urb_state urb_status = URB_IDLE;
usbh_data_recev (pudev,
puhost->control.buf,
puhost->control.pipe_in_num,
puhost->control.ctl_len);
usbh_data_recev(pudev, puhost->control.buf, puhost->control.pipe_in_num, puhost->control.ctl_len);
urb_status = usbh_urb_wait (pudev, puhost, puhost->control.pipe_in_num, DATA_STAGE_TIMEOUT);
urb_status = usbh_urb_wait(pudev, puhost, puhost->control.pipe_in_num, DATA_STAGE_TIMEOUT);
if (URB_DONE == urb_status) {
puhost->control.ctl_state = CTL_STATUS_OUT;
@@ -269,18 +256,14 @@ static void usbh_data_in_transc (usb_core_driver *pudev, usbh_host *puhost)
\param[out] none
\retval none
*/
static void usbh_data_out_transc (usb_core_driver *pudev, usbh_host *puhost)
{
static void usbh_data_out_transc(usb_core_driver *pudev, usbh_host *puhost) {
usb_urb_state urb_status = URB_IDLE;
pudev->host.pipe[puhost->control.pipe_out_num].data_toggle_out = 1U;
usbh_data_send (pudev,
puhost->control.buf,
puhost->control.pipe_out_num,
puhost->control.ctl_len);
usbh_data_send(pudev, puhost->control.buf, puhost->control.pipe_out_num, puhost->control.ctl_len);
urb_status = usbh_urb_wait (pudev, puhost, puhost->control.pipe_out_num, DATA_STAGE_TIMEOUT);
urb_status = usbh_urb_wait(pudev, puhost, puhost->control.pipe_out_num, DATA_STAGE_TIMEOUT);
if (URB_DONE == urb_status) {
puhost->control.ctl_state = CTL_STATUS_IN;
@@ -296,15 +279,14 @@ static void usbh_data_out_transc (usb_core_driver *pudev, usbh_host *puhost)
\param[out] none
\retval none
*/
static void usbh_status_in_transc (usb_core_driver *pudev, usbh_host *puhost)
{
static void usbh_status_in_transc(usb_core_driver *pudev, usbh_host *puhost) {
uint8_t pp_num = puhost->control.pipe_in_num;
usb_urb_state urb_status = URB_IDLE;
usbh_data_recev (pudev, NULL, pp_num, 0U);
usbh_data_recev(pudev, NULL, pp_num, 0U);
urb_status = usbh_urb_wait (pudev, puhost, pp_num, NODATA_STAGE_TIMEOUT);
urb_status = usbh_urb_wait(pudev, puhost, pp_num, NODATA_STAGE_TIMEOUT);
if (URB_DONE == urb_status) {
puhost->control.ctl_state = CTL_FINISH;
@@ -318,17 +300,16 @@ static void usbh_status_in_transc (usb_core_driver *pudev, usbh_host *puhost)
\param[out] none
\retval none
*/
static void usbh_status_out_transc (usb_core_driver *pudev, usbh_host *puhost)
{
static void usbh_status_out_transc(usb_core_driver *pudev, usbh_host *puhost) {
uint8_t pp_num = puhost->control.pipe_out_num;
usb_urb_state urb_status = URB_IDLE;
pudev->host.pipe[pp_num].data_toggle_out ^= 1U;
usbh_data_send (pudev, NULL, pp_num, 0U);
usbh_data_send(pudev, NULL, pp_num, 0U);
urb_status = usbh_urb_wait (pudev, puhost, pp_num, NODATA_STAGE_TIMEOUT);
urb_status = usbh_urb_wait(pudev, puhost, pp_num, NODATA_STAGE_TIMEOUT);
if (URB_DONE == urb_status) {
puhost->control.ctl_state = CTL_FINISH;
@@ -342,29 +323,28 @@ static void usbh_status_out_transc (usb_core_driver *pudev, usbh_host *puhost)
\param[out] none
\retval operation status
*/
usbh_status usbh_ctl_handler (usb_core_driver *pudev, usbh_host *puhost)
{
usbh_status usbh_ctl_handler(usb_core_driver *pudev, usbh_host *puhost) {
usbh_status status = USBH_BUSY;
switch (puhost->control.ctl_state) {
case CTL_SETUP:
usbh_setup_transc (pudev, puhost);
usbh_setup_transc(pudev, puhost);
break;
case CTL_DATA_IN:
usbh_data_in_transc (pudev, puhost);
usbh_data_in_transc(pudev, puhost);
break;
case CTL_DATA_OUT:
usbh_data_out_transc (pudev, puhost);
usbh_data_out_transc(pudev, puhost);
break;
case CTL_STATUS_IN:
usbh_status_in_transc (pudev, puhost);
usbh_status_in_transc(pudev, puhost);
break;
case CTL_STATUS_OUT:
usbh_status_out_transc (pudev, puhost);
usbh_status_out_transc(pudev, puhost);
break;
case CTL_FINISH:
@@ -388,4 +368,3 @@ usbh_status usbh_ctl_handler (usb_core_driver *pudev, usbh_host *puhost)
return status;
}

301
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_adc.c vendored
View File

@@ -63,9 +63,8 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void adc_deinit(uint32_t adc_periph)
{
switch(adc_periph){
void adc_deinit(uint32_t adc_periph) {
switch (adc_periph) {
case ADC0:
/* reset ADC0 */
rcu_periph_reset_enable(RCU_ADC0RST);
@@ -99,8 +98,7 @@ void adc_deinit(uint32_t adc_periph)
\param[out] none
\retval none
*/
void adc_mode_config(uint32_t adc_periph, uint32_t mode)
{
void adc_mode_config(uint32_t adc_periph, uint32_t mode) {
ADC_CTL0(adc_periph) &= ~(ADC_CTL0_SYNCM);
ADC_CTL0(adc_periph) |= mode;
}
@@ -117,31 +115,30 @@ void adc_mode_config(uint32_t adc_periph, uint32_t mode)
\param[out] none
\retval none
*/
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
{
if(newvalue){
if(0U != (function & ADC_SCAN_MODE)){
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) {
if (newvalue) {
if (0U != (function & ADC_SCAN_MODE)) {
/* enable scan mode */
ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
}
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
if (0U != (function & ADC_INSERTED_CHANNEL_AUTO)) {
/* enable inserted channel group convert automatically */
ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
}
if(0U != (function & ADC_CONTINUOUS_MODE)){
if (0U != (function & ADC_CONTINUOUS_MODE)) {
/* enable continuous mode */
ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
}
}else{
if(0U != (function & ADC_SCAN_MODE)){
} else {
if (0U != (function & ADC_SCAN_MODE)) {
/* disable scan mode */
ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
}
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
if (0U != (function & ADC_INSERTED_CHANNEL_AUTO)) {
/* disable inserted channel group convert automatically */
ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
}
if(0U != (function & ADC_CONTINUOUS_MODE)){
if (0U != (function & ADC_CONTINUOUS_MODE)) {
/* disable continuous mode */
ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
}
@@ -158,12 +155,11 @@ void adc_special_function_config(uint32_t adc_periph, uint32_t function, Control
\param[out] none
\retval none
*/
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
{
if(ADC_DATAALIGN_RIGHT != data_alignment){
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) {
if (ADC_DATAALIGN_RIGHT != data_alignment) {
/* MSB alignment */
ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
}else{
} else {
/* LSB alignment */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
}
@@ -175,9 +171,8 @@ void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
\param[out] none
\retval none
*/
void adc_enable(uint32_t adc_periph)
{
if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
void adc_enable(uint32_t adc_periph) {
if (RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) {
/* enable ADC */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
}
@@ -189,8 +184,7 @@ void adc_enable(uint32_t adc_periph)
\param[out] none
\retval none
*/
void adc_disable(uint32_t adc_periph)
{
void adc_disable(uint32_t adc_periph) {
/* disable ADC */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
}
@@ -201,18 +195,15 @@ void adc_disable(uint32_t adc_periph)
\param[out] none
\retval none
*/
void adc_calibration_enable(uint32_t adc_periph)
{
void adc_calibration_enable(uint32_t adc_periph) {
/* reset the selected ADC1 calibration registers */
ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_RSTCLB;
/* check the RSTCLB bit state */
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
}
while (RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) {}
/* enable ADC calibration process */
ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
/* check the CLB bit state */
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
}
while (RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) {}
}
/*!
@@ -221,8 +212,7 @@ void adc_calibration_enable(uint32_t adc_periph)
\param[out] none
\retval none
*/
void adc_tempsensor_vrefint_enable(void)
{
void adc_tempsensor_vrefint_enable(void) {
/* enable the temperature sensor and Vrefint channel */
ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
}
@@ -233,8 +223,7 @@ void adc_tempsensor_vrefint_enable(void)
\param[out] none
\retval none
*/
void adc_tempsensor_vrefint_disable(void)
{
void adc_tempsensor_vrefint_disable(void) {
/* disable the temperature sensor and Vrefint channel */
ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
}
@@ -245,8 +234,7 @@ void adc_tempsensor_vrefint_disable(void)
\param[out] none
\retval none
*/
void adc_dma_mode_enable(uint32_t adc_periph)
{
void adc_dma_mode_enable(uint32_t adc_periph) {
/* enable DMA request */
ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
}
@@ -257,8 +245,7 @@ void adc_dma_mode_enable(uint32_t adc_periph)
\param[out] none
\retval none
*/
void adc_dma_mode_disable(uint32_t adc_periph)
{
void adc_dma_mode_disable(uint32_t adc_periph) {
/* disable DMA request */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
}
@@ -276,11 +263,10 @@ void adc_dma_mode_disable(uint32_t adc_periph)
\param[out] none
\retval none
*/
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
{
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) {
/* disable discontinuous mode of regular & inserted channel */
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
switch(adc_channel_group){
switch (adc_channel_group) {
case ADC_REGULAR_CHANNEL:
/* config the number of conversions in discontinuous mode */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
@@ -312,18 +298,17 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou
\param[out] none
\retval none
*/
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
{
switch(adc_channel_group){
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) {
switch (adc_channel_group) {
case ADC_REGULAR_CHANNEL:
/* configure the length of regular channel group */
ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
break;
case ADC_INSERTED_CHANNEL:
/* configure the length of inserted channel group */
ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
break;
default:
break;
@@ -350,51 +335,50 @@ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, u
\param[out] none
\retval none
*/
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
{
uint32_t rsq,sampt;
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) {
uint32_t rsq, sampt;
/* ADC regular sequence config */
if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){
if (rank < ADC_REGULAR_CHANNEL_RANK_SIX) {
/* the regular group sequence rank is smaller than six */
rsq = ADC_RSQ2(adc_periph);
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)));
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank)));
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank));
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank));
ADC_RSQ2(adc_periph) = rsq;
}else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){
} else if (rank < ADC_REGULAR_CHANNEL_RANK_TWELVE) {
/* the regular group sequence rank is smaller than twelve */
rsq = ADC_RSQ1(adc_periph);
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))));
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX))));
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)));
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX)));
ADC_RSQ1(adc_periph) = rsq;
}else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){
} else if (rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN) {
/* the regular group sequence rank is smaller than sixteen */
rsq = ADC_RSQ0(adc_periph);
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))));
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE))));
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)));
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE)));
ADC_RSQ0(adc_periph) = rsq;
}else{
} else {
}
/* ADC sampling time config */
if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
if (adc_channel < ADC_CHANNEL_SAMPLE_TEN) {
/* the regular group sequence rank is smaller than ten */
sampt = ADC_SAMPT1(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)));
/* channel sample time set*/
sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel));
sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel));
ADC_SAMPT1(adc_periph) = sampt;
}else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
} else if (adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN) {
/* the regular group sequence rank is smaller than eighteen */
sampt = ADC_SAMPT0(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))));
/* channel sample time set*/
sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)));
ADC_SAMPT0(adc_periph) = sampt;
}else{
} else {
}
}
@@ -418,34 +402,33 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
\param[out] none
\retval none
*/
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
{
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) {
uint8_t inserted_length;
uint32_t isq,sampt;
uint32_t isq, sampt;
/* get inserted channel group length */
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U);
/* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */
isq = ADC_ISQ(adc_periph);
isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)));
isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH));
isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)));
isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH));
ADC_ISQ(adc_periph) = isq;
/* ADC sampling time config */
if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
if (adc_channel < ADC_CHANNEL_SAMPLE_TEN) {
/* the inserted group sequence rank is smaller than ten */
sampt = ADC_SAMPT1(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)));
/* channel sample time set*/
sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel);
sampt |= (uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel);
ADC_SAMPT1(adc_periph) = sampt;
}else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
} else if (adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN) {
/* the inserted group sequence rank is smaller than eighteen */
sampt = ADC_SAMPT0(adc_periph);
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))));
/* channel sample time set*/
sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)));
ADC_SAMPT0(adc_periph) = sampt;
}else{
} else {
}
}
@@ -462,15 +445,14 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_
\param[out] none
\retval none
*/
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
{
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) {
uint8_t inserted_length;
uint32_t num = 0U;
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U);
num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
if(num <= ADC_OFFSET_LENGTH){
if (num <= ADC_OFFSET_LENGTH) {
/* calculate the offset of the register */
num = num * ADC_OFFSET_SHIFT_LENGTH;
/* config the offset of the selected channels */
@@ -508,9 +490,8 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch
\param[out] none
\retval none
*/
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
{
switch(adc_channel_group){
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) {
switch (adc_channel_group) {
case ADC_REGULAR_CHANNEL:
/* configure ADC regular group external trigger source */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
@@ -537,23 +518,22 @@ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel
\param[out] none
\retval none
*/
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
{
if(newvalue){
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) {
if (newvalue) {
if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
/* enable ADC regular channel group external trigger */
ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
}
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
/* enable ADC inserted channel group external trigger */
ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
}
}else{
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
} else {
if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
/* disable ADC regular channel group external trigger */
ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
}
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
/* disable ADC regular channel group external trigger */
ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
}
@@ -570,13 +550,12 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group,
\param[out] none
\retval none
*/
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
{
if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) {
if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
/* enable ADC regular channel group software trigger */
ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
}
if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
/* enable ADC inserted channel group software trigger */
ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
}
@@ -589,10 +568,7 @@ void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
\param[out] none
\retval the conversion value
*/
uint16_t adc_regular_data_read(uint32_t adc_periph)
{
return (uint16_t)(ADC_RDATA(adc_periph));
}
uint16_t adc_regular_data_read(uint32_t adc_periph) { return (uint16_t)(ADC_RDATA(adc_periph)); }
/*!
\brief read ADC inserted group data register
@@ -606,11 +582,10 @@ uint16_t adc_regular_data_read(uint32_t adc_periph)
\param[out] none
\retval the conversion value
*/
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
{
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) {
uint32_t idata;
/* read the data of the selected channel */
switch(inserted_channel){
switch (inserted_channel) {
case ADC_INSERTED_CHANNEL_0:
/* read the data of channel 0 */
idata = ADC_IDATA0(adc_periph);
@@ -640,13 +615,11 @@ uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
\param[out] none
\retval the conversion value
*/
uint32_t adc_sync_mode_convert_value_read(void)
{
uint32_t adc_sync_mode_convert_value_read(void) {
/* return conversion value */
return ADC_RDATA(ADC0);
}
/*!
\brief configure ADC analog watchdog single channel
\param[in] adc_periph: ADCx, x=0,1
@@ -656,9 +629,8 @@ uint32_t adc_sync_mode_convert_value_read(void)
\param[out] none
\retval none
*/
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
{
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) {
ADC_CTL0(adc_periph) &= (uint32_t) ~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
/* analog watchdog channel select */
ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
@@ -675,18 +647,17 @@ void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel
\param[out] none
\retval none
*/
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
{
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) {
ADC_CTL0(adc_periph) &= (uint32_t) ~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
/* select the group */
switch(adc_channel_group){
switch (adc_channel_group) {
case ADC_REGULAR_CHANNEL:
/* regular channel analog watchdog enable */
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_RWDEN;
break;
case ADC_INSERTED_CHANNEL:
/* inserted channel analog watchdog enable */
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_IWDEN;
break;
case ADC_REGULAR_INSERTED_CHANNEL:
/* regular and inserted channel analog watchdog enable */
@@ -703,10 +674,7 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_
\param[out] none
\retval none
*/
void adc_watchdog_disable(uint32_t adc_periph)
{
ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
}
void adc_watchdog_disable(uint32_t adc_periph) { ADC_CTL0(adc_periph) &= (uint32_t) ~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); }
/*!
\brief configure ADC analog watchdog threshold
@@ -716,8 +684,7 @@ void adc_watchdog_disable(uint32_t adc_periph)
\param[out] none
\retval none
*/
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
{
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) {
ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
}
@@ -735,10 +702,9 @@ void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold,
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag)
{
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) {
FlagStatus reval = RESET;
if(ADC_STAT(adc_periph) & adc_flag){
if (ADC_STAT(adc_periph) & adc_flag) {
reval = SET;
}
return reval;
@@ -757,10 +723,7 @@ FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag)
\param[out] none
\retval none
*/
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag)
{
ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
}
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) { ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); }
/*!
\brief get the bit state of ADCx software start conversion
@@ -769,10 +732,9 @@ void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
{
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) {
FlagStatus reval = RESET;
if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){
if ((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)) {
reval = SET;
}
return reval;
@@ -785,10 +747,9 @@ FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
{
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) {
FlagStatus reval = RESET;
if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){
if ((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)) {
reval = SET;
}
return reval;
@@ -805,30 +766,29 @@ FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt)
{
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) {
FlagStatus interrupt_flag = RESET;
uint32_t state;
/* check the interrupt bits */
switch(adc_interrupt){
switch (adc_interrupt) {
case ADC_INT_FLAG_WDE:
/* get the ADC analog watchdog interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
if ((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state) {
interrupt_flag = SET;
}
break;
case ADC_INT_FLAG_EOC:
/* get the ADC end of group conversion interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
if ((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) {
interrupt_flag = SET;
}
break;
case ADC_INT_FLAG_EOIC:
/* get the ADC end of inserted group conversion interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
if ((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) {
interrupt_flag = SET;
}
break;
@@ -849,10 +809,7 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt)
\param[out] none
\retval none
*/
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt)
{
ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
}
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) { ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); }
/*!
\brief enable ADC interrupt
@@ -865,19 +822,18 @@ void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt)
\param[out] none
\retval none
*/
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt)
{
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) {
/* enable ADC analog watchdog interrupt */
if(0U != (adc_interrupt & ADC_INT_WDE)){
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
if (0U != (adc_interrupt & ADC_INT_WDE)) {
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_WDEIE;
}
/* enable ADC end of group conversion interrupt */
if(0U != (adc_interrupt & ADC_INT_EOC)){
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
if (0U != (adc_interrupt & ADC_INT_EOC)) {
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_EOCIE;
}
/* enable ADC end of inserted group conversion interrupt */
if(0U != (adc_interrupt & ADC_INT_EOIC)){
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
if (0U != (adc_interrupt & ADC_INT_EOIC)) {
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_EOICIE;
}
}
@@ -892,19 +848,18 @@ void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt)
\param[out] none
\retval none
*/
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
{
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) {
/* disable ADC analog watchdog interrupt */
if(0U != (adc_interrupt & ADC_INT_WDE)){
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
if (0U != (adc_interrupt & ADC_INT_WDE)) {
ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_WDEIE;
}
/* disable ADC end of group conversion interrupt */
if(0U != (adc_interrupt & ADC_INT_EOC)){
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
if (0U != (adc_interrupt & ADC_INT_EOC)) {
ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_EOCIE;
}
/* disable ADC end of inserted group conversion interrupt */
if(0U != (adc_interrupt & ADC_INT_EOIC)){
ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
if (0U != (adc_interrupt & ADC_INT_EOIC)) {
ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_EOICIE;
}
}
@@ -920,8 +875,7 @@ void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
\param[out] none
\retval none
*/
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
{
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) {
ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_DRES);
ADC_OVSCR(adc_periph) |= (uint32_t)resolution;
}
@@ -959,11 +913,10 @@ void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
\param[out] none
\retval none
*/
void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift,uint8_t ratio)
{
if(mode){
void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio) {
if (mode) {
ADC_OVSCR(adc_periph) |= (uint32_t)ADC_OVSCR_TOVS;
}else{
} else {
ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_TOVS);
}
/* config the shift and ratio */
@@ -977,10 +930,7 @@ void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shif
\param[out] none
\retval none
*/
void adc_oversample_mode_enable(uint32_t adc_periph)
{
ADC_OVSCR(adc_periph) |= ADC_OVSCR_OVSEN;
}
void adc_oversample_mode_enable(uint32_t adc_periph) { ADC_OVSCR(adc_periph) |= ADC_OVSCR_OVSEN; }
/*!
\brief disable ADC oversample mode
@@ -988,7 +938,4 @@ void adc_oversample_mode_enable(uint32_t adc_periph)
\param[out] none
\retval none
*/
void adc_oversample_mode_disable(uint32_t adc_periph)
{
ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_OVSEN);
}
void adc_oversample_mode_disable(uint32_t adc_periph) { ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_OVSEN); }

94
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_bkp.c vendored
View File

@@ -43,8 +43,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void bkp_deinit(void)
{
void bkp_deinit(void) {
/* reset BKP domain register*/
rcu_bkp_reset_enable();
rcu_bkp_reset_disable();
@@ -59,13 +58,12 @@ void bkp_deinit(void)
\param[out] none
\retval none
*/
void bkp_data_write(bkp_data_register_enum register_number, uint16_t data)
{
if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) {
if ((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) {
BKP_DATA10_41(register_number - 1U) = data;
}else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
} else if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) {
BKP_DATA0_9(register_number - 1U) = data;
}else{
} else {
/* illegal parameters */
}
}
@@ -78,16 +76,15 @@ void bkp_data_write(bkp_data_register_enum register_number, uint16_t data)
\param[out] none
\retval data of BKP data register
*/
uint16_t bkp_data_read(bkp_data_register_enum register_number)
{
uint16_t bkp_data_read(bkp_data_register_enum register_number) {
uint16_t data = 0U;
/* get the data from the BKP data register */
if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
if ((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) {
data = BKP_DATA10_41(register_number - 1U);
}else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
} else if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) {
data = BKP_DATA0_9(register_number - 1U);
}else{
} else {
/* illegal parameters */
}
return data;
@@ -99,10 +96,7 @@ uint16_t bkp_data_read(bkp_data_register_enum register_number)
\param[out] none
\retval none
*/
void bkp_rtc_calibration_output_enable(void)
{
BKP_OCTL |= (uint16_t)BKP_OCTL_COEN;
}
void bkp_rtc_calibration_output_enable(void) { BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; }
/*!
\brief disable RTC clock calibration output
@@ -110,10 +104,7 @@ void bkp_rtc_calibration_output_enable(void)
\param[out] none
\retval none
*/
void bkp_rtc_calibration_output_disable(void)
{
BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN;
}
void bkp_rtc_calibration_output_disable(void) { BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; }
/*!
\brief enable RTC alarm or second signal output
@@ -121,10 +112,7 @@ void bkp_rtc_calibration_output_disable(void)
\param[out] none
\retval none
*/
void bkp_rtc_signal_output_enable(void)
{
BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN;
}
void bkp_rtc_signal_output_enable(void) { BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; }
/*!
\brief disable RTC alarm or second signal output
@@ -132,10 +120,7 @@ void bkp_rtc_signal_output_enable(void)
\param[out] none
\retval none
*/
void bkp_rtc_signal_output_disable(void)
{
BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN;
}
void bkp_rtc_signal_output_disable(void) { BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; }
/*!
\brief select RTC output
@@ -146,8 +131,7 @@ void bkp_rtc_signal_output_disable(void)
\param[out] none
\retval none
*/
void bkp_rtc_output_select(uint16_t outputsel)
{
void bkp_rtc_output_select(uint16_t outputsel) {
uint16_t ctl = 0U;
/* configure BKP_OCTL_ROSEL with outputsel */
@@ -164,8 +148,7 @@ void bkp_rtc_output_select(uint16_t outputsel)
\param[out] none
\retval none
*/
void bkp_rtc_calibration_value_set(uint8_t value)
{
void bkp_rtc_calibration_value_set(uint8_t value) {
uint16_t ctl;
/* configure BKP_OCTL_RCCV with value */
@@ -181,10 +164,7 @@ void bkp_rtc_calibration_value_set(uint8_t value)
\param[out] none
\retval none
*/
void bkp_tamper_detection_enable(void)
{
BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN;
}
void bkp_tamper_detection_enable(void) { BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; }
/*!
\brief disable tamper detection
@@ -192,10 +172,7 @@ void bkp_tamper_detection_enable(void)
\param[out] none
\retval none
*/
void bkp_tamper_detection_disable(void)
{
BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN;
}
void bkp_tamper_detection_disable(void) { BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; }
/*!
\brief set tamper pin active level
@@ -206,8 +183,7 @@ void bkp_tamper_detection_disable(void)
\param[out] none
\retval none
*/
void bkp_tamper_active_level_set(uint16_t level)
{
void bkp_tamper_active_level_set(uint16_t level) {
uint16_t ctl = 0U;
/* configure BKP_TPCTL_TPAL with level */
@@ -223,10 +199,7 @@ void bkp_tamper_active_level_set(uint16_t level)
\param[out] none
\retval none
*/
void bkp_interrupt_enable(void)
{
BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE;
}
void bkp_interrupt_enable(void) { BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; }
/*!
\brief disable tamper interrupt
@@ -234,10 +207,7 @@ void bkp_interrupt_enable(void)
\param[out] none
\retval none
*/
void bkp_interrupt_disable(void)
{
BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE;
}
void bkp_interrupt_disable(void) { BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; }
/*!
\brief get tamper flag state
@@ -245,11 +215,10 @@ void bkp_interrupt_disable(void)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus bkp_flag_get(void)
{
if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){
FlagStatus bkp_flag_get(void) {
if (RESET != (BKP_TPCS & BKP_FLAG_TAMPER)) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -260,10 +229,7 @@ FlagStatus bkp_flag_get(void)
\param[out] none
\retval none
*/
void bkp_flag_clear(void)
{
BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET);
}
void bkp_flag_clear(void) { BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); }
/*!
\brief get tamper interrupt flag state
@@ -271,11 +237,10 @@ void bkp_flag_clear(void)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus bkp_interrupt_flag_get(void)
{
if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){
FlagStatus bkp_interrupt_flag_get(void) {
if (RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -286,7 +251,4 @@ FlagStatus bkp_interrupt_flag_get(void)
\param[out] none
\retval none
*/
void bkp_interrupt_flag_clear(void)
{
BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET);
}
void bkp_interrupt_flag_clear(void) { BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); }

383
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_can.c vendored
View File

@@ -34,7 +34,9 @@ OF SUCH DAMAGE.
#include "gd32vf103_can.h"
#define CAN_ERROR_HANDLE(s) do{}while(1)
#define CAN_ERROR_HANDLE(s) \
do { \
} while (1)
/*!
\brief deinitialize CAN
@@ -43,12 +45,11 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void can_deinit(uint32_t can_periph)
{
if(CAN0 == can_periph){
void can_deinit(uint32_t can_periph) {
if (CAN0 == can_periph) {
rcu_periph_reset_enable(RCU_CAN0RST);
rcu_periph_reset_disable(RCU_CAN0RST);
}else{
} else {
rcu_periph_reset_enable(RCU_CAN1RST);
rcu_periph_reset_disable(RCU_CAN1RST);
}
@@ -66,65 +67,64 @@ void can_deinit(uint32_t can_periph)
\param[out] none
\retval none
*/
void can_struct_para_init(can_struct_type_enum type, void* p_struct)
{
void can_struct_para_init(can_struct_type_enum type, void *p_struct) {
uint8_t i;
/* get type of the struct */
switch(type){
switch (type) {
/* used for can_init() */
case CAN_INIT_STRUCT:
((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE;
((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE;
((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE;
((can_parameter_struct*)p_struct)->prescaler = 0x03FFU;
((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE;
((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ;
((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ;
((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ;
((can_parameter_struct*)p_struct)->time_triggered = DISABLE;
((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE;
((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE;
((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE;
((can_parameter_struct *)p_struct)->no_auto_retrans = DISABLE;
((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE;
((can_parameter_struct *)p_struct)->prescaler = 0x03FFU;
((can_parameter_struct *)p_struct)->rec_fifo_overwrite = DISABLE;
((can_parameter_struct *)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ;
((can_parameter_struct *)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ;
((can_parameter_struct *)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ;
((can_parameter_struct *)p_struct)->time_triggered = DISABLE;
((can_parameter_struct *)p_struct)->trans_fifo_order = DISABLE;
((can_parameter_struct *)p_struct)->working_mode = CAN_NORMAL_MODE;
break;
/* used for can_filter_init() */
case CAN_FILTER_STRUCT:
((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT;
((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE;
((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0;
((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U;
((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U;
((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U;
((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U;
((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK;
((can_filter_parameter_struct*)p_struct)->filter_number = 0U;
((can_filter_parameter_struct *)p_struct)->filter_bits = CAN_FILTERBITS_32BIT;
((can_filter_parameter_struct *)p_struct)->filter_enable = DISABLE;
((can_filter_parameter_struct *)p_struct)->filter_fifo_number = CAN_FIFO0;
((can_filter_parameter_struct *)p_struct)->filter_list_high = 0x0000U;
((can_filter_parameter_struct *)p_struct)->filter_list_low = 0x0000U;
((can_filter_parameter_struct *)p_struct)->filter_mask_high = 0x0000U;
((can_filter_parameter_struct *)p_struct)->filter_mask_low = 0x0000U;
((can_filter_parameter_struct *)p_struct)->filter_mode = CAN_FILTERMODE_MASK;
((can_filter_parameter_struct *)p_struct)->filter_number = 0U;
break;
/* used for can_message_transmit() */
case CAN_TX_MESSAGE_STRUCT:
for(i = 0U; i < 8U; i++){
((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U;
for (i = 0U; i < 8U; i++) {
((can_trasnmit_message_struct *)p_struct)->tx_data[i] = 0U;
}
((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u;
((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U;
((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD;
((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA;
((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U;
((can_trasnmit_message_struct *)p_struct)->tx_dlen = 0u;
((can_trasnmit_message_struct *)p_struct)->tx_efid = 0U;
((can_trasnmit_message_struct *)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD;
((can_trasnmit_message_struct *)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA;
((can_trasnmit_message_struct *)p_struct)->tx_sfid = 0U;
break;
/* used for can_message_receive() */
case CAN_RX_MESSAGE_STRUCT:
for(i = 0U; i < 8U; i++){
((can_receive_message_struct*)p_struct)->rx_data[i] = 0U;
for (i = 0U; i < 8U; i++) {
((can_receive_message_struct *)p_struct)->rx_data[i] = 0U;
}
((can_receive_message_struct*)p_struct)->rx_dlen = 0U;
((can_receive_message_struct*)p_struct)->rx_efid = 0U;
((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD;
((can_receive_message_struct*)p_struct)->rx_fi = 0U;
((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA;
((can_receive_message_struct*)p_struct)->rx_sfid = 0U;
((can_receive_message_struct *)p_struct)->rx_dlen = 0U;
((can_receive_message_struct *)p_struct)->rx_efid = 0U;
((can_receive_message_struct *)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD;
((can_receive_message_struct *)p_struct)->rx_fi = 0U;
((can_receive_message_struct *)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA;
((can_receive_message_struct *)p_struct)->rx_sfid = 0U;
break;
@@ -152,8 +152,7 @@ void can_struct_para_init(can_struct_type_enum type, void* p_struct)
\param[out] none
\retval ErrStatus: SUCCESS or ERROR
*/
ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init)
{
ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init) {
uint32_t timeout = CAN_TIMEOUT;
ErrStatus flag = ERROR;
@@ -162,65 +161,62 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init
/* enable initialize mode */
CAN_CTL(can_periph) |= CAN_CTL_IWMOD;
/* wait ACK */
while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
while ((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) {
timeout--;
}
/* check initialize working success */
if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
if (CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) {
flag = ERROR;
}else{
} else {
/* set the bit timing register */
CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \
BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \
BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \
BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | BT_BS1((uint32_t)can_parameter_init->time_segment_1)
| BT_BS2((uint32_t)can_parameter_init->time_segment_2) | BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
/* time trigger communication mode */
if(ENABLE == can_parameter_init->time_triggered){
if (ENABLE == can_parameter_init->time_triggered) {
CAN_CTL(can_periph) |= CAN_CTL_TTC;
}else{
} else {
CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
}
/* automatic bus-off managment */
if(ENABLE == can_parameter_init->auto_bus_off_recovery){
if (ENABLE == can_parameter_init->auto_bus_off_recovery) {
CAN_CTL(can_periph) |= CAN_CTL_ABOR;
}else{
} else {
CAN_CTL(can_periph) &= ~CAN_CTL_ABOR;
}
/* automatic wakeup mode */
if(ENABLE == can_parameter_init->auto_wake_up){
if (ENABLE == can_parameter_init->auto_wake_up) {
CAN_CTL(can_periph) |= CAN_CTL_AWU;
}else{
} else {
CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
}
/* automatic retransmission mode disable*/
if(ENABLE == can_parameter_init->no_auto_retrans){
if (ENABLE == can_parameter_init->no_auto_retrans) {
CAN_CTL(can_periph) |= CAN_CTL_ARD;
}else{
} else {
CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
}
/* receive fifo overwrite mode */
if(ENABLE == can_parameter_init->rec_fifo_overwrite){
if (ENABLE == can_parameter_init->rec_fifo_overwrite) {
CAN_CTL(can_periph) |= CAN_CTL_RFOD;
}else{
} else {
CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
}
/* transmit fifo order */
if(ENABLE == can_parameter_init->trans_fifo_order){
if (ENABLE == can_parameter_init->trans_fifo_order) {
CAN_CTL(can_periph) |= CAN_CTL_TFO;
}else{
} else {
CAN_CTL(can_periph) &= ~CAN_CTL_TFO;
}
/* disable initialize mode */
CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD;
timeout = CAN_TIMEOUT;
/* wait the ACK */
while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
while ((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) {
timeout--;
}
/* check exit initialize mode */
if(0U != timeout){
if (0U != timeout) {
flag = SUCCESS;
}
}
@@ -255,8 +251,7 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init
\param[out] none
\retval none
*/
void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init)
{
void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init) {
uint32_t val = 0U;
val = ((uint32_t)1) << (can_filter_parameter_init->filter_number);
@@ -266,52 +261,48 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init)
CAN_FW(CAN0) &= ~(uint32_t)val;
/* filter 16 bits */
if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){
if (CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits) {
/* set filter 16 bits */
CAN_FSCFG(CAN0) &= ~(uint32_t)val;
/* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */
CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \
FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number)
= FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
/* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */
CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \
FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS);
CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number)
= FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS);
}
/* filter 32 bits */
if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){
if (CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits) {
/* set filter 32 bits */
CAN_FSCFG(CAN0) |= (uint32_t)val;
/* 32 bits list or first 32 bits list */
CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \
FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) |
FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number)
= FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS);
/* 32 bits mask or second 32 bits list */
CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \
FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) |
FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS);
CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number)
= FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS);
}
/* filter mode */
if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){
if (CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode) {
/* mask mode */
CAN_FMCFG(CAN0) &= ~(uint32_t)val;
}else{
} else {
/* list mode */
CAN_FMCFG(CAN0) |= (uint32_t)val;
}
/* filter FIFO */
if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){
if (CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) {
/* FIFO0 */
CAN_FAFIFO(CAN0) &= ~(uint32_t)val;
}else{
} else {
/* FIFO1 */
CAN_FAFIFO(CAN0) |= (uint32_t)val;
}
/* filter working */
if(ENABLE == can_filter_parameter_init->filter_enable){
if (ENABLE == can_filter_parameter_init->filter_enable) {
CAN_FW(CAN0) |= (uint32_t)val;
}
@@ -328,8 +319,7 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init)
\param[out] none
\retval none
*/
void can1_filter_start_bank(uint8_t start_bank)
{
void can1_filter_start_bank(uint8_t start_bank) {
/* filter lock disable */
CAN_FCTL(CAN0) |= CAN_FCTL_FLD;
/* set CAN1 filter start number */
@@ -346,13 +336,12 @@ void can1_filter_start_bank(uint8_t start_bank)
\param[out] none
\retval none
*/
void can_debug_freeze_enable(uint32_t can_periph)
{
void can_debug_freeze_enable(uint32_t can_periph) {
/* set DFZ bit */
CAN_CTL(can_periph) |= CAN_CTL_DFZ;
if(CAN0 == can_periph){
if (CAN0 == can_periph) {
dbg_periph_enable(DBG_CAN0_HOLD);
}else{
} else {
dbg_periph_enable(DBG_CAN1_HOLD);
}
}
@@ -364,13 +353,12 @@ void can_debug_freeze_enable(uint32_t can_periph)
\param[out] none
\retval none
*/
void can_debug_freeze_disable(uint32_t can_periph)
{
void can_debug_freeze_disable(uint32_t can_periph) {
/* set DFZ bit */
CAN_CTL(can_periph) &= ~CAN_CTL_DFZ;
if(CAN0 == can_periph){
if (CAN0 == can_periph) {
dbg_periph_disable(DBG_CAN0_HOLD);
}else{
} else {
dbg_periph_disable(DBG_CAN1_HOLD);
}
}
@@ -382,14 +370,13 @@ void can_debug_freeze_disable(uint32_t can_periph)
\param[out] none
\retval none
*/
void can_time_trigger_mode_enable(uint32_t can_periph)
{
void can_time_trigger_mode_enable(uint32_t can_periph) {
uint8_t mailbox_number;
/* enable the tcc mode */
CAN_CTL(can_periph) |= CAN_CTL_TTC;
/* enable time stamp */
for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){
for (mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) {
CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN;
}
}
@@ -401,14 +388,13 @@ void can_time_trigger_mode_enable(uint32_t can_periph)
\param[out] none
\retval none
*/
void can_time_trigger_mode_disable(uint32_t can_periph)
{
void can_time_trigger_mode_disable(uint32_t can_periph) {
uint8_t mailbox_number;
/* disable the TCC mode */
CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
/* reset TSEN bits */
for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){
for (mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) {
CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN;
}
}
@@ -427,48 +413,40 @@ void can_time_trigger_mode_disable(uint32_t can_periph)
\param[out] none
\retval mailbox_number
*/
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message)
{
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message) {
uint8_t mailbox_number = CAN_MAILBOX0;
/* select one empty mailbox */
if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){
if (CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_TME0)) {
mailbox_number = CAN_MAILBOX0;
}else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){
} else if (CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_TME1)) {
mailbox_number = CAN_MAILBOX1;
}else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){
} else if (CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_TME2)) {
mailbox_number = CAN_MAILBOX2;
}else{
} else {
mailbox_number = CAN_NOMAILBOX;
}
/* return no mailbox empty */
if(CAN_NOMAILBOX == mailbox_number){
if (CAN_NOMAILBOX == mailbox_number) {
return CAN_NOMAILBOX;
}
CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN;
if(CAN_FF_STANDARD == transmit_message->tx_ff){
if (CAN_FF_STANDARD == transmit_message->tx_ff) {
/* set transmit mailbox standard identifier */
CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \
transmit_message->tx_ft);
}else{
CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | transmit_message->tx_ft);
} else {
/* set transmit mailbox extended identifier */
CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \
transmit_message->tx_ff | \
transmit_message->tx_ft);
CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | transmit_message->tx_ff | transmit_message->tx_ft);
}
/* set the data length */
CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC;
CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen;
/* set the data */
CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \
TMDATA0_DB2(transmit_message->tx_data[2]) | \
TMDATA0_DB1(transmit_message->tx_data[1]) | \
TMDATA0_DB0(transmit_message->tx_data[0]);
CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \
TMDATA1_DB6(transmit_message->tx_data[6]) | \
TMDATA1_DB5(transmit_message->tx_data[5]) | \
TMDATA1_DB4(transmit_message->tx_data[4]);
CAN_TMDATA0(can_periph, mailbox_number)
= TMDATA0_DB3(transmit_message->tx_data[3]) | TMDATA0_DB2(transmit_message->tx_data[2]) | TMDATA0_DB1(transmit_message->tx_data[1]) | TMDATA0_DB0(transmit_message->tx_data[0]);
CAN_TMDATA1(can_periph, mailbox_number)
= TMDATA1_DB7(transmit_message->tx_data[7]) | TMDATA1_DB6(transmit_message->tx_data[6]) | TMDATA1_DB5(transmit_message->tx_data[5]) | TMDATA1_DB4(transmit_message->tx_data[4]);
/* enable transmission */
CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN;
@@ -485,13 +463,12 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* t
\param[out] none
\retval can_transmit_state_enum
*/
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number)
{
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) {
can_transmit_state_enum state = CAN_TRANSMIT_FAILED;
uint32_t val = 0U;
/* check selected mailbox state */
switch(mailbox_number){
switch (mailbox_number) {
/* mailbox0 */
case CAN_MAILBOX0:
val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0);
@@ -509,7 +486,7 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox
break;
}
switch(val){
switch (val) {
/* transmit pending */
case (CAN_STATE_PENDING):
state = CAN_TRANSMIT_PENDING;
@@ -544,21 +521,17 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox
\param[out] none
\retval none
*/
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
{
if(CAN_MAILBOX0 == mailbox_number){
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) {
if (CAN_MAILBOX0 == mailbox_number) {
CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0;
while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){
}
}else if(CAN_MAILBOX1 == mailbox_number){
while (CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) {}
} else if (CAN_MAILBOX1 == mailbox_number) {
CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1;
while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){
}
}else if(CAN_MAILBOX2 == mailbox_number){
while (CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) {}
} else if (CAN_MAILBOX2 == mailbox_number) {
CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2;
while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){
}
}else{
while (CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) {}
} else {
/* illegal parameters */
}
}
@@ -579,14 +552,13 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number)
\arg rx_fi: 0 - 27
\retval none
*/
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message)
{
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message) {
/* get the frame format */
receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number));
if(CAN_FF_STANDARD == receive_message->rx_ff){
if (CAN_FF_STANDARD == receive_message->rx_ff) {
/* get standard identifier */
receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number)));
}else{
} else {
/* get extended identifier */
receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number)));
}
@@ -599,19 +571,19 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m
receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number)));
/* receive data */
receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number)));
receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number)));
receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number)));
receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number)));
receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number)));
receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number)));
receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number)));
receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number)));
receive_message->rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number)));
receive_message->rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number)));
receive_message->rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number)));
receive_message->rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number)));
receive_message->rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number)));
receive_message->rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number)));
receive_message->rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number)));
receive_message->rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number)));
/* release FIFO */
if(CAN_FIFO0 == fifo_number){
if (CAN_FIFO0 == fifo_number) {
CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
}else{
} else {
CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
}
}
@@ -626,13 +598,12 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m
\param[out] none
\retval none
*/
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number)
{
if(CAN_FIFO0 == fifo_number){
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) {
if (CAN_FIFO0 == fifo_number) {
CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0;
}else if(CAN_FIFO1 == fifo_number){
} else if (CAN_FIFO1 == fifo_number) {
CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1;
}else{
} else {
/* illegal parameters */
CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n");
}
@@ -648,17 +619,16 @@ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number)
\param[out] none
\retval message length
*/
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number)
{
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) {
uint8_t val = 0U;
if(CAN_FIFO0 == fifo_number){
if (CAN_FIFO0 == fifo_number) {
/* FIFO0 */
val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK);
}else if(CAN_FIFO1 == fifo_number){
} else if (CAN_FIFO1 == fifo_number) {
/* FIFO1 */
val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK);
}else{
} else {
/* illegal parameters */
}
return val;
@@ -676,53 +646,52 @@ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number)
\param[out] none
\retval ErrStatus: SUCCESS or ERROR
*/
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
{
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) {
ErrStatus flag = ERROR;
/* timeout for IWS or also for SLPWS bits */
uint32_t timeout = CAN_TIMEOUT;
if(CAN_MODE_INITIALIZE == working_mode){
if (CAN_MODE_INITIALIZE == working_mode) {
/* disable sleep mode */
CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD);
/* set initialize mode */
CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD;
/* wait the acknowledge */
while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){
while ((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) {
timeout--;
}
if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){
if (CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) {
flag = ERROR;
}else{
} else {
flag = SUCCESS;
}
}else if(CAN_MODE_NORMAL == working_mode){
} else if (CAN_MODE_NORMAL == working_mode) {
/* enter normal mode */
CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD);
/* wait the acknowledge */
while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){
while ((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) {
timeout--;
}
if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){
if (0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) {
flag = ERROR;
}else{
} else {
flag = SUCCESS;
}
}else if(CAN_MODE_SLEEP == working_mode){
} else if (CAN_MODE_SLEEP == working_mode) {
/* disable initialize mode */
CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD);
/* set sleep mode */
CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD;
/* wait the acknowledge */
while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){
while ((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)) {
timeout--;
}
if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
if (CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) {
flag = ERROR;
}else{
} else {
flag = SUCCESS;
}
}else{
} else {
flag = ERROR;
}
return flag;
@@ -735,21 +704,20 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode)
\param[out] none
\retval ErrStatus: SUCCESS or ERROR
*/
ErrStatus can_wakeup(uint32_t can_periph)
{
ErrStatus can_wakeup(uint32_t can_periph) {
ErrStatus flag = ERROR;
uint32_t timeout = CAN_TIMEOUT;
/* wakeup */
CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD;
while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){
while ((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)) {
timeout--;
}
/* check state */
if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){
if (0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) {
flag = ERROR;
}else{
} else {
flag = SUCCESS;
}
return flag;
@@ -770,8 +738,7 @@ ErrStatus can_wakeup(uint32_t can_periph)
\arg CAN_ERROR_CRC: CRC error
\arg CAN_ERROR_SOFTWARECFG: software configure
*/
can_error_enum can_error_get(uint32_t can_periph)
{
can_error_enum can_error_get(uint32_t can_periph) {
can_error_enum error;
error = CAN_ERROR_NONE;
@@ -787,8 +754,7 @@ can_error_enum can_error_get(uint32_t can_periph)
\param[out] none
\retval error number
*/
uint8_t can_receive_error_number_get(uint32_t can_periph)
{
uint8_t can_receive_error_number_get(uint32_t can_periph) {
uint8_t val;
/* get error count */
@@ -803,8 +769,7 @@ uint8_t can_receive_error_number_get(uint32_t can_periph)
\param[out] none
\retval error number
*/
uint8_t can_transmit_error_number_get(uint32_t can_periph)
{
uint8_t can_transmit_error_number_get(uint32_t can_periph) {
uint8_t val;
val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph)));
@@ -834,10 +799,7 @@ uint8_t can_transmit_error_number_get(uint32_t can_periph)
\param[out] none
\retval none
*/
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt)
{
CAN_INTEN(can_periph) |= interrupt;
}
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) { CAN_INTEN(can_periph) |= interrupt; }
/*!
\brief disable CAN interrupt
@@ -862,10 +824,7 @@ void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt)
\param[out] none
\retval none
*/
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
{
CAN_INTEN(can_periph) &= ~interrupt;
}
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) { CAN_INTEN(can_periph) &= ~interrupt; }
/*!
\brief get CAN flag state
@@ -889,12 +848,11 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
{
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) {
/* get flag and interrupt enable state */
if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){
if (RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -921,10 +879,7 @@ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag)
\param[out] none
\retval none
*/
void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
{
CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag));
}
void can_flag_clear(uint32_t can_periph, can_flag_enum flag) { CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); }
/*!
\brief get CAN interrupt flag state
@@ -945,8 +900,7 @@ void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag)
{
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) {
uint32_t ret1 = RESET;
uint32_t ret2 = RESET;
@@ -954,9 +908,9 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f
ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag));
/* get the staus of interrupt enale bit */
ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag));
if(ret1 && ret2){
if (ret1 && ret2) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -983,7 +937,4 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f
\param[out] none
\retval none
*/
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag)
{
CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag));
}
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) { CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag)); }

27
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_crc.c vendored
View File

@@ -43,8 +43,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void crc_deinit(void)
{
void crc_deinit(void) {
CRC_DATA = CRC_DATA_RESET_VALUE;
CRC_FDATA = CRC_FDATA_RESET_VALUE;
CRC_CTL = (uint32_t)CRC_CTL_RST;
@@ -56,10 +55,7 @@ void crc_deinit(void)
\param[out] none
\retval none
*/
void crc_data_register_reset(void)
{
CRC_CTL |= (uint32_t)CRC_CTL_RST;
}
void crc_data_register_reset(void) { CRC_CTL |= (uint32_t)CRC_CTL_RST; }
/*!
\brief read the value of the data register
@@ -67,8 +63,7 @@ void crc_data_register_reset(void)
\param[out] none
\retval 32-bit value of the data register
*/
uint32_t crc_data_register_read(void)
{
uint32_t crc_data_register_read(void) {
uint32_t data;
data = CRC_DATA;
return (data);
@@ -80,8 +75,7 @@ uint32_t crc_data_register_read(void)
\param[out] none
\retval 8-bit value of the free data register
*/
uint8_t crc_free_data_register_read(void)
{
uint8_t crc_free_data_register_read(void) {
uint8_t fdata;
fdata = (uint8_t)CRC_FDATA;
return (fdata);
@@ -93,10 +87,7 @@ uint8_t crc_free_data_register_read(void)
\param[out] none
\retval none
*/
void crc_free_data_register_write(uint8_t free_data)
{
CRC_FDATA = (uint32_t)free_data;
}
void crc_free_data_register_write(uint8_t free_data) { CRC_FDATA = (uint32_t)free_data; }
/*!
\brief calculate the CRC value of a 32-bit data
@@ -104,8 +95,7 @@ void crc_free_data_register_write(uint8_t free_data)
\param[out] none
\retval 32-bit value calculated by CRC
*/
uint32_t crc_single_data_calculate(uint32_t sdata)
{
uint32_t crc_single_data_calculate(uint32_t sdata) {
CRC_DATA = sdata;
return (CRC_DATA);
}
@@ -117,10 +107,9 @@ uint32_t crc_single_data_calculate(uint32_t sdata)
\param[out] none
\retval 32-bit value calculated by CRC
*/
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
{
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) {
uint32_t index;
for(index = 0U; index < size; index++){
for (index = 0U; index < size; index++) {
CRC_DATA = array[index];
}
return (CRC_DATA);

149
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dac.c vendored
View File

@@ -45,8 +45,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void dac_deinit(void)
{
void dac_deinit(void) {
rcu_periph_reset_enable(RCU_DACRST);
rcu_periph_reset_disable(RCU_DACRST);
}
@@ -57,11 +56,10 @@ void dac_deinit(void)
\param[out] none
\retval none
*/
void dac_enable(uint32_t dac_periph)
{
if(DAC0 == dac_periph){
void dac_enable(uint32_t dac_periph) {
if (DAC0 == dac_periph) {
DAC_CTL |= DAC_CTL_DEN0;
}else{
} else {
DAC_CTL |= DAC_CTL_DEN1;
}
}
@@ -72,11 +70,10 @@ void dac_enable(uint32_t dac_periph)
\param[out] none
\retval none
*/
void dac_disable(uint32_t dac_periph)
{
if(DAC0 == dac_periph){
void dac_disable(uint32_t dac_periph) {
if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DEN0;
}else{
} else {
DAC_CTL &= ~DAC_CTL_DEN1;
}
}
@@ -87,11 +84,10 @@ void dac_disable(uint32_t dac_periph)
\param[out] none
\retval none
*/
void dac_dma_enable(uint32_t dac_periph)
{
if(DAC0 == dac_periph){
void dac_dma_enable(uint32_t dac_periph) {
if (DAC0 == dac_periph) {
DAC_CTL |= DAC_CTL_DDMAEN0;
}else{
} else {
DAC_CTL |= DAC_CTL_DDMAEN1;
}
}
@@ -102,11 +98,10 @@ void dac_dma_enable(uint32_t dac_periph)
\param[out] none
\retval none
*/
void dac_dma_disable(uint32_t dac_periph)
{
if(DAC0 == dac_periph){
void dac_dma_disable(uint32_t dac_periph) {
if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DDMAEN0;
}else{
} else {
DAC_CTL &= ~DAC_CTL_DDMAEN1;
}
}
@@ -117,11 +112,10 @@ void dac_dma_disable(uint32_t dac_periph)
\param[out] none
\retval none
*/
void dac_output_buffer_enable(uint32_t dac_periph)
{
if(DAC0 == dac_periph){
void dac_output_buffer_enable(uint32_t dac_periph) {
if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DBOFF0;
}else{
} else {
DAC_CTL &= ~DAC_CTL_DBOFF1;
}
}
@@ -132,11 +126,10 @@ void dac_output_buffer_enable(uint32_t dac_periph)
\param[out] none
\retval none
*/
void dac_output_buffer_disable(uint32_t dac_periph)
{
if(DAC0 == dac_periph){
void dac_output_buffer_disable(uint32_t dac_periph) {
if (DAC0 == dac_periph) {
DAC_CTL |= DAC_CTL_DBOFF0;
}else{
} else {
DAC_CTL |= DAC_CTL_DBOFF1;
}
}
@@ -147,13 +140,12 @@ void dac_output_buffer_disable(uint32_t dac_periph)
\param[out] none
\retval DAC output data
*/
uint16_t dac_output_value_get(uint32_t dac_periph)
{
uint16_t dac_output_value_get(uint32_t dac_periph) {
uint16_t data = 0U;
if(DAC0 == dac_periph){
if (DAC0 == dac_periph) {
/* store the DAC0 output value */
data = (uint16_t)DAC0_DO;
}else{
} else {
/* store the DAC1 output value */
data = (uint16_t)DAC1_DO;
}
@@ -172,10 +164,9 @@ uint16_t dac_output_value_get(uint32_t dac_periph)
\param[out] none
\retval none
*/
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
{
if(DAC0 == dac_periph){
switch(dac_align){
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) {
if (DAC0 == dac_periph) {
switch (dac_align) {
/* data right 12 bit alignment */
case DAC_ALIGN_12B_R:
DAC0_R12DH = data;
@@ -191,8 +182,8 @@ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
default:
break;
}
}else{
switch(dac_align){
} else {
switch (dac_align) {
/* data right 12 bit alignment */
case DAC_ALIGN_12B_R:
DAC1_R12DH = data;
@@ -217,11 +208,10 @@ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
\param[out] none
\retval none
*/
void dac_trigger_enable(uint32_t dac_periph)
{
if(DAC0 == dac_periph){
void dac_trigger_enable(uint32_t dac_periph) {
if (DAC0 == dac_periph) {
DAC_CTL |= DAC_CTL_DTEN0;
}else{
} else {
DAC_CTL |= DAC_CTL_DTEN1;
}
}
@@ -232,11 +222,10 @@ void dac_trigger_enable(uint32_t dac_periph)
\param[out] none
\retval none
*/
void dac_trigger_disable(uint32_t dac_periph)
{
if(DAC0 == dac_periph){
void dac_trigger_disable(uint32_t dac_periph) {
if (DAC0 == dac_periph) {
DAC_CTL &= ~DAC_CTL_DTEN0;
}else{
} else {
DAC_CTL &= ~DAC_CTL_DTEN1;
}
}
@@ -257,13 +246,12 @@ void dac_trigger_disable(uint32_t dac_periph)
\param[out] none
\retval none
*/
void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource)
{
if(DAC0 == dac_periph){
void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource) {
if (DAC0 == dac_periph) {
/* configure DAC0 trigger source */
DAC_CTL &= ~DAC_CTL_DTSEL0;
DAC_CTL |= triggersource;
}else{
} else {
/* configure DAC1 trigger source */
DAC_CTL &= ~DAC_CTL_DTSEL1;
DAC_CTL |= (triggersource << DAC1_REG_OFFSET);
@@ -275,11 +263,10 @@ void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource)
\param[in] dac_periph: DACx(x = 0,1)
\retval none
*/
void dac_software_trigger_enable(uint32_t dac_periph)
{
if(DAC0 == dac_periph){
void dac_software_trigger_enable(uint32_t dac_periph) {
if (DAC0 == dac_periph) {
DAC_SWT |= DAC_SWT_SWTR0;
}else{
} else {
DAC_SWT |= DAC_SWT_SWTR1;
}
}
@@ -290,11 +277,10 @@ void dac_software_trigger_enable(uint32_t dac_periph)
\param[out] none
\retval none
*/
void dac_software_trigger_disable(uint32_t dac_periph)
{
if(DAC0 == dac_periph){
void dac_software_trigger_disable(uint32_t dac_periph) {
if (DAC0 == dac_periph) {
DAC_SWT &= ~DAC_SWT_SWTR0;
}else{
} else {
DAC_SWT &= ~DAC_SWT_SWTR1;
}
}
@@ -310,13 +296,12 @@ void dac_software_trigger_disable(uint32_t dac_periph)
\param[out] none
\retval none
*/
void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode)
{
if(DAC0 == dac_periph){
void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) {
if (DAC0 == dac_periph) {
/* configure DAC0 wave mode */
DAC_CTL &= ~DAC_CTL_DWM0;
DAC_CTL |= wave_mode;
}else{
} else {
/* configure DAC1 wave mode */
DAC_CTL &= ~DAC_CTL_DWM1;
DAC_CTL |= (wave_mode << DAC1_REG_OFFSET);
@@ -343,13 +328,12 @@ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode)
\param[out] none
\retval none
*/
void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width)
{
if(DAC0 == dac_periph){
void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) {
if (DAC0 == dac_periph) {
/* configure DAC0 wave bit width */
DAC_CTL &= ~DAC_CTL_DWBW0;
DAC_CTL |= bit_width;
}else{
} else {
/* configure DAC1 wave bit width */
DAC_CTL &= ~DAC_CTL_DWBW1;
DAC_CTL |= (bit_width << DAC1_REG_OFFSET);
@@ -376,13 +360,12 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width)
\param[out] none
\retval none
*/
void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits)
{
if(DAC0 == dac_periph){
void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) {
if (DAC0 == dac_periph) {
/* configure DAC0 LFSR noise mode */
DAC_CTL &= ~DAC_CTL_DWBW0;
DAC_CTL |= unmask_bits;
}else{
} else {
/* configure DAC1 LFSR noise mode */
DAC_CTL &= ~DAC_CTL_DWBW1;
DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET);
@@ -409,13 +392,12 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits)
\param[out] none
\retval none
*/
void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude)
{
if(DAC0 == dac_periph){
void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) {
if (DAC0 == dac_periph) {
/* configure DAC0 triangle noise mode */
DAC_CTL &= ~DAC_CTL_DWBW0;
DAC_CTL |= amplitude;
}else{
} else {
/* configure DAC1 triangle noise mode */
DAC_CTL &= ~DAC_CTL_DWBW1;
DAC_CTL |= (amplitude << DAC1_REG_OFFSET);
@@ -428,8 +410,7 @@ void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude)
\param[out] none
\retval none
*/
void dac_concurrent_enable(void)
{
void dac_concurrent_enable(void) {
uint32_t ctl = 0U;
ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
DAC_CTL |= (ctl);
@@ -441,8 +422,7 @@ void dac_concurrent_enable(void)
\param[out] none
\retval none
*/
void dac_concurrent_disable(void)
{
void dac_concurrent_disable(void) {
uint32_t ctl = 0U;
ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
DAC_CTL &= (~ctl);
@@ -454,8 +434,7 @@ void dac_concurrent_disable(void)
\param[out] none
\retval none
*/
void dac_concurrent_software_trigger_enable(void)
{
void dac_concurrent_software_trigger_enable(void) {
uint32_t swt = 0U;
swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
DAC_SWT |= (swt);
@@ -467,8 +446,7 @@ void dac_concurrent_software_trigger_enable(void)
\param[out] none
\retval none
*/
void dac_concurrent_software_trigger_disable(void)
{
void dac_concurrent_software_trigger_disable(void) {
uint32_t swt = 0U;
swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
DAC_SWT &= (~swt);
@@ -480,8 +458,7 @@ void dac_concurrent_software_trigger_disable(void)
\param[out] none
\retval none
*/
void dac_concurrent_output_buffer_enable(void)
{
void dac_concurrent_output_buffer_enable(void) {
uint32_t ctl = 0U;
ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
DAC_CTL &= (~ctl);
@@ -493,8 +470,7 @@ void dac_concurrent_output_buffer_enable(void)
\param[out] none
\retval none
*/
void dac_concurrent_output_buffer_disable(void)
{
void dac_concurrent_output_buffer_disable(void) {
uint32_t ctl = 0U;
ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
DAC_CTL |= (ctl);
@@ -512,10 +488,9 @@ void dac_concurrent_output_buffer_disable(void)
\param[out] none
\retval none
*/
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1)
{
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) {
uint32_t data = 0U;
switch(dac_align){
switch (dac_align) {
/* data right 12b alignment */
case DAC_ALIGN_12B_R:
data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0;

25
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dbg.c vendored
View File

@@ -40,10 +40,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval DBG_ID code
*/
uint32_t dbg_id_get(void)
{
return DBG_ID;
}
uint32_t dbg_id_get(void) { return DBG_ID; }
/*!
\brief enable low power behavior when the mcu is in debug mode
@@ -55,10 +52,7 @@ uint32_t dbg_id_get(void)
\param[out] none
\retval none
*/
void dbg_low_power_enable(uint32_t dbg_low_power)
{
DBG_CTL |= dbg_low_power;
}
void dbg_low_power_enable(uint32_t dbg_low_power) { DBG_CTL |= dbg_low_power; }
/*!
\brief disable low power behavior when the mcu is in debug mode
@@ -70,10 +64,7 @@ void dbg_low_power_enable(uint32_t dbg_low_power)
\param[out] none
\retval none
*/
void dbg_low_power_disable(uint32_t dbg_low_power)
{
DBG_CTL &= ~dbg_low_power;
}
void dbg_low_power_disable(uint32_t dbg_low_power) { DBG_CTL &= ~dbg_low_power; }
/*!
\brief enable peripheral behavior when the mcu is in debug mode
@@ -87,10 +78,7 @@ void dbg_low_power_disable(uint32_t dbg_low_power)
\param[out] none
\retval none
*/
void dbg_periph_enable(dbg_periph_enum dbg_periph)
{
DBG_CTL |= (uint32_t)dbg_periph;
}
void dbg_periph_enable(dbg_periph_enum dbg_periph) { DBG_CTL |= (uint32_t)dbg_periph; }
/*!
\brief disable peripheral behavior when the mcu is in debug mode
@@ -104,7 +92,4 @@ void dbg_periph_enable(dbg_periph_enum dbg_periph)
\param[out] none
\retval none
*/
void dbg_periph_disable(dbg_periph_enum dbg_periph)
{
DBG_CTL &= ~(uint32_t)dbg_periph;
}
void dbg_periph_disable(dbg_periph_enum dbg_periph) { DBG_CTL &= ~(uint32_t)dbg_periph; }

163
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dma.c vendored
View File

@@ -34,7 +34,8 @@ OF SUCH DAMAGE.
#include "gd32vf103_dma.h"
#define DMA_WRONG_HANDLE while(1){}
#define DMA_WRONG_HANDLE \
while (1) {}
/* check whether peripheral matches channels or not */
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx);
@@ -49,9 +50,8 @@ static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_e
\param[out] none
\retval none
*/
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -71,8 +71,7 @@ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_struct_para_init(dma_parameter_struct* init_struct)
{
void dma_struct_para_init(dma_parameter_struct *init_struct) {
/* set the DMA struct with the default values */
init_struct->periph_addr = 0U;
init_struct->periph_width = 0U;
@@ -105,11 +104,10 @@ void dma_struct_para_init(dma_parameter_struct* init_struct)
\param[out] none
\retval none
*/
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct)
{
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct) {
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -129,23 +127,23 @@ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_stru
DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){
if (DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
}else{
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
}
/* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){
if (DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
}else{
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/* configure the direction of data transfer */
if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){
if (DMA_PERIPHERAL_TO_MEMORY == init_struct->direction) {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
}else{
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
}
}
@@ -160,9 +158,8 @@ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_stru
\param[out] none
\retval none
*/
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -179,9 +176,8 @@ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -198,9 +194,8 @@ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -217,9 +212,8 @@ void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -236,9 +230,8 @@ void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx
\param[out] none
\retval none
*/
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -255,9 +248,8 @@ void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -275,9 +267,8 @@ void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -295,9 +286,8 @@ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, u
\param[out] none
\retval none
*/
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -315,9 +305,8 @@ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, u
\param[out] none
\retval none
*/
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -334,9 +323,8 @@ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx,
\param[out] none
\retval uint32_t: the number of remaining data to be transferred by the DMA
*/
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -359,11 +347,10 @@ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
{
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) {
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -390,11 +377,10 @@ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_
\param[out] none
\retval none
*/
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
{
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) {
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -421,11 +407,10 @@ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin
\param[out] none
\retval none
*/
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
{
void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) {
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -447,9 +432,8 @@ void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, ui
\param[out] none
\retval none
*/
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -466,9 +450,8 @@ void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -485,9 +468,8 @@ void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -504,9 +486,8 @@ void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -527,13 +508,12 @@ void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
\param[out] none
\retval none
*/
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
if(DMA_PERIPHERAL_TO_MEMORY == direction){
if (DMA_PERIPHERAL_TO_MEMORY == direction) {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
@@ -556,13 +536,12 @@ void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channel
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) {
FlagStatus reval;
if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){
if (RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))) {
reval = SET;
}else{
} else {
reval = RESET;
}
@@ -585,10 +564,7 @@ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t
\param[out] none
\retval none
*/
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
}
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); }
/*!
\brief check DMA flag and interrupt enable bit is set or not
@@ -605,11 +581,10 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) {
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
switch(flag){
switch (flag) {
case DMA_INT_FLAG_FTF:
/* check whether the full transfer finish interrupt flag is set and enabled */
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
@@ -630,9 +605,9 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
}
/* when the interrupt flag is set and enabled, return SET */
if(interrupt_flag && interrupt_enable){
if (interrupt_flag && interrupt_enable) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -653,10 +628,7 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
\param[out] none
\retval none
*/
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
}
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); }
/*!
\brief enable DMA interrupt
@@ -673,9 +645,8 @@ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, ui
\param[out] none
\retval none
*/
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -697,9 +668,8 @@ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32
\param[out] none
\retval none
*/
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) {
if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) {
DMA_WRONG_HANDLE
}
@@ -716,13 +686,12 @@ void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint3
\param[out] none
\retval none
*/
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx)
{
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) {
ErrStatus val = SUCCESS;
if(DMA1 == dma_periph){
if (DMA1 == dma_periph) {
/* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */
if(channelx > DMA_CH4){
if (channelx > DMA_CH4) {
val = ERROR;
}
}

11
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_eclic.c vendored
View File

@@ -37,7 +37,6 @@ OF SUCH DAMAGE.
#define REG_DBGMCU2 ((uint32_t)0xE0042008)
#define REG_DBGMCU2EN ((uint32_t)0xE004200C)
/*!
\brief set the priority group
\param[in] prigroup: specify the priority group
@@ -49,10 +48,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void eclic_priority_group_set(uint32_t prigroup) {
ECLIC_SetCfgNlbits(prigroup);
}
void eclic_priority_group_set(uint32_t prigroup) { ECLIC_SetCfgNlbits(prigroup); }
/*!
\brief enable the interrupt request
@@ -74,9 +70,7 @@ void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority) {
\param[out] none
\retval none
*/
void eclic_irq_disable(uint32_t source) {
ECLIC_DisableIRQ(source);
}
void eclic_irq_disable(uint32_t source) { ECLIC_DisableIRQ(source); }
/*!
\brief reset system
@@ -88,4 +82,3 @@ void eclic_system_reset(void) {
REG32(REG_DBGMCU2EN) = 0x4b5a6978;
REG32(REG_DBGMCU2) = 0x1;
}

44
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exmc.c vendored
View File

@@ -55,10 +55,9 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void exmc_norsram_deinit(uint32_t norsram_region)
{
void exmc_norsram_deinit(uint32_t norsram_region) {
/* reset the registers */
if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){
if (EXMC_BANK0_NORSRAM_REGION0 == norsram_region) {
EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET;
}
@@ -71,8 +70,7 @@ void exmc_norsram_deinit(uint32_t norsram_region)
\param[out] exmc_norsram_init_struct: the initialized structure exmc_norsram_parameter_struct pointer
\retval none
*/
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
{
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) {
/* configure the structure with default value */
exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
exmc_norsram_init_struct->address_data_mux = ENABLE;
@@ -105,32 +103,26 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i
\param[out] none
\retval none
*/
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
{
void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) {
uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U;
/* get the register value */
snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
/* clear relative bits */
snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL |
EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX));
snctl &= ((uint32_t) ~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX));
snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
exmc_norsram_init_struct->memory_type |
exmc_norsram_init_struct->databus_width |
exmc_norsram_init_struct->nwait_polarity |
(exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
(exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
(exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET);
snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | exmc_norsram_init_struct->memory_type | exmc_norsram_init_struct->databus_width
| exmc_norsram_init_struct->nwait_polarity | (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET)
| (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET);
sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
(((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT );
sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U) & EXMC_SNTCFG_ASET)
| (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET) & EXMC_SNTCFG_AHLD)
| (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNTCFG_DSET)
| (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U) << SNTCFG_BUSLAT_OFFSET) & EXMC_SNTCFG_BUSLAT);
/* nor flash access enable */
if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
if (EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) {
snctl |= (uint32_t)EXMC_SNCTL_NREN;
}
@@ -146,10 +138,7 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
\param[out] none
\retval none
*/
void exmc_norsram_enable(uint32_t norsram_region)
{
EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
}
void exmc_norsram_enable(uint32_t norsram_region) { EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; }
/*!
\brief disable EXMC NOR/PSRAM bank region
@@ -158,7 +147,4 @@ void exmc_norsram_enable(uint32_t norsram_region)
\param[out] none
\retval none
*/
void exmc_norsram_disable(uint32_t norsram_region)
{
EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
}
void exmc_norsram_disable(uint32_t norsram_region) { EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; }

82
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exti.c vendored
View File

@@ -42,8 +42,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void exti_deinit(void)
{
void exti_deinit(void) {
/* reset the value of all the EXTI registers */
EXTI_INTEN = EXTI_REG_RESET_VALUE;
EXTI_EVEN = EXTI_REG_RESET_VALUE;
@@ -70,21 +69,20 @@ void exti_deinit(void)
\param[out] none
\retval none
*/
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
{
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) {
/* reset the EXTI line x */
EXTI_INTEN &= ~(uint32_t) linex;
EXTI_EVEN &= ~(uint32_t) linex;
EXTI_RTEN &= ~(uint32_t) linex;
EXTI_FTEN &= ~(uint32_t) linex;
EXTI_INTEN &= ~(uint32_t)linex;
EXTI_EVEN &= ~(uint32_t)linex;
EXTI_RTEN &= ~(uint32_t)linex;
EXTI_FTEN &= ~(uint32_t)linex;
/* set the EXTI mode and enable the interrupts or events from EXTI line x */
switch (mode) {
case EXTI_INTERRUPT:
EXTI_INTEN |= (uint32_t) linex;
EXTI_INTEN |= (uint32_t)linex;
break;
case EXTI_EVENT:
EXTI_EVEN |= (uint32_t) linex;
EXTI_EVEN |= (uint32_t)linex;
break;
default:
break;
@@ -93,16 +91,16 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr
/* set the EXTI trigger type */
switch (trig_type) {
case EXTI_TRIG_RISING:
EXTI_RTEN |= (uint32_t) linex;
EXTI_FTEN &= ~(uint32_t) linex;
EXTI_RTEN |= (uint32_t)linex;
EXTI_FTEN &= ~(uint32_t)linex;
break;
case EXTI_TRIG_FALLING:
EXTI_RTEN &= ~(uint32_t) linex;
EXTI_FTEN |= (uint32_t) linex;
EXTI_RTEN &= ~(uint32_t)linex;
EXTI_FTEN |= (uint32_t)linex;
break;
case EXTI_TRIG_BOTH:
EXTI_RTEN |= (uint32_t) linex;
EXTI_FTEN |= (uint32_t) linex;
EXTI_RTEN |= (uint32_t)linex;
EXTI_FTEN |= (uint32_t)linex;
break;
case EXTI_TRIG_NONE:
default:
@@ -118,10 +116,7 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr
\param[out] none
\retval none
*/
void exti_interrupt_enable(exti_line_enum linex)
{
EXTI_INTEN |= (uint32_t) linex;
}
void exti_interrupt_enable(exti_line_enum linex) { EXTI_INTEN |= (uint32_t)linex; }
/*!
\brief enable the events from EXTI line x
@@ -131,10 +126,7 @@ void exti_interrupt_enable(exti_line_enum linex)
\param[out] none
\retval none
*/
void exti_event_enable(exti_line_enum linex)
{
EXTI_EVEN |= (uint32_t) linex;
}
void exti_event_enable(exti_line_enum linex) { EXTI_EVEN |= (uint32_t)linex; }
/*!
\brief disable the interrupt from EXTI line x
@@ -144,10 +136,7 @@ void exti_event_enable(exti_line_enum linex)
\param[out] none
\retval none
*/
void exti_interrupt_disable(exti_line_enum linex)
{
EXTI_INTEN &= ~(uint32_t) linex;
}
void exti_interrupt_disable(exti_line_enum linex) { EXTI_INTEN &= ~(uint32_t)linex; }
/*!
\brief disable the events from EXTI line x
@@ -157,10 +146,7 @@ void exti_interrupt_disable(exti_line_enum linex)
\param[out] none
\retval none
*/
void exti_event_disable(exti_line_enum linex)
{
EXTI_EVEN &= ~(uint32_t) linex;
}
void exti_event_disable(exti_line_enum linex) { EXTI_EVEN &= ~(uint32_t)linex; }
/*!
\brief get EXTI lines flag
@@ -170,9 +156,8 @@ void exti_event_disable(exti_line_enum linex)
\param[out] none
\retval FlagStatus: status of flag (RESET or SET)
*/
FlagStatus exti_flag_get(exti_line_enum linex)
{
if (RESET != (EXTI_PD & (uint32_t) linex)) {
FlagStatus exti_flag_get(exti_line_enum linex) {
if (RESET != (EXTI_PD & (uint32_t)linex)) {
return SET;
} else {
return RESET;
@@ -187,10 +172,7 @@ FlagStatus exti_flag_get(exti_line_enum linex)
\param[out] none
\retval none
*/
void exti_flag_clear(exti_line_enum linex)
{
EXTI_PD = (uint32_t) linex;
}
void exti_flag_clear(exti_line_enum linex) { EXTI_PD = (uint32_t)linex; }
/*!
\brief get EXTI lines flag when the interrupt flag is set
@@ -200,12 +182,11 @@ void exti_flag_clear(exti_line_enum linex)
\param[out] none
\retval FlagStatus: status of flag (RESET or SET)
*/
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
{
FlagStatus exti_interrupt_flag_get(exti_line_enum linex) {
uint32_t flag_left, flag_right;
flag_left = EXTI_PD & (uint32_t) linex;
flag_right = EXTI_INTEN & (uint32_t) linex;
flag_left = EXTI_PD & (uint32_t)linex;
flag_right = EXTI_INTEN & (uint32_t)linex;
if ((RESET != flag_left) && (RESET != flag_right)) {
return SET;
@@ -222,10 +203,7 @@ FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
\param[out] none
\retval none
*/
void exti_interrupt_flag_clear(exti_line_enum linex)
{
EXTI_PD = (uint32_t) linex;
}
void exti_interrupt_flag_clear(exti_line_enum linex) { EXTI_PD = (uint32_t)linex; }
/*!
\brief enable EXTI software interrupt event
@@ -235,10 +213,7 @@ void exti_interrupt_flag_clear(exti_line_enum linex)
\param[out] none
\retval none
*/
void exti_software_interrupt_enable(exti_line_enum linex)
{
EXTI_SWIEV |= (uint32_t) linex;
}
void exti_software_interrupt_enable(exti_line_enum linex) { EXTI_SWIEV |= (uint32_t)linex; }
/*!
\brief disable EXTI software interrupt event
@@ -248,7 +223,4 @@ void exti_software_interrupt_enable(exti_line_enum linex)
\param[out] none
\retval none
*/
void exti_software_interrupt_disable(exti_line_enum linex)
{
EXTI_SWIEV &= ~(uint32_t) linex;
}
void exti_software_interrupt_disable(exti_line_enum linex) { EXTI_SWIEV &= ~(uint32_t)linex; }

185
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fmc.c vendored
View File

@@ -43,8 +43,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void fmc_wscnt_set(uint32_t wscnt)
{
void fmc_wscnt_set(uint32_t wscnt) {
uint32_t reg;
reg = FMC_WS;
@@ -59,9 +58,8 @@ void fmc_wscnt_set(uint32_t wscnt)
\param[out] none
\retval none
*/
void fmc_unlock(void)
{
if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
void fmc_unlock(void) {
if ((RESET != (FMC_CTL0 & FMC_CTL0_LK))) {
/* write the FMC unlock key */
FMC_KEY0 = UNLOCK_KEY0;
FMC_KEY0 = UNLOCK_KEY1;
@@ -74,21 +72,18 @@ void fmc_unlock(void)
\param[out] none
\retval none
*/
void fmc_lock(void)
{
void fmc_lock(void) {
/* set the LK bit */
FMC_CTL0 |= FMC_CTL0_LK;
}
/*!
\brief FMC erase page
\param[in] page_address: the page address to be erased.
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum fmc_page_erase(uint32_t page_address)
{
fmc_state_enum fmc_page_erase(uint32_t page_address) {
fmc_state_enum fmc_state;
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* if the last operation is completed, start page erase */
@@ -111,12 +106,11 @@ fmc_state_enum fmc_page_erase(uint32_t page_address)
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum fmc_mass_erase(void)
{
fmc_state_enum fmc_mass_erase(void) {
fmc_state_enum fmc_state;
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
if (FMC_READY == fmc_state) {
/* start whole chip erase */
FMC_CTL0 |= FMC_CTL0_MER;
FMC_CTL0 |= FMC_CTL0_START;
@@ -136,12 +130,11 @@ fmc_state_enum fmc_mass_erase(void)
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
{
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) {
fmc_state_enum fmc_state = FMC_READY;
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
if (FMC_READY == fmc_state) {
/* set the PG bit to start program */
FMC_CTL0 |= FMC_CTL0_PG;
REG32(address) = data;
@@ -160,12 +153,11 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
{
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) {
fmc_state_enum fmc_state = FMC_READY;
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
if (FMC_READY == fmc_state) {
/* set the PG bit to start program */
FMC_CTL0 |= FMC_CTL0_PG;
REG16(address) = data;
@@ -184,17 +176,15 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
\param[out] none
\retval none
*/
void ob_unlock(void)
{
if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
void ob_unlock(void) {
if (RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)) {
/* write the FMC key */
FMC_OBKEY = UNLOCK_KEY0;
FMC_OBKEY = UNLOCK_KEY1;
}
/* wait until OBWEN bit is set by hardware */
while (RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)) {
}
while (RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)) {}
}
/*!
@@ -203,8 +193,7 @@ void ob_unlock(void)
\param[out] none
\retval none
*/
void ob_lock(void)
{
void ob_lock(void) {
/* reset the OBWEN bit */
FMC_CTL0 &= ~FMC_CTL0_OBWEN;
}
@@ -216,18 +205,17 @@ void ob_lock(void)
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum ob_erase(void)
{
fmc_state_enum ob_erase(void) {
uint16_t temp_spc = FMC_NSPC;
fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* check the option byte security protection value */
if(RESET != ob_spc_get()){
if (RESET != ob_spc_get()) {
temp_spc = FMC_USPC;
}
if(FMC_READY == fmc_state){
if (FMC_READY == fmc_state) {
/* start erase the option byte */
FMC_CTL0 |= FMC_CTL0_OBER;
@@ -236,21 +224,21 @@ fmc_state_enum ob_erase(void)
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
if (FMC_READY == fmc_state) {
/* reset the OBER bit */
FMC_CTL0 &= ~FMC_CTL0_OBER;
/* set the OBPG bit */
FMC_CTL0 |= FMC_CTL0_OBPG;
/* no security protection */
OB_SPC = (uint16_t) temp_spc;
OB_SPC = (uint16_t)temp_spc;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
}
}else{
if(FMC_TOERR != fmc_state){
} else {
if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
}
@@ -271,48 +259,47 @@ fmc_state_enum ob_erase(void)
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
{
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) {
uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3;
fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
ob_wp = (uint32_t) (~ob_wp);
temp_wp0 = (uint16_t) (ob_wp & OB_WP0_WP0);
temp_wp1 = (uint16_t) ((ob_wp & OB_WP1_WP1) >> 8U);
temp_wp2 = (uint16_t) ((ob_wp & OB_WP2_WP2) >> 16U);
temp_wp3 = (uint16_t) ((ob_wp & OB_WP3_WP3) >> 24U);
ob_wp = (uint32_t)(~ob_wp);
temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0);
temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U);
temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U);
temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U);
if(FMC_READY == fmc_state){
if (FMC_READY == fmc_state) {
/* set the OBPG bit*/
FMC_CTL0 |= FMC_CTL0_OBPG;
if(0xFFU != temp_wp0){
if (0xFFU != temp_wp0) {
OB_WP0 = temp_wp0;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
}
if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){
if ((FMC_READY == fmc_state) && (0xFFU != temp_wp1)) {
OB_WP1 = temp_wp1;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
}
if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){
if ((FMC_READY == fmc_state) && (0xFFU != temp_wp2)) {
OB_WP2 = temp_wp2;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
}
if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){
if ((FMC_READY == fmc_state) && (0xFFU != temp_wp3)) {
OB_WP3 = temp_wp3;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
}
if(FMC_TOERR != fmc_state){
if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
}
@@ -330,25 +317,24 @@ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
{
fmc_state_enum ob_security_protection_config(uint8_t ob_spc) {
fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
if (FMC_READY == fmc_state) {
FMC_CTL0 |= FMC_CTL0_OBER;
FMC_CTL0 |= FMC_CTL0_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
if (FMC_READY == fmc_state) {
/* reset the OBER bit */
FMC_CTL0 &= ~FMC_CTL0_OBER;
/* start the option byte program */
FMC_CTL0 |= FMC_CTL0_OBPG;
OB_SPC = (uint16_t) ob_spc;
OB_SPC = (uint16_t)ob_spc;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
@@ -357,7 +343,7 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
}
}else{
} else {
if (FMC_TOERR != fmc_state) {
/* reset the OBER bit */
FMC_CTL0 &= ~FMC_CTL0_OBER;
@@ -384,25 +370,24 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot)
{
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) {
fmc_state_enum fmc_state = FMC_READY;
uint8_t temp;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
if (FMC_READY == fmc_state) {
/* set the OBPG bit*/
FMC_CTL0 |= FMC_CTL0_OBPG;
temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK);
OB_USER = (uint16_t) temp;
OB_USER = (uint16_t)temp;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_TOERR != fmc_state){
if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
}
@@ -421,7 +406,7 @@ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_
fmc_state_enum ob_data_program(uint32_t address, uint8_t data) {
fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
if (FMC_READY == fmc_state) {
/* set the OBPG bit */
FMC_CTL0 |= FMC_CTL0_OBPG;
REG16(address) = data;
@@ -429,7 +414,7 @@ fmc_state_enum ob_data_program(uint32_t address, uint8_t data) {
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_TOERR != fmc_state){
if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
}
@@ -444,10 +429,9 @@ fmc_state_enum ob_data_program(uint32_t address, uint8_t data) {
\param[out] none
\retval the FMC user option byte values
*/
uint8_t ob_user_get(void)
{
uint8_t ob_user_get(void) {
/* return the FMC user option byte value */
return (uint8_t) (FMC_OBSTAT >> 2U);
return (uint8_t)(FMC_OBSTAT >> 2U);
}
/*!
@@ -456,10 +440,7 @@ uint8_t ob_user_get(void)
\param[out] none
\retval ob_data
*/
uint16_t ob_data_get(void)
{
return (uint16_t) (FMC_OBSTAT >> 10U);
}
uint16_t ob_data_get(void) { return (uint16_t)(FMC_OBSTAT >> 10U); }
/*!
\brief get the FMC option byte write protection
@@ -467,8 +448,7 @@ uint16_t ob_data_get(void)
\param[out] none
\retval the FMC write protection option byte value
*/
uint32_t ob_write_protection_get(void)
{
uint32_t ob_write_protection_get(void) {
/* return the FMC write protection option byte value */
return FMC_WP;
}
@@ -479,13 +459,12 @@ uint32_t ob_write_protection_get(void)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus ob_spc_get(void)
{
FlagStatus ob_spc_get(void) {
FlagStatus spc_state = RESET;
if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){
if (RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)) {
spc_state = SET;
}else{
} else {
spc_state = RESET;
}
return spc_state;
@@ -500,10 +479,7 @@ FlagStatus ob_spc_get(void)
\param[out] none
\retval none
*/
void fmc_interrupt_enable(uint32_t interrupt)
{
FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt));
}
void fmc_interrupt_enable(uint32_t interrupt) { FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); }
/*!
\brief disable FMC interrupt
@@ -514,10 +490,7 @@ void fmc_interrupt_enable(uint32_t interrupt)
\param[out] none
\retval none
*/
void fmc_interrupt_disable(uint32_t interrupt)
{
FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt));
}
void fmc_interrupt_disable(uint32_t interrupt) { FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); }
/*!
\brief check flag is set or not
@@ -531,9 +504,8 @@ void fmc_interrupt_disable(uint32_t interrupt)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus fmc_flag_get(uint32_t flag)
{
if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){
FlagStatus fmc_flag_get(uint32_t flag) {
if (RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))) {
return SET;
} else {
return RESET;
@@ -550,10 +522,7 @@ FlagStatus fmc_flag_get(uint32_t flag)
\param[out] none
\retval none
*/
void fmc_flag_clear(uint32_t flag)
{
FMC_REG_VAL(flag) = (!FMC_REG_VAL(flag)) | BIT(FMC_BIT_POS(flag));
}
void fmc_flag_clear(uint32_t flag) { FMC_REG_VAL(flag) = (!FMC_REG_VAL(flag)) | BIT(FMC_BIT_POS(flag)); }
/*!
\brief get FMC interrupt flag state
@@ -565,21 +534,20 @@ void fmc_flag_clear(uint32_t flag)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag)
{
FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) {
FlagStatus ret1 = RESET;
FlagStatus ret2 = RESET;
if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){
if (FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)) {
/* get the staus of interrupt flag */
ret1 = (FlagStatus) (FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
/* get the staus of interrupt enale bit */
ret2 = (FlagStatus) (FMC_CTL0 & BIT(FMC_BIT_POS1(flag)));
ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag)));
}
if(ret1 && ret2){
if (ret1 && ret2) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -594,10 +562,7 @@ FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag)
\param[out] none
\retval none
*/
void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag)
{
FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag));
}
void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) { FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); }
/*!
\brief get the FMC state
@@ -605,17 +570,16 @@ void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag)
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum fmc_state_get(void)
{
fmc_state_enum fmc_state_get(void) {
fmc_state_enum fmc_state = FMC_READY;
if((uint32_t) 0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){
if ((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)) {
fmc_state = FMC_BUSY;
}else{
if((uint32_t) 0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){
} else {
if ((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)) {
fmc_state = FMC_WPERR;
}else{
if((uint32_t) 0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){
} else {
if ((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))) {
fmc_state = FMC_PGERR;
}
}
@@ -630,18 +594,17 @@ fmc_state_enum fmc_state_get(void)
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum fmc_ready_wait(uint32_t timeout)
{
fmc_state_enum fmc_ready_wait(uint32_t timeout) {
fmc_state_enum fmc_state = FMC_BUSY;
/* wait for FMC ready */
do{
do {
/* get FMC state */
fmc_state = fmc_state_get();
timeout--;
}while((FMC_BUSY == fmc_state) && (0x00U != timeout));
} while ((FMC_BUSY == fmc_state) && (0x00U != timeout));
if(FMC_BUSY == fmc_state){
if (FMC_BUSY == fmc_state) {
fmc_state = FMC_TOERR;
}
/* return the FMC state */

44
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fwdgt.c vendored
View File

@@ -35,9 +35,9 @@ OF SUCH DAMAGE.
#include "gd32vf103_fwdgt.h"
/* write value to FWDGT_CTL_CMD bit field */
#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
#define CTL_CMD(regval) (BITS(0, 15) & ((uint32_t)(regval) << 0))
/* write value to FWDGT_RLD_RLD bit field */
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
#define RLD_RLD(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0))
/*!
\brief enable write access to FWDGT_PSC and FWDGT_RLD
@@ -45,10 +45,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void fwdgt_write_enable(void)
{
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
}
void fwdgt_write_enable(void) { FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; }
/*!
\brief disable write access to FWDGT_PSC and FWDGT_RLD
@@ -56,10 +53,7 @@ void fwdgt_write_enable(void)
\param[out] none
\retval none
*/
void fwdgt_write_disable(void)
{
FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
}
void fwdgt_write_disable(void) { FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; }
/*!
\brief start the free watchdog timer counter
@@ -67,10 +61,7 @@ void fwdgt_write_disable(void)
\param[out] none
\retval none
*/
void fwdgt_enable(void)
{
FWDGT_CTL = FWDGT_KEY_ENABLE;
}
void fwdgt_enable(void) { FWDGT_CTL = FWDGT_KEY_ENABLE; }
/*!
\brief reload the counter of FWDGT
@@ -78,10 +69,7 @@ void fwdgt_enable(void)
\param[out] none
\retval none
*/
void fwdgt_counter_reload(void)
{
FWDGT_CTL = FWDGT_KEY_RELOAD;
}
void fwdgt_counter_reload(void) { FWDGT_CTL = FWDGT_KEY_RELOAD; }
/*!
\brief configure counter reload value, and prescaler divider value
@@ -98,19 +86,18 @@ void fwdgt_counter_reload(void)
\param[out] none
\retval ErrStatus: ERROR or SUCCESS
*/
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
{
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) {
uint32_t timeout = FWDGT_PSC_TIMEOUT;
uint32_t flag_status = RESET;
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
/* wait until the PUD flag to be reset */
do{
do {
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
} while ((--timeout > 0U) && ((uint32_t)RESET != flag_status));
if((uint32_t)RESET != flag_status){
if ((uint32_t)RESET != flag_status) {
return ERROR;
}
/* configure FWDGT */
@@ -118,11 +105,11 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
timeout = FWDGT_RLD_TIMEOUT;
/* wait until the RUD flag to be reset */
do{
do {
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
} while ((--timeout > 0U) && ((uint32_t)RESET != flag_status));
if((uint32_t)RESET != flag_status){
if ((uint32_t)RESET != flag_status) {
return ERROR;
}
FWDGT_RLD = RLD_RLD(reload_value);
@@ -141,9 +128,8 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus fwdgt_flag_get(uint16_t flag)
{
if(FWDGT_STAT & flag){
FlagStatus fwdgt_flag_get(uint16_t flag) {
if (FWDGT_STAT & flag) {
return SET;
}

124
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_gpio.c vendored
View File

@@ -50,8 +50,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void gpio_deinit(uint32_t gpio_periph)
{
void gpio_deinit(uint32_t gpio_periph) {
switch (gpio_periph) {
case GPIOA:
/* reset GPIOA */
@@ -89,8 +88,7 @@ void gpio_deinit(uint32_t gpio_periph)
\param[out] none
\retval none
*/
void gpio_afio_deinit(void)
{
void gpio_afio_deinit(void) {
rcu_periph_reset_enable(RCU_AFRST);
rcu_periph_reset_disable(RCU_AFRST);
}
@@ -120,20 +118,18 @@ void gpio_afio_deinit(void)
\param[out] none
\retval none
*/
void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed,
uint32_t pin)
{
void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) {
uint16_t i;
uint32_t temp_mode = 0U;
uint32_t reg = 0U;
/* GPIO mode configuration */
temp_mode = (uint32_t) (mode & ((uint32_t) 0x0FU));
temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU));
/* GPIO speed configuration */
if (((uint32_t) 0x00U) != ((uint32_t) mode & ((uint32_t) 0x10U))) {
if (((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))) {
/* output mode max speed:10MHz,2MHz,50MHz */
temp_mode |= (uint32_t) speed;
temp_mode |= (uint32_t)speed;
}
/* configure the eight low port pins with GPIO_CTL0 */
@@ -149,11 +145,11 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed,
/* set IPD or IPU */
if (GPIO_MODE_IPD == mode) {
/* reset the corresponding OCTL bit */
GPIO_BC(gpio_periph) = (uint32_t) ((1U << i) & pin);
GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin);
} else {
/* set the corresponding OCTL bit */
if (GPIO_MODE_IPU == mode) {
GPIO_BOP(gpio_periph) = (uint32_t) ((1U << i) & pin);
GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin);
}
}
/* set GPIO_CTL0 register */
@@ -173,11 +169,11 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed,
/* set IPD or IPU */
if (GPIO_MODE_IPD == mode) {
/* reset the corresponding OCTL bit */
GPIO_BC(gpio_periph) = (uint32_t) ((1U << i) & pin);
GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin);
} else {
/* set the corresponding OCTL bit */
if (GPIO_MODE_IPU == mode) {
GPIO_BOP(gpio_periph) = (uint32_t) ((1U << i) & pin);
GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin);
}
}
/* set GPIO_CTL1 register */
@@ -195,10 +191,7 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed,
\param[out] none
\retval none
*/
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
{
GPIO_BOP(gpio_periph) = (uint32_t) pin;
}
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) { GPIO_BOP(gpio_periph) = (uint32_t)pin; }
/*!
\brief reset GPIO pin
@@ -209,10 +202,7 @@ void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
\param[out] none
\retval none
*/
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
{
GPIO_BC(gpio_periph) = (uint32_t) pin;
}
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) { GPIO_BC(gpio_periph) = (uint32_t)pin; }
/*!
\brief write data to the specified GPIO pin
@@ -227,12 +217,11 @@ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
\param[out] none
\retval none
*/
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
{
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) {
if (RESET != bit_value) {
GPIO_BOP(gpio_periph) = (uint32_t) pin;
GPIO_BOP(gpio_periph) = (uint32_t)pin;
} else {
GPIO_BC(gpio_periph) = (uint32_t) pin;
GPIO_BC(gpio_periph) = (uint32_t)pin;
}
}
@@ -243,10 +232,7 @@ void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
\param[out] none
\retval none
*/
void gpio_port_write(uint32_t gpio_periph, uint16_t data)
{
GPIO_OCTL(gpio_periph) = (uint32_t) data;
}
void gpio_port_write(uint32_t gpio_periph, uint16_t data) { GPIO_OCTL(gpio_periph) = (uint32_t)data; }
/*!
\brief get GPIO pin input status
@@ -257,9 +243,8 @@ void gpio_port_write(uint32_t gpio_periph, uint16_t data)
\param[out] none
\retval input status of gpio pin: SET or RESET
*/
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
{
if ((uint32_t) RESET != (GPIO_ISTAT(gpio_periph) & (pin))) {
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) {
if ((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) {
return SET;
} else {
return RESET;
@@ -272,10 +257,7 @@ FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
\param[out] none
\retval input status of gpio all pins
*/
uint16_t gpio_input_port_get(uint32_t gpio_periph)
{
return (uint16_t) (GPIO_ISTAT(gpio_periph));
}
uint16_t gpio_input_port_get(uint32_t gpio_periph) { return (uint16_t)(GPIO_ISTAT(gpio_periph)); }
/*!
\brief get GPIO pin output status
@@ -286,9 +268,8 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph)
\param[out] none
\retval output status of gpio pin: SET or RESET
*/
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
{
if ((uint32_t) RESET != (GPIO_OCTL(gpio_periph) & (pin))) {
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) {
if ((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) {
return SET;
} else {
return RESET;
@@ -301,10 +282,7 @@ FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
\param[out] none
\retval output status of gpio all pins
*/
uint16_t gpio_output_port_get(uint32_t gpio_periph)
{
return ((uint16_t) GPIO_OCTL(gpio_periph));
}
uint16_t gpio_output_port_get(uint32_t gpio_periph) { return ((uint16_t)GPIO_OCTL(gpio_periph)); }
/*!
\brief configure GPIO pin remap
@@ -338,8 +316,7 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph)
\param[out] none
\retval none
*/
void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue)
{
void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) {
uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U;
if (AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) {
@@ -354,12 +331,11 @@ void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue)
remap1 = remap & LSB_16BIT_MASK;
/* judge pin remap type */
if ((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK)
== (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))) {
if ((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))) {
temp_reg &= PCF_SWJCFG_MASK;
AFIO_PCF0 &= PCF_SWJCFG_MASK;
} else if (PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)) {
remap2 = ((uint32_t) 0x03U) << temp_mask;
remap2 = ((uint32_t)0x03U) << temp_mask;
temp_reg &= ~remap2;
temp_reg |= ~PCF_SWJCFG_MASK;
} else {
@@ -394,37 +370,27 @@ void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue)
\param[out] none
\retval none
*/
void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin)
{
void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) {
uint32_t source = 0U;
source = ((uint32_t) 0x0FU)
<< (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK));
source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK));
/* select EXTI sources */
if (GPIO_PIN_SOURCE_4 > output_pin) {
/* select EXTI0/EXTI1/EXTI2/EXTI3 */
AFIO_EXTISS0 &= ~source;
AFIO_EXTISS0 |= (((uint32_t) output_port)
<< (AFIO_EXTI_SOURCE_FIELDS
* (output_pin & AFIO_EXTI_SOURCE_MASK)));
AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
} else if (GPIO_PIN_SOURCE_8 > output_pin) {
/* select EXTI4/EXTI5/EXTI6/EXTI7 */
AFIO_EXTISS1 &= ~source;
AFIO_EXTISS1 |= (((uint32_t) output_port)
<< (AFIO_EXTI_SOURCE_FIELDS
* (output_pin & AFIO_EXTI_SOURCE_MASK)));
AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
} else if (GPIO_PIN_SOURCE_12 > output_pin) {
/* select EXTI8/EXTI9/EXTI10/EXTI11 */
AFIO_EXTISS2 &= ~source;
AFIO_EXTISS2 |= (((uint32_t) output_port)
<< (AFIO_EXTI_SOURCE_FIELDS
* (output_pin & AFIO_EXTI_SOURCE_MASK)));
AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
} else {
/* select EXTI12/EXTI13/EXTI14/EXTI15 */
AFIO_EXTISS3 &= ~source;
AFIO_EXTISS3 |= (((uint32_t) output_port)
<< (AFIO_EXTI_SOURCE_FIELDS
* (output_pin & AFIO_EXTI_SOURCE_MASK)));
AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
}
}
@@ -443,16 +409,15 @@ void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin)
\param[out] none
\retval none
*/
void gpio_event_output_config(uint8_t output_port, uint8_t output_pin)
{
void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) {
uint32_t reg = 0U;
reg = AFIO_EC;
/* clear AFIO_EC_PORT and AFIO_EC_PIN bits */
reg &= (uint32_t) (~(AFIO_EC_PORT | AFIO_EC_PIN));
reg &= (uint32_t)(~(AFIO_EC_PORT | AFIO_EC_PIN));
reg |= (uint32_t) ((uint32_t) output_port << GPIO_OUTPUT_PORT_OFFSET);
reg |= (uint32_t) output_pin;
reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET);
reg |= (uint32_t)output_pin;
AFIO_EC = reg;
}
@@ -463,10 +428,7 @@ void gpio_event_output_config(uint8_t output_port, uint8_t output_pin)
\param[out] none
\retval none
*/
void gpio_event_output_enable(void)
{
AFIO_EC |= AFIO_EC_EOE;
}
void gpio_event_output_enable(void) { AFIO_EC |= AFIO_EC_EOE; }
/*!
\brief disable GPIO pin event output
@@ -474,10 +436,7 @@ void gpio_event_output_enable(void)
\param[out] none
\retval none
*/
void gpio_event_output_disable(void)
{
AFIO_EC &= (uint32_t) (~AFIO_EC_EOE);
}
void gpio_event_output_disable(void) { AFIO_EC &= (uint32_t)(~AFIO_EC_EOE); }
/*!
\brief lock GPIO pin
@@ -488,15 +447,14 @@ void gpio_event_output_disable(void)
\param[out] none
\retval none
*/
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
{
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) {
uint32_t lock = 0x00010000U;
lock |= pin;
/* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */
GPIO_LOCK(gpio_periph) = (uint32_t) lock;
GPIO_LOCK(gpio_periph) = (uint32_t) pin;
GPIO_LOCK(gpio_periph) = (uint32_t) lock;
GPIO_LOCK(gpio_periph) = (uint32_t)lock;
GPIO_LOCK(gpio_periph) = (uint32_t)pin;
GPIO_LOCK(gpio_periph) = (uint32_t)lock;
lock = GPIO_LOCK(gpio_periph);
lock = GPIO_LOCK(gpio_periph);
}

131
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_i2c.c vendored
View File

@@ -50,8 +50,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void i2c_deinit(uint32_t i2c_periph)
{
void i2c_deinit(uint32_t i2c_periph) {
switch (i2c_periph) {
case I2C0:
/* reset I2C0 */
@@ -79,14 +78,13 @@ void i2c_deinit(uint32_t i2c_periph)
\param[out] none
\retval none
*/
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
{
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) {
uint32_t pclk1, clkc, freq, risetime;
uint32_t temp;
pclk1 = rcu_clock_freq_get(CK_APB1);
/* I2C peripheral clock frequency */
freq = (uint32_t) (pclk1 / 1000000U);
freq = (uint32_t)(pclk1 / 1000000U);
if (freq >= I2CCLK_MAX) {
freq = I2CCLK_MAX;
}
@@ -98,7 +96,7 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
if (100000U >= clkspeed) {
/* the maximum SCL rise time is 1000ns in standard mode */
risetime = (uint32_t) ((pclk1 / 1000000U) + 1U);
risetime = (uint32_t)((pclk1 / 1000000U) + 1U);
if (risetime >= I2CCLK_MAX) {
I2C_RT(i2c_periph) = I2CCLK_MAX;
} else if (risetime <= I2CCLK_MIN) {
@@ -106,7 +104,7 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
} else {
I2C_RT(i2c_periph) = risetime;
}
clkc = (uint32_t) (pclk1 / (clkspeed * 2U));
clkc = (uint32_t)(pclk1 / (clkspeed * 2U));
if (clkc < 0x04U) {
/* the CLKC in standard mode minmum value is 4 */
clkc = 0x04U;
@@ -115,15 +113,14 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
} else if (400000U >= clkspeed) {
/* the maximum SCL rise time is 300ns in fast mode */
I2C_RT(i2c_periph) = (uint32_t) (((freq * (uint32_t) 300U)
/ (uint32_t) 1000U) + (uint32_t) 1U);
I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U);
if (I2C_DTCY_2 == dutycyc) {
/* I2C duty cycle is 2 */
clkc = (uint32_t) (pclk1 / (clkspeed * 3U));
clkc = (uint32_t)(pclk1 / (clkspeed * 3U));
I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
} else {
/* I2C duty cycle is 16/9 */
clkc = (uint32_t) (pclk1 / (clkspeed * 25U));
clkc = (uint32_t)(pclk1 / (clkspeed * 25U));
I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
}
if (0U == (clkc & I2C_CKCFG_CLKC)) {
@@ -151,8 +148,7 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
\param[out] none
\retval none
*/
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr)
{
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) {
/* SMBus/I2C mode selected */
uint32_t ctl = 0U;
@@ -175,8 +171,7 @@ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat,
\param[out] none
\retval none
*/
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
{
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) {
if (I2C_SMBUS_HOST == type) {
I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
} else {
@@ -194,8 +189,7 @@ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
\param[out] none
\retval none
*/
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
{
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) {
if (I2C_ACK_ENABLE == ack) {
I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
} else {
@@ -213,8 +207,7 @@ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
\param[out] none
\retval none
*/
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
{
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) {
/* configure I2C POAP position */
if (I2C_ACKPOS_NEXT == pos) {
I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
@@ -234,8 +227,7 @@ void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
\param[out] none
\retval none
*/
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection)
{
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) {
/* master is a transmitter or a receiver */
if (I2C_TRANSMITTER == trandirection) {
addr = addr & I2C_TRANSMITTER;
@@ -253,8 +245,7 @@ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirec
\param[out] none
\retval none
*/
void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr)
{
void i2c_saddr1_config(uint32_t i2c_periph, uint32_t addr) {
/* configure saddress1 */
I2C_SADDR1(i2c_periph) = (0xFE & addr);
}
@@ -266,8 +257,7 @@ void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr)
\param[out] none
\retval none
*/
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr)
{
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) {
/* configure address */
addr = addr & I2C_ADDRESS2_MASK;
I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr);
@@ -279,10 +269,7 @@ void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr)
\param[out] none
\retval none
*/
void i2c_dualaddr_disable(uint32_t i2c_periph)
{
I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
}
void i2c_dualaddr_disable(uint32_t i2c_periph) { I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); }
/*!
\brief enable I2C
@@ -290,10 +277,7 @@ void i2c_dualaddr_disable(uint32_t i2c_periph)
\param[out] none
\retval none
*/
void i2c_enable(uint32_t i2c_periph)
{
I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
}
void i2c_enable(uint32_t i2c_periph) { I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; }
/*!
\brief disable I2C
@@ -301,10 +285,7 @@ void i2c_enable(uint32_t i2c_periph)
\param[out] none
\retval none
*/
void i2c_disable(uint32_t i2c_periph)
{
I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
}
void i2c_disable(uint32_t i2c_periph) { I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); }
/*!
\brief generate a START condition on I2C bus
@@ -312,10 +293,7 @@ void i2c_disable(uint32_t i2c_periph)
\param[out] none
\retval none
*/
void i2c_start_on_bus(uint32_t i2c_periph)
{
I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
}
void i2c_start_on_bus(uint32_t i2c_periph) { I2C_CTL0(i2c_periph) |= I2C_CTL0_START; }
/*!
\brief generate a STOP condition on I2C bus
@@ -323,10 +301,7 @@ void i2c_start_on_bus(uint32_t i2c_periph)
\param[out] none
\retval none
*/
void i2c_stop_on_bus(uint32_t i2c_periph)
{
I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
}
void i2c_stop_on_bus(uint32_t i2c_periph) { I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; }
/*!
\brief I2C transmit data function
@@ -335,10 +310,7 @@ void i2c_stop_on_bus(uint32_t i2c_periph)
\param[out] none
\retval none
*/
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
{
I2C_DATA(i2c_periph) = DATA_TRANS(data);
}
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) { I2C_DATA(i2c_periph) = DATA_TRANS(data); }
/*!
\brief I2C receive data function
@@ -346,10 +318,7 @@ void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
\param[out] none
\retval data of received
*/
uint8_t i2c_data_receive(uint32_t i2c_periph)
{
return (uint8_t) DATA_RECV(I2C_DATA(i2c_periph));
}
uint8_t i2c_data_receive(uint32_t i2c_periph) { return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); }
/*!
\brief enable I2C DMA mode
@@ -361,8 +330,7 @@ uint8_t i2c_data_receive(uint32_t i2c_periph)
\param[out] none
\retval none
*/
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
{
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) {
/* configure I2C DMA function */
uint32_t ctl = 0U;
@@ -382,8 +350,7 @@ void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
\param[out] none
\retval none
*/
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast)
{
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) {
/* configure DMA last transfer */
uint32_t ctl = 0U;
@@ -403,8 +370,7 @@ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast)
\param[out] none
\retval none
*/
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
{
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) {
/* configure I2C SCL strerching enable or disable */
uint32_t ctl = 0U;
@@ -424,8 +390,7 @@ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
\param[out] none
\retval none
*/
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
{
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) {
/* configure slave response to a general call enable or disable */
uint32_t ctl = 0U;
@@ -445,8 +410,7 @@ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
\param[out] none
\retval none
*/
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
{
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) {
/* modify CTL0 and configure software reset I2C state */
uint32_t ctl = 0U;
@@ -466,8 +430,7 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
\param[out] none
\retval none
*/
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
{
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) {
/* on/off PEC calculation */
uint32_t ctl = 0U;
@@ -487,8 +450,7 @@ void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
\param[out] none
\retval none
*/
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
{
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) {
/* whether to transfer PEC */
uint32_t ctl = 0U;
@@ -504,10 +466,7 @@ void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
\param[out] none
\retval PEC value
*/
uint8_t i2c_pec_value_get(uint32_t i2c_periph)
{
return (uint8_t) ((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>> STAT1_PECV_OFFSET);
}
uint8_t i2c_pec_value_get(uint32_t i2c_periph) { return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); }
/*!
\brief I2C issue alert through SMBA pin
@@ -519,8 +478,7 @@ uint8_t i2c_pec_value_get(uint32_t i2c_periph)
\param[out] none
\retval none
*/
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
{
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) {
/* issue alert through SMBA pin configure*/
uint32_t ctl = 0U;
@@ -540,8 +498,7 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
\param[out] none
\retval none
*/
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
{
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) {
/* enable or disable I2C ARP protocol*/
uint32_t ctl = 0U;
@@ -580,8 +537,7 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag)
{
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) {
if (RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) {
return SET;
} else {
@@ -605,8 +561,7 @@ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag)
\param[out] none
\retval none
*/
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag)
{
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) {
uint32_t temp;
if (I2C_FLAG_ADDSEND == flag) {
/* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
@@ -628,10 +583,7 @@ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag)
\param[out] none
\retval none
*/
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
{
I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt));
}
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) { I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); }
/*!
\brief disable I2C interrupt
@@ -644,10 +596,7 @@ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
\param[out] none
\retval none
*/
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
{
I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt));
}
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) { I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); }
/*!
\brief check I2C interrupt flag
@@ -671,8 +620,7 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag)
{
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) {
uint32_t intenable = 0U, flagstatus = 0U, bufie;
/* check BUFIE */
@@ -681,7 +629,7 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum in
/* get the interrupt enable bit status */
intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag)));
/* get the corresponding flag bit status */
flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag)& BIT(I2C_BIT_POS2(int_flag)));
flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag)));
if ((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) {
if (intenable && bufie) {
@@ -713,8 +661,7 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum in
\param[out] none
\retval none
*/
void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag)
{
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) {
uint32_t temp;
if (I2C_INT_FLAG_ADDSEND == int_flag) {
/* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */

64
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_pmu.c vendored
View File

@@ -40,8 +40,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void pmu_deinit(void)
{
void pmu_deinit(void) {
/* reset PMU */
rcu_periph_reset_enable(RCU_PMURST);
rcu_periph_reset_disable(RCU_PMURST);
@@ -62,8 +61,7 @@ void pmu_deinit(void)
\param[out] none
\retval none
*/
void pmu_lvd_select(uint32_t lvdt_n)
{
void pmu_lvd_select(uint32_t lvdt_n) {
/* disable LVD */
PMU_CTL &= ~PMU_CTL_LVDEN;
/* clear LVDT bits */
@@ -80,8 +78,7 @@ void pmu_lvd_select(uint32_t lvdt_n)
\param[out] none
\retval none
*/
void pmu_lvd_disable(void)
{
void pmu_lvd_disable(void) {
/* disable LVD */
PMU_CTL &= ~PMU_CTL_LVDEN;
}
@@ -95,15 +92,14 @@ void pmu_lvd_disable(void)
\param[out] none
\retval none
*/
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
void pmu_to_sleepmode(uint8_t sleepmodecmd) {
/* clear sleepdeep bit of RISC-V system control register */
__RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
/* select WFI or WFE command to enter sleep mode */
if(WFI_CMD == sleepmodecmd){
if (WFI_CMD == sleepmodecmd) {
__WFI();
}else{
} else {
__disable_irq();
__WFE();
__enable_irq();
@@ -123,8 +119,7 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd)
\param[out] none
\retval none
*/
void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
{
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd) {
/* clear stbmod and ldolp bits */
PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
/* set ldolp bit according to pmu_ldo */
@@ -132,9 +127,9 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
/* set CSR_SLEEPVALUE bit of RISC-V system control register */
__RV_CSR_SET(CSR_WFE, WFE_WFE);
/* select WFI or WFE command to enter deepsleep mode */
if(WFI_CMD == deepsleepmodecmd){
if (WFI_CMD == deepsleepmodecmd) {
__WFI();
}else{
} else {
__disable_irq();
__WFE();
__enable_irq();
@@ -152,8 +147,7 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
\param[out] none
\retval none
*/
void pmu_to_standbymode(uint8_t standbymodecmd)
{
void pmu_to_standbymode(uint8_t standbymodecmd) {
/* set CSR_SLEEPVALUE bit of RISC-V system control register */
__RV_CSR_SET(CSR_WFE, WFE_WFE);
@@ -164,9 +158,9 @@ void pmu_to_standbymode(uint8_t standbymodecmd)
PMU_CTL |= PMU_CTL_WURST;
/* select WFI or WFE command to enter standby mode */
if(WFI_CMD == standbymodecmd){
if (WFI_CMD == standbymodecmd) {
__WFI();
}else{
} else {
__disable_irq();
__WFE();
__enable_irq();
@@ -180,10 +174,7 @@ void pmu_to_standbymode(uint8_t standbymodecmd)
\param[out] none
\retval none
*/
void pmu_wakeup_pin_enable(void)
{
PMU_CS |= PMU_CS_WUPEN;
}
void pmu_wakeup_pin_enable(void) { PMU_CS |= PMU_CS_WUPEN; }
/*!
\brief disable wakeup pin
@@ -191,10 +182,7 @@ void pmu_wakeup_pin_enable(void)
\param[out] none
\retval none
*/
void pmu_wakeup_pin_disable(void)
{
PMU_CS &= ~PMU_CS_WUPEN;
}
void pmu_wakeup_pin_disable(void) { PMU_CS &= ~PMU_CS_WUPEN; }
/*!
\brief enable write access to the registers in backup domain
@@ -202,10 +190,7 @@ void pmu_wakeup_pin_disable(void)
\param[out] none
\retval none
*/
void pmu_backup_write_enable(void)
{
PMU_CTL |= PMU_CTL_BKPWEN;
}
void pmu_backup_write_enable(void) { PMU_CTL |= PMU_CTL_BKPWEN; }
/*!
\brief disable write access to the registers in backup domain
@@ -213,10 +198,7 @@ void pmu_backup_write_enable(void)
\param[out] none
\retval none
*/
void pmu_backup_write_disable(void)
{
PMU_CTL &= ~PMU_CTL_BKPWEN;
}
void pmu_backup_write_disable(void) { PMU_CTL &= ~PMU_CTL_BKPWEN; }
/*!
\brief get flag state
@@ -228,11 +210,10 @@ void pmu_backup_write_disable(void)
\param[out] none
\retval FlagStatus SET or RESET
*/
FlagStatus pmu_flag_get(uint32_t flag)
{
if(PMU_CS & flag){
FlagStatus pmu_flag_get(uint32_t flag) {
if (PMU_CS & flag) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -246,9 +227,8 @@ FlagStatus pmu_flag_get(uint32_t flag)
\param[out] none
\retval none
*/
void pmu_flag_clear(uint32_t flag_reset)
{
switch(flag_reset){
void pmu_flag_clear(uint32_t flag_reset) {
switch (flag_reset) {
case PMU_FLAG_RESET_WAKEUP:
/* reset wakeup flag */
PMU_CTL |= PMU_CTL_WURST;
@@ -257,7 +237,7 @@ void pmu_flag_clear(uint32_t flag_reset)
/* reset standby flag */
PMU_CTL |= PMU_CTL_STBRST;
break;
default :
default:
break;
}
}

234
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rcu.c vendored
View File

@@ -34,31 +34,27 @@ OF SUCH DAMAGE.
#include "gd32vf103_rcu.h"
/*!
\brief deinitialize the RCU
\param[in] none
\param[out] none
\retval none
*/
void rcu_deinit(void)
{
void rcu_deinit(void) {
/* enable IRC8M */
RCU_CTL |= RCU_CTL_IRC8MEN;
rcu_osci_stab_wait(RCU_IRC8M);
/* reset CFG0 register */
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4);
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL
| RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4);
/* reset CTL register */
RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
RCU_CTL &= ~RCU_CTL_HXTALBPS;
RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN);
/* reset INT and CFG1 register */
RCU_INT = 0x00ff0000U;
RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF |
RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL);
RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL);
}
/*!
@@ -86,10 +82,7 @@ void rcu_deinit(void)
\param[out] none
\retval none
*/
void rcu_periph_clock_enable(rcu_periph_enum periph)
{
RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
}
void rcu_periph_clock_enable(rcu_periph_enum periph) { RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); }
/*!
\brief disable the peripherals clock
@@ -116,10 +109,7 @@ void rcu_periph_clock_enable(rcu_periph_enum periph)
\param[out] none
\retval none
*/
void rcu_periph_clock_disable(rcu_periph_enum periph)
{
RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
}
void rcu_periph_clock_disable(rcu_periph_enum periph) { RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); }
/*!
\brief enable the peripherals clock when sleep mode
@@ -130,10 +120,7 @@ void rcu_periph_clock_disable(rcu_periph_enum periph)
\param[out] none
\retval none
*/
void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
{
RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph));
}
void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) { RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); }
/*!
\brief disable the peripherals clock when sleep mode
@@ -144,10 +131,7 @@ void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph)
\param[out] none
\retval none
*/
void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
{
RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph));
}
void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) { RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); }
/*!
\brief reset the peripherals
@@ -170,10 +154,7 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph)
\param[out] none
\retval none
*/
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
{
RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset));
}
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) { RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); }
/*!
\brief disable reset the peripheral
@@ -196,10 +177,7 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset)
\param[out] none
\retval none
*/
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
{
RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset));
}
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) { RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); }
/*!
\brief reset the BKP domain
@@ -207,10 +185,7 @@ void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset)
\param[out] none
\retval none
*/
void rcu_bkp_reset_enable(void)
{
RCU_BDCTL |= RCU_BDCTL_BKPRST;
}
void rcu_bkp_reset_enable(void) { RCU_BDCTL |= RCU_BDCTL_BKPRST; }
/*!
\brief disable the BKP domain reset
@@ -218,10 +193,7 @@ void rcu_bkp_reset_enable(void)
\param[out] none
\retval none
*/
void rcu_bkp_reset_disable(void)
{
RCU_BDCTL &= ~RCU_BDCTL_BKPRST;
}
void rcu_bkp_reset_disable(void) { RCU_BDCTL &= ~RCU_BDCTL_BKPRST; }
/*!
\brief configure the system clock source
@@ -233,8 +205,7 @@ void rcu_bkp_reset_disable(void)
\param[out] none
\retval none
*/
void rcu_system_clock_source_config(uint32_t ck_sys)
{
void rcu_system_clock_source_config(uint32_t ck_sys) {
uint32_t reg;
reg = RCU_CFG0;
@@ -252,10 +223,7 @@ void rcu_system_clock_source_config(uint32_t ck_sys)
\arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source
\arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source
*/
uint32_t rcu_system_clock_source_get(void)
{
return (RCU_CFG0 & RCU_CFG0_SCSS);
}
uint32_t rcu_system_clock_source_get(void) { return (RCU_CFG0 & RCU_CFG0_SCSS); }
/*!
\brief configure the AHB clock prescaler selection
@@ -265,8 +233,7 @@ uint32_t rcu_system_clock_source_get(void)
\param[out] none
\retval none
*/
void rcu_ahb_clock_config(uint32_t ck_ahb)
{
void rcu_ahb_clock_config(uint32_t ck_ahb) {
uint32_t reg;
reg = RCU_CFG0;
@@ -288,8 +255,7 @@ void rcu_ahb_clock_config(uint32_t ck_ahb)
\param[out] none
\retval none
*/
void rcu_apb1_clock_config(uint32_t ck_apb1)
{
void rcu_apb1_clock_config(uint32_t ck_apb1) {
uint32_t reg;
reg = RCU_CFG0;
@@ -311,8 +277,7 @@ void rcu_apb1_clock_config(uint32_t ck_apb1)
\param[out] none
\retval none
*/
void rcu_apb2_clock_config(uint32_t ck_apb2)
{
void rcu_apb2_clock_config(uint32_t ck_apb2) {
uint32_t reg;
reg = RCU_CFG0;
@@ -338,8 +303,7 @@ void rcu_apb2_clock_config(uint32_t ck_apb2)
\param[out] none
\retval none
*/
void rcu_ckout0_config(uint32_t ckout0_src)
{
void rcu_ckout0_config(uint32_t ckout0_src) {
uint32_t reg;
reg = RCU_CFG0;
@@ -361,8 +325,7 @@ void rcu_ckout0_config(uint32_t ckout0_src)
\param[out] none
\retval none
*/
void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
{
void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) {
uint32_t reg = 0U;
reg = RCU_CFG0;
@@ -386,8 +349,7 @@ void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul)
\param[out] none
\retval none
*/
void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div)
{
void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) {
uint32_t reg = 0U;
reg = RCU_CFG1;
@@ -407,8 +369,7 @@ void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div)
\param[out] none
\retval none
*/
void rcu_predv1_config(uint32_t predv1_div)
{
void rcu_predv1_config(uint32_t predv1_div) {
uint32_t reg = 0U;
reg = RCU_CFG1;
@@ -428,8 +389,7 @@ void rcu_predv1_config(uint32_t predv1_div)
\param[out] none
\retval none
*/
void rcu_pll1_config(uint32_t pll_mul)
{
void rcu_pll1_config(uint32_t pll_mul) {
RCU_CFG1 &= ~RCU_CFG1_PLL1MF;
RCU_CFG1 |= pll_mul;
}
@@ -442,8 +402,7 @@ void rcu_pll1_config(uint32_t pll_mul)
\param[out] none
\retval none
*/
void rcu_pll2_config(uint32_t pll_mul)
{
void rcu_pll2_config(uint32_t pll_mul) {
RCU_CFG1 &= ~RCU_CFG1_PLL2MF;
RCU_CFG1 |= pll_mul;
}
@@ -461,8 +420,7 @@ void rcu_pll2_config(uint32_t pll_mul)
\param[out] none
\retval none
*/
void rcu_adc_clock_config(uint32_t adc_psc)
{
void rcu_adc_clock_config(uint32_t adc_psc) {
uint32_t reg0;
/* reset the ADCPSC bits */
@@ -470,7 +428,7 @@ void rcu_adc_clock_config(uint32_t adc_psc)
reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC);
/* set the ADC prescaler factor */
switch(adc_psc){
switch (adc_psc) {
case RCU_CKADC_CKAPB2_DIV2:
case RCU_CKADC_CKAPB2_DIV4:
case RCU_CKADC_CKAPB2_DIV6:
@@ -503,8 +461,7 @@ void rcu_adc_clock_config(uint32_t adc_psc)
\param[out] none
\retval none
*/
void rcu_usb_clock_config(uint32_t usb_psc)
{
void rcu_usb_clock_config(uint32_t usb_psc) {
uint32_t reg;
reg = RCU_CFG0;
@@ -525,8 +482,7 @@ void rcu_usb_clock_config(uint32_t usb_psc)
\param[out] none
\retval none
*/
void rcu_rtc_clock_config(uint32_t rtc_clock_source)
{
void rcu_rtc_clock_config(uint32_t rtc_clock_source) {
uint32_t reg;
reg = RCU_BDCTL;
@@ -544,8 +500,7 @@ void rcu_rtc_clock_config(uint32_t rtc_clock_source)
\param[out] none
\retval none
*/
void rcu_i2s1_clock_config(uint32_t i2s_clock_source)
{
void rcu_i2s1_clock_config(uint32_t i2s_clock_source) {
uint32_t reg;
reg = RCU_CFG1;
@@ -563,8 +518,7 @@ void rcu_i2s1_clock_config(uint32_t i2s_clock_source)
\param[out] none
\retval none
*/
void rcu_i2s2_clock_config(uint32_t i2s_clock_source)
{
void rcu_i2s2_clock_config(uint32_t i2s_clock_source) {
uint32_t reg;
reg = RCU_CFG1;
@@ -593,12 +547,11 @@ void rcu_i2s2_clock_config(uint32_t i2s_clock_source)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus rcu_flag_get(rcu_flag_enum flag)
{
FlagStatus rcu_flag_get(rcu_flag_enum flag) {
/* get the rcu flag */
if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
if (RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -609,10 +562,7 @@ FlagStatus rcu_flag_get(rcu_flag_enum flag)
\param[out] none
\retval none
*/
void rcu_all_reset_flag_clear(void)
{
RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
}
void rcu_all_reset_flag_clear(void) { RCU_RSTSCK |= RCU_RSTSCK_RSTFC; }
/*!
\brief get the clock stabilization interrupt and ckm flags
@@ -629,12 +579,11 @@ void rcu_all_reset_flag_clear(void)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
{
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) {
/* get the rcu interrupt flag */
if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
if (RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -654,10 +603,7 @@ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
\param[out] none
\retval none
*/
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
{
RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear));
}
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) { RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); }
/*!
\brief enable the stabilization interrupt
@@ -673,10 +619,7 @@ void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear)
\param[out] none
\retval none
*/
void rcu_interrupt_enable(rcu_int_enum stab_int)
{
RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int));
}
void rcu_interrupt_enable(rcu_int_enum stab_int) { RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); }
/*!
\brief disable the stabilization interrupt
@@ -692,10 +635,7 @@ void rcu_interrupt_enable(rcu_int_enum stab_int)
\param[out] none
\retval none
*/
void rcu_interrupt_disable(rcu_int_enum stab_int)
{
RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int));
}
void rcu_interrupt_disable(rcu_int_enum stab_int) { RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); }
/*!
\brief wait for oscillator stabilization flags is SET or oscillator startup is timeout
@@ -711,98 +651,97 @@ void rcu_interrupt_disable(rcu_int_enum stab_int)
\param[out] none
\retval ErrStatus: SUCCESS or ERROR
*/
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
{
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) {
uint32_t stb_cnt = 0U;
ErrStatus reval = ERROR;
FlagStatus osci_stat = RESET;
switch(osci){
switch (osci) {
/* wait HXTAL stable */
case RCU_HXTAL:
while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){
while ((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB);
stb_cnt++;
}
/* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){
if (RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) {
reval = SUCCESS;
}
break;
/* wait LXTAL stable */
case RCU_LXTAL:
while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){
while ((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB);
stb_cnt++;
}
/* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){
if (RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) {
reval = SUCCESS;
}
break;
/* wait IRC8M stable */
case RCU_IRC8M:
while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){
while ((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB);
stb_cnt++;
}
/* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){
if (RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) {
reval = SUCCESS;
}
break;
/* wait IRC40K stable */
case RCU_IRC40K:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB);
stb_cnt++;
}
/* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){
if (RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) {
reval = SUCCESS;
}
break;
/* wait PLL stable */
case RCU_PLL_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB);
stb_cnt++;
}
/* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){
if (RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) {
reval = SUCCESS;
}
break;
/* wait PLL1 stable */
case RCU_PLL1_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB);
stb_cnt++;
}
/* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){
if (RESET != rcu_flag_get(RCU_FLAG_PLL1STB)) {
reval = SUCCESS;
}
break;
/* wait PLL2 stable */
case RCU_PLL2_CK:
while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){
while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) {
osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB);
stb_cnt++;
}
/* check whether flag is set or not */
if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){
if (RESET != rcu_flag_get(RCU_FLAG_PLL2STB)) {
reval = SUCCESS;
}
break;
@@ -829,10 +768,7 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci)
\param[out] none
\retval none
*/
void rcu_osci_on(rcu_osci_type_enum osci)
{
RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci));
}
void rcu_osci_on(rcu_osci_type_enum osci) { RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); }
/*!
\brief turn off the oscillator
@@ -848,10 +784,7 @@ void rcu_osci_on(rcu_osci_type_enum osci)
\param[out] none
\retval none
*/
void rcu_osci_off(rcu_osci_type_enum osci)
{
RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci));
}
void rcu_osci_off(rcu_osci_type_enum osci) { RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); }
/*!
\brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it
@@ -862,11 +795,10 @@ void rcu_osci_off(rcu_osci_type_enum osci)
\param[out] none
\retval none
*/
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
{
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) {
uint32_t reg;
switch(osci){
switch (osci) {
/* enable HXTAL to bypass mode */
case RCU_HXTAL:
reg = RCU_CTL;
@@ -899,11 +831,10 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci)
\param[out] none
\retval none
*/
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
{
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) {
uint32_t reg;
switch(osci){
switch (osci) {
/* disable HXTAL to bypass mode */
case RCU_HXTAL:
reg = RCU_CTL;
@@ -934,10 +865,7 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
\retval none
*/
void rcu_hxtal_clock_monitor_enable(void)
{
RCU_CTL |= RCU_CTL_CKMEN;
}
void rcu_hxtal_clock_monitor_enable(void) { RCU_CTL |= RCU_CTL_CKMEN; }
/*!
\brief disable the HXTAL clock monitor
@@ -945,10 +873,7 @@ void rcu_hxtal_clock_monitor_enable(void)
\param[out] none
\retval none
*/
void rcu_hxtal_clock_monitor_disable(void)
{
RCU_CTL &= ~RCU_CTL_CKMEN;
}
void rcu_hxtal_clock_monitor_disable(void) { RCU_CTL &= ~RCU_CTL_CKMEN; }
/*!
\brief set the IRC8M adjust value
@@ -956,8 +881,7 @@ void rcu_hxtal_clock_monitor_disable(void)
\param[out] none
\retval none
*/
void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)
{
void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) {
uint32_t reg;
reg = RCU_CTL;
@@ -977,8 +901,7 @@ void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval)
\param[out] none
\retval none
*/
void rcu_deepsleep_voltage_set(uint32_t dsvol)
{
void rcu_deepsleep_voltage_set(uint32_t dsvol) {
dsvol &= RCU_DSV_DSLPVS;
RCU_DSV = dsvol;
}
@@ -994,11 +917,10 @@ void rcu_deepsleep_voltage_set(uint32_t dsvol)
\param[out] none
\retval clock frequency of system, AHB, APB1, APB2
*/
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
{
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) {
uint32_t sws, ck_freq = 0U;
uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq;
uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp;
uint32_t pllsel, predv0sel, pllmf, ck_src, idx, clk_exp;
uint32_t predv0, predv1, pll1mf;
/* exponent of AHB, APB1 and APB2 clock divider */
@@ -1007,7 +929,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4};
sws = GET_BITS(RCU_CFG0, 2, 3);
switch(sws){
switch (sws) {
/* IRC8M is selected as CK_SYS */
case SEL_IRC8M:
cksys_freq = IRC8M_VALUE;
@@ -1021,41 +943,41 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
/* PLL clock source selection, HXTAL or IRC8M/2 */
pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
if(RCU_PLLSRC_HXTAL == pllsel) {
if (RCU_PLLSRC_HXTAL == pllsel) {
/* PLL clock source is HXTAL */
ck_src = HXTAL_VALUE;
predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
/* source clock use PLL1 */
if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
if (RCU_PREDV0SRC_CKPLL1 == predv0sel) {
predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
if(17U == pll1mf){
if (17U == pll1mf) {
pll1mf = 20U;
}
ck_src = (ck_src / predv1) * pll1mf;
}
predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
ck_src /= predv0;
}else{
} else {
/* PLL clock source is IRC8M/2 */
ck_src = IRC8M_VALUE/2U;
ck_src = IRC8M_VALUE / 2U;
}
/* PLL multiplication factor */
pllmf = GET_BITS(RCU_CFG0, 18, 21);
if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) {
pllmf |= 0x10U;
}
if(pllmf < 15U){
if (pllmf < 15U) {
pllmf += 2U;
}else{
} else {
pllmf += 1U;
}
cksys_freq = ck_src * pllmf;
if(15U == pllmf){
if (15U == pllmf) {
/* PLL source clock multiply by 6.5 */
cksys_freq = ck_src * 6U + ck_src / 2U;
}
@@ -1083,7 +1005,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
apb2_freq = ahb_freq >> clk_exp;
/* return the clocks frequency */
switch(clock){
switch (clock) {
case CK_SYS:
ck_freq = cksys_freq;
break;

67
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rtc.c vendored
View File

@@ -47,10 +47,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void rtc_configuration_mode_enter(void)
{
RTC_CTL |= RTC_CTL_CMF;
}
void rtc_configuration_mode_enter(void) { RTC_CTL |= RTC_CTL_CMF; }
/*!
\brief exit RTC configuration mode
@@ -58,10 +55,7 @@ void rtc_configuration_mode_enter(void)
\param[out] none
\retval none
*/
void rtc_configuration_mode_exit(void)
{
RTC_CTL &= ~RTC_CTL_CMF;
}
void rtc_configuration_mode_exit(void) { RTC_CTL &= ~RTC_CTL_CMF; }
/*!
\brief set RTC counter value
@@ -69,8 +63,7 @@ void rtc_configuration_mode_exit(void)
\param[out] none
\retval none
*/
void rtc_counter_set(uint32_t cnt)
{
void rtc_counter_set(uint32_t cnt) {
rtc_configuration_mode_enter();
/* set the RTC counter high bits */
RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET);
@@ -85,8 +78,7 @@ void rtc_counter_set(uint32_t cnt)
\param[out] none
\retval none
*/
void rtc_prescaler_set(uint32_t psc)
{
void rtc_prescaler_set(uint32_t psc) {
rtc_configuration_mode_enter();
/* set the RTC prescaler high bits */
RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET);
@@ -101,11 +93,9 @@ void rtc_prescaler_set(uint32_t psc)
\param[out] none
\retval none
*/
void rtc_lwoff_wait(void)
{
void rtc_lwoff_wait(void) {
/* loop until LWOFF flag is set */
while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){
}
while (RESET == (RTC_CTL & RTC_CTL_LWOFF)) {}
}
/*!
@@ -114,13 +104,11 @@ void rtc_lwoff_wait(void)
\param[out] none
\retval none
*/
void rtc_register_sync_wait(void)
{
void rtc_register_sync_wait(void) {
/* clear RSYNF flag */
RTC_CTL &= ~RTC_CTL_RSYNF;
/* loop until RSYNF flag is set */
while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){
}
while (RESET == (RTC_CTL & RTC_CTL_RSYNF)) {}
}
/*!
@@ -129,8 +117,7 @@ void rtc_register_sync_wait(void)
\param[out] none
\retval none
*/
void rtc_alarm_config(uint32_t alarm)
{
void rtc_alarm_config(uint32_t alarm) {
rtc_configuration_mode_enter();
/* set the alarm high bits */
RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET);
@@ -145,8 +132,7 @@ void rtc_alarm_config(uint32_t alarm)
\param[out] none
\retval RTC counter value
*/
uint32_t rtc_counter_get(void)
{
uint32_t rtc_counter_get(void) {
uint32_t temp = 0x0U;
temp = RTC_CNTL;
@@ -160,8 +146,7 @@ uint32_t rtc_counter_get(void)
\param[out] none
\retval RTC divider value
*/
uint32_t rtc_divider_get(void)
{
uint32_t rtc_divider_get(void) {
uint32_t temp = 0x00U;
temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET);
@@ -181,11 +166,10 @@ uint32_t rtc_divider_get(void)
\param[out] none
\retval SET or RESET
*/
FlagStatus rtc_flag_get(uint32_t flag)
{
if(RESET != (RTC_CTL & flag)){
FlagStatus rtc_flag_get(uint32_t flag) {
if (RESET != (RTC_CTL & flag)) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -201,8 +185,7 @@ FlagStatus rtc_flag_get(uint32_t flag)
\param[out] none
\retval none
*/
void rtc_flag_clear(uint32_t flag)
{
void rtc_flag_clear(uint32_t flag) {
/* clear RTC flag */
RTC_CTL &= ~flag;
}
@@ -217,11 +200,10 @@ void rtc_flag_clear(uint32_t flag)
\param[out] none
\retval SET or RESET
*/
FlagStatus rtc_interrupt_flag_get(uint32_t flag)
{
if(RESET != (RTC_CTL & flag)){
FlagStatus rtc_interrupt_flag_get(uint32_t flag) {
if (RESET != (RTC_CTL & flag)) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -236,8 +218,7 @@ FlagStatus rtc_interrupt_flag_get(uint32_t flag)
\param[out] none
\retval none
*/
void rtc_interrupt_flag_clear(uint32_t flag)
{
void rtc_interrupt_flag_clear(uint32_t flag) {
/* clear RTC interrupt flag */
RTC_CTL &= ~flag;
}
@@ -252,10 +233,7 @@ void rtc_interrupt_flag_clear(uint32_t flag)
\param[out] none
\retval none
*/
void rtc_interrupt_enable(uint32_t interrupt)
{
RTC_INTEN |= interrupt;
}
void rtc_interrupt_enable(uint32_t interrupt) { RTC_INTEN |= interrupt; }
/*!
\brief disable RTC interrupt
@@ -267,7 +245,4 @@ void rtc_interrupt_enable(uint32_t interrupt)
\param[out] none
\retval none
*/
void rtc_interrupt_disable(uint32_t interrupt)
{
RTC_INTEN &= ~interrupt;
}
void rtc_interrupt_disable(uint32_t interrupt) { RTC_INTEN &= ~interrupt; }

203
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_spi.c vendored
View File

@@ -55,9 +55,8 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void spi_i2s_deinit(uint32_t spi_periph)
{
switch(spi_periph){
void spi_i2s_deinit(uint32_t spi_periph) {
switch (spi_periph) {
case SPI0:
/* reset SPI0 */
rcu_periph_reset_enable(RCU_SPI0RST);
@@ -73,7 +72,7 @@ void spi_i2s_deinit(uint32_t spi_periph)
rcu_periph_reset_enable(RCU_SPI2RST);
rcu_periph_reset_disable(RCU_SPI2RST);
break;
default :
default:
break;
}
}
@@ -84,8 +83,7 @@ void spi_i2s_deinit(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_struct_para_init(spi_parameter_struct* spi_struct)
{
void spi_struct_para_init(spi_parameter_struct *spi_struct) {
/* set the SPI struct with the default values */
spi_struct->device_mode = SPI_SLAVE;
spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX;
@@ -112,8 +110,7 @@ void spi_struct_para_init(spi_parameter_struct* spi_struct)
\param[out] none
\retval none
*/
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
{
void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) {
uint32_t reg = 0U;
reg = SPI_CTL0(spi_periph);
reg &= SPI_INIT_MASK;
@@ -145,10 +142,7 @@ void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
\param[out] none
\retval none
*/
void spi_enable(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
}
void spi_enable(uint32_t spi_periph) { SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; }
/*!
\brief disable SPI
@@ -156,10 +150,7 @@ void spi_enable(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_disable(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
}
void spi_disable(uint32_t spi_periph) { SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); }
/*!
\brief initialize I2S parameter
@@ -184,8 +175,7 @@ void spi_disable(uint32_t spi_periph)
\param[out] none
\retval none
*/
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
{
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) {
uint32_t reg = 0U;
reg = SPI_I2SCTL(spi_periph);
reg &= I2S_INIT_MASK;
@@ -230,8 +220,7 @@ void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ck
\param[out] none
\retval none
*/
void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
{
void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) {
uint32_t i2sdiv = 2U, i2sof = 0U;
uint32_t clks = 0U;
uint32_t i2sclock = 0U;
@@ -240,23 +229,23 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE;
/* get the I2S clock source */
if(SPI1 == ((uint32_t)spi_periph)){
if (SPI1 == ((uint32_t)spi_periph)) {
/* I2S1 clock source selection */
clks = I2S1_CLOCK_SEL;
}else{
} else {
/* I2S2 clock source selection */
clks = I2S2_CLOCK_SEL;
}
if(0U != (RCU_CFG1 & clks)){
if (0U != (RCU_CFG1 & clks)) {
/* get RCU PLL2 clock multiplication factor */
clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET);
if((clks > 5U) && (clks < 15U)){
if ((clks > 5U) && (clks < 15U)) {
/* multiplier is between 8 and 16 */
clks += 2U;
}else{
if(15U == clks){
} else {
if (15U == clks) {
/* multiplier is 20 */
clks = 20U;
}
@@ -266,19 +255,19 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U);
/* calculate I2S clock based on PLL2 and PREDV1 */
i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U);
}else{
} else {
/* get system clock */
i2sclock = rcu_clock_freq_get(CK_SYS);
}
/* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
if(I2S_MCKOUT_ENABLE == mckout){
if (I2S_MCKOUT_ENABLE == mckout) {
clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
}else{
if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){
clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample);
}else{
clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample);
} else {
if (I2S_FRAMEFORMAT_DT16B_CH16B == frameformat) {
clks = (uint32_t)(((i2sclock / 32U) * 10U) / audiosample);
} else {
clks = (uint32_t)(((i2sclock / 64U) * 10U) / audiosample);
}
}
@@ -289,7 +278,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
i2sof = (i2sof << 8U);
/* set the default values */
if((i2sdiv < 2U) || (i2sdiv > 255U)){
if ((i2sdiv < 2U) || (i2sdiv > 255U)) {
i2sdiv = 2U;
i2sof = 0U;
}
@@ -308,10 +297,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor
\param[out] none
\retval none
*/
void i2s_enable(uint32_t spi_periph)
{
SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
}
void i2s_enable(uint32_t spi_periph) { SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; }
/*!
\brief disable I2S
@@ -319,10 +305,7 @@ void i2s_enable(uint32_t spi_periph)
\param[out] none
\retval none
*/
void i2s_disable(uint32_t spi_periph)
{
SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
}
void i2s_disable(uint32_t spi_periph) { SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); }
/*!
\brief enable SPI NSS output
@@ -330,10 +313,7 @@ void i2s_disable(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_nss_output_enable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
}
void spi_nss_output_enable(uint32_t spi_periph) { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; }
/*!
\brief disable SPI NSS output
@@ -341,10 +321,7 @@ void spi_nss_output_enable(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_nss_output_disable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
}
void spi_nss_output_disable(uint32_t spi_periph) { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); }
/*!
\brief SPI NSS pin high level in software mode
@@ -352,10 +329,7 @@ void spi_nss_output_disable(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_nss_internal_high(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
}
void spi_nss_internal_high(uint32_t spi_periph) { SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; }
/*!
\brief SPI NSS pin low level in software mode
@@ -363,10 +337,7 @@ void spi_nss_internal_high(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_nss_internal_low(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
}
void spi_nss_internal_low(uint32_t spi_periph) { SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); }
/*!
\brief enable SPI DMA send or receive
@@ -378,11 +349,10 @@ void spi_nss_internal_low(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
{
if(SPI_DMA_TRANSMIT == dma){
void spi_dma_enable(uint32_t spi_periph, uint8_t dma) {
if (SPI_DMA_TRANSMIT == dma) {
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
}else{
} else {
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
}
}
@@ -397,11 +367,10 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
\param[out] none
\retval none
*/
void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
{
if(SPI_DMA_TRANSMIT == dma){
void spi_dma_disable(uint32_t spi_periph, uint8_t dma) {
if (SPI_DMA_TRANSMIT == dma) {
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
}else{
} else {
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
}
}
@@ -416,8 +385,7 @@ void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
\param[out] none
\retval none
*/
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
{
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) {
/* clear SPI_CTL0_FF16 bit */
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
/* configure SPI_CTL0_FF16 bit */
@@ -431,10 +399,7 @@ void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format
\param[out] none
\retval none
*/
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
{
SPI_DATA(spi_periph) = (uint32_t)data;
}
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) { SPI_DATA(spi_periph) = (uint32_t)data; }
/*!
\brief SPI receive data
@@ -442,10 +407,7 @@ void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
\param[out] none
\retval 16-bit data
*/
uint16_t spi_i2s_data_receive(uint32_t spi_periph)
{
return ((uint16_t)SPI_DATA(spi_periph));
}
uint16_t spi_i2s_data_receive(uint32_t spi_periph) { return ((uint16_t)SPI_DATA(spi_periph)); }
/*!
\brief configure SPI bidirectional transfer direction
@@ -457,12 +419,11 @@ uint16_t spi_i2s_data_receive(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
{
if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) {
if (SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) {
/* set the transmit-only mode */
SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
}else{
} else {
/* set the receive-only mode */
SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
}
@@ -475,8 +436,7 @@ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_di
\param[out] none
\retval none
*/
void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly)
{
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) {
/* enable SPI CRC */
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
@@ -490,10 +450,7 @@ void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly)
\param[out] none
\retval 16-bit CRC polynomial
*/
uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
{
return ((uint16_t)SPI_CRCPOLY(spi_periph));
}
uint16_t spi_crc_polynomial_get(uint32_t spi_periph) { return ((uint16_t)SPI_CRCPOLY(spi_periph)); }
/*!
\brief turn on CRC function
@@ -501,10 +458,7 @@ uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_crc_on(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
}
void spi_crc_on(uint32_t spi_periph) { SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; }
/*!
\brief turn off CRC function
@@ -512,10 +466,7 @@ void spi_crc_on(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_crc_off(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
}
void spi_crc_off(uint32_t spi_periph) { SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); }
/*!
\brief SPI next data is CRC value
@@ -523,10 +474,7 @@ void spi_crc_off(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_crc_next(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
}
void spi_crc_next(uint32_t spi_periph) { SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; }
/*!
\brief get SPI CRC send value or receive value
@@ -538,11 +486,10 @@ void spi_crc_next(uint32_t spi_periph)
\param[out] none
\retval 16-bit CRC value
*/
uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc)
{
if(SPI_CRC_TX == crc){
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) {
if (SPI_CRC_TX == crc) {
return ((uint16_t)(SPI_TCRC(spi_periph)));
}else{
} else {
return ((uint16_t)(SPI_RCRC(spi_periph)));
}
}
@@ -553,10 +500,7 @@ uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc)
\param[out] none
\retval none
*/
void spi_ti_mode_enable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
}
void spi_ti_mode_enable(uint32_t spi_periph) { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; }
/*!
\brief disable SPI TI mode
@@ -564,10 +508,7 @@ void spi_ti_mode_enable(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_ti_mode_disable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
}
void spi_ti_mode_disable(uint32_t spi_periph) { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); }
/*!
\brief enable SPI NSS pulse mode
@@ -575,10 +516,7 @@ void spi_ti_mode_disable(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_nssp_mode_enable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP;
}
void spi_nssp_mode_enable(uint32_t spi_periph) { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; }
/*!
\brief disable SPI NSS pulse mode
@@ -586,11 +524,7 @@ void spi_nssp_mode_enable(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_nssp_mode_disable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP);
}
void spi_nssp_mode_disable(uint32_t spi_periph) { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); }
/*!
\brief enable SPI and I2S interrupt
@@ -604,9 +538,8 @@ void spi_nssp_mode_disable(uint32_t spi_periph)
\param[out] none
\retval none
*/
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
{
switch(interrupt){
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) {
switch (interrupt) {
/* SPI/I2S transmit buffer empty interrupt */
case SPI_I2S_INT_TBE:
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
@@ -636,9 +569,8 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
\param[out] none
\retval none
*/
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
{
switch(interrupt){
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) {
switch (interrupt) {
/* SPI/I2S transmit buffer empty interrupt */
case SPI_I2S_INT_TBE:
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
@@ -671,12 +603,11 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
{
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) {
uint32_t reg1 = SPI_STAT(spi_periph);
uint32_t reg2 = SPI_CTL1(spi_periph);
switch(interrupt){
switch (interrupt) {
/* SPI/I2S transmit buffer empty interrupt */
case SPI_I2S_INT_FLAG_TBE:
reg1 = reg1 & SPI_STAT_TBE;
@@ -716,9 +647,9 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
break;
}
/* get SPI/I2S interrupt flag status */
if((0U != reg1) && (0U != reg2)){
if ((0U != reg1) && (0U != reg2)) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -745,11 +676,10 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
{
if(RESET != (SPI_STAT(spi_periph) & flag)){
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) {
if (RESET != (SPI_STAT(spi_periph) & flag)) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -760,7 +690,4 @@ FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
\param[out] none
\retval none
*/
void spi_crc_error_clear(uint32_t spi_periph)
{
SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
}
void spi_crc_error_clear(uint32_t spi_periph) { SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); }

379
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_timer.c vendored
View File

@@ -44,9 +44,8 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void timer_deinit(uint32_t timer_periph)
{
switch(timer_periph){
void timer_deinit(uint32_t timer_periph) {
switch (timer_periph) {
case TIMER0:
/* reset TIMER0 */
rcu_periph_reset_enable(RCU_TIMER0RST);
@@ -94,8 +93,7 @@ void timer_deinit(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_struct_para_init(timer_parameter_struct* initpara)
{
void timer_struct_para_init(timer_parameter_struct *initpara) {
/* initialize the init parameter struct member with the default value */
initpara->prescaler = 0U;
initpara->alignedmode = TIMER_COUNTER_EDGE;
@@ -119,26 +117,24 @@ void timer_struct_para_init(timer_parameter_struct* initpara)
\param[out] none
\retval none
*/
void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
{
void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) {
/* configure the counter prescaler value */
TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
/* configure the counter direction and aligned mode */
if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)
|| (TIMER3 == timer_periph) || (TIMER4 == timer_periph) ){
if ((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) || (TIMER4 == timer_periph)) {
TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM));
TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK);
TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK);
}else{
TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR);
} else {
TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_DIR);
TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK);
}
/* configure the autoreload value */
TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){
if ((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) {
/* reset the CKDIV bit */
TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV);
TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK);
@@ -159,10 +155,7 @@ void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
\param[out] none
\retval none
*/
void timer_enable(uint32_t timer_periph)
{
TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
}
void timer_enable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; }
/*!
\brief disable a timer
@@ -170,10 +163,7 @@ void timer_enable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_disable(uint32_t timer_periph)
{
TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
}
void timer_disable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; }
/*!
\brief enable the auto reload shadow function
@@ -181,10 +171,7 @@ void timer_disable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_auto_reload_shadow_enable(uint32_t timer_periph)
{
TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
}
void timer_auto_reload_shadow_enable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; }
/*!
\brief disable the auto reload shadow function
@@ -192,10 +179,7 @@ void timer_auto_reload_shadow_enable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_auto_reload_shadow_disable(uint32_t timer_periph)
{
TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
}
void timer_auto_reload_shadow_disable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; }
/*!
\brief enable the update event
@@ -203,10 +187,7 @@ void timer_auto_reload_shadow_disable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_update_event_enable(uint32_t timer_periph)
{
TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
}
void timer_update_event_enable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; }
/*!
\brief disable the update event
@@ -214,10 +195,7 @@ void timer_update_event_enable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_update_event_disable(uint32_t timer_periph)
{
TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
}
void timer_update_event_disable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPDIS; }
/*!
\brief set TIMER counter alignment mode
@@ -231,8 +209,7 @@ void timer_update_event_disable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
{
void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) {
TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM);
TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
}
@@ -243,10 +220,7 @@ void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
\param[out] none
\retval none
*/
void timer_counter_up_direction(uint32_t timer_periph)
{
TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
}
void timer_counter_up_direction(uint32_t timer_periph) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; }
/*!
\brief set TIMER counter down direction
@@ -254,10 +228,7 @@ void timer_counter_up_direction(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_counter_down_direction(uint32_t timer_periph)
{
TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
}
void timer_counter_down_direction(uint32_t timer_periph) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; }
/*!
\brief configure TIMER prescaler
@@ -270,11 +241,10 @@ void timer_counter_down_direction(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload)
{
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) {
TIMER_PSC(timer_periph) = (uint32_t)prescaler;
if(TIMER_PSC_RELOAD_NOW == pscreload){
if (TIMER_PSC_RELOAD_NOW == pscreload) {
TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
}
}
@@ -286,10 +256,7 @@ void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t
\param[out] none
\retval none
*/
void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
{
TIMER_CREP(timer_periph) = (uint32_t)repetition;
}
void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) { TIMER_CREP(timer_periph) = (uint32_t)repetition; }
/*!
\brief configure TIMER autoreload register value
@@ -298,10 +265,7 @@ void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
\param[out] none
\retval none
*/
void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload)
{
TIMER_CAR(timer_periph) = (uint32_t)autoreload;
}
void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload) { TIMER_CAR(timer_periph) = (uint32_t)autoreload; }
/*!
\brief configure TIMER counter register value
@@ -310,10 +274,7 @@ void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload)
\param[out] none
\retval none
*/
void timer_counter_value_config(uint32_t timer_periph, uint16_t counter)
{
TIMER_CNT(timer_periph) = (uint32_t)counter;
}
void timer_counter_value_config(uint32_t timer_periph, uint16_t counter) { TIMER_CNT(timer_periph) = (uint32_t)counter; }
/*!
\brief read TIMER counter value
@@ -321,8 +282,7 @@ void timer_counter_value_config(uint32_t timer_periph, uint16_t counter)
\param[out] none
\retval counter value
*/
uint32_t timer_counter_read(uint32_t timer_periph)
{
uint32_t timer_counter_read(uint32_t timer_periph) {
uint32_t count_value = 0U;
count_value = TIMER_CNT(timer_periph);
return (count_value);
@@ -334,10 +294,9 @@ uint32_t timer_counter_read(uint32_t timer_periph)
\param[out] none
\retval prescaler register value
*/
uint16_t timer_prescaler_read(uint32_t timer_periph)
{
uint16_t timer_prescaler_read(uint32_t timer_periph) {
uint16_t prescaler_value = 0U;
prescaler_value = (uint16_t) (TIMER_PSC(timer_periph));
prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
return (prescaler_value);
}
@@ -351,13 +310,12 @@ uint16_t timer_prescaler_read(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
{
if(TIMER_SP_MODE_SINGLE == spmode){
void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) {
if (TIMER_SP_MODE_SINGLE == spmode) {
TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
}else if(TIMER_SP_MODE_REPETITIVE == spmode){
} else if (TIMER_SP_MODE_REPETITIVE == spmode) {
TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
}else{
} else {
/* illegal parameters */
}
}
@@ -373,13 +331,12 @@ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
\param[out] none
\retval none
*/
void timer_update_source_config(uint32_t timer_periph, uint32_t update)
{
if(TIMER_UPDATE_SRC_REGULAR == update){
void timer_update_source_config(uint32_t timer_periph, uint32_t update) {
if (TIMER_UPDATE_SRC_REGULAR == update) {
TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
}else if(TIMER_UPDATE_SRC_GLOBAL == update){
} else if (TIMER_UPDATE_SRC_GLOBAL == update) {
TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
}else{
} else {
/* illegal parameters */
}
}
@@ -399,10 +356,7 @@ void timer_update_source_config(uint32_t timer_periph, uint32_t update)
\param[out] none
\retval none
*/
void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
{
TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
}
void timer_dma_enable(uint32_t timer_periph, uint16_t dma) { TIMER_DMAINTEN(timer_periph) |= (uint32_t)dma; }
/*!
\brief disable the TIMER DMA
@@ -419,10 +373,7 @@ void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
\param[out] none
\retval none
*/
void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
{
TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
}
void timer_dma_disable(uint32_t timer_periph, uint16_t dma) { TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); }
/*!
\brief channel DMA request source selection
@@ -434,13 +385,12 @@ void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
\param[out] none
\retval none
*/
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request)
{
if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) {
if (TIMER_DMAREQUEST_UPDATEEVENT == dma_request) {
TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
}else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
} else if (TIMER_DMAREQUEST_CHANNELEVENT == dma_request) {
TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
}else{
} else {
/* illegal parameters */
}
}
@@ -475,8 +425,7 @@ void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma
\param[out] none
\retval none
*/
void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
{
void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) {
TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
}
@@ -497,10 +446,7 @@ void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uin
\param[out] none
\retval none
*/
void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
{
TIMER_SWEVG(timer_periph) |= (uint32_t)event;
}
void timer_event_software_generate(uint32_t timer_periph, uint16_t event) { TIMER_SWEVG(timer_periph) |= (uint32_t)event; }
/*!
\brief initialize TIMER break parameter struct with a default value
@@ -508,8 +454,7 @@ void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
\param[out] none
\retval none
*/
void timer_break_struct_para_init(timer_break_parameter_struct* breakpara)
{
void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) {
/* initialize the break parameter struct member with the default value */
breakpara->runoffstate = TIMER_ROS_STATE_DISABLE;
breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE;
@@ -534,15 +479,9 @@ void timer_break_struct_para_init(timer_break_parameter_struct* breakpara)
\param[out] none
\retval none
*/
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
{
TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
((uint32_t)(breakpara->ideloffstate))|
((uint32_t)(breakpara->deadtime)) |
((uint32_t)(breakpara->breakpolarity)) |
((uint32_t)(breakpara->outputautostate)) |
((uint32_t)(breakpara->protectmode)) |
((uint32_t)(breakpara->breakstate)));
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) {
TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | ((uint32_t)(breakpara->ideloffstate)) | ((uint32_t)(breakpara->deadtime)) | ((uint32_t)(breakpara->breakpolarity))
| ((uint32_t)(breakpara->outputautostate)) | ((uint32_t)(breakpara->protectmode)) | ((uint32_t)(breakpara->breakstate)));
}
/*!
@@ -551,10 +490,7 @@ void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* bre
\param[out] none
\retval none
*/
void timer_break_enable(uint32_t timer_periph)
{
TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
}
void timer_break_enable(uint32_t timer_periph) { TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; }
/*!
\brief disable TIMER break function
@@ -562,10 +498,7 @@ void timer_break_enable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_break_disable(uint32_t timer_periph)
{
TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
}
void timer_break_disable(uint32_t timer_periph) { TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; }
/*!
\brief enable TIMER output automatic function
@@ -573,10 +506,7 @@ void timer_break_disable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_automatic_output_enable(uint32_t timer_periph)
{
TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
}
void timer_automatic_output_enable(uint32_t timer_periph) { TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; }
/*!
\brief disable TIMER output automatic function
@@ -584,10 +514,7 @@ void timer_automatic_output_enable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_automatic_output_disable(uint32_t timer_periph)
{
TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
}
void timer_automatic_output_disable(uint32_t timer_periph) { TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; }
/*!
\brief enable or disable TIMER primary output function
@@ -596,11 +523,10 @@ void timer_automatic_output_disable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
{
if(ENABLE == newvalue){
void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) {
if (ENABLE == newvalue) {
TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
}else{
} else {
TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
}
}
@@ -612,11 +538,10 @@ void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
\param[out] none
\retval none
*/
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
{
if(ENABLE == newvalue){
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) {
if (ENABLE == newvalue) {
TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
}else{
} else {
TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
}
}
@@ -631,13 +556,12 @@ void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus ne
\param[out] none
\retval none
*/
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl)
{
if(TIMER_UPDATECTL_CCU == ccuctl){
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) {
if (TIMER_UPDATECTL_CCU == ccuctl) {
TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
}else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
} else if (TIMER_UPDATECTL_CCUTRI == ccuctl) {
TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
}else{
} else {
/* illegal parameters */
}
}
@@ -648,8 +572,7 @@ void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t
\param[out] none
\retval none
*/
void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara)
{
void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) {
/* initialize the channel output parameter struct member with the default value */
ocpara->outputstate = TIMER_CCX_DISABLE;
ocpara->outputnstate = TIMER_CCXN_DISABLE;
@@ -678,9 +601,8 @@ void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara)
\param[out] none
\retval none
*/
void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
{
switch(channel){
void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
/* reset the CH0EN bit */
@@ -777,7 +699,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_
/* configure TIMER_CH_3 */
case TIMER_CH_3:
/* reset the CH3EN bit */
TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
/* set the CH3EN bit */
TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U);
/* reset the CH3P bit */
@@ -820,9 +742,8 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_
\param[out] none
\retval none
*/
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
{
switch(channel){
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
@@ -861,9 +782,8 @@ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, u
\param[out] none
\retval none
*/
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
{
switch(channel){
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
@@ -901,9 +821,8 @@ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t cha
\param[out] none
\retval none
*/
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
{
switch(channel){
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
@@ -945,9 +864,8 @@ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel,
\param[out] none
\retval none
*/
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
{
switch(channel){
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
@@ -989,9 +907,8 @@ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, u
\param[out] none
\retval none
*/
void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
{
switch(channel){
void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
@@ -1033,9 +950,8 @@ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel,
\param[out] none
\retval none
*/
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
{
switch(channel){
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
@@ -1076,9 +992,8 @@ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channe
\param[out] none
\retval none
*/
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
{
switch(channel){
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
@@ -1115,9 +1030,8 @@ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, u
\param[out] none
\retval none
*/
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
{
switch(channel){
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
@@ -1158,9 +1072,8 @@ void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel,
\param[out] none
\retval none
*/
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
{
switch(channel){
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
@@ -1187,8 +1100,7 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint
\param[out] none
\retval none
*/
void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara)
{
void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) {
/* initialize the channel input parameter struct member with the default value */
icpara->icpolarity = TIMER_IC_POLARITY_RISING;
icpara->icselection = TIMER_IC_SELECTION_DIRECTTI;
@@ -1216,9 +1128,8 @@ void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara)
\param[out] none
\retval none
*/
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara)
{
switch(channel){
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
/* reset the CH0EN bit */
@@ -1321,9 +1232,8 @@ void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_i
\param[out] none
\retval none
*/
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
{
switch(channel){
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) {
switch (channel) {
/* configure TIMER_CH_0 */
case TIMER_CH_0:
TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
@@ -1361,11 +1271,10 @@ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_
\param[out] none
\retval channel capture compare register value
*/
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
{
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) {
uint32_t count_value = 0U;
switch(channel){
switch (channel) {
case TIMER_CH_0:
/* read TIMER channel 0 capture compare register value */
count_value = TIMER_CH0CV(timer_periph);
@@ -1404,25 +1313,24 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16
\param[out] none
\retval none
*/
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
{
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) {
uint16_t icpolarity = 0x0U;
uint16_t icselection = 0x0U;
/* Set channel input polarity */
if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
if (TIMER_IC_POLARITY_RISING == icpwm->icpolarity) {
icpolarity = TIMER_IC_POLARITY_FALLING;
}else{
} else {
icpolarity = TIMER_IC_POLARITY_RISING;
}
/* Set channel input mode selection */
if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
if (TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) {
icselection = TIMER_IC_SELECTION_INDIRECTTI;
}else{
} else {
icselection = TIMER_IC_SELECTION_DIRECTTI;
}
if(TIMER_CH_0 == channel){
if (TIMER_CH_0 == channel) {
/* reset the CH0EN bit */
TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
/* reset the CH0P and CH0NP bits */
@@ -1447,7 +1355,7 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim
/* reset the CH1P and CH1NP bits */
TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
/* set the CH1P and CH1NP bits */
TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U);
TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U);
/* reset the CH1MS bit */
TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
/* set the CH1MS bit */
@@ -1460,7 +1368,7 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim
TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
/* configure TIMER channel input capture prescaler value */
timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
}else{
} else {
/* reset the CH1EN bit */
TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
/* reset the CH1P and CH1NP bits */
@@ -1511,13 +1419,12 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim
\param[out] none
\retval none
*/
void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)
{
if(TIMER_HALLINTERFACE_ENABLE == hallmode){
void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) {
if (TIMER_HALLINTERFACE_ENABLE == hallmode) {
TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
}else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
} else if (TIMER_HALLINTERFACE_DISABLE == hallmode) {
TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
}else{
} else {
/* illegal parameters */
}
}
@@ -1538,8 +1445,7 @@ void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)
\param[out] none
\retval none
*/
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
{
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) {
TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
}
@@ -1560,8 +1466,7 @@ void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger
\param[out] none
\retval none
*/
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
{
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) {
TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
}
@@ -1583,8 +1488,7 @@ void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t o
\retval none
*/
void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
{
void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) {
TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
}
@@ -1599,13 +1503,12 @@ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
\param[out] none
\retval none
*/
void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
{
if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) {
if (TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) {
TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
}else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
} else if (TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) {
TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
}else{
} else {
/* illegal parameters */
}
}
@@ -1627,8 +1530,7 @@ void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
\param[out] none
\retval none
*/
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
{
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) {
TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity);
TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
@@ -1653,8 +1555,7 @@ void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler,
\param[out] none
\retval none
*/
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
{
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity) {
/* configure the quadrature decoder mode */
TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
@@ -1673,10 +1574,7 @@ void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomo
\param[out] none
\retval none
*/
void timer_internal_clock_config(uint32_t timer_periph)
{
TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
}
void timer_internal_clock_config(uint32_t timer_periph) { TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; }
/*!
\brief configure TIMER the internal trigger as external clock input
@@ -1690,8 +1588,7 @@ void timer_internal_clock_config(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
{
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) {
timer_input_trigger_source_select(timer_periph, intrigger);
TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
@@ -1713,9 +1610,8 @@ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint
\param[out] none
\retval none
*/
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter)
{
if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) {
if (TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) {
/* reset the CH1EN bit */
TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
/* reset the CH1NP bit */
@@ -1732,7 +1628,7 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint
TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U);
/* set the CH1EN bit */
TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
}else{
} else {
/* reset the CH0EN bit */
TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
/* reset the CH0P and CH0NP bits */
@@ -1775,8 +1671,7 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint
\param[out] none
\retval none
*/
void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
{
void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) {
/* configure TIMER external trigger input */
timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
/* reset the SMC bit,TRGS bit */
@@ -1802,8 +1697,7 @@ void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extpresca
\param[out] none
\retval none
*/
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
{
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) {
/* configure TIMER external trigger input */
timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
@@ -1815,10 +1709,7 @@ void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extpresca
\param[out] none
\retval none
*/
void timer_external_clock_mode1_disable(uint32_t timer_periph)
{
TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
}
void timer_external_clock_mode1_disable(uint32_t timer_periph) { TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; }
/*!
\brief enable the TIMER interrupt
@@ -1836,10 +1727,7 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph)
\param[out] none
\retval none
*/
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
{
TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
}
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) { TIMER_DMAINTEN(timer_periph) |= (uint32_t)interrupt; }
/*!
\brief disable the TIMER interrupt
@@ -1857,10 +1745,7 @@ void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
\param[out] none
\retval none
*/
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
{
TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
}
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) { TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); }
/*!
\brief get timer interrupt flag
@@ -1878,13 +1763,12 @@ void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
{
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) {
uint32_t val;
val = (TIMER_DMAINTEN(timer_periph) & interrupt);
if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)){
if ((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -1905,10 +1789,7 @@ FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
\param[out] none
\retval none
*/
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
{
TIMER_INTF(timer_periph) = (~(uint32_t)interrupt);
}
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) { TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); }
/*!
\brief get TIMER flags
@@ -1930,11 +1811,10 @@ void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
{
if(RESET != (TIMER_INTF(timer_periph) & flag)){
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) {
if (RESET != (TIMER_INTF(timer_periph) & flag)) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -1959,9 +1839,4 @@ FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
\param[out] none
\retval none
*/
void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
{
TIMER_INTF(timer_periph) = (~(uint32_t)flag);
}
void timer_flag_clear(uint32_t timer_periph, uint32_t flag) { TIMER_INTF(timer_periph) = (~(uint32_t)flag); }

222
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_usart.c vendored
View File

@@ -40,9 +40,8 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void usart_deinit(uint32_t usart_periph)
{
switch(usart_periph){
void usart_deinit(uint32_t usart_periph) {
switch (usart_periph) {
case USART0:
/* reset USART0 */
rcu_periph_reset_enable(RCU_USART0RST);
@@ -80,36 +79,35 @@ void usart_deinit(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
{
uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U;
switch(usart_periph){
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) {
uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U;
switch (usart_periph) {
/* get clock frequency */
case USART0:
/* get USART0 clock */
uclk=rcu_clock_freq_get(CK_APB2);
uclk = rcu_clock_freq_get(CK_APB2);
break;
case USART1:
/* get USART1 clock */
uclk=rcu_clock_freq_get(CK_APB1);
uclk = rcu_clock_freq_get(CK_APB1);
break;
case USART2:
/* get USART2 clock */
uclk=rcu_clock_freq_get(CK_APB1);
uclk = rcu_clock_freq_get(CK_APB1);
break;
case UART3:
/* get UART3 clock */
uclk=rcu_clock_freq_get(CK_APB1);
uclk = rcu_clock_freq_get(CK_APB1);
break;
case UART4:
/* get UART4 clock */
uclk=rcu_clock_freq_get(CK_APB1);
uclk = rcu_clock_freq_get(CK_APB1);
break;
default:
break;
}
/* oversampling by 16, configure the value of USART_BAUD */
udiv = (uclk+baudval/2U)/baudval;
udiv = (uclk + baudval / 2U) / baudval;
intdiv = udiv & (0x0000fff0U);
fradiv = udiv & (0x0000000fU);
USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv));
@@ -126,12 +124,11 @@ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval)
\param[out] none
\retval none
*/
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
{
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) {
/* clear USART_CTL0 PM,PCEN bits */
USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN);
/* configure USART parity mode */
USART_CTL0(usart_periph) |= paritycfg ;
USART_CTL0(usart_periph) |= paritycfg;
}
/*!
@@ -144,8 +141,7 @@ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg)
\param[out] none
\retval none
*/
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
{
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) {
/* clear USART_CTL0 WL bit */
USART_CTL0(usart_periph) &= ~USART_CTL0_WL;
/* configure USART word length */
@@ -164,8 +160,7 @@ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen)
\param[out] none
\retval none
*/
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
{
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) {
/* clear USART_CTL1 STB bits */
USART_CTL1(usart_periph) &= ~USART_CTL1_STB;
/* configure USART stop bits */
@@ -178,10 +173,7 @@ void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen)
\param[out] none
\retval none
*/
void usart_enable(uint32_t usart_periph)
{
USART_CTL0(usart_periph) |= USART_CTL0_UEN;
}
void usart_enable(uint32_t usart_periph) { USART_CTL0(usart_periph) |= USART_CTL0_UEN; }
/*!
\brief disable USART
@@ -189,10 +181,7 @@ void usart_enable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_disable(uint32_t usart_periph)
{
USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN);
}
void usart_disable(uint32_t usart_periph) { USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); }
/*!
\brief configure USART transmitter
@@ -204,8 +193,7 @@ void usart_disable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
{
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) {
uint32_t ctl = 0U;
ctl = USART_CTL0(usart_periph);
@@ -225,8 +213,7 @@ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig)
\param[out] none
\retval none
*/
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
{
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) {
uint32_t ctl = 0U;
ctl = USART_CTL0(usart_periph);
@@ -243,10 +230,7 @@ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig)
\param[out] none
\retval none
*/
void usart_data_transmit(uint32_t usart_periph, uint32_t data)
{
USART_DATA(usart_periph) = USART_DATA_DATA & data;
}
void usart_data_transmit(uint32_t usart_periph, uint32_t data) { USART_DATA(usart_periph) = USART_DATA_DATA & data; }
/*!
\brief USART receive data function
@@ -254,10 +238,7 @@ void usart_data_transmit(uint32_t usart_periph, uint32_t data)
\param[out] none
\retval data of received
*/
uint16_t usart_data_receive(uint32_t usart_periph)
{
return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U));
}
uint16_t usart_data_receive(uint32_t usart_periph) { return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); }
/*!
\brief configure the address of the USART in wake up by address match mode
@@ -266,8 +247,7 @@ uint16_t usart_data_receive(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_address_config(uint32_t usart_periph, uint8_t addr)
{
void usart_address_config(uint32_t usart_periph, uint8_t addr) {
USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr);
}
@@ -278,10 +258,7 @@ void usart_address_config(uint32_t usart_periph, uint8_t addr)
\param[out] none
\retval none
*/
void usart_mute_mode_enable(uint32_t usart_periph)
{
USART_CTL0(usart_periph) |= USART_CTL0_RWU;
}
void usart_mute_mode_enable(uint32_t usart_periph) { USART_CTL0(usart_periph) |= USART_CTL0_RWU; }
/*!
\brief receiver in active mode
@@ -289,10 +266,7 @@ void usart_mute_mode_enable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_mute_mode_disable(uint32_t usart_periph)
{
USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU);
}
void usart_mute_mode_disable(uint32_t usart_periph) { USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); }
/*!
\brief configure wakeup method in mute mode
@@ -304,8 +278,7 @@ void usart_mute_mode_disable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
{
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) {
USART_CTL0(usart_periph) &= ~(USART_CTL0_WM);
USART_CTL0(usart_periph) |= wmethod;
}
@@ -316,10 +289,7 @@ void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod)
\param[out] none
\retval none
*/
void usart_lin_mode_enable(uint32_t usart_periph)
{
USART_CTL1(usart_periph) |= USART_CTL1_LMEN;
}
void usart_lin_mode_enable(uint32_t usart_periph) { USART_CTL1(usart_periph) |= USART_CTL1_LMEN; }
/*!
\brief disable LIN mode
@@ -327,10 +297,7 @@ void usart_lin_mode_enable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_lin_mode_disable(uint32_t usart_periph)
{
USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN);
}
void usart_lin_mode_disable(uint32_t usart_periph) { USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); }
/*!
\brief configure lin break frame length
@@ -342,8 +309,7 @@ void usart_lin_mode_disable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen)
{
void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) {
USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN);
USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen);
}
@@ -354,10 +320,7 @@ void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lbl
\param[out] none
\retval none
*/
void usart_send_break(uint32_t usart_periph)
{
USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD;
}
void usart_send_break(uint32_t usart_periph) { USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; }
/*!
\brief enable half duplex mode
@@ -365,10 +328,7 @@ void usart_send_break(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_halfduplex_enable(uint32_t usart_periph)
{
USART_CTL2(usart_periph) |= USART_CTL2_HDEN;
}
void usart_halfduplex_enable(uint32_t usart_periph) { USART_CTL2(usart_periph) |= USART_CTL2_HDEN; }
/*!
\brief disable half duplex mode
@@ -376,10 +336,7 @@ void usart_halfduplex_enable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_halfduplex_disable(uint32_t usart_periph)
{
USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN);
}
void usart_halfduplex_disable(uint32_t usart_periph) { USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); }
/*!
\brief enable CK pin in synchronous mode
@@ -387,10 +344,7 @@ void usart_halfduplex_disable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_synchronous_clock_enable(uint32_t usart_periph)
{
USART_CTL1(usart_periph) |= USART_CTL1_CKEN;
}
void usart_synchronous_clock_enable(uint32_t usart_periph) { USART_CTL1(usart_periph) |= USART_CTL1_CKEN; }
/*!
\brief disable CK pin in synchronous mode
@@ -398,10 +352,7 @@ void usart_synchronous_clock_enable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_synchronous_clock_disable(uint32_t usart_periph)
{
USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN);
}
void usart_synchronous_clock_disable(uint32_t usart_periph) { USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); }
/*!
\brief configure USART synchronous mode parameters
@@ -421,8 +372,7 @@ void usart_synchronous_clock_disable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
{
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) {
uint32_t ctl = 0U;
/* read USART_CTL1 register */
@@ -441,10 +391,9 @@ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32
\param[out] none
\retval none
*/
void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut)
{
void usart_guard_time_config(uint32_t usart_periph, uint32_t gaut) {
USART_GP(usart_periph) &= ~(USART_GP_GUAT);
USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8));
USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut) << 8));
}
/*!
@@ -453,10 +402,7 @@ void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut)
\param[out] none
\retval none
*/
void usart_smartcard_mode_enable(uint32_t usart_periph)
{
USART_CTL2(usart_periph) |= USART_CTL2_SCEN;
}
void usart_smartcard_mode_enable(uint32_t usart_periph) { USART_CTL2(usart_periph) |= USART_CTL2_SCEN; }
/*!
\brief disable smartcard mode
@@ -464,10 +410,7 @@ void usart_smartcard_mode_enable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_smartcard_mode_disable(uint32_t usart_periph)
{
USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN);
}
void usart_smartcard_mode_disable(uint32_t usart_periph) { USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); }
/*!
\brief enable NACK in smartcard mode
@@ -475,10 +418,7 @@ void usart_smartcard_mode_disable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
{
USART_CTL2(usart_periph) |= USART_CTL2_NKEN;
}
void usart_smartcard_mode_nack_enable(uint32_t usart_periph) { USART_CTL2(usart_periph) |= USART_CTL2_NKEN; }
/*!
\brief disable NACK in smartcard mode
@@ -486,10 +426,7 @@ void usart_smartcard_mode_nack_enable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
{
USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN);
}
void usart_smartcard_mode_nack_disable(uint32_t usart_periph) { USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); }
/*!
\brief enable IrDA mode
@@ -497,10 +434,7 @@ void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_irda_mode_enable(uint32_t usart_periph)
{
USART_CTL2(usart_periph) |= USART_CTL2_IREN;
}
void usart_irda_mode_enable(uint32_t usart_periph) { USART_CTL2(usart_periph) |= USART_CTL2_IREN; }
/*!
\brief disable IrDA mode
@@ -508,10 +442,7 @@ void usart_irda_mode_enable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_irda_mode_disable(uint32_t usart_periph)
{
USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN);
}
void usart_irda_mode_disable(uint32_t usart_periph) { USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); }
/*!
\brief configure the peripheral clock prescaler in USART IrDA low-power mode
@@ -520,8 +451,7 @@ void usart_irda_mode_disable(uint32_t usart_periph)
\param[out] none
\retval none
*/
void usart_prescaler_config(uint32_t usart_periph, uint8_t psc)
{
void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) {
USART_GP(usart_periph) &= ~(USART_GP_PSC);
USART_GP(usart_periph) |= psc;
}
@@ -536,8 +466,7 @@ void usart_prescaler_config(uint32_t usart_periph, uint8_t psc)
\param[out] none
\retval none
*/
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
{
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) {
USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP);
USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp);
}
@@ -552,8 +481,7 @@ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
\param[out] none
\retval none
*/
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
{
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) {
uint32_t ctl = 0U;
ctl = USART_CTL2(usart_periph);
@@ -573,8 +501,7 @@ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
\param[out] none
\retval none
*/
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
{
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) {
uint32_t ctl = 0U;
ctl = USART_CTL2(usart_periph);
@@ -594,8 +521,7 @@ void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
\param[out] none
\retval none
*/
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
{
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) {
uint32_t ctl = 0U;
ctl = USART_CTL2(usart_periph);
@@ -615,8 +541,7 @@ void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
\param[out] none
\retval none
*/
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
{
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) {
uint32_t ctl = 0U;
ctl = USART_CTL2(usart_periph);
@@ -644,11 +569,10 @@ void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
{
if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) {
if (RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -665,10 +589,7 @@ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
\param[out] none
\retval none
*/
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
{
USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag));
}
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) { USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); }
/*!
\brief enable USART interrupt
@@ -686,10 +607,7 @@ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
\param[out] none
\retval none
*/
void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag)
{
USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag));
}
void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) { USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag)); }
/*!
\brief disable USART interrupt
@@ -707,10 +625,7 @@ void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag)
\param[out] none
\retval none
*/
void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag)
{
USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag));
}
void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) { USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag)); }
/*!
\brief get USART interrupt and flag status
@@ -731,17 +646,16 @@ void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
{
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) {
uint32_t intenable = 0U, flagstatus = 0U;
/* get the interrupt enable bit status */
intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)));
/* get the corresponding flag bit status */
flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag)));
if(flagstatus && intenable){
if (flagstatus && intenable) {
return SET;
}else{
} else {
return RESET;
}
}
@@ -758,24 +672,18 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
\param[out] none
\retval none
*/
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
{
USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag));
}
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag) { USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); }
int usart_write(uint32_t usart_periph,int ch)
{
usart_data_transmit(usart_periph, (uint8_t) ch );
while (usart_flag_get(usart_periph, USART_FLAG_TBE)== RESET){
}
int usart_write(uint32_t usart_periph, int ch) {
usart_data_transmit(usart_periph, (uint8_t)ch);
while (usart_flag_get(usart_periph, USART_FLAG_TBE) == RESET) {}
return ch;
}
uint8_t usart_read(uint32_t usart_periph)
{
uint8_t usart_read(uint32_t usart_periph) {
/* loop until RBNE = 1 */
while (usart_flag_get(usart_periph, USART_FLAG_RBNE) == RESET);
return(usart_data_receive(usart_periph));
while (usart_flag_get(usart_periph, USART_FLAG_RBNE) == RESET)
;
return (usart_data_receive(usart_periph));
}

37
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_wwdgt.c vendored
View File

@@ -35,9 +35,9 @@ OF SUCH DAMAGE.
#include "gd32vf103_wwdgt.h"
/* write value to WWDGT_CTL_CNT bit field */
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
#define CTL_CNT(regval) (BITS(0, 6) & ((uint32_t)(regval) << 0))
/* write value to WWDGT_CFG_WIN bit field */
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
#define CFG_WIN(regval) (BITS(0, 6) & ((uint32_t)(regval) << 0))
/*!
\brief reset the window watchdog timer configuration
@@ -45,8 +45,7 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void wwdgt_deinit(void)
{
void wwdgt_deinit(void) {
rcu_periph_reset_enable(RCU_WWDGTRST);
rcu_periph_reset_disable(RCU_WWDGTRST);
}
@@ -57,10 +56,7 @@ void wwdgt_deinit(void)
\param[out] none
\retval none
*/
void wwdgt_enable(void)
{
WWDGT_CTL |= WWDGT_CTL_WDGTEN;
}
void wwdgt_enable(void) { WWDGT_CTL |= WWDGT_CTL_WDGTEN; }
/*!
\brief configure the window watchdog timer counter value
@@ -68,8 +64,7 @@ void wwdgt_enable(void)
\param[out] none
\retval none
*/
void wwdgt_counter_update(uint16_t counter_value)
{
void wwdgt_counter_update(uint16_t counter_value) {
uint32_t reg = 0U;
reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
@@ -91,13 +86,12 @@ void wwdgt_counter_update(uint16_t counter_value)
\param[out] none
\retval none
*/
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
{
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) {
uint32_t reg_cfg = 0U, reg_ctl = 0U;
/* clear WIN and PSC bits, clear CNT bit */
reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
reg_cfg = (WWDGT_CFG & (~(WWDGT_CFG_WIN | WWDGT_CFG_PSC)));
reg_ctl = (WWDGT_CTL & (~WWDGT_CTL_CNT));
/* configure WIN and PSC bits, configure CNT bit */
reg_cfg |= CFG_WIN(window);
@@ -114,10 +108,7 @@ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
\param[out] none
\retval none
*/
void wwdgt_interrupt_enable(void)
{
WWDGT_CFG |= WWDGT_CFG_EWIE;
}
void wwdgt_interrupt_enable(void) { WWDGT_CFG |= WWDGT_CFG_EWIE; }
/*!
\brief check early wakeup interrupt state of WWDGT
@@ -125,9 +116,8 @@ void wwdgt_interrupt_enable(void)
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus wwdgt_flag_get(void)
{
if(WWDGT_STAT & WWDGT_STAT_EWIF){
FlagStatus wwdgt_flag_get(void) {
if (WWDGT_STAT & WWDGT_STAT_EWIF) {
return SET;
}
@@ -140,7 +130,4 @@ FlagStatus wwdgt_flag_get(void)
\param[out] none
\retval none
*/
void wwdgt_flag_clear(void)
{
WWDGT_STAT &= (~WWDGT_STAT_EWIF);
}
void wwdgt_flag_clear(void) { WWDGT_STAT &= (~WWDGT_STAT_EWIF); }

7
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/close.c vendored
View File

@@ -1,7 +1,4 @@
#include <errno.h>
#include "stub.h"
#include <errno.h>
int _close(int fd)
{
return _stub(EBADF);
}
int _close(int fd) { return _stub(EBADF); }

11
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/fstat.c vendored
View File

@@ -1,9 +1,6 @@
#include <errno.h>
#include <unistd.h>
#include <sys/stat.h>
#include "stub.h"
#include <errno.h>
#include <sys/stat.h>
#include <unistd.h>
int _fstat(int fd, struct stat* st)
{
return _stub(EBADF);
}
int _fstat(int fd, struct stat *st) { return _stub(EBADF); }

5
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/gettimeofday.c vendored
View File

@@ -1,9 +1,8 @@
#include "nuclei_sdk_soc.h"
#include <errno.h>
#include <sys/time.h>
#include "nuclei_sdk_soc.h"
int _gettimeofday(struct timeval *tp, void *tzp)
{
int _gettimeofday(struct timeval *tp, void *tzp) {
uint64_t cycles;
cycles = __get_rv_cycle();

3
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/isatty.c vendored
View File

@@ -2,8 +2,7 @@
#include <unistd.h>
int _isatty(int fd)
{
int _isatty(int fd) {
if (fd == STDOUT_FILENO || fd == STDERR_FILENO) {
return 1;
}

11
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/lseek.c vendored
View File

@@ -1,9 +1,6 @@
#include <errno.h>
#include <unistd.h>
#include <sys/types.h>
#include "stub.h"
#include <errno.h>
#include <sys/types.h>
#include <unistd.h>
off_t _lseek(int fd, off_t ptr, int dir)
{
return _stub(EBADF);
}
off_t _lseek(int fd, off_t ptr, int dir) { return _stub(EBADF); }

14
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/read.c vendored
View File

@@ -1,12 +1,10 @@
#include <stdint.h>
#include <errno.h>
#include <unistd.h>
#include <sys/types.h>
#include "nuclei_sdk_hal.h"
#include "gd32vf103_usart.h"
#include "nuclei_sdk_hal.h"
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
// #define UART_AUTO_ECHO
ssize_t _read(int fd, void* ptr, size_t len) {
return -1;
}
ssize_t _read(int fd, void *ptr, size_t len) { return -1; }

5
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/sbrk.c vendored
View File

@@ -1,11 +1,10 @@
/* See LICENSE of license details. */
#include <stdint.h>
#include <stddef.h>
#include <stdint.h>
#include <unistd.h>
void *_sbrk(ptrdiff_t incr)
{
void *_sbrk(ptrdiff_t incr) {
extern char _end[];
extern char _heap_end[];
static char *curbrk = _end;

14
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/Stubs/write.c vendored
View File

@@ -1,12 +1,10 @@
/* See LICENSE of license details. */
#include <stdint.h>
#include <errno.h>
#include <unistd.h>
#include <sys/types.h>
#include <nuclei_sdk_hal.h>
#include "gd32vf103_usart.h"
#include <errno.h>
#include <nuclei_sdk_hal.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
ssize_t _write(int fd, const void* ptr, size_t len) {
return -1;
}
ssize_t _write(int fd, const void *ptr, size_t len) { return -1; }

17
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/gd32vf103_soc.c vendored
View File

@@ -1,12 +1,8 @@
#include "nuclei_sdk_soc.h"
static uint32_t get_timer_freq()
{
return SOC_TIMER_FREQ;
}
static uint32_t get_timer_freq() { return SOC_TIMER_FREQ; }
uint32_t measure_cpu_freq(uint32_t n)
{
uint32_t measure_cpu_freq(uint32_t n) {
uint32_t start_mcycle, delta_mcycle;
uint32_t start_mtime, delta_mtime;
uint32_t mtime_freq = get_timer_freq();
@@ -23,12 +19,10 @@ uint32_t measure_cpu_freq(uint32_t n)
delta_mcycle = __RV_CSR_READ(CSR_MCYCLE) - start_mcycle;
} while (delta_mtime < n);
return (delta_mcycle / delta_mtime) * mtime_freq
+ ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
return (delta_mcycle / delta_mtime) * mtime_freq + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
}
uint32_t get_cpu_freq()
{
uint32_t get_cpu_freq() {
uint32_t cpu_freq;
// warm up
@@ -46,8 +40,7 @@ uint32_t get_cpu_freq()
* \param[in] count: count in milliseconds
* \remarks
*/
void delay_1ms(uint32_t count)
{
void delay_1ms(uint32_t count) {
uint64_t start_mtime, delta_mtime;
uint64_t delay_ticks = (SOC_TIMER_FREQ * (uint64_t)count) / 1000;

93
source/Core/BSP/Pine64/Vendor/SoC/gd32vf103/Common/Source/system_gd32vf103.c vendored
View File

@@ -23,9 +23,9 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "nuclei_sdk_hal.h"
#include <stdint.h>
#include <stdio.h>
#include "nuclei_sdk_hal.h"
/*----------------------------------------------------------------------------
Define clocks
@@ -109,8 +109,7 @@ static void system_clock_108m_hxtal(void) {
/* if fail */
if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while (1) {
}
while (1) {}
}
/* HXTAL is stable */
@@ -127,54 +126,44 @@ static void system_clock_108m_hxtal(void) {
if (HXTAL_VALUE == 25000000) {
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF |
RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 |
RCU_PREDV0_DIV10);
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10);
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {
}
while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {}
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL2EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {
}
while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {}
} else if (HXTAL_VALUE == 8000000) {
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF |
RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 |
RCU_PLL1_MUL20 | RCU_PLL2_MUL20);
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20);
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {
}
while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {}
/* enable PLL2 */
RCU_CTL |= RCU_CTL_PLL2EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {
}
while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {}
}
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
}
while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
}
while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {}
}
/*!
@@ -183,9 +172,7 @@ static void system_clock_108m_hxtal(void) {
\param[out] none
\retval none
*/
static void system_clock_config(void) {
system_clock_108m_hxtal();
}
static void system_clock_config(void) { system_clock_108m_hxtal(); }
/**
* \brief Function to update the variable \ref SystemCoreClock
@@ -292,9 +279,7 @@ void SystemInit(void) {
RCU_CTL |= RCU_CTL_IRC8MEN;
/* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC
| RCU_CFG0_APB2PSC |
RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL);
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL);
/* reset HXTALEN, CKMEN, PLLEN bits */
RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
@@ -304,13 +289,11 @@ void SystemInit(void) {
/* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4);
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4);
RCU_CFG1 = 0x00000000U;
/* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN
| RCU_CTL_HXTALEN);
RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
/* disable all interrupts */
RCU_INT = 0x00FF0000U;
@@ -354,8 +337,7 @@ typedef void (*EXC_HANDLER)(unsigned long mcause, unsigned long sp);
* This function provided a default exception and NMI handling code for all exception ids.
* By default, It will just print some information for debug, Vendor can customize it according to its requirements.
*/
static void system_default_exception_handler(unsigned long mcause,
unsigned long sp) {
static void system_default_exception_handler(unsigned long mcause, unsigned long sp) {
/* TODO: Uncomment this if you have implement printf function */
printf("MCAUSE: 0x%lx\r\n", mcause);
printf("MEPC : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC));
@@ -373,8 +355,7 @@ static void system_default_exception_handler(unsigned long mcause,
*/
static void Exception_Init(void) {
for (int i = 0; i < MAX_SYSTEM_EXCEPTION_NUM + 1; i++) {
SystemExceptionHandlers[i] =
(unsigned long) system_default_exception_handler;
SystemExceptionHandlers[i] = (unsigned long)system_default_exception_handler;
}
}
@@ -424,30 +405,29 @@ unsigned long Exception_Get_EXC(uint32_t EXCn) {
* which can help developer to register your exception handler for specific exception number.
*/
uint32_t core_exception_handler(unsigned long mcause, unsigned long sp) {
uint32_t EXCn = (uint32_t) (mcause & 0X00000fff);
uint32_t EXCn = (uint32_t)(mcause & 0X00000fff);
EXC_HANDLER exc_handler;
if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM)) {
exc_handler = (EXC_HANDLER) SystemExceptionHandlers[EXCn];
exc_handler = (EXC_HANDLER)SystemExceptionHandlers[EXCn];
} else if (EXCn == NMI_EXCn) {
exc_handler =
(EXC_HANDLER) SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM];
exc_handler = (EXC_HANDLER)SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM];
} else {
exc_handler = (EXC_HANDLER) system_default_exception_handler;
exc_handler = (EXC_HANDLER)system_default_exception_handler;
}
if (exc_handler != NULL) {
exc_handler(mcause, sp);
}
return 0;
}
/** @} *//* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
void SystemBannerPrint(void) {
#if defined(NUCLEI_BANNER) && (NUCLEI_BANNER == 1)
#ifndef DOWNLOAD_MODE
#error DOWNLOAD_MODE is not defined via build system, please check!
#endif
const char* download_modes[] = {"FLASHXIP", "FLASH", "ILM", "DDR"};
const char *download_modes[] = {"FLASHXIP", "FLASH", "ILM", "DDR"};
printf("Nuclei SDK Build Time: %s, %s\r\n", __DATE__, __TIME__);
printf("Download Mode: %s\r\n", download_modes[DOWNLOAD_MODE]);
printf("CPU Frequency %d Hz\r\n", SystemCoreClock);
@@ -482,11 +462,8 @@ void ECLIC_Init(void) {
* - This function use to configure specific eclic interrupt and register its interrupt handler and enable its interrupt.
* - If the vector table is placed in read-only section(FLASHXIP mode), handler could not be installed
*/
int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv,
ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority,
void *handler) {
if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT)
|| (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void *handler) {
if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) || (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
return -1;
}
@@ -500,13 +477,13 @@ int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv,
ECLIC_SetPriorityIRQ(IRQn, priority);
if (handler != NULL) {
/* set interrupt handler entry to vector table */
ECLIC_SetVector(IRQn, (rv_csr_t) handler);
ECLIC_SetVector(IRQn, (rv_csr_t)handler);
}
/* enable interrupt */
ECLIC_EnableIRQ(IRQn);
return 0;
}
/** @} *//* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
/**
* \brief early init function before main
@@ -534,9 +511,7 @@ void _premain_init(void) {
* by __libc_fini_array function, so we defined a new function
* to do initialization
*/
void _postmain_fini(int status) {
/* TODO: Add your own finishing code here, called after main */
}
void _postmain_fini(int status) { /* TODO: Add your own finishing code here, called after main */ }
/**
* \brief _init function called in __libc_init_array()
@@ -547,9 +522,7 @@ void _postmain_fini(int status) {
* \note
* Please use \ref _premain_init function now
*/
void _init(void) {
/* Don't put any code here, please use _premain_init now */
}
void _init(void) { /* Don't put any code here, please use _premain_init now */ }
/**
* \brief _fini function called in __libc_fini_array()
@@ -560,8 +533,6 @@ void _init(void) {
* \note
* Please use \ref _postmain_fini function now
*/
void _fini(void) {
/* Don't put any code here, please use _postmain_fini now */
}
void _fini(void) { /* Don't put any code here, please use _postmain_fini now */ }
/** @} *//* End of Doxygen Group NMSIS_Core_SystemAndClock */
/** @} */ /* End of Doxygen Group NMSIS_Core_SystemAndClock */

17
source/Core/BSP/Pine64/flash.c
View File

@@ -10,9 +10,9 @@
#include "gd32vf103_libopt.h"
#include "string.h"
#define FMC_PAGE_SIZE ((uint16_t)0x400U)
//static uint16_t settings_page[FMC_PAGE_SIZE] __attribute__ ((section (".settings_page")));
//Linker script doesnt want to play, so for now its hard coded
#define SETTINGS_START_PAGE (0x08000000 +(127*1024))
// static uint16_t settings_page[FMC_PAGE_SIZE] __attribute__ ((section (".settings_page")));
// Linker script doesnt want to play, so for now its hard coded
#define SETTINGS_START_PAGE (0x08000000 + (127 * 1024))
uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
/* unlock the flash program/erase controller */
@@ -23,11 +23,11 @@ uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
fmc_flag_clear(FMC_FLAG_WPERR);
fmc_flag_clear(FMC_FLAG_PGERR);
resetWatchdog();
fmc_page_erase((uint32_t) SETTINGS_START_PAGE);
fmc_page_erase((uint32_t)SETTINGS_START_PAGE);
resetWatchdog();
uint16_t *data = (uint16_t*) buffer;
uint16_t *data = (uint16_t *)buffer;
for (uint8_t i = 0; i < (length / 2); i++) {
fmc_halfword_program((uint32_t) SETTINGS_START_PAGE + (i * 2), data[i]);
fmc_halfword_program((uint32_t)SETTINGS_START_PAGE + (i * 2), data[i]);
fmc_flag_clear(FMC_FLAG_END);
fmc_flag_clear(FMC_FLAG_WPERR);
fmc_flag_clear(FMC_FLAG_PGERR);
@@ -38,10 +38,9 @@ uint8_t flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
}
void flash_read_buffer(uint8_t *buffer, const uint16_t length) {
uint32_t* b = (uint32_t*) buffer;
uint32_t* b2 = (uint32_t*) SETTINGS_START_PAGE;
uint32_t *b = (uint32_t *)buffer;
uint32_t *b2 = (uint32_t *)SETTINGS_START_PAGE;
for (int i = 0; i < length / 4; i++) {
b[i] = b2[i];
}
}

106
source/Core/BSP/Pine64/fusb302b.cpp
View File

@@ -16,12 +16,12 @@
*/
#include "Model_Config.h"
#ifdef POW_PD
#include "Setup.h"
#include "BSP.h"
#include "fusb302b.h"
#include "I2C_Wrapper.hpp"
#include <pd.h>
#include "Setup.h"
#include "fusb302b.h"
#include "int_n.h"
#include <pd.h>
/*
* Read a single byte from the FUSB302B
*
@@ -32,7 +32,7 @@
*/
static uint8_t fusb_read_byte(uint8_t addr) {
uint8_t data[1];
if (!FRToSI2C::Mem_Read(FUSB302B_ADDR, addr, (uint8_t*) data, 1)) {
if (!FRToSI2C::Mem_Read(FUSB302B_ADDR, addr, (uint8_t *)data, 1)) {
return 0;
}
return data[0];
@@ -46,9 +46,7 @@ static uint8_t fusb_read_byte(uint8_t addr) {
* size: The number of bytes to read
* buf: The buffer into which data will be read
*/
static bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) {
return FRToSI2C::Mem_Read(FUSB302B_ADDR, addr, buf, size);
}
static bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) { return FRToSI2C::Mem_Read(FUSB302B_ADDR, addr, buf, size); }
/*
* Write a single byte to the FUSB302B
@@ -58,7 +56,7 @@ static bool fusb_read_buf(uint8_t addr, uint8_t size, uint8_t *buf) {
* byte: The value to write
*/
static bool fusb_write_byte(uint8_t addr, uint8_t byte) {
FRToSI2C::Mem_Write(FUSB302B_ADDR, addr, (uint8_t*) &byte, 1);
FRToSI2C::Mem_Write(FUSB302B_ADDR, addr, (uint8_t *)&byte, 1);
return true;
}
@@ -71,24 +69,15 @@ static bool fusb_write_byte(uint8_t addr, uint8_t byte) {
* buf: The buffer to write
*/
static bool fusb_write_buf(uint8_t addr, uint8_t size, const uint8_t *buf) {
FRToSI2C::Mem_Write(FUSB302B_ADDR, addr, (uint8_t*) buf, size);
return true; //TODO
FRToSI2C::Mem_Write(FUSB302B_ADDR, addr, (uint8_t *)buf, size);
return true; // TODO
}
void fusb_send_message(const union pd_msg *msg) {
/* Token sequences for the FUSB302B */
static uint8_t sop_seq[5] = {
FUSB_FIFO_TX_SOP1,
FUSB_FIFO_TX_SOP1,
FUSB_FIFO_TX_SOP1,
FUSB_FIFO_TX_SOP2,
FUSB_FIFO_TX_PACKSYM };
static const uint8_t eop_seq[4] = {
FUSB_FIFO_TX_JAM_CRC,
FUSB_FIFO_TX_EOP,
FUSB_FIFO_TX_TXOFF,
FUSB_FIFO_TX_TXON };
static uint8_t sop_seq[5] = {FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP1, FUSB_FIFO_TX_SOP2, FUSB_FIFO_TX_PACKSYM};
static const uint8_t eop_seq[4] = {FUSB_FIFO_TX_JAM_CRC, FUSB_FIFO_TX_EOP, FUSB_FIFO_TX_TXOFF, FUSB_FIFO_TX_TXON};
/* Take the I2C2 mutex now so there can't be a race condition on sop_seq */
/* Get the length of the message: a two-octet header plus NUMOBJ four-octet
@@ -99,10 +88,9 @@ void fusb_send_message(const union pd_msg *msg) {
sop_seq[4] = FUSB_FIFO_TX_PACKSYM | msg_len;
/* Write all three parts of the message to the TX FIFO */
fusb_write_buf( FUSB_FIFOS, 5, sop_seq);
fusb_write_buf( FUSB_FIFOS, msg_len, msg->bytes);
fusb_write_buf( FUSB_FIFOS, 4, eop_seq);
fusb_write_buf(FUSB_FIFOS, 5, sop_seq);
fusb_write_buf(FUSB_FIFOS, msg_len, msg->bytes);
fusb_write_buf(FUSB_FIFOS, 4, eop_seq);
}
uint8_t fusb_read_message(union pd_msg *msg) {
@@ -112,17 +100,17 @@ uint8_t fusb_read_message(union pd_msg *msg) {
// Read the header. If its not a SOP we dont actually want it at all
// But on some revisions of the fusb if you dont both pick them up and read them out of the fifo, it gets stuck
fusb_read_byte( FUSB_FIFOS);
fusb_read_byte(FUSB_FIFOS);
/* Read the message header into msg */
fusb_read_buf( FUSB_FIFOS, 2, msg->bytes);
fusb_read_buf(FUSB_FIFOS, 2, msg->bytes);
/* Get the number of data objects */
numobj = PD_NUMOBJ_GET(msg);
/* If there is at least one data object, read the data objects */
if (numobj > 0) {
fusb_read_buf( FUSB_FIFOS, numobj * 4, msg->bytes + 2);
fusb_read_buf(FUSB_FIFOS, numobj * 4, msg->bytes + 2);
}
/* Throw the CRC32 in the garbage, since the PHY already checked it. */
fusb_read_buf( FUSB_FIFOS, 4, garbage);
fusb_read_buf(FUSB_FIFOS, 4, garbage);
return 0;
}
@@ -130,8 +118,7 @@ uint8_t fusb_read_message(union pd_msg *msg) {
void fusb_send_hardrst() {
/* Send a hard reset */
fusb_write_byte( FUSB_CONTROL3, 0x07 | FUSB_CONTROL3_SEND_HARD_RESET);
fusb_write_byte(FUSB_CONTROL3, 0x07 | FUSB_CONTROL3_SEND_HARD_RESET);
}
bool fusb_setup() {
@@ -139,52 +126,51 @@ bool fusb_setup() {
return false;
}
/* Fully reset the FUSB302B */
fusb_write_byte( FUSB_RESET, FUSB_RESET_SW_RES);
fusb_write_byte(FUSB_RESET, FUSB_RESET_SW_RES);
osDelay(2);
uint8_t tries = 0;
while (!fusb_read_id()) {
osDelay(10);
tries++;
if (tries > 5) {
return false; //Welp :(
return false; // Welp :(
}
}
/* Turn on all power */
fusb_write_byte( FUSB_POWER, 0x0F);
fusb_write_byte(FUSB_POWER, 0x0F);
/* Set interrupt masks */
//Setting to 0 so interrupts are allowed
fusb_write_byte( FUSB_MASK1, 0x00);
fusb_write_byte( FUSB_MASKA, 0x00);
fusb_write_byte( FUSB_MASKB, 0x00);
fusb_write_byte( FUSB_CONTROL0, 0b11 << 2);
// Setting to 0 so interrupts are allowed
fusb_write_byte(FUSB_MASK1, 0x00);
fusb_write_byte(FUSB_MASKA, 0x00);
fusb_write_byte(FUSB_MASKB, 0x00);
fusb_write_byte(FUSB_CONTROL0, 0b11 << 2);
/* Enable automatic retransmission */
fusb_write_byte( FUSB_CONTROL3, 0x07);
//set defaults
fusb_write_byte( FUSB_CONTROL2, 0x00);
fusb_write_byte(FUSB_CONTROL3, 0x07);
// set defaults
fusb_write_byte(FUSB_CONTROL2, 0x00);
/* Flush the RX buffer */
fusb_write_byte( FUSB_CONTROL1,
FUSB_CONTROL1_RX_FLUSH);
fusb_write_byte(FUSB_CONTROL1, FUSB_CONTROL1_RX_FLUSH);
/* Measure CC1 */
fusb_write_byte( FUSB_SWITCHES0, 0x07);
fusb_write_byte(FUSB_SWITCHES0, 0x07);
osDelay(10);
uint8_t cc1 = fusb_read_byte( FUSB_STATUS0) & FUSB_STATUS0_BC_LVL;
uint8_t cc1 = fusb_read_byte(FUSB_STATUS0) & FUSB_STATUS0_BC_LVL;
/* Measure CC2 */
fusb_write_byte( FUSB_SWITCHES0, 0x0B);
fusb_write_byte(FUSB_SWITCHES0, 0x0B);
osDelay(10);
uint8_t cc2 = fusb_read_byte( FUSB_STATUS0) & FUSB_STATUS0_BC_LVL;
uint8_t cc2 = fusb_read_byte(FUSB_STATUS0) & FUSB_STATUS0_BC_LVL;
/* Select the correct CC line for BMC signaling; also enable AUTO_CRC */
if (cc1 > cc2) {
fusb_write_byte( FUSB_SWITCHES1, 0x25);
fusb_write_byte( FUSB_SWITCHES0, 0x07);
fusb_write_byte(FUSB_SWITCHES1, 0x25);
fusb_write_byte(FUSB_SWITCHES0, 0x07);
} else {
fusb_write_byte( FUSB_SWITCHES1, 0x26);
fusb_write_byte( FUSB_SWITCHES0, 0x0B);
fusb_write_byte(FUSB_SWITCHES1, 0x26);
fusb_write_byte(FUSB_SWITCHES0, 0x0B);
}
fusb_reset();
@@ -195,15 +181,13 @@ bool fusb_setup() {
void fusb_get_status(union fusb_status *status) {
/* Read the interrupt and status flags into status */
fusb_read_buf( FUSB_STATUS0A, 7, status->bytes);
fusb_read_buf(FUSB_STATUS0A, 7, status->bytes);
}
enum fusb_typec_current fusb_get_typec_current() {
/* Read the BC_LVL into a variable */
enum fusb_typec_current bc_lvl = (enum fusb_typec_current) (fusb_read_byte(
FUSB_STATUS0) & FUSB_STATUS0_BC_LVL);
enum fusb_typec_current bc_lvl = (enum fusb_typec_current)(fusb_read_byte(FUSB_STATUS0) & FUSB_STATUS0_BC_LVL);
return bc_lvl;
}
@@ -211,15 +195,15 @@ enum fusb_typec_current fusb_get_typec_current() {
void fusb_reset() {
/* Flush the TX buffer */
fusb_write_byte( FUSB_CONTROL0, 0x44);
fusb_write_byte(FUSB_CONTROL0, 0x44);
/* Flush the RX buffer */
fusb_write_byte( FUSB_CONTROL1, FUSB_CONTROL1_RX_FLUSH);
fusb_write_byte(FUSB_CONTROL1, FUSB_CONTROL1_RX_FLUSH);
/* Reset the PD logic */
// fusb_write_byte( FUSB_RESET, FUSB_RESET_PD_RESET);
// fusb_write_byte( FUSB_RESET, FUSB_RESET_PD_RESET);
}
bool fusb_read_id() {
//Return true if read of the revision ID is sane
// Return true if read of the revision ID is sane
uint8_t version = 0;
fusb_read_buf(FUSB_DEVICE_ID, 1, &version);
if (version == 0 || version == 0xFF)
@@ -227,7 +211,7 @@ bool fusb_read_id() {
return true;
}
uint8_t fusb302_detect() {
//Probe the I2C bus for its address
// Probe the I2C bus for its address
return FRToSI2C::probe(FUSB302B_ADDR);
}

7
source/Core/BSP/Pine64/logo.cpp
View File

@@ -13,13 +13,12 @@
#define LOGO_HEADER_VALUE 0xF00DAA55
uint8_t showBootLogoIfavailable() {
// Do not show logo data if signature is not found.
if (LOGO_HEADER_VALUE != *(reinterpret_cast<const uint32_t*>(FLASH_LOGOADDR))) {
// Do not show logo data if signature is not found.
if (LOGO_HEADER_VALUE != *(reinterpret_cast<const uint32_t *>(FLASH_LOGOADDR))) {
return 0;
}
OLED::drawAreaSwapped(0, 0, 96, 16, (uint8_t*) (FLASH_LOGOADDR + 4));
OLED::drawAreaSwapped(0, 0, 96, 16, (uint8_t *)(FLASH_LOGOADDR + 4));
OLED::refresh();
return 1;
}

14
source/Core/BSP/Pine64/postRTOS.cpp
View File

@@ -1,15 +1,15 @@
#include "BSP.h"
#include "FreeRTOS.h"
#include "I2C_Wrapper.hpp"
#include "QC3.h"
#include "Settings.h"
#include "Si7210.h"
#include "cmsis_os.h"
#include "fusbpd.h"
#include "main.hpp"
#include "power.hpp"
#include "stdlib.h"
#include "task.h"
#include "I2C_Wrapper.hpp"
#include "fusbpd.h"
#include "Si7210.h"
bool hall_effect_present = false;
void postRToSInit() {
@@ -20,19 +20,15 @@ void postRToSInit() {
}
#endif
#ifdef POW_PD
//Spawn all of the USB-C processors
// Spawn all of the USB-C processors
fusb302_start_processing();
#endif
}
int16_t getRawHallEffect() {
if (hall_effect_present) {
return Si7210::read();
}
return 0;
}
bool getHallSensorFitted() {
return hall_effect_present;
}
bool getHallSensorFitted() { return hall_effect_present; }

4
source/Core/BSP/Pine64/preRTOS.cpp
View File

@@ -5,13 +5,13 @@
* Author: Ralim
*/
#include "gd32vf103_libopt.h"
#include "BSP.h"
#include "Pins.h"
#include "Setup.h"
#include "gd32vf103_libopt.h"
#include <I2C_Wrapper.hpp>
void preRToSInit() {
//Normal system bringup -- GPIO etc
// Normal system bringup -- GPIO etc
hardware_init();
delay_ms(5);