diff --git a/source/Core/BSP/Magic/IRQ.cpp b/source/Core/BSP/Magic/IRQ.cpp index 9e2eefe6..9e514faf 100644 --- a/source/Core/BSP/Magic/IRQ.cpp +++ b/source/Core/BSP/Magic/IRQ.cpp @@ -22,15 +22,11 @@ extern "C" { history ADC_Vin; history ADC_Temp; history ADC_Tip; - - -void adc_fifo_irq(void) { +void adc_fifo_irq(void) { if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) { - bool wakePID = false; // Read out all entries in the fifo - const uint8_t cnt = ADC_Get_FIFO_Count(); - for (uint8_t i = 0; i < cnt; i++) { - const uint32_t reading = ADC_Read_FIFO(); + while (ADC_Get_FIFO_Count()) { + volatile uint32_t reading = ADC_Read_FIFO(); // As per manual, 26 bit reading; lowest 16 are the ADC uint16_t sample = reading & 0xFFFF; uint8_t source = (reading >> 21) & 0b11111; @@ -40,7 +36,6 @@ void adc_fifo_irq(void) { break; case TIP_TEMP_ADC_CHANNEL: ADC_Tip.update(sample); - wakePID = true; break; case VIN_ADC_CHANNEL: ADC_Vin.update(sample); @@ -50,19 +45,18 @@ void adc_fifo_irq(void) { break; } } - if (wakePID) { - // unblock the PID controller thread - if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - if (pidTaskNotification) { - vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken); - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - } + + // unblock the PID controller thread + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + if (pidTaskNotification) { + vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } } - // Clear IRQ - ADC_IntClr(ADC_INT_FIFO_READY); } + // Clear IRQ + ADC_IntClr(ADC_INT_ALL); } static bool fastPWM = false; diff --git a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h index 9fe07dac..94227094 100644 --- a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h +++ b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h @@ -24,54 +24,54 @@ #define __HAL_GPIO__H__ #ifdef __cplusplus -extern "C"{ +extern "C" { #endif -#include "hal_common.h" -#include "drv_device.h" #include "bl702_config.h" +#include "drv_device.h" +#include "hal_common.h" enum gpio_pin_type { - GPIO_PIN_0 = 0, - GPIO_PIN_1, - GPIO_PIN_2, - GPIO_PIN_3, - GPIO_PIN_4, - GPIO_PIN_5, - GPIO_PIN_6, - GPIO_PIN_7, - GPIO_PIN_8, - GPIO_PIN_9, - GPIO_PIN_10, - GPIO_PIN_11, - GPIO_PIN_12, - GPIO_PIN_13, - GPIO_PIN_14, - GPIO_PIN_15, - GPIO_PIN_16, - GPIO_PIN_17, - GPIO_PIN_18, - GPIO_PIN_19, - GPIO_PIN_20, - GPIO_PIN_21, - GPIO_PIN_22, - GPIO_PIN_23, - GPIO_PIN_24, - GPIO_PIN_25, - GPIO_PIN_26, - GPIO_PIN_27, - GPIO_PIN_28, - GPIO_PIN_29, - GPIO_PIN_30, - GPIO_PIN_31, - GPIO_PIN_MAX, + GPIO_PIN_0 = 0, + GPIO_PIN_1, + GPIO_PIN_2, + GPIO_PIN_3, + GPIO_PIN_4, + GPIO_PIN_5, + GPIO_PIN_6, + GPIO_PIN_7, + GPIO_PIN_8, + GPIO_PIN_9, + GPIO_PIN_10, + GPIO_PIN_11, + GPIO_PIN_12, + GPIO_PIN_13, + GPIO_PIN_14, + GPIO_PIN_15, + GPIO_PIN_16, + GPIO_PIN_17, + GPIO_PIN_18, + GPIO_PIN_19, + GPIO_PIN_20, + GPIO_PIN_21, + GPIO_PIN_22, + GPIO_PIN_23, + GPIO_PIN_24, + GPIO_PIN_25, + GPIO_PIN_26, + GPIO_PIN_27, + GPIO_PIN_28, + GPIO_PIN_29, + GPIO_PIN_30, + GPIO_PIN_31, + GPIO_PIN_MAX, }; #define GPIO_OUTPUT_MODE 0 #define GPIO_OUTPUT_PP_MODE 1 #define GPIO_OUTPUT_PD_MODE 2 #define GPIO_INPUT_MODE 3 -#define GPIO_INPUT_PP_MODE 4 +#define GPIO_INPUT_PU_MODE 4 #define GPIO_INPUT_PD_MODE 5 #define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6 #define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7 @@ -86,7 +86,7 @@ enum gpio_pin_type { void gpio_set_mode(uint32_t pin, uint32_t mode); void gpio_write(uint32_t pin, uint32_t value); void gpio_toggle(uint32_t pin); -int gpio_read(uint32_t pin); +int gpio_read(uint32_t pin); void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)); void gpio_irq_enable(uint32_t pin, uint8_t enabled); diff --git a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_adc.c b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_adc.c deleted file mode 100644 index 1ceae33e..00000000 --- a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_adc.c +++ /dev/null @@ -1,427 +0,0 @@ -/** - * @file hal_adc.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_adc.h" -#include "hal_clock.h" -#include "hal_dma.h" -#include "bl702_glb.h" -#include "bl702_dma.h" -#include "bl702_adc.h" -#include "adc_config.h" - -#ifdef BSP_USING_ADC0 -static void ADC_IRQ(void); -#endif - -static adc_device_t adcx_device[ADC_MAX_INDEX] = { -#ifdef BSP_USING_ADC0 - ADC0_CONFIG, -#endif -}; - -/** - * @brief Check whether Channel Corresponding IO is configed success by Board System - * - * @param pos_list pos channel list - * @param neg_list negative channel list - * @param channelNum channel number - */ -uint8_t adc_check_channel_status(uint8_t *pos_list, uint8_t *neg_list, uint16_t channelNum) -{ - uint16_t i = 0; - - uint8_t channel_io_reference_table[] = { - GLB_GPIO_PIN_8, /* CH0 IO */ - GLB_GPIO_PIN_15, /* CH1 IO */ - GLB_GPIO_PIN_17, /* CH2 IO */ - GLB_GPIO_PIN_11, /* CH3 IO */ - GLB_GPIO_PIN_12, /* CH4 IO */ - GLB_GPIO_PIN_14, /* CH5 IO */ - GLB_GPIO_PIN_7, /* CH6 IO */ - GLB_GPIO_PIN_9, /* CH7 IO */ - GLB_GPIO_PIN_18, /* CH8 IO */ - GLB_GPIO_PIN_19, /* CH9 IO */ - GLB_GPIO_PIN_20, /* CH10 IO */ - GLB_GPIO_PIN_21, /* CH11 IO */ - - }; - - for (i = 0; i < channelNum; i++) { - if (pos_list[i] > ADC_CHANNEL11) { - continue; - } - - if (GLB_GPIO_Get_Fun(channel_io_reference_table[pos_list[i]]) != GPIO_FUN_ANALOG) { - return ERROR; - } - } - - return SUCCESS; -} -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int adc_open(struct device *dev, uint16_t oflag) -{ - adc_device_t *adc_device = (adc_device_t *)dev; - ADC_CFG_Type adc_cfg = { 0 }; - ADC_FIFO_Cfg_Type adc_fifo_cfg = { 0 }; - - CPU_Interrupt_Disable(GPADC_DMA_IRQn); - ADC_IntMask(ADC_INT_ALL, MASK); - - adc_cfg.clkDiv = adc_device->clk_div; - - adc_cfg.vref = adc_device->vref; - adc_cfg.resWidth = adc_device->data_width; - adc_cfg.inputMode = adc_device->differential_mode; - - adc_cfg.v18Sel = ADC_V18_SELECT; - adc_cfg.v11Sel = ADC_V11_SELECT; - adc_cfg.gain1 = ADC_PGA_GAIN1; - adc_cfg.gain2 = ADC_PGA_GAIN2; - adc_cfg.chopMode = ADC_CHOP_MODE; - adc_cfg.biasSel = ADC_BIAS_SELECT; - adc_cfg.vcm = ADC_PGA_VCM; - adc_cfg.offsetCalibEn = ADC_OFFSET_CALIB_EN; - adc_cfg.offsetCalibVal = ADC_OFFSER_CALIB_VAL; - - adc_fifo_cfg.dmaEn = DISABLE; - adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold; - - if (oflag & DEVICE_OFLAG_STREAM_TX) { - } - - if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) { -#ifdef BSP_USING_ADC0 - Interrupt_Handler_Register(GPADC_DMA_IRQn, ADC_IRQ); -#endif - } - - if (oflag & DEVICE_OFLAG_DMA_TX) { - } - - if (oflag & DEVICE_OFLAG_DMA_RX) { - adc_fifo_cfg.dmaEn = ENABLE; - } - - ADC_Disable(); - ADC_Enable(); - - ADC_Reset(); - - ADC_Init(&adc_cfg); - - ADC_FIFO_Cfg(&adc_fifo_cfg); - - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int adc_close(struct device *dev) -{ - uint32_t tmpVal; - - ADC_IntMask(ADC_INT_ALL, MASK); - - /* disable convert start */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - - /*disable adc */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - - /*disable vbat */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - - ADC_Reset(); - return 0; -} - -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int adc_control(struct device *dev, int cmd, void *args) -{ - adc_device_t *adc_device = (adc_device_t *)dev; - adc_channel_cfg_t *adc_channel_cfg = (adc_channel_cfg_t *)args; - uint8_t rlt = 0; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: { - uint32_t offset = __builtin_ctz((uint32_t)args); - while ((2 <= offset) && (offset < 6)) { - if ((uint32_t)args & (1 << offset)) { - ADC_IntMask(offset, UNMASK); - } - offset++; - } - CPU_Interrupt_Enable(GPADC_DMA_IRQn); - - break; - } - - case DEVICE_CTRL_CLR_INT: { - uint32_t offset = __builtin_ctz((uint32_t)args); - while ((2 <= offset) && (offset < 6)) { - if ((uint32_t)args & (1 << offset)) { - ADC_IntMask(offset, UNMASK); - } - offset++; - } - CPU_Interrupt_Disable(GPADC_DMA_IRQn); - - break; - } - - case DEVICE_CTRL_GET_INT: - break; - - case DEVICE_CTRL_CONFIG: - break; - - case DEVICE_CTRL_ADC_CHANNEL_CONFIG: - if (adc_channel_cfg->num == 1) { - ADC_Channel_Config(*adc_channel_cfg->pos_channel, *adc_channel_cfg->neg_channel, adc_device->continuous_conv_mode); - rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, 1); - } else { - ADC_Scan_Channel_Config(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, adc_channel_cfg->num, adc_device->continuous_conv_mode); - rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, adc_channel_cfg->num); - } - - break; - - case DEVICE_CTRL_ADC_CHANNEL_START: { - uint32_t regCmd; - - /* disable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - - BL702_Delay_US(100); - - /* enable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - } break; - - case DEVICE_CTRL_ADC_CHANNEL_STOP: { - uint32_t tmpVal; - - /* disable convert start */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - break; - } - - case DEVICE_CTRL_ADC_VBAT_ON: { - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - break; - } - - case DEVICE_CTRL_ADC_VBAT_OFF: { - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - break; - } - - case DEVICE_CTRL_ADC_TSEN_ON: - ADC_Tsen_Init(ADC_TSEN_MOD_INTERNAL_DIODE); - break; - - case DEVICE_CTRL_ADC_TSEN_OFF: - - break; - case DEVICE_CTRL_ATTACH_RX_DMA: - adc_device->rx_dma = (struct device *)args; - break; - case DEVICE_CTRL_ADC_DATA_PARSE: { - adc_data_parse_t *parse = (adc_data_parse_t *)args; - ADC_Parse_Result(parse->input, parse->num, (ADC_Result_Type *)parse->output); - } - break; - default: - break; - } - - return rlt; -} -// int adc_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -// { - -// return 0; -// } -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - uint32_t adc_fifo_val[32]; - int ret = -1; - adc_device_t *adc_device = (adc_device_t *)dev; - - if (dev->oflag & DEVICE_OFLAG_STREAM_RX) { - if (size > 32) - return -1; - while (ADC_Get_FIFO_Count() < size) { - } - - for (uint32_t i = 0; i < size; i++) { - adc_fifo_val[i] = ADC_Read_FIFO(); - } - adc_channel_val_t *adc_parse_val = (adc_channel_val_t *)buffer; - ADC_Parse_Result(adc_fifo_val, size, (ADC_Result_Type *)adc_parse_val); - return size; - } else if (dev->oflag & DEVICE_OFLAG_DMA_RX) { - struct device *dma_ch = (struct device *)adc_device->rx_dma; - if (!dma_ch) - return -1; - - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_ADC_RDR, (uint32_t)buffer, size); - dma_channel_start(dma_ch); - - return ret; - } - return ret; -} - -int adc_trim_tsen(uint16_t *tsen_offset) -{ - return ADC_Trim_TSEN(tsen_offset); -} - -float adc_get_tsen(uint16_t tsen_offset) -{ - return TSEN_Get_Temp(tsen_offset); -} - -/** - * @brief - * - * @param index - * @param name - * @return int - */ -int adc_register(enum adc_index_type index, const char *name) -{ - struct device *dev; - - if (ADC_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(adcx_device[index].parent); - - dev->open = adc_open; - dev->close = adc_close; - dev->control = adc_control; - dev->write = NULL; - dev->read = adc_read; - - dev->type = DEVICE_CLASS_ADC; - dev->handle = NULL; - - return device_register(dev, name); -} - -/** - * @brief - * - * @param handle - */ -void adc_isr(adc_device_t *handle) -{ - if (!handle->parent.callback) - return; - - if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET && ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK) { - //handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_POS_SATURATION); - ADC_IntClr(ADC_INT_POS_SATURATION); - } - - if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET && ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK) { - //handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_NEG_SATURATION); - ADC_IntClr(ADC_INT_NEG_SATURATION); - } - - if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) { - ADC_IntClr(ADC_INT_FIFO_UNDERRUN); - handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_UNDERRUN); - } - - if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) { - ADC_IntClr(ADC_INT_FIFO_OVERRUN); - handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_OVERRUN); - } - - if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET && ADC_IntGetMask(ADC_INT_FIFO_READY) == UNMASK) { - ADC_IntClr(ADC_INT_FIFO_READY); - uint32_t adc_count = ADC_Get_FIFO_Count(); - uint32_t adc_fifo_val[32]; - adc_channel_val_t adc_parse_val[32]; - for (uint32_t i = 0; i < adc_count; i++) { - adc_fifo_val[i] = ADC_Read_FIFO(); - } - ADC_Parse_Result(adc_fifo_val, adc_count, (ADC_Result_Type *)adc_parse_val); - handle->parent.callback(&handle->parent, (void *)adc_parse_val, adc_count, ADC_EVENT_FIFO); - } -} -#ifdef BSP_USING_ADC0 -void ADC_IRQ(void) -{ - adc_isr(&adcx_device[ADC0_INDEX]); -} -#endif \ No newline at end of file diff --git a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c index de878e5e..20778c90 100644 --- a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c +++ b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c @@ -69,7 +69,7 @@ void gpio_set_mode(uint32_t pin, uint32_t mode) { gpio_cfg.pullType = GPIO_PULL_NONE; break; - case GPIO_INPUT_PP_MODE: + case GPIO_INPUT_PU_MODE: gpio_cfg.gpioMode = GPIO_MODE_INPUT; gpio_cfg.pullType = GPIO_PULL_UP; break; diff --git a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h index 59eee9d8..294d1d80 100644 --- a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h +++ b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h @@ -72,39 +72,39 @@ #define __BL702_GPIO_H__ typedef enum { - GLB_GPIO_PIN_0 = 0, - GLB_GPIO_PIN_1, - GLB_GPIO_PIN_2, - GLB_GPIO_PIN_3, - GLB_GPIO_PIN_4, - GLB_GPIO_PIN_5, - GLB_GPIO_PIN_6, - GLB_GPIO_PIN_7, - GLB_GPIO_PIN_8, - GLB_GPIO_PIN_9, - GLB_GPIO_PIN_10, - GLB_GPIO_PIN_11, - GLB_GPIO_PIN_12, - GLB_GPIO_PIN_13, - GLB_GPIO_PIN_14, - GLB_GPIO_PIN_15, - GLB_GPIO_PIN_16, - GLB_GPIO_PIN_17, - GLB_GPIO_PIN_18, - GLB_GPIO_PIN_19, - GLB_GPIO_PIN_20, - GLB_GPIO_PIN_21, - GLB_GPIO_PIN_22, - GLB_GPIO_PIN_23, - GLB_GPIO_PIN_24, - GLB_GPIO_PIN_25, - GLB_GPIO_PIN_26, - GLB_GPIO_PIN_27, - GLB_GPIO_PIN_28, - GLB_GPIO_PIN_29, - GLB_GPIO_PIN_30, - GLB_GPIO_PIN_31, - GLB_GPIO_PIN_MAX, + GLB_GPIO_PIN_0 = 0, + GLB_GPIO_PIN_1, + GLB_GPIO_PIN_2, + GLB_GPIO_PIN_3, + GLB_GPIO_PIN_4, + GLB_GPIO_PIN_5, + GLB_GPIO_PIN_6, + GLB_GPIO_PIN_7, + GLB_GPIO_PIN_8, + GLB_GPIO_PIN_9, + GLB_GPIO_PIN_10, + GLB_GPIO_PIN_11, + GLB_GPIO_PIN_12, + GLB_GPIO_PIN_13, + GLB_GPIO_PIN_14, + GLB_GPIO_PIN_15, + GLB_GPIO_PIN_16, + GLB_GPIO_PIN_17, + GLB_GPIO_PIN_18, + GLB_GPIO_PIN_19, + GLB_GPIO_PIN_20, + GLB_GPIO_PIN_21, + GLB_GPIO_PIN_22, + GLB_GPIO_PIN_23, + GLB_GPIO_PIN_24, + GLB_GPIO_PIN_25, + GLB_GPIO_PIN_26, + GLB_GPIO_PIN_27, + GLB_GPIO_PIN_28, + GLB_GPIO_PIN_29, + GLB_GPIO_PIN_30, + GLB_GPIO_PIN_31, + GLB_GPIO_PIN_MAX, } GLB_GPIO_Type; #define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ @@ -116,67 +116,66 @@ typedef enum { #define GPIO_PULL_NONE ((uint32_t)0x00000002U) /*!< GPIO no pull up or down */ typedef enum { - GPIO_FUN_CLK_OUT = 0, - GPIO_FUN_BT_COEXIST = 1, - GPIO_FUN_FLASH_PSRAM = 2, - GPIO_FUN_QSPI = 2, - GPIO_FUN_I2S = 3, - GPIO_FUN_SPI = 4, - GPIO_FUN_I2C = 6, - GPIO_FUN_UART = 7, - GPIO_FUN_PWM = 8, - GPIO_FUN_CAM = 9, - GPIO_FUN_ANALOG = 10, - GPIO_FUN_GPIO = 11, - GPIO_FUN_RF_TEST = 12, - GPIO_FUN_SCAN = 13, - GPIO_FUN_E21_JTAG = 14, - GPIO_FUN_DEBUG = 15, - GPIO_FUN_EXTERNAL_PA = 16, - GPIO_FUN_USB_TRANCEIVER = 17, - GPIO_FUN_USB_CONTROLLER = 18, - GPIO_FUN_ETHER_MAC = 19, - GPIO_FUN_EMAC = 19, - GPIO_FUN_QDEC = 20, - GPIO_FUN_KEY_SCAN_IN = 21, - GPIO_FUN_KEY_SCAN_ROW = 21, - GPIO_FUN_KEY_SCAN_DRIVE = 22, - GPIO_FUN_KEY_SCAN_COL = 22, - GPIO_FUN_CAM_MISC = 23, - GPIO_FUN_USB = 0xD0, - GPIO_FUN_DAC = 0xD1, - GPIO_FUN_ADC = 0xD2, - GPIO_FUN_QDEC_LED = 0xD3, - GPIO_FUN_GPIO_OUTPUT_UP = 0xE0, - GPIO_FUN_GPIO_OUTPUT_DOWN = 0xE1, - GPIO_FUN_GPIO_OUTPUT_NONE = 0xE2, - GPIO_FUN_GPIO_INPUT_UP = 0xE3, - GPIO_FUN_GPIO_INPUT_DOWN = 0xE4, - GPIO_FUN_GPIO_INPUT_NONE = 0xE5, - GPIO_FUN_GPIO_EXTI_RISING_EDGE = 0xE6, - GPIO_FUN_GPIO_EXTI_FALLING_EDGE = 0xE7, - GPIO_FUN_GPIO_EXTI_HIGH_LEVEL = 0xE8, - GPIO_FUN_GPIO_EXTI_LOW_LEVEL = 0xE9, - GPIO_FUN_UART0_RTS = 0xF0, - GPIO_FUN_UART0_CTS = 0xF1, - GPIO_FUN_UART0_TX = 0xF2, - GPIO_FUN_UART0_RX = 0xF3, - GPIO_FUN_UART1_RTS = 0xF4, - GPIO_FUN_UART1_CTS = 0xF5, - GPIO_FUN_UART1_TX = 0xF6, - GPIO_FUN_UART1_RX = 0xF7, - GPIO_FUN_WAKEUP = 0xFE, - GPIO_FUN_UNUSED = 0xFF + GPIO_FUN_CLK_OUT = 0, + GPIO_FUN_BT_COEXIST = 1, + GPIO_FUN_FLASH_PSRAM = 2, + GPIO_FUN_QSPI = 2, + GPIO_FUN_I2S = 3, + GPIO_FUN_SPI = 4, + GPIO_FUN_I2C = 6, + GPIO_FUN_UART = 7, + GPIO_FUN_PWM = 8, + GPIO_FUN_CAM = 9, + GPIO_FUN_ANALOG = 10, + GPIO_FUN_GPIO = 11, + GPIO_FUN_RF_TEST = 12, + GPIO_FUN_SCAN = 13, + GPIO_FUN_E21_JTAG = 14, + GPIO_FUN_DEBUG = 15, + GPIO_FUN_EXTERNAL_PA = 16, + GPIO_FUN_USB_TRANCEIVER = 17, + GPIO_FUN_USB_CONTROLLER = 18, + GPIO_FUN_ETHER_MAC = 19, + GPIO_FUN_EMAC = 19, + GPIO_FUN_QDEC = 20, + GPIO_FUN_KEY_SCAN_IN = 21, + GPIO_FUN_KEY_SCAN_ROW = 21, + GPIO_FUN_KEY_SCAN_DRIVE = 22, + GPIO_FUN_KEY_SCAN_COL = 22, + GPIO_FUN_CAM_MISC = 23, + GPIO_FUN_USB = 0xD0, + GPIO_FUN_DAC = 0xD1, + GPIO_FUN_ADC = 0xD2, + GPIO_FUN_QDEC_LED = 0xD3, + GPIO_FUN_GPIO_OUTPUT_UP = 0xE0, + GPIO_FUN_GPIO_OUTPUT_DOWN = 0xE1, + GPIO_FUN_GPIO_OUTPUT_NONE = 0xE2, + GPIO_FUN_GPIO_INPUT_UP = 0xE3, + GPIO_FUN_GPIO_INPUT_DOWN = 0xE4, + GPIO_FUN_GPIO_INPUT_NONE = 0xE5, + GPIO_FUN_GPIO_EXTI_RISING_EDGE = 0xE6, + GPIO_FUN_GPIO_EXTI_FALLING_EDGE = 0xE7, + GPIO_FUN_GPIO_EXTI_HIGH_LEVEL = 0xE8, + GPIO_FUN_GPIO_EXTI_LOW_LEVEL = 0xE9, + GPIO_FUN_UART0_RTS = 0xF0, + GPIO_FUN_UART0_CTS = 0xF1, + GPIO_FUN_UART0_TX = 0xF2, + GPIO_FUN_UART0_RX = 0xF3, + GPIO_FUN_UART1_RTS = 0xF4, + GPIO_FUN_UART1_CTS = 0xF5, + GPIO_FUN_UART1_TX = 0xF6, + GPIO_FUN_UART1_RX = 0xF7, + GPIO_FUN_WAKEUP = 0xFE, + GPIO_FUN_UNUSED = 0xFF } GLB_GPIO_FUNC_Type; -typedef struct -{ - uint8_t gpioPin; - uint8_t gpioFun; - uint8_t gpioMode; - uint8_t pullType; - uint8_t drive; - uint8_t smtCtrl; +typedef struct { + uint8_t gpioPin; + uint8_t gpioFun; + uint8_t gpioMode; + uint8_t pullType; + uint8_t drive; + uint8_t smtCtrl; // Schmitt trigger } GLB_GPIO_Cfg_Type; /* GPIO0 function definition */ @@ -948,5 +947,4 @@ typedef struct #define GPIO31_FUN_COL_O_11 22 #define GPIO31_FUN_CAM_REF_CLK 23 - #endif /*__BL702_GPIO_H__ */ diff --git a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c index 16dfd7c6..e4bd8213 100644 --- a/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c +++ b/source/Core/BSP/Magic/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c @@ -185,7 +185,7 @@ void ADC_Init(ADC_CFG_Type *cfg) { CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth)); /* config 1 */ - regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); + regCfg1 = 0; // BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V18_SEL, cfg->v18Sel); regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V11_SEL, cfg->v11Sel); regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_DITHER_EN); @@ -200,11 +200,13 @@ void ADC_Init(ADC_CFG_Type *cfg) { /* config 2 */ regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x02); + regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x00); regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA1_GAIN, cfg->gain1); regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA2_GAIN, cfg->gain2); regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_BIAS_SEL, cfg->biasSel); regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, cfg->chopMode); + regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_VBAT_EN); // vbat enabled (off) + regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_TSVBE_LOW); // tsen didoe current /* pga_vcmi_en is for mic */ regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_VCMI_EN); diff --git a/source/Core/BSP/Magic/board.c b/source/Core/BSP/Magic/board.c index 9bd151fc..a1ef0288 100644 --- a/source/Core/BSP/Magic/board.c +++ b/source/Core/BSP/Magic/board.c @@ -133,7 +133,7 @@ static const struct pin_mux_cfg af_pin_table[] = { static void board_pin_mux_init(void) { GLB_GPIO_Cfg_Type gpio_cfg; uint32_t tmpVal; - gpio_cfg.drive = 0; + gpio_cfg.drive = 3; gpio_cfg.smtCtrl = 1; uint8_t hbn_gpio_mask = 0x1f; uint8_t hbn_aon_ie = 0;