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Refactor BSP
Magic BSP -> PinecilV2 Pine64 BSP -> Pinecil Update Makefile
This commit is contained in:
Ben V. Brown
266
source/Core/BSP/Pinecilv2/peripheral_config.h
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266
source/Core/BSP/Pinecilv2/peripheral_config.h
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/**
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* @file peripheral_config.h
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* @brief
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*
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* Copyright (c) 2021 Bouffalolab team
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*/
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#ifndef _PERIPHERAL_CONFIG_H_
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#define _PERIPHERAL_CONFIG_H_
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/* PERIPHERAL USING LIST */
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#define BSP_USING_ADC0
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// #define BSP_USING_DAC0
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#define BSP_USING_UART0
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// #define BSP_USING_UART1
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// #define BSP_USING_SPI0
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#define BSP_USING_I2C0
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// #define BSP_USING_I2S0
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// #define BSP_USING_PWM_CH0
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#define BSP_USING_PWM_CH1
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// #define BSP_USING_PWM_CH2
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// #define BSP_USING_PWM_CH3
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// #define BSP_USING_PWM_CH4
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#define BSP_USING_TIMER0
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#define BSP_USING_TIMER1
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#define BSP_USING_WDT
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// #define BSP_USING_KEYSCAN
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// #define BSP_USING_QDEC0
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// #define BSP_USING_QDEC1
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// #define BSP_USING_QDEC2
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// #define BSP_USING_USB
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/* ----------------------*/
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/* PERIPHERAL With DMA LIST */
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#define BSP_USING_DMA0_CH0
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#define BSP_USING_DMA0_CH1
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#define BSP_USING_DMA0_CH2
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#define BSP_USING_DMA0_CH3
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#define BSP_USING_DMA0_CH4
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#define BSP_USING_DMA0_CH5
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#define BSP_USING_DMA0_CH6
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#define BSP_USING_DMA0_CH7
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/* PERIPHERAL CONFIG */
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#if defined(BSP_USING_ADC0)
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#ifndef ADC0_CONFIG
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#define ADC0_CONFIG \
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{ \
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.clk_div = ADC_CLOCK_DIV_32, .vref = ADC_VREF_3V2, .continuous_conv_mode = DISABLE, .differential_mode = DISABLE, .data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, \
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.fifo_threshold = ADC_FIFO_THRESHOLD_8BYTE, .gain = ADC_GAIN_1 \
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}
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#endif
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#endif
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#if defined(BSP_USING_DAC0)
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#ifndef DAC_CONFIG
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#define DAC_CONFIG \
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{ .channels = DAC_CHANNEL_0, .sample_freq = DAC_SAMPLE_FREQ_500KHZ, .vref = DAC_VREF_INTERNAL, }
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#endif
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#endif
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#if defined(BSP_USING_UART0)
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#ifndef UART0_CONFIG
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#define UART0_CONFIG \
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{ .id = 0, .baudrate = 2000000, .databits = UART_DATA_LEN_8, .stopbits = UART_STOP_ONE, .parity = UART_PAR_NONE, .fifo_threshold = 0, }
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#endif
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#endif
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#if defined(BSP_USING_PWM_CH0)
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#ifndef PWM_CH0_CONFIG
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#define PWM_CH0_CONFIG \
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{ .ch = 0, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
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#endif
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#endif
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#if defined(BSP_USING_PWM_CH1)
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#ifndef PWM_CH1_CONFIG
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#define PWM_CH1_CONFIG \
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{ .ch = 1, .polarity_invert_mode = DISABLE, .period = 100, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
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#endif
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#endif
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#if defined(BSP_USING_PWM_CH2)
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#ifndef PWM_CH2_CONFIG
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#define PWM_CH2_CONFIG \
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{ .ch = 2, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
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#endif
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#endif
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#if defined(BSP_USING_PWM_CH3)
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#ifndef PWM_CH3_CONFIG
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#define PWM_CH3_CONFIG \
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{ .ch = 3, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
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#endif
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#endif
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#if defined(BSP_USING_PWM_CH4)
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#ifndef PWM_CH4_CONFIG
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#define PWM_CH4_CONFIG \
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{ .ch = 4, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH0)
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#ifndef DMA0_CH0_CONFIG
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#define DMA0_CH0_CONFIG \
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{ \
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.id = 0, .ch = 0, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_4BYTE, .dst_burst_size = DMA_BURST_4BYTE, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH1)
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#ifndef DMA0_CH1_CONFIG
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#define DMA0_CH1_CONFIG \
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{ \
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.id = 0, .ch = 1, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_4BYTE, .dst_burst_size = DMA_BURST_4BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH2)
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#ifndef DMA0_CH2_CONFIG
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#define DMA0_CH2_CONFIG \
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{ \
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.id = 0, .ch = 2, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_UART1_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH3)
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#ifndef DMA0_CH3_CONFIG
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#define DMA0_CH3_CONFIG \
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{ \
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.id = 0, .ch = 3, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_SPI0_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH4)
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#ifndef DMA0_CH4_CONFIG
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#define DMA0_CH4_CONFIG \
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{ \
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.id = 0, .ch = 4, .direction = DMA_PERIPH_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_SPI0_RX, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH5)
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#ifndef DMA0_CH5_CONFIG
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#define DMA0_CH5_CONFIG \
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{ \
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.id = 0, .ch = 5, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH6)
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#ifndef DMA0_CH6_CONFIG
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#define DMA0_CH6_CONFIG \
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{ \
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.id = 0, .ch = 6, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_DMA0_CH7)
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#ifndef DMA0_CH7_CONFIG
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#define DMA0_CH7_CONFIG \
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{ \
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.id = 0, .ch = 7, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_1BYTE, .dst_burst_size = DMA_BURST_1BYTE, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
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}
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#endif
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#endif
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#if defined(BSP_USING_I2C0)
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#ifndef I2C0_CONFIG
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#define I2C0_CONFIG \
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{ .id = 0, .mode = I2C_HW_MODE, .phase = 15, }
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#endif
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#endif
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#if defined(BSP_USING_TIMER0)
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#ifndef TIMER0_CONFIG
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#define TIMER0_CONFIG \
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{ .id = 0, .cnt_mode = TIMER_CNT_PRELOAD, .trigger = TIMER_PRELOAD_TRIGGER_COMP2, .reload = 0, .timeout1 = 1000000, .timeout2 = 2000000, .timeout3 = 3000000, }
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#endif
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#endif
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#if defined(BSP_USING_TIMER1)
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#ifndef TIMER1_CONFIG
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#define TIMER1_CONFIG \
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{ .id = 1, .cnt_mode = TIMER_CNT_PRELOAD, .trigger = TIMER_PRELOAD_TRIGGER_COMP0, .reload = 0, .timeout1 = 1000000, .timeout2 = 2000000, .timeout3 = 3000000, }
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#endif
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#endif
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#if defined(BSP_USING_WDT)
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#ifndef WDT_CONFIG
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#define WDT_CONFIG \
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{ .id = 0, .wdt_timeout = 6000, }
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#endif
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#endif
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#if defined(BSP_USING_KEYSCAN)
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#ifndef KEYSCAN_CONFIG
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#define KEYSCAN_CONFIG \
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{ .col_num = COL_NUM_4, .row_num = ROW_NUM_4, .deglitch_count = 0, }
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#endif
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#endif
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#if defined(BSP_USING_QDEC0)
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#ifndef QDEC0_CONFIG
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#define QDEC0_CONFIG \
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{ \
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.id = 0, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
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.led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0, \
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}
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#endif
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#endif
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#if defined(BSP_USING_QDEC1)
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#ifndef QDEC1_CONFIG
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#define QDEC1_CONFIG \
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{ \
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.id = 1, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
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.led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0, \
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}
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#endif
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#endif
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#if defined(BSP_USING_QDEC2)
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#ifndef QDEC2_CONFIG
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#define QDEC2_CONFIG \
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{ \
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.id = 2, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
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.led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0, \
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}
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#endif
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#endif
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#endif
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