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https://github.com/Ralim/IronOS.git
synced 2025-02-26 07:53:55 +00:00
Fix watchdog timeouts && get unit to boot
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@@ -94,6 +94,9 @@ uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) {
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sum += samples[i];
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sum += samples[i];
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sum /= BATTFILTERDEPTH;
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sum /= BATTFILTERDEPTH;
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if (divisor == 0) {
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divisor = 1;
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}
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return sum * 4 / divisor;
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return sum * 4 / divisor;
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}
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}
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@@ -13,7 +13,7 @@
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#define SDA_LOW() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET)
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#define SDA_LOW() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET)
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#define SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port,SDA2_Pin)==GPIO_PIN_SET?1:0)
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#define SDA_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port,SDA2_Pin)==GPIO_PIN_SET?1:0)
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#define SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port,SCL2_Pin)==GPIO_PIN_SET?1:0)
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#define SCL_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port,SCL2_Pin)==GPIO_PIN_SET?1:0)
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#define I2C_DELAY() HAL_Delay(1);
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#define I2C_DELAY() {for(int xx=0;xx<100;xx++){asm("nop");}}
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void I2CBB::init() {
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void I2CBB::init() {
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//Set GPIO's to output open drain
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//Set GPIO's to output open drain
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GPIO_InitTypeDef GPIO_InitStruct;
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GPIO_InitTypeDef GPIO_InitStruct;
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@@ -70,6 +70,7 @@ bool I2CBB::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData,
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return false;
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return false;
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}
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}
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while (Size) {
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while (Size) {
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resetWatchdog();
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bool ack = send(pData[0]);
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bool ack = send(pData[0]);
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if (!ack) {
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if (!ack) {
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stop();
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stop();
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@@ -182,7 +183,7 @@ bool I2CBB::send(uint8_t value) {
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value <<= 1;
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value <<= 1;
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}
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}
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bool ack = read_bit()==0;
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bool ack = read_bit() == 0;
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return ack;
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return ack;
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}
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}
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@@ -152,14 +152,21 @@ void fusb_setup() {
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/* Flush the RX buffer */
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/* Flush the RX buffer */
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fusb_write_byte( FUSB_CONTROL1, FUSB_CONTROL1_RX_FLUSH);
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fusb_write_byte( FUSB_CONTROL1, FUSB_CONTROL1_RX_FLUSH);
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resetWatchdog();
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/* Measure CC1 */
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/* Measure CC1 */
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fusb_write_byte( FUSB_SWITCHES0, 0x07);
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fusb_write_byte( FUSB_SWITCHES0, 0x07);
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osDelay(1);
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resetWatchdog();
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delay_ms(1);
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resetWatchdog();
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uint8_t cc1 = fusb_read_byte( FUSB_STATUS0) & FUSB_STATUS0_BC_LVL;
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uint8_t cc1 = fusb_read_byte( FUSB_STATUS0) & FUSB_STATUS0_BC_LVL;
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resetWatchdog();
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/* Measure CC2 */
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/* Measure CC2 */
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resetWatchdog();
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fusb_write_byte( FUSB_SWITCHES0, 0x0B);
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fusb_write_byte( FUSB_SWITCHES0, 0x0B);
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osDelay(1);
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resetWatchdog();
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delay_ms(1);
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resetWatchdog();
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uint8_t cc2 = fusb_read_byte( FUSB_STATUS0) & FUSB_STATUS0_BC_LVL;
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uint8_t cc2 = fusb_read_byte( FUSB_STATUS0) & FUSB_STATUS0_BC_LVL;
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/* Select the correct CC line for BMC signaling; also enable AUTO_CRC */
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/* Select the correct CC line for BMC signaling; also enable AUTO_CRC */
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@@ -170,6 +177,7 @@ void fusb_setup() {
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fusb_write_byte( FUSB_SWITCHES1, 0x26);
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fusb_write_byte( FUSB_SWITCHES1, 0x26);
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fusb_write_byte( FUSB_SWITCHES0, 0x0B);
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fusb_write_byte( FUSB_SWITCHES0, 0x0B);
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}
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}
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resetWatchdog();
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/* Reset the PD logic */
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/* Reset the PD logic */
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fusb_write_byte( FUSB_RESET, FUSB_RESET_PD_RESET);
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fusb_write_byte( FUSB_RESET, FUSB_RESET_PD_RESET);
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@@ -24,10 +24,10 @@
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#include <pdb_msg.h>
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#include <pdb_msg.h>
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/* I2C addresses of the FUSB302B chips */
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/* I2C addresses of the FUSB302B chips */
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#define FUSB302B_ADDR 0x22
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#define FUSB302B_ADDR (0x22<<1)
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#define FUSB302B01_ADDR 0x23
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#define FUSB302B01_ADDR (0x23<<1)
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#define FUSB302B10_ADDR 0x24
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#define FUSB302B10_ADDR (0x24<<1)
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#define FUSB302B11_ADDR 0x25
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#define FUSB302B11_ADDR (0x25<<1)
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/* Device ID register */
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/* Device ID register */
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#define FUSB_DEVICE_ID 0x01
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#define FUSB_DEVICE_ID 0x01
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